| stats.txt (9924:31ef410b6843) | stats.txt (9978:81d7551dd3be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.149802 # Number of seconds simulated 4sim_ticks 5149801602000 # Number of ticks simulated 5final_tick 5149801602000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.133932 # Number of seconds simulated 4sim_ticks 5133932129000 # Number of ticks simulated 5final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 149544 # Simulator instruction rate (inst/s) 8host_op_rate 295611 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1888705545 # Simulator tick rate (ticks/s) 10host_mem_usage 733444 # Number of bytes of host memory used 11host_seconds 2726.63 # Real time elapsed on the host 12sim_insts 407752265 # Number of instructions simulated 13sim_ops 806021401 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2464448 # Number of bytes read from this memory | 7host_inst_rate 157497 # Simulator instruction rate (inst/s) 8host_op_rate 311329 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1982921852 # Simulator tick rate (ticks/s) 10host_mem_usage 759792 # Number of bytes of host memory used 11host_seconds 2589.07 # Real time elapsed on the host 12sim_insts 407772261 # Number of instructions simulated 13sim_ops 806052921 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 1029696 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10712000 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14210368 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1029696 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1029696 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9492864 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9492864 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38507 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.inst 16089 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 167375 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 222037 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 148326 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 148326 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 478552 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 758 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.inst 199949 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2080080 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2759401 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 199949 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 199949 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1843346 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1843346 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1843346 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 478552 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 758 # Total bandwidth to/from this memory (bytes/s) | 35system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) |
| 45system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.inst 199949 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2080080 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4602747 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 222037 # Total number of read requests accepted by DRAM controller 50system.physmem.writeReqs 148326 # Total number of write requests accepted by DRAM controller 51system.physmem.readBursts 222037 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 52system.physmem.writeBursts 148326 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 53system.physmem.bytesRead 14210368 # Total number of bytes read from memory 54system.physmem.bytesWritten 9492864 # Total number of bytes written to memory 55system.physmem.bytesConsumedRd 14210368 # bytesRead derated as per pkt->getSize() 56system.physmem.bytesConsumedWr 9492864 # bytesWritten derated as per pkt->getSize() 57system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by write Q 58system.physmem.neitherReadNorWrite 1678 # Reqs where no action is needed 59system.physmem.perBankRdReqs::0 14222 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::1 14028 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::2 14693 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::3 13767 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::4 13958 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::5 13755 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::6 13651 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::7 13963 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::8 13415 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::9 13462 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::10 13512 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::11 13712 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::12 14980 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::13 14150 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::14 13362 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::15 13288 # Track reads on a per bank basis 75system.physmem.perBankWrReqs::0 9612 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::1 9534 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::2 9830 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::3 9200 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::4 9484 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::5 9208 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::6 9093 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::7 9396 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::8 8748 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::9 8829 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::10 9077 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::11 9138 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::12 10300 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::13 9366 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::14 8795 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::15 8716 # Track writes on a per bank basis 91system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 92system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry 93system.physmem.totGap 5149801548000 # Total gap between requests 94system.physmem.readPktSize::0 0 # Categorize read packet sizes 95system.physmem.readPktSize::1 0 # Categorize read packet sizes 96system.physmem.readPktSize::2 0 # Categorize read packet sizes 97system.physmem.readPktSize::3 0 # Categorize read packet sizes 98system.physmem.readPktSize::4 0 # Categorize read packet sizes 99system.physmem.readPktSize::5 0 # Categorize read packet sizes 100system.physmem.readPktSize::6 222037 # Categorize read packet sizes 101system.physmem.writePktSize::0 0 # Categorize write packet sizes 102system.physmem.writePktSize::1 0 # Categorize write packet sizes 103system.physmem.writePktSize::2 0 # Categorize write packet sizes 104system.physmem.writePktSize::3 0 # Categorize write packet sizes 105system.physmem.writePktSize::4 0 # Categorize write packet sizes 106system.physmem.writePktSize::5 0 # Categorize write packet sizes 107system.physmem.writePktSize::6 148326 # Categorize write packet sizes 108system.physmem.rdQLenPdf::0 173642 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 21423 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 7433 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 2962 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 2531 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 2108 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 1301 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 1174 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 1084 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 1011 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 947 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 916 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 856 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 955 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 745 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 522 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 251 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 149 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see | 46system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 222430 # Number of read requests accepted 50system.physmem.writeReqs 148587 # Number of write requests accepted 51system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue 52system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue 53system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM 54system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue 55system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM 56system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side 57system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side 58system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue 59system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 60system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write 61system.physmem.perBankRdBursts::0 14853 # Per bank write bursts 62system.physmem.perBankRdBursts::1 13635 # Per bank write bursts 63system.physmem.perBankRdBursts::2 14415 # Per bank write bursts 64system.physmem.perBankRdBursts::3 13770 # Per bank write bursts 65system.physmem.perBankRdBursts::4 14136 # Per bank write bursts 66system.physmem.perBankRdBursts::5 13341 # Per bank write bursts 67system.physmem.perBankRdBursts::6 13755 # Per bank write bursts 68system.physmem.perBankRdBursts::7 13953 # Per bank write bursts 69system.physmem.perBankRdBursts::8 13590 # Per bank write bursts 70system.physmem.perBankRdBursts::9 13369 # Per bank write bursts 71system.physmem.perBankRdBursts::10 13469 # Per bank write bursts 72system.physmem.perBankRdBursts::11 13962 # Per bank write bursts 73system.physmem.perBankRdBursts::12 14252 # Per bank write bursts 74system.physmem.perBankRdBursts::13 14454 # Per bank write bursts 75system.physmem.perBankRdBursts::14 13844 # Per bank write bursts 76system.physmem.perBankRdBursts::15 13571 # Per bank write bursts 77system.physmem.perBankWrBursts::0 10225 # Per bank write bursts 78system.physmem.perBankWrBursts::1 9089 # Per bank write bursts 79system.physmem.perBankWrBursts::2 9605 # Per bank write bursts 80system.physmem.perBankWrBursts::3 9165 # Per bank write bursts 81system.physmem.perBankWrBursts::4 9475 # Per bank write bursts 82system.physmem.perBankWrBursts::5 8866 # Per bank write bursts 83system.physmem.perBankWrBursts::6 9032 # Per bank write bursts 84system.physmem.perBankWrBursts::7 9363 # Per bank write bursts 85system.physmem.perBankWrBursts::8 8843 # Per bank write bursts 86system.physmem.perBankWrBursts::9 8764 # Per bank write bursts 87system.physmem.perBankWrBursts::10 9099 # Per bank write bursts 88system.physmem.perBankWrBursts::11 9352 # Per bank write bursts 89system.physmem.perBankWrBursts::12 9596 # Per bank write bursts 90system.physmem.perBankWrBursts::13 9639 # Per bank write bursts 91system.physmem.perBankWrBursts::14 9447 # Per bank write bursts 92system.physmem.perBankWrBursts::15 9010 # Per bank write bursts 93system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 94system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 95system.physmem.totGap 5133932076000 # Total gap between requests 96system.physmem.readPktSize::0 0 # Read request sizes (log2) 97system.physmem.readPktSize::1 0 # Read request sizes (log2) 98system.physmem.readPktSize::2 0 # Read request sizes (log2) 99system.physmem.readPktSize::3 0 # Read request sizes (log2) 100system.physmem.readPktSize::4 0 # Read request sizes (log2) 101system.physmem.readPktSize::5 0 # Read request sizes (log2) 102system.physmem.readPktSize::6 222430 # Read request sizes (log2) 103system.physmem.writePktSize::0 0 # Write request sizes (log2) 104system.physmem.writePktSize::1 0 # Write request sizes (log2) 105system.physmem.writePktSize::2 0 # Write request sizes (log2) 106system.physmem.writePktSize::3 0 # Write request sizes (log2) 107system.physmem.writePktSize::4 0 # Write request sizes (log2) 108system.physmem.writePktSize::5 0 # Write request sizes (log2) 109system.physmem.writePktSize::6 148587 # Write request sizes (log2) 110system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see |
| 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 140system.physmem.wrQLenPdf::0 5426 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::1 5696 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::2 6386 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::3 6428 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::5 6435 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::6 6441 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::7 6443 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::8 6443 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::9 6449 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::10 6449 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::11 6449 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::12 6449 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::13 6449 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::14 6449 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::15 6449 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::16 6449 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::17 6449 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::18 6449 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::19 6449 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::20 6449 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::21 6449 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::22 6448 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::23 1023 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::24 753 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::25 63 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see 172system.physmem.bytesPerActivate::samples 62488 # Bytes accessed per row activation 173system.physmem.bytesPerActivate::mean 379.140187 # Bytes accessed per row activation 174system.physmem.bytesPerActivate::gmean 154.041653 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::stdev 1280.875932 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::64-67 27817 44.52% 44.52% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::128-131 9622 15.40% 59.91% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::192-195 5951 9.52% 69.44% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::256-259 3940 6.31% 75.74% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::320-323 2520 4.03% 79.78% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::384-387 1986 3.18% 82.95% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::448-451 1542 2.47% 85.42% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::512-515 1215 1.94% 87.37% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::576-579 1005 1.61% 88.97% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::640-643 910 1.46% 90.43% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::704-707 598 0.96% 91.39% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::768-771 543 0.87% 92.26% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::832-835 367 0.59% 92.84% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::896-899 364 0.58% 93.43% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::960-963 356 0.57% 94.00% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1024-1027 454 0.73% 94.72% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1088-1091 284 0.45% 95.18% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1152-1155 192 0.31% 95.48% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1216-1219 180 0.29% 95.77% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1280-1283 146 0.23% 96.01% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1344-1347 174 0.28% 96.28% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1408-1411 177 0.28% 96.57% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1472-1475 484 0.77% 97.34% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1536-1539 176 0.28% 97.62% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1600-1603 118 0.19% 97.81% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1664-1667 94 0.15% 97.96% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1728-1731 80 0.13% 98.09% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1792-1795 58 0.09% 98.18% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1856-1859 28 0.04% 98.23% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1920-1923 25 0.04% 98.27% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1984-1987 31 0.05% 98.32% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2048-2051 34 0.05% 98.37% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2112-2115 13 0.02% 98.39% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2176-2179 15 0.02% 98.42% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.43% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2304-2307 19 0.03% 98.46% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.49% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2432-2435 8 0.01% 98.50% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2496-2499 10 0.02% 98.52% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2560-2563 8 0.01% 98.53% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.54% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2688-2691 3 0.00% 98.54% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2752-2755 9 0.01% 98.56% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.57% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2880-2883 9 0.01% 98.58% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.59% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3072-3075 3 0.00% 98.60% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3136-3139 7 0.01% 98.61% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.61% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3264-3267 3 0.00% 98.62% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3328-3331 3 0.00% 98.62% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3392-3395 5 0.01% 98.63% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3456-3459 14 0.02% 98.65% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.67% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.67% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3712-3715 6 0.01% 98.68% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.70% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3904-3907 3 0.00% 98.71% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.72% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4032-4035 1 0.00% 98.72% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4096-4099 21 0.03% 98.75% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4160-4163 7 0.01% 98.76% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.76% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.77% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4416-4419 6 0.01% 98.78% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4480-4483 3 0.00% 98.79% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4544-4547 5 0.01% 98.79% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.80% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.80% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.80% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4928-4931 3 0.00% 98.81% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.81% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5120-5123 4 0.01% 98.82% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.82% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.83% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5376-5379 4 0.01% 98.84% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.84% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.84% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5952-5955 2 0.00% 98.85% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6016-6019 2 0.00% 98.85% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.85% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.86% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6336-6339 2 0.00% 98.86% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.87% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6464-6467 1 0.00% 98.87% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6848-6851 2 0.00% 98.88% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6912-6915 7 0.01% 98.89% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.89% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7104-7107 2 0.00% 98.90% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.91% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.91% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.91% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.91% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7616-7619 2 0.00% 98.92% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7680-7683 2 0.00% 98.92% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.92% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.93% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::8000-8003 2 0.00% 98.93% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.93% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.94% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8192-8195 339 0.54% 99.48% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.48% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.48% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.49% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.49% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.49% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.49% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9536-9539 8 0.01% 99.51% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.51% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9664-9667 3 0.00% 99.51% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.52% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.52% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::10048-10051 4 0.01% 99.52% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.53% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::10560-10563 2 0.00% 99.53% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.53% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.54% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.54% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.55% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.55% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.55% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.55% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.55% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::12352-12355 2 0.00% 99.56% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.56% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.56% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.56% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.57% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.57% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.57% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.58% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.58% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.58% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::14464-14467 3 0.00% 99.59% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.59% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.59% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::14912-14915 28 0.04% 99.64% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::14976-14979 15 0.02% 99.66% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::15040-15043 10 0.02% 99.68% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.69% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.70% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::15232-15235 4 0.01% 99.71% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.72% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::15360-15363 3 0.00% 99.72% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.73% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.74% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::15552-15555 3 0.00% 99.75% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::15616-15619 4 0.01% 99.75% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::15680-15683 6 0.01% 99.76% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.76% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.77% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::15872-15875 7 0.01% 99.79% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::15936-15939 6 0.01% 99.80% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.80% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::16064-16067 8 0.01% 99.81% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.82% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.84% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::16256-16259 12 0.02% 99.86% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::16320-16323 11 0.02% 99.88% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::16384-16387 62 0.10% 99.98% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.98% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::16512-16515 3 0.00% 99.98% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::17216-17219 2 0.00% 100.00% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::total 62488 # Bytes accessed per row activation 373system.physmem.totQLat 4021160000 # Total cycles spent in queuing delays 374system.physmem.totMemAccLat 8281507500 # Sum of mem lat for all requests 375system.physmem.totBusLat 1109590000 # Total cycles spent in databus access 376system.physmem.totBankLat 3150757500 # Total cycles spent in bank access 377system.physmem.avgQLat 18120.03 # Average queueing delay per request 378system.physmem.avgBankLat 14197.85 # Average bank access latency per request 379system.physmem.avgBusLat 5000.00 # Average bus latency per request 380system.physmem.avgMemAccLat 37317.87 # Average memory access latency 381system.physmem.avgRdBW 2.76 # Average achieved read bandwidth in MB/s 382system.physmem.avgWrBW 1.84 # Average achieved write bandwidth in MB/s 383system.physmem.avgConsumedRdBW 2.76 # Average consumed read bandwidth in MB/s 384system.physmem.avgConsumedWrBW 1.84 # Average consumed write bandwidth in MB/s 385system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 142system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see 174system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation 394system.physmem.totQLat 5163279754 # Total ticks spent queuing 395system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM 396system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers 397system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks 398system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst 399system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst 400system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 401system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst 402system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s 403system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s 404system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s 405system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s 406system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 386system.physmem.busUtil 0.04 # Data bus utilization in percentage | 407system.physmem.busUtil 0.04 # Data bus utilization in percentage |
| 387system.physmem.avgRdQLen 0.00 # Average read queue length over time 388system.physmem.avgWrQLen 9.63 # Average write queue length over time 389system.physmem.readRowHits 198603 # Number of row buffer hits during reads 390system.physmem.writeRowHits 109131 # Number of row buffer hits during writes 391system.physmem.readRowHitRate 89.49 # Row buffer hit rate for reads 392system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes 393system.physmem.avgGap 13904740.88 # Average gap between requests 394system.membus.throughput 5073674 # Throughput (bytes/s) 395system.membus.trans_dist::ReadReq 662109 # Transaction distribution 396system.membus.trans_dist::ReadResp 662107 # Transaction distribution 397system.membus.trans_dist::WriteReq 13770 # Transaction distribution 398system.membus.trans_dist::WriteResp 13770 # Transaction distribution 399system.membus.trans_dist::Writeback 148326 # Transaction distribution 400system.membus.trans_dist::UpgradeReq 2172 # Transaction distribution 401system.membus.trans_dist::UpgradeResp 1696 # Transaction distribution 402system.membus.trans_dist::ReadExReq 179020 # Transaction distribution 403system.membus.trans_dist::ReadExResp 179014 # Transaction distribution 404system.membus.trans_dist::MessageReq 1646 # Transaction distribution 405system.membus.trans_dist::MessageResp 1646 # Transaction distribution 406system.membus.trans_dist::BadAddressError 2 # Transaction distribution 407system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3292 # Packet count per connected master and slave (bytes) 408system.membus.pkt_count_system.apicbridge.master::total 3292 # Packet count per connected master and slave (bytes) 409system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) 410system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775088 # Packet count per connected master and slave (bytes) 411system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473242 # Packet count per connected master and slave (bytes) 412system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) 413system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719372 # Packet count per connected master and slave (bytes) 414system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132805 # Packet count per connected master and slave (bytes) 415system.membus.pkt_count_system.iocache.mem_side::total 132805 # Packet count per connected master and slave (bytes) 416system.membus.pkt_count::total 1855469 # Packet count per connected master and slave (bytes) 417system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6584 # Cumulative packet size per connected master and slave (bytes) 418system.membus.tot_pkt_size_system.apicbridge.master::total 6584 # Cumulative packet size per connected master and slave (bytes) 419system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) 420system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550173 # Cumulative packet size per connected master and slave (bytes) 421system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18252032 # Cumulative packet size per connected master and slave (bytes) 422system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20044007 # Cumulative packet size per connected master and slave (bytes) 423system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5451200 # Cumulative packet size per connected master and slave (bytes) 424system.membus.tot_pkt_size_system.iocache.mem_side::total 5451200 # Cumulative packet size per connected master and slave (bytes) 425system.membus.tot_pkt_size::total 25501791 # Cumulative packet size per connected master and slave (bytes) 426system.membus.data_through_bus 25501791 # Total data (bytes) 427system.membus.snoop_data_through_bus 626624 # Total snoop data (bytes) 428system.membus.reqLayer0.occupancy 250581000 # Layer occupancy (ticks) | 408system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 409system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 410system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing 411system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing 412system.physmem.readRowHits 193089 # Number of row buffer hits during reads 413system.physmem.writeRowHits 108689 # Number of row buffer hits during writes 414system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads 415system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes 416system.physmem.avgGap 13837457.79 # Average gap between requests 417system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined 418system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state 419system.membus.throughput 5101771 # Throughput (bytes/s) 420system.membus.trans_dist::ReadReq 662370 # Transaction distribution 421system.membus.trans_dist::ReadResp 662362 # Transaction distribution 422system.membus.trans_dist::WriteReq 13778 # Transaction distribution 423system.membus.trans_dist::WriteResp 13778 # Transaction distribution 424system.membus.trans_dist::Writeback 148587 # Transaction distribution 425system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution 426system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution 427system.membus.trans_dist::ReadExReq 179504 # Transaction distribution 428system.membus.trans_dist::ReadExResp 179502 # Transaction distribution 429system.membus.trans_dist::MessageReq 1643 # Transaction distribution 430system.membus.trans_dist::MessageResp 1643 # Transaction distribution 431system.membus.trans_dist::BadAddressError 8 # Transaction distribution 432system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) 433system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) 434system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) 435system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) 436system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes) 437system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) 438system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes) 439system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes) 440system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes) 441system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes) 442system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) 443system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) 444system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) 445system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) 446system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes) 447system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes) 448system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes) 449system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes) 450system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes) 451system.membus.data_through_bus 25543633 # Total data (bytes) 452system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes) 453system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks) |
| 429system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 454system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 430system.membus.reqLayer1.occupancy 583304500 # Layer occupancy (ticks) | 455system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks) |
| 431system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 456system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 432system.membus.reqLayer2.occupancy 3292000 # Layer occupancy (ticks) | 457system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) |
| 433system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 458system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 434system.membus.reqLayer3.occupancy 1605050249 # Layer occupancy (ticks) | 459system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks) |
| 435system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 460system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 436system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) | 461system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) |
| 437system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 462system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 438system.membus.respLayer0.occupancy 1646000 # Layer occupancy (ticks) | 463system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) |
| 439system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 464system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 440system.membus.respLayer2.occupancy 3149132971 # Layer occupancy (ticks) | 465system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks) |
| 441system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 466system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 442system.membus.respLayer4.occupancy 429400997 # Layer occupancy (ticks) | 467system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks) |
| 443system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 444system.iocache.tags.replacements 47576 # number of replacements | 468system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 469system.iocache.tags.replacements 47576 # number of replacements |
| 445system.iocache.tags.tagsinuse 0.153339 # Cycle average of tags in use | 470system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use |
| 446system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 447system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. 448system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 471system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 472system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. 473system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 449system.iocache.tags.warmup_cycle 4992838664000 # Cycle when the warmup percentage was hit. 450system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.153339 # Average occupied blocks per requestor 451system.iocache.tags.occ_percent::pc.south_bridge.ide 0.009584 # Average percentage of cache occupancy 452system.iocache.tags.occ_percent::total 0.009584 # Average percentage of cache occupancy 453system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses 454system.iocache.ReadReq_misses::total 910 # number of ReadReq misses | 474system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit. 475system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor 476system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy 477system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy 478system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 479system.iocache.ReadReq_misses::total 911 # number of ReadReq misses |
| 455system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 456system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses | 480system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 481system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses |
| 457system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses 458system.iocache.demand_misses::total 47630 # number of demand (read+write) misses 459system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses 460system.iocache.overall_misses::total 47630 # number of overall misses 461system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152977935 # number of ReadReq miss cycles 462system.iocache.ReadReq_miss_latency::total 152977935 # number of ReadReq miss cycles 463system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10361858110 # number of WriteReq miss cycles 464system.iocache.WriteReq_miss_latency::total 10361858110 # number of WriteReq miss cycles 465system.iocache.demand_miss_latency::pc.south_bridge.ide 10514836045 # number of demand (read+write) miss cycles 466system.iocache.demand_miss_latency::total 10514836045 # number of demand (read+write) miss cycles 467system.iocache.overall_miss_latency::pc.south_bridge.ide 10514836045 # number of overall miss cycles 468system.iocache.overall_miss_latency::total 10514836045 # number of overall miss cycles 469system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) 470system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) | 482system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 483system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 484system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 485system.iocache.overall_misses::total 47631 # number of overall misses 486system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles 487system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles 488system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles 489system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles 490system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles 491system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles 492system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles 493system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles 494system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 495system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) |
| 471system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 472system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) | 496system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 497system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) |
| 473system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses 474system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses 475system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses 476system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses | 498system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 499system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 500system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 501system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses |
| 477system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 478system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 479system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 480system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 481system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 482system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 483system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 484system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 502system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 503system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 504system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 505system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 506system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 507system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 508system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 509system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 485system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 168107.620879 # average ReadReq miss latency 486system.iocache.ReadReq_avg_miss_latency::total 168107.620879 # average ReadReq miss latency 487system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221786.346533 # average WriteReq miss latency 488system.iocache.WriteReq_avg_miss_latency::total 221786.346533 # average WriteReq miss latency 489system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency 490system.iocache.demand_avg_miss_latency::total 220760.781965 # average overall miss latency 491system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency 492system.iocache.overall_avg_miss_latency::total 220760.781965 # average overall miss latency 493system.iocache.blocked_cycles::no_mshrs 148180 # number of cycles access was blocked | 510system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency 511system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency 512system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency 513system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency 514system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency 515system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency 516system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency 517system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency 518system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked |
| 494system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 519system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 495system.iocache.blocked::no_mshrs 13622 # number of cycles access was blocked | 520system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked |
| 496system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 521system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 497system.iocache.avg_blocked_cycles::no_mshrs 10.877991 # average number of cycles each access was blocked | 522system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked |
| 498system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 499system.iocache.fast_writes 0 # number of fast writes performed 500system.iocache.cache_copies 0 # number of cache copies performed | 523system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 524system.iocache.fast_writes 0 # number of fast writes performed 525system.iocache.cache_copies 0 # number of cache copies performed |
| 501system.iocache.writebacks::writebacks 46668 # number of writebacks 502system.iocache.writebacks::total 46668 # number of writebacks 503system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses 504system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses | 526system.iocache.writebacks::writebacks 46667 # number of writebacks 527system.iocache.writebacks::total 46667 # number of writebacks 528system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 529system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses |
| 505system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 506system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses | 530system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 531system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses |
| 507system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses 508system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses 509system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses 510system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses 511system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105623935 # number of ReadReq MSHR miss cycles 512system.iocache.ReadReq_mshr_miss_latency::total 105623935 # number of ReadReq MSHR miss cycles 513system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7930990116 # number of WriteReq MSHR miss cycles 514system.iocache.WriteReq_mshr_miss_latency::total 7930990116 # number of WriteReq MSHR miss cycles 515system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of demand (read+write) MSHR miss cycles 516system.iocache.demand_mshr_miss_latency::total 8036614051 # number of demand (read+write) MSHR miss cycles 517system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of overall MSHR miss cycles 518system.iocache.overall_mshr_miss_latency::total 8036614051 # number of overall MSHR miss cycles | 532system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 533system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 534system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 535system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses 536system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles 537system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles 538system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles 539system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles 540system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles 541system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles 542system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles 543system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles |
| 519system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 520system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 521system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 522system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 523system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 524system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 525system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 526system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 544system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 545system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 546system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 547system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 548system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 549system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 550system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 551system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 527system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116070.258242 # average ReadReq mshr miss latency 528system.iocache.ReadReq_avg_mshr_miss_latency::total 116070.258242 # average ReadReq mshr miss latency 529system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169755.781592 # average WriteReq mshr miss latency 530system.iocache.WriteReq_avg_mshr_miss_latency::total 169755.781592 # average WriteReq mshr miss latency 531system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency 532system.iocache.demand_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency 533system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency 534system.iocache.overall_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency | 552system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency 553system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency 554system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency 555system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency 556system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency 557system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency 558system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency 559system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency |
| 535system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 536system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 537system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). | 560system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 562system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |
| 538system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). | 563system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). |
| 539system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 540system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 541system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 542system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 543system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 544system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 545system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 546system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 547system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 564system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 565system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 566system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 567system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 568system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 569system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 570system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 571system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 572system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 548system.iobus.throughput 636182 # Throughput (bytes/s) 549system.iobus.trans_dist::ReadReq 225558 # Transaction distribution 550system.iobus.trans_dist::ReadResp 225558 # Transaction distribution 551system.iobus.trans_dist::WriteReq 57591 # Transaction distribution 552system.iobus.trans_dist::WriteResp 57591 # Transaction distribution 553system.iobus.trans_dist::MessageReq 1646 # Transaction distribution 554system.iobus.trans_dist::MessageResp 1646 # Transaction distribution | 573system.iobus.throughput 638153 # Throughput (bytes/s) 574system.iobus.trans_dist::ReadReq 225567 # Transaction distribution 575system.iobus.trans_dist::ReadResp 225567 # Transaction distribution 576system.iobus.trans_dist::WriteReq 57606 # Transaction distribution 577system.iobus.trans_dist::WriteResp 57606 # Transaction distribution 578system.iobus.trans_dist::MessageReq 1643 # Transaction distribution 579system.iobus.trans_dist::MessageResp 1643 # Transaction distribution |
| 555system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 556system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) | 580system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 581system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) |
| 557system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) | 582system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) |
| 558system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 559system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 560system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 561system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 562system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 563system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 564system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 565system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 566system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 567system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 568system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 569system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 570system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 571system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 572system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) | 583system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 595system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 596system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 597system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) |
| 573system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) 574system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) 575system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) 576system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3292 # Packet count per connected master and slave (bytes) 577system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3292 # Packet count per connected master and slave (bytes) 578system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) | 598system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) 599system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) 600system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) 601system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) 602system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) 603system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes) |
| 579system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 580system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) | 604system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 605system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) |
| 581system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) | 606system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) |
| 582system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 583system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 584system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 585system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 586system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 587system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 588system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 589system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 590system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 591system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 592system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 593system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 594system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 595system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 596system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) | 607system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 608system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) |
| 597system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) 598system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) 599system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) 600system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6584 # Cumulative packet size per connected master and slave (bytes) 601system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6584 # Cumulative packet size per connected master and slave (bytes) 602system.iobus.tot_pkt_size::total 3276210 # Cumulative packet size per connected master and slave (bytes) 603system.iobus.data_through_bus 3276210 # Total data (bytes) 604system.iobus.reqLayer0.occupancy 3927144 # Layer occupancy (ticks) | 622system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.data_through_bus 3276232 # Total data (bytes) 629system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks) |
| 605system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 606system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 607system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 608system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 609system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 630system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 631system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 632system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 633system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 634system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 610system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) | 635system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) |
| 611system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 612system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 613system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 614system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 615system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 616system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 617system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 618system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) --- 13 unchanged lines hidden (view full) --- 632system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 633system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 634system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 635system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 636system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 637system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 638system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 639system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 636system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 637system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 638system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 639system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 640system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 641system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 642system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 643system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) --- 13 unchanged lines hidden (view full) --- 657system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 658system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 660system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 662system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 664system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 640system.iobus.reqLayer18.occupancy 424444048 # Layer occupancy (ticks) | 665system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks) |
| 641system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 642system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 643system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) | 666system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 667system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 668system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) |
| 644system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) | 669system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) |
| 645system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 670system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 646system.iobus.respLayer1.occupancy 53407003 # Layer occupancy (ticks) | 671system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks) |
| 647system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 672system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 648system.iobus.respLayer2.occupancy 1646000 # Layer occupancy (ticks) | 673system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) |
| 649system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) | 674system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 650system.cpu.branchPred.lookups 85588006 # Number of BP lookups 651system.cpu.branchPred.condPredicted 85588006 # Number of conditional branches predicted 652system.cpu.branchPred.condIncorrect 877454 # Number of conditional branches incorrect 653system.cpu.branchPred.BTBLookups 79215990 # Number of BTB lookups 654system.cpu.branchPred.BTBHits 77530840 # Number of BTB hits | 675system.cpu.branchPred.lookups 85592238 # Number of BP lookups 676system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted 677system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect 678system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups 679system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits |
| 655system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 680system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 656system.cpu.branchPred.BTBHitPct 97.872715 # BTB Hit Percentage 657system.cpu.branchPred.usedRAS 1437704 # Number of times the RAS was used to get a target. 658system.cpu.branchPred.RASInCorrect 180381 # Number of incorrect RAS predictions. 659system.cpu.numCycles 453669464 # number of cpu cycles simulated | 681system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage 682system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target. 683system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions. 684system.cpu.numCycles 453841851 # number of cpu cycles simulated |
| 660system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 661system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 685system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 686system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 662system.cpu.fetch.icacheStallCycles 25482716 # Number of cycles fetch is stalled on an Icache miss 663system.cpu.fetch.Insts 422686689 # Number of instructions fetch has processed 664system.cpu.fetch.Branches 85588006 # Number of branches that fetch encountered 665system.cpu.fetch.predictedBranches 78968544 # Number of branches that fetch has predicted taken 666system.cpu.fetch.Cycles 162633276 # Number of cycles fetch has run and was not squashing or blocked 667system.cpu.fetch.SquashCycles 3972302 # Number of cycles fetch has spent squashing 668system.cpu.fetch.TlbCycles 106554 # Number of cycles fetch has spent waiting for tlb 669system.cpu.fetch.BlockedCycles 71193509 # Number of cycles fetch has spent blocked 670system.cpu.fetch.MiscStallCycles 45334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 671system.cpu.fetch.PendingTrapStallCycles 89294 # Number of stall cycles due to pending traps 672system.cpu.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR 673system.cpu.fetch.CacheLines 8469801 # Number of cache lines fetched 674system.cpu.fetch.IcacheSquashes 382535 # Number of outstanding Icache misses that were squashed 675system.cpu.fetch.ItlbSquashes 2385 # Number of outstanding ITLB misses that were squashed 676system.cpu.fetch.rateDist::samples 262601517 # Number of instructions fetched each cycle (Total) 677system.cpu.fetch.rateDist::mean 3.178991 # Number of instructions fetched each cycle (Total) 678system.cpu.fetch.rateDist::stdev 3.411463 # Number of instructions fetched each cycle (Total) | 687system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss 688system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed 689system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered 690system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken 691system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked 692system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing 693system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb 694system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked 695system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 696system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps 697system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR 698system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched 699system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed 700system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed 701system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total) 702system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total) 703system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total) |
| 679system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 704system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 680system.cpu.fetch.rateDist::0 100383881 38.23% 38.23% # Number of instructions fetched each cycle (Total) 681system.cpu.fetch.rateDist::1 1533037 0.58% 38.81% # Number of instructions fetched each cycle (Total) 682system.cpu.fetch.rateDist::2 71821115 27.35% 66.16% # Number of instructions fetched each cycle (Total) 683system.cpu.fetch.rateDist::3 895642 0.34% 66.50% # Number of instructions fetched each cycle (Total) 684system.cpu.fetch.rateDist::4 1564995 0.60% 67.10% # Number of instructions fetched each cycle (Total) 685system.cpu.fetch.rateDist::5 2390879 0.91% 68.01% # Number of instructions fetched each cycle (Total) 686system.cpu.fetch.rateDist::6 1017520 0.39% 68.40% # Number of instructions fetched each cycle (Total) 687system.cpu.fetch.rateDist::7 1329446 0.51% 68.90% # Number of instructions fetched each cycle (Total) 688system.cpu.fetch.rateDist::8 81665002 31.10% 100.00% # Number of instructions fetched each cycle (Total) | 705system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total) 706system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total) 707system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total) 708system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total) 709system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total) 710system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total) 711system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total) 712system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total) 713system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total) |
| 689system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 690system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 691system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 714system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 715system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 716system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 692system.cpu.fetch.rateDist::total 262601517 # Number of instructions fetched each cycle (Total) 693system.cpu.fetch.branchRate 0.188657 # Number of branch fetches per cycle 694system.cpu.fetch.rate 0.931706 # Number of inst fetches per cycle 695system.cpu.decode.IdleCycles 29392698 # Number of cycles decode is idle 696system.cpu.decode.BlockedCycles 68340203 # Number of cycles decode is blocked 697system.cpu.decode.RunCycles 158479192 # Number of cycles decode is running 698system.cpu.decode.UnblockCycles 3338868 # Number of cycles decode is unblocking 699system.cpu.decode.SquashCycles 3050556 # Number of cycles decode is squashing 700system.cpu.decode.DecodedInsts 832478930 # Number of instructions handled by decode 701system.cpu.decode.SquashedInsts 959 # Number of squashed instructions handled by decode 702system.cpu.rename.SquashCycles 3050556 # Number of cycles rename is squashing 703system.cpu.rename.IdleCycles 32088006 # Number of cycles rename is idle 704system.cpu.rename.BlockCycles 43079490 # Number of cycles rename is blocking 705system.cpu.rename.serializeStallCycles 12529275 # count of cycles rename stalled for serializing inst 706system.cpu.rename.RunCycles 158770454 # Number of cycles rename is running 707system.cpu.rename.UnblockCycles 13083736 # Number of cycles rename is unblocking 708system.cpu.rename.RenamedInsts 829577701 # Number of instructions processed by rename 709system.cpu.rename.ROBFullEvents 21771 # Number of times rename has blocked due to ROB full 710system.cpu.rename.IQFullEvents 6064622 # Number of times rename has blocked due to IQ full 711system.cpu.rename.LSQFullEvents 5141489 # Number of times rename has blocked due to LSQ full 712system.cpu.rename.RenamedOperands 991205554 # Number of destination operands rename has renamed 713system.cpu.rename.RenameLookups 1800191267 # Number of register rename lookups that rename has made 714system.cpu.rename.int_rename_lookups 1106790785 # Number of integer rename lookups 715system.cpu.rename.fp_rename_lookups 123 # Number of floating rename lookups 716system.cpu.rename.CommittedMaps 963930499 # Number of HB maps that are committed 717system.cpu.rename.UndoneMaps 27275048 # Number of HB maps that are undone due to squashing 718system.cpu.rename.serializingInsts 452761 # count of serializing insts renamed 719system.cpu.rename.tempSerializingInsts 458610 # count of temporary serializing insts renamed 720system.cpu.rename.skidInsts 29575764 # count of insts added to the skid buffer 721system.cpu.memDep0.insertedLoads 16714812 # Number of loads inserted to the mem dependence unit. 722system.cpu.memDep0.insertedStores 9817459 # Number of stores inserted to the mem dependence unit. 723system.cpu.memDep0.conflictingLoads 1139197 # Number of conflicting loads. 724system.cpu.memDep0.conflictingStores 962008 # Number of conflicting stores. 725system.cpu.iq.iqInstsAdded 824812969 # Number of instructions added to the IQ (excludes non-spec) 726system.cpu.iq.iqNonSpecInstsAdded 1184552 # Number of non-speculative instructions added to the IQ 727system.cpu.iq.iqInstsIssued 820895267 # Number of instructions issued 728system.cpu.iq.iqSquashedInstsIssued 151456 # Number of squashed instructions issued 729system.cpu.iq.iqSquashedInstsExamined 19155682 # Number of squashed instructions iterated over during squash; mainly for profiling 730system.cpu.iq.iqSquashedOperandsExamined 29185416 # Number of squashed operands that are examined and possibly removed from graph 731system.cpu.iq.iqSquashedNonSpecRemoved 129934 # Number of squashed non-spec instructions that were removed 732system.cpu.iq.issued_per_cycle::samples 262601517 # Number of insts issued each cycle 733system.cpu.iq.issued_per_cycle::mean 3.126011 # Number of insts issued each cycle 734system.cpu.iq.issued_per_cycle::stdev 2.400353 # Number of insts issued each cycle | 717system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total) 718system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle 719system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle 720system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle 721system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked 722system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running 723system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking 724system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing 725system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode 726system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode 727system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing 728system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle 729system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking 730system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst 731system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running 732system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking 733system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename 734system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full 735system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full 736system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full 737system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed 738system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made 739system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups 740system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups 741system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed 742system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing 743system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed 744system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed 745system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer 746system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit. 747system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit. 748system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads. 749system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores. 750system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec) 751system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ 752system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued 753system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued 754system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling 755system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph 756system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed 757system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle 758system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle 759system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle |
| 735system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 760system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 736system.cpu.iq.issued_per_cycle::0 76255592 29.04% 29.04% # Number of insts issued each cycle 737system.cpu.iq.issued_per_cycle::1 15761044 6.00% 35.04% # Number of insts issued each cycle 738system.cpu.iq.issued_per_cycle::2 10531368 4.01% 39.05% # Number of insts issued each cycle 739system.cpu.iq.issued_per_cycle::3 7369443 2.81% 41.86% # Number of insts issued each cycle 740system.cpu.iq.issued_per_cycle::4 75730840 28.84% 70.70% # Number of insts issued each cycle 741system.cpu.iq.issued_per_cycle::5 3739599 1.42% 72.12% # Number of insts issued each cycle 742system.cpu.iq.issued_per_cycle::6 72299562 27.53% 99.65% # Number of insts issued each cycle 743system.cpu.iq.issued_per_cycle::7 768121 0.29% 99.94% # Number of insts issued each cycle 744system.cpu.iq.issued_per_cycle::8 145948 0.06% 100.00% # Number of insts issued each cycle | 761system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle 762system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle 763system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle 764system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle 765system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle 766system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle 767system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle 768system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle 769system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle |
| 745system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 746system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 747system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 770system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 771system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 772system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 748system.cpu.iq.issued_per_cycle::total 262601517 # Number of insts issued each cycle | 773system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle |
| 749system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 774system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 750system.cpu.iq.fu_full::IntAlu 345012 32.94% 32.94% # attempts to use FU when none available 751system.cpu.iq.fu_full::IntMult 241 0.02% 32.97% # attempts to use FU when none available 752system.cpu.iq.fu_full::IntDiv 974 0.09% 33.06% # attempts to use FU when none available 753system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.06% # attempts to use FU when none available 754system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.06% # attempts to use FU when none available 755system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.06% # attempts to use FU when none available 756system.cpu.iq.fu_full::FloatMult 0 0.00% 33.06% # attempts to use FU when none available 757system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.06% # attempts to use FU when none available 758system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.06% # attempts to use FU when none available 759system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.06% # attempts to use FU when none available 760system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.06% # attempts to use FU when none available 761system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.06% # attempts to use FU when none available 762system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.06% # attempts to use FU when none available 763system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.06% # attempts to use FU when none available 764system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.06% # attempts to use FU when none available 765system.cpu.iq.fu_full::SimdMult 0 0.00% 33.06% # attempts to use FU when none available 766system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.06% # attempts to use FU when none available 767system.cpu.iq.fu_full::SimdShift 0 0.00% 33.06% # attempts to use FU when none available 768system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.06% # attempts to use FU when none available 769system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.06% # attempts to use FU when none available 770system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.06% # attempts to use FU when none available 771system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.06% # attempts to use FU when none available 772system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.06% # attempts to use FU when none available 773system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.06% # attempts to use FU when none available 774system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.06% # attempts to use FU when none available 775system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.06% # attempts to use FU when none available 776system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.06% # attempts to use FU when none available 777system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.06% # attempts to use FU when none available 778system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.06% # attempts to use FU when none available 779system.cpu.iq.fu_full::MemRead 547730 52.30% 85.36% # attempts to use FU when none available 780system.cpu.iq.fu_full::MemWrite 153356 14.64% 100.00% # attempts to use FU when none available | 775system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available 776system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available 777system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available 778system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available 779system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available 780system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available 781system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available 782system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available 783system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available 784system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available 785system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available 786system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available 787system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available 788system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available 789system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available 790system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available 791system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available 792system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available 793system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available 794system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available 795system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available 796system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available 797system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available 798system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available 799system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available 800system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available 801system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available 802system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available 803system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available 804system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available 805system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available |
| 781system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 782system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 806system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 807system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 783system.cpu.iq.FU_type_0::No_OpClass 307746 0.04% 0.04% # Type of FU issued 784system.cpu.iq.FU_type_0::IntAlu 793434579 96.65% 96.69% # Type of FU issued 785system.cpu.iq.FU_type_0::IntMult 149572 0.02% 96.71% # Type of FU issued 786system.cpu.iq.FU_type_0::IntDiv 124688 0.02% 96.73% # Type of FU issued 787system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.73% # Type of FU issued 788system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.73% # Type of FU issued 789system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.73% # Type of FU issued 790system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.73% # Type of FU issued 791system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.73% # Type of FU issued 792system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.73% # Type of FU issued 793system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.73% # Type of FU issued 794system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.73% # Type of FU issued 795system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.73% # Type of FU issued 796system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.73% # Type of FU issued 797system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.73% # Type of FU issued 798system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.73% # Type of FU issued 799system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.73% # Type of FU issued 800system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.73% # Type of FU issued 801system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.73% # Type of FU issued 802system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.73% # Type of FU issued 803system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.73% # Type of FU issued 804system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.73% # Type of FU issued 805system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.73% # Type of FU issued 806system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.73% # Type of FU issued 807system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.73% # Type of FU issued 808system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.73% # Type of FU issued 809system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.73% # Type of FU issued 810system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.73% # Type of FU issued 811system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.73% # Type of FU issued 812system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.73% # Type of FU issued 813system.cpu.iq.FU_type_0::MemRead 17663300 2.15% 98.88% # Type of FU issued 814system.cpu.iq.FU_type_0::MemWrite 9215382 1.12% 100.00% # Type of FU issued | 808system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued 809system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued 810system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued 811system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued 812system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued 813system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued 814system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued 815system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued 816system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued 817system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued 818system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued 819system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued 820system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued 821system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued 822system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued 823system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued 824system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued 825system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued 826system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued 827system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued 828system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued 829system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued 830system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued 831system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued 832system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued 833system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued 834system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued 835system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued 836system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued 837system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued 838system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued 839system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued |
| 815system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 816system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 840system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 841system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 817system.cpu.iq.FU_type_0::total 820895267 # Type of FU issued 818system.cpu.iq.rate 1.809457 # Inst issue rate 819system.cpu.iq.fu_busy_cnt 1047313 # FU busy when requested 820system.cpu.iq.fu_busy_rate 0.001276 # FU busy rate (busy events/executed inst) 821system.cpu.iq.int_inst_queue_reads 1905699959 # Number of integer instruction queue reads 822system.cpu.iq.int_inst_queue_writes 845163637 # Number of integer instruction queue writes 823system.cpu.iq.int_inst_queue_wakeup_accesses 816985295 # Number of integer instruction queue wakeup accesses 824system.cpu.iq.fp_inst_queue_reads 199 # Number of floating instruction queue reads 825system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes 826system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses 827system.cpu.iq.int_alu_accesses 821634741 # Number of integer alu accesses 828system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses 829system.cpu.iew.lsq.thread0.forwLoads 1691465 # Number of loads that had data forwarded from stores | 842system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued 843system.cpu.iq.rate 1.808871 # Inst issue rate 844system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested 845system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst) 846system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads 847system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes 848system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses 849system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads 850system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes 851system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses 852system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses 853system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses 854system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores |
| 830system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 855system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 831system.cpu.iew.lsq.thread0.squashedLoads 2728859 # Number of loads squashed 832system.cpu.iew.lsq.thread0.ignoredResponses 17017 # Number of memory responses ignored because the instruction is squashed 833system.cpu.iew.lsq.thread0.memOrderViolation 11975 # Number of memory ordering violations 834system.cpu.iew.lsq.thread0.squashedStores 1400009 # Number of stores squashed | 856system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed 857system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed 858system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations 859system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed |
| 835system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 836system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 860system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 861system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 837system.cpu.iew.lsq.thread0.rescheduledLoads 1931860 # Number of loads that were rescheduled 838system.cpu.iew.lsq.thread0.cacheBlocked 12243 # Number of times an access to memory failed due to the cache being blocked | 862system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled 863system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked |
| 839system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 864system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 840system.cpu.iew.iewSquashCycles 3050556 # Number of cycles IEW is squashing 841system.cpu.iew.iewBlockCycles 31208951 # Number of cycles IEW is blocking 842system.cpu.iew.iewUnblockCycles 2150350 # Number of cycles IEW is unblocking 843system.cpu.iew.iewDispatchedInsts 825997521 # Number of instructions dispatched to IQ 844system.cpu.iew.iewDispSquashedInsts 243405 # Number of squashed instructions skipped by dispatch 845system.cpu.iew.iewDispLoadInsts 16714812 # Number of dispatched load instructions 846system.cpu.iew.iewDispStoreInsts 9817459 # Number of dispatched store instructions 847system.cpu.iew.iewDispNonSpecInsts 689575 # Number of dispatched non-speculative instructions 848system.cpu.iew.iewIQFullEvents 1619766 # Number of times the IQ has become full, causing a stall 849system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall 850system.cpu.iew.memOrderViolationEvents 11975 # Number of memory order violations 851system.cpu.iew.predictedTakenIncorrect 493977 # Number of branches that were predicted taken incorrectly 852system.cpu.iew.predictedNotTakenIncorrect 506066 # Number of branches that were predicted not taken incorrectly 853system.cpu.iew.branchMispredicts 1000043 # Number of branch mispredicts detected at execute 854system.cpu.iew.iewExecutedInsts 819488058 # Number of executed instructions 855system.cpu.iew.iewExecLoadInsts 17361171 # Number of load instructions executed 856system.cpu.iew.iewExecSquashedInsts 1407208 # Number of squashed instructions skipped in execute | 865system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing 866system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking 867system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking 868system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ 869system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch 870system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions 871system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions 872system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions 873system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall 874system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall 875system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations 876system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly 877system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly 878system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute 879system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions 880system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed 881system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute |
| 857system.cpu.iew.exec_swp 0 # number of swp insts executed 858system.cpu.iew.exec_nop 0 # number of nop insts executed | 882system.cpu.iew.exec_swp 0 # number of swp insts executed 883system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 859system.cpu.iew.exec_refs 26390625 # number of memory reference insts executed 860system.cpu.iew.exec_branches 83079645 # Number of branches executed 861system.cpu.iew.exec_stores 9029454 # Number of stores executed 862system.cpu.iew.exec_rate 1.806355 # Inst execution rate 863system.cpu.iew.wb_sent 819086222 # cumulative count of insts sent to commit 864system.cpu.iew.wb_count 816985349 # cumulative count of insts written-back 865system.cpu.iew.wb_producers 638544896 # num instructions producing a value 866system.cpu.iew.wb_consumers 1043866074 # num instructions consuming a value | 884system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed 885system.cpu.iew.exec_branches 83090404 # Number of branches executed 886system.cpu.iew.exec_stores 9036920 # Number of stores executed 887system.cpu.iew.exec_rate 1.805776 # Inst execution rate 888system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit 889system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back 890system.cpu.iew.wb_producers 638560375 # num instructions producing a value 891system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value |
| 867system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 892system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 868system.cpu.iew.wb_rate 1.800838 # insts written-back per cycle 869system.cpu.iew.wb_fanout 0.611712 # average fanout of values written-back | 893system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle 894system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back |
| 870system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 895system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 871system.cpu.commit.commitSquashedInsts 19867682 # The number of squashed insts skipped by commit 872system.cpu.commit.commitNonSpecStalls 1054616 # The number of times commit has been forced to stall to communicate backwards 873system.cpu.commit.branchMispredicts 887449 # The number of times a branch was mispredicted 874system.cpu.commit.committed_per_cycle::samples 259550960 # Number of insts commited each cycle 875system.cpu.commit.committed_per_cycle::mean 3.105446 # Number of insts commited each cycle 876system.cpu.commit.committed_per_cycle::stdev 2.863698 # Number of insts commited each cycle | 896system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit 897system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards 898system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted 899system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle 900system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle 901system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle |
| 877system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 902system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 878system.cpu.commit.committed_per_cycle::0 88027122 33.92% 33.92% # Number of insts commited each cycle 879system.cpu.commit.committed_per_cycle::1 11847553 4.56% 38.48% # Number of insts commited each cycle 880system.cpu.commit.committed_per_cycle::2 3827434 1.47% 39.95% # Number of insts commited each cycle 881system.cpu.commit.committed_per_cycle::3 74752127 28.80% 68.75% # Number of insts commited each cycle 882system.cpu.commit.committed_per_cycle::4 2379438 0.92% 69.67% # Number of insts commited each cycle 883system.cpu.commit.committed_per_cycle::5 1475953 0.57% 70.24% # Number of insts commited each cycle 884system.cpu.commit.committed_per_cycle::6 857436 0.33% 70.57% # Number of insts commited each cycle 885system.cpu.commit.committed_per_cycle::7 70850710 27.30% 97.87% # Number of insts commited each cycle 886system.cpu.commit.committed_per_cycle::8 5533187 2.13% 100.00% # Number of insts commited each cycle | 903system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle 904system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle 905system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle 906system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle 907system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle 908system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle 909system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle 910system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle 911system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle |
| 887system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 888system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 889system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 912system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 913system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 914system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 890system.cpu.commit.committed_per_cycle::total 259550960 # Number of insts commited each cycle 891system.cpu.commit.committedInsts 407752265 # Number of instructions committed 892system.cpu.commit.committedOps 806021401 # Number of ops (including micro ops) committed | 915system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle 916system.cpu.commit.committedInsts 407772261 # Number of instructions committed 917system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed |
| 893system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 918system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 894system.cpu.commit.refs 22403400 # Number of memory references committed 895system.cpu.commit.loads 13985950 # Number of loads committed 896system.cpu.commit.membars 474657 # Number of memory barriers committed 897system.cpu.commit.branches 82156128 # Number of branches committed | 919system.cpu.commit.refs 22412414 # Number of memory references committed 920system.cpu.commit.loads 13990896 # Number of loads committed 921system.cpu.commit.membars 474709 # Number of memory barriers committed 922system.cpu.commit.branches 82160310 # Number of branches committed |
| 898system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 923system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 899system.cpu.commit.int_insts 734862948 # Number of committed integer instructions. 900system.cpu.commit.function_calls 1155170 # Number of function calls committed. 901system.cpu.commit.bw_lim_events 5533187 # number cycles where commit BW limit reached | 924system.cpu.commit.int_insts 734896243 # Number of committed integer instructions. 925system.cpu.commit.function_calls 1155289 # Number of function calls committed. 926system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached |
| 902system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 927system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 903system.cpu.rob.rob_reads 1079828496 # The number of ROB reads 904system.cpu.rob.rob_writes 1654843441 # The number of ROB writes 905system.cpu.timesIdled 1258915 # Number of times that the entire CPU went into an idle state and unscheduled itself 906system.cpu.idleCycles 191067947 # Total number of cycles that the CPU has spent unscheduled due to idling 907system.cpu.quiesceCycles 9845938983 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 908system.cpu.committedInsts 407752265 # Number of Instructions Simulated 909system.cpu.committedOps 806021401 # Number of Ops (including micro ops) Simulated 910system.cpu.committedInsts_total 407752265 # Number of Instructions Simulated 911system.cpu.cpi 1.112611 # CPI: Cycles Per Instruction 912system.cpu.cpi_total 1.112611 # CPI: Total CPI of All Threads 913system.cpu.ipc 0.898787 # IPC: Instructions Per Cycle 914system.cpu.ipc_total 0.898787 # IPC: Total IPC of All Threads 915system.cpu.int_regfile_reads 1088694796 # number of integer regfile reads 916system.cpu.int_regfile_writes 653771353 # number of integer regfile writes 917system.cpu.fp_regfile_reads 54 # number of floating regfile reads 918system.cpu.cc_regfile_reads 415601025 # number of cc regfile reads 919system.cpu.cc_regfile_writes 321483560 # number of cc regfile writes 920system.cpu.misc_regfile_reads 264032145 # number of misc regfile reads 921system.cpu.misc_regfile_writes 402444 # number of misc regfile writes 922system.cpu.toL2Bus.throughput 53392020 # Throughput (bytes/s) 923system.cpu.toL2Bus.trans_dist::ReadReq 3013693 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::ReadResp 3013151 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::WriteReq 13770 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::WriteResp 13770 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::Writeback 1577044 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadExReq 334035 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadExResp 287322 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution 933system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908198 # Packet count per connected master and slave (bytes) 934system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121437 # Packet count per connected master and slave (bytes) 935system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18680 # Packet count per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 151603 # Packet count per connected master and slave (bytes) 937system.cpu.toL2Bus.pkt_count::total 8199918 # Packet count per connected master and slave (bytes) 938system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61058944 # Cumulative packet size per connected master and slave (bytes) 939system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207524391 # Cumulative packet size per connected master and slave (bytes) 940system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 566848 # Cumulative packet size per connected master and slave (bytes) 941system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5217216 # Cumulative packet size per connected master and slave (bytes) 942system.cpu.toL2Bus.tot_pkt_size::total 274367399 # Cumulative packet size per connected master and slave (bytes) 943system.cpu.toL2Bus.data_through_bus 274343271 # Total data (bytes) 944system.cpu.toL2Bus.snoop_data_through_bus 615040 # Total snoop data (bytes) 945system.cpu.toL2Bus.reqLayer0.occupancy 4030545417 # Layer occupancy (ticks) | 928system.cpu.rob.rob_reads 1080212949 # The number of ROB reads 929system.cpu.rob.rob_writes 1654925831 # The number of ROB writes 930system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself 931system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling 932system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 933system.cpu.committedInsts 407772261 # Number of Instructions Simulated 934system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated 935system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated 936system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction 937system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads 938system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle 939system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads 940system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads 941system.cpu.int_regfile_writes 653799671 # number of integer regfile writes 942system.cpu.fp_regfile_reads 52 # number of floating regfile reads 943system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads 944system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes 945system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads 946system.cpu.misc_regfile_writes 402440 # number of misc regfile writes 947system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s) 948system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution 949system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution 956system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution 957system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution 958system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes) 959system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes) 961system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes) 962system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes) 963system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes) 964system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes) 965system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes) 966system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes) 967system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes) 968system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes) 969system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes) 970system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks) |
| 946system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 971system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 947system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) | 972system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks) |
| 948system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 973system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 949system.cpu.toL2Bus.respLayer0.occupancy 1435258580 # Layer occupancy (ticks) | 974system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks) |
| 950system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 975system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 951system.cpu.toL2Bus.respLayer1.occupancy 3141587747 # Layer occupancy (ticks) | 976system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks) |
| 952system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 977system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 953system.cpu.toL2Bus.respLayer2.occupancy 14741736 # Layer occupancy (ticks) | 978system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks) |
| 954system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 979system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 955system.cpu.toL2Bus.respLayer3.occupancy 105191645 # Layer occupancy (ticks) | 980system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks) |
| 956system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 981system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 957system.cpu.icache.tags.replacements 953576 # number of replacements 958system.cpu.icache.tags.tagsinuse 510.036469 # Cycle average of tags in use 959system.cpu.icache.tags.total_refs 7463561 # Total number of references to valid blocks. 960system.cpu.icache.tags.sampled_refs 954088 # Sample count of references to valid blocks. 961system.cpu.icache.tags.avg_refs 7.822718 # Average number of references to valid blocks. 962system.cpu.icache.tags.warmup_cycle 147479259250 # Cycle when the warmup percentage was hit. 963system.cpu.icache.tags.occ_blocks::cpu.inst 510.036469 # Average occupied blocks per requestor 964system.cpu.icache.tags.occ_percent::cpu.inst 0.996165 # Average percentage of cache occupancy 965system.cpu.icache.tags.occ_percent::total 0.996165 # Average percentage of cache occupancy 966system.cpu.icache.ReadReq_hits::cpu.inst 7463561 # number of ReadReq hits 967system.cpu.icache.ReadReq_hits::total 7463561 # number of ReadReq hits 968system.cpu.icache.demand_hits::cpu.inst 7463561 # number of demand (read+write) hits 969system.cpu.icache.demand_hits::total 7463561 # number of demand (read+write) hits 970system.cpu.icache.overall_hits::cpu.inst 7463561 # number of overall hits 971system.cpu.icache.overall_hits::total 7463561 # number of overall hits 972system.cpu.icache.ReadReq_misses::cpu.inst 1006237 # number of ReadReq misses 973system.cpu.icache.ReadReq_misses::total 1006237 # number of ReadReq misses 974system.cpu.icache.demand_misses::cpu.inst 1006237 # number of demand (read+write) misses 975system.cpu.icache.demand_misses::total 1006237 # number of demand (read+write) misses 976system.cpu.icache.overall_misses::cpu.inst 1006237 # number of overall misses 977system.cpu.icache.overall_misses::total 1006237 # number of overall misses 978system.cpu.icache.ReadReq_miss_latency::cpu.inst 14239259264 # number of ReadReq miss cycles 979system.cpu.icache.ReadReq_miss_latency::total 14239259264 # number of ReadReq miss cycles 980system.cpu.icache.demand_miss_latency::cpu.inst 14239259264 # number of demand (read+write) miss cycles 981system.cpu.icache.demand_miss_latency::total 14239259264 # number of demand (read+write) miss cycles 982system.cpu.icache.overall_miss_latency::cpu.inst 14239259264 # number of overall miss cycles 983system.cpu.icache.overall_miss_latency::total 14239259264 # number of overall miss cycles 984system.cpu.icache.ReadReq_accesses::cpu.inst 8469798 # number of ReadReq accesses(hits+misses) 985system.cpu.icache.ReadReq_accesses::total 8469798 # number of ReadReq accesses(hits+misses) 986system.cpu.icache.demand_accesses::cpu.inst 8469798 # number of demand (read+write) accesses 987system.cpu.icache.demand_accesses::total 8469798 # number of demand (read+write) accesses 988system.cpu.icache.overall_accesses::cpu.inst 8469798 # number of overall (read+write) accesses 989system.cpu.icache.overall_accesses::total 8469798 # number of overall (read+write) accesses 990system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118803 # miss rate for ReadReq accesses 991system.cpu.icache.ReadReq_miss_rate::total 0.118803 # miss rate for ReadReq accesses 992system.cpu.icache.demand_miss_rate::cpu.inst 0.118803 # miss rate for demand accesses 993system.cpu.icache.demand_miss_rate::total 0.118803 # miss rate for demand accesses 994system.cpu.icache.overall_miss_rate::cpu.inst 0.118803 # miss rate for overall accesses 995system.cpu.icache.overall_miss_rate::total 0.118803 # miss rate for overall accesses 996system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14150.999480 # average ReadReq miss latency 997system.cpu.icache.ReadReq_avg_miss_latency::total 14150.999480 # average ReadReq miss latency 998system.cpu.icache.demand_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency 999system.cpu.icache.demand_avg_miss_latency::total 14150.999480 # average overall miss latency 1000system.cpu.icache.overall_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency 1001system.cpu.icache.overall_avg_miss_latency::total 14150.999480 # average overall miss latency 1002system.cpu.icache.blocked_cycles::no_mshrs 7035 # number of cycles access was blocked 1003system.cpu.icache.blocked_cycles::no_targets 587 # number of cycles access was blocked 1004system.cpu.icache.blocked::no_mshrs 207 # number of cycles access was blocked 1005system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 1006system.cpu.icache.avg_blocked_cycles::no_mshrs 33.985507 # average number of cycles each access was blocked 1007system.cpu.icache.avg_blocked_cycles::no_targets 587 # average number of cycles each access was blocked | 982system.cpu.icache.tags.replacements 959142 # number of replacements 983system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use 984system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks. 985system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks. 986system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks. 987system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. 988system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor 989system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy 990system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy 991system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits 992system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits 993system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits 994system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits 995system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits 996system.cpu.icache.overall_hits::total 7468451 # number of overall hits 997system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses 998system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses 999system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses 1000system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses 1001system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses 1002system.cpu.icache.overall_misses::total 1013022 # number of overall misses 1003system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles 1004system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles 1005system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles 1006system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles 1007system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles 1008system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles 1009system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses) 1010system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses) 1011system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses 1012system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses 1013system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses 1014system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses 1015system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses 1016system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses 1017system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses 1018system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses 1019system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses 1020system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses 1021system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency 1022system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency 1023system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency 1024system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency 1025system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency 1026system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency 1027system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked 1028system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1029system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked 1030system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1031system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked 1032system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1008system.cpu.icache.fast_writes 0 # number of fast writes performed 1009system.cpu.icache.cache_copies 0 # number of cache copies performed | 1033system.cpu.icache.fast_writes 0 # number of fast writes performed 1034system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 1010system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52085 # number of ReadReq MSHR hits 1011system.cpu.icache.ReadReq_mshr_hits::total 52085 # number of ReadReq MSHR hits 1012system.cpu.icache.demand_mshr_hits::cpu.inst 52085 # number of demand (read+write) MSHR hits 1013system.cpu.icache.demand_mshr_hits::total 52085 # number of demand (read+write) MSHR hits 1014system.cpu.icache.overall_mshr_hits::cpu.inst 52085 # number of overall MSHR hits 1015system.cpu.icache.overall_mshr_hits::total 52085 # number of overall MSHR hits 1016system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954152 # number of ReadReq MSHR misses 1017system.cpu.icache.ReadReq_mshr_misses::total 954152 # number of ReadReq MSHR misses 1018system.cpu.icache.demand_mshr_misses::cpu.inst 954152 # number of demand (read+write) MSHR misses 1019system.cpu.icache.demand_mshr_misses::total 954152 # number of demand (read+write) MSHR misses 1020system.cpu.icache.overall_mshr_misses::cpu.inst 954152 # number of overall MSHR misses 1021system.cpu.icache.overall_mshr_misses::total 954152 # number of overall MSHR misses 1022system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11748055164 # number of ReadReq MSHR miss cycles 1023system.cpu.icache.ReadReq_mshr_miss_latency::total 11748055164 # number of ReadReq MSHR miss cycles 1024system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11748055164 # number of demand (read+write) MSHR miss cycles 1025system.cpu.icache.demand_mshr_miss_latency::total 11748055164 # number of demand (read+write) MSHR miss cycles 1026system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11748055164 # number of overall MSHR miss cycles 1027system.cpu.icache.overall_mshr_miss_latency::total 11748055164 # number of overall MSHR miss cycles 1028system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for ReadReq accesses 1029system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112653 # mshr miss rate for ReadReq accesses 1030system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for demand accesses 1031system.cpu.icache.demand_mshr_miss_rate::total 0.112653 # mshr miss rate for demand accesses 1032system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for overall accesses 1033system.cpu.icache.overall_mshr_miss_rate::total 0.112653 # mshr miss rate for overall accesses 1034system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12312.561483 # average ReadReq mshr miss latency 1035system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12312.561483 # average ReadReq mshr miss latency 1036system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12312.561483 # average overall mshr miss latency 1037system.cpu.icache.demand_avg_mshr_miss_latency::total 12312.561483 # average overall mshr miss latency 1038system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12312.561483 # average overall mshr miss latency 1039system.cpu.icache.overall_avg_mshr_miss_latency::total 12312.561483 # average overall mshr miss latency | 1035system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53298 # number of ReadReq MSHR hits 1036system.cpu.icache.ReadReq_mshr_hits::total 53298 # number of ReadReq MSHR hits 1037system.cpu.icache.demand_mshr_hits::cpu.inst 53298 # number of demand (read+write) MSHR hits 1038system.cpu.icache.demand_mshr_hits::total 53298 # number of demand (read+write) MSHR hits 1039system.cpu.icache.overall_mshr_hits::cpu.inst 53298 # number of overall MSHR hits 1040system.cpu.icache.overall_mshr_hits::total 53298 # number of overall MSHR hits 1041system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959724 # number of ReadReq MSHR misses 1042system.cpu.icache.ReadReq_mshr_misses::total 959724 # number of ReadReq MSHR misses 1043system.cpu.icache.demand_mshr_misses::cpu.inst 959724 # number of demand (read+write) MSHR misses 1044system.cpu.icache.demand_mshr_misses::total 959724 # number of demand (read+write) MSHR misses 1045system.cpu.icache.overall_mshr_misses::cpu.inst 959724 # number of overall MSHR misses 1046system.cpu.icache.overall_mshr_misses::total 959724 # number of overall MSHR misses 1047system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11694537694 # number of ReadReq MSHR miss cycles 1048system.cpu.icache.ReadReq_mshr_miss_latency::total 11694537694 # number of ReadReq MSHR miss cycles 1049system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11694537694 # number of demand (read+write) MSHR miss cycles 1050system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles 1051system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles 1052system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles 1053system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses 1054system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses 1055system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for demand accesses 1056system.cpu.icache.demand_mshr_miss_rate::total 0.113155 # mshr miss rate for demand accesses 1057system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for overall accesses 1058system.cpu.icache.overall_mshr_miss_rate::total 0.113155 # mshr miss rate for overall accesses 1059system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12185.313376 # average ReadReq mshr miss latency 1060system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12185.313376 # average ReadReq mshr miss latency 1061system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency 1062system.cpu.icache.demand_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency 1063system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency 1064system.cpu.icache.overall_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency |
| 1040system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1065system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1041system.cpu.itb_walker_cache.tags.replacements 8937 # number of replacements 1042system.cpu.itb_walker_cache.tags.tagsinuse 6.031585 # Cycle average of tags in use 1043system.cpu.itb_walker_cache.tags.total_refs 20273 # Total number of references to valid blocks. 1044system.cpu.itb_walker_cache.tags.sampled_refs 8949 # Sample count of references to valid blocks. 1045system.cpu.itb_walker_cache.tags.avg_refs 2.265393 # Average number of references to valid blocks. 1046system.cpu.itb_walker_cache.tags.warmup_cycle 5104907998500 # Cycle when the warmup percentage was hit. 1047system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031585 # Average occupied blocks per requestor 1048system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376974 # Average percentage of cache occupancy 1049system.cpu.itb_walker_cache.tags.occ_percent::total 0.376974 # Average percentage of cache occupancy 1050system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20288 # number of ReadReq hits 1051system.cpu.itb_walker_cache.ReadReq_hits::total 20288 # number of ReadReq hits | 1066system.cpu.itb_walker_cache.tags.replacements 8004 # number of replacements 1067system.cpu.itb_walker_cache.tags.tagsinuse 6.959011 # Cycle average of tags in use 1068system.cpu.itb_walker_cache.tags.total_refs 21893 # Total number of references to valid blocks. 1069system.cpu.itb_walker_cache.tags.sampled_refs 8020 # Sample count of references to valid blocks. 1070system.cpu.itb_walker_cache.tags.avg_refs 2.729800 # Average number of references to valid blocks. 1071system.cpu.itb_walker_cache.tags.warmup_cycle 5103903665500 # Cycle when the warmup percentage was hit. 1072system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.959011 # Average occupied blocks per requestor 1073system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.434938 # Average percentage of cache occupancy 1074system.cpu.itb_walker_cache.tags.occ_percent::total 0.434938 # Average percentage of cache occupancy 1075system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21891 # number of ReadReq hits 1076system.cpu.itb_walker_cache.ReadReq_hits::total 21891 # number of ReadReq hits |
| 1052system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1053system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 1077system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1078system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 1054system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20290 # number of demand (read+write) hits 1055system.cpu.itb_walker_cache.demand_hits::total 20290 # number of demand (read+write) hits 1056system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20290 # number of overall hits 1057system.cpu.itb_walker_cache.overall_hits::total 20290 # number of overall hits 1058system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses 1059system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses 1060system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses 1061system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses 1062system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses 1063system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses 1064system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 106143491 # number of ReadReq miss cycles 1065system.cpu.itb_walker_cache.ReadReq_miss_latency::total 106143491 # number of ReadReq miss cycles 1066system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 106143491 # number of demand (read+write) miss cycles 1067system.cpu.itb_walker_cache.demand_miss_latency::total 106143491 # number of demand (read+write) miss cycles 1068system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 106143491 # number of overall miss cycles 1069system.cpu.itb_walker_cache.overall_miss_latency::total 106143491 # number of overall miss cycles 1070system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30111 # number of ReadReq accesses(hits+misses) 1071system.cpu.itb_walker_cache.ReadReq_accesses::total 30111 # number of ReadReq accesses(hits+misses) | 1079system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21893 # number of demand (read+write) hits 1080system.cpu.itb_walker_cache.demand_hits::total 21893 # number of demand (read+write) hits 1081system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21893 # number of overall hits 1082system.cpu.itb_walker_cache.overall_hits::total 21893 # number of overall hits 1083system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8894 # number of ReadReq misses 1084system.cpu.itb_walker_cache.ReadReq_misses::total 8894 # number of ReadReq misses 1085system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8894 # number of demand (read+write) misses 1086system.cpu.itb_walker_cache.demand_misses::total 8894 # number of demand (read+write) misses 1087system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8894 # number of overall misses 1088system.cpu.itb_walker_cache.overall_misses::total 8894 # number of overall misses 1089system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 101842497 # number of ReadReq miss cycles 1090system.cpu.itb_walker_cache.ReadReq_miss_latency::total 101842497 # number of ReadReq miss cycles 1091system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 101842497 # number of demand (read+write) miss cycles 1092system.cpu.itb_walker_cache.demand_miss_latency::total 101842497 # number of demand (read+write) miss cycles 1093system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 101842497 # number of overall miss cycles 1094system.cpu.itb_walker_cache.overall_miss_latency::total 101842497 # number of overall miss cycles 1095system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30785 # number of ReadReq accesses(hits+misses) 1096system.cpu.itb_walker_cache.ReadReq_accesses::total 30785 # number of ReadReq accesses(hits+misses) |
| 1072system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1073system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 1097system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1098system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 1074system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30113 # number of demand (read+write) accesses 1075system.cpu.itb_walker_cache.demand_accesses::total 30113 # number of demand (read+write) accesses 1076system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30113 # number of overall (read+write) accesses 1077system.cpu.itb_walker_cache.overall_accesses::total 30113 # number of overall (read+write) accesses 1078system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.326226 # miss rate for ReadReq accesses 1079system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.326226 # miss rate for ReadReq accesses 1080system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.326205 # miss rate for demand accesses 1081system.cpu.itb_walker_cache.demand_miss_rate::total 0.326205 # miss rate for demand accesses 1082system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.326205 # miss rate for overall accesses 1083system.cpu.itb_walker_cache.overall_miss_rate::total 0.326205 # miss rate for overall accesses 1084system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10805.608368 # average ReadReq miss latency 1085system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10805.608368 # average ReadReq miss latency 1086system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10805.608368 # average overall miss latency 1087system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10805.608368 # average overall miss latency 1088system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10805.608368 # average overall miss latency 1089system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10805.608368 # average overall miss latency | 1099system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30787 # number of demand (read+write) accesses 1100system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses 1101system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses 1102system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses 1103system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses 1104system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses 1105system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses 1106system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses 1107system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses 1108system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses 1109system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency 1110system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency 1111system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency 1112system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency 1113system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency 1114system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency |
| 1090system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1091system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1093system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1094system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1095system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1096system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1097system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 1115system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1116system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1117system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1118system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1119system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1120system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1121system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1122system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1098system.cpu.itb_walker_cache.writebacks::writebacks 1536 # number of writebacks 1099system.cpu.itb_walker_cache.writebacks::total 1536 # number of writebacks 1100system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses 1101system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses 1102system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses 1103system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses 1104system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses 1105system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses 1106system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86483019 # number of ReadReq MSHR miss cycles 1107system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86483019 # number of ReadReq MSHR miss cycles 1108system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86483019 # number of demand (read+write) MSHR miss cycles 1109system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86483019 # number of demand (read+write) MSHR miss cycles 1110system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86483019 # number of overall MSHR miss cycles 1111system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86483019 # number of overall MSHR miss cycles 1112system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.326226 # mshr miss rate for ReadReq accesses 1113system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.326226 # mshr miss rate for ReadReq accesses 1114system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for demand accesses 1115system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.326205 # mshr miss rate for demand accesses 1116system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for overall accesses 1117system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.326205 # mshr miss rate for overall accesses 1118system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average ReadReq mshr miss latency 1119system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8804.135091 # average ReadReq mshr miss latency 1120system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency 1121system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency 1122system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency 1123system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency | 1123system.cpu.itb_walker_cache.writebacks::writebacks 2197 # number of writebacks 1124system.cpu.itb_walker_cache.writebacks::total 2197 # number of writebacks 1125system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8894 # number of ReadReq MSHR misses 1126system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses 1127system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8894 # number of demand (read+write) MSHR misses 1128system.cpu.itb_walker_cache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses 1129system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8894 # number of overall MSHR misses 1130system.cpu.itb_walker_cache.overall_mshr_misses::total 8894 # number of overall MSHR misses 1131system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 84047009 # number of ReadReq MSHR miss cycles 1132system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 84047009 # number of ReadReq MSHR miss cycles 1133system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 84047009 # number of demand (read+write) MSHR miss cycles 1134system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 84047009 # number of demand (read+write) MSHR miss cycles 1135system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 84047009 # number of overall MSHR miss cycles 1136system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles 1137system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses 1138system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses 1139system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses 1140system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses 1141system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses 1142system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses 1143system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency 1144system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency 1145system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency 1146system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency 1147system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency 1148system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency |
| 1124system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1125system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements | 1149system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1150system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements |
| 1126system.cpu.dtb_walker_cache.tags.tagsinuse 14.904441 # Cycle average of tags in use 1127system.cpu.dtb_walker_cache.tags.total_refs 92410 # Total number of references to valid blocks. | 1151system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use 1152system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks. |
| 1128system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. | 1153system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. |
| 1129system.cpu.dtb_walker_cache.tags.avg_refs 1.337976 # Average number of references to valid blocks. 1130system.cpu.dtb_walker_cache.tags.warmup_cycle 4994136871250 # Cycle when the warmup percentage was hit. 1131system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.904441 # Average occupied blocks per requestor 1132system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.931528 # Average percentage of cache occupancy 1133system.cpu.dtb_walker_cache.tags.occ_percent::total 0.931528 # Average percentage of cache occupancy 1134system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92410 # number of ReadReq hits 1135system.cpu.dtb_walker_cache.ReadReq_hits::total 92410 # number of ReadReq hits 1136system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92410 # number of demand (read+write) hits 1137system.cpu.dtb_walker_cache.demand_hits::total 92410 # number of demand (read+write) hits 1138system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92410 # number of overall hits 1139system.cpu.dtb_walker_cache.overall_hits::total 92410 # number of overall hits 1140system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70084 # number of ReadReq misses 1141system.cpu.dtb_walker_cache.ReadReq_misses::total 70084 # number of ReadReq misses 1142system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70084 # number of demand (read+write) misses 1143system.cpu.dtb_walker_cache.demand_misses::total 70084 # number of demand (read+write) misses 1144system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70084 # number of overall misses 1145system.cpu.dtb_walker_cache.overall_misses::total 70084 # number of overall misses 1146system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 863900211 # number of ReadReq miss cycles 1147system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 863900211 # number of ReadReq miss cycles 1148system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 863900211 # number of demand (read+write) miss cycles 1149system.cpu.dtb_walker_cache.demand_miss_latency::total 863900211 # number of demand (read+write) miss cycles 1150system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 863900211 # number of overall miss cycles 1151system.cpu.dtb_walker_cache.overall_miss_latency::total 863900211 # number of overall miss cycles 1152system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162494 # number of ReadReq accesses(hits+misses) 1153system.cpu.dtb_walker_cache.ReadReq_accesses::total 162494 # number of ReadReq accesses(hits+misses) 1154system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162494 # number of demand (read+write) accesses 1155system.cpu.dtb_walker_cache.demand_accesses::total 162494 # number of demand (read+write) accesses 1156system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162494 # number of overall (read+write) accesses 1157system.cpu.dtb_walker_cache.overall_accesses::total 162494 # number of overall (read+write) accesses 1158system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.431302 # miss rate for ReadReq accesses 1159system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.431302 # miss rate for ReadReq accesses 1160system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.431302 # miss rate for demand accesses 1161system.cpu.dtb_walker_cache.demand_miss_rate::total 0.431302 # miss rate for demand accesses 1162system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.431302 # miss rate for overall accesses 1163system.cpu.dtb_walker_cache.overall_miss_rate::total 0.431302 # miss rate for overall accesses 1164system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12326.639618 # average ReadReq miss latency 1165system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12326.639618 # average ReadReq miss latency 1166system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency 1167system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12326.639618 # average overall miss latency 1168system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency 1169system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12326.639618 # average overall miss latency | 1154system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks. 1155system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit. 1156system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor 1157system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy 1158system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy 1159system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits 1160system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits 1161system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits 1162system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits 1163system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits 1164system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits 1165system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses 1166system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses 1167system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses 1168system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses 1169system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses 1170system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses 1171system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles 1172system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles 1173system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles 1174system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles 1175system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles 1176system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles 1177system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses) 1178system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses) 1179system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses 1180system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses 1181system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses 1182system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses 1183system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses 1184system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses 1185system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses 1186system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses 1187system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses 1188system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses 1189system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency 1190system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency 1191system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency 1192system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency 1193system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency 1194system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency |
| 1170system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1171system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1172system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1173system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1174system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1175system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1176system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1177system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 1195system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1196system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1197system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1198system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1199system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1200system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1201system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1202system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1178system.cpu.dtb_walker_cache.writebacks::writebacks 17433 # number of writebacks 1179system.cpu.dtb_walker_cache.writebacks::total 17433 # number of writebacks 1180system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70084 # number of ReadReq MSHR misses 1181system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70084 # number of ReadReq MSHR misses 1182system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70084 # number of demand (read+write) MSHR misses 1183system.cpu.dtb_walker_cache.demand_mshr_misses::total 70084 # number of demand (read+write) MSHR misses 1184system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70084 # number of overall MSHR misses 1185system.cpu.dtb_walker_cache.overall_mshr_misses::total 70084 # number of overall MSHR misses 1186system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 723600921 # number of ReadReq MSHR miss cycles 1187system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 723600921 # number of ReadReq MSHR miss cycles 1188system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 723600921 # number of demand (read+write) MSHR miss cycles 1189system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 723600921 # number of demand (read+write) MSHR miss cycles 1190system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 723600921 # number of overall MSHR miss cycles 1191system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 723600921 # number of overall MSHR miss cycles 1192system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for ReadReq accesses 1193system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.431302 # mshr miss rate for ReadReq accesses 1194system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for demand accesses 1195system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.431302 # mshr miss rate for demand accesses 1196system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for overall accesses 1197system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.431302 # mshr miss rate for overall accesses 1198system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average ReadReq mshr miss latency 1199system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10324.766295 # average ReadReq mshr miss latency 1200system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency 1201system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency 1202system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency 1203system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency | 1203system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks 1204system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks 1205system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses 1206system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses 1207system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses 1208system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses 1209system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses 1210system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses 1211system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles 1212system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles 1213system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles 1214system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles 1215system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles 1216system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles 1217system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses 1218system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses 1219system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses 1220system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses 1221system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses 1222system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses 1223system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency 1224system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency 1225system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency 1226system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency 1227system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency 1228system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency |
| 1204system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1229system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1205system.cpu.dcache.tags.replacements 1656223 # number of replacements 1206system.cpu.dcache.tags.tagsinuse 511.995363 # Cycle average of tags in use 1207system.cpu.dcache.tags.total_refs 18981681 # Total number of references to valid blocks. 1208system.cpu.dcache.tags.sampled_refs 1656735 # Sample count of references to valid blocks. 1209system.cpu.dcache.tags.avg_refs 11.457283 # Average number of references to valid blocks. 1210system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. 1211system.cpu.dcache.tags.occ_blocks::cpu.data 511.995363 # Average occupied blocks per requestor 1212system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 1213system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy 1214system.cpu.dcache.ReadReq_hits::cpu.data 10886449 # number of ReadReq hits 1215system.cpu.dcache.ReadReq_hits::total 10886449 # number of ReadReq hits 1216system.cpu.dcache.WriteReq_hits::cpu.data 8092566 # number of WriteReq hits 1217system.cpu.dcache.WriteReq_hits::total 8092566 # number of WriteReq hits 1218system.cpu.dcache.demand_hits::cpu.data 18979015 # number of demand (read+write) hits 1219system.cpu.dcache.demand_hits::total 18979015 # number of demand (read+write) hits 1220system.cpu.dcache.overall_hits::cpu.data 18979015 # number of overall hits 1221system.cpu.dcache.overall_hits::total 18979015 # number of overall hits 1222system.cpu.dcache.ReadReq_misses::cpu.data 2233485 # number of ReadReq misses 1223system.cpu.dcache.ReadReq_misses::total 2233485 # number of ReadReq misses 1224system.cpu.dcache.WriteReq_misses::cpu.data 315362 # number of WriteReq misses 1225system.cpu.dcache.WriteReq_misses::total 315362 # number of WriteReq misses 1226system.cpu.dcache.demand_misses::cpu.data 2548847 # number of demand (read+write) misses 1227system.cpu.dcache.demand_misses::total 2548847 # number of demand (read+write) misses 1228system.cpu.dcache.overall_misses::cpu.data 2548847 # number of overall misses 1229system.cpu.dcache.overall_misses::total 2548847 # number of overall misses 1230system.cpu.dcache.ReadReq_miss_latency::cpu.data 33146878091 # number of ReadReq miss cycles 1231system.cpu.dcache.ReadReq_miss_latency::total 33146878091 # number of ReadReq miss cycles 1232system.cpu.dcache.WriteReq_miss_latency::cpu.data 12110851955 # number of WriteReq miss cycles 1233system.cpu.dcache.WriteReq_miss_latency::total 12110851955 # number of WriteReq miss cycles 1234system.cpu.dcache.demand_miss_latency::cpu.data 45257730046 # number of demand (read+write) miss cycles 1235system.cpu.dcache.demand_miss_latency::total 45257730046 # number of demand (read+write) miss cycles 1236system.cpu.dcache.overall_miss_latency::cpu.data 45257730046 # number of overall miss cycles 1237system.cpu.dcache.overall_miss_latency::total 45257730046 # number of overall miss cycles 1238system.cpu.dcache.ReadReq_accesses::cpu.data 13119934 # number of ReadReq accesses(hits+misses) 1239system.cpu.dcache.ReadReq_accesses::total 13119934 # number of ReadReq accesses(hits+misses) 1240system.cpu.dcache.WriteReq_accesses::cpu.data 8407928 # number of WriteReq accesses(hits+misses) 1241system.cpu.dcache.WriteReq_accesses::total 8407928 # number of WriteReq accesses(hits+misses) 1242system.cpu.dcache.demand_accesses::cpu.data 21527862 # number of demand (read+write) accesses 1243system.cpu.dcache.demand_accesses::total 21527862 # number of demand (read+write) accesses 1244system.cpu.dcache.overall_accesses::cpu.data 21527862 # number of overall (read+write) accesses 1245system.cpu.dcache.overall_accesses::total 21527862 # number of overall (read+write) accesses 1246system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170236 # miss rate for ReadReq accesses 1247system.cpu.dcache.ReadReq_miss_rate::total 0.170236 # miss rate for ReadReq accesses 1248system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037508 # miss rate for WriteReq accesses 1249system.cpu.dcache.WriteReq_miss_rate::total 0.037508 # miss rate for WriteReq accesses 1250system.cpu.dcache.demand_miss_rate::cpu.data 0.118398 # miss rate for demand accesses 1251system.cpu.dcache.demand_miss_rate::total 0.118398 # miss rate for demand accesses 1252system.cpu.dcache.overall_miss_rate::cpu.data 0.118398 # miss rate for overall accesses 1253system.cpu.dcache.overall_miss_rate::total 0.118398 # miss rate for overall accesses 1254system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14840.877862 # average ReadReq miss latency 1255system.cpu.dcache.ReadReq_avg_miss_latency::total 14840.877862 # average ReadReq miss latency 1256system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38403.016074 # average WriteReq miss latency 1257system.cpu.dcache.WriteReq_avg_miss_latency::total 38403.016074 # average WriteReq miss latency 1258system.cpu.dcache.demand_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency 1259system.cpu.dcache.demand_avg_miss_latency::total 17756.157998 # average overall miss latency 1260system.cpu.dcache.overall_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency 1261system.cpu.dcache.overall_avg_miss_latency::total 17756.157998 # average overall miss latency 1262system.cpu.dcache.blocked_cycles::no_mshrs 397029 # number of cycles access was blocked | 1230system.cpu.dcache.tags.replacements 1657437 # number of replacements 1231system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use 1232system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks. 1233system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks. 1234system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks. 1235system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. 1236system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor 1237system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy 1238system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy 1239system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits 1240system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits 1241system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits 1242system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits 1243system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits 1244system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits 1245system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits 1246system.cpu.dcache.overall_hits::total 18986697 # number of overall hits 1247system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses 1248system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses 1249system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses 1250system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses 1251system.cpu.dcache.demand_misses::cpu.data 2550677 # number of demand (read+write) misses 1252system.cpu.dcache.demand_misses::total 2550677 # number of demand (read+write) misses 1253system.cpu.dcache.overall_misses::cpu.data 2550677 # number of overall misses 1254system.cpu.dcache.overall_misses::total 2550677 # number of overall misses 1255system.cpu.dcache.ReadReq_miss_latency::cpu.data 33004921637 # number of ReadReq miss cycles 1256system.cpu.dcache.ReadReq_miss_latency::total 33004921637 # number of ReadReq miss cycles 1257system.cpu.dcache.WriteReq_miss_latency::cpu.data 12257889032 # number of WriteReq miss cycles 1258system.cpu.dcache.WriteReq_miss_latency::total 12257889032 # number of WriteReq miss cycles 1259system.cpu.dcache.demand_miss_latency::cpu.data 45262810669 # number of demand (read+write) miss cycles 1260system.cpu.dcache.demand_miss_latency::total 45262810669 # number of demand (read+write) miss cycles 1261system.cpu.dcache.overall_miss_latency::cpu.data 45262810669 # number of overall miss cycles 1262system.cpu.dcache.overall_miss_latency::total 45262810669 # number of overall miss cycles 1263system.cpu.dcache.ReadReq_accesses::cpu.data 13125399 # number of ReadReq accesses(hits+misses) 1264system.cpu.dcache.ReadReq_accesses::total 13125399 # number of ReadReq accesses(hits+misses) 1265system.cpu.dcache.WriteReq_accesses::cpu.data 8411975 # number of WriteReq accesses(hits+misses) 1266system.cpu.dcache.WriteReq_accesses::total 8411975 # number of WriteReq accesses(hits+misses) 1267system.cpu.dcache.demand_accesses::cpu.data 21537374 # number of demand (read+write) accesses 1268system.cpu.dcache.demand_accesses::total 21537374 # number of demand (read+write) accesses 1269system.cpu.dcache.overall_accesses::cpu.data 21537374 # number of overall (read+write) accesses 1270system.cpu.dcache.overall_accesses::total 21537374 # number of overall (read+write) accesses 1271system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170241 # miss rate for ReadReq accesses 1272system.cpu.dcache.ReadReq_miss_rate::total 0.170241 # miss rate for ReadReq accesses 1273system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses 1274system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses 1275system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses 1276system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses 1277system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses 1278system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses 1279system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency 1280system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency 1281system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency 1282system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency 1283system.cpu.dcache.demand_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency 1284system.cpu.dcache.demand_avg_miss_latency::total 17745.410598 # average overall miss latency 1285system.cpu.dcache.overall_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency 1286system.cpu.dcache.overall_avg_miss_latency::total 17745.410598 # average overall miss latency 1287system.cpu.dcache.blocked_cycles::no_mshrs 397669 # number of cycles access was blocked |
| 1263system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1288system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1264system.cpu.dcache.blocked::no_mshrs 42211 # number of cycles access was blocked | 1289system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked |
| 1265system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1290system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1266system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.405818 # average number of cycles each access was blocked | 1291system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked |
| 1267system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1268system.cpu.dcache.fast_writes 0 # number of fast writes performed 1269system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1292system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1293system.cpu.dcache.fast_writes 0 # number of fast writes performed 1294system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1270system.cpu.dcache.writebacks::writebacks 1558075 # number of writebacks 1271system.cpu.dcache.writebacks::total 1558075 # number of writebacks 1272system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863964 # number of ReadReq MSHR hits 1273system.cpu.dcache.ReadReq_mshr_hits::total 863964 # number of ReadReq MSHR hits 1274system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25903 # number of WriteReq MSHR hits 1275system.cpu.dcache.WriteReq_mshr_hits::total 25903 # number of WriteReq MSHR hits 1276system.cpu.dcache.demand_mshr_hits::cpu.data 889867 # number of demand (read+write) MSHR hits 1277system.cpu.dcache.demand_mshr_hits::total 889867 # number of demand (read+write) MSHR hits 1278system.cpu.dcache.overall_mshr_hits::cpu.data 889867 # number of overall MSHR hits 1279system.cpu.dcache.overall_mshr_hits::total 889867 # number of overall MSHR hits 1280system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369521 # number of ReadReq MSHR misses 1281system.cpu.dcache.ReadReq_mshr_misses::total 1369521 # number of ReadReq MSHR misses 1282system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289459 # number of WriteReq MSHR misses 1283system.cpu.dcache.WriteReq_mshr_misses::total 289459 # number of WriteReq MSHR misses 1284system.cpu.dcache.demand_mshr_misses::cpu.data 1658980 # number of demand (read+write) MSHR misses 1285system.cpu.dcache.demand_mshr_misses::total 1658980 # number of demand (read+write) MSHR misses 1286system.cpu.dcache.overall_mshr_misses::cpu.data 1658980 # number of overall MSHR misses 1287system.cpu.dcache.overall_mshr_misses::total 1658980 # number of overall MSHR misses 1288system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17890697467 # number of ReadReq MSHR miss cycles 1289system.cpu.dcache.ReadReq_mshr_miss_latency::total 17890697467 # number of ReadReq MSHR miss cycles 1290system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11213904776 # number of WriteReq MSHR miss cycles 1291system.cpu.dcache.WriteReq_mshr_miss_latency::total 11213904776 # number of WriteReq MSHR miss cycles 1292system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29104602243 # number of demand (read+write) MSHR miss cycles 1293system.cpu.dcache.demand_mshr_miss_latency::total 29104602243 # number of demand (read+write) MSHR miss cycles 1294system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29104602243 # number of overall MSHR miss cycles 1295system.cpu.dcache.overall_mshr_miss_latency::total 29104602243 # number of overall MSHR miss cycles 1296system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363389500 # number of ReadReq MSHR uncacheable cycles 1297system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363389500 # number of ReadReq MSHR uncacheable cycles 1298system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537212500 # number of WriteReq MSHR uncacheable cycles 1299system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537212500 # number of WriteReq MSHR uncacheable cycles 1300system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99900602000 # number of overall MSHR uncacheable cycles 1301system.cpu.dcache.overall_mshr_uncacheable_latency::total 99900602000 # number of overall MSHR uncacheable cycles 1302system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104385 # mshr miss rate for ReadReq accesses 1303system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104385 # mshr miss rate for ReadReq accesses 1304system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034427 # mshr miss rate for WriteReq accesses 1305system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034427 # mshr miss rate for WriteReq accesses 1306system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077062 # mshr miss rate for demand accesses 1307system.cpu.dcache.demand_mshr_miss_rate::total 0.077062 # mshr miss rate for demand accesses 1308system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077062 # mshr miss rate for overall accesses 1309system.cpu.dcache.overall_mshr_miss_rate::total 0.077062 # mshr miss rate for overall accesses 1310system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13063.470708 # average ReadReq mshr miss latency 1311system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13063.470708 # average ReadReq mshr miss latency 1312system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38740.908992 # average WriteReq mshr miss latency 1313system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38740.908992 # average WriteReq mshr miss latency 1314system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17543.672765 # average overall mshr miss latency 1315system.cpu.dcache.demand_avg_mshr_miss_latency::total 17543.672765 # average overall mshr miss latency 1316system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17543.672765 # average overall mshr miss latency 1317system.cpu.dcache.overall_avg_mshr_miss_latency::total 17543.672765 # average overall mshr miss latency | 1295system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks 1296system.cpu.dcache.writebacks::total 1558744 # number of writebacks 1297system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits 1298system.cpu.dcache.ReadReq_mshr_hits::total 864490 # number of ReadReq MSHR hits 1299system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25919 # number of WriteReq MSHR hits 1300system.cpu.dcache.WriteReq_mshr_hits::total 25919 # number of WriteReq MSHR hits 1301system.cpu.dcache.demand_mshr_hits::cpu.data 890409 # number of demand (read+write) MSHR hits 1302system.cpu.dcache.demand_mshr_hits::total 890409 # number of demand (read+write) MSHR hits 1303system.cpu.dcache.overall_mshr_hits::cpu.data 890409 # number of overall MSHR hits 1304system.cpu.dcache.overall_mshr_hits::total 890409 # number of overall MSHR hits 1305system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369989 # number of ReadReq MSHR misses 1306system.cpu.dcache.ReadReq_mshr_misses::total 1369989 # number of ReadReq MSHR misses 1307system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290279 # number of WriteReq MSHR misses 1308system.cpu.dcache.WriteReq_mshr_misses::total 290279 # number of WriteReq MSHR misses 1309system.cpu.dcache.demand_mshr_misses::cpu.data 1660268 # number of demand (read+write) MSHR misses 1310system.cpu.dcache.demand_mshr_misses::total 1660268 # number of demand (read+write) MSHR misses 1311system.cpu.dcache.overall_mshr_misses::cpu.data 1660268 # number of overall MSHR misses 1312system.cpu.dcache.overall_mshr_misses::total 1660268 # number of overall MSHR misses 1313system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17836083706 # number of ReadReq MSHR miss cycles 1314system.cpu.dcache.ReadReq_mshr_miss_latency::total 17836083706 # number of ReadReq MSHR miss cycles 1315system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11362753211 # number of WriteReq MSHR miss cycles 1316system.cpu.dcache.WriteReq_mshr_miss_latency::total 11362753211 # number of WriteReq MSHR miss cycles 1317system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29198836917 # number of demand (read+write) MSHR miss cycles 1318system.cpu.dcache.demand_mshr_miss_latency::total 29198836917 # number of demand (read+write) MSHR miss cycles 1319system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29198836917 # number of overall MSHR miss cycles 1320system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles 1321system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles 1322system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles 1323system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles 1324system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles 1325system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles 1326system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles 1327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses 1328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses 1329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034508 # mshr miss rate for WriteReq accesses 1330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034508 # mshr miss rate for WriteReq accesses 1331system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses 1332system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses 1333system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses 1334system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses 1335system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13019.143735 # average ReadReq mshr miss latency 1336system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13019.143735 # average ReadReq mshr miss latency 1337system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39144.248158 # average WriteReq mshr miss latency 1338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39144.248158 # average WriteReq mshr miss latency 1339system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency 1340system.cpu.dcache.demand_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency 1341system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency 1342system.cpu.dcache.overall_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency |
| 1318system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1319system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1320system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1321system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1322system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1323system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1324system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1343system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1344system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1345system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1346system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1347system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1348system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1325system.cpu.l2cache.tags.replacements 111030 # number of replacements 1326system.cpu.l2cache.tags.tagsinuse 64826.472459 # Cycle average of tags in use 1327system.cpu.l2cache.tags.total_refs 3778684 # Total number of references to valid blocks. 1328system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. 1329system.cpu.l2cache.tags.avg_refs 21.568570 # Average number of references to valid blocks. | 1350system.cpu.l2cache.tags.replacements 111632 # number of replacements 1351system.cpu.l2cache.tags.tagsinuse 64821.705622 # Cycle average of tags in use 1352system.cpu.l2cache.tags.total_refs 3786761 # Total number of references to valid blocks. 1353system.cpu.l2cache.tags.sampled_refs 175570 # Sample count of references to valid blocks. 1354system.cpu.l2cache.tags.avg_refs 21.568383 # Average number of references to valid blocks. |
| 1330system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1355system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1331system.cpu.l2cache.tags.occ_blocks::writebacks 50681.739726 # Average occupied blocks per requestor 1332system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.389473 # Average occupied blocks per requestor 1333system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126360 # Average occupied blocks per requestor 1334system.cpu.l2cache.tags.occ_blocks::cpu.inst 3154.839076 # Average occupied blocks per requestor 1335system.cpu.l2cache.tags.occ_blocks::cpu.data 10976.377823 # Average occupied blocks per requestor 1336system.cpu.l2cache.tags.occ_percent::writebacks 0.773342 # Average percentage of cache occupancy 1337system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000204 # Average percentage of cache occupancy | 1356system.cpu.l2cache.tags.occ_blocks::writebacks 50709.515998 # Average occupied blocks per requestor 1357system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.756367 # Average occupied blocks per requestor 1358system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126012 # Average occupied blocks per requestor 1359system.cpu.l2cache.tags.occ_blocks::cpu.inst 3028.517183 # Average occupied blocks per requestor 1360system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.790063 # Average occupied blocks per requestor 1361system.cpu.l2cache.tags.occ_percent::writebacks 0.773766 # Average percentage of cache occupancy 1362system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000118 # Average percentage of cache occupancy |
| 1338system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 1363system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 1339system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048139 # Average percentage of cache occupancy 1340system.cpu.l2cache.tags.occ_percent::cpu.data 0.167486 # Average percentage of cache occupancy 1341system.cpu.l2cache.tags.occ_percent::total 0.989173 # Average percentage of cache occupancy 1342system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64025 # number of ReadReq hits 1343system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7316 # number of ReadReq hits 1344system.cpu.l2cache.ReadReq_hits::cpu.inst 937955 # number of ReadReq hits 1345system.cpu.l2cache.ReadReq_hits::cpu.data 1333061 # number of ReadReq hits 1346system.cpu.l2cache.ReadReq_hits::total 2342357 # number of ReadReq hits 1347system.cpu.l2cache.Writeback_hits::writebacks 1577044 # number of Writeback hits 1348system.cpu.l2cache.Writeback_hits::total 1577044 # number of Writeback hits 1349system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits 1350system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits 1351system.cpu.l2cache.ReadExReq_hits::cpu.data 154757 # number of ReadExReq hits 1352system.cpu.l2cache.ReadExReq_hits::total 154757 # number of ReadExReq hits 1353system.cpu.l2cache.demand_hits::cpu.dtb.walker 64025 # number of demand (read+write) hits 1354system.cpu.l2cache.demand_hits::cpu.itb.walker 7316 # number of demand (read+write) hits 1355system.cpu.l2cache.demand_hits::cpu.inst 937955 # number of demand (read+write) hits 1356system.cpu.l2cache.demand_hits::cpu.data 1487818 # number of demand (read+write) hits 1357system.cpu.l2cache.demand_hits::total 2497114 # number of demand (read+write) hits 1358system.cpu.l2cache.overall_hits::cpu.dtb.walker 64025 # number of overall hits 1359system.cpu.l2cache.overall_hits::cpu.itb.walker 7316 # number of overall hits 1360system.cpu.l2cache.overall_hits::cpu.inst 937955 # number of overall hits 1361system.cpu.l2cache.overall_hits::cpu.data 1487818 # number of overall hits 1362system.cpu.l2cache.overall_hits::total 2497114 # number of overall hits | 1364system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046212 # Average percentage of cache occupancy 1365system.cpu.l2cache.tags.occ_percent::cpu.data 0.169003 # Average percentage of cache occupancy 1366system.cpu.l2cache.tags.occ_percent::total 0.989101 # Average percentage of cache occupancy 1367system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits 1368system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7222 # number of ReadReq hits 1369system.cpu.l2cache.ReadReq_hits::cpu.inst 943511 # number of ReadReq hits 1370system.cpu.l2cache.ReadReq_hits::cpu.data 1333169 # number of ReadReq hits 1371system.cpu.l2cache.ReadReq_hits::total 2348748 # number of ReadReq hits 1372system.cpu.l2cache.Writeback_hits::writebacks 1585586 # number of Writeback hits 1373system.cpu.l2cache.Writeback_hits::total 1585586 # number of Writeback hits 1374system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits 1375system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits 1376system.cpu.l2cache.ReadExReq_hits::cpu.data 155047 # number of ReadExReq hits 1377system.cpu.l2cache.ReadExReq_hits::total 155047 # number of ReadExReq hits 1378system.cpu.l2cache.demand_hits::cpu.dtb.walker 64846 # number of demand (read+write) hits 1379system.cpu.l2cache.demand_hits::cpu.itb.walker 7222 # number of demand (read+write) hits 1380system.cpu.l2cache.demand_hits::cpu.inst 943511 # number of demand (read+write) hits 1381system.cpu.l2cache.demand_hits::cpu.data 1488216 # number of demand (read+write) hits 1382system.cpu.l2cache.demand_hits::total 2503795 # number of demand (read+write) hits 1383system.cpu.l2cache.overall_hits::cpu.dtb.walker 64846 # number of overall hits 1384system.cpu.l2cache.overall_hits::cpu.itb.walker 7222 # number of overall hits 1385system.cpu.l2cache.overall_hits::cpu.inst 943511 # number of overall hits 1386system.cpu.l2cache.overall_hits::cpu.data 1488216 # number of overall hits 1387system.cpu.l2cache.overall_hits::total 2503795 # number of overall hits |
| 1363system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses 1364system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 1388system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses 1389system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 1365system.cpu.l2cache.ReadReq_misses::cpu.inst 16091 # number of ReadReq misses 1366system.cpu.l2cache.ReadReq_misses::cpu.data 35754 # number of ReadReq misses 1367system.cpu.l2cache.ReadReq_misses::total 51911 # number of ReadReq misses 1368system.cpu.l2cache.UpgradeReq_misses::cpu.data 1443 # number of UpgradeReq misses 1369system.cpu.l2cache.UpgradeReq_misses::total 1443 # number of UpgradeReq misses 1370system.cpu.l2cache.ReadExReq_misses::cpu.data 132547 # number of ReadExReq misses 1371system.cpu.l2cache.ReadExReq_misses::total 132547 # number of ReadExReq misses | 1390system.cpu.l2cache.ReadReq_misses::cpu.inst 16089 # number of ReadReq misses 1391system.cpu.l2cache.ReadReq_misses::cpu.data 36006 # number of ReadReq misses 1392system.cpu.l2cache.ReadReq_misses::total 52161 # number of ReadReq misses 1393system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses 1394system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses 1395system.cpu.l2cache.ReadExReq_misses::cpu.data 133062 # number of ReadExReq misses 1396system.cpu.l2cache.ReadExReq_misses::total 133062 # number of ReadExReq misses |
| 1372system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses 1373system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 1397system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses 1398system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 1374system.cpu.l2cache.demand_misses::cpu.inst 16091 # number of demand (read+write) misses 1375system.cpu.l2cache.demand_misses::cpu.data 168301 # number of demand (read+write) misses 1376system.cpu.l2cache.demand_misses::total 184458 # number of demand (read+write) misses | 1399system.cpu.l2cache.demand_misses::cpu.inst 16089 # number of demand (read+write) misses 1400system.cpu.l2cache.demand_misses::cpu.data 169068 # number of demand (read+write) misses 1401system.cpu.l2cache.demand_misses::total 185223 # number of demand (read+write) misses |
| 1377system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses 1378system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 1402system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses 1403system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 1379system.cpu.l2cache.overall_misses::cpu.inst 16091 # number of overall misses 1380system.cpu.l2cache.overall_misses::cpu.data 168301 # number of overall misses 1381system.cpu.l2cache.overall_misses::total 184458 # number of overall misses 1382system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5633750 # number of ReadReq miss cycles 1383system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 417750 # number of ReadReq miss cycles 1384system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1393223986 # number of ReadReq miss cycles 1385system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2996305709 # number of ReadReq miss cycles 1386system.cpu.l2cache.ReadReq_miss_latency::total 4395581195 # number of ReadReq miss cycles 1387system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16716837 # number of UpgradeReq miss cycles 1388system.cpu.l2cache.UpgradeReq_miss_latency::total 16716837 # number of UpgradeReq miss cycles 1389system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9332768700 # number of ReadExReq miss cycles 1390system.cpu.l2cache.ReadExReq_miss_latency::total 9332768700 # number of ReadExReq miss cycles 1391system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5633750 # number of demand (read+write) miss cycles 1392system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 417750 # number of demand (read+write) miss cycles 1393system.cpu.l2cache.demand_miss_latency::cpu.inst 1393223986 # number of demand (read+write) miss cycles 1394system.cpu.l2cache.demand_miss_latency::cpu.data 12329074409 # number of demand (read+write) miss cycles 1395system.cpu.l2cache.demand_miss_latency::total 13728349895 # number of demand (read+write) miss cycles 1396system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5633750 # number of overall miss cycles 1397system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 417750 # number of overall miss cycles 1398system.cpu.l2cache.overall_miss_latency::cpu.inst 1393223986 # number of overall miss cycles 1399system.cpu.l2cache.overall_miss_latency::cpu.data 12329074409 # number of overall miss cycles 1400system.cpu.l2cache.overall_miss_latency::total 13728349895 # number of overall miss cycles 1401system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64086 # number of ReadReq accesses(hits+misses) 1402system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7321 # number of ReadReq accesses(hits+misses) 1403system.cpu.l2cache.ReadReq_accesses::cpu.inst 954046 # number of ReadReq accesses(hits+misses) 1404system.cpu.l2cache.ReadReq_accesses::cpu.data 1368815 # number of ReadReq accesses(hits+misses) 1405system.cpu.l2cache.ReadReq_accesses::total 2394268 # number of ReadReq accesses(hits+misses) 1406system.cpu.l2cache.Writeback_accesses::writebacks 1577044 # number of Writeback accesses(hits+misses) 1407system.cpu.l2cache.Writeback_accesses::total 1577044 # number of Writeback accesses(hits+misses) 1408system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1759 # number of UpgradeReq accesses(hits+misses) 1409system.cpu.l2cache.UpgradeReq_accesses::total 1759 # number of UpgradeReq accesses(hits+misses) 1410system.cpu.l2cache.ReadExReq_accesses::cpu.data 287304 # number of ReadExReq accesses(hits+misses) 1411system.cpu.l2cache.ReadExReq_accesses::total 287304 # number of ReadExReq accesses(hits+misses) 1412system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64086 # number of demand (read+write) accesses 1413system.cpu.l2cache.demand_accesses::cpu.itb.walker 7321 # number of demand (read+write) accesses 1414system.cpu.l2cache.demand_accesses::cpu.inst 954046 # number of demand (read+write) accesses 1415system.cpu.l2cache.demand_accesses::cpu.data 1656119 # number of demand (read+write) accesses 1416system.cpu.l2cache.demand_accesses::total 2681572 # number of demand (read+write) accesses 1417system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64086 # number of overall (read+write) accesses 1418system.cpu.l2cache.overall_accesses::cpu.itb.walker 7321 # number of overall (read+write) accesses 1419system.cpu.l2cache.overall_accesses::cpu.inst 954046 # number of overall (read+write) accesses 1420system.cpu.l2cache.overall_accesses::cpu.data 1656119 # number of overall (read+write) accesses 1421system.cpu.l2cache.overall_accesses::total 2681572 # number of overall (read+write) accesses 1422system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000952 # miss rate for ReadReq accesses 1423system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000683 # miss rate for ReadReq accesses 1424system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016866 # miss rate for ReadReq accesses 1425system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026120 # miss rate for ReadReq accesses 1426system.cpu.l2cache.ReadReq_miss_rate::total 0.021681 # miss rate for ReadReq accesses 1427system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820352 # miss rate for UpgradeReq accesses 1428system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820352 # miss rate for UpgradeReq accesses 1429system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461348 # miss rate for ReadExReq accesses 1430system.cpu.l2cache.ReadExReq_miss_rate::total 0.461348 # miss rate for ReadExReq accesses 1431system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000952 # miss rate for demand accesses 1432system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000683 # miss rate for demand accesses 1433system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016866 # miss rate for demand accesses 1434system.cpu.l2cache.demand_miss_rate::cpu.data 0.101624 # miss rate for demand accesses 1435system.cpu.l2cache.demand_miss_rate::total 0.068787 # miss rate for demand accesses 1436system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000952 # miss rate for overall accesses 1437system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000683 # miss rate for overall accesses 1438system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016866 # miss rate for overall accesses 1439system.cpu.l2cache.overall_miss_rate::cpu.data 0.101624 # miss rate for overall accesses 1440system.cpu.l2cache.overall_miss_rate::total 0.068787 # miss rate for overall accesses 1441system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92356.557377 # average ReadReq miss latency 1442system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83550 # average ReadReq miss latency 1443system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86584.052327 # average ReadReq miss latency 1444system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83803.370504 # average ReadReq miss latency 1445system.cpu.l2cache.ReadReq_avg_miss_latency::total 84675.332685 # average ReadReq miss latency 1446system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11584.779626 # average UpgradeReq miss latency 1447system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11584.779626 # average UpgradeReq miss latency 1448system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70411.014206 # average ReadExReq miss latency 1449system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70411.014206 # average ReadExReq miss latency 1450system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92356.557377 # average overall miss latency 1451system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency 1452system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86584.052327 # average overall miss latency 1453system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73256.097165 # average overall miss latency 1454system.cpu.l2cache.demand_avg_miss_latency::total 74425.342869 # average overall miss latency 1455system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92356.557377 # average overall miss latency 1456system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency 1457system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86584.052327 # average overall miss latency 1458system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73256.097165 # average overall miss latency 1459system.cpu.l2cache.overall_avg_miss_latency::total 74425.342869 # average overall miss latency | 1404system.cpu.l2cache.overall_misses::cpu.inst 16089 # number of overall misses 1405system.cpu.l2cache.overall_misses::cpu.data 169068 # number of overall misses 1406system.cpu.l2cache.overall_misses::total 185223 # number of overall misses 1407system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5260500 # number of ReadReq miss cycles 1408system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389750 # number of ReadReq miss cycles 1409system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1277797734 # number of ReadReq miss cycles 1410system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940044940 # number of ReadReq miss cycles 1411system.cpu.l2cache.ReadReq_miss_latency::total 4223492924 # number of ReadReq miss cycles 1412system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17900790 # number of UpgradeReq miss cycles 1413system.cpu.l2cache.UpgradeReq_miss_latency::total 17900790 # number of UpgradeReq miss cycles 1414system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9477459899 # number of ReadExReq miss cycles 1415system.cpu.l2cache.ReadExReq_miss_latency::total 9477459899 # number of ReadExReq miss cycles 1416system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5260500 # number of demand (read+write) miss cycles 1417system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389750 # number of demand (read+write) miss cycles 1418system.cpu.l2cache.demand_miss_latency::cpu.inst 1277797734 # number of demand (read+write) miss cycles 1419system.cpu.l2cache.demand_miss_latency::cpu.data 12417504839 # number of demand (read+write) miss cycles 1420system.cpu.l2cache.demand_miss_latency::total 13700952823 # number of demand (read+write) miss cycles 1421system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5260500 # number of overall miss cycles 1422system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389750 # number of overall miss cycles 1423system.cpu.l2cache.overall_miss_latency::cpu.inst 1277797734 # number of overall miss cycles 1424system.cpu.l2cache.overall_miss_latency::cpu.data 12417504839 # number of overall miss cycles 1425system.cpu.l2cache.overall_miss_latency::total 13700952823 # number of overall miss cycles 1426system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64907 # number of ReadReq accesses(hits+misses) 1427system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7227 # number of ReadReq accesses(hits+misses) 1428system.cpu.l2cache.ReadReq_accesses::cpu.inst 959600 # number of ReadReq accesses(hits+misses) 1429system.cpu.l2cache.ReadReq_accesses::cpu.data 1369175 # number of ReadReq accesses(hits+misses) 1430system.cpu.l2cache.ReadReq_accesses::total 2400909 # number of ReadReq accesses(hits+misses) 1431system.cpu.l2cache.Writeback_accesses::writebacks 1585586 # number of Writeback accesses(hits+misses) 1432system.cpu.l2cache.Writeback_accesses::total 1585586 # number of Writeback accesses(hits+misses) 1433system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1776 # number of UpgradeReq accesses(hits+misses) 1434system.cpu.l2cache.UpgradeReq_accesses::total 1776 # number of UpgradeReq accesses(hits+misses) 1435system.cpu.l2cache.ReadExReq_accesses::cpu.data 288109 # number of ReadExReq accesses(hits+misses) 1436system.cpu.l2cache.ReadExReq_accesses::total 288109 # number of ReadExReq accesses(hits+misses) 1437system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64907 # number of demand (read+write) accesses 1438system.cpu.l2cache.demand_accesses::cpu.itb.walker 7227 # number of demand (read+write) accesses 1439system.cpu.l2cache.demand_accesses::cpu.inst 959600 # number of demand (read+write) accesses 1440system.cpu.l2cache.demand_accesses::cpu.data 1657284 # number of demand (read+write) accesses 1441system.cpu.l2cache.demand_accesses::total 2689018 # number of demand (read+write) accesses 1442system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64907 # number of overall (read+write) accesses 1443system.cpu.l2cache.overall_accesses::cpu.itb.walker 7227 # number of overall (read+write) accesses 1444system.cpu.l2cache.overall_accesses::cpu.inst 959600 # number of overall (read+write) accesses 1445system.cpu.l2cache.overall_accesses::cpu.data 1657284 # number of overall (read+write) accesses 1446system.cpu.l2cache.overall_accesses::total 2689018 # number of overall (read+write) accesses 1447system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000940 # miss rate for ReadReq accesses 1448system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000692 # miss rate for ReadReq accesses 1449system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016766 # miss rate for ReadReq accesses 1450system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026298 # miss rate for ReadReq accesses 1451system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses 1452system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823198 # miss rate for UpgradeReq accesses 1453system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823198 # miss rate for UpgradeReq accesses 1454system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461846 # miss rate for ReadExReq accesses 1455system.cpu.l2cache.ReadExReq_miss_rate::total 0.461846 # miss rate for ReadExReq accesses 1456system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000940 # miss rate for demand accesses 1457system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000692 # miss rate for demand accesses 1458system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016766 # miss rate for demand accesses 1459system.cpu.l2cache.demand_miss_rate::cpu.data 0.102015 # miss rate for demand accesses 1460system.cpu.l2cache.demand_miss_rate::total 0.068881 # miss rate for demand accesses 1461system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000940 # miss rate for overall accesses 1462system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000692 # miss rate for overall accesses 1463system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016766 # miss rate for overall accesses 1464system.cpu.l2cache.overall_miss_rate::cpu.data 0.102015 # miss rate for overall accesses 1465system.cpu.l2cache.overall_miss_rate::total 0.068881 # miss rate for overall accesses 1466system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86237.704918 # average ReadReq miss latency 1467system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77950 # average ReadReq miss latency 1468system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79420.581391 # average ReadReq miss latency 1469system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81654.305949 # average ReadReq miss latency 1470system.cpu.l2cache.ReadReq_avg_miss_latency::total 80970.321198 # average ReadReq miss latency 1471system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12244.042408 # average UpgradeReq miss latency 1472system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12244.042408 # average UpgradeReq miss latency 1473system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71225.893937 # average ReadExReq miss latency 1474system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71225.893937 # average ReadExReq miss latency 1475system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency 1476system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency 1477system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency 1478system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency 1479system.cpu.l2cache.demand_avg_miss_latency::total 73970.040562 # average overall miss latency 1480system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency 1481system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency 1482system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency 1483system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency 1484system.cpu.l2cache.overall_avg_miss_latency::total 73970.040562 # average overall miss latency |
| 1460system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1461system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1462system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1463system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1464system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1465system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1466system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1467system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1485system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1486system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1487system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1488system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1489system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1490system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1491system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1492system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1468system.cpu.l2cache.writebacks::writebacks 101658 # number of writebacks 1469system.cpu.l2cache.writebacks::total 101658 # number of writebacks | 1493system.cpu.l2cache.writebacks::writebacks 101920 # number of writebacks 1494system.cpu.l2cache.writebacks::total 101920 # number of writebacks |
| 1470system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits | 1495system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits |
| 1471system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits 1472system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits | 1496system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1497system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits |
| 1473system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits | 1498system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits |
| 1474system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits 1475system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits | 1499system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1500system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits |
| 1476system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits | 1501system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits |
| 1477system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits 1478system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits | 1502system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1503system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits |
| 1479system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses 1480system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses | 1504system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses 1505system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses |
| 1481system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16089 # number of ReadReq MSHR misses 1482system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35751 # number of ReadReq MSHR misses 1483system.cpu.l2cache.ReadReq_mshr_misses::total 51906 # number of ReadReq MSHR misses 1484system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1443 # number of UpgradeReq MSHR misses 1485system.cpu.l2cache.UpgradeReq_mshr_misses::total 1443 # number of UpgradeReq MSHR misses 1486system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132547 # number of ReadExReq MSHR misses 1487system.cpu.l2cache.ReadExReq_mshr_misses::total 132547 # number of ReadExReq MSHR misses | 1506system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16087 # number of ReadReq MSHR misses 1507system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36005 # number of ReadReq MSHR misses 1508system.cpu.l2cache.ReadReq_mshr_misses::total 52158 # number of ReadReq MSHR misses 1509system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses 1510system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses 1511system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133062 # number of ReadExReq MSHR misses 1512system.cpu.l2cache.ReadExReq_mshr_misses::total 133062 # number of ReadExReq MSHR misses |
| 1488system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses 1489system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses | 1513system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses 1514system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses |
| 1490system.cpu.l2cache.demand_mshr_misses::cpu.inst 16089 # number of demand (read+write) MSHR misses 1491system.cpu.l2cache.demand_mshr_misses::cpu.data 168298 # number of demand (read+write) MSHR misses 1492system.cpu.l2cache.demand_mshr_misses::total 184453 # number of demand (read+write) MSHR misses | 1515system.cpu.l2cache.demand_mshr_misses::cpu.inst 16087 # number of demand (read+write) MSHR misses 1516system.cpu.l2cache.demand_mshr_misses::cpu.data 169067 # number of demand (read+write) MSHR misses 1517system.cpu.l2cache.demand_mshr_misses::total 185220 # number of demand (read+write) MSHR misses |
| 1493system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses 1494system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses | 1518system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses 1519system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses |
| 1495system.cpu.l2cache.overall_mshr_misses::cpu.inst 16089 # number of overall MSHR misses 1496system.cpu.l2cache.overall_mshr_misses::cpu.data 168298 # number of overall MSHR misses 1497system.cpu.l2cache.overall_mshr_misses::total 184453 # number of overall MSHR misses 1498system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4857750 # number of ReadReq MSHR miss cycles 1499system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 353750 # number of ReadReq MSHR miss cycles 1500system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1189838014 # number of ReadReq MSHR miss cycles 1501system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545516291 # number of ReadReq MSHR miss cycles 1502system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3740565805 # number of ReadReq MSHR miss cycles 1503system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15357924 # number of UpgradeReq MSHR miss cycles 1504system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15357924 # number of UpgradeReq MSHR miss cycles 1505system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7668131300 # number of ReadExReq MSHR miss cycles 1506system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7668131300 # number of ReadExReq MSHR miss cycles 1507system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4857750 # number of demand (read+write) MSHR miss cycles 1508system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 353750 # number of demand (read+write) MSHR miss cycles 1509system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1189838014 # number of demand (read+write) MSHR miss cycles 1510system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10213647591 # number of demand (read+write) MSHR miss cycles 1511system.cpu.l2cache.demand_mshr_miss_latency::total 11408697105 # number of demand (read+write) MSHR miss cycles 1512system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4857750 # number of overall MSHR miss cycles 1513system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 353750 # number of overall MSHR miss cycles 1514system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1189838014 # number of overall MSHR miss cycles 1515system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10213647591 # number of overall MSHR miss cycles 1516system.cpu.l2cache.overall_mshr_miss_latency::total 11408697105 # number of overall MSHR miss cycles 1517system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250267000 # number of ReadReq MSHR uncacheable cycles 1518system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250267000 # number of ReadReq MSHR uncacheable cycles 1519system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2371416000 # number of WriteReq MSHR uncacheable cycles 1520system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2371416000 # number of WriteReq MSHR uncacheable cycles 1521system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91621683000 # number of overall MSHR uncacheable cycles 1522system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91621683000 # number of overall MSHR uncacheable cycles 1523system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for ReadReq accesses 1524system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for ReadReq accesses 1525system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for ReadReq accesses 1526system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026118 # mshr miss rate for ReadReq accesses 1527system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021679 # mshr miss rate for ReadReq accesses 1528system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820352 # mshr miss rate for UpgradeReq accesses 1529system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820352 # mshr miss rate for UpgradeReq accesses 1530system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461348 # mshr miss rate for ReadExReq accesses 1531system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461348 # mshr miss rate for ReadExReq accesses 1532system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for demand accesses 1533system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for demand accesses 1534system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for demand accesses 1535system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for demand accesses 1536system.cpu.l2cache.demand_mshr_miss_rate::total 0.068785 # mshr miss rate for demand accesses 1537system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for overall accesses 1538system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for overall accesses 1539system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for overall accesses 1540system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for overall accesses 1541system.cpu.l2cache.overall_mshr_miss_rate::total 0.068785 # mshr miss rate for overall accesses 1542system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average ReadReq mshr miss latency 1543system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70750 # average ReadReq mshr miss latency 1544system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73953.509479 # average ReadReq mshr miss latency 1545system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71201.261251 # average ReadReq mshr miss latency 1546system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72064.227739 # average ReadReq mshr miss latency 1547system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10643.051975 # average UpgradeReq mshr miss latency 1548system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10643.051975 # average UpgradeReq mshr miss latency 1549system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57852.167910 # average ReadExReq mshr miss latency 1550system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57852.167910 # average ReadExReq mshr miss latency 1551system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average overall mshr miss latency 1552system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency 1553system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency 1554system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency 1555system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency 1556system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average overall mshr miss latency 1557system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency 1558system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency 1559system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency 1560system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency | 1520system.cpu.l2cache.overall_mshr_misses::cpu.inst 16087 # number of overall MSHR misses 1521system.cpu.l2cache.overall_mshr_misses::cpu.data 169067 # number of overall MSHR misses 1522system.cpu.l2cache.overall_mshr_misses::total 185220 # number of overall MSHR misses 1523system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4502000 # number of ReadReq MSHR miss cycles 1524system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles 1525system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075523016 # number of ReadReq MSHR miss cycles 1526system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2491735810 # number of ReadReq MSHR miss cycles 1527system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3572087076 # number of ReadReq MSHR miss cycles 1528system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15586943 # number of UpgradeReq MSHR miss cycles 1529system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15586943 # number of UpgradeReq MSHR miss cycles 1530system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7807116101 # number of ReadExReq MSHR miss cycles 1531system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7807116101 # number of ReadExReq MSHR miss cycles 1532system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4502000 # number of demand (read+write) MSHR miss cycles 1533system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles 1534system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075523016 # number of demand (read+write) MSHR miss cycles 1535system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10298851911 # number of demand (read+write) MSHR miss cycles 1536system.cpu.l2cache.demand_mshr_miss_latency::total 11379203177 # number of demand (read+write) MSHR miss cycles 1537system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4502000 # number of overall MSHR miss cycles 1538system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles 1539system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075523016 # number of overall MSHR miss cycles 1540system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10298851911 # number of overall MSHR miss cycles 1541system.cpu.l2cache.overall_mshr_miss_latency::total 11379203177 # number of overall MSHR miss cycles 1542system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251387000 # number of ReadReq MSHR uncacheable cycles 1543system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251387000 # number of ReadReq MSHR uncacheable cycles 1544system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372677500 # number of WriteReq MSHR uncacheable cycles 1545system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372677500 # number of WriteReq MSHR uncacheable cycles 1546system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624064500 # number of overall MSHR uncacheable cycles 1547system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624064500 # number of overall MSHR uncacheable cycles 1548system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for ReadReq accesses 1549system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for ReadReq accesses 1550system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for ReadReq accesses 1551system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026297 # mshr miss rate for ReadReq accesses 1552system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses 1553system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823198 # mshr miss rate for UpgradeReq accesses 1554system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823198 # mshr miss rate for UpgradeReq accesses 1555system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461846 # mshr miss rate for ReadExReq accesses 1556system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461846 # mshr miss rate for ReadExReq accesses 1557system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for demand accesses 1558system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for demand accesses 1559system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for demand accesses 1560system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for demand accesses 1561system.cpu.l2cache.demand_mshr_miss_rate::total 0.068880 # mshr miss rate for demand accesses 1562system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for overall accesses 1563system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for overall accesses 1564system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for overall accesses 1565system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for overall accesses 1566system.cpu.l2cache.overall_mshr_miss_rate::total 0.068880 # mshr miss rate for overall accesses 1567system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency 1568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency 1569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency 1570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency 1571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency 1572system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency 1573system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency 1574system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency 1575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency 1576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency 1577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1578system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency 1579system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency 1580system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency 1581system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency 1582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency 1584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency 1585system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency |
| 1561system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1562system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1563system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1564system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1565system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1566system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1567system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1568system.cpu.kern.inst.arm 0 # number of arm instructions executed 1569system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1570 1571---------- End Simulation Statistics ---------- | 1586system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1587system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1588system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1589system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1590system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1591system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1592system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1593system.cpu.kern.inst.arm 0 # number of arm instructions executed 1594system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1595 1596---------- End Simulation Statistics ---------- |