| stats.txt (9702:094d0280e481) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.140938 # Number of seconds simulated 4sim_ticks 5140937585000 # Number of ticks simulated 5final_tick 5140937585000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.125717 # Number of seconds simulated 4sim_ticks 5125716951000 # Number of ticks simulated 5final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 121697 # Simulator instruction rate (inst/s) 8host_op_rate 240559 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1534230705 # Simulator tick rate (ticks/s) 10host_mem_usage 773616 # Number of bytes of host memory used 11host_seconds 3350.82 # Real time elapsed on the host 12sim_insts 407786881 # Number of instructions simulated 13sim_ops 806071515 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2479872 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory | 7host_inst_rate 203249 # Simulator instruction rate (inst/s) 8host_op_rate 401765 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2555120499 # Simulator tick rate (ticks/s) 10host_mem_usage 728844 # Number of bytes of host memory used 11host_seconds 2006.06 # Real time elapsed on the host 12sim_insts 407728401 # Number of instructions simulated 13sim_ops 805963181 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 1026240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10765120 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14275328 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1026240 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1026240 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9536256 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9536256 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38748 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.inst 16035 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168205 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 223052 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149004 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149004 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 482377 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 722 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.inst 199621 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2093999 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2776795 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 199621 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 199621 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1854964 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1854964 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1854964 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482377 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s) | 35system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) |
| 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.inst 199621 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2093999 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4631759 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 223052 # Total number of read requests seen 50system.physmem.writeReqs 149004 # Total number of write requests seen 51system.physmem.cpureqs 373790 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14275328 # Total number of bytes read from memory 53system.physmem.bytesWritten 9536256 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14275328 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9536256 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q | 46system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 222005 # Total number of read requests seen 50system.physmem.writeReqs 148125 # Total number of write requests seen 51system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14208320 # Total number of bytes read from memory 53system.physmem.bytesWritten 9480000 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q |
| 57system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed | 57system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed |
| 58system.physmem.perBankRdReqs::0 13636 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 12914 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 13124 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 16345 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13470 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 13111 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13382 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 16266 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13519 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 13235 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13394 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 15885 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13088 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 12601 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13202 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15809 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 8837 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 8387 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8583 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 11810 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8818 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 8522 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8723 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 11661 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8790 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8601 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 8761 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 11230 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8431 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8583 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 11174 # Track writes on a per bank basis | 58system.physmem.perBankRdReqs::0 13839 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 13931 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 14596 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 13757 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13936 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 13652 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13421 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 14010 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13333 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 13233 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13920 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 13971 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 14973 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 14183 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13896 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 13262 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 9392 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 9725 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 9208 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 9406 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 9142 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8981 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 9409 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8580 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8586 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 9440 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 9338 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 10150 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 9429 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 9215 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 8819 # Track writes on a per bank basis |
| 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 91system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5140937531500 # Total gap between requests | 91system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5125716897500 # Total gap between requests |
| 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes | 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 99system.physmem.readPktSize::6 223052 # Categorize read packet sizes | 99system.physmem.readPktSize::6 222005 # Categorize read packet sizes |
| 100system.physmem.writePktSize::0 0 # Categorize write packet sizes 101system.physmem.writePktSize::1 0 # Categorize write packet sizes 102system.physmem.writePktSize::2 0 # Categorize write packet sizes 103system.physmem.writePktSize::3 0 # Categorize write packet sizes 104system.physmem.writePktSize::4 0 # Categorize write packet sizes 105system.physmem.writePktSize::5 0 # Categorize write packet sizes | 100system.physmem.writePktSize::0 0 # Categorize write packet sizes 101system.physmem.writePktSize::1 0 # Categorize write packet sizes 102system.physmem.writePktSize::2 0 # Categorize write packet sizes 103system.physmem.writePktSize::3 0 # Categorize write packet sizes 104system.physmem.writePktSize::4 0 # Categorize write packet sizes 105system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 106system.physmem.writePktSize::6 149004 # Categorize write packet sizes 107system.physmem.rdQLenPdf::0 172997 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 18175 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 7573 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 3487 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 3011 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 2422 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1861 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1763 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::9 1672 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::10 1114 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1019 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 962 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 902 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::14 823 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::16 907 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::17 865 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::18 412 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::19 253 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::20 31 # What read queue length does an incoming req see | 106system.physmem.writePktSize::6 148125 # Categorize write packet sizes 107system.physmem.rdQLenPdf::0 174153 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 21252 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 7390 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 2984 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 2510 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 2064 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1118 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1035 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::9 974 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::10 917 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 901 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 864 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::15 933 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::16 750 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::17 519 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::18 246 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::19 155 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see |
| 128system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see | 128system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see |
| 129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see | 129system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see |
| 132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 139system.physmem.wrQLenPdf::0 5326 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::1 5675 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::2 6279 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::3 6374 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::4 6421 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::6 6466 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::7 6470 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 6471 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 6479 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 6478 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 6478 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 6478 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 6478 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 6478 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::15 6478 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 6478 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 6478 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 6478 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 6478 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6478 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 804 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 200 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 105 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 58 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see | 139system.physmem.wrQLenPdf::0 5396 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::1 5689 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::2 6383 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::3 6417 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::4 6424 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::5 6425 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::6 6430 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::7 6431 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 6433 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 6440 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 6440 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 6440 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 6440 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 6440 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 6440 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::15 6440 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 6440 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 6440 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 6440 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 6440 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6440 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 6440 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 1045 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 752 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see |
| 170system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 171system.physmem.totQLat 4794975750 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 9301923250 # Sum of mem lat for all requests 173system.physmem.totBusLat 1114905000 # Total cycles spent in databus access 174system.physmem.totBankLat 3392042500 # Total cycles spent in bank access 175system.physmem.avgQLat 21503.97 # Average queueing delay per request 176system.physmem.avgBankLat 15212.25 # Average bank access latency per request | 170system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see 171system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation 172system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation 173system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation 174system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3968-3971 4 0.01% 98.71% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4736-4739 1 0.00% 98.79% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4864-4867 3 0.00% 98.80% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.80% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.86% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.86% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6848-6851 4 0.01% 98.88% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6976-6979 4 0.01% 98.89% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.90% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.91% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7360-7363 2 0.00% 98.92% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.92% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.92% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7936-7939 3 0.00% 98.93% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.94% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.48% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.48% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.49% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.49% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.49% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::9536-9539 7 0.01% 99.50% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.51% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.51% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.51% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.52% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.52% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.52% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.53% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.53% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.53% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::10560-10563 3 0.00% 99.54% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::10624-10627 2 0.00% 99.54% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.55% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.55% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.55% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.56% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.56% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.58% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.58% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.59% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.59% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.60% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.60% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.71% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.76% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::16000-16003 7 0.01% 99.81% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.83% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.98% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation 372system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays 373system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests 374system.physmem.totBusLat 1109565000 # Total cycles spent in databus access 375system.physmem.totBankLat 3154263750 # Total cycles spent in bank access 376system.physmem.avgQLat 18030.39 # Average queueing delay per request 377system.physmem.avgBankLat 14213.97 # Average bank access latency per request |
| 177system.physmem.avgBusLat 5000.00 # Average bus latency per request | 378system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 178system.physmem.avgMemAccLat 41716.21 # Average memory access latency 179system.physmem.avgRdBW 2.78 # Average achieved read bandwidth in MB/s | 379system.physmem.avgMemAccLat 37244.35 # Average memory access latency 380system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s |
| 180system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s | 381system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s |
| 181system.physmem.avgConsumedRdBW 2.78 # Average consumed read bandwidth in MB/s | 382system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s |
| 182system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 184system.physmem.busUtil 0.04 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.00 # Average read queue length over time | 383system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s 384system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 385system.physmem.busUtil 0.04 # Data bus utilization in percentage 386system.physmem.avgRdQLen 0.00 # Average read queue length over time |
| 186system.physmem.avgWrQLen 15.58 # Average write queue length over time 187system.physmem.readRowHits 191257 # Number of row buffer hits during reads 188system.physmem.writeRowHits 105612 # Number of row buffer hits during writes 189system.physmem.readRowHitRate 85.77 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate 70.88 # Row buffer hit rate for writes 191system.physmem.avgGap 13817644.47 # Average gap between requests 192system.iocache.replacements 47576 # number of replacements 193system.iocache.tagsinuse 0.128763 # Cycle average of tags in use | 387system.physmem.avgWrQLen 11.40 # Average write queue length over time 388system.physmem.readRowHits 198637 # Number of row buffer hits during reads 389system.physmem.writeRowHits 108987 # Number of row buffer hits during writes 390system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads 391system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes 392system.physmem.avgGap 13848423.25 # Average gap between requests 393system.membus.throughput 5098961 # Throughput (bytes/s) 394system.membus.trans_dist::ReadReq 662131 # Transaction distribution 395system.membus.trans_dist::ReadResp 662131 # Transaction distribution 396system.membus.trans_dist::WriteReq 13694 # Transaction distribution 397system.membus.trans_dist::WriteResp 13694 # Transaction distribution 398system.membus.trans_dist::Writeback 148125 # Transaction distribution 399system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution 400system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution 401system.membus.trans_dist::ReadExReq 179249 # Transaction distribution 402system.membus.trans_dist::ReadExResp 179246 # Transaction distribution 403system.membus.trans_dist::MessageReq 1640 # Transaction distribution 404system.membus.trans_dist::MessageResp 1640 # Transaction distribution 405system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) 406system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes) 407system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes) 408system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) 409system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) 410system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes) 411system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes) 412system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes) 413system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes) 414system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) 415system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) 416system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) 417system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes) 418system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) 419system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes) 420system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes) 421system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) 422system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) 423system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes) 424system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes) 425system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes) 426system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes) 427system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) 428system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) 429system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) 430system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes) 431system.membus.data_through_bus 25486679 # Total data (bytes) 432system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes) 433system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks) 434system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 435system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks) 436system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 437system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks) 438system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 439system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks) 440system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 441system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks) 442system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 443system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks) 444system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 445system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks) 446system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 447system.iocache.replacements 47577 # number of replacements 448system.iocache.tagsinuse 0.079131 # Cycle average of tags in use |
| 194system.iocache.total_refs 0 # Total number of references to valid blocks. | 449system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 195system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. | 450system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. |
| 196system.iocache.avg_refs 0 # Average number of references to valid blocks. | 451system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 197system.iocache.warmup_cycle 4991974997000 # Cycle when the warmup percentage was hit. 198system.iocache.occ_blocks::pc.south_bridge.ide 0.128763 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.008048 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.008048 # Average percentage of cache occupancy 201system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 911 # number of ReadReq misses | 452system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit. 453system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor 454system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy 455system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy 456system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses 457system.iocache.ReadReq_misses::total 912 # number of ReadReq misses |
| 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses | 458system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 459system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses |
| 205system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 206system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 207system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 208system.iocache.overall_misses::total 47631 # number of overall misses 209system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147497397 # number of ReadReq miss cycles 210system.iocache.ReadReq_miss_latency::total 147497397 # number of ReadReq miss cycles 211system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10072244306 # number of WriteReq miss cycles 212system.iocache.WriteReq_miss_latency::total 10072244306 # number of WriteReq miss cycles 213system.iocache.demand_miss_latency::pc.south_bridge.ide 10219741703 # number of demand (read+write) miss cycles 214system.iocache.demand_miss_latency::total 10219741703 # number of demand (read+write) miss cycles 215system.iocache.overall_miss_latency::pc.south_bridge.ide 10219741703 # number of overall miss cycles 216system.iocache.overall_miss_latency::total 10219741703 # number of overall miss cycles 217system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 218system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) | 460system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses 461system.iocache.demand_misses::total 47632 # number of demand (read+write) misses 462system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses 463system.iocache.overall_misses::total 47632 # number of overall misses 464system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles 465system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles 466system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles 467system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles 468system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles 469system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles 470system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles 471system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles 472system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) 473system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) |
| 219system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 220system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) | 474system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 475system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) |
| 221system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 222system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 223system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 224system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses | 476system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses 477system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses 478system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses 479system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses |
| 225system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 226system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 227system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 228system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 229system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 231system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 480system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 481system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 482system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 483system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 484system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 485system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 486system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 487system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 233system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723 # average ReadReq miss latency 234system.iocache.ReadReq_avg_miss_latency::total 161907.131723 # average ReadReq miss latency 235system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933 # average WriteReq miss latency 236system.iocache.WriteReq_avg_miss_latency::total 215587.420933 # average WriteReq miss latency 237system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency 238system.iocache.demand_avg_miss_latency::total 214560.721022 # average overall miss latency 239system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency 240system.iocache.overall_avg_miss_latency::total 214560.721022 # average overall miss latency 241system.iocache.blocked_cycles::no_mshrs 139153 # number of cycles access was blocked | 488system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency 489system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency 490system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency 491system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency 492system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency 493system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency 494system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency 495system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency 496system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked |
| 242system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 497system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 243system.iocache.blocked::no_mshrs 12645 # number of cycles access was blocked | 498system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked |
| 244system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 499system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 245system.iocache.avg_blocked_cycles::no_mshrs 11.004587 # average number of cycles each access was blocked | 500system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked |
| 246system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.iocache.fast_writes 0 # number of fast writes performed 248system.iocache.cache_copies 0 # number of cache copies performed 249system.iocache.writebacks::writebacks 46667 # number of writebacks 250system.iocache.writebacks::total 46667 # number of writebacks | 501system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 502system.iocache.fast_writes 0 # number of fast writes performed 503system.iocache.cache_copies 0 # number of cache copies performed 504system.iocache.writebacks::writebacks 46667 # number of writebacks 505system.iocache.writebacks::total 46667 # number of writebacks |
| 251system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 252system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses | 506system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses 507system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses |
| 253system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 254system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses | 508system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 509system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses |
| 255system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 256system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 257system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 258system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses 259system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100104427 # number of ReadReq MSHR miss cycles 260system.iocache.ReadReq_mshr_miss_latency::total 100104427 # number of ReadReq MSHR miss cycles 261system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7641446543 # number of WriteReq MSHR miss cycles 262system.iocache.WriteReq_mshr_miss_latency::total 7641446543 # number of WriteReq MSHR miss cycles 263system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of demand (read+write) MSHR miss cycles 264system.iocache.demand_mshr_miss_latency::total 7741550970 # number of demand (read+write) MSHR miss cycles 265system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of overall MSHR miss cycles 266system.iocache.overall_mshr_miss_latency::total 7741550970 # number of overall MSHR miss cycles | 510system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses 511system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses 512system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses 513system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses 514system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles 515system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles 516system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles 517system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles 518system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles 519system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles 520system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles 521system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles |
| 267system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 268system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 269system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 270system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 271system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 272system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 273system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 274system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 522system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 523system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 524system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 525system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 526system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 527system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 528system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 529system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 275system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063 # average ReadReq mshr miss latency 276system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063 # average ReadReq mshr miss latency 277system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225 # average WriteReq mshr miss latency 278system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225 # average WriteReq mshr miss latency 279system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency 280system.iocache.demand_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency 281system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency 282system.iocache.overall_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency | 530system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency 531system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency 532system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency 533system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency 534system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency 535system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency 536system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency 537system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency |
| 283system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 285system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 286system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 287system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 288system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 289system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 290system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 291system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 292system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 293system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 294system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 295system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 538system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 539system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 540system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 541system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 542system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 543system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 544system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 545system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 546system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 547system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 548system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 549system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 550system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 296system.cpu.branchPred.lookups 85620726 # Number of BP lookups 297system.cpu.branchPred.condPredicted 85620726 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 882198 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 79268619 # Number of BTB lookups 300system.cpu.branchPred.BTBHits 77534559 # Number of BTB hits | 551system.iobus.throughput 639145 # Throughput (bytes/s) 552system.iobus.trans_dist::ReadReq 225496 # Transaction distribution 553system.iobus.trans_dist::ReadResp 225496 # Transaction distribution 554system.iobus.trans_dist::WriteReq 57527 # Transaction distribution 555system.iobus.trans_dist::WriteResp 57527 # Transaction distribution 556system.iobus.trans_dist::MessageReq 1640 # Transaction distribution 557system.iobus.trans_dist::MessageResp 1640 # Transaction distribution 558system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 559system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 560system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) 561system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 562system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 563system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 564system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 565system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 566system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 567system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 568system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 569system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 570system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) 571system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 572system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 573system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 574system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 575system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 576system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes) 577system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) 578system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes) 579system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) 580system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes) 581system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) 582system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 583system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) 595system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 596system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 597system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 598system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 599system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) 600system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 601system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes) 602system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 603system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 604system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) 605system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 606system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 607system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 608system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 643system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) 644system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 645system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes) 646system.iobus.data_through_bus 3276074 # Total data (bytes) 647system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks) 648system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 649system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 650system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 651system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 652system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 653system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) 654system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 655system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 656system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 657system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 658system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 660system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 662system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 664system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 666system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 667system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 668system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 669system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 670system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 671system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 672system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 673system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks) 674system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 675system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 676system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 677system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 678system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 679system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 680system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 681system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 682system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 683system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks) 684system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 685system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 686system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 687system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks) 688system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 689system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks) 690system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 691system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks) 692system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 693system.cpu.branchPred.lookups 85601186 # Number of BP lookups 694system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted 695system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect 696system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups 697system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits |
| 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 698system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 302system.cpu.branchPred.BTBHitPct 97.812426 # BTB Hit Percentage 303system.cpu.branchPred.usedRAS 1442315 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 180251 # Number of incorrect RAS predictions. 305system.cpu.numCycles 447791761 # number of cpu cycles simulated | 699system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage 700system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target. 701system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions. 702system.cpu.numCycles 453375451 # number of cpu cycles simulated |
| 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 703system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 704system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 308system.cpu.fetch.icacheStallCycles 25559948 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 422856490 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 85620726 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 78976874 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 162677741 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 4000997 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 98298 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.BlockedCycles 65919320 # Number of cycles fetch has spent blocked 316system.cpu.fetch.MiscStallCycles 43594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 317system.cpu.fetch.PendingTrapStallCycles 86507 # Number of stall cycles due to pending traps 318system.cpu.fetch.IcacheWaitRetryStallCycles 459 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 8492083 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 383635 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 2345 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 257461374 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 3.243647 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.415529 # Number of instructions fetched each cycle (Total) | 705system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss 706system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed 707system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered 708system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken 709system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked 710system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing 711system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb 712system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked 713system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 714system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps 715system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR 716system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched 717system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed 718system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed 719system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total) 720system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total) 721system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total) |
| 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 722system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 326system.cpu.fetch.rateDist::0 95198026 36.98% 36.98% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 1534816 0.60% 37.57% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 71825104 27.90% 65.47% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 895357 0.35% 65.82% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 1570607 0.61% 66.43% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 2391332 0.93% 67.36% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 1020158 0.40% 67.75% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 1325162 0.51% 68.27% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 81700812 31.73% 100.00% # Number of instructions fetched each cycle (Total) | 723system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total) 724system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total) 725system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total) 726system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total) 727system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total) 728system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total) 729system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total) 730system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total) 731system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total) |
| 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 732system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 733system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 734system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 338system.cpu.fetch.rateDist::total 257461374 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.191207 # Number of branch fetches per cycle 340system.cpu.fetch.rate 0.944315 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 29461192 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 63064302 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 158550724 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 3309649 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 3075507 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 832761340 # Number of instructions handled by decode 347system.cpu.decode.SquashedInsts 863 # Number of squashed instructions handled by decode 348system.cpu.rename.SquashCycles 3075507 # Number of cycles rename is squashing 349system.cpu.rename.IdleCycles 32153278 # Number of cycles rename is idle 350system.cpu.rename.BlockCycles 38465118 # Number of cycles rename is blocking 351system.cpu.rename.serializeStallCycles 12079112 # count of cycles rename stalled for serializing inst 352system.cpu.rename.RunCycles 158824437 # Number of cycles rename is running 353system.cpu.rename.UnblockCycles 12863922 # Number of cycles rename is unblocking 354system.cpu.rename.RenamedInsts 829829025 # Number of instructions processed by rename 355system.cpu.rename.ROBFullEvents 19879 # Number of times rename has blocked due to ROB full 356system.cpu.rename.IQFullEvents 6055166 # Number of times rename has blocked due to IQ full 357system.cpu.rename.LSQFullEvents 4924546 # Number of times rename has blocked due to LSQ full 358system.cpu.rename.FullRegisterEvents 11525 # Number of times there has been no free registers 359system.cpu.rename.RenamedOperands 991492877 # Number of destination operands rename has renamed 360system.cpu.rename.RenameLookups 1800847756 # Number of register rename lookups that rename has made 361system.cpu.rename.int_rename_lookups 1800847292 # Number of integer rename lookups 362system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups 363system.cpu.rename.CommittedMaps 963999366 # Number of HB maps that are committed 364system.cpu.rename.UndoneMaps 27493506 # Number of HB maps that are undone due to squashing 365system.cpu.rename.serializingInsts 456551 # count of serializing insts renamed 366system.cpu.rename.tempSerializingInsts 462682 # count of temporary serializing insts renamed 367system.cpu.rename.skidInsts 29304477 # count of insts added to the skid buffer 368system.cpu.memDep0.insertedLoads 16752339 # Number of loads inserted to the mem dependence unit. 369system.cpu.memDep0.insertedStores 9837983 # Number of stores inserted to the mem dependence unit. 370system.cpu.memDep0.conflictingLoads 1099709 # Number of conflicting loads. 371system.cpu.memDep0.conflictingStores 928773 # Number of conflicting stores. 372system.cpu.iq.iqInstsAdded 825036488 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqNonSpecInstsAdded 1186686 # Number of non-speculative instructions added to the IQ 374system.cpu.iq.iqInstsIssued 821069910 # Number of instructions issued 375system.cpu.iq.iqSquashedInstsIssued 146070 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 19309743 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 29357166 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 131932 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 257461374 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 3.189099 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 2.383585 # Number of insts issued each cycle | 735system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total) 736system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle 737system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle 738system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle 739system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked 740system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running 741system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking 742system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing 743system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode 744system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode 745system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing 746system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle 747system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking 748system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst 749system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running 750system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking 751system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename 752system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full 753system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full 754system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full 755system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers 756system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed 757system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made 758system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups 759system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups 760system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed 761system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing 762system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed 763system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed 764system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer 765system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit. 766system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit. 767system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads. 768system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores. 769system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec) 770system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ 771system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued 772system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued 773system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling 774system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph 775system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed 776system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle 777system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle 778system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle |
| 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 779system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 383system.cpu.iq.issued_per_cycle::0 71259249 27.68% 27.68% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 15575755 6.05% 33.73% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 10479111 4.07% 37.80% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 7383615 2.87% 40.67% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 75752504 29.42% 70.09% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 3772068 1.47% 71.55% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 72307575 28.08% 99.64% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 782694 0.30% 99.94% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 148803 0.06% 100.00% # Number of insts issued each cycle | 780system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle 781system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle 782system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle 783system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle 784system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle 785system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle 786system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle 787system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle 788system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle |
| 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 789system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 790system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 791system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 395system.cpu.iq.issued_per_cycle::total 257461374 # Number of insts issued each cycle | 792system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle |
| 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 793system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 397system.cpu.iq.fu_full::IntAlu 356313 33.63% 33.63% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntMult 241 0.02% 33.66% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 2452 0.23% 33.89% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.89% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemRead 547502 51.68% 85.57% # attempts to use FU when none available 427system.cpu.iq.fu_full::MemWrite 152922 14.43% 100.00% # attempts to use FU when none available | 794system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available 795system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available 796system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available 797system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available 798system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available 799system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available 800system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available 801system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available 802system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available 803system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available 804system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available 805system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available 806system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available 807system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available 808system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available 809system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available 810system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available 811system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available 812system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available 813system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available 814system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available 815system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available 816system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available 817system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available 818system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available 819system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available 820system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available 821system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available 822system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available 823system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available 824system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available |
| 428system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 825system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 826system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 430system.cpu.iq.FU_type_0::No_OpClass 308526 0.04% 0.04% # Type of FU issued 431system.cpu.iq.FU_type_0::IntAlu 793557907 96.65% 96.69% # Type of FU issued 432system.cpu.iq.FU_type_0::IntMult 150412 0.02% 96.71% # Type of FU issued 433system.cpu.iq.FU_type_0::IntDiv 124298 0.02% 96.72% # Type of FU issued | 827system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued 828system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued 829system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued 830system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued |
| 434system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 452system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued | 831system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued 832system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued 833system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued 834system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued 835system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued 836system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued 837system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued 838system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 849system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued 850system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued 851system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued 852system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued 853system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued 854system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued 855system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued 856system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued |
| 460system.cpu.iq.FU_type_0::MemRead 17694567 2.16% 98.88% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 9234200 1.12% 100.00% # Type of FU issued | 857system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued 858system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued |
| 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 859system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 860system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 464system.cpu.iq.FU_type_0::total 821069910 # Type of FU issued 465system.cpu.iq.rate 1.833598 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 1059430 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.001290 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 1900915279 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 845543458 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 817157785 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 821820724 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 1686147 # Number of loads that had data forwarded from stores | 861system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued 862system.cpu.iq.rate 1.810787 # Inst issue rate 863system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested 864system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) 865system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads 866system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes 867system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses 868system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads 869system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes 870system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses 871system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses 872system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses 873system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores |
| 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 874system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 478system.cpu.iew.lsq.thread0.squashedLoads 2748440 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 17101 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 11930 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 1411969 # Number of stores squashed | 875system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed 876system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed 877system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations 878system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed |
| 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 879system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 880system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 484system.cpu.iew.lsq.thread0.rescheduledLoads 1931504 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 11624 # Number of times an access to memory failed due to the cache being blocked | 881system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled 882system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked |
| 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 883system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 487system.cpu.iew.iewSquashCycles 3075507 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 26873503 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 2150322 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 826223174 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 241070 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 16752339 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 9837983 # Number of dispatched store instructions 494system.cpu.iew.iewDispNonSpecInsts 692103 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 1621529 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 12267 # Number of times the LSQ has become full, causing a stall 497system.cpu.iew.memOrderViolationEvents 11930 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 498132 # Number of branches that were predicted taken incorrectly 499system.cpu.iew.predictedNotTakenIncorrect 506603 # Number of branches that were predicted not taken incorrectly 500system.cpu.iew.branchMispredicts 1004735 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 819660888 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 17391685 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 1409021 # Number of squashed instructions skipped in execute | 884system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing 885system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking 886system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking 887system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ 888system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch 889system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions 890system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions 891system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions 892system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall 893system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall 894system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations 895system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly 896system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly 897system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute 898system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions 899system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed 900system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute |
| 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed | 901system.cpu.iew.exec_swp 0 # number of swp insts executed 902system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 506system.cpu.iew.exec_refs 26440023 # number of memory reference insts executed 507system.cpu.iew.exec_branches 83107253 # Number of branches executed 508system.cpu.iew.exec_stores 9048338 # Number of stores executed 509system.cpu.iew.exec_rate 1.830451 # Inst execution rate 510system.cpu.iew.wb_sent 819258374 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 817157837 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 638799704 # num instructions producing a value 513system.cpu.iew.wb_consumers 1044337102 # num instructions consuming a value | 903system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed 904system.cpu.iew.exec_branches 83095032 # Number of branches executed 905system.cpu.iew.exec_stores 9034738 # Number of stores executed 906system.cpu.iew.exec_rate 1.807683 # Inst execution rate 907system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit 908system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back 909system.cpu.iew.wb_producers 638600685 # num instructions producing a value 910system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value |
| 514system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 911system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 515system.cpu.iew.wb_rate 1.824861 # insts written-back per cycle 516system.cpu.iew.wb_fanout 0.611680 # average fanout of values written-back | 912system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle 913system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back |
| 517system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 914system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 518system.cpu.commit.commitSquashedInsts 20042352 # The number of squashed insts skipped by commit 519system.cpu.commit.commitNonSpecStalls 1054753 # The number of times commit has been forced to stall to communicate backwards 520system.cpu.commit.branchMispredicts 891546 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 254385866 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 3.168696 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 2.858566 # Number of insts commited each cycle | 915system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit 916system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards 917system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted 918system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle 919system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle 920system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle |
| 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 921system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 525system.cpu.commit.committed_per_cycle::0 82972146 32.62% 32.62% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::1 11724447 4.61% 37.23% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::2 3813249 1.50% 38.72% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 74747378 29.38% 68.11% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::4 2384925 0.94% 69.05% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::5 1476326 0.58% 69.63% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::6 865615 0.34% 69.97% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 70850824 27.85% 97.82% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 5550956 2.18% 100.00% # Number of insts commited each cycle | 922system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle 923system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle 924system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle 925system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle 926system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle 927system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle 928system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle 929system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle 930system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle |
| 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 931system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 932system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 933system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 537system.cpu.commit.committed_per_cycle::total 254385866 # Number of insts commited each cycle 538system.cpu.commit.committedInsts 407786881 # Number of instructions committed 539system.cpu.commit.committedOps 806071515 # Number of ops (including micro ops) committed | 934system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle 935system.cpu.commit.committedInsts 407728401 # Number of instructions committed 936system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed |
| 540system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 937system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 541system.cpu.commit.refs 22429911 # Number of memory references committed 542system.cpu.commit.loads 14003897 # Number of loads committed 543system.cpu.commit.membars 474463 # Number of memory barriers committed 544system.cpu.commit.branches 82163817 # Number of branches committed | 938system.cpu.commit.refs 22399743 # Number of memory references committed 939system.cpu.commit.loads 13982748 # Number of loads committed 940system.cpu.commit.membars 474399 # Number of memory barriers committed 941system.cpu.commit.branches 82153759 # Number of branches committed |
| 545system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 942system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 546system.cpu.commit.int_insts 735061477 # Number of committed integer instructions. 547system.cpu.commit.function_calls 1156045 # Number of function calls committed. 548system.cpu.commit.bw_lim_events 5550956 # number cycles where commit BW limit reached | 943system.cpu.commit.int_insts 734952654 # Number of committed integer instructions. 944system.cpu.commit.function_calls 1154691 # Number of function calls committed. 945system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached |
| 549system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 946system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 550system.cpu.rob.rob_reads 1074870508 # The number of ROB reads 551system.cpu.rob.rob_writes 1655318425 # The number of ROB writes 552system.cpu.timesIdled 1256763 # Number of times that the entire CPU went into an idle state and unscheduled itself 553system.cpu.idleCycles 190330387 # Total number of cycles that the CPU has spent unscheduled due to idling 554system.cpu.quiesceCycles 9834088814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 555system.cpu.committedInsts 407786881 # Number of Instructions Simulated 556system.cpu.committedOps 806071515 # Number of Ops (including micro ops) Simulated 557system.cpu.committedInsts_total 407786881 # Number of Instructions Simulated 558system.cpu.cpi 1.098102 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 1.098102 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.910662 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.910662 # IPC: Total IPC of All Threads 562system.cpu.int_regfile_reads 1504614065 # number of integer regfile reads 563system.cpu.int_regfile_writes 975429838 # number of integer regfile writes 564system.cpu.fp_regfile_reads 52 # number of floating regfile reads 565system.cpu.misc_regfile_reads 264130300 # number of misc regfile reads 566system.cpu.misc_regfile_writes 403010 # number of misc regfile writes 567system.cpu.icache.replacements 955437 # number of replacements 568system.cpu.icache.tagsinuse 509.903328 # Cycle average of tags in use 569system.cpu.icache.total_refs 7482159 # Total number of references to valid blocks. 570system.cpu.icache.sampled_refs 955949 # Sample count of references to valid blocks. 571system.cpu.icache.avg_refs 7.826944 # Average number of references to valid blocks. 572system.cpu.icache.warmup_cycle 146514700000 # Cycle when the warmup percentage was hit. 573system.cpu.icache.occ_blocks::cpu.inst 509.903328 # Average occupied blocks per requestor 574system.cpu.icache.occ_percent::cpu.inst 0.995905 # Average percentage of cache occupancy 575system.cpu.icache.occ_percent::total 0.995905 # Average percentage of cache occupancy 576system.cpu.icache.ReadReq_hits::cpu.inst 7482159 # number of ReadReq hits 577system.cpu.icache.ReadReq_hits::total 7482159 # number of ReadReq hits 578system.cpu.icache.demand_hits::cpu.inst 7482159 # number of demand (read+write) hits 579system.cpu.icache.demand_hits::total 7482159 # number of demand (read+write) hits 580system.cpu.icache.overall_hits::cpu.inst 7482159 # number of overall hits 581system.cpu.icache.overall_hits::total 7482159 # number of overall hits 582system.cpu.icache.ReadReq_misses::cpu.inst 1009922 # number of ReadReq misses 583system.cpu.icache.ReadReq_misses::total 1009922 # number of ReadReq misses 584system.cpu.icache.demand_misses::cpu.inst 1009922 # number of demand (read+write) misses 585system.cpu.icache.demand_misses::total 1009922 # number of demand (read+write) misses 586system.cpu.icache.overall_misses::cpu.inst 1009922 # number of overall misses 587system.cpu.icache.overall_misses::total 1009922 # number of overall misses 588system.cpu.icache.ReadReq_miss_latency::cpu.inst 13938284992 # number of ReadReq miss cycles 589system.cpu.icache.ReadReq_miss_latency::total 13938284992 # number of ReadReq miss cycles 590system.cpu.icache.demand_miss_latency::cpu.inst 13938284992 # number of demand (read+write) miss cycles 591system.cpu.icache.demand_miss_latency::total 13938284992 # number of demand (read+write) miss cycles 592system.cpu.icache.overall_miss_latency::cpu.inst 13938284992 # number of overall miss cycles 593system.cpu.icache.overall_miss_latency::total 13938284992 # number of overall miss cycles 594system.cpu.icache.ReadReq_accesses::cpu.inst 8492081 # number of ReadReq accesses(hits+misses) 595system.cpu.icache.ReadReq_accesses::total 8492081 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.demand_accesses::cpu.inst 8492081 # number of demand (read+write) accesses 597system.cpu.icache.demand_accesses::total 8492081 # number of demand (read+write) accesses 598system.cpu.icache.overall_accesses::cpu.inst 8492081 # number of overall (read+write) accesses 599system.cpu.icache.overall_accesses::total 8492081 # number of overall (read+write) accesses 600system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118925 # miss rate for ReadReq accesses 601system.cpu.icache.ReadReq_miss_rate::total 0.118925 # miss rate for ReadReq accesses 602system.cpu.icache.demand_miss_rate::cpu.inst 0.118925 # miss rate for demand accesses 603system.cpu.icache.demand_miss_rate::total 0.118925 # miss rate for demand accesses 604system.cpu.icache.overall_miss_rate::cpu.inst 0.118925 # miss rate for overall accesses 605system.cpu.icache.overall_miss_rate::total 0.118925 # miss rate for overall accesses 606system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.348017 # average ReadReq miss latency 607system.cpu.icache.ReadReq_avg_miss_latency::total 13801.348017 # average ReadReq miss latency 608system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency 609system.cpu.icache.demand_avg_miss_latency::total 13801.348017 # average overall miss latency 610system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::total 13801.348017 # average overall miss latency 612system.cpu.icache.blocked_cycles::no_mshrs 8199 # number of cycles access was blocked | 947system.cpu.rob.rob_reads 1079657633 # The number of ROB reads 948system.cpu.rob.rob_writes 1655096826 # The number of ROB writes 949system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself 950system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling 951system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 952system.cpu.committedInsts 407728401 # Number of Instructions Simulated 953system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated 954system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated 955system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction 956system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads 957system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle 958system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads 959system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads 960system.cpu.int_regfile_writes 975319683 # number of integer regfile writes 961system.cpu.fp_regfile_reads 50 # number of floating regfile reads 962system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads 963system.cpu.misc_regfile_writes 401987 # number of misc regfile writes 964system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s) 965system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution 966system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution 967system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution 968system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution 969system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution 970system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution 971system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution 972system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution 973system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution 974system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes) 975system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes) 976system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes) 977system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes) 978system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes) 979system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes) 980system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes) 981system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes) 982system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes) 983system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes) 984system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes) 985system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes) 986system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks) 987system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 988system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) 989system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 990system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks) 991system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 992system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks) 993system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 994system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks) 995system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 996system.cpu.toL2Bus.respLayer3.occupancy 102839393 # Layer occupancy (ticks) 997system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 998system.cpu.icache.replacements 953322 # number of replacements 999system.cpu.icache.tagsinuse 510.127378 # Cycle average of tags in use 1000system.cpu.icache.total_refs 7473092 # Total number of references to valid blocks. 1001system.cpu.icache.sampled_refs 953834 # Sample count of references to valid blocks. 1002system.cpu.icache.avg_refs 7.834793 # Average number of references to valid blocks. 1003system.cpu.icache.warmup_cycle 147390294000 # Cycle when the warmup percentage was hit. 1004system.cpu.icache.occ_blocks::cpu.inst 510.127378 # Average occupied blocks per requestor 1005system.cpu.icache.occ_percent::cpu.inst 0.996343 # Average percentage of cache occupancy 1006system.cpu.icache.occ_percent::total 0.996343 # Average percentage of cache occupancy 1007system.cpu.icache.ReadReq_hits::cpu.inst 7473092 # number of ReadReq hits 1008system.cpu.icache.ReadReq_hits::total 7473092 # number of ReadReq hits 1009system.cpu.icache.demand_hits::cpu.inst 7473092 # number of demand (read+write) hits 1010system.cpu.icache.demand_hits::total 7473092 # number of demand (read+write) hits 1011system.cpu.icache.overall_hits::cpu.inst 7473092 # number of overall hits 1012system.cpu.icache.overall_hits::total 7473092 # number of overall hits 1013system.cpu.icache.ReadReq_misses::cpu.inst 1006614 # number of ReadReq misses 1014system.cpu.icache.ReadReq_misses::total 1006614 # number of ReadReq misses 1015system.cpu.icache.demand_misses::cpu.inst 1006614 # number of demand (read+write) misses 1016system.cpu.icache.demand_misses::total 1006614 # number of demand (read+write) misses 1017system.cpu.icache.overall_misses::cpu.inst 1006614 # number of overall misses 1018system.cpu.icache.overall_misses::total 1006614 # number of overall misses 1019system.cpu.icache.ReadReq_miss_latency::cpu.inst 14222924496 # number of ReadReq miss cycles 1020system.cpu.icache.ReadReq_miss_latency::total 14222924496 # number of ReadReq miss cycles 1021system.cpu.icache.demand_miss_latency::cpu.inst 14222924496 # number of demand (read+write) miss cycles 1022system.cpu.icache.demand_miss_latency::total 14222924496 # number of demand (read+write) miss cycles 1023system.cpu.icache.overall_miss_latency::cpu.inst 14222924496 # number of overall miss cycles 1024system.cpu.icache.overall_miss_latency::total 14222924496 # number of overall miss cycles 1025system.cpu.icache.ReadReq_accesses::cpu.inst 8479706 # number of ReadReq accesses(hits+misses) 1026system.cpu.icache.ReadReq_accesses::total 8479706 # number of ReadReq accesses(hits+misses) 1027system.cpu.icache.demand_accesses::cpu.inst 8479706 # number of demand (read+write) accesses 1028system.cpu.icache.demand_accesses::total 8479706 # number of demand (read+write) accesses 1029system.cpu.icache.overall_accesses::cpu.inst 8479706 # number of overall (read+write) accesses 1030system.cpu.icache.overall_accesses::total 8479706 # number of overall (read+write) accesses 1031system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118709 # miss rate for ReadReq accesses 1032system.cpu.icache.ReadReq_miss_rate::total 0.118709 # miss rate for ReadReq accesses 1033system.cpu.icache.demand_miss_rate::cpu.inst 0.118709 # miss rate for demand accesses 1034system.cpu.icache.demand_miss_rate::total 0.118709 # miss rate for demand accesses 1035system.cpu.icache.overall_miss_rate::cpu.inst 0.118709 # miss rate for overall accesses 1036system.cpu.icache.overall_miss_rate::total 0.118709 # miss rate for overall accesses 1037system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14129.472167 # average ReadReq miss latency 1038system.cpu.icache.ReadReq_avg_miss_latency::total 14129.472167 # average ReadReq miss latency 1039system.cpu.icache.demand_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency 1040system.cpu.icache.demand_avg_miss_latency::total 14129.472167 # average overall miss latency 1041system.cpu.icache.overall_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency 1042system.cpu.icache.overall_avg_miss_latency::total 14129.472167 # average overall miss latency 1043system.cpu.icache.blocked_cycles::no_mshrs 8172 # number of cycles access was blocked |
| 613system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1044system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 614system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked | 1045system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked |
| 615system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1046system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 616system.cpu.icache.avg_blocked_cycles::no_mshrs 40.389163 # average number of cycles each access was blocked | 1047system.cpu.icache.avg_blocked_cycles::no_mshrs 43.238095 # average number of cycles each access was blocked |
| 617system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 618system.cpu.icache.fast_writes 0 # number of fast writes performed 619system.cpu.icache.cache_copies 0 # number of cache copies performed | 1048system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1049system.cpu.icache.fast_writes 0 # number of fast writes performed 1050system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 620system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53908 # number of ReadReq MSHR hits 621system.cpu.icache.ReadReq_mshr_hits::total 53908 # number of ReadReq MSHR hits 622system.cpu.icache.demand_mshr_hits::cpu.inst 53908 # number of demand (read+write) MSHR hits 623system.cpu.icache.demand_mshr_hits::total 53908 # number of demand (read+write) MSHR hits 624system.cpu.icache.overall_mshr_hits::cpu.inst 53908 # number of overall MSHR hits 625system.cpu.icache.overall_mshr_hits::total 53908 # number of overall MSHR hits 626system.cpu.icache.ReadReq_mshr_misses::cpu.inst 956014 # number of ReadReq MSHR misses 627system.cpu.icache.ReadReq_mshr_misses::total 956014 # number of ReadReq MSHR misses 628system.cpu.icache.demand_mshr_misses::cpu.inst 956014 # number of demand (read+write) MSHR misses 629system.cpu.icache.demand_mshr_misses::total 956014 # number of demand (read+write) MSHR misses 630system.cpu.icache.overall_mshr_misses::cpu.inst 956014 # number of overall MSHR misses 631system.cpu.icache.overall_mshr_misses::total 956014 # number of overall MSHR misses 632system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11502740492 # number of ReadReq MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_miss_latency::total 11502740492 # number of ReadReq MSHR miss cycles 634system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11502740492 # number of demand (read+write) MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::total 11502740492 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11502740492 # number of overall MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::total 11502740492 # number of overall MSHR miss cycles 638system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112577 # mshr miss rate for ReadReq accesses 640system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for demand accesses 641system.cpu.icache.demand_mshr_miss_rate::total 0.112577 # mshr miss rate for demand accesses 642system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for overall accesses 643system.cpu.icache.overall_mshr_miss_rate::total 0.112577 # mshr miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.979126 # average ReadReq mshr miss latency 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.979126 # average ReadReq mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency | 1051system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52705 # number of ReadReq MSHR hits 1052system.cpu.icache.ReadReq_mshr_hits::total 52705 # number of ReadReq MSHR hits 1053system.cpu.icache.demand_mshr_hits::cpu.inst 52705 # number of demand (read+write) MSHR hits 1054system.cpu.icache.demand_mshr_hits::total 52705 # number of demand (read+write) MSHR hits 1055system.cpu.icache.overall_mshr_hits::cpu.inst 52705 # number of overall MSHR hits 1056system.cpu.icache.overall_mshr_hits::total 52705 # number of overall MSHR hits 1057system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953909 # number of ReadReq MSHR misses 1058system.cpu.icache.ReadReq_mshr_misses::total 953909 # number of ReadReq MSHR misses 1059system.cpu.icache.demand_mshr_misses::cpu.inst 953909 # number of demand (read+write) MSHR misses 1060system.cpu.icache.demand_mshr_misses::total 953909 # number of demand (read+write) MSHR misses 1061system.cpu.icache.overall_mshr_misses::cpu.inst 953909 # number of overall MSHR misses 1062system.cpu.icache.overall_mshr_misses::total 953909 # number of overall MSHR misses 1063system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11745970674 # number of ReadReq MSHR miss cycles 1064system.cpu.icache.ReadReq_mshr_miss_latency::total 11745970674 # number of ReadReq MSHR miss cycles 1065system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11745970674 # number of demand (read+write) MSHR miss cycles 1066system.cpu.icache.demand_mshr_miss_latency::total 11745970674 # number of demand (read+write) MSHR miss cycles 1067system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11745970674 # number of overall MSHR miss cycles 1068system.cpu.icache.overall_mshr_miss_latency::total 11745970674 # number of overall MSHR miss cycles 1069system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for ReadReq accesses 1070system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112493 # mshr miss rate for ReadReq accesses 1071system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for demand accesses 1072system.cpu.icache.demand_mshr_miss_rate::total 0.112493 # mshr miss rate for demand accesses 1073system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for overall accesses 1074system.cpu.icache.overall_mshr_miss_rate::total 0.112493 # mshr miss rate for overall accesses 1075system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12313.512792 # average ReadReq mshr miss latency 1076system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12313.512792 # average ReadReq mshr miss latency 1077system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency 1078system.cpu.icache.demand_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency 1079system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency 1080system.cpu.icache.overall_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency |
| 650system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1081system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 651system.cpu.itb_walker_cache.replacements 7960 # number of replacements 652system.cpu.itb_walker_cache.tagsinuse 6.326712 # Cycle average of tags in use 653system.cpu.itb_walker_cache.total_refs 20386 # Total number of references to valid blocks. 654system.cpu.itb_walker_cache.sampled_refs 7973 # Sample count of references to valid blocks. 655system.cpu.itb_walker_cache.avg_refs 2.556879 # Average number of references to valid blocks. 656system.cpu.itb_walker_cache.warmup_cycle 5107329698000 # Cycle when the warmup percentage was hit. 657system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.326712 # Average occupied blocks per requestor 658system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.395420 # Average percentage of cache occupancy 659system.cpu.itb_walker_cache.occ_percent::total 0.395420 # Average percentage of cache occupancy 660system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20403 # number of ReadReq hits 661system.cpu.itb_walker_cache.ReadReq_hits::total 20403 # number of ReadReq hits | 1082system.cpu.itb_walker_cache.replacements 7857 # number of replacements 1083system.cpu.itb_walker_cache.tagsinuse 6.317656 # Cycle average of tags in use 1084system.cpu.itb_walker_cache.total_refs 21864 # Total number of references to valid blocks. 1085system.cpu.itb_walker_cache.sampled_refs 7868 # Sample count of references to valid blocks. 1086system.cpu.itb_walker_cache.avg_refs 2.778851 # Average number of references to valid blocks. 1087system.cpu.itb_walker_cache.warmup_cycle 5104284128000 # Cycle when the warmup percentage was hit. 1088system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.317656 # Average occupied blocks per requestor 1089system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.394853 # Average percentage of cache occupancy 1090system.cpu.itb_walker_cache.occ_percent::total 0.394853 # Average percentage of cache occupancy 1091system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21875 # number of ReadReq hits 1092system.cpu.itb_walker_cache.ReadReq_hits::total 21875 # number of ReadReq hits |
| 662system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 663system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 1093system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1094system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 664system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20405 # number of demand (read+write) hits 665system.cpu.itb_walker_cache.demand_hits::total 20405 # number of demand (read+write) hits 666system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20405 # number of overall hits 667system.cpu.itb_walker_cache.overall_hits::total 20405 # number of overall hits 668system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8843 # number of ReadReq misses 669system.cpu.itb_walker_cache.ReadReq_misses::total 8843 # number of ReadReq misses 670system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8843 # number of demand (read+write) misses 671system.cpu.itb_walker_cache.demand_misses::total 8843 # number of demand (read+write) misses 672system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8843 # number of overall misses 673system.cpu.itb_walker_cache.overall_misses::total 8843 # number of overall misses 674system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 96821500 # number of ReadReq miss cycles 675system.cpu.itb_walker_cache.ReadReq_miss_latency::total 96821500 # number of ReadReq miss cycles 676system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 96821500 # number of demand (read+write) miss cycles 677system.cpu.itb_walker_cache.demand_miss_latency::total 96821500 # number of demand (read+write) miss cycles 678system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 96821500 # number of overall miss cycles 679system.cpu.itb_walker_cache.overall_miss_latency::total 96821500 # number of overall miss cycles 680system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 29246 # number of ReadReq accesses(hits+misses) 681system.cpu.itb_walker_cache.ReadReq_accesses::total 29246 # number of ReadReq accesses(hits+misses) | 1095system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21877 # number of demand (read+write) hits 1096system.cpu.itb_walker_cache.demand_hits::total 21877 # number of demand (read+write) hits 1097system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21877 # number of overall hits 1098system.cpu.itb_walker_cache.overall_hits::total 21877 # number of overall hits 1099system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8730 # number of ReadReq misses 1100system.cpu.itb_walker_cache.ReadReq_misses::total 8730 # number of ReadReq misses 1101system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8730 # number of demand (read+write) misses 1102system.cpu.itb_walker_cache.demand_misses::total 8730 # number of demand (read+write) misses 1103system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8730 # number of overall misses 1104system.cpu.itb_walker_cache.overall_misses::total 8730 # number of overall misses 1105system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 99800500 # number of ReadReq miss cycles 1106system.cpu.itb_walker_cache.ReadReq_miss_latency::total 99800500 # number of ReadReq miss cycles 1107system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 99800500 # number of demand (read+write) miss cycles 1108system.cpu.itb_walker_cache.demand_miss_latency::total 99800500 # number of demand (read+write) miss cycles 1109system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 99800500 # number of overall miss cycles 1110system.cpu.itb_walker_cache.overall_miss_latency::total 99800500 # number of overall miss cycles 1111system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30605 # number of ReadReq accesses(hits+misses) 1112system.cpu.itb_walker_cache.ReadReq_accesses::total 30605 # number of ReadReq accesses(hits+misses) |
| 682system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 683system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 1113system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1114system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 684system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29248 # number of demand (read+write) accesses 685system.cpu.itb_walker_cache.demand_accesses::total 29248 # number of demand (read+write) accesses 686system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29248 # number of overall (read+write) accesses 687system.cpu.itb_walker_cache.overall_accesses::total 29248 # number of overall (read+write) accesses 688system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.302366 # miss rate for ReadReq accesses 689system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.302366 # miss rate for ReadReq accesses 690system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.302345 # miss rate for demand accesses 691system.cpu.itb_walker_cache.demand_miss_rate::total 0.302345 # miss rate for demand accesses 692system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.302345 # miss rate for overall accesses 693system.cpu.itb_walker_cache.overall_miss_rate::total 0.302345 # miss rate for overall accesses 694system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10948.942667 # average ReadReq miss latency 695system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10948.942667 # average ReadReq miss latency 696system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency 697system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10948.942667 # average overall miss latency 698system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency 699system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10948.942667 # average overall miss latency | 1115system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30607 # number of demand (read+write) accesses 1116system.cpu.itb_walker_cache.demand_accesses::total 30607 # number of demand (read+write) accesses 1117system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30607 # number of overall (read+write) accesses 1118system.cpu.itb_walker_cache.overall_accesses::total 30607 # number of overall (read+write) accesses 1119system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285248 # miss rate for ReadReq accesses 1120system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285248 # miss rate for ReadReq accesses 1121system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285229 # miss rate for demand accesses 1122system.cpu.itb_walker_cache.demand_miss_rate::total 0.285229 # miss rate for demand accesses 1123system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285229 # miss rate for overall accesses 1124system.cpu.itb_walker_cache.overall_miss_rate::total 0.285229 # miss rate for overall accesses 1125system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11431.901489 # average ReadReq miss latency 1126system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11431.901489 # average ReadReq miss latency 1127system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency 1128system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11431.901489 # average overall miss latency 1129system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency 1130system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11431.901489 # average overall miss latency |
| 700system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 701system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 702system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 703system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 704system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 705system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 706system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 707system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 1131system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1132system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1133system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1134system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1135system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1136system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1137system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1138system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 708system.cpu.itb_walker_cache.writebacks::writebacks 1394 # number of writebacks 709system.cpu.itb_walker_cache.writebacks::total 1394 # number of writebacks 710system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8843 # number of ReadReq MSHR misses 711system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses 712system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8843 # number of demand (read+write) MSHR misses 713system.cpu.itb_walker_cache.demand_mshr_misses::total 8843 # number of demand (read+write) MSHR misses 714system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8843 # number of overall MSHR misses 715system.cpu.itb_walker_cache.overall_mshr_misses::total 8843 # number of overall MSHR misses 716system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79135500 # number of ReadReq MSHR miss cycles 717system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 79135500 # number of ReadReq MSHR miss cycles 718system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 79135500 # number of demand (read+write) MSHR miss cycles 719system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 79135500 # number of demand (read+write) MSHR miss cycles 720system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 79135500 # number of overall MSHR miss cycles 721system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 79135500 # number of overall MSHR miss cycles 722system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.302366 # mshr miss rate for ReadReq accesses 723system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.302366 # mshr miss rate for ReadReq accesses 724system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for demand accesses 725system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.302345 # mshr miss rate for demand accesses 726system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for overall accesses 727system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.302345 # mshr miss rate for overall accesses 728system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average ReadReq mshr miss latency 729system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8948.942667 # average ReadReq mshr miss latency 730system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency 731system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency 732system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency 733system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency | 1139system.cpu.itb_walker_cache.writebacks::writebacks 1569 # number of writebacks 1140system.cpu.itb_walker_cache.writebacks::total 1569 # number of writebacks 1141system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8730 # number of ReadReq MSHR misses 1142system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8730 # number of ReadReq MSHR misses 1143system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8730 # number of demand (read+write) MSHR misses 1144system.cpu.itb_walker_cache.demand_mshr_misses::total 8730 # number of demand (read+write) MSHR misses 1145system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8730 # number of overall MSHR misses 1146system.cpu.itb_walker_cache.overall_mshr_misses::total 8730 # number of overall MSHR misses 1147system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 82333015 # number of ReadReq MSHR miss cycles 1148system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 82333015 # number of ReadReq MSHR miss cycles 1149system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 82333015 # number of demand (read+write) MSHR miss cycles 1150system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 82333015 # number of demand (read+write) MSHR miss cycles 1151system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 82333015 # number of overall MSHR miss cycles 1152system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 82333015 # number of overall MSHR miss cycles 1153system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285248 # mshr miss rate for ReadReq accesses 1154system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285248 # mshr miss rate for ReadReq accesses 1155system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for demand accesses 1156system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses 1157system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for overall accesses 1158system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses 1159system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average ReadReq mshr miss latency 1160system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9431.044101 # average ReadReq mshr miss latency 1161system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency 1162system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency 1163system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency 1164system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency |
| 734system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1165system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 735system.cpu.dtb_walker_cache.replacements 67560 # number of replacements 736system.cpu.dtb_walker_cache.tagsinuse 14.837353 # Cycle average of tags in use 737system.cpu.dtb_walker_cache.total_refs 92239 # Total number of references to valid blocks. 738system.cpu.dtb_walker_cache.sampled_refs 67575 # Sample count of references to valid blocks. 739system.cpu.dtb_walker_cache.avg_refs 1.364987 # Average number of references to valid blocks. 740system.cpu.dtb_walker_cache.warmup_cycle 5100574572500 # Cycle when the warmup percentage was hit. 741system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.837353 # Average occupied blocks per requestor 742system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.927335 # Average percentage of cache occupancy 743system.cpu.dtb_walker_cache.occ_percent::total 0.927335 # Average percentage of cache occupancy 744system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92240 # number of ReadReq hits 745system.cpu.dtb_walker_cache.ReadReq_hits::total 92240 # number of ReadReq hits 746system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92240 # number of demand (read+write) hits 747system.cpu.dtb_walker_cache.demand_hits::total 92240 # number of demand (read+write) hits 748system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92240 # number of overall hits 749system.cpu.dtb_walker_cache.overall_hits::total 92240 # number of overall hits 750system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68644 # number of ReadReq misses 751system.cpu.dtb_walker_cache.ReadReq_misses::total 68644 # number of ReadReq misses 752system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68644 # number of demand (read+write) misses 753system.cpu.dtb_walker_cache.demand_misses::total 68644 # number of demand (read+write) misses 754system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68644 # number of overall misses 755system.cpu.dtb_walker_cache.overall_misses::total 68644 # number of overall misses 756system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 852599000 # number of ReadReq miss cycles 757system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 852599000 # number of ReadReq miss cycles 758system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 852599000 # number of demand (read+write) miss cycles 759system.cpu.dtb_walker_cache.demand_miss_latency::total 852599000 # number of demand (read+write) miss cycles 760system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 852599000 # number of overall miss cycles 761system.cpu.dtb_walker_cache.overall_miss_latency::total 852599000 # number of overall miss cycles 762system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160884 # number of ReadReq accesses(hits+misses) 763system.cpu.dtb_walker_cache.ReadReq_accesses::total 160884 # number of ReadReq accesses(hits+misses) 764system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160884 # number of demand (read+write) accesses 765system.cpu.dtb_walker_cache.demand_accesses::total 160884 # number of demand (read+write) accesses 766system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160884 # number of overall (read+write) accesses 767system.cpu.dtb_walker_cache.overall_accesses::total 160884 # number of overall (read+write) accesses 768system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426668 # miss rate for ReadReq accesses 769system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426668 # miss rate for ReadReq accesses 770system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426668 # miss rate for demand accesses 771system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426668 # miss rate for demand accesses 772system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426668 # miss rate for overall accesses 773system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426668 # miss rate for overall accesses 774system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12420.590292 # average ReadReq miss latency 775system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12420.590292 # average ReadReq miss latency 776system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency 777system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12420.590292 # average overall miss latency 778system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency 779system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12420.590292 # average overall miss latency | 1166system.cpu.dtb_walker_cache.replacements 67431 # number of replacements 1167system.cpu.dtb_walker_cache.tagsinuse 14.830291 # Cycle average of tags in use 1168system.cpu.dtb_walker_cache.total_refs 90986 # Total number of references to valid blocks. 1169system.cpu.dtb_walker_cache.sampled_refs 67447 # Sample count of references to valid blocks. 1170system.cpu.dtb_walker_cache.avg_refs 1.349000 # Average number of references to valid blocks. 1171system.cpu.dtb_walker_cache.warmup_cycle 4994048518000 # Cycle when the warmup percentage was hit. 1172system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.830291 # Average occupied blocks per requestor 1173system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.926893 # Average percentage of cache occupancy 1174system.cpu.dtb_walker_cache.occ_percent::total 0.926893 # Average percentage of cache occupancy 1175system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90986 # number of ReadReq hits 1176system.cpu.dtb_walker_cache.ReadReq_hits::total 90986 # number of ReadReq hits 1177system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90986 # number of demand (read+write) hits 1178system.cpu.dtb_walker_cache.demand_hits::total 90986 # number of demand (read+write) hits 1179system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90986 # number of overall hits 1180system.cpu.dtb_walker_cache.overall_hits::total 90986 # number of overall hits 1181system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68526 # number of ReadReq misses 1182system.cpu.dtb_walker_cache.ReadReq_misses::total 68526 # number of ReadReq misses 1183system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68526 # number of demand (read+write) misses 1184system.cpu.dtb_walker_cache.demand_misses::total 68526 # number of demand (read+write) misses 1185system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68526 # number of overall misses 1186system.cpu.dtb_walker_cache.overall_misses::total 68526 # number of overall misses 1187system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854232500 # number of ReadReq miss cycles 1188system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854232500 # number of ReadReq miss cycles 1189system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854232500 # number of demand (read+write) miss cycles 1190system.cpu.dtb_walker_cache.demand_miss_latency::total 854232500 # number of demand (read+write) miss cycles 1191system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854232500 # number of overall miss cycles 1192system.cpu.dtb_walker_cache.overall_miss_latency::total 854232500 # number of overall miss cycles 1193system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 159512 # number of ReadReq accesses(hits+misses) 1194system.cpu.dtb_walker_cache.ReadReq_accesses::total 159512 # number of ReadReq accesses(hits+misses) 1195system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 159512 # number of demand (read+write) accesses 1196system.cpu.dtb_walker_cache.demand_accesses::total 159512 # number of demand (read+write) accesses 1197system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 159512 # number of overall (read+write) accesses 1198system.cpu.dtb_walker_cache.overall_accesses::total 159512 # number of overall (read+write) accesses 1199system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429598 # miss rate for ReadReq accesses 1200system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429598 # miss rate for ReadReq accesses 1201system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429598 # miss rate for demand accesses 1202system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429598 # miss rate for demand accesses 1203system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429598 # miss rate for overall accesses 1204system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429598 # miss rate for overall accesses 1205system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.815895 # average ReadReq miss latency 1206system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.815895 # average ReadReq miss latency 1207system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency 1208system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.815895 # average overall miss latency 1209system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency 1210system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.815895 # average overall miss latency |
| 780system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 781system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 783system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 785system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 787system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 1211system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1212system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1213system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1214system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1215system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1216system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1217system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1218system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 788system.cpu.dtb_walker_cache.writebacks::writebacks 19876 # number of writebacks 789system.cpu.dtb_walker_cache.writebacks::total 19876 # number of writebacks 790system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68644 # number of ReadReq MSHR misses 791system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68644 # number of ReadReq MSHR misses 792system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68644 # number of demand (read+write) MSHR misses 793system.cpu.dtb_walker_cache.demand_mshr_misses::total 68644 # number of demand (read+write) MSHR misses 794system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68644 # number of overall MSHR misses 795system.cpu.dtb_walker_cache.overall_mshr_misses::total 68644 # number of overall MSHR misses 796system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 715311000 # number of ReadReq MSHR miss cycles 797system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 715311000 # number of ReadReq MSHR miss cycles 798system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 715311000 # number of demand (read+write) MSHR miss cycles 799system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 715311000 # number of demand (read+write) MSHR miss cycles 800system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 715311000 # number of overall MSHR miss cycles 801system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 715311000 # number of overall MSHR miss cycles 802system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426668 # mshr miss rate for ReadReq accesses 804system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for demand accesses 805system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426668 # mshr miss rate for demand accesses 806system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for overall accesses 807system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426668 # mshr miss rate for overall accesses 808system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average ReadReq mshr miss latency 809system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10420.590292 # average ReadReq mshr miss latency 810system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency 811system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency 812system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency 813system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency | 1219system.cpu.dtb_walker_cache.writebacks::writebacks 18479 # number of writebacks 1220system.cpu.dtb_walker_cache.writebacks::total 18479 # number of writebacks 1221system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68526 # number of ReadReq MSHR misses 1222system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68526 # number of ReadReq MSHR misses 1223system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68526 # number of demand (read+write) MSHR misses 1224system.cpu.dtb_walker_cache.demand_mshr_misses::total 68526 # number of demand (read+write) MSHR misses 1225system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68526 # number of overall MSHR misses 1226system.cpu.dtb_walker_cache.overall_mshr_misses::total 68526 # number of overall MSHR misses 1227system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 717130107 # number of ReadReq MSHR miss cycles 1228system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 717130107 # number of ReadReq MSHR miss cycles 1229system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 717130107 # number of demand (read+write) MSHR miss cycles 1230system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 717130107 # number of demand (read+write) MSHR miss cycles 1231system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 717130107 # number of overall MSHR miss cycles 1232system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 717130107 # number of overall MSHR miss cycles 1233system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for ReadReq accesses 1234system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429598 # mshr miss rate for ReadReq accesses 1235system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for demand accesses 1236system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429598 # mshr miss rate for demand accesses 1237system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for overall accesses 1238system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429598 # mshr miss rate for overall accesses 1239system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average ReadReq mshr miss latency 1240system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.080510 # average ReadReq mshr miss latency 1241system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency 1242system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency 1243system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency 1244system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency |
| 814system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1245system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 815system.cpu.dcache.replacements 1655094 # number of replacements 816system.cpu.dcache.tagsinuse 511.995445 # Cycle average of tags in use 817system.cpu.dcache.total_refs 19021390 # Total number of references to valid blocks. 818system.cpu.dcache.sampled_refs 1655606 # Sample count of references to valid blocks. 819system.cpu.dcache.avg_refs 11.489080 # Average number of references to valid blocks. 820system.cpu.dcache.warmup_cycle 27980000 # Cycle when the warmup percentage was hit. 821system.cpu.dcache.occ_blocks::cpu.data 511.995445 # Average occupied blocks per requestor 822system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 823system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy 824system.cpu.dcache.ReadReq_hits::cpu.data 10917270 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 10917270 # number of ReadReq hits 826system.cpu.dcache.WriteReq_hits::cpu.data 8101435 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 8101435 # number of WriteReq hits 828system.cpu.dcache.demand_hits::cpu.data 19018705 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 19018705 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 19018705 # number of overall hits 831system.cpu.dcache.overall_hits::total 19018705 # number of overall hits 832system.cpu.dcache.ReadReq_misses::cpu.data 2239579 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2239579 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 315092 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 315092 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2554671 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2554671 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2554671 # number of overall misses 839system.cpu.dcache.overall_misses::total 2554671 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 31946998000 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 31946998000 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 9622210995 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 9622210995 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 41569208995 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 41569208995 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 41569208995 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 41569208995 # number of overall miss cycles 848system.cpu.dcache.ReadReq_accesses::cpu.data 13156849 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 13156849 # number of ReadReq accesses(hits+misses) 850system.cpu.dcache.WriteReq_accesses::cpu.data 8416527 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 8416527 # number of WriteReq accesses(hits+misses) 852system.cpu.dcache.demand_accesses::cpu.data 21573376 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 21573376 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 21573376 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 21573376 # number of overall (read+write) accesses 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170222 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.170222 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037437 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.037437 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.118418 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.118418 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.118418 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.118418 # miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14264.733684 # average ReadReq miss latency 865system.cpu.dcache.ReadReq_avg_miss_latency::total 14264.733684 # average ReadReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30537.782600 # average WriteReq miss latency 867system.cpu.dcache.WriteReq_avg_miss_latency::total 30537.782600 # average WriteReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 16271.844396 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 16271.844396 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 387071 # number of cycles access was blocked | 1246system.cpu.dcache.replacements 1656381 # number of replacements 1247system.cpu.dcache.tagsinuse 511.996762 # Cycle average of tags in use 1248system.cpu.dcache.total_refs 18981789 # Total number of references to valid blocks. 1249system.cpu.dcache.sampled_refs 1656893 # Sample count of references to valid blocks. 1250system.cpu.dcache.avg_refs 11.456255 # Average number of references to valid blocks. 1251system.cpu.dcache.warmup_cycle 37864000 # Cycle when the warmup percentage was hit. 1252system.cpu.dcache.occ_blocks::cpu.data 511.996762 # Average occupied blocks per requestor 1253system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 1254system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy 1255system.cpu.dcache.ReadReq_hits::cpu.data 10887156 # number of ReadReq hits 1256system.cpu.dcache.ReadReq_hits::total 10887156 # number of ReadReq hits 1257system.cpu.dcache.WriteReq_hits::cpu.data 8091896 # number of WriteReq hits 1258system.cpu.dcache.WriteReq_hits::total 8091896 # number of WriteReq hits 1259system.cpu.dcache.demand_hits::cpu.data 18979052 # number of demand (read+write) hits 1260system.cpu.dcache.demand_hits::total 18979052 # number of demand (read+write) hits 1261system.cpu.dcache.overall_hits::cpu.data 18979052 # number of overall hits 1262system.cpu.dcache.overall_hits::total 18979052 # number of overall hits 1263system.cpu.dcache.ReadReq_misses::cpu.data 2237799 # number of ReadReq misses 1264system.cpu.dcache.ReadReq_misses::total 2237799 # number of ReadReq misses 1265system.cpu.dcache.WriteReq_misses::cpu.data 315625 # number of WriteReq misses 1266system.cpu.dcache.WriteReq_misses::total 315625 # number of WriteReq misses 1267system.cpu.dcache.demand_misses::cpu.data 2553424 # number of demand (read+write) misses 1268system.cpu.dcache.demand_misses::total 2553424 # number of demand (read+write) misses 1269system.cpu.dcache.overall_misses::cpu.data 2553424 # number of overall misses 1270system.cpu.dcache.overall_misses::total 2553424 # number of overall misses 1271system.cpu.dcache.ReadReq_miss_latency::cpu.data 33108471000 # number of ReadReq miss cycles 1272system.cpu.dcache.ReadReq_miss_latency::total 33108471000 # number of ReadReq miss cycles 1273system.cpu.dcache.WriteReq_miss_latency::cpu.data 12021128996 # number of WriteReq miss cycles 1274system.cpu.dcache.WriteReq_miss_latency::total 12021128996 # number of WriteReq miss cycles 1275system.cpu.dcache.demand_miss_latency::cpu.data 45129599996 # number of demand (read+write) miss cycles 1276system.cpu.dcache.demand_miss_latency::total 45129599996 # number of demand (read+write) miss cycles 1277system.cpu.dcache.overall_miss_latency::cpu.data 45129599996 # number of overall miss cycles 1278system.cpu.dcache.overall_miss_latency::total 45129599996 # number of overall miss cycles 1279system.cpu.dcache.ReadReq_accesses::cpu.data 13124955 # number of ReadReq accesses(hits+misses) 1280system.cpu.dcache.ReadReq_accesses::total 13124955 # number of ReadReq accesses(hits+misses) 1281system.cpu.dcache.WriteReq_accesses::cpu.data 8407521 # number of WriteReq accesses(hits+misses) 1282system.cpu.dcache.WriteReq_accesses::total 8407521 # number of WriteReq accesses(hits+misses) 1283system.cpu.dcache.demand_accesses::cpu.data 21532476 # number of demand (read+write) accesses 1284system.cpu.dcache.demand_accesses::total 21532476 # number of demand (read+write) accesses 1285system.cpu.dcache.overall_accesses::cpu.data 21532476 # number of overall (read+write) accesses 1286system.cpu.dcache.overall_accesses::total 21532476 # number of overall (read+write) accesses 1287system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170500 # miss rate for ReadReq accesses 1288system.cpu.dcache.ReadReq_miss_rate::total 0.170500 # miss rate for ReadReq accesses 1289system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037541 # miss rate for WriteReq accesses 1290system.cpu.dcache.WriteReq_miss_rate::total 0.037541 # miss rate for WriteReq accesses 1291system.cpu.dcache.demand_miss_rate::cpu.data 0.118585 # miss rate for demand accesses 1292system.cpu.dcache.demand_miss_rate::total 0.118585 # miss rate for demand accesses 1293system.cpu.dcache.overall_miss_rate::cpu.data 0.118585 # miss rate for overall accesses 1294system.cpu.dcache.overall_miss_rate::total 0.118585 # miss rate for overall accesses 1295system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14795.104922 # average ReadReq miss latency 1296system.cpu.dcache.ReadReq_avg_miss_latency::total 14795.104922 # average ReadReq miss latency 1297system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38086.745334 # average WriteReq miss latency 1298system.cpu.dcache.WriteReq_avg_miss_latency::total 38086.745334 # average WriteReq miss latency 1299system.cpu.dcache.demand_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency 1300system.cpu.dcache.demand_avg_miss_latency::total 17674.150472 # average overall miss latency 1301system.cpu.dcache.overall_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency 1302system.cpu.dcache.overall_avg_miss_latency::total 17674.150472 # average overall miss latency 1303system.cpu.dcache.blocked_cycles::no_mshrs 405217 # number of cycles access was blocked |
| 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1304system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 874system.cpu.dcache.blocked::no_mshrs 42390 # number of cycles access was blocked | 1305system.cpu.dcache.blocked::no_mshrs 42719 # number of cycles access was blocked |
| 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1306system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.131187 # average number of cycles each access was blocked | 1307system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.485639 # average number of cycles each access was blocked |
| 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1308system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1309system.cpu.dcache.fast_writes 0 # number of fast writes performed 1310system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 880system.cpu.dcache.writebacks::writebacks 1557214 # number of writebacks 881system.cpu.dcache.writebacks::total 1557214 # number of writebacks 882system.cpu.dcache.ReadReq_mshr_hits::cpu.data 870911 # number of ReadReq MSHR hits 883system.cpu.dcache.ReadReq_mshr_hits::total 870911 # number of ReadReq MSHR hits 884system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25892 # number of WriteReq MSHR hits 885system.cpu.dcache.WriteReq_mshr_hits::total 25892 # number of WriteReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 896803 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 896803 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 896803 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 896803 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1368668 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 1368668 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289200 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 289200 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 1657868 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 1657868 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 1657868 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 1657868 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17401159000 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 17401159000 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794383495 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794383495 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26195542495 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 26195542495 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26195542495 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 26195542495 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349101500 # number of ReadReq MSHR uncacheable cycles 907system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349101500 # number of ReadReq MSHR uncacheable cycles 908system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2522345500 # number of WriteReq MSHR uncacheable cycles 909system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2522345500 # number of WriteReq MSHR uncacheable cycles 910system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99871447000 # number of overall MSHR uncacheable cycles 911system.cpu.dcache.overall_mshr_uncacheable_latency::total 99871447000 # number of overall MSHR uncacheable cycles 912system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104027 # mshr miss rate for ReadReq accesses 913system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104027 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034361 # mshr miss rate for WriteReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034361 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076848 # mshr miss rate for demand accesses 917system.cpu.dcache.demand_mshr_miss_rate::total 0.076848 # mshr miss rate for demand accesses 918system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076848 # mshr miss rate for overall accesses 919system.cpu.dcache.overall_mshr_miss_rate::total 0.076848 # mshr miss rate for overall accesses 920system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12713.937200 # average ReadReq mshr miss latency 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12713.937200 # average ReadReq mshr miss latency 922system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30409.348185 # average WriteReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30409.348185 # average WriteReq mshr miss latency 924system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.740768 # average overall mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.740768 # average overall mshr miss latency 926system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.740768 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.740768 # average overall mshr miss latency | 1311system.cpu.dcache.writebacks::writebacks 1558312 # number of writebacks 1312system.cpu.dcache.writebacks::total 1558312 # number of writebacks 1313system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868331 # number of ReadReq MSHR hits 1314system.cpu.dcache.ReadReq_mshr_hits::total 868331 # number of ReadReq MSHR hits 1315system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25900 # number of WriteReq MSHR hits 1316system.cpu.dcache.WriteReq_mshr_hits::total 25900 # number of WriteReq MSHR hits 1317system.cpu.dcache.demand_mshr_hits::cpu.data 894231 # number of demand (read+write) MSHR hits 1318system.cpu.dcache.demand_mshr_hits::total 894231 # number of demand (read+write) MSHR hits 1319system.cpu.dcache.overall_mshr_hits::cpu.data 894231 # number of overall MSHR hits 1320system.cpu.dcache.overall_mshr_hits::total 894231 # number of overall MSHR hits 1321system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369468 # number of ReadReq MSHR misses 1322system.cpu.dcache.ReadReq_mshr_misses::total 1369468 # number of ReadReq MSHR misses 1323system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289725 # number of WriteReq MSHR misses 1324system.cpu.dcache.WriteReq_mshr_misses::total 289725 # number of WriteReq MSHR misses 1325system.cpu.dcache.demand_mshr_misses::cpu.data 1659193 # number of demand (read+write) MSHR misses 1326system.cpu.dcache.demand_mshr_misses::total 1659193 # number of demand (read+write) MSHR misses 1327system.cpu.dcache.overall_mshr_misses::cpu.data 1659193 # number of overall MSHR misses 1328system.cpu.dcache.overall_mshr_misses::total 1659193 # number of overall MSHR misses 1329system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17883109030 # number of ReadReq MSHR miss cycles 1330system.cpu.dcache.ReadReq_mshr_miss_latency::total 17883109030 # number of ReadReq MSHR miss cycles 1331system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11189452001 # number of WriteReq MSHR miss cycles 1332system.cpu.dcache.WriteReq_mshr_miss_latency::total 11189452001 # number of WriteReq MSHR miss cycles 1333system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29072561031 # number of demand (read+write) MSHR miss cycles 1334system.cpu.dcache.demand_mshr_miss_latency::total 29072561031 # number of demand (read+write) MSHR miss cycles 1335system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29072561031 # number of overall MSHR miss cycles 1336system.cpu.dcache.overall_mshr_miss_latency::total 29072561031 # number of overall MSHR miss cycles 1337system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349104500 # number of ReadReq MSHR uncacheable cycles 1338system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349104500 # number of ReadReq MSHR uncacheable cycles 1339system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521383000 # number of WriteReq MSHR uncacheable cycles 1340system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521383000 # number of WriteReq MSHR uncacheable cycles 1341system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99870487500 # number of overall MSHR uncacheable cycles 1342system.cpu.dcache.overall_mshr_uncacheable_latency::total 99870487500 # number of overall MSHR uncacheable cycles 1343system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104341 # mshr miss rate for ReadReq accesses 1344system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104341 # mshr miss rate for ReadReq accesses 1345system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034460 # mshr miss rate for WriteReq accesses 1346system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034460 # mshr miss rate for WriteReq accesses 1347system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for demand accesses 1348system.cpu.dcache.demand_mshr_miss_rate::total 0.077055 # mshr miss rate for demand accesses 1349system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for overall accesses 1350system.cpu.dcache.overall_mshr_miss_rate::total 0.077055 # mshr miss rate for overall accesses 1351system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13058.435122 # average ReadReq mshr miss latency 1352system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13058.435122 # average ReadReq mshr miss latency 1353system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38620.940551 # average WriteReq mshr miss latency 1354system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38620.940551 # average WriteReq mshr miss latency 1355system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency 1356system.cpu.dcache.demand_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency 1357system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency 1358system.cpu.dcache.overall_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency |
| 928system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 929system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 930system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 931system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 932system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 933system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1359system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1360system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1361system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1362system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1363system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1364system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1365system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 935system.cpu.l2cache.replacements 111963 # number of replacements 936system.cpu.l2cache.tagsinuse 64818.241357 # Cycle average of tags in use 937system.cpu.l2cache.total_refs 3779325 # Total number of references to valid blocks. 938system.cpu.l2cache.sampled_refs 176193 # Sample count of references to valid blocks. 939system.cpu.l2cache.avg_refs 21.449916 # Average number of references to valid blocks. | 1366system.cpu.l2cache.replacements 110887 # number of replacements 1367system.cpu.l2cache.tagsinuse 64831.056251 # Cycle average of tags in use 1368system.cpu.l2cache.total_refs 3780740 # Total number of references to valid blocks. 1369system.cpu.l2cache.sampled_refs 175156 # Sample count of references to valid blocks. 1370system.cpu.l2cache.avg_refs 21.584987 # Average number of references to valid blocks. |
| 940system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1371system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 941system.cpu.l2cache.occ_blocks::writebacks 50535.271880 # Average occupied blocks per requestor 942system.cpu.l2cache.occ_blocks::cpu.dtb.walker 14.689116 # Average occupied blocks per requestor 943system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.441967 # Average occupied blocks per requestor 944system.cpu.l2cache.occ_blocks::cpu.inst 3088.733265 # Average occupied blocks per requestor 945system.cpu.l2cache.occ_blocks::cpu.data 11179.105128 # Average occupied blocks per requestor 946system.cpu.l2cache.occ_percent::writebacks 0.771107 # Average percentage of cache occupancy 947system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000224 # Average percentage of cache occupancy | 1372system.cpu.l2cache.occ_blocks::writebacks 50733.546083 # Average occupied blocks per requestor 1373system.cpu.l2cache.occ_blocks::cpu.dtb.walker 16.870188 # Average occupied blocks per requestor 1374system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.435873 # Average occupied blocks per requestor 1375system.cpu.l2cache.occ_blocks::cpu.inst 3102.105896 # Average occupied blocks per requestor 1376system.cpu.l2cache.occ_blocks::cpu.data 10978.098210 # Average occupied blocks per requestor 1377system.cpu.l2cache.occ_percent::writebacks 0.774132 # Average percentage of cache occupancy 1378system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000257 # Average percentage of cache occupancy |
| 948system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy | 1379system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy |
| 949system.cpu.l2cache.occ_percent::cpu.inst 0.047130 # Average percentage of cache occupancy 950system.cpu.l2cache.occ_percent::cpu.data 0.170580 # Average percentage of cache occupancy 951system.cpu.l2cache.occ_percent::total 0.989048 # Average percentage of cache occupancy 952system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63019 # number of ReadReq hits 953system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6673 # number of ReadReq hits 954system.cpu.l2cache.ReadReq_hits::cpu.inst 939861 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.data 1331810 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 2341363 # number of ReadReq hits 957system.cpu.l2cache.Writeback_hits::writebacks 1578484 # number of Writeback hits 958system.cpu.l2cache.Writeback_hits::total 1578484 # number of Writeback hits 959system.cpu.l2cache.UpgradeReq_hits::cpu.data 313 # number of UpgradeReq hits 960system.cpu.l2cache.UpgradeReq_hits::total 313 # number of UpgradeReq hits 961system.cpu.l2cache.ReadExReq_hits::cpu.data 154035 # number of ReadExReq hits 962system.cpu.l2cache.ReadExReq_hits::total 154035 # number of ReadExReq hits 963system.cpu.l2cache.demand_hits::cpu.dtb.walker 63019 # number of demand (read+write) hits 964system.cpu.l2cache.demand_hits::cpu.itb.walker 6673 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.inst 939861 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1485845 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2495398 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.dtb.walker 63019 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.itb.walker 6673 # number of overall hits 970system.cpu.l2cache.overall_hits::cpu.inst 939861 # number of overall hits 971system.cpu.l2cache.overall_hits::cpu.data 1485845 # number of overall hits 972system.cpu.l2cache.overall_hits::total 2495398 # number of overall hits 973system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 58 # number of ReadReq misses | 1380system.cpu.l2cache.occ_percent::cpu.inst 0.047334 # Average percentage of cache occupancy 1381system.cpu.l2cache.occ_percent::cpu.data 0.167512 # Average percentage of cache occupancy 1382system.cpu.l2cache.occ_percent::total 0.989243 # Average percentage of cache occupancy 1383system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63592 # number of ReadReq hits 1384system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7072 # number of ReadReq hits 1385system.cpu.l2cache.ReadReq_hits::cpu.inst 937746 # number of ReadReq hits 1386system.cpu.l2cache.ReadReq_hits::cpu.data 1332853 # number of ReadReq hits 1387system.cpu.l2cache.ReadReq_hits::total 2341263 # number of ReadReq hits 1388system.cpu.l2cache.Writeback_hits::writebacks 1578360 # number of Writeback hits 1389system.cpu.l2cache.Writeback_hits::total 1578360 # number of Writeback hits 1390system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits 1391system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits 1392system.cpu.l2cache.ReadExReq_hits::cpu.data 154746 # number of ReadExReq hits 1393system.cpu.l2cache.ReadExReq_hits::total 154746 # number of ReadExReq hits 1394system.cpu.l2cache.demand_hits::cpu.dtb.walker 63592 # number of demand (read+write) hits 1395system.cpu.l2cache.demand_hits::cpu.itb.walker 7072 # number of demand (read+write) hits 1396system.cpu.l2cache.demand_hits::cpu.inst 937746 # number of demand (read+write) hits 1397system.cpu.l2cache.demand_hits::cpu.data 1487599 # number of demand (read+write) hits 1398system.cpu.l2cache.demand_hits::total 2496009 # number of demand (read+write) hits 1399system.cpu.l2cache.overall_hits::cpu.dtb.walker 63592 # number of overall hits 1400system.cpu.l2cache.overall_hits::cpu.itb.walker 7072 # number of overall hits 1401system.cpu.l2cache.overall_hits::cpu.inst 937746 # number of overall hits 1402system.cpu.l2cache.overall_hits::cpu.data 1487599 # number of overall hits 1403system.cpu.l2cache.overall_hits::total 2496009 # number of overall hits 1404system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses |
| 974system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses | 1405system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses |
| 975system.cpu.l2cache.ReadReq_misses::cpu.inst 16036 # number of ReadReq misses 976system.cpu.l2cache.ReadReq_misses::cpu.data 36136 # number of ReadReq misses 977system.cpu.l2cache.ReadReq_misses::total 52236 # number of ReadReq misses 978system.cpu.l2cache.UpgradeReq_misses::cpu.data 1469 # number of UpgradeReq misses 979system.cpu.l2cache.UpgradeReq_misses::total 1469 # number of UpgradeReq misses 980system.cpu.l2cache.ReadExReq_misses::cpu.data 133013 # number of ReadExReq misses 981system.cpu.l2cache.ReadExReq_misses::total 133013 # number of ReadExReq misses 982system.cpu.l2cache.demand_misses::cpu.dtb.walker 58 # number of demand (read+write) misses | 1406system.cpu.l2cache.ReadReq_misses::cpu.inst 16053 # number of ReadReq misses 1407system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses 1408system.cpu.l2cache.ReadReq_misses::total 51995 # number of ReadReq misses 1409system.cpu.l2cache.UpgradeReq_misses::cpu.data 1482 # number of UpgradeReq misses 1410system.cpu.l2cache.UpgradeReq_misses::total 1482 # number of UpgradeReq misses 1411system.cpu.l2cache.ReadExReq_misses::cpu.data 132789 # number of ReadExReq misses 1412system.cpu.l2cache.ReadExReq_misses::total 132789 # number of ReadExReq misses 1413system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses |
| 983system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses | 1414system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses |
| 984system.cpu.l2cache.demand_misses::cpu.inst 16036 # number of demand (read+write) misses 985system.cpu.l2cache.demand_misses::cpu.data 169149 # number of demand (read+write) misses 986system.cpu.l2cache.demand_misses::total 185249 # number of demand (read+write) misses 987system.cpu.l2cache.overall_misses::cpu.dtb.walker 58 # number of overall misses | 1415system.cpu.l2cache.demand_misses::cpu.inst 16053 # number of demand (read+write) misses 1416system.cpu.l2cache.demand_misses::cpu.data 168664 # number of demand (read+write) misses 1417system.cpu.l2cache.demand_misses::total 184784 # number of demand (read+write) misses 1418system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses |
| 988system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses | 1419system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses |
| 989system.cpu.l2cache.overall_misses::cpu.inst 16036 # number of overall misses 990system.cpu.l2cache.overall_misses::cpu.data 169149 # number of overall misses 991system.cpu.l2cache.overall_misses::total 185249 # number of overall misses 992system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4739500 # number of ReadReq miss cycles 993system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 386000 # number of ReadReq miss cycles 994system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1102660000 # number of ReadReq miss cycles 995system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2500024999 # number of ReadReq miss cycles 996system.cpu.l2cache.ReadReq_miss_latency::total 3607810499 # number of ReadReq miss cycles 997system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 18004500 # number of UpgradeReq miss cycles 998system.cpu.l2cache.UpgradeReq_miss_latency::total 18004500 # number of UpgradeReq miss cycles 999system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6917223500 # number of ReadExReq miss cycles 1000system.cpu.l2cache.ReadExReq_miss_latency::total 6917223500 # number of ReadExReq miss cycles 1001system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4739500 # number of demand (read+write) miss cycles 1002system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 386000 # number of demand (read+write) miss cycles 1003system.cpu.l2cache.demand_miss_latency::cpu.inst 1102660000 # number of demand (read+write) miss cycles 1004system.cpu.l2cache.demand_miss_latency::cpu.data 9417248499 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.demand_miss_latency::total 10525033999 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4739500 # number of overall miss cycles 1007system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 386000 # number of overall miss cycles 1008system.cpu.l2cache.overall_miss_latency::cpu.inst 1102660000 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.data 9417248499 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::total 10525033999 # number of overall miss cycles 1011system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63077 # number of ReadReq accesses(hits+misses) 1012system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 6679 # number of ReadReq accesses(hits+misses) 1013system.cpu.l2cache.ReadReq_accesses::cpu.inst 955897 # number of ReadReq accesses(hits+misses) 1014system.cpu.l2cache.ReadReq_accesses::cpu.data 1367946 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::total 2393599 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.Writeback_accesses::writebacks 1578484 # number of Writeback accesses(hits+misses) 1017system.cpu.l2cache.Writeback_accesses::total 1578484 # number of Writeback accesses(hits+misses) 1018system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1782 # number of UpgradeReq accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::total 1782 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.ReadExReq_accesses::cpu.data 287048 # number of ReadExReq accesses(hits+misses) 1021system.cpu.l2cache.ReadExReq_accesses::total 287048 # number of ReadExReq accesses(hits+misses) 1022system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63077 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::cpu.itb.walker 6679 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.inst 955897 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 1654994 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 2680647 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63077 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.itb.walker 6679 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.inst 955897 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::cpu.data 1654994 # number of overall (read+write) accesses 1031system.cpu.l2cache.overall_accesses::total 2680647 # number of overall (read+write) accesses 1032system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses 1033system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000898 # miss rate for ReadReq accesses 1034system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016776 # miss rate for ReadReq accesses 1035system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026416 # miss rate for ReadReq accesses 1036system.cpu.l2cache.ReadReq_miss_rate::total 0.021823 # miss rate for ReadReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.824355 # miss rate for UpgradeReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::total 0.824355 # miss rate for UpgradeReq accesses 1039system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463382 # miss rate for ReadExReq accesses 1040system.cpu.l2cache.ReadExReq_miss_rate::total 0.463382 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # 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| 1096system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses | 1530system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses |
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number of overall MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327785169 # number of overall MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::total 8235215486 # number of overall MSHR miss cycles 1124system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236811500 # number of ReadReq MSHR uncacheable cycles 1125system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236811500 # number of ReadReq MSHR uncacheable cycles 1126system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357396500 # number of WriteReq MSHR uncacheable cycles 1127system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357396500 # number of WriteReq MSHR uncacheable cycles 1128system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91594208000 # number of overall MSHR uncacheable cycles 1129system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91594208000 # number of overall MSHR uncacheable cycles 1130system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for ReadReq accesses 1131system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for ReadReq accesses 1132system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for ReadReq accesses 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026416 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021823 # mshr miss rate for ReadReq accesses 1135system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.824355 # mshr miss rate for UpgradeReq accesses 1136system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.824355 # mshr miss rate for UpgradeReq accesses 1137system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463382 # mshr miss rate for ReadExReq accesses 1138system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463382 # mshr miss rate for ReadExReq accesses 1139system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for demand accesses 1140system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for demand accesses 1141system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for demand accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102205 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::total 0.069106 # mshr miss rate for demand accesses 1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for overall accesses 1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for overall accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for overall accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102205 # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::total 0.069106 # mshr miss rate for overall accesses 1149system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average ReadReq mshr miss latency 1150system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average ReadReq mshr miss latency 1151system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56320.783037 # average ReadReq mshr miss latency 1152system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56752.997758 # average ReadReq mshr miss latency 1153system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56633.610491 # average ReadReq mshr miss latency 1154system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10705.205582 # average UpgradeReq mshr miss latency 1155system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10705.205582 # average UpgradeReq mshr miss latency 1156system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39672.504507 # average ReadExReq mshr miss latency 1157system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39672.504507 # average ReadExReq mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency | 1536system.cpu.l2cache.overall_mshr_misses::cpu.inst 16050 # number of overall MSHR misses 1537system.cpu.l2cache.overall_mshr_misses::cpu.data 168662 # number of overall MSHR misses 1538system.cpu.l2cache.overall_mshr_misses::total 184779 # number of overall MSHR misses 1539system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5260750 # number of ReadReq MSHR miss cycles 1540system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 430000 # number of ReadReq MSHR miss cycles 1541system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1193323263 # number of ReadReq MSHR miss cycles 1542system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545977303 # number of ReadReq MSHR miss cycles 1543system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3744991316 # number of ReadReq MSHR miss cycles 1544system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15894959 # number of UpgradeReq MSHR miss cycles 1545system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15894959 # number of UpgradeReq MSHR miss cycles 1546system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7671814321 # number of ReadExReq MSHR miss cycles 1547system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7671814321 # number of ReadExReq MSHR miss cycles 1548system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5260750 # number of demand (read+write) MSHR miss cycles 1549system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) MSHR miss cycles 1550system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1193323263 # number of demand (read+write) MSHR miss cycles 1551system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10217791624 # number of demand (read+write) MSHR miss cycles 1552system.cpu.l2cache.demand_mshr_miss_latency::total 11416805637 # number of demand (read+write) MSHR miss cycles 1553system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5260750 # number of overall MSHR miss cycles 1554system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles 1555system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1193323263 # number of overall MSHR miss cycles 1556system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10217791624 # number of overall MSHR miss cycles 1557system.cpu.l2cache.overall_mshr_miss_latency::total 11416805637 # number of overall MSHR miss cycles 1558system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236814500 # number of ReadReq MSHR uncacheable cycles 1559system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236814500 # number of ReadReq MSHR uncacheable cycles 1560system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2356578000 # number of WriteReq MSHR uncacheable cycles 1561system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2356578000 # number of WriteReq MSHR uncacheable cycles 1562system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593392500 # number of overall MSHR uncacheable cycles 1563system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593392500 # number of overall MSHR uncacheable cycles 1564system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for ReadReq accesses 1565system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for ReadReq accesses 1566system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for ReadReq accesses 1567system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026209 # mshr miss rate for ReadReq accesses 1568system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses 1569system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823791 # mshr miss rate for UpgradeReq accesses 1570system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823791 # mshr miss rate for UpgradeReq accesses 1571system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461819 # mshr miss rate for ReadExReq accesses 1572system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461819 # mshr miss rate for ReadExReq accesses 1573system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for demand accesses 1574system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for demand accesses 1575system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for demand accesses 1576system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for demand accesses 1577system.cpu.l2cache.demand_mshr_miss_rate::total 0.068927 # mshr miss rate for demand accesses 1578system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for overall accesses 1579system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for overall accesses 1580system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for overall accesses 1581system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for overall accesses 1582system.cpu.l2cache.overall_mshr_miss_rate::total 0.068927 # mshr miss rate for overall accesses 1583system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average ReadReq mshr miss latency 1584system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency 1585system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74350.359065 # average ReadReq mshr miss latency 1586system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70971.965071 # average ReadReq mshr miss latency 1587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72032.916253 # average ReadReq mshr miss latency 1588system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10725.343455 # average UpgradeReq mshr miss latency 1589system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10725.343455 # average UpgradeReq mshr miss latency 1590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57774.471688 # average ReadExReq mshr miss latency 1591system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57774.471688 # average ReadExReq mshr miss latency 1592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency 1593system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency 1594system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency 1595system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency 1596system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency 1597system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency 1598system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency 1599system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency 1600system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency 1601system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency |
| 1168system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1169system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1170system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1171system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1172system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1173system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1174system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1175system.cpu.kern.inst.arm 0 # number of arm instructions executed 1176system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1177 1178---------- End Simulation Statistics ---------- | 1602system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1603system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1604system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1605system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1606system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1607system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1608system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1609system.cpu.kern.inst.arm 0 # number of arm instructions executed 1610system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1611 1612---------- End Simulation Statistics ---------- |