| stats.txt (9568:cd1351d4d850) | stats.txt (9575:6c4d6fdf3644) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.136865 # Number of seconds simulated 4sim_ticks 5136864535500 # Number of ticks simulated 5final_tick 5136864535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.132858 # Number of seconds simulated 4sim_ticks 5132857897000 # Number of ticks simulated 5final_tick 5132857897000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 199949 # Simulator instruction rate (inst/s) 8host_op_rate 395248 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2517891877 # Simulator tick rate (ticks/s) 10host_mem_usage 755196 # Number of bytes of host memory used 11host_seconds 2040.15 # Real time elapsed on the host 12sim_insts 407925588 # Number of instructions simulated 13sim_ops 806363480 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2498048 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory | 7host_inst_rate 156379 # Simulator instruction rate (inst/s) 8host_op_rate 309121 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1967786651 # Simulator tick rate (ticks/s) 10host_mem_usage 752412 # Number of bytes of host memory used 11host_seconds 2608.44 # Real time elapsed on the host 12sim_insts 407905700 # Number of instructions simulated 13sim_ops 806325509 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2501312 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 1077760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10804608 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14383936 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1077760 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1077760 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9566528 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9566528 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 39032 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 1078144 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10788736 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14371776 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1078144 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1078144 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9560192 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9560192 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 39083 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.inst 16840 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168822 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 224749 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149477 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149477 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 486298 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::cpu.inst 16846 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168574 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 224559 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149378 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149378 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 487314 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 623 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.inst 209809 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2103347 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2800139 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 209809 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 209809 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1862328 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1862328 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1862328 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 486298 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) | 35system.physmem.bw_read::cpu.inst 210048 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2101896 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2799956 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 210048 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 210048 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1862548 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1862548 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1862548 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 487314 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 623 # Total bandwidth to/from this memory (bytes/s) |
| 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.inst 209809 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2103347 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4662468 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 224749 # Total number of read requests seen 50system.physmem.writeReqs 149477 # Total number of write requests seen 51system.physmem.cpureqs 378758 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14383936 # Total number of bytes read from memory 53system.physmem.bytesWritten 9566528 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14383936 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9566528 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 3970 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 14108 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 13038 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 13174 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 16315 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13707 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 13158 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13525 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 16255 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13935 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 13285 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13290 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 15648 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13203 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 12660 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13428 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15923 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 9005 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 8432 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8529 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 11625 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8800 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 8560 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8903 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 11692 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 9007 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8684 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 8693 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 11170 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8382 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 8108 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8695 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 11192 # Track writes on a per bank basis | 46system.physmem.bw_total::cpu.inst 210048 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2101896 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4662504 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 224559 # Total number of read requests seen 50system.physmem.writeReqs 149378 # Total number of write requests seen 51system.physmem.cpureqs 379116 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14371776 # Total number of bytes read from memory 53system.physmem.bytesWritten 9560192 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14371776 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9560192 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 86 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 3988 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 14046 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 12988 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 13113 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 16256 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13686 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 13149 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13495 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 16230 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13981 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 13311 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13328 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 15635 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13184 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 12667 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13446 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15958 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 9012 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 8453 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8452 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 11545 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8811 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 8570 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8847 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 11675 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 9048 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8676 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 8758 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 11176 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8354 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 8087 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8705 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 11209 # Track writes on a per bank basis |
| 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 91system.physmem.numWrRetry 562 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5136864483000 # Total gap between requests | 91system.physmem.numWrRetry 1191 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5132857844500 # Total gap between requests |
| 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes | 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 99system.physmem.readPktSize::6 224749 # Categorize read packet sizes | 99system.physmem.readPktSize::6 224559 # Categorize read packet sizes |
| 100system.physmem.writePktSize::0 0 # Categorize write packet sizes 101system.physmem.writePktSize::1 0 # Categorize write packet sizes 102system.physmem.writePktSize::2 0 # Categorize write packet sizes 103system.physmem.writePktSize::3 0 # Categorize write packet sizes 104system.physmem.writePktSize::4 0 # Categorize write packet sizes 105system.physmem.writePktSize::5 0 # Categorize write packet sizes | 100system.physmem.writePktSize::0 0 # Categorize write packet sizes 101system.physmem.writePktSize::1 0 # Categorize write packet sizes 102system.physmem.writePktSize::2 0 # Categorize write packet sizes 103system.physmem.writePktSize::3 0 # Categorize write packet sizes 104system.physmem.writePktSize::4 0 # Categorize write packet sizes 105system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 106system.physmem.writePktSize::6 149477 # Categorize write packet sizes 107system.physmem.rdQLenPdf::0 173174 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 19685 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 3521 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 3015 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 2402 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1894 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1830 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1773 # What read queue length does an incoming req see | 106system.physmem.writePktSize::6 149378 # Categorize write packet sizes 107system.physmem.rdQLenPdf::0 172944 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 19784 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 7536 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 3483 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 3003 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1885 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1824 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1768 # What read queue length does an incoming req see |
| 116system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see | 116system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see |
| 117system.physmem.rdQLenPdf::10 1145 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 964 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 885 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::15 809 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::16 906 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::17 870 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::18 386 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::19 240 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see | 117system.physmem.rdQLenPdf::10 1142 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1043 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 975 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::14 814 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::15 816 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::17 857 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::18 400 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::19 249 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::20 32 # What read queue length does an incoming req see |
| 128system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 128system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 139system.physmem.wrQLenPdf::0 5359 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::1 5713 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::2 6316 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::3 6398 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::4 6438 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::5 6479 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::6 6486 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::7 6489 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 6490 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 1140 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 786 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 183 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 101 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see 171system.physmem.totQLat 4764271250 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 9277483750 # Sum of mem lat for all requests 173system.physmem.totBusLat 1123260000 # Total cycles spent in databus access 174system.physmem.totBankLat 3389952500 # Total cycles spent in bank access 175system.physmem.avgQLat 21207.34 # Average queueing delay per request 176system.physmem.avgBankLat 15089.79 # Average bank access latency per request | 139system.physmem.wrQLenPdf::0 5358 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::1 5717 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::2 6325 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::3 6395 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::4 6435 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::5 6471 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::6 6478 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 6495 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 6495 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 6495 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 6495 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 6495 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 6495 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::15 6495 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 6494 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 6494 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 6494 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 6494 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6494 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 6494 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 1137 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 778 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 100 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 60 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see 171system.physmem.totQLat 4795272000 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 9305637000 # Sum of mem lat for all requests 173system.physmem.totBusLat 1122365000 # Total cycles spent in databus access 174system.physmem.totBankLat 3388000000 # Total cycles spent in bank access 175system.physmem.avgQLat 21362.36 # Average queueing delay per request 176system.physmem.avgBankLat 15093.13 # Average bank access latency per request |
| 177system.physmem.avgBusLat 5000.00 # Average bus latency per request | 177system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 178system.physmem.avgMemAccLat 41297.13 # Average memory access latency | 178system.physmem.avgMemAccLat 41455.48 # Average memory access latency |
| 179system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s 180system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s 181system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s 182system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 184system.physmem.busUtil 0.04 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.00 # Average read queue length over time | 179system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s 180system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s 181system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s 182system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 184system.physmem.busUtil 0.04 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.00 # Average read queue length over time |
| 186system.physmem.avgWrQLen 11.02 # Average write queue length over time 187system.physmem.readRowHits 193727 # Number of row buffer hits during reads 188system.physmem.writeRowHits 105780 # Number of row buffer hits during writes 189system.physmem.readRowHitRate 86.23 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes 191system.physmem.avgGap 13726637.07 # Average gap between requests | 186system.physmem.avgWrQLen 11.03 # Average write queue length over time 187system.physmem.readRowHits 193515 # Number of row buffer hits during reads 188system.physmem.writeRowHits 105640 # Number of row buffer hits during writes 189system.physmem.readRowHitRate 86.21 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate 70.72 # Row buffer hit rate for writes 191system.physmem.avgGap 13726531.06 # Average gap between requests |
| 192system.iocache.replacements 47576 # number of replacements | 192system.iocache.replacements 47576 # number of replacements |
| 193system.iocache.tagsinuse 0.116322 # Cycle average of tags in use | 193system.iocache.tagsinuse 0.103924 # Cycle average of tags in use |
| 194system.iocache.total_refs 0 # Total number of references to valid blocks. 195system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. 196system.iocache.avg_refs 0 # Average number of references to valid blocks. 197system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. | 194system.iocache.total_refs 0 # Total number of references to valid blocks. 195system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. 196system.iocache.avg_refs 0 # Average number of references to valid blocks. 197system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. |
| 198system.iocache.occ_blocks::pc.south_bridge.ide 0.116322 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy | 198system.iocache.occ_blocks::pc.south_bridge.ide 0.103924 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.006495 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.006495 # Average percentage of cache occupancy |
| 201system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 911 # number of ReadReq misses 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 205system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 206system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 207system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 208system.iocache.overall_misses::total 47631 # number of overall misses | 201system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 911 # number of ReadReq misses 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 205system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 206system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 207system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 208system.iocache.overall_misses::total 47631 # number of overall misses |
| 209system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151593932 # number of ReadReq miss cycles 210system.iocache.ReadReq_miss_latency::total 151593932 # number of ReadReq miss cycles 211system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10023192160 # number of WriteReq miss cycles 212system.iocache.WriteReq_miss_latency::total 10023192160 # number of WriteReq miss cycles 213system.iocache.demand_miss_latency::pc.south_bridge.ide 10174786092 # number of demand (read+write) miss cycles 214system.iocache.demand_miss_latency::total 10174786092 # number of demand (read+write) miss cycles 215system.iocache.overall_miss_latency::pc.south_bridge.ide 10174786092 # number of overall miss cycles 216system.iocache.overall_miss_latency::total 10174786092 # number of overall miss cycles | 209system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146639932 # number of ReadReq miss cycles 210system.iocache.ReadReq_miss_latency::total 146639932 # number of ReadReq miss cycles 211system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10056560160 # number of WriteReq miss cycles 212system.iocache.WriteReq_miss_latency::total 10056560160 # number of WriteReq miss cycles 213system.iocache.demand_miss_latency::pc.south_bridge.ide 10203200092 # number of demand (read+write) miss cycles 214system.iocache.demand_miss_latency::total 10203200092 # number of demand (read+write) miss cycles 215system.iocache.overall_miss_latency::pc.south_bridge.ide 10203200092 # number of overall miss cycles 216system.iocache.overall_miss_latency::total 10203200092 # number of overall miss cycles |
| 217system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 218system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) 219system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 220system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 221system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 222system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 223system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 224system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses 225system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 226system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 227system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 228system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 229system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 231system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 217system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 218system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) 219system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 220system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 221system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 222system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 223system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 224system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses 225system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 226system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 227system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 228system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 229system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 231system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 233system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166403.877058 # average ReadReq miss latency 234system.iocache.ReadReq_avg_miss_latency::total 166403.877058 # average ReadReq miss latency 235system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214537.503425 # average WriteReq miss latency 236system.iocache.WriteReq_avg_miss_latency::total 214537.503425 # average WriteReq miss latency 237system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency 238system.iocache.demand_avg_miss_latency::total 213616.890093 # average overall miss latency 239system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency 240system.iocache.overall_avg_miss_latency::total 213616.890093 # average overall miss latency 241system.iocache.blocked_cycles::no_mshrs 136470 # number of cycles access was blocked | 233system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160965.896817 # average ReadReq miss latency 234system.iocache.ReadReq_avg_miss_latency::total 160965.896817 # average ReadReq miss latency 235system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215251.715753 # average WriteReq miss latency 236system.iocache.WriteReq_avg_miss_latency::total 215251.715753 # average WriteReq miss latency 237system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214213.434360 # average overall miss latency 238system.iocache.demand_avg_miss_latency::total 214213.434360 # average overall miss latency 239system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214213.434360 # average overall miss latency 240system.iocache.overall_avg_miss_latency::total 214213.434360 # average overall miss latency 241system.iocache.blocked_cycles::no_mshrs 137627 # number of cycles access was blocked |
| 242system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 242system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 243system.iocache.blocked::no_mshrs 12410 # number of cycles access was blocked | 243system.iocache.blocked::no_mshrs 12509 # number of cycles access was blocked |
| 244system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 244system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 245system.iocache.avg_blocked_cycles::no_mshrs 10.996777 # average number of cycles each access was blocked | 245system.iocache.avg_blocked_cycles::no_mshrs 11.002238 # average number of cycles each access was blocked |
| 246system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.iocache.fast_writes 0 # number of fast writes performed 248system.iocache.cache_copies 0 # number of cache copies performed 249system.iocache.writebacks::writebacks 46667 # number of writebacks 250system.iocache.writebacks::total 46667 # number of writebacks 251system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 252system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses 253system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 254system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 255system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 256system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 257system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 258system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses | 246system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.iocache.fast_writes 0 # number of fast writes performed 248system.iocache.cache_copies 0 # number of cache copies performed 249system.iocache.writebacks::writebacks 46667 # number of writebacks 250system.iocache.writebacks::total 46667 # number of writebacks 251system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 252system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses 253system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 254system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 255system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 256system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 257system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 258system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses |
| 259system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104200712 # number of ReadReq MSHR miss cycles 260system.iocache.ReadReq_mshr_miss_latency::total 104200712 # number of ReadReq MSHR miss cycles 261system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7592410619 # number of WriteReq MSHR miss cycles 262system.iocache.WriteReq_mshr_miss_latency::total 7592410619 # number of WriteReq MSHR miss cycles 263system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of demand (read+write) MSHR miss cycles 264system.iocache.demand_mshr_miss_latency::total 7696611331 # number of demand (read+write) MSHR miss cycles 265system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of overall MSHR miss cycles 266system.iocache.overall_mshr_miss_latency::total 7696611331 # number of overall MSHR miss cycles | 259system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99246962 # number of ReadReq MSHR miss cycles 260system.iocache.ReadReq_mshr_miss_latency::total 99246962 # number of ReadReq MSHR miss cycles 261system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7625786368 # number of WriteReq MSHR miss cycles 262system.iocache.WriteReq_mshr_miss_latency::total 7625786368 # number of WriteReq MSHR miss cycles 263system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7725033330 # number of demand (read+write) MSHR miss cycles 264system.iocache.demand_mshr_miss_latency::total 7725033330 # number of demand (read+write) MSHR miss cycles 265system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7725033330 # number of overall MSHR miss cycles 266system.iocache.overall_mshr_miss_latency::total 7725033330 # number of overall MSHR miss cycles |
| 267system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 268system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 269system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 270system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 271system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 272system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 273system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 274system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 267system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 268system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 269system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 270system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 271system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 272system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 273system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 274system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 275system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114380.583974 # average ReadReq mshr miss latency 276system.iocache.ReadReq_avg_mshr_miss_latency::total 114380.583974 # average ReadReq mshr miss latency 277system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162508.788934 # average WriteReq mshr miss latency 278system.iocache.WriteReq_avg_mshr_miss_latency::total 162508.788934 # average WriteReq mshr miss latency 279system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency 280system.iocache.demand_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency 281system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency 282system.iocache.overall_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency | 275system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108942.878156 # average ReadReq mshr miss latency 276system.iocache.ReadReq_avg_mshr_miss_latency::total 108942.878156 # average ReadReq mshr miss latency 277system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163223.167123 # average WriteReq mshr miss latency 278system.iocache.WriteReq_avg_mshr_miss_latency::total 163223.167123 # average WriteReq mshr miss latency 279system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162184.991497 # average overall mshr miss latency 280system.iocache.demand_avg_mshr_miss_latency::total 162184.991497 # average overall mshr miss latency 281system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162184.991497 # average overall mshr miss latency 282system.iocache.overall_avg_mshr_miss_latency::total 162184.991497 # average overall mshr miss latency |
| 283system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 285system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 286system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 287system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 288system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 289system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 290system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 291system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 292system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 293system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 294system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 295system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 283system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 285system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 286system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 287system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 288system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 289system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 290system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 291system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 292system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 293system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 294system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 295system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 296system.cpu.branchPred.lookups 86198193 # Number of BP lookups 297system.cpu.branchPred.condPredicted 86198193 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 1106234 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 81290548 # Number of BTB lookups 300system.cpu.branchPred.BTBHits 79213904 # Number of BTB hits | 296system.cpu.branchPred.lookups 86194611 # Number of BP lookups 297system.cpu.branchPred.condPredicted 86194611 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 1105724 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 81284951 # Number of BTB lookups 300system.cpu.branchPred.BTBHits 79210874 # Number of BTB hits |
| 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 302system.cpu.branchPred.BTBHitPct 97.445405 # BTB Hit Percentage | 302system.cpu.branchPred.BTBHitPct 97.448387 # BTB Hit Percentage |
| 303system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. | 303system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 305system.cpu.numCycles 448153841 # number of cpu cycles simulated | 305system.cpu.numCycles 448157181 # number of cpu cycles simulated |
| 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 308system.cpu.fetch.icacheStallCycles 27415171 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 425937394 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 86198193 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 79213904 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 163576958 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 4698498 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 117961 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.BlockedCycles 63103393 # Number of cycles fetch has spent blocked 316system.cpu.fetch.MiscStallCycles 36350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 317system.cpu.fetch.PendingTrapStallCycles 51299 # Number of stall cycles due to pending traps 318system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 9010068 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 483485 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 3126 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 257855511 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 3.261045 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.418033 # Number of instructions fetched each cycle (Total) | 308system.cpu.fetch.icacheStallCycles 27411589 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 425916361 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 86194611 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 79210874 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 163569758 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 4698258 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 127091 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.BlockedCycles 63100705 # Number of cycles fetch has spent blocked 316system.cpu.fetch.MiscStallCycles 36134 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 317system.cpu.fetch.PendingTrapStallCycles 51634 # Number of stall cycles due to pending traps 318system.cpu.fetch.IcacheWaitRetryStallCycles 488 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 9006921 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 482292 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 2784 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 257851520 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 3.260962 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.418035 # Number of instructions fetched each cycle (Total) |
| 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 326system.cpu.fetch.rateDist::0 94705411 36.73% 36.73% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 1566235 0.61% 37.34% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 71918028 27.89% 65.23% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 935930 0.36% 65.59% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 1598963 0.62% 66.21% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 2419267 0.94% 67.15% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 1070398 0.42% 67.56% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 1376464 0.53% 68.10% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 82264815 31.90% 100.00% # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.rateDist::0 94708741 36.73% 36.73% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 1565189 0.61% 37.34% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 71915500 27.89% 65.23% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 936812 0.36% 65.59% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 1597915 0.62% 66.21% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 2418163 0.94% 67.15% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 1071060 0.42% 67.56% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 1376608 0.53% 68.10% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 82261532 31.90% 100.00% # Number of instructions fetched each cycle (Total) |
| 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 338system.cpu.fetch.rateDist::total 257855511 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.192341 # Number of branch fetches per cycle 340system.cpu.fetch.rate 0.950427 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 31132857 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 60536501 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 159370274 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 3261936 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 3553943 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 837748670 # Number of instructions handled by decode 347system.cpu.decode.SquashedInsts 951 # Number of squashed instructions handled by decode 348system.cpu.rename.SquashCycles 3553943 # Number of cycles rename is squashing 349system.cpu.rename.IdleCycles 33869883 # Number of cycles rename is idle 350system.cpu.rename.BlockCycles 37385632 # Number of cycles rename is blocking 351system.cpu.rename.serializeStallCycles 11021591 # count of cycles rename stalled for serializing inst 352system.cpu.rename.RunCycles 159568277 # Number of cycles rename is running 353system.cpu.rename.UnblockCycles 12456185 # Number of cycles rename is unblocking 354system.cpu.rename.RenamedInsts 834115262 # Number of instructions processed by rename 355system.cpu.rename.ROBFullEvents 19668 # Number of times rename has blocked due to ROB full 356system.cpu.rename.IQFullEvents 5867494 # Number of times rename has blocked due to IQ full 357system.cpu.rename.LSQFullEvents 4754545 # Number of times rename has blocked due to LSQ full 358system.cpu.rename.FullRegisterEvents 8312 # Number of times there has been no free registers 359system.cpu.rename.RenamedOperands 995635482 # Number of destination operands rename has renamed 360system.cpu.rename.RenameLookups 1810665967 # Number of register rename lookups that rename has made 361system.cpu.rename.int_rename_lookups 1810665163 # Number of integer rename lookups 362system.cpu.rename.fp_rename_lookups 804 # Number of floating rename lookups 363system.cpu.rename.CommittedMaps 964341342 # Number of HB maps that are committed 364system.cpu.rename.UndoneMaps 31294133 # Number of HB maps that are undone due to squashing 365system.cpu.rename.serializingInsts 459159 # count of serializing insts renamed 366system.cpu.rename.tempSerializingInsts 467055 # count of temporary serializing insts renamed 367system.cpu.rename.skidInsts 28798095 # count of insts added to the skid buffer 368system.cpu.memDep0.insertedLoads 17056943 # Number of loads inserted to the mem dependence unit. 369system.cpu.memDep0.insertedStores 10123506 # Number of stores inserted to the mem dependence unit. 370system.cpu.memDep0.conflictingLoads 1248285 # Number of conflicting loads. 371system.cpu.memDep0.conflictingStores 987203 # Number of conflicting stores. 372system.cpu.iq.iqInstsAdded 827998215 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqNonSpecInstsAdded 1251183 # Number of non-speculative instructions added to the IQ 374system.cpu.iq.iqInstsIssued 823066756 # Number of instructions issued 375system.cpu.iq.iqSquashedInstsIssued 148002 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 21984557 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 33441202 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 198541 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 257855511 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 3.191969 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 2.384014 # Number of insts issued each cycle | 338system.cpu.fetch.rateDist::total 257851520 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.192331 # Number of branch fetches per cycle 340system.cpu.fetch.rate 0.950373 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 31130056 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 60542452 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 159362996 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 3261895 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 3554121 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 837710983 # Number of instructions handled by decode 347system.cpu.decode.SquashedInsts 948 # Number of squashed instructions handled by decode 348system.cpu.rename.SquashCycles 3554121 # Number of cycles rename is squashing 349system.cpu.rename.IdleCycles 33866246 # Number of cycles rename is idle 350system.cpu.rename.BlockCycles 37401594 # Number of cycles rename is blocking 351system.cpu.rename.serializeStallCycles 11010183 # count of cycles rename stalled for serializing inst 352system.cpu.rename.RunCycles 159560886 # Number of cycles rename is running 353system.cpu.rename.UnblockCycles 12458490 # Number of cycles rename is unblocking 354system.cpu.rename.RenamedInsts 834077749 # Number of instructions processed by rename 355system.cpu.rename.ROBFullEvents 19680 # Number of times rename has blocked due to ROB full 356system.cpu.rename.IQFullEvents 5867270 # Number of times rename has blocked due to IQ full 357system.cpu.rename.LSQFullEvents 4756403 # Number of times rename has blocked due to LSQ full 358system.cpu.rename.FullRegisterEvents 8649 # Number of times there has been no free registers 359system.cpu.rename.RenamedOperands 995584301 # Number of destination operands rename has renamed 360system.cpu.rename.RenameLookups 1810575684 # Number of register rename lookups that rename has made 361system.cpu.rename.int_rename_lookups 1810574876 # Number of integer rename lookups 362system.cpu.rename.fp_rename_lookups 808 # Number of floating rename lookups 363system.cpu.rename.CommittedMaps 964290633 # Number of HB maps that are committed 364system.cpu.rename.UndoneMaps 31293661 # Number of HB maps that are undone due to squashing 365system.cpu.rename.serializingInsts 458949 # count of serializing insts renamed 366system.cpu.rename.tempSerializingInsts 466891 # count of temporary serializing insts renamed 367system.cpu.rename.skidInsts 28798932 # count of insts added to the skid buffer 368system.cpu.memDep0.insertedLoads 17055930 # Number of loads inserted to the mem dependence unit. 369system.cpu.memDep0.insertedStores 10122177 # Number of stores inserted to the mem dependence unit. 370system.cpu.memDep0.conflictingLoads 1247187 # Number of conflicting loads. 371system.cpu.memDep0.conflictingStores 990912 # Number of conflicting stores. 372system.cpu.iq.iqInstsAdded 827964566 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqNonSpecInstsAdded 1250540 # Number of non-speculative instructions added to the IQ 374system.cpu.iq.iqInstsIssued 823033686 # Number of instructions issued 375system.cpu.iq.iqSquashedInstsIssued 148209 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 21990342 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 33439565 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 197993 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 257851520 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 3.191890 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 2.384052 # Number of insts issued each cycle |
| 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 383system.cpu.iq.issued_per_cycle::0 71390186 27.69% 27.69% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 15517919 6.02% 33.70% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 10294138 3.99% 37.70% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 7464826 2.89% 40.59% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 75904474 29.44% 70.03% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 3838948 1.49% 71.52% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 72513480 28.12% 99.64% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 779753 0.30% 99.94% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 151787 0.06% 100.00% # Number of insts issued each cycle | 383system.cpu.iq.issued_per_cycle::0 71392246 27.69% 27.69% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 15523930 6.02% 33.71% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 10289230 3.99% 37.70% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 7461063 2.89% 40.59% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 75902807 29.44% 70.03% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 3840005 1.49% 71.52% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 72510870 28.12% 99.64% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 779318 0.30% 99.94% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 152051 0.06% 100.00% # Number of insts issued each cycle |
| 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 395system.cpu.iq.issued_per_cycle::total 257855511 # Number of insts issued each cycle | 395system.cpu.iq.issued_per_cycle::total 257851520 # Number of insts issued each cycle |
| 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 397system.cpu.iq.fu_full::IntAlu 363612 34.06% 34.06% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntMult 0 0.00% 34.06% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 0 0.00% 34.06% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.06% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.06% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.06% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 34.06% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.06% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.06% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.06% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.06% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.06% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.06% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.06% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.06% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMult 0 0.00% 34.06% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.06% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShift 0 0.00% 34.06% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.06% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.06% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.06% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.06% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.06% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.06% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.06% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.06% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.06% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.06% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.06% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemRead 553162 51.82% 85.88% # attempts to use FU when none available 427system.cpu.iq.fu_full::MemWrite 150741 14.12% 100.00% # attempts to use FU when none available | 397system.cpu.iq.fu_full::IntAlu 361997 33.96% 33.96% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntMult 0 0.00% 33.96% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 0 0.00% 33.96% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.96% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.96% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.96% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 33.96% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.96% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.96% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.96% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.96% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.96% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.96% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.96% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.96% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMult 0 0.00% 33.96% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.96% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShift 0 0.00% 33.96% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.96% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.96% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.96% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.96% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.96% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.96% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.96% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.96% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.96% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.96% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.96% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemRead 553138 51.89% 85.84% # attempts to use FU when none available 427system.cpu.iq.fu_full::MemWrite 150897 14.16% 100.00% # attempts to use FU when none available |
| 428system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 428system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 430system.cpu.iq.FU_type_0::No_OpClass 311137 0.04% 0.04% # Type of FU issued 431system.cpu.iq.FU_type_0::IntAlu 795540449 96.66% 96.69% # Type of FU issued | 430system.cpu.iq.FU_type_0::No_OpClass 310952 0.04% 0.04% # Type of FU issued 431system.cpu.iq.FU_type_0::IntAlu 795510781 96.66% 96.69% # Type of FU issued |
| 432system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued 433system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 452system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued | 432system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued 433system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 452system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued |
| 460system.cpu.iq.FU_type_0::MemRead 17836742 2.17% 98.86% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 9378428 1.14% 100.00% # Type of FU issued | 460system.cpu.iq.FU_type_0::MemRead 17835089 2.17% 98.86% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 9376864 1.14% 100.00% # Type of FU issued |
| 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 464system.cpu.iq.FU_type_0::total 823066756 # Type of FU issued 465system.cpu.iq.rate 1.836572 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 1067515 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 1905334904 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 851243829 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 818598323 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 260 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 823823020 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 114 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 1639481 # Number of loads that had data forwarded from stores | 464system.cpu.iq.FU_type_0::total 823033686 # Type of FU issued 465system.cpu.iq.rate 1.836484 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 1066032 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.001295 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 1905263509 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 851215281 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 818564848 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 272 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 382 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 823788636 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 1638773 # Number of loads that had data forwarded from stores |
| 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 478system.cpu.iew.lsq.thread0.squashedLoads 3079539 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 22701 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 11520 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 1710580 # Number of stores squashed | 478system.cpu.iew.lsq.thread0.squashedLoads 3081166 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 22705 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 11479 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 1710957 # Number of stores squashed |
| 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 484system.cpu.iew.lsq.thread0.rescheduledLoads 1932434 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 12204 # Number of times an access to memory failed due to the cache being blocked | 484system.cpu.iew.lsq.thread0.rescheduledLoads 1932446 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 12217 # Number of times an access to memory failed due to the cache being blocked |
| 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 487system.cpu.iew.iewSquashCycles 3553943 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 26124965 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 2116869 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 829249398 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 321104 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 17056943 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 10123506 # Number of dispatched store instructions 494system.cpu.iew.iewDispNonSpecInsts 718931 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 1615774 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 10404 # Number of times the LSQ has become full, causing a stall 497system.cpu.iew.memOrderViolationEvents 11520 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 649169 # Number of branches that were predicted taken incorrectly 499system.cpu.iew.predictedNotTakenIncorrect 592997 # Number of branches that were predicted not taken incorrectly 500system.cpu.iew.branchMispredicts 1242166 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 821195112 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 17426068 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 1871643 # Number of squashed instructions skipped in execute | 487system.cpu.iew.iewSquashCycles 3554121 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 26141117 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 2116575 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 829215106 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 320591 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 17055930 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 10122177 # Number of dispatched store instructions 494system.cpu.iew.iewDispNonSpecInsts 718653 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 1615740 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 10506 # Number of times the LSQ has become full, causing a stall 497system.cpu.iew.memOrderViolationEvents 11479 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 648838 # Number of branches that were predicted taken incorrectly 499system.cpu.iew.predictedNotTakenIncorrect 592977 # Number of branches that were predicted not taken incorrectly 500system.cpu.iew.branchMispredicts 1241815 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 821161230 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 17423630 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 1872455 # Number of squashed instructions skipped in execute |
| 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed | 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 506system.cpu.iew.exec_refs 26572625 # number of memory reference insts executed 507system.cpu.iew.exec_branches 83197450 # Number of branches executed 508system.cpu.iew.exec_stores 9146557 # Number of stores executed 509system.cpu.iew.exec_rate 1.832396 # Inst execution rate 510system.cpu.iew.wb_sent 820733466 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 818598386 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 639795417 # num instructions producing a value 513system.cpu.iew.wb_consumers 1045555736 # num instructions consuming a value | 506system.cpu.iew.exec_refs 26568531 # number of memory reference insts executed 507system.cpu.iew.exec_branches 83193011 # Number of branches executed 508system.cpu.iew.exec_stores 9144901 # Number of stores executed 509system.cpu.iew.exec_rate 1.832306 # Inst execution rate 510system.cpu.iew.wb_sent 820700229 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 818564922 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 639778882 # num instructions producing a value 513system.cpu.iew.wb_consumers 1045529467 # num instructions consuming a value |
| 514system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 514system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 515system.cpu.iew.wb_rate 1.826601 # insts written-back per cycle | 515system.cpu.iew.wb_rate 1.826513 # insts written-back per cycle |
| 516system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back 517system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 516system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back 517system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 518system.cpu.commit.commitSquashedInsts 22777543 # The number of squashed insts skipped by commit 519system.cpu.commit.commitNonSpecStalls 1052640 # The number of times commit has been forced to stall to communicate backwards 520system.cpu.commit.branchMispredicts 1110740 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 254301568 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 3.170895 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 2.853974 # Number of insts commited each cycle | 518system.cpu.commit.commitSquashedInsts 22781132 # The number of squashed insts skipped by commit 519system.cpu.commit.commitNonSpecStalls 1052545 # The number of times commit has been forced to stall to communicate backwards 520system.cpu.commit.branchMispredicts 1110334 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 254297399 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 3.170797 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 2.853937 # Number of insts commited each cycle |
| 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 525system.cpu.commit.committed_per_cycle::0 82529406 32.45% 32.45% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::1 11802979 4.64% 37.09% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::2 3912644 1.54% 38.63% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 74944166 29.47% 68.10% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::4 2437687 0.96% 69.06% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::5 1481720 0.58% 69.65% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::6 940520 0.37% 70.01% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 70919321 27.89% 97.90% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 5333125 2.10% 100.00% # Number of insts commited each cycle | 525system.cpu.commit.committed_per_cycle::0 82526547 32.45% 32.45% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::1 11810769 4.64% 37.10% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::2 3910269 1.54% 38.63% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 74942576 29.47% 68.11% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::4 2436425 0.96% 69.06% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::5 1481605 0.58% 69.65% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::6 941054 0.37% 70.02% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 70918807 27.89% 97.90% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 5329347 2.10% 100.00% # Number of insts commited each cycle |
| 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 537system.cpu.commit.committed_per_cycle::total 254301568 # Number of insts commited each cycle 538system.cpu.commit.committedInsts 407925588 # Number of instructions committed 539system.cpu.commit.committedOps 806363480 # Number of ops (including micro ops) committed | 537system.cpu.commit.committed_per_cycle::total 254297399 # Number of insts commited each cycle 538system.cpu.commit.committedInsts 407905700 # Number of instructions committed 539system.cpu.commit.committedOps 806325509 # Number of ops (including micro ops) committed |
| 540system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 540system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 541system.cpu.commit.refs 22390327 # Number of memory references committed 542system.cpu.commit.loads 13977401 # Number of loads committed | 541system.cpu.commit.refs 22385981 # Number of memory references committed 542system.cpu.commit.loads 13974761 # Number of loads committed |
| 543system.cpu.commit.membars 473457 # Number of memory barriers committed | 543system.cpu.commit.membars 473457 # Number of memory barriers committed |
| 544system.cpu.commit.branches 82191015 # Number of branches committed | 544system.cpu.commit.branches 82185695 # Number of branches committed |
| 545system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 545system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 546system.cpu.commit.int_insts 735304742 # Number of committed integer instructions. | 546system.cpu.commit.int_insts 735267209 # Number of committed integer instructions. |
| 547system.cpu.commit.function_calls 0 # Number of function calls committed. | 547system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 548system.cpu.commit.bw_lim_events 5333125 # number cycles where commit BW limit reached | 548system.cpu.commit.bw_lim_events 5329347 # number cycles where commit BW limit reached |
| 549system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 549system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 550system.cpu.rob.rob_reads 1078031216 # The number of ROB reads 551system.cpu.rob.rob_writes 1661854677 # The number of ROB writes 552system.cpu.timesIdled 1219790 # Number of times that the entire CPU went into an idle state and unscheduled itself 553system.cpu.idleCycles 190298330 # Total number of cycles that the CPU has spent unscheduled due to idling 554system.cpu.quiesceCycles 9825572650 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 555system.cpu.committedInsts 407925588 # Number of Instructions Simulated 556system.cpu.committedOps 806363480 # Number of Ops (including micro ops) Simulated 557system.cpu.committedInsts_total 407925588 # Number of Instructions Simulated 558system.cpu.cpi 1.098617 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 1.098617 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.910236 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.910236 # IPC: Total IPC of All Threads 562system.cpu.int_regfile_reads 1506687590 # number of integer regfile reads 563system.cpu.int_regfile_writes 976781809 # number of integer regfile writes 564system.cpu.fp_regfile_reads 63 # number of floating regfile reads 565system.cpu.misc_regfile_reads 264621583 # number of misc regfile reads 566system.cpu.misc_regfile_writes 402234 # number of misc regfile writes 567system.cpu.icache.replacements 1045798 # number of replacements 568system.cpu.icache.tagsinuse 510.125014 # Cycle average of tags in use 569system.cpu.icache.total_refs 7900747 # Total number of references to valid blocks. 570system.cpu.icache.sampled_refs 1046310 # Sample count of references to valid blocks. 571system.cpu.icache.avg_refs 7.551058 # Average number of references to valid blocks. | 550system.cpu.rob.rob_reads 1077996488 # The number of ROB reads 551system.cpu.rob.rob_writes 1661786087 # The number of ROB writes 552system.cpu.timesIdled 1219722 # Number of times that the entire CPU went into an idle state and unscheduled itself 553system.cpu.idleCycles 190305661 # Total number of cycles that the CPU has spent unscheduled due to idling 554system.cpu.quiesceCycles 9817556036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 555system.cpu.committedInsts 407905700 # Number of Instructions Simulated 556system.cpu.committedOps 806325509 # Number of Ops (including micro ops) Simulated 557system.cpu.committedInsts_total 407905700 # Number of Instructions Simulated 558system.cpu.cpi 1.098678 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 1.098678 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.910184 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.910184 # IPC: Total IPC of All Threads 562system.cpu.int_regfile_reads 1506617542 # number of integer regfile reads 563system.cpu.int_regfile_writes 976738350 # number of integer regfile writes 564system.cpu.fp_regfile_reads 74 # number of floating regfile reads 565system.cpu.misc_regfile_reads 264608213 # number of misc regfile reads 566system.cpu.misc_regfile_writes 402112 # number of misc regfile writes 567system.cpu.icache.replacements 1045620 # number of replacements 568system.cpu.icache.tagsinuse 510.123573 # Cycle average of tags in use 569system.cpu.icache.total_refs 7898000 # Total number of references to valid blocks. 570system.cpu.icache.sampled_refs 1046132 # Sample count of references to valid blocks. 571system.cpu.icache.avg_refs 7.549716 # Average number of references to valid blocks. |
| 572system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. | 572system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. |
| 573system.cpu.icache.occ_blocks::cpu.inst 510.125014 # Average occupied blocks per requestor 574system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy 575system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy 576system.cpu.icache.ReadReq_hits::cpu.inst 7900747 # number of ReadReq hits 577system.cpu.icache.ReadReq_hits::total 7900747 # number of ReadReq hits 578system.cpu.icache.demand_hits::cpu.inst 7900747 # number of demand (read+write) hits 579system.cpu.icache.demand_hits::total 7900747 # number of demand (read+write) hits 580system.cpu.icache.overall_hits::cpu.inst 7900747 # number of overall hits 581system.cpu.icache.overall_hits::total 7900747 # number of overall hits 582system.cpu.icache.ReadReq_misses::cpu.inst 1109320 # number of ReadReq misses 583system.cpu.icache.ReadReq_misses::total 1109320 # number of ReadReq misses 584system.cpu.icache.demand_misses::cpu.inst 1109320 # number of demand (read+write) misses 585system.cpu.icache.demand_misses::total 1109320 # number of demand (read+write) misses 586system.cpu.icache.overall_misses::cpu.inst 1109320 # number of overall misses 587system.cpu.icache.overall_misses::total 1109320 # number of overall misses 588system.cpu.icache.ReadReq_miss_latency::cpu.inst 15268069493 # number of ReadReq miss cycles 589system.cpu.icache.ReadReq_miss_latency::total 15268069493 # number of ReadReq miss cycles 590system.cpu.icache.demand_miss_latency::cpu.inst 15268069493 # number of demand (read+write) miss cycles 591system.cpu.icache.demand_miss_latency::total 15268069493 # number of demand (read+write) miss cycles 592system.cpu.icache.overall_miss_latency::cpu.inst 15268069493 # number of overall miss cycles 593system.cpu.icache.overall_miss_latency::total 15268069493 # number of overall miss cycles 594system.cpu.icache.ReadReq_accesses::cpu.inst 9010067 # number of ReadReq accesses(hits+misses) 595system.cpu.icache.ReadReq_accesses::total 9010067 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.demand_accesses::cpu.inst 9010067 # number of demand (read+write) accesses 597system.cpu.icache.demand_accesses::total 9010067 # number of demand (read+write) accesses 598system.cpu.icache.overall_accesses::cpu.inst 9010067 # number of overall (read+write) accesses 599system.cpu.icache.overall_accesses::total 9010067 # number of overall (read+write) accesses 600system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123120 # miss rate for ReadReq accesses 601system.cpu.icache.ReadReq_miss_rate::total 0.123120 # miss rate for ReadReq accesses 602system.cpu.icache.demand_miss_rate::cpu.inst 0.123120 # miss rate for demand accesses 603system.cpu.icache.demand_miss_rate::total 0.123120 # miss rate for demand accesses 604system.cpu.icache.overall_miss_rate::cpu.inst 0.123120 # miss rate for overall accesses 605system.cpu.icache.overall_miss_rate::total 0.123120 # miss rate for overall accesses 606system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13763.449224 # average ReadReq miss latency 607system.cpu.icache.ReadReq_avg_miss_latency::total 13763.449224 # average ReadReq miss latency 608system.cpu.icache.demand_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency 609system.cpu.icache.demand_avg_miss_latency::total 13763.449224 # average overall miss latency 610system.cpu.icache.overall_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::total 13763.449224 # average overall miss latency 612system.cpu.icache.blocked_cycles::no_mshrs 12508 # number of cycles access was blocked | 573system.cpu.icache.occ_blocks::cpu.inst 510.123573 # Average occupied blocks per requestor 574system.cpu.icache.occ_percent::cpu.inst 0.996335 # Average percentage of cache occupancy 575system.cpu.icache.occ_percent::total 0.996335 # Average percentage of cache occupancy 576system.cpu.icache.ReadReq_hits::cpu.inst 7898000 # number of ReadReq hits 577system.cpu.icache.ReadReq_hits::total 7898000 # number of ReadReq hits 578system.cpu.icache.demand_hits::cpu.inst 7898000 # number of demand (read+write) hits 579system.cpu.icache.demand_hits::total 7898000 # number of demand (read+write) hits 580system.cpu.icache.overall_hits::cpu.inst 7898000 # number of overall hits 581system.cpu.icache.overall_hits::total 7898000 # number of overall hits 582system.cpu.icache.ReadReq_misses::cpu.inst 1108918 # number of ReadReq misses 583system.cpu.icache.ReadReq_misses::total 1108918 # number of ReadReq misses 584system.cpu.icache.demand_misses::cpu.inst 1108918 # number of demand (read+write) misses 585system.cpu.icache.demand_misses::total 1108918 # number of demand (read+write) misses 586system.cpu.icache.overall_misses::cpu.inst 1108918 # number of overall misses 587system.cpu.icache.overall_misses::total 1108918 # number of overall misses 588system.cpu.icache.ReadReq_miss_latency::cpu.inst 15254848492 # number of ReadReq miss cycles 589system.cpu.icache.ReadReq_miss_latency::total 15254848492 # number of ReadReq miss cycles 590system.cpu.icache.demand_miss_latency::cpu.inst 15254848492 # number of demand (read+write) miss cycles 591system.cpu.icache.demand_miss_latency::total 15254848492 # number of demand (read+write) miss cycles 592system.cpu.icache.overall_miss_latency::cpu.inst 15254848492 # number of overall miss cycles 593system.cpu.icache.overall_miss_latency::total 15254848492 # number of overall miss cycles 594system.cpu.icache.ReadReq_accesses::cpu.inst 9006918 # number of ReadReq accesses(hits+misses) 595system.cpu.icache.ReadReq_accesses::total 9006918 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.demand_accesses::cpu.inst 9006918 # number of demand (read+write) accesses 597system.cpu.icache.demand_accesses::total 9006918 # number of demand (read+write) accesses 598system.cpu.icache.overall_accesses::cpu.inst 9006918 # number of overall (read+write) accesses 599system.cpu.icache.overall_accesses::total 9006918 # number of overall (read+write) accesses 600system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123118 # miss rate for ReadReq accesses 601system.cpu.icache.ReadReq_miss_rate::total 0.123118 # miss rate for ReadReq accesses 602system.cpu.icache.demand_miss_rate::cpu.inst 0.123118 # miss rate for demand accesses 603system.cpu.icache.demand_miss_rate::total 0.123118 # miss rate for demand accesses 604system.cpu.icache.overall_miss_rate::cpu.inst 0.123118 # miss rate for overall accesses 605system.cpu.icache.overall_miss_rate::total 0.123118 # miss rate for overall accesses 606system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13756.516255 # average ReadReq miss latency 607system.cpu.icache.ReadReq_avg_miss_latency::total 13756.516255 # average ReadReq miss latency 608system.cpu.icache.demand_avg_miss_latency::cpu.inst 13756.516255 # average overall miss latency 609system.cpu.icache.demand_avg_miss_latency::total 13756.516255 # average overall miss latency 610system.cpu.icache.overall_avg_miss_latency::cpu.inst 13756.516255 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::total 13756.516255 # average overall miss latency 612system.cpu.icache.blocked_cycles::no_mshrs 9824 # number of cycles access was blocked |
| 613system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 613system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 614system.cpu.icache.blocked::no_mshrs 293 # number of cycles access was blocked | 614system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked |
| 615system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 615system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 616system.cpu.icache.avg_blocked_cycles::no_mshrs 42.689420 # average number of cycles each access was blocked | 616system.cpu.icache.avg_blocked_cycles::no_mshrs 33.189189 # average number of cycles each access was blocked |
| 617system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 618system.cpu.icache.fast_writes 0 # number of fast writes performed 619system.cpu.icache.cache_copies 0 # number of cache copies performed | 617system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 618system.cpu.icache.fast_writes 0 # number of fast writes performed 619system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 620system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60685 # number of ReadReq MSHR hits 621system.cpu.icache.ReadReq_mshr_hits::total 60685 # number of ReadReq MSHR hits 622system.cpu.icache.demand_mshr_hits::cpu.inst 60685 # number of demand (read+write) MSHR hits 623system.cpu.icache.demand_mshr_hits::total 60685 # number of demand (read+write) MSHR hits 624system.cpu.icache.overall_mshr_hits::cpu.inst 60685 # number of overall MSHR hits 625system.cpu.icache.overall_mshr_hits::total 60685 # number of overall MSHR hits 626system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048635 # number of ReadReq MSHR misses 627system.cpu.icache.ReadReq_mshr_misses::total 1048635 # number of ReadReq MSHR misses 628system.cpu.icache.demand_mshr_misses::cpu.inst 1048635 # number of demand (read+write) MSHR misses 629system.cpu.icache.demand_mshr_misses::total 1048635 # number of demand (read+write) MSHR misses 630system.cpu.icache.overall_mshr_misses::cpu.inst 1048635 # number of overall MSHR misses 631system.cpu.icache.overall_mshr_misses::total 1048635 # number of overall MSHR misses 632system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12573562493 # number of ReadReq MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_miss_latency::total 12573562493 # number of ReadReq MSHR miss cycles 634system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12573562493 # number of demand (read+write) MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::total 12573562493 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12573562493 # number of overall MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::total 12573562493 # number of overall MSHR miss cycles 638system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116385 # mshr miss rate for ReadReq accesses 640system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for demand accesses 641system.cpu.icache.demand_mshr_miss_rate::total 0.116385 # mshr miss rate for demand accesses 642system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for overall accesses 643system.cpu.icache.overall_mshr_miss_rate::total 0.116385 # mshr miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11990.408954 # average ReadReq mshr miss latency 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11990.408954 # average ReadReq mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency | 620system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60463 # number of ReadReq MSHR hits 621system.cpu.icache.ReadReq_mshr_hits::total 60463 # number of ReadReq MSHR hits 622system.cpu.icache.demand_mshr_hits::cpu.inst 60463 # number of demand (read+write) MSHR hits 623system.cpu.icache.demand_mshr_hits::total 60463 # number of demand (read+write) MSHR hits 624system.cpu.icache.overall_mshr_hits::cpu.inst 60463 # number of overall MSHR hits 625system.cpu.icache.overall_mshr_hits::total 60463 # number of overall MSHR hits 626system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048455 # number of ReadReq MSHR misses 627system.cpu.icache.ReadReq_mshr_misses::total 1048455 # number of ReadReq MSHR misses 628system.cpu.icache.demand_mshr_misses::cpu.inst 1048455 # number of demand (read+write) MSHR misses 629system.cpu.icache.demand_mshr_misses::total 1048455 # number of demand (read+write) MSHR misses 630system.cpu.icache.overall_mshr_misses::cpu.inst 1048455 # number of overall MSHR misses 631system.cpu.icache.overall_mshr_misses::total 1048455 # number of overall MSHR misses 632system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12565081992 # number of ReadReq MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_miss_latency::total 12565081992 # number of ReadReq MSHR miss cycles 634system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12565081992 # number of demand (read+write) MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::total 12565081992 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12565081992 # number of overall MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::total 12565081992 # number of overall MSHR miss cycles 638system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116406 # mshr miss rate for ReadReq accesses 640system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for demand accesses 641system.cpu.icache.demand_mshr_miss_rate::total 0.116406 # mshr miss rate for demand accesses 642system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for overall accesses 643system.cpu.icache.overall_mshr_miss_rate::total 0.116406 # mshr miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11984.378912 # average ReadReq mshr miss latency 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11984.378912 # average ReadReq mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11984.378912 # average overall mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::total 11984.378912 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11984.378912 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::total 11984.378912 # average overall mshr miss latency |
| 650system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 650system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 651system.cpu.itb_walker_cache.replacements 9600 # number of replacements 652system.cpu.itb_walker_cache.tagsinuse 6.016014 # Cycle average of tags in use 653system.cpu.itb_walker_cache.total_refs 25681 # Total number of references to valid blocks. 654system.cpu.itb_walker_cache.sampled_refs 9614 # Sample count of references to valid blocks. 655system.cpu.itb_walker_cache.avg_refs 2.671209 # Average number of references to valid blocks. 656system.cpu.itb_walker_cache.warmup_cycle 5103990045500 # Cycle when the warmup percentage was hit. 657system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016014 # Average occupied blocks per requestor 658system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376001 # Average percentage of cache occupancy 659system.cpu.itb_walker_cache.occ_percent::total 0.376001 # Average percentage of cache occupancy 660system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25689 # number of ReadReq hits 661system.cpu.itb_walker_cache.ReadReq_hits::total 25689 # number of ReadReq hits | 651system.cpu.itb_walker_cache.replacements 9450 # number of replacements 652system.cpu.itb_walker_cache.tagsinuse 6.008249 # Cycle average of tags in use 653system.cpu.itb_walker_cache.total_refs 25808 # Total number of references to valid blocks. 654system.cpu.itb_walker_cache.sampled_refs 9463 # Sample count of references to valid blocks. 655system.cpu.itb_walker_cache.avg_refs 2.727254 # Average number of references to valid blocks. 656system.cpu.itb_walker_cache.warmup_cycle 5103990002500 # Cycle when the warmup percentage was hit. 657system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008249 # Average occupied blocks per requestor 658system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375516 # Average percentage of cache occupancy 659system.cpu.itb_walker_cache.occ_percent::total 0.375516 # Average percentage of cache occupancy 660system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25828 # number of ReadReq hits 661system.cpu.itb_walker_cache.ReadReq_hits::total 25828 # number of ReadReq hits |
| 662system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 663system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 662system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 663system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 664system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25691 # number of demand (read+write) hits 665system.cpu.itb_walker_cache.demand_hits::total 25691 # number of demand (read+write) hits 666system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25691 # number of overall hits 667system.cpu.itb_walker_cache.overall_hits::total 25691 # number of overall hits 668system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10488 # number of ReadReq misses 669system.cpu.itb_walker_cache.ReadReq_misses::total 10488 # number of ReadReq misses 670system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10488 # number of demand (read+write) misses 671system.cpu.itb_walker_cache.demand_misses::total 10488 # number of demand (read+write) misses 672system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10488 # number of overall misses 673system.cpu.itb_walker_cache.overall_misses::total 10488 # number of overall misses 674system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116654500 # number of ReadReq miss cycles 675system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116654500 # number of ReadReq miss cycles 676system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116654500 # number of demand (read+write) miss cycles 677system.cpu.itb_walker_cache.demand_miss_latency::total 116654500 # number of demand (read+write) miss cycles 678system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116654500 # number of overall miss cycles 679system.cpu.itb_walker_cache.overall_miss_latency::total 116654500 # number of overall miss cycles 680system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36177 # number of ReadReq accesses(hits+misses) 681system.cpu.itb_walker_cache.ReadReq_accesses::total 36177 # number of ReadReq accesses(hits+misses) | 664system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25830 # number of demand (read+write) hits 665system.cpu.itb_walker_cache.demand_hits::total 25830 # number of demand (read+write) hits 666system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25830 # number of overall hits 667system.cpu.itb_walker_cache.overall_hits::total 25830 # number of overall hits 668system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10341 # number of ReadReq misses 669system.cpu.itb_walker_cache.ReadReq_misses::total 10341 # number of ReadReq misses 670system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10341 # number of demand (read+write) misses 671system.cpu.itb_walker_cache.demand_misses::total 10341 # number of demand (read+write) misses 672system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10341 # number of overall misses 673system.cpu.itb_walker_cache.overall_misses::total 10341 # number of overall misses 674system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 115658000 # number of ReadReq miss cycles 675system.cpu.itb_walker_cache.ReadReq_miss_latency::total 115658000 # number of ReadReq miss cycles 676system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 115658000 # number of demand (read+write) miss cycles 677system.cpu.itb_walker_cache.demand_miss_latency::total 115658000 # number of demand (read+write) miss cycles 678system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 115658000 # number of overall miss cycles 679system.cpu.itb_walker_cache.overall_miss_latency::total 115658000 # number of overall miss cycles 680system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36169 # number of ReadReq accesses(hits+misses) 681system.cpu.itb_walker_cache.ReadReq_accesses::total 36169 # number of ReadReq accesses(hits+misses) |
| 682system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 683system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 682system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 683system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 684system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36179 # number of demand (read+write) accesses 685system.cpu.itb_walker_cache.demand_accesses::total 36179 # number of demand (read+write) accesses 686system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36179 # number of overall (read+write) accesses 687system.cpu.itb_walker_cache.overall_accesses::total 36179 # number of overall (read+write) accesses 688system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.289908 # miss rate for ReadReq accesses 689system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.289908 # miss rate for ReadReq accesses 690system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.289892 # miss rate for demand accesses 691system.cpu.itb_walker_cache.demand_miss_rate::total 0.289892 # miss rate for demand accesses 692system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.289892 # miss rate for overall accesses 693system.cpu.itb_walker_cache.overall_miss_rate::total 0.289892 # miss rate for overall accesses 694system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11122.663997 # average ReadReq miss latency 695system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11122.663997 # average ReadReq miss latency 696system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency 697system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11122.663997 # average overall miss latency 698system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency 699system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11122.663997 # average overall miss latency | 684system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36171 # number of demand (read+write) accesses 685system.cpu.itb_walker_cache.demand_accesses::total 36171 # number of demand (read+write) accesses 686system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36171 # number of overall (read+write) accesses 687system.cpu.itb_walker_cache.overall_accesses::total 36171 # number of overall (read+write) accesses 688system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285908 # miss rate for ReadReq accesses 689system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285908 # miss rate for ReadReq accesses 690system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285892 # miss rate for demand accesses 691system.cpu.itb_walker_cache.demand_miss_rate::total 0.285892 # miss rate for demand accesses 692system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285892 # miss rate for overall accesses 693system.cpu.itb_walker_cache.overall_miss_rate::total 0.285892 # miss rate for overall accesses 694system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11184.411566 # average ReadReq miss latency 695system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11184.411566 # average ReadReq miss latency 696system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11184.411566 # average overall miss latency 697system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11184.411566 # average overall miss latency 698system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11184.411566 # average overall miss latency 699system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11184.411566 # average overall miss latency |
| 700system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 701system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 702system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 703system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 704system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 705system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 706system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 707system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 700system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 701system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 702system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 703system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 704system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 705system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 706system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 707system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 708system.cpu.itb_walker_cache.writebacks::writebacks 1936 # number of writebacks 709system.cpu.itb_walker_cache.writebacks::total 1936 # number of writebacks 710system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10488 # number of ReadReq MSHR misses 711system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10488 # number of ReadReq MSHR misses 712system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10488 # number of demand (read+write) MSHR misses 713system.cpu.itb_walker_cache.demand_mshr_misses::total 10488 # number of demand (read+write) MSHR misses 714system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10488 # number of overall MSHR misses 715system.cpu.itb_walker_cache.overall_mshr_misses::total 10488 # number of overall MSHR misses 716system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 95678500 # number of ReadReq MSHR miss cycles 717system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 95678500 # number of ReadReq MSHR miss cycles 718system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 95678500 # number of demand (read+write) MSHR miss cycles 719system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 95678500 # number of demand (read+write) MSHR miss cycles 720system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 95678500 # number of overall MSHR miss cycles 721system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 95678500 # number of overall MSHR miss cycles 722system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.289908 # mshr miss rate for ReadReq accesses 723system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.289908 # mshr miss rate for ReadReq accesses 724system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for demand accesses 725system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.289892 # mshr miss rate for demand accesses 726system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for overall accesses 727system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.289892 # mshr miss rate for overall accesses 728system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average ReadReq mshr miss latency 729system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9122.663997 # average ReadReq mshr miss latency 730system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency 731system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency 732system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency 733system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency | 708system.cpu.itb_walker_cache.writebacks::writebacks 1982 # number of writebacks 709system.cpu.itb_walker_cache.writebacks::total 1982 # number of writebacks 710system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10341 # number of ReadReq MSHR misses 711system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10341 # number of ReadReq MSHR misses 712system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10341 # number of demand (read+write) MSHR misses 713system.cpu.itb_walker_cache.demand_mshr_misses::total 10341 # number of demand (read+write) MSHR misses 714system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10341 # number of overall MSHR misses 715system.cpu.itb_walker_cache.overall_mshr_misses::total 10341 # number of overall MSHR misses 716system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94976000 # number of ReadReq MSHR miss cycles 717system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94976000 # number of ReadReq MSHR miss cycles 718system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94976000 # number of demand (read+write) MSHR miss cycles 719system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94976000 # number of demand (read+write) MSHR miss cycles 720system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94976000 # number of overall MSHR miss cycles 721system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94976000 # number of overall MSHR miss cycles 722system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285908 # mshr miss rate for ReadReq accesses 723system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285908 # mshr miss rate for ReadReq accesses 724system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285892 # mshr miss rate for demand accesses 725system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285892 # mshr miss rate for demand accesses 726system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285892 # mshr miss rate for overall accesses 727system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285892 # mshr miss rate for overall accesses 728system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average ReadReq mshr miss latency 729system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9184.411566 # average ReadReq mshr miss latency 730system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average overall mshr miss latency 731system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9184.411566 # average overall mshr miss latency 732system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average overall mshr miss latency 733system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9184.411566 # average overall mshr miss latency |
| 734system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 734system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 735system.cpu.dtb_walker_cache.replacements 108181 # number of replacements 736system.cpu.dtb_walker_cache.tagsinuse 12.959012 # Cycle average of tags in use 737system.cpu.dtb_walker_cache.total_refs 134869 # Total number of references to valid blocks. 738system.cpu.dtb_walker_cache.sampled_refs 108196 # Sample count of references to valid blocks. 739system.cpu.dtb_walker_cache.avg_refs 1.246525 # Average number of references to valid blocks. | 735system.cpu.dtb_walker_cache.replacements 109668 # number of replacements 736system.cpu.dtb_walker_cache.tagsinuse 12.956689 # Cycle average of tags in use 737system.cpu.dtb_walker_cache.total_refs 133742 # Total number of references to valid blocks. 738system.cpu.dtb_walker_cache.sampled_refs 109682 # Sample count of references to valid blocks. 739system.cpu.dtb_walker_cache.avg_refs 1.219361 # Average number of references to valid blocks. |
| 740system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. | 740system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. |
| 741system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959012 # Average occupied blocks per requestor 742system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809938 # Average percentage of cache occupancy 743system.cpu.dtb_walker_cache.occ_percent::total 0.809938 # Average percentage of cache occupancy 744system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134886 # number of ReadReq hits 745system.cpu.dtb_walker_cache.ReadReq_hits::total 134886 # number of ReadReq hits 746system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134886 # number of demand (read+write) hits 747system.cpu.dtb_walker_cache.demand_hits::total 134886 # number of demand (read+write) hits 748system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134886 # number of overall hits 749system.cpu.dtb_walker_cache.overall_hits::total 134886 # number of overall hits 750system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109218 # number of ReadReq misses 751system.cpu.dtb_walker_cache.ReadReq_misses::total 109218 # number of ReadReq misses 752system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109218 # number of demand (read+write) misses 753system.cpu.dtb_walker_cache.demand_misses::total 109218 # number of demand (read+write) misses 754system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109218 # number of overall misses 755system.cpu.dtb_walker_cache.overall_misses::total 109218 # number of overall misses 756system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1375116000 # number of ReadReq miss cycles 757system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1375116000 # number of ReadReq miss cycles 758system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1375116000 # number of demand (read+write) miss cycles 759system.cpu.dtb_walker_cache.demand_miss_latency::total 1375116000 # number of demand (read+write) miss cycles 760system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1375116000 # number of overall miss cycles 761system.cpu.dtb_walker_cache.overall_miss_latency::total 1375116000 # number of overall miss cycles 762system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244104 # number of ReadReq accesses(hits+misses) 763system.cpu.dtb_walker_cache.ReadReq_accesses::total 244104 # number of ReadReq accesses(hits+misses) 764system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244104 # number of demand (read+write) accesses 765system.cpu.dtb_walker_cache.demand_accesses::total 244104 # number of demand (read+write) accesses 766system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244104 # number of overall (read+write) accesses 767system.cpu.dtb_walker_cache.overall_accesses::total 244104 # number of overall (read+write) accesses 768system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447424 # miss rate for ReadReq accesses 769system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447424 # miss rate for ReadReq accesses 770system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447424 # miss rate for demand accesses 771system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447424 # miss rate for demand accesses 772system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447424 # miss rate for overall accesses 773system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447424 # miss rate for overall accesses 774system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12590.561995 # average ReadReq miss latency 775system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12590.561995 # average ReadReq miss latency 776system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency 777system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12590.561995 # average overall miss latency 778system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency 779system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12590.561995 # average overall miss latency | 741system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.956689 # Average occupied blocks per requestor 742system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809793 # Average percentage of cache occupancy 743system.cpu.dtb_walker_cache.occ_percent::total 0.809793 # Average percentage of cache occupancy 744system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 133765 # number of ReadReq hits 745system.cpu.dtb_walker_cache.ReadReq_hits::total 133765 # number of ReadReq hits 746system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 133765 # number of demand (read+write) hits 747system.cpu.dtb_walker_cache.demand_hits::total 133765 # number of demand (read+write) hits 748system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 133765 # number of overall hits 749system.cpu.dtb_walker_cache.overall_hits::total 133765 # number of overall hits 750system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110693 # number of ReadReq misses 751system.cpu.dtb_walker_cache.ReadReq_misses::total 110693 # number of ReadReq misses 752system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110693 # number of demand (read+write) misses 753system.cpu.dtb_walker_cache.demand_misses::total 110693 # number of demand (read+write) misses 754system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110693 # number of overall misses 755system.cpu.dtb_walker_cache.overall_misses::total 110693 # number of overall misses 756system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1390562000 # number of ReadReq miss cycles 757system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1390562000 # number of ReadReq miss cycles 758system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1390562000 # number of demand (read+write) miss cycles 759system.cpu.dtb_walker_cache.demand_miss_latency::total 1390562000 # number of demand (read+write) miss cycles 760system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1390562000 # number of overall miss cycles 761system.cpu.dtb_walker_cache.overall_miss_latency::total 1390562000 # number of overall miss cycles 762system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244458 # number of ReadReq accesses(hits+misses) 763system.cpu.dtb_walker_cache.ReadReq_accesses::total 244458 # number of ReadReq accesses(hits+misses) 764system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244458 # number of demand (read+write) accesses 765system.cpu.dtb_walker_cache.demand_accesses::total 244458 # number of demand (read+write) accesses 766system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244458 # number of overall (read+write) accesses 767system.cpu.dtb_walker_cache.overall_accesses::total 244458 # number of overall (read+write) accesses 768system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452810 # miss rate for ReadReq accesses 769system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452810 # miss rate for ReadReq accesses 770system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452810 # miss rate for demand accesses 771system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452810 # miss rate for demand accesses 772system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452810 # miss rate for overall accesses 773system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452810 # miss rate for overall accesses 774system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12562.330048 # average ReadReq miss latency 775system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12562.330048 # average ReadReq miss latency 776system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12562.330048 # average overall miss latency 777system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12562.330048 # average overall miss latency 778system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12562.330048 # average overall miss latency 779system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12562.330048 # average overall miss latency |
| 780system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 781system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 783system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 785system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 787system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 780system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 781system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 783system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 785system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 787system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 788system.cpu.dtb_walker_cache.writebacks::writebacks 35252 # number of writebacks 789system.cpu.dtb_walker_cache.writebacks::total 35252 # number of writebacks 790system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109218 # number of ReadReq MSHR misses 791system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109218 # number of ReadReq MSHR misses 792system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109218 # number of demand (read+write) MSHR misses 793system.cpu.dtb_walker_cache.demand_mshr_misses::total 109218 # number of demand (read+write) MSHR misses 794system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109218 # number of overall MSHR misses 795system.cpu.dtb_walker_cache.overall_mshr_misses::total 109218 # number of overall MSHR misses 796system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of ReadReq MSHR miss cycles 797system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1156680000 # number of ReadReq MSHR miss cycles 798system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of demand (read+write) MSHR miss cycles 799system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1156680000 # number of demand (read+write) MSHR miss cycles 800system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of overall MSHR miss cycles 801system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1156680000 # number of overall MSHR miss cycles 802system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447424 # mshr miss rate for ReadReq accesses 804system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for demand accesses 805system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447424 # mshr miss rate for demand accesses 806system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for overall accesses 807system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447424 # mshr miss rate for overall accesses 808system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average ReadReq mshr miss latency 809system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10590.561995 # average ReadReq mshr miss latency 810system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency 811system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency 812system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency 813system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency | 788system.cpu.dtb_walker_cache.writebacks::writebacks 35480 # number of writebacks 789system.cpu.dtb_walker_cache.writebacks::total 35480 # number of writebacks 790system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110693 # number of ReadReq MSHR misses 791system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110693 # number of ReadReq MSHR misses 792system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110693 # number of demand (read+write) MSHR misses 793system.cpu.dtb_walker_cache.demand_mshr_misses::total 110693 # number of demand (read+write) MSHR misses 794system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110693 # number of overall MSHR misses 795system.cpu.dtb_walker_cache.overall_mshr_misses::total 110693 # number of overall MSHR misses 796system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of ReadReq MSHR miss cycles 797system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1169176000 # number of ReadReq MSHR miss cycles 798system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of demand (read+write) MSHR miss cycles 799system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1169176000 # number of demand (read+write) MSHR miss cycles 800system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of overall MSHR miss cycles 801system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1169176000 # number of overall MSHR miss cycles 802system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452810 # mshr miss rate for ReadReq accesses 804system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for demand accesses 805system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452810 # mshr miss rate for demand accesses 806system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for overall accesses 807system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452810 # mshr miss rate for overall accesses 808system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average ReadReq mshr miss latency 809system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.330048 # average ReadReq mshr miss latency 810system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average overall mshr miss latency 811system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10562.330048 # average overall mshr miss latency 812system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average overall mshr miss latency 813system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10562.330048 # average overall mshr miss latency |
| 814system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 814system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 815system.cpu.dcache.replacements 1660118 # number of replacements 816system.cpu.dcache.tagsinuse 511.992206 # Cycle average of tags in use 817system.cpu.dcache.total_refs 19078637 # Total number of references to valid blocks. 818system.cpu.dcache.sampled_refs 1660630 # Sample count of references to valid blocks. 819system.cpu.dcache.avg_refs 11.488795 # Average number of references to valid blocks. | 815system.cpu.dcache.replacements 1659150 # number of replacements 816system.cpu.dcache.tagsinuse 511.992464 # Cycle average of tags in use 817system.cpu.dcache.total_refs 19077771 # Total number of references to valid blocks. 818system.cpu.dcache.sampled_refs 1659662 # Sample count of references to valid blocks. 819system.cpu.dcache.avg_refs 11.494974 # Average number of references to valid blocks. |
| 820system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. | 820system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. |
| 821system.cpu.dcache.occ_blocks::cpu.data 511.992206 # Average occupied blocks per requestor | 821system.cpu.dcache.occ_blocks::cpu.data 511.992464 # Average occupied blocks per requestor |
| 822system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy 823system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy | 822system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy 823system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy |
| 824system.cpu.dcache.ReadReq_hits::cpu.data 10987895 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 10987895 # number of ReadReq hits 826system.cpu.dcache.WriteReq_hits::cpu.data 8085738 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 8085738 # number of WriteReq hits 828system.cpu.dcache.demand_hits::cpu.data 19073633 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 19073633 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 19073633 # number of overall hits 831system.cpu.dcache.overall_hits::total 19073633 # number of overall hits 832system.cpu.dcache.ReadReq_misses::cpu.data 2236252 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2236252 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 317957 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 317957 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2554209 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2554209 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2554209 # number of overall misses 839system.cpu.dcache.overall_misses::total 2554209 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 32134007500 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 32134007500 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 9664278994 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 9664278994 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 41798286494 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 41798286494 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 41798286494 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 41798286494 # number of overall miss cycles 848system.cpu.dcache.ReadReq_accesses::cpu.data 13224147 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 13224147 # number of ReadReq accesses(hits+misses) 850system.cpu.dcache.WriteReq_accesses::cpu.data 8403695 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 8403695 # number of WriteReq accesses(hits+misses) 852system.cpu.dcache.demand_accesses::cpu.data 21627842 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 21627842 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 21627842 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 21627842 # number of overall (read+write) accesses 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169104 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.169104 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037835 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.037835 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.118098 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.118098 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.118098 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.118098 # miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14369.582453 # average ReadReq miss latency 865system.cpu.dcache.ReadReq_avg_miss_latency::total 14369.582453 # average ReadReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30394.924452 # average WriteReq miss latency 867system.cpu.dcache.WriteReq_avg_miss_latency::total 30394.924452 # average WriteReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 16364.473892 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 16364.473892 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 400642 # number of cycles access was blocked | 824system.cpu.dcache.ReadReq_hits::cpu.data 10988579 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 10988579 # number of ReadReq hits 826system.cpu.dcache.WriteReq_hits::cpu.data 8084208 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 8084208 # number of WriteReq hits 828system.cpu.dcache.demand_hits::cpu.data 19072787 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 19072787 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 19072787 # number of overall hits 831system.cpu.dcache.overall_hits::total 19072787 # number of overall hits 832system.cpu.dcache.ReadReq_misses::cpu.data 2233798 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2233798 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 317777 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 317777 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2551575 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2551575 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2551575 # number of overall misses 839system.cpu.dcache.overall_misses::total 2551575 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 32133763000 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 32133763000 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 9654013491 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 9654013491 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 41787776491 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 41787776491 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 41787776491 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 41787776491 # number of overall miss cycles 848system.cpu.dcache.ReadReq_accesses::cpu.data 13222377 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 13222377 # number of ReadReq accesses(hits+misses) 850system.cpu.dcache.WriteReq_accesses::cpu.data 8401985 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 8401985 # number of WriteReq accesses(hits+misses) 852system.cpu.dcache.demand_accesses::cpu.data 21624362 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 21624362 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 21624362 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 21624362 # number of overall (read+write) accesses 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168941 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.168941 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037822 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.037822 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.117995 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.117995 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.117995 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.117995 # miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14385.259097 # average ReadReq miss latency 865system.cpu.dcache.ReadReq_avg_miss_latency::total 14385.259097 # average ReadReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30379.837090 # average WriteReq miss latency 867system.cpu.dcache.WriteReq_avg_miss_latency::total 30379.837090 # average WriteReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 16377.247971 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 16377.247971 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 16377.247971 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 16377.247971 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 403205 # number of cycles access was blocked |
| 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 874system.cpu.dcache.blocked::no_mshrs 42486 # number of cycles access was blocked | 874system.cpu.dcache.blocked::no_mshrs 42533 # number of cycles access was blocked |
| 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.429977 # average number of cycles each access was blocked | 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.479816 # average number of cycles each access was blocked |
| 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed | 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 880system.cpu.dcache.writebacks::writebacks 1561388 # number of writebacks 881system.cpu.dcache.writebacks::total 1561388 # number of writebacks 882system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864027 # number of ReadReq MSHR hits 883system.cpu.dcache.ReadReq_mshr_hits::total 864027 # number of ReadReq MSHR hits 884system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25006 # number of WriteReq MSHR hits 885system.cpu.dcache.WriteReq_mshr_hits::total 25006 # number of WriteReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 889033 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 889033 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 889033 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 889033 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1372225 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 1372225 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292951 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 292951 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 1665176 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 1665176 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 1665176 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 1665176 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17481793000 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 17481793000 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8820305494 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 8820305494 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26302098494 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 26302098494 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26302098494 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 26302098494 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296698500 # number of ReadReq MSHR uncacheable cycles 907system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296698500 # number of ReadReq MSHR uncacheable cycles 908system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470686500 # number of WriteReq MSHR uncacheable cycles 909system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470686500 # number of WriteReq MSHR uncacheable cycles 910system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767385000 # number of overall MSHR uncacheable cycles 911system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767385000 # number of overall MSHR uncacheable cycles 912system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103767 # mshr miss rate for ReadReq accesses 913system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103767 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034860 # mshr miss rate for WriteReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034860 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for demand accesses 917system.cpu.dcache.demand_mshr_miss_rate::total 0.076992 # mshr miss rate for demand accesses 918system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for overall accesses 919system.cpu.dcache.overall_mshr_miss_rate::total 0.076992 # mshr miss rate for overall accesses 920system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12739.742389 # average ReadReq mshr miss latency 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12739.742389 # average ReadReq mshr miss latency 922system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30108.466925 # average WriteReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30108.466925 # average WriteReq mshr miss latency 924system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency 926system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency | 880system.cpu.dcache.writebacks::writebacks 1560680 # number of writebacks 881system.cpu.dcache.writebacks::total 1560680 # number of writebacks 882system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862352 # number of ReadReq MSHR hits 883system.cpu.dcache.ReadReq_mshr_hits::total 862352 # number of ReadReq MSHR hits 884system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25015 # number of WriteReq MSHR hits 885system.cpu.dcache.WriteReq_mshr_hits::total 25015 # number of WriteReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 887367 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 887367 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 887367 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 887367 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371446 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 1371446 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292762 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 292762 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 1664208 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 1664208 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 1664208 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 1664208 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17485386500 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 17485386500 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8810445491 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 8810445491 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26295831991 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 26295831991 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26295831991 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 26295831991 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296686000 # number of ReadReq MSHR uncacheable cycles 907system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296686000 # number of ReadReq MSHR uncacheable cycles 908system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470456500 # number of WriteReq MSHR uncacheable cycles 909system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470456500 # number of WriteReq MSHR uncacheable cycles 910system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767142500 # number of overall MSHR uncacheable cycles 911system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767142500 # number of overall MSHR uncacheable cycles 912system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103722 # mshr miss rate for ReadReq accesses 913system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103722 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034844 # mshr miss rate for WriteReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034844 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076960 # mshr miss rate for demand accesses 917system.cpu.dcache.demand_mshr_miss_rate::total 0.076960 # mshr miss rate for demand accesses 918system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076960 # mshr miss rate for overall accesses 919system.cpu.dcache.overall_mshr_miss_rate::total 0.076960 # mshr miss rate for overall accesses 920system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12749.598963 # average ReadReq mshr miss latency 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12749.598963 # average ReadReq mshr miss latency 922system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30094.224971 # average WriteReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30094.224971 # average WriteReq mshr miss latency 924system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.808547 # average overall mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.808547 # average overall mshr miss latency 926system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.808547 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.808547 # average overall mshr miss latency |
| 928system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 929system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 930system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 931system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 932system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 933system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 928system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 929system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 930system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 931system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 932system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 933system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 935system.cpu.l2cache.replacements 113561 # number of replacements 936system.cpu.l2cache.tagsinuse 64842.483679 # Cycle average of tags in use 937system.cpu.l2cache.total_refs 3930962 # Total number of references to valid blocks. 938system.cpu.l2cache.sampled_refs 177626 # Sample count of references to valid blocks. 939system.cpu.l2cache.avg_refs 22.130555 # Average number of references to valid blocks. | 935system.cpu.l2cache.replacements 113397 # number of replacements 936system.cpu.l2cache.tagsinuse 64842.962658 # Cycle average of tags in use 937system.cpu.l2cache.total_refs 3927368 # Total number of references to valid blocks. 938system.cpu.l2cache.sampled_refs 177482 # Sample count of references to valid blocks. 939system.cpu.l2cache.avg_refs 22.128261 # Average number of references to valid blocks. |
| 940system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 940system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 941system.cpu.l2cache.occ_blocks::writebacks 50033.446344 # Average occupied blocks per requestor 942system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.888296 # Average occupied blocks per requestor 943system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133449 # Average occupied blocks per requestor 944system.cpu.l2cache.occ_blocks::cpu.inst 3280.677554 # Average occupied blocks per requestor 945system.cpu.l2cache.occ_blocks::cpu.data 11517.338036 # Average occupied blocks per requestor 946system.cpu.l2cache.occ_percent::writebacks 0.763450 # Average percentage of cache occupancy | 941system.cpu.l2cache.occ_blocks::writebacks 50042.897281 # Average occupied blocks per requestor 942system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.875640 # Average occupied blocks per requestor 943system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131992 # Average occupied blocks per requestor 944system.cpu.l2cache.occ_blocks::cpu.inst 3274.977227 # Average occupied blocks per requestor 945system.cpu.l2cache.occ_blocks::cpu.data 11514.080519 # Average occupied blocks per requestor 946system.cpu.l2cache.occ_percent::writebacks 0.763594 # Average percentage of cache occupancy |
| 947system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy 948system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 947system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy 948system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 949system.cpu.l2cache.occ_percent::cpu.inst 0.050059 # Average percentage of cache occupancy 950system.cpu.l2cache.occ_percent::cpu.data 0.175741 # Average percentage of cache occupancy 951system.cpu.l2cache.occ_percent::total 0.989418 # Average percentage of cache occupancy 952system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102246 # number of ReadReq hits 953system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8058 # number of ReadReq hits 954system.cpu.l2cache.ReadReq_hits::cpu.inst 1029420 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.data 1334149 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 2473873 # number of ReadReq hits 957system.cpu.l2cache.Writeback_hits::writebacks 1598576 # number of Writeback hits 958system.cpu.l2cache.Writeback_hits::total 1598576 # number of Writeback hits 959system.cpu.l2cache.UpgradeReq_hits::cpu.data 345 # number of UpgradeReq hits 960system.cpu.l2cache.UpgradeReq_hits::total 345 # number of UpgradeReq hits 961system.cpu.l2cache.ReadExReq_hits::cpu.data 156103 # number of ReadExReq hits 962system.cpu.l2cache.ReadExReq_hits::total 156103 # number of ReadExReq hits 963system.cpu.l2cache.demand_hits::cpu.dtb.walker 102246 # number of demand (read+write) hits 964system.cpu.l2cache.demand_hits::cpu.itb.walker 8058 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.inst 1029420 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1490252 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2629976 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.dtb.walker 102246 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.itb.walker 8058 # number of overall hits 970system.cpu.l2cache.overall_hits::cpu.inst 1029420 # number of overall hits 971system.cpu.l2cache.overall_hits::cpu.data 1490252 # number of overall hits 972system.cpu.l2cache.overall_hits::total 2629976 # number of overall hits 973system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses | 949system.cpu.l2cache.occ_percent::cpu.inst 0.049972 # Average percentage of cache occupancy 950system.cpu.l2cache.occ_percent::cpu.data 0.175691 # Average percentage of cache occupancy 951system.cpu.l2cache.occ_percent::total 0.989425 # Average percentage of cache occupancy 952system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103288 # number of ReadReq hits 953system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8019 # number of ReadReq hits 954system.cpu.l2cache.ReadReq_hits::cpu.inst 1029235 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.data 1333401 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 2473943 # number of ReadReq hits 957system.cpu.l2cache.Writeback_hits::writebacks 1598142 # number of Writeback hits 958system.cpu.l2cache.Writeback_hits::total 1598142 # number of Writeback hits 959system.cpu.l2cache.UpgradeReq_hits::cpu.data 335 # number of UpgradeReq hits 960system.cpu.l2cache.UpgradeReq_hits::total 335 # number of UpgradeReq hits 961system.cpu.l2cache.ReadExReq_hits::cpu.data 156168 # number of ReadExReq hits 962system.cpu.l2cache.ReadExReq_hits::total 156168 # number of ReadExReq hits 963system.cpu.l2cache.demand_hits::cpu.dtb.walker 103288 # number of demand (read+write) hits 964system.cpu.l2cache.demand_hits::cpu.itb.walker 8019 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.inst 1029235 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1489569 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2630111 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.dtb.walker 103288 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.itb.walker 8019 # number of overall hits 970system.cpu.l2cache.overall_hits::cpu.inst 1029235 # number of overall hits 971system.cpu.l2cache.overall_hits::cpu.data 1489569 # number of overall hits 972system.cpu.l2cache.overall_hits::total 2630111 # number of overall hits 973system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 50 # number of ReadReq misses |
| 974system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses | 974system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses |
| 975system.cpu.l2cache.ReadReq_misses::cpu.inst 16841 # number of ReadReq misses 976system.cpu.l2cache.ReadReq_misses::cpu.data 36881 # number of ReadReq misses 977system.cpu.l2cache.ReadReq_misses::total 53777 # number of ReadReq misses 978system.cpu.l2cache.UpgradeReq_misses::cpu.data 3693 # number of UpgradeReq misses 979system.cpu.l2cache.UpgradeReq_misses::total 3693 # number of UpgradeReq misses 980system.cpu.l2cache.ReadExReq_misses::cpu.data 132888 # number of ReadExReq misses 981system.cpu.l2cache.ReadExReq_misses::total 132888 # number of ReadExReq misses 982system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses | 975system.cpu.l2cache.ReadReq_misses::cpu.inst 16847 # number of ReadReq misses 976system.cpu.l2cache.ReadReq_misses::cpu.data 36871 # number of ReadReq misses 977system.cpu.l2cache.ReadReq_misses::total 53774 # number of ReadReq misses 978system.cpu.l2cache.UpgradeReq_misses::cpu.data 3714 # number of UpgradeReq misses 979system.cpu.l2cache.UpgradeReq_misses::total 3714 # number of UpgradeReq misses 980system.cpu.l2cache.ReadExReq_misses::cpu.data 132646 # number of ReadExReq misses 981system.cpu.l2cache.ReadExReq_misses::total 132646 # number of ReadExReq misses 982system.cpu.l2cache.demand_misses::cpu.dtb.walker 50 # number of demand (read+write) misses |
| 983system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses | 983system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses |
| 984system.cpu.l2cache.demand_misses::cpu.inst 16841 # number of demand (read+write) misses 985system.cpu.l2cache.demand_misses::cpu.data 169769 # number of demand (read+write) misses 986system.cpu.l2cache.demand_misses::total 186665 # number of demand (read+write) misses 987system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses | 984system.cpu.l2cache.demand_misses::cpu.inst 16847 # number of demand (read+write) misses 985system.cpu.l2cache.demand_misses::cpu.data 169517 # number of demand (read+write) misses 986system.cpu.l2cache.demand_misses::total 186420 # number of demand (read+write) misses 987system.cpu.l2cache.overall_misses::cpu.dtb.walker 50 # number of overall misses |
| 988system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses | 988system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses |
| 989system.cpu.l2cache.overall_misses::cpu.inst 16841 # number of overall misses 990system.cpu.l2cache.overall_misses::cpu.data 169769 # number of overall misses 991system.cpu.l2cache.overall_misses::total 186665 # number of overall misses 992system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6312000 # number of ReadReq miss cycles | 989system.cpu.l2cache.overall_misses::cpu.inst 16847 # number of overall misses 990system.cpu.l2cache.overall_misses::cpu.data 169517 # number of overall misses 991system.cpu.l2cache.overall_misses::total 186420 # number of overall misses 992system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6252000 # number of ReadReq miss cycles |
| 993system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles | 993system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles |
| 994system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1177562500 # number of ReadReq miss cycles 995system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2538376499 # number of ReadReq miss cycles 996system.cpu.l2cache.ReadReq_miss_latency::total 3722640499 # number of ReadReq miss cycles 997system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16930000 # number of UpgradeReq miss cycles 998system.cpu.l2cache.UpgradeReq_miss_latency::total 16930000 # number of UpgradeReq miss cycles 999system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6874050999 # number of ReadExReq miss cycles 1000system.cpu.l2cache.ReadExReq_miss_latency::total 6874050999 # number of ReadExReq miss cycles 1001system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6312000 # number of demand (read+write) miss cycles | 994system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1171120500 # number of ReadReq miss cycles 995system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2550395499 # number of ReadReq miss cycles 996system.cpu.l2cache.ReadReq_miss_latency::total 3728157499 # number of ReadReq miss cycles 997system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17029000 # number of UpgradeReq miss cycles 998system.cpu.l2cache.UpgradeReq_miss_latency::total 17029000 # number of UpgradeReq miss cycles 999system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6863407500 # number of ReadExReq miss cycles 1000system.cpu.l2cache.ReadExReq_miss_latency::total 6863407500 # number of ReadExReq miss cycles 1001system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6252000 # number of demand (read+write) miss cycles |
| 1002system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles | 1002system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles |
| 1003system.cpu.l2cache.demand_miss_latency::cpu.inst 1177562500 # number of demand (read+write) miss cycles 1004system.cpu.l2cache.demand_miss_latency::cpu.data 9412427498 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.demand_miss_latency::total 10596691498 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6312000 # number of overall miss cycles | 1003system.cpu.l2cache.demand_miss_latency::cpu.inst 1171120500 # number of demand (read+write) miss cycles 1004system.cpu.l2cache.demand_miss_latency::cpu.data 9413802999 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.demand_miss_latency::total 10591564999 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6252000 # number of overall miss cycles |
| 1007system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles | 1007system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles |
| 1008system.cpu.l2cache.overall_miss_latency::cpu.inst 1177562500 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.data 9412427498 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::total 10596691498 # number of overall miss cycles 1011system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 102295 # number of ReadReq accesses(hits+misses) 1012system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8064 # number of ReadReq accesses(hits+misses) 1013system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046261 # number of ReadReq accesses(hits+misses) 1014system.cpu.l2cache.ReadReq_accesses::cpu.data 1371030 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::total 2527650 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.Writeback_accesses::writebacks 1598576 # number of Writeback accesses(hits+misses) 1017system.cpu.l2cache.Writeback_accesses::total 1598576 # number of Writeback accesses(hits+misses) 1018system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4038 # number of UpgradeReq accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::total 4038 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.ReadExReq_accesses::cpu.data 288991 # number of ReadExReq accesses(hits+misses) 1021system.cpu.l2cache.ReadExReq_accesses::total 288991 # number of ReadExReq accesses(hits+misses) 1022system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102295 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::cpu.itb.walker 8064 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.inst 1046261 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 1660021 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 2816641 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102295 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.itb.walker 8064 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.inst 1046261 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::cpu.data 1660021 # number of overall (read+write) accesses 1031system.cpu.l2cache.overall_accesses::total 2816641 # number of overall (read+write) accesses 1032system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000479 # miss rate for ReadReq accesses 1033system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000744 # miss rate for ReadReq accesses 1034system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016096 # miss rate for ReadReq accesses 1035system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026900 # miss rate for ReadReq accesses 1036system.cpu.l2cache.ReadReq_miss_rate::total 0.021275 # miss rate for ReadReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.914562 # miss rate for UpgradeReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::total 0.914562 # miss rate for UpgradeReq accesses 1039system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459834 # miss rate for ReadExReq accesses 1040system.cpu.l2cache.ReadExReq_miss_rate::total 0.459834 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000479 # miss rate for demand accesses 1042system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000744 # miss rate for demand accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016096 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.data 0.102269 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::total 0.066272 # miss rate for demand accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000479 # miss rate for overall accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000744 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016096 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.data 0.102269 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::total 0.066272 # miss rate for overall accesses 1051system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 128816.326531 # average ReadReq miss latency | 1008system.cpu.l2cache.overall_miss_latency::cpu.inst 1171120500 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.data 9413802999 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::total 10591564999 # number of overall miss cycles 1011system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103338 # number of ReadReq accesses(hits+misses) 1012system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8025 # number of ReadReq accesses(hits+misses) 1013system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046082 # number of ReadReq accesses(hits+misses) 1014system.cpu.l2cache.ReadReq_accesses::cpu.data 1370272 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::total 2527717 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.Writeback_accesses::writebacks 1598142 # number of Writeback accesses(hits+misses) 1017system.cpu.l2cache.Writeback_accesses::total 1598142 # number of Writeback accesses(hits+misses) 1018system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4049 # number of UpgradeReq accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::total 4049 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.ReadExReq_accesses::cpu.data 288814 # number of ReadExReq accesses(hits+misses) 1021system.cpu.l2cache.ReadExReq_accesses::total 288814 # number of ReadExReq accesses(hits+misses) 1022system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103338 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::cpu.itb.walker 8025 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.inst 1046082 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 1659086 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 2816531 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103338 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.itb.walker 8025 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.inst 1046082 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::cpu.data 1659086 # number of overall (read+write) accesses 1031system.cpu.l2cache.overall_accesses::total 2816531 # number of overall (read+write) accesses 1032system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses 1033system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000748 # miss rate for ReadReq accesses 1034system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016105 # miss rate for ReadReq accesses 1035system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026908 # miss rate for ReadReq accesses 1036system.cpu.l2cache.ReadReq_miss_rate::total 0.021274 # miss rate for ReadReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.917264 # miss rate for UpgradeReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::total 0.917264 # miss rate for UpgradeReq accesses 1039system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459278 # miss rate for ReadExReq accesses 1040system.cpu.l2cache.ReadExReq_miss_rate::total 0.459278 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses 1042system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000748 # miss rate for demand accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016105 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.data 0.102175 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::total 0.066188 # miss rate for demand accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000748 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016105 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.data 0.102175 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::total 0.066188 # miss rate for overall accesses 1051system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 125040 # average ReadReq miss latency |
| 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency | 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency |
| 1053system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69922.362093 # average ReadReq miss latency 1054system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68826.129959 # average ReadReq miss latency 1055system.cpu.l2cache.ReadReq_avg_miss_latency::total 69223.655076 # average ReadReq miss latency 1056system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4584.348768 # average UpgradeReq miss latency 1057system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4584.348768 # average UpgradeReq miss latency 1058system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51728.154529 # average ReadExReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51728.154529 # average ReadExReq miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency | 1053system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69515.076868 # average ReadReq miss latency 1054system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69170.771040 # average ReadReq miss latency 1055system.cpu.l2cache.ReadReq_avg_miss_latency::total 69330.113047 # average ReadReq miss latency 1056system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4585.083468 # average UpgradeReq miss latency 1057system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4585.083468 # average UpgradeReq miss latency 1058system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51742.287743 # average ReadExReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51742.287743 # average ReadExReq miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 125040 # average overall miss latency |
| 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency | 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency |
| 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency 1064system.cpu.l2cache.demand_avg_miss_latency::total 56768.497029 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency | 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69515.076868 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55533.091071 # average overall miss latency 1064system.cpu.l2cache.demand_avg_miss_latency::total 56815.604544 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 125040 # average overall miss latency |
| 1066system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency | 1066system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency |
| 1067system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency 1069system.cpu.l2cache.overall_avg_miss_latency::total 56768.497029 # average overall miss latency | 1067system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69515.076868 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55533.091071 # average overall miss latency 1069system.cpu.l2cache.overall_avg_miss_latency::total 56815.604544 # average overall miss latency |
| 1070system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1077system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1070system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1077system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1078system.cpu.l2cache.writebacks::writebacks 102810 # number of writebacks 1079system.cpu.l2cache.writebacks::total 102810 # number of writebacks | 1078system.cpu.l2cache.writebacks::writebacks 102711 # number of writebacks 1079system.cpu.l2cache.writebacks::total 102711 # number of writebacks |
| 1080system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1081system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1082system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1083system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1084system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1085system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 1086system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1087system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1088system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits | 1080system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1081system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1082system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1083system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1084system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1085system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 1086system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1087system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1088system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits |
| 1089system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses | 1089system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 50 # number of ReadReq MSHR misses |
| 1090system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses | 1090system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses |
| 1091system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16840 # number of ReadReq MSHR misses 1092system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36880 # number of ReadReq MSHR misses 1093system.cpu.l2cache.ReadReq_mshr_misses::total 53775 # number of ReadReq MSHR misses 1094system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3693 # number of UpgradeReq MSHR misses 1095system.cpu.l2cache.UpgradeReq_mshr_misses::total 3693 # number of UpgradeReq MSHR misses 1096system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132888 # number of ReadExReq MSHR misses 1097system.cpu.l2cache.ReadExReq_mshr_misses::total 132888 # number of ReadExReq MSHR misses 1098system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses | 1091system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16846 # number of ReadReq MSHR misses 1092system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36870 # number of ReadReq MSHR misses 1093system.cpu.l2cache.ReadReq_mshr_misses::total 53772 # number of ReadReq MSHR misses 1094system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3714 # number of UpgradeReq MSHR misses 1095system.cpu.l2cache.UpgradeReq_mshr_misses::total 3714 # number of UpgradeReq MSHR misses 1096system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132646 # number of ReadExReq MSHR misses 1097system.cpu.l2cache.ReadExReq_mshr_misses::total 132646 # number of ReadExReq MSHR misses 1098system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 50 # number of demand (read+write) MSHR misses |
| 1099system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses | 1099system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses |
| 1100system.cpu.l2cache.demand_mshr_misses::cpu.inst 16840 # number of demand (read+write) MSHR misses 1101system.cpu.l2cache.demand_mshr_misses::cpu.data 169768 # number of demand (read+write) MSHR misses 1102system.cpu.l2cache.demand_mshr_misses::total 186663 # number of demand (read+write) MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses | 1100system.cpu.l2cache.demand_mshr_misses::cpu.inst 16846 # number of demand (read+write) MSHR misses 1101system.cpu.l2cache.demand_mshr_misses::cpu.data 169516 # number of demand (read+write) MSHR misses 1102system.cpu.l2cache.demand_mshr_misses::total 186418 # number of demand (read+write) MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 50 # number of overall MSHR misses |
| 1104system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses | 1104system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses |
| 1105system.cpu.l2cache.overall_mshr_misses::cpu.inst 16840 # number of overall MSHR misses 1106system.cpu.l2cache.overall_mshr_misses::cpu.data 169768 # number of overall MSHR misses 1107system.cpu.l2cache.overall_mshr_misses::total 186663 # number of overall MSHR misses 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5701045 # number of ReadReq MSHR miss cycles | 1105system.cpu.l2cache.overall_mshr_misses::cpu.inst 16846 # number of overall MSHR misses 1106system.cpu.l2cache.overall_mshr_misses::cpu.data 169516 # number of overall MSHR misses 1107system.cpu.l2cache.overall_mshr_misses::total 186418 # number of overall MSHR misses 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5629796 # number of ReadReq MSHR miss cycles |
| 1109system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles | 1109system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles |
| 1110system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 968087231 # number of ReadReq MSHR miss cycles 1111system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2080048452 # number of ReadReq MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3054150983 # number of ReadReq MSHR miss cycles 1113system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37901173 # number of UpgradeReq MSHR miss cycles 1114system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37901173 # number of UpgradeReq MSHR miss cycles 1115system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235111902 # number of ReadExReq MSHR miss cycles 1116system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235111902 # number of ReadExReq MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5701045 # number of demand (read+write) MSHR miss cycles | 1110system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 961575741 # number of ReadReq MSHR miss cycles 1111system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2092180467 # number of ReadReq MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3059700259 # number of ReadReq MSHR miss cycles 1113system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 38132194 # number of UpgradeReq MSHR miss cycles 1114system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 38132194 # number of UpgradeReq MSHR miss cycles 1115system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5227507665 # number of ReadExReq MSHR miss cycles 1116system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5227507665 # number of ReadExReq MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5629796 # number of demand (read+write) MSHR miss cycles |
| 1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles | 1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles |
| 1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 968087231 # number of demand (read+write) MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7315160354 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.demand_mshr_miss_latency::total 8289262885 # number of demand (read+write) MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5701045 # number of overall MSHR miss cycles | 1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 961575741 # number of demand (read+write) MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7319688132 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.demand_mshr_miss_latency::total 8287207924 # number of demand (read+write) MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5629796 # number of overall MSHR miss cycles |
| 1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles | 1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles |
| 1124system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 968087231 # number of overall MSHR miss cycles 1125system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7315160354 # number of overall MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::total 8289262885 # number of overall MSHR miss cycles 1127system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187415500 # number of ReadReq MSHR uncacheable cycles 1128system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187415500 # number of ReadReq MSHR uncacheable cycles 1129system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308505000 # number of WriteReq MSHR uncacheable cycles 1130system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308505000 # number of WriteReq MSHR uncacheable cycles 1131system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495920500 # number of overall MSHR uncacheable cycles 1132system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495920500 # number of overall MSHR uncacheable cycles 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for ReadReq accesses 1135system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for ReadReq accesses 1136system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026899 # mshr miss rate for ReadReq accesses 1137system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021275 # mshr miss rate for ReadReq accesses 1138system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.914562 # mshr miss rate for UpgradeReq accesses 1139system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.914562 # mshr miss rate for UpgradeReq accesses 1140system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459834 # mshr miss rate for ReadExReq accesses 1141system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459834 # mshr miss rate for ReadExReq accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for demand accesses 1145system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for demand accesses 1146system.cpu.l2cache.demand_mshr_miss_rate::total 0.066271 # mshr miss rate for demand accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for overall accesses 1149system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for overall accesses 1150system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for overall accesses 1151system.cpu.l2cache.overall_mshr_miss_rate::total 0.066271 # mshr miss rate for overall accesses 1152system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average ReadReq mshr miss latency | 1124system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 961575741 # number of overall MSHR miss cycles 1125system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7319688132 # number of overall MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::total 8287207924 # number of overall MSHR miss cycles 1127system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187404000 # number of ReadReq MSHR uncacheable cycles 1128system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187404000 # number of ReadReq MSHR uncacheable cycles 1129system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308295000 # number of WriteReq MSHR uncacheable cycles 1130system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308295000 # number of WriteReq MSHR uncacheable cycles 1131system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495699000 # number of overall MSHR uncacheable cycles 1132system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495699000 # number of overall MSHR uncacheable cycles 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for ReadReq accesses 1135system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for ReadReq accesses 1136system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026907 # mshr miss rate for ReadReq accesses 1137system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021273 # mshr miss rate for ReadReq accesses 1138system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.917264 # mshr miss rate for UpgradeReq accesses 1139system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.917264 # mshr miss rate for UpgradeReq accesses 1140system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459278 # mshr miss rate for ReadExReq accesses 1141system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459278 # mshr miss rate for ReadExReq accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for demand accesses 1145system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102174 # mshr miss rate for demand accesses 1146system.cpu.l2cache.demand_mshr_miss_rate::total 0.066187 # mshr miss rate for demand accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for overall accesses 1149system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for overall accesses 1150system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102174 # mshr miss rate for overall accesses 1151system.cpu.l2cache.overall_mshr_miss_rate::total 0.066187 # mshr miss rate for overall accesses 1152system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average ReadReq mshr miss latency |
| 1153system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency | 1153system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency |
| 1154system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57487.365261 # average ReadReq mshr miss latency 1155system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56400.446095 # average ReadReq mshr miss latency 1156system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56794.997359 # average ReadReq mshr miss latency 1157system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.976713 # average UpgradeReq mshr miss latency 1158system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.976713 # average UpgradeReq mshr miss latency 1159system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39394.918292 # average ReadExReq mshr miss latency 1160system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39394.918292 # average ReadExReq mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency | 1154system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57080.359789 # average ReadReq mshr miss latency 1155system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56744.791619 # average ReadReq mshr miss latency 1156system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56901.366120 # average ReadReq mshr miss latency 1157system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10267.149704 # average UpgradeReq mshr miss latency 1158system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10267.149704 # average UpgradeReq mshr miss latency 1159system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39409.463271 # average ReadExReq mshr miss latency 1160system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39409.463271 # average ReadExReq mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average overall mshr miss latency |
| 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency | 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency |
| 1163system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency 1164system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency 1165system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency | 1163system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57080.359789 # average overall mshr miss latency 1164system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43179.924798 # average overall mshr miss latency 1165system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44454.977116 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average overall mshr miss latency |
| 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency | 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency |
| 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency 1169system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency 1170system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency | 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57080.359789 # average overall mshr miss latency 1169system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43179.924798 # average overall mshr miss latency 1170system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44454.977116 # average overall mshr miss latency |
| 1171system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1172system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1173system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1174system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1175system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1176system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1177system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1178system.cpu.kern.inst.arm 0 # number of arm instructions executed 1179system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1180 1181---------- End Simulation Statistics ---------- | 1171system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1172system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1173system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1174system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1175system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1176system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1177system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1178system.cpu.kern.inst.arm 0 # number of arm instructions executed 1179system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1180 1181---------- End Simulation Statistics ---------- |