| stats.txt (9536:8149223cd7db) | stats.txt (9568:cd1351d4d850) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.140861 # Number of seconds simulated 4sim_ticks 5140860798000 # Number of ticks simulated 5final_tick 5140860798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.136865 # Number of seconds simulated 4sim_ticks 5136864535500 # Number of ticks simulated 5final_tick 5136864535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 170494 # Simulator instruction rate (inst/s) 8host_op_rate 337025 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2148706625 # Simulator tick rate (ticks/s) 10host_mem_usage 754648 # Number of bytes of host memory used 11host_seconds 2392.54 # Real time elapsed on the host 12sim_insts 407913764 # Number of instructions simulated 13sim_ops 806343994 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2474560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory | 7host_inst_rate 199949 # Simulator instruction rate (inst/s) 8host_op_rate 395248 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2517891877 # Simulator tick rate (ticks/s) 10host_mem_usage 755196 # Number of bytes of host memory used 11host_seconds 2040.15 # Real time elapsed on the host 12sim_insts 407925588 # Number of instructions simulated 13sim_ops 806363480 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2498048 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 1078400 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10800768 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14357184 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1078400 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1078400 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9566720 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9566720 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38665 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 1077760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10804608 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14383936 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1077760 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1077760 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9566528 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9566528 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 39032 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.inst 16850 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168762 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 224331 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149480 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149480 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 481351 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 598 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::cpu.inst 16840 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168822 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 224749 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149477 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149477 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 486298 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.inst 209770 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2100965 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2792759 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 209770 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 209770 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1860918 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1860918 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1860918 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 481351 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 598 # Total bandwidth to/from this memory (bytes/s) | 35system.physmem.bw_read::cpu.inst 209809 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2103347 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2800139 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 209809 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 209809 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1862328 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1862328 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1862328 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 486298 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) |
| 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.inst 209770 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2100965 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4653677 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 224331 # Total number of read requests seen 50system.physmem.writeReqs 149480 # Total number of write requests seen 51system.physmem.cpureqs 389156 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14357184 # Total number of bytes read from memory 53system.physmem.bytesWritten 9566720 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14357184 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9566720 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 64 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 4099 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 14350 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 13262 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 13450 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 16479 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13640 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 13135 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13368 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 16367 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13625 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 12973 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13147 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 15567 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13297 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 12659 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13305 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15643 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 9342 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 8759 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8814 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 11838 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8747 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 8497 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8701 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 11708 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8726 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8403 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 8587 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 10999 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8504 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 8205 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8619 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 11031 # Track writes on a per bank basis | 46system.physmem.bw_total::cpu.inst 209809 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2103347 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4662468 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 224749 # Total number of read requests seen 50system.physmem.writeReqs 149477 # Total number of write requests seen 51system.physmem.cpureqs 378758 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14383936 # Total number of bytes read from memory 53system.physmem.bytesWritten 9566528 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14383936 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9566528 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 3970 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 14108 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 13038 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 13174 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 16315 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13707 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 13158 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13525 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 16255 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13935 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 13285 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13290 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 15648 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13203 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 12660 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13428 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15923 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 9005 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 8432 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8529 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 11625 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8800 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 8560 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8903 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 11692 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 9007 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8684 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 8693 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 11170 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8382 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 8108 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8695 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 11192 # Track writes on a per bank basis |
| 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 91system.physmem.numWrRetry 1147 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5140860745500 # Total gap between requests | 91system.physmem.numWrRetry 562 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5136864483000 # Total gap between requests |
| 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes | 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 99system.physmem.readPktSize::6 224331 # Categorize read packet sizes 100system.physmem.readPktSize::7 0 # Categorize read packet sizes 101system.physmem.readPktSize::8 0 # Categorize read packet sizes 102system.physmem.writePktSize::0 0 # categorize write packet sizes 103system.physmem.writePktSize::1 0 # categorize write packet sizes 104system.physmem.writePktSize::2 0 # categorize write packet sizes 105system.physmem.writePktSize::3 0 # categorize write packet sizes 106system.physmem.writePktSize::4 0 # categorize write packet sizes 107system.physmem.writePktSize::5 0 # categorize write packet sizes 108system.physmem.writePktSize::6 150627 # categorize write packet sizes 109system.physmem.writePktSize::7 0 # categorize write packet sizes 110system.physmem.writePktSize::8 0 # categorize write packet sizes 111system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 112system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 113system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::6 4099 # categorize neither packet sizes 118system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 120system.physmem.rdQLenPdf::0 173172 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::1 19537 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::2 7348 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::3 3492 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::4 2979 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::5 2415 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::7 1865 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::8 1784 # What read queue length does an incoming req see | 99system.physmem.readPktSize::6 224749 # Categorize read packet sizes 100system.physmem.writePktSize::0 0 # Categorize write packet sizes 101system.physmem.writePktSize::1 0 # Categorize write packet sizes 102system.physmem.writePktSize::2 0 # Categorize write packet sizes 103system.physmem.writePktSize::3 0 # Categorize write packet sizes 104system.physmem.writePktSize::4 0 # Categorize write packet sizes 105system.physmem.writePktSize::5 0 # Categorize write packet sizes 106system.physmem.writePktSize::6 149477 # Categorize write packet sizes 107system.physmem.rdQLenPdf::0 173174 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 19685 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 3521 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 3015 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 2402 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1894 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1830 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1773 # What read queue length does an incoming req see |
| 129system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see | 116system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see |
| 130system.physmem.rdQLenPdf::10 1139 # What read queue length does an incoming req see | 117system.physmem.rdQLenPdf::10 1145 # What read queue length does an incoming req see |
| 131system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see | 118system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see |
| 132system.physmem.rdQLenPdf::12 969 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::13 886 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::14 806 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::15 796 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::16 879 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::17 856 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::18 418 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::19 233 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::20 28 # What read queue length does an incoming req see | 119system.physmem.rdQLenPdf::12 964 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 885 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::15 809 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::16 906 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::17 870 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::18 386 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::19 240 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see |
| 141system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 128system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 152system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 153system.physmem.wrQLenPdf::0 5364 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::1 5718 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::2 6328 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::3 6401 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::4 6443 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::5 6469 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::6 6476 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see | 139system.physmem.wrQLenPdf::0 5359 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::1 5713 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::2 6316 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::3 6398 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::4 6438 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::5 6479 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::6 6486 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::7 6489 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 6490 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see |
| 176system.physmem.wrQLenPdf::23 1136 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::25 172 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::26 98 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 186system.physmem.totQLat 4794174501 # Total cycles spent in queuing delays 187system.physmem.totMemAccLat 9303317001 # Sum of mem lat for all requests 188system.physmem.totBusLat 1121335000 # Total cycles spent in databus access 189system.physmem.totBankLat 3387807500 # Total cycles spent in bank access 190system.physmem.avgQLat 21377.08 # Average queueing delay per request 191system.physmem.avgBankLat 15106.13 # Average bank access latency per request | 162system.physmem.wrQLenPdf::23 1140 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 786 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 183 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 101 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see 171system.physmem.totQLat 4764271250 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 9277483750 # Sum of mem lat for all requests 173system.physmem.totBusLat 1123260000 # Total cycles spent in databus access 174system.physmem.totBankLat 3389952500 # Total cycles spent in bank access 175system.physmem.avgQLat 21207.34 # Average queueing delay per request 176system.physmem.avgBankLat 15089.79 # Average bank access latency per request |
| 192system.physmem.avgBusLat 5000.00 # Average bus latency per request | 177system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 193system.physmem.avgMemAccLat 41483.22 # Average memory access latency 194system.physmem.avgRdBW 2.79 # Average achieved read bandwidth in MB/s | 178system.physmem.avgMemAccLat 41297.13 # Average memory access latency 179system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s |
| 195system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s | 180system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s |
| 196system.physmem.avgConsumedRdBW 2.79 # Average consumed read bandwidth in MB/s | 181system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s |
| 197system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s 198system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 199system.physmem.busUtil 0.04 # Data bus utilization in percentage 200system.physmem.avgRdQLen 0.00 # Average read queue length over time | 182system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 184system.physmem.busUtil 0.04 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.00 # Average read queue length over time |
| 201system.physmem.avgWrQLen 8.88 # Average write queue length over time 202system.physmem.readRowHits 193356 # Number of row buffer hits during reads 203system.physmem.writeRowHits 105797 # Number of row buffer hits during writes 204system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads 205system.physmem.writeRowHitRate 70.78 # Row buffer hit rate for writes 206system.physmem.avgGap 13752566.79 # Average gap between requests 207system.iocache.replacements 47574 # number of replacements 208system.iocache.tagsinuse 0.128668 # Cycle average of tags in use | 186system.physmem.avgWrQLen 11.02 # Average write queue length over time 187system.physmem.readRowHits 193727 # Number of row buffer hits during reads 188system.physmem.writeRowHits 105780 # Number of row buffer hits during writes 189system.physmem.readRowHitRate 86.23 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes 191system.physmem.avgGap 13726637.07 # Average gap between requests 192system.iocache.replacements 47576 # number of replacements 193system.iocache.tagsinuse 0.116322 # Cycle average of tags in use |
| 209system.iocache.total_refs 0 # Total number of references to valid blocks. | 194system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 210system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. | 195system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. |
| 211system.iocache.avg_refs 0 # Average number of references to valid blocks. | 196system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 212system.iocache.warmup_cycle 4991908358000 # Cycle when the warmup percentage was hit. 213system.iocache.occ_blocks::pc.south_bridge.ide 0.128668 # Average occupied blocks per requestor 214system.iocache.occ_percent::pc.south_bridge.ide 0.008042 # Average percentage of cache occupancy 215system.iocache.occ_percent::total 0.008042 # Average percentage of cache occupancy 216system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses 217system.iocache.ReadReq_misses::total 909 # number of ReadReq misses | 197system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. 198system.iocache.occ_blocks::pc.south_bridge.ide 0.116322 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy 201system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 911 # number of ReadReq misses |
| 218system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 219system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses | 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses |
| 220system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses 221system.iocache.demand_misses::total 47629 # number of demand (read+write) misses 222system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses 223system.iocache.overall_misses::total 47629 # number of overall misses 224system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143200932 # number of ReadReq miss cycles 225system.iocache.ReadReq_miss_latency::total 143200932 # number of ReadReq miss cycles 226system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10097082160 # number of WriteReq miss cycles 227system.iocache.WriteReq_miss_latency::total 10097082160 # number of WriteReq miss cycles 228system.iocache.demand_miss_latency::pc.south_bridge.ide 10240283092 # number of demand (read+write) miss cycles 229system.iocache.demand_miss_latency::total 10240283092 # number of demand (read+write) miss cycles 230system.iocache.overall_miss_latency::pc.south_bridge.ide 10240283092 # number of overall miss cycles 231system.iocache.overall_miss_latency::total 10240283092 # number of overall miss cycles 232system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) 233system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) | 205system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 206system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 207system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 208system.iocache.overall_misses::total 47631 # number of overall misses 209system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151593932 # number of ReadReq miss cycles 210system.iocache.ReadReq_miss_latency::total 151593932 # number of ReadReq miss cycles 211system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10023192160 # number of WriteReq miss cycles 212system.iocache.WriteReq_miss_latency::total 10023192160 # number of WriteReq miss cycles 213system.iocache.demand_miss_latency::pc.south_bridge.ide 10174786092 # number of demand (read+write) miss cycles 214system.iocache.demand_miss_latency::total 10174786092 # number of demand (read+write) miss cycles 215system.iocache.overall_miss_latency::pc.south_bridge.ide 10174786092 # number of overall miss cycles 216system.iocache.overall_miss_latency::total 10174786092 # number of overall miss cycles 217system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 218system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) |
| 234system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 235system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) | 219system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 220system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) |
| 236system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses 237system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses 238system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses 239system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses | 221system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 222system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 223system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 224system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses |
| 240system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 241system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 242system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 243system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 244system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 245system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 246system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 247system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 225system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 226system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 227system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 228system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 229system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 231system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 248system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157536.778878 # average ReadReq miss latency 249system.iocache.ReadReq_avg_miss_latency::total 157536.778878 # average ReadReq miss latency 250system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 216119.053082 # average WriteReq miss latency 251system.iocache.WriteReq_avg_miss_latency::total 216119.053082 # average WriteReq miss latency 252system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency 253system.iocache.demand_avg_miss_latency::total 215001.009721 # average overall miss latency 254system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency 255system.iocache.overall_avg_miss_latency::total 215001.009721 # average overall miss latency 256system.iocache.blocked_cycles::no_mshrs 136887 # number of cycles access was blocked | 233system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166403.877058 # average ReadReq miss latency 234system.iocache.ReadReq_avg_miss_latency::total 166403.877058 # average ReadReq miss latency 235system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214537.503425 # average WriteReq miss latency 236system.iocache.WriteReq_avg_miss_latency::total 214537.503425 # average WriteReq miss latency 237system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency 238system.iocache.demand_avg_miss_latency::total 213616.890093 # average overall miss latency 239system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency 240system.iocache.overall_avg_miss_latency::total 213616.890093 # average overall miss latency 241system.iocache.blocked_cycles::no_mshrs 136470 # number of cycles access was blocked |
| 257system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 242system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 258system.iocache.blocked::no_mshrs 12650 # number of cycles access was blocked | 243system.iocache.blocked::no_mshrs 12410 # number of cycles access was blocked |
| 259system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 244system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 260system.iocache.avg_blocked_cycles::no_mshrs 10.821107 # average number of cycles each access was blocked | 245system.iocache.avg_blocked_cycles::no_mshrs 10.996777 # average number of cycles each access was blocked |
| 261system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 262system.iocache.fast_writes 0 # number of fast writes performed 263system.iocache.cache_copies 0 # number of cache copies performed 264system.iocache.writebacks::writebacks 46667 # number of writebacks 265system.iocache.writebacks::total 46667 # number of writebacks | 246system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.iocache.fast_writes 0 # number of fast writes performed 248system.iocache.cache_copies 0 # number of cache copies performed 249system.iocache.writebacks::writebacks 46667 # number of writebacks 250system.iocache.writebacks::total 46667 # number of writebacks |
| 266system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses 267system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses | 251system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 252system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses |
| 268system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 269system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses | 253system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 254system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses |
| 270system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses 271system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses 272system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses 273system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses 274system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95911989 # number of ReadReq MSHR miss cycles 275system.iocache.ReadReq_mshr_miss_latency::total 95911989 # number of ReadReq MSHR miss cycles 276system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7666293817 # number of WriteReq MSHR miss cycles 277system.iocache.WriteReq_mshr_miss_latency::total 7666293817 # number of WriteReq MSHR miss cycles 278system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of demand (read+write) MSHR miss cycles 279system.iocache.demand_mshr_miss_latency::total 7762205806 # number of demand (read+write) MSHR miss cycles 280system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of overall MSHR miss cycles 281system.iocache.overall_mshr_miss_latency::total 7762205806 # number of overall MSHR miss cycles | 255system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 256system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 257system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 258system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses 259system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104200712 # number of ReadReq MSHR miss cycles 260system.iocache.ReadReq_mshr_miss_latency::total 104200712 # number of ReadReq MSHR miss cycles 261system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7592410619 # number of WriteReq MSHR miss cycles 262system.iocache.WriteReq_mshr_miss_latency::total 7592410619 # number of WriteReq MSHR miss cycles 263system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of demand (read+write) MSHR miss cycles 264system.iocache.demand_mshr_miss_latency::total 7696611331 # number of demand (read+write) MSHR miss cycles 265system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of overall MSHR miss cycles 266system.iocache.overall_mshr_miss_latency::total 7696611331 # number of overall MSHR miss cycles |
| 282system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 283system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 284system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 285system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 286system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 287system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 288system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 289system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 267system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 268system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 269system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 270system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 271system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 272system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 273system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 274system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 290system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105513.739274 # average ReadReq mshr miss latency 291system.iocache.ReadReq_avg_mshr_miss_latency::total 105513.739274 # average ReadReq mshr miss latency 292system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 164090.193001 # average WriteReq mshr miss latency 293system.iocache.WriteReq_avg_mshr_miss_latency::total 164090.193001 # average WriteReq mshr miss latency 294system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency 295system.iocache.demand_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency 296system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency 297system.iocache.overall_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency | 275system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114380.583974 # average ReadReq mshr miss latency 276system.iocache.ReadReq_avg_mshr_miss_latency::total 114380.583974 # average ReadReq mshr miss latency 277system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162508.788934 # average WriteReq mshr miss latency 278system.iocache.WriteReq_avg_mshr_miss_latency::total 162508.788934 # average WriteReq mshr miss latency 279system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency 280system.iocache.demand_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency 281system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency 282system.iocache.overall_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency |
| 298system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 299system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 300system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 301system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 302system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 303system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 304system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 305system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 306system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 307system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 308system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 309system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 310system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 283system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 285system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 286system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 287system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 288system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 289system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 290system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 291system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 292system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 293system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 294system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 295system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 311system.cpu.branchPred.lookups 86195570 # Number of BP lookups 312system.cpu.branchPred.condPredicted 86195570 # Number of conditional branches predicted 313system.cpu.branchPred.condIncorrect 1107298 # Number of conditional branches incorrect 314system.cpu.branchPred.BTBLookups 81287324 # Number of BTB lookups 315system.cpu.branchPred.BTBHits 79211919 # Number of BTB hits | 296system.cpu.branchPred.lookups 86198193 # Number of BP lookups 297system.cpu.branchPred.condPredicted 86198193 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 1106234 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 81290548 # Number of BTB lookups 300system.cpu.branchPred.BTBHits 79213904 # Number of BTB hits |
| 316system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 317system.cpu.branchPred.BTBHitPct 97.446828 # BTB Hit Percentage | 302system.cpu.branchPred.BTBHitPct 97.445405 # BTB Hit Percentage |
| 318system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 319system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. | 303system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 320system.cpu.numCycles 448232203 # number of cpu cycles simulated | 305system.cpu.numCycles 448153841 # number of cpu cycles simulated |
| 321system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 322system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 323system.cpu.fetch.icacheStallCycles 27444393 # Number of cycles fetch is stalled on an Icache miss 324system.cpu.fetch.Insts 425935714 # Number of instructions fetch has processed 325system.cpu.fetch.Branches 86195570 # Number of branches that fetch encountered 326system.cpu.fetch.predictedBranches 79211919 # Number of branches that fetch has predicted taken 327system.cpu.fetch.Cycles 163577459 # Number of cycles fetch has run and was not squashing or blocked 328system.cpu.fetch.SquashCycles 4703661 # Number of cycles fetch has spent squashing 329system.cpu.fetch.TlbCycles 120329 # Number of cycles fetch has spent waiting for tlb 330system.cpu.fetch.BlockedCycles 63100618 # Number of cycles fetch has spent blocked 331system.cpu.fetch.MiscStallCycles 36734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 332system.cpu.fetch.PendingTrapStallCycles 50393 # Number of stall cycles due to pending traps 333system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR 334system.cpu.fetch.CacheLines 9010824 # Number of cache lines fetched 335system.cpu.fetch.IcacheSquashes 484273 # Number of outstanding Icache misses that were squashed 336system.cpu.fetch.ItlbSquashes 3255 # Number of outstanding ITLB misses that were squashed 337system.cpu.fetch.rateDist::samples 257888489 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::mean 3.260624 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::stdev 3.418001 # Number of instructions fetched each cycle (Total) | 308system.cpu.fetch.icacheStallCycles 27415171 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 425937394 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 86198193 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 79213904 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 163576958 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 4698498 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 117961 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.BlockedCycles 63103393 # Number of cycles fetch has spent blocked 316system.cpu.fetch.MiscStallCycles 36350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 317system.cpu.fetch.PendingTrapStallCycles 51299 # Number of stall cycles due to pending traps 318system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 9010068 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 483485 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 3126 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 257855511 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 3.261045 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.418033 # Number of instructions fetched each cycle (Total) |
| 340system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 341system.cpu.fetch.rateDist::0 94737944 36.74% 36.74% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::1 1567529 0.61% 37.34% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::2 71915391 27.89% 65.23% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::3 936422 0.36% 65.59% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::4 1600476 0.62% 66.21% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::5 2419747 0.94% 67.15% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::6 1072144 0.42% 67.57% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::7 1374255 0.53% 68.10% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::8 82264581 31.90% 100.00% # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.rateDist::0 94705411 36.73% 36.73% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 1566235 0.61% 37.34% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 71918028 27.89% 65.23% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 935930 0.36% 65.59% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 1598963 0.62% 66.21% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 2419267 0.94% 67.15% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 1070398 0.42% 67.56% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 1376464 0.53% 68.10% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 82264815 31.90% 100.00% # Number of instructions fetched each cycle (Total) |
| 350system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 353system.cpu.fetch.rateDist::total 257888489 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.branchRate 0.192301 # Number of branch fetches per cycle 355system.cpu.fetch.rate 0.950257 # Number of inst fetches per cycle 356system.cpu.decode.IdleCycles 31158433 # Number of cycles decode is idle 357system.cpu.decode.BlockedCycles 60539785 # Number of cycles decode is blocked 358system.cpu.decode.RunCycles 159369860 # Number of cycles decode is running 359system.cpu.decode.UnblockCycles 3262201 # Number of cycles decode is unblocking 360system.cpu.decode.SquashCycles 3558210 # Number of cycles decode is squashing 361system.cpu.decode.DecodedInsts 837747525 # Number of instructions handled by decode 362system.cpu.decode.SquashedInsts 908 # Number of squashed instructions handled by decode 363system.cpu.rename.SquashCycles 3558210 # Number of cycles rename is squashing 364system.cpu.rename.IdleCycles 33896779 # Number of cycles rename is idle 365system.cpu.rename.BlockCycles 37429027 # Number of cycles rename is blocking 366system.cpu.rename.serializeStallCycles 10979367 # count of cycles rename stalled for serializing inst 367system.cpu.rename.RunCycles 159568616 # Number of cycles rename is running 368system.cpu.rename.UnblockCycles 12456490 # Number of cycles rename is unblocking 369system.cpu.rename.RenamedInsts 834117350 # Number of instructions processed by rename 370system.cpu.rename.ROBFullEvents 19334 # Number of times rename has blocked due to ROB full 371system.cpu.rename.IQFullEvents 5870357 # Number of times rename has blocked due to IQ full 372system.cpu.rename.LSQFullEvents 4754276 # Number of times rename has blocked due to LSQ full 373system.cpu.rename.FullRegisterEvents 7741 # Number of times there has been no free registers 374system.cpu.rename.RenamedOperands 995632267 # Number of destination operands rename has renamed 375system.cpu.rename.RenameLookups 1810669462 # Number of register rename lookups that rename has made 376system.cpu.rename.int_rename_lookups 1810668566 # Number of integer rename lookups 377system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups 378system.cpu.rename.CommittedMaps 964317189 # Number of HB maps that are committed 379system.cpu.rename.UndoneMaps 31315071 # Number of HB maps that are undone due to squashing 380system.cpu.rename.serializingInsts 459232 # count of serializing insts renamed 381system.cpu.rename.tempSerializingInsts 466806 # count of temporary serializing insts renamed 382system.cpu.rename.skidInsts 28815526 # count of insts added to the skid buffer 383system.cpu.memDep0.insertedLoads 17065121 # Number of loads inserted to the mem dependence unit. 384system.cpu.memDep0.insertedStores 10125717 # Number of stores inserted to the mem dependence unit. 385system.cpu.memDep0.conflictingLoads 1247966 # Number of conflicting loads. 386system.cpu.memDep0.conflictingStores 991465 # Number of conflicting stores. 387system.cpu.iq.iqInstsAdded 828007231 # Number of instructions added to the IQ (excludes non-spec) 388system.cpu.iq.iqNonSpecInstsAdded 1251140 # Number of non-speculative instructions added to the IQ 389system.cpu.iq.iqInstsIssued 823065161 # Number of instructions issued 390system.cpu.iq.iqSquashedInstsIssued 148512 # Number of squashed instructions issued 391system.cpu.iq.iqSquashedInstsExamined 22000890 # Number of squashed instructions iterated over during squash; mainly for profiling 392system.cpu.iq.iqSquashedOperandsExamined 33478625 # Number of squashed operands that are examined and possibly removed from graph 393system.cpu.iq.iqSquashedNonSpecRemoved 198442 # Number of squashed non-spec instructions that were removed 394system.cpu.iq.issued_per_cycle::samples 257888489 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::mean 3.191554 # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::stdev 2.384086 # Number of insts issued each cycle | 338system.cpu.fetch.rateDist::total 257855511 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.192341 # Number of branch fetches per cycle 340system.cpu.fetch.rate 0.950427 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 31132857 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 60536501 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 159370274 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 3261936 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 3553943 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 837748670 # Number of instructions handled by decode 347system.cpu.decode.SquashedInsts 951 # Number of squashed instructions handled by decode 348system.cpu.rename.SquashCycles 3553943 # Number of cycles rename is squashing 349system.cpu.rename.IdleCycles 33869883 # Number of cycles rename is idle 350system.cpu.rename.BlockCycles 37385632 # Number of cycles rename is blocking 351system.cpu.rename.serializeStallCycles 11021591 # count of cycles rename stalled for serializing inst 352system.cpu.rename.RunCycles 159568277 # Number of cycles rename is running 353system.cpu.rename.UnblockCycles 12456185 # Number of cycles rename is unblocking 354system.cpu.rename.RenamedInsts 834115262 # Number of instructions processed by rename 355system.cpu.rename.ROBFullEvents 19668 # Number of times rename has blocked due to ROB full 356system.cpu.rename.IQFullEvents 5867494 # Number of times rename has blocked due to IQ full 357system.cpu.rename.LSQFullEvents 4754545 # Number of times rename has blocked due to LSQ full 358system.cpu.rename.FullRegisterEvents 8312 # Number of times there has been no free registers 359system.cpu.rename.RenamedOperands 995635482 # Number of destination operands rename has renamed 360system.cpu.rename.RenameLookups 1810665967 # Number of register rename lookups that rename has made 361system.cpu.rename.int_rename_lookups 1810665163 # Number of integer rename lookups 362system.cpu.rename.fp_rename_lookups 804 # Number of floating rename lookups 363system.cpu.rename.CommittedMaps 964341342 # Number of HB maps that are committed 364system.cpu.rename.UndoneMaps 31294133 # Number of HB maps that are undone due to squashing 365system.cpu.rename.serializingInsts 459159 # count of serializing insts renamed 366system.cpu.rename.tempSerializingInsts 467055 # count of temporary serializing insts renamed 367system.cpu.rename.skidInsts 28798095 # count of insts added to the skid buffer 368system.cpu.memDep0.insertedLoads 17056943 # Number of loads inserted to the mem dependence unit. 369system.cpu.memDep0.insertedStores 10123506 # Number of stores inserted to the mem dependence unit. 370system.cpu.memDep0.conflictingLoads 1248285 # Number of conflicting loads. 371system.cpu.memDep0.conflictingStores 987203 # Number of conflicting stores. 372system.cpu.iq.iqInstsAdded 827998215 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqNonSpecInstsAdded 1251183 # Number of non-speculative instructions added to the IQ 374system.cpu.iq.iqInstsIssued 823066756 # Number of instructions issued 375system.cpu.iq.iqSquashedInstsIssued 148002 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 21984557 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 33441202 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 198541 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 257855511 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 3.191969 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 2.384014 # Number of insts issued each cycle |
| 397system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 398system.cpu.iq.issued_per_cycle::0 71416188 27.69% 27.69% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::1 15522620 6.02% 33.71% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::2 10297220 3.99% 37.70% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::3 7470539 2.90% 40.60% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::4 75900478 29.43% 70.03% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::5 3837629 1.49% 71.52% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::6 72511548 28.12% 99.64% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::7 780997 0.30% 99.94% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::8 151270 0.06% 100.00% # Number of insts issued each cycle | 383system.cpu.iq.issued_per_cycle::0 71390186 27.69% 27.69% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 15517919 6.02% 33.70% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 10294138 3.99% 37.70% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 7464826 2.89% 40.59% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 75904474 29.44% 70.03% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 3838948 1.49% 71.52% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 72513480 28.12% 99.64% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 779753 0.30% 99.94% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 151787 0.06% 100.00% # Number of insts issued each cycle |
| 407system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 410system.cpu.iq.issued_per_cycle::total 257888489 # Number of insts issued each cycle | 395system.cpu.iq.issued_per_cycle::total 257855511 # Number of insts issued each cycle |
| 411system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 412system.cpu.iq.fu_full::IntAlu 362608 34.00% 34.00% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntMult 0 0.00% 34.00% # attempts to use FU when none available 414system.cpu.iq.fu_full::IntDiv 0 0.00% 34.00% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.00% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.00% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatMult 0 0.00% 34.00% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.00% # attempts to use FU when none available 420system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.00% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.00% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.00% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.00% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.00% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.00% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMult 0 0.00% 34.00% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdShift 0 0.00% 34.00% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.00% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.00% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.00% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.00% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.00% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.00% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.00% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.00% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.00% # attempts to use FU when none available 441system.cpu.iq.fu_full::MemRead 553228 51.88% 85.88% # attempts to use FU when none available 442system.cpu.iq.fu_full::MemWrite 150521 14.12% 100.00% # attempts to use FU when none available | 397system.cpu.iq.fu_full::IntAlu 363612 34.06% 34.06% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntMult 0 0.00% 34.06% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 0 0.00% 34.06% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.06% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.06% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.06% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 34.06% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.06% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.06% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.06% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.06% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.06% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.06% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.06% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.06% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMult 0 0.00% 34.06% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.06% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShift 0 0.00% 34.06% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.06% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.06% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.06% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.06% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.06% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.06% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.06% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.06% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.06% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.06% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.06% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemRead 553162 51.82% 85.88% # attempts to use FU when none available 427system.cpu.iq.fu_full::MemWrite 150741 14.12% 100.00% # attempts to use FU when none available |
| 443system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 444system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 428system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 445system.cpu.iq.FU_type_0::No_OpClass 311367 0.04% 0.04% # Type of FU issued 446system.cpu.iq.FU_type_0::IntAlu 795535215 96.66% 96.69% # Type of FU issued | 430system.cpu.iq.FU_type_0::No_OpClass 311137 0.04% 0.04% # Type of FU issued 431system.cpu.iq.FU_type_0::IntAlu 795540449 96.66% 96.69% # Type of FU issued |
| 447system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued 448system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 467system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued | 432system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued 433system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 452system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued |
| 475system.cpu.iq.FU_type_0::MemRead 17840146 2.17% 98.86% # Type of FU issued 476system.cpu.iq.FU_type_0::MemWrite 9378433 1.14% 100.00% # Type of FU issued | 460system.cpu.iq.FU_type_0::MemRead 17836742 2.17% 98.86% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 9378428 1.14% 100.00% # Type of FU issued |
| 477system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 479system.cpu.iq.FU_type_0::total 823065161 # Type of FU issued 480system.cpu.iq.rate 1.836247 # Inst issue rate 481system.cpu.iq.fu_busy_cnt 1066357 # FU busy when requested 482system.cpu.iq.fu_busy_rate 0.001296 # FU busy rate (busy events/executed inst) 483system.cpu.iq.int_inst_queue_reads 1905364388 # Number of integer instruction queue reads 484system.cpu.iq.int_inst_queue_writes 851269170 # Number of integer instruction queue writes 485system.cpu.iq.int_inst_queue_wakeup_accesses 818594497 # Number of integer instruction queue wakeup accesses 486system.cpu.iq.fp_inst_queue_reads 333 # Number of floating instruction queue reads 487system.cpu.iq.fp_inst_queue_writes 414 # Number of floating instruction queue writes 488system.cpu.iq.fp_inst_queue_wakeup_accesses 81 # Number of floating instruction queue wakeup accesses 489system.cpu.iq.int_alu_accesses 823820002 # Number of integer alu accesses 490system.cpu.iq.fp_alu_accesses 149 # Number of floating point alu accesses 491system.cpu.iew.lsq.thread0.forwLoads 1640065 # Number of loads that had data forwarded from stores | 464system.cpu.iq.FU_type_0::total 823066756 # Type of FU issued 465system.cpu.iq.rate 1.836572 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 1067515 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 1905334904 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 851243829 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 818598323 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 260 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 823823020 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 114 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 1639481 # Number of loads that had data forwarded from stores |
| 492system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 493system.cpu.iew.lsq.thread0.squashedLoads 3087216 # Number of loads squashed 494system.cpu.iew.lsq.thread0.ignoredResponses 23041 # Number of memory responses ignored because the instruction is squashed 495system.cpu.iew.lsq.thread0.memOrderViolation 11568 # Number of memory ordering violations 496system.cpu.iew.lsq.thread0.squashedStores 1713876 # Number of stores squashed | 478system.cpu.iew.lsq.thread0.squashedLoads 3079539 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 22701 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 11520 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 1710580 # Number of stores squashed |
| 497system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 498system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 499system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled 500system.cpu.iew.lsq.thread0.cacheBlocked 12043 # Number of times an access to memory failed due to the cache being blocked | 484system.cpu.iew.lsq.thread0.rescheduledLoads 1932434 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 12204 # Number of times an access to memory failed due to the cache being blocked |
| 501system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 502system.cpu.iew.iewSquashCycles 3558210 # Number of cycles IEW is squashing 503system.cpu.iew.iewBlockCycles 26163339 # Number of cycles IEW is blocking 504system.cpu.iew.iewUnblockCycles 2115746 # Number of cycles IEW is unblocking 505system.cpu.iew.iewDispatchedInsts 829258371 # Number of instructions dispatched to IQ 506system.cpu.iew.iewDispSquashedInsts 321958 # Number of squashed instructions skipped by dispatch 507system.cpu.iew.iewDispLoadInsts 17065121 # Number of dispatched load instructions 508system.cpu.iew.iewDispStoreInsts 10125717 # Number of dispatched store instructions 509system.cpu.iew.iewDispNonSpecInsts 719121 # Number of dispatched non-speculative instructions 510system.cpu.iew.iewIQFullEvents 1615790 # Number of times the IQ has become full, causing a stall 511system.cpu.iew.iewLSQFullEvents 11387 # Number of times the LSQ has become full, causing a stall 512system.cpu.iew.memOrderViolationEvents 11568 # Number of memory order violations 513system.cpu.iew.predictedTakenIncorrect 649229 # Number of branches that were predicted taken incorrectly 514system.cpu.iew.predictedNotTakenIncorrect 593828 # Number of branches that were predicted not taken incorrectly 515system.cpu.iew.branchMispredicts 1243057 # Number of branch mispredicts detected at execute 516system.cpu.iew.iewExecutedInsts 821192043 # Number of executed instructions 517system.cpu.iew.iewExecLoadInsts 17430508 # Number of load instructions executed 518system.cpu.iew.iewExecSquashedInsts 1873117 # Number of squashed instructions skipped in execute | 487system.cpu.iew.iewSquashCycles 3553943 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 26124965 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 2116869 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 829249398 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 321104 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 17056943 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 10123506 # Number of dispatched store instructions 494system.cpu.iew.iewDispNonSpecInsts 718931 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 1615774 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 10404 # Number of times the LSQ has become full, causing a stall 497system.cpu.iew.memOrderViolationEvents 11520 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 649169 # Number of branches that were predicted taken incorrectly 499system.cpu.iew.predictedNotTakenIncorrect 592997 # Number of branches that were predicted not taken incorrectly 500system.cpu.iew.branchMispredicts 1242166 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 821195112 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 17426068 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 1871643 # Number of squashed instructions skipped in execute |
| 519system.cpu.iew.exec_swp 0 # number of swp insts executed 520system.cpu.iew.exec_nop 0 # number of nop insts executed | 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 521system.cpu.iew.exec_refs 26576754 # number of memory reference insts executed 522system.cpu.iew.exec_branches 83195358 # Number of branches executed 523system.cpu.iew.exec_stores 9146246 # Number of stores executed 524system.cpu.iew.exec_rate 1.832068 # Inst execution rate 525system.cpu.iew.wb_sent 820730031 # cumulative count of insts sent to commit 526system.cpu.iew.wb_count 818594578 # cumulative count of insts written-back 527system.cpu.iew.wb_producers 639788924 # num instructions producing a value 528system.cpu.iew.wb_consumers 1045548924 # num instructions consuming a value | 506system.cpu.iew.exec_refs 26572625 # number of memory reference insts executed 507system.cpu.iew.exec_branches 83197450 # Number of branches executed 508system.cpu.iew.exec_stores 9146557 # Number of stores executed 509system.cpu.iew.exec_rate 1.832396 # Inst execution rate 510system.cpu.iew.wb_sent 820733466 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 818598386 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 639795417 # num instructions producing a value 513system.cpu.iew.wb_consumers 1045555736 # num instructions consuming a value |
| 529system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 514system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 530system.cpu.iew.wb_rate 1.826273 # insts written-back per cycle 531system.cpu.iew.wb_fanout 0.611917 # average fanout of values written-back | 515system.cpu.iew.wb_rate 1.826601 # insts written-back per cycle 516system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back |
| 532system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 517system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 533system.cpu.commit.commitSquashedInsts 22806507 # The number of squashed insts skipped by commit 534system.cpu.commit.commitNonSpecStalls 1052696 # The number of times commit has been forced to stall to communicate backwards 535system.cpu.commit.branchMispredicts 1111685 # The number of times a branch was mispredicted 536system.cpu.commit.committed_per_cycle::samples 254330279 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::mean 3.170460 # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::stdev 2.853927 # Number of insts commited each cycle | 518system.cpu.commit.commitSquashedInsts 22777543 # The number of squashed insts skipped by commit 519system.cpu.commit.commitNonSpecStalls 1052640 # The number of times commit has been forced to stall to communicate backwards 520system.cpu.commit.branchMispredicts 1110740 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 254301568 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 3.170895 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 2.853974 # Number of insts commited each cycle |
| 539system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 540system.cpu.commit.committed_per_cycle::0 82551524 32.46% 32.46% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::1 11813015 4.64% 37.10% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::2 3912372 1.54% 38.64% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::3 74944552 29.47% 68.11% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::4 2436279 0.96% 69.07% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::5 1482727 0.58% 69.65% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::6 942941 0.37% 70.02% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::7 70918770 27.88% 97.91% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::8 5328099 2.09% 100.00% # Number of insts commited each cycle | 525system.cpu.commit.committed_per_cycle::0 82529406 32.45% 32.45% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::1 11802979 4.64% 37.09% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::2 3912644 1.54% 38.63% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 74944166 29.47% 68.10% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::4 2437687 0.96% 69.06% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::5 1481720 0.58% 69.65% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::6 940520 0.37% 70.01% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 70919321 27.89% 97.90% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 5333125 2.10% 100.00% # Number of insts commited each cycle |
| 549system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 552system.cpu.commit.committed_per_cycle::total 254330279 # Number of insts commited each cycle 553system.cpu.commit.committedInsts 407913764 # Number of instructions committed 554system.cpu.commit.committedOps 806343994 # Number of ops (including micro ops) committed | 537system.cpu.commit.committed_per_cycle::total 254301568 # Number of insts commited each cycle 538system.cpu.commit.committedInsts 407925588 # Number of instructions committed 539system.cpu.commit.committedOps 806363480 # Number of ops (including micro ops) committed |
| 555system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 540system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 556system.cpu.commit.refs 22389743 # Number of memory references committed 557system.cpu.commit.loads 13977902 # Number of loads committed 558system.cpu.commit.membars 473467 # Number of memory barriers committed 559system.cpu.commit.branches 82188680 # Number of branches committed | 541system.cpu.commit.refs 22390327 # Number of memory references committed 542system.cpu.commit.loads 13977401 # Number of loads committed 543system.cpu.commit.membars 473457 # Number of memory barriers committed 544system.cpu.commit.branches 82191015 # Number of branches committed |
| 560system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 545system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 561system.cpu.commit.int_insts 735286834 # Number of committed integer instructions. | 546system.cpu.commit.int_insts 735304742 # Number of committed integer instructions. |
| 562system.cpu.commit.function_calls 0 # Number of function calls committed. | 547system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 563system.cpu.commit.bw_lim_events 5328099 # number cycles where commit BW limit reached | 548system.cpu.commit.bw_lim_events 5333125 # number cycles where commit BW limit reached |
| 564system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 549system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 565system.cpu.rob.rob_reads 1078074430 # The number of ROB reads 566system.cpu.rob.rob_writes 1661878047 # The number of ROB writes 567system.cpu.timesIdled 1220922 # Number of times that the entire CPU went into an idle state and unscheduled itself 568system.cpu.idleCycles 190343714 # Total number of cycles that the CPU has spent unscheduled due to idling 569system.cpu.quiesceCycles 9833486813 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 570system.cpu.committedInsts 407913764 # Number of Instructions Simulated 571system.cpu.committedOps 806343994 # Number of Ops (including micro ops) Simulated 572system.cpu.committedInsts_total 407913764 # Number of Instructions Simulated 573system.cpu.cpi 1.098841 # CPI: Cycles Per Instruction 574system.cpu.cpi_total 1.098841 # CPI: Total CPI of All Threads 575system.cpu.ipc 0.910050 # IPC: Instructions Per Cycle 576system.cpu.ipc_total 0.910050 # IPC: Total IPC of All Threads 577system.cpu.int_regfile_reads 1506675506 # number of integer regfile reads 578system.cpu.int_regfile_writes 976772305 # number of integer regfile writes 579system.cpu.fp_regfile_reads 81 # number of floating regfile reads 580system.cpu.misc_regfile_reads 264620330 # number of misc regfile reads 581system.cpu.misc_regfile_writes 402287 # number of misc regfile writes 582system.cpu.icache.replacements 1047202 # number of replacements 583system.cpu.icache.tagsinuse 510.392599 # Cycle average of tags in use 584system.cpu.icache.total_refs 7900027 # Total number of references to valid blocks. 585system.cpu.icache.sampled_refs 1047714 # Sample count of references to valid blocks. 586system.cpu.icache.avg_refs 7.540251 # Average number of references to valid blocks. | 550system.cpu.rob.rob_reads 1078031216 # The number of ROB reads 551system.cpu.rob.rob_writes 1661854677 # The number of ROB writes 552system.cpu.timesIdled 1219790 # Number of times that the entire CPU went into an idle state and unscheduled itself 553system.cpu.idleCycles 190298330 # Total number of cycles that the CPU has spent unscheduled due to idling 554system.cpu.quiesceCycles 9825572650 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 555system.cpu.committedInsts 407925588 # Number of Instructions Simulated 556system.cpu.committedOps 806363480 # Number of Ops (including micro ops) Simulated 557system.cpu.committedInsts_total 407925588 # Number of Instructions Simulated 558system.cpu.cpi 1.098617 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 1.098617 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.910236 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.910236 # IPC: Total IPC of All Threads 562system.cpu.int_regfile_reads 1506687590 # number of integer regfile reads 563system.cpu.int_regfile_writes 976781809 # number of integer regfile writes 564system.cpu.fp_regfile_reads 63 # number of floating regfile reads 565system.cpu.misc_regfile_reads 264621583 # number of misc regfile reads 566system.cpu.misc_regfile_writes 402234 # number of misc regfile writes 567system.cpu.icache.replacements 1045798 # number of replacements 568system.cpu.icache.tagsinuse 510.125014 # Cycle average of tags in use 569system.cpu.icache.total_refs 7900747 # Total number of references to valid blocks. 570system.cpu.icache.sampled_refs 1046310 # Sample count of references to valid blocks. 571system.cpu.icache.avg_refs 7.551058 # Average number of references to valid blocks. |
| 587system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. | 572system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. |
| 588system.cpu.icache.occ_blocks::cpu.inst 510.392599 # Average occupied blocks per requestor 589system.cpu.icache.occ_percent::cpu.inst 0.996861 # Average percentage of cache occupancy 590system.cpu.icache.occ_percent::total 0.996861 # Average percentage of cache occupancy 591system.cpu.icache.ReadReq_hits::cpu.inst 7900027 # number of ReadReq hits 592system.cpu.icache.ReadReq_hits::total 7900027 # number of ReadReq hits 593system.cpu.icache.demand_hits::cpu.inst 7900027 # number of demand (read+write) hits 594system.cpu.icache.demand_hits::total 7900027 # number of demand (read+write) hits 595system.cpu.icache.overall_hits::cpu.inst 7900027 # number of overall hits 596system.cpu.icache.overall_hits::total 7900027 # number of overall hits 597system.cpu.icache.ReadReq_misses::cpu.inst 1110794 # number of ReadReq misses 598system.cpu.icache.ReadReq_misses::total 1110794 # number of ReadReq misses 599system.cpu.icache.demand_misses::cpu.inst 1110794 # number of demand (read+write) misses 600system.cpu.icache.demand_misses::total 1110794 # number of demand (read+write) misses 601system.cpu.icache.overall_misses::cpu.inst 1110794 # number of overall misses 602system.cpu.icache.overall_misses::total 1110794 # number of overall misses 603system.cpu.icache.ReadReq_miss_latency::cpu.inst 15299065993 # number of ReadReq miss cycles 604system.cpu.icache.ReadReq_miss_latency::total 15299065993 # number of ReadReq miss cycles 605system.cpu.icache.demand_miss_latency::cpu.inst 15299065993 # number of demand (read+write) miss cycles 606system.cpu.icache.demand_miss_latency::total 15299065993 # number of demand (read+write) miss cycles 607system.cpu.icache.overall_miss_latency::cpu.inst 15299065993 # number of overall miss cycles 608system.cpu.icache.overall_miss_latency::total 15299065993 # number of overall miss cycles 609system.cpu.icache.ReadReq_accesses::cpu.inst 9010821 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.ReadReq_accesses::total 9010821 # number of ReadReq accesses(hits+misses) 611system.cpu.icache.demand_accesses::cpu.inst 9010821 # number of demand (read+write) accesses 612system.cpu.icache.demand_accesses::total 9010821 # number of demand (read+write) accesses 613system.cpu.icache.overall_accesses::cpu.inst 9010821 # number of overall (read+write) accesses 614system.cpu.icache.overall_accesses::total 9010821 # number of overall (read+write) accesses 615system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123273 # miss rate for ReadReq accesses 616system.cpu.icache.ReadReq_miss_rate::total 0.123273 # miss rate for ReadReq accesses 617system.cpu.icache.demand_miss_rate::cpu.inst 0.123273 # miss rate for demand accesses 618system.cpu.icache.demand_miss_rate::total 0.123273 # miss rate for demand accesses 619system.cpu.icache.overall_miss_rate::cpu.inst 0.123273 # miss rate for overall accesses 620system.cpu.icache.overall_miss_rate::total 0.123273 # miss rate for overall accesses 621system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13773.090234 # average ReadReq miss latency 622system.cpu.icache.ReadReq_avg_miss_latency::total 13773.090234 # average ReadReq miss latency 623system.cpu.icache.demand_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency 624system.cpu.icache.demand_avg_miss_latency::total 13773.090234 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency 626system.cpu.icache.overall_avg_miss_latency::total 13773.090234 # average overall miss latency 627system.cpu.icache.blocked_cycles::no_mshrs 10781 # number of cycles access was blocked | 573system.cpu.icache.occ_blocks::cpu.inst 510.125014 # Average occupied blocks per requestor 574system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy 575system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy 576system.cpu.icache.ReadReq_hits::cpu.inst 7900747 # number of ReadReq hits 577system.cpu.icache.ReadReq_hits::total 7900747 # number of ReadReq hits 578system.cpu.icache.demand_hits::cpu.inst 7900747 # number of demand (read+write) hits 579system.cpu.icache.demand_hits::total 7900747 # number of demand (read+write) hits 580system.cpu.icache.overall_hits::cpu.inst 7900747 # number of overall hits 581system.cpu.icache.overall_hits::total 7900747 # number of overall hits 582system.cpu.icache.ReadReq_misses::cpu.inst 1109320 # number of ReadReq misses 583system.cpu.icache.ReadReq_misses::total 1109320 # number of ReadReq misses 584system.cpu.icache.demand_misses::cpu.inst 1109320 # number of demand (read+write) misses 585system.cpu.icache.demand_misses::total 1109320 # number of demand (read+write) misses 586system.cpu.icache.overall_misses::cpu.inst 1109320 # number of overall misses 587system.cpu.icache.overall_misses::total 1109320 # number of overall misses 588system.cpu.icache.ReadReq_miss_latency::cpu.inst 15268069493 # number of ReadReq miss cycles 589system.cpu.icache.ReadReq_miss_latency::total 15268069493 # number of ReadReq miss cycles 590system.cpu.icache.demand_miss_latency::cpu.inst 15268069493 # number of demand (read+write) miss cycles 591system.cpu.icache.demand_miss_latency::total 15268069493 # number of demand (read+write) miss cycles 592system.cpu.icache.overall_miss_latency::cpu.inst 15268069493 # number of overall miss cycles 593system.cpu.icache.overall_miss_latency::total 15268069493 # number of overall miss cycles 594system.cpu.icache.ReadReq_accesses::cpu.inst 9010067 # number of ReadReq accesses(hits+misses) 595system.cpu.icache.ReadReq_accesses::total 9010067 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.demand_accesses::cpu.inst 9010067 # number of demand (read+write) accesses 597system.cpu.icache.demand_accesses::total 9010067 # number of demand (read+write) accesses 598system.cpu.icache.overall_accesses::cpu.inst 9010067 # number of overall (read+write) accesses 599system.cpu.icache.overall_accesses::total 9010067 # number of overall (read+write) accesses 600system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123120 # miss rate for ReadReq accesses 601system.cpu.icache.ReadReq_miss_rate::total 0.123120 # miss rate for ReadReq accesses 602system.cpu.icache.demand_miss_rate::cpu.inst 0.123120 # miss rate for demand accesses 603system.cpu.icache.demand_miss_rate::total 0.123120 # miss rate for demand accesses 604system.cpu.icache.overall_miss_rate::cpu.inst 0.123120 # miss rate for overall accesses 605system.cpu.icache.overall_miss_rate::total 0.123120 # miss rate for overall accesses 606system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13763.449224 # average ReadReq miss latency 607system.cpu.icache.ReadReq_avg_miss_latency::total 13763.449224 # average ReadReq miss latency 608system.cpu.icache.demand_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency 609system.cpu.icache.demand_avg_miss_latency::total 13763.449224 # average overall miss latency 610system.cpu.icache.overall_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::total 13763.449224 # average overall miss latency 612system.cpu.icache.blocked_cycles::no_mshrs 12508 # number of cycles access was blocked |
| 628system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 613system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 629system.cpu.icache.blocked::no_mshrs 279 # number of cycles access was blocked | 614system.cpu.icache.blocked::no_mshrs 293 # number of cycles access was blocked |
| 630system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 615system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 631system.cpu.icache.avg_blocked_cycles::no_mshrs 38.641577 # average number of cycles each access was blocked | 616system.cpu.icache.avg_blocked_cycles::no_mshrs 42.689420 # average number of cycles each access was blocked |
| 632system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 633system.cpu.icache.fast_writes 0 # number of fast writes performed 634system.cpu.icache.cache_copies 0 # number of cache copies performed | 617system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 618system.cpu.icache.fast_writes 0 # number of fast writes performed 619system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 635system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60632 # number of ReadReq MSHR hits 636system.cpu.icache.ReadReq_mshr_hits::total 60632 # number of ReadReq MSHR hits 637system.cpu.icache.demand_mshr_hits::cpu.inst 60632 # number of demand (read+write) MSHR hits 638system.cpu.icache.demand_mshr_hits::total 60632 # number of demand (read+write) MSHR hits 639system.cpu.icache.overall_mshr_hits::cpu.inst 60632 # number of overall MSHR hits 640system.cpu.icache.overall_mshr_hits::total 60632 # number of overall MSHR hits 641system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1050162 # number of ReadReq MSHR misses 642system.cpu.icache.ReadReq_mshr_misses::total 1050162 # number of ReadReq MSHR misses 643system.cpu.icache.demand_mshr_misses::cpu.inst 1050162 # number of demand (read+write) MSHR misses 644system.cpu.icache.demand_mshr_misses::total 1050162 # number of demand (read+write) MSHR misses 645system.cpu.icache.overall_mshr_misses::cpu.inst 1050162 # number of overall MSHR misses 646system.cpu.icache.overall_mshr_misses::total 1050162 # number of overall MSHR misses 647system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12588415993 # number of ReadReq MSHR miss cycles 648system.cpu.icache.ReadReq_mshr_miss_latency::total 12588415993 # number of ReadReq MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12588415993 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.demand_mshr_miss_latency::total 12588415993 # number of demand (read+write) MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12588415993 # number of overall MSHR miss cycles 652system.cpu.icache.overall_mshr_miss_latency::total 12588415993 # number of overall MSHR miss cycles 653system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for ReadReq accesses 654system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116545 # mshr miss rate for ReadReq accesses 655system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for demand accesses 656system.cpu.icache.demand_mshr_miss_rate::total 0.116545 # mshr miss rate for demand accesses 657system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for overall accesses 658system.cpu.icache.overall_mshr_miss_rate::total 0.116545 # mshr miss rate for overall accesses 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11987.118171 # average ReadReq mshr miss latency 660system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11987.118171 # average ReadReq mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency 662system.cpu.icache.demand_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency 664system.cpu.icache.overall_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency | 620system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60685 # number of ReadReq MSHR hits 621system.cpu.icache.ReadReq_mshr_hits::total 60685 # number of ReadReq MSHR hits 622system.cpu.icache.demand_mshr_hits::cpu.inst 60685 # number of demand (read+write) MSHR hits 623system.cpu.icache.demand_mshr_hits::total 60685 # number of demand (read+write) MSHR hits 624system.cpu.icache.overall_mshr_hits::cpu.inst 60685 # number of overall MSHR hits 625system.cpu.icache.overall_mshr_hits::total 60685 # number of overall MSHR hits 626system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048635 # number of ReadReq MSHR misses 627system.cpu.icache.ReadReq_mshr_misses::total 1048635 # number of ReadReq MSHR misses 628system.cpu.icache.demand_mshr_misses::cpu.inst 1048635 # number of demand (read+write) MSHR misses 629system.cpu.icache.demand_mshr_misses::total 1048635 # number of demand (read+write) MSHR misses 630system.cpu.icache.overall_mshr_misses::cpu.inst 1048635 # number of overall MSHR misses 631system.cpu.icache.overall_mshr_misses::total 1048635 # number of overall MSHR misses 632system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12573562493 # number of ReadReq MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_miss_latency::total 12573562493 # number of ReadReq MSHR miss cycles 634system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12573562493 # number of demand (read+write) MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::total 12573562493 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12573562493 # number of overall MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::total 12573562493 # number of overall MSHR miss cycles 638system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116385 # mshr miss rate for ReadReq accesses 640system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for demand accesses 641system.cpu.icache.demand_mshr_miss_rate::total 0.116385 # mshr miss rate for demand accesses 642system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for overall accesses 643system.cpu.icache.overall_mshr_miss_rate::total 0.116385 # mshr miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11990.408954 # average ReadReq mshr miss latency 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11990.408954 # average ReadReq mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency |
| 665system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 650system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 666system.cpu.itb_walker_cache.replacements 9719 # number of replacements 667system.cpu.itb_walker_cache.tagsinuse 6.023103 # Cycle average of tags in use 668system.cpu.itb_walker_cache.total_refs 25822 # Total number of references to valid blocks. 669system.cpu.itb_walker_cache.sampled_refs 9733 # Sample count of references to valid blocks. 670system.cpu.itb_walker_cache.avg_refs 2.653036 # Average number of references to valid blocks. 671system.cpu.itb_walker_cache.warmup_cycle 5104044206500 # Cycle when the warmup percentage was hit. 672system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.023103 # Average occupied blocks per requestor 673system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376444 # Average percentage of cache occupancy 674system.cpu.itb_walker_cache.occ_percent::total 0.376444 # Average percentage of cache occupancy 675system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25827 # number of ReadReq hits 676system.cpu.itb_walker_cache.ReadReq_hits::total 25827 # number of ReadReq hits | 651system.cpu.itb_walker_cache.replacements 9600 # number of replacements 652system.cpu.itb_walker_cache.tagsinuse 6.016014 # Cycle average of tags in use 653system.cpu.itb_walker_cache.total_refs 25681 # Total number of references to valid blocks. 654system.cpu.itb_walker_cache.sampled_refs 9614 # Sample count of references to valid blocks. 655system.cpu.itb_walker_cache.avg_refs 2.671209 # Average number of references to valid blocks. 656system.cpu.itb_walker_cache.warmup_cycle 5103990045500 # Cycle when the warmup percentage was hit. 657system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016014 # Average occupied blocks per requestor 658system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376001 # Average percentage of cache occupancy 659system.cpu.itb_walker_cache.occ_percent::total 0.376001 # Average percentage of cache occupancy 660system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25689 # number of ReadReq hits 661system.cpu.itb_walker_cache.ReadReq_hits::total 25689 # number of ReadReq hits |
| 677system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 678system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 662system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 663system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 679system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25829 # number of demand (read+write) hits 680system.cpu.itb_walker_cache.demand_hits::total 25829 # number of demand (read+write) hits 681system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25829 # number of overall hits 682system.cpu.itb_walker_cache.overall_hits::total 25829 # number of overall hits 683system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10616 # number of ReadReq misses 684system.cpu.itb_walker_cache.ReadReq_misses::total 10616 # number of ReadReq misses 685system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10616 # number of demand (read+write) misses 686system.cpu.itb_walker_cache.demand_misses::total 10616 # number of demand (read+write) misses 687system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10616 # number of overall misses 688system.cpu.itb_walker_cache.overall_misses::total 10616 # number of overall misses 689system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 119043500 # number of ReadReq miss cycles 690system.cpu.itb_walker_cache.ReadReq_miss_latency::total 119043500 # number of ReadReq miss cycles 691system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 119043500 # number of demand (read+write) miss cycles 692system.cpu.itb_walker_cache.demand_miss_latency::total 119043500 # number of demand (read+write) miss cycles 693system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 119043500 # number of overall miss cycles 694system.cpu.itb_walker_cache.overall_miss_latency::total 119043500 # number of overall miss cycles 695system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36443 # number of ReadReq accesses(hits+misses) 696system.cpu.itb_walker_cache.ReadReq_accesses::total 36443 # number of ReadReq accesses(hits+misses) | 664system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25691 # number of demand (read+write) hits 665system.cpu.itb_walker_cache.demand_hits::total 25691 # number of demand (read+write) hits 666system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25691 # number of overall hits 667system.cpu.itb_walker_cache.overall_hits::total 25691 # number of overall hits 668system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10488 # number of ReadReq misses 669system.cpu.itb_walker_cache.ReadReq_misses::total 10488 # number of ReadReq misses 670system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10488 # number of demand (read+write) misses 671system.cpu.itb_walker_cache.demand_misses::total 10488 # number of demand (read+write) misses 672system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10488 # number of overall misses 673system.cpu.itb_walker_cache.overall_misses::total 10488 # number of overall misses 674system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116654500 # number of ReadReq miss cycles 675system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116654500 # number of ReadReq miss cycles 676system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116654500 # number of demand (read+write) miss cycles 677system.cpu.itb_walker_cache.demand_miss_latency::total 116654500 # number of demand (read+write) miss cycles 678system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116654500 # number of overall miss cycles 679system.cpu.itb_walker_cache.overall_miss_latency::total 116654500 # number of overall miss cycles 680system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36177 # number of ReadReq accesses(hits+misses) 681system.cpu.itb_walker_cache.ReadReq_accesses::total 36177 # number of ReadReq accesses(hits+misses) |
| 697system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 698system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 682system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 683system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 699system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36445 # number of demand (read+write) accesses 700system.cpu.itb_walker_cache.demand_accesses::total 36445 # number of demand (read+write) accesses 701system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36445 # number of overall (read+write) accesses 702system.cpu.itb_walker_cache.overall_accesses::total 36445 # number of overall (read+write) accesses 703system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.291304 # miss rate for ReadReq accesses 704system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.291304 # miss rate for ReadReq accesses 705system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.291288 # miss rate for demand accesses 706system.cpu.itb_walker_cache.demand_miss_rate::total 0.291288 # miss rate for demand accesses 707system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.291288 # miss rate for overall accesses 708system.cpu.itb_walker_cache.overall_miss_rate::total 0.291288 # miss rate for overall accesses 709system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11213.592690 # average ReadReq miss latency 710system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11213.592690 # average ReadReq miss latency 711system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency 712system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11213.592690 # average overall miss latency 713system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency 714system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11213.592690 # average overall miss latency | 684system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36179 # number of demand (read+write) accesses 685system.cpu.itb_walker_cache.demand_accesses::total 36179 # number of demand (read+write) accesses 686system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36179 # number of overall (read+write) accesses 687system.cpu.itb_walker_cache.overall_accesses::total 36179 # number of overall (read+write) accesses 688system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.289908 # miss rate for ReadReq accesses 689system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.289908 # miss rate for ReadReq accesses 690system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.289892 # miss rate for demand accesses 691system.cpu.itb_walker_cache.demand_miss_rate::total 0.289892 # miss rate for demand accesses 692system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.289892 # miss rate for overall accesses 693system.cpu.itb_walker_cache.overall_miss_rate::total 0.289892 # miss rate for overall accesses 694system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11122.663997 # average ReadReq miss latency 695system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11122.663997 # average ReadReq miss latency 696system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency 697system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11122.663997 # average overall miss latency 698system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency 699system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11122.663997 # average overall miss latency |
| 715system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 716system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 717system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 718system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 719system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 720system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 721system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 722system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 700system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 701system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 702system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 703system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 704system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 705system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 706system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 707system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 723system.cpu.itb_walker_cache.writebacks::writebacks 2031 # number of writebacks 724system.cpu.itb_walker_cache.writebacks::total 2031 # number of writebacks 725system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10616 # number of ReadReq MSHR misses 726system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10616 # number of ReadReq MSHR misses 727system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10616 # number of demand (read+write) MSHR misses 728system.cpu.itb_walker_cache.demand_mshr_misses::total 10616 # number of demand (read+write) MSHR misses 729system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10616 # number of overall MSHR misses 730system.cpu.itb_walker_cache.overall_mshr_misses::total 10616 # number of overall MSHR misses 731system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97811500 # number of ReadReq MSHR miss cycles 732system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97811500 # number of ReadReq MSHR miss cycles 733system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 97811500 # number of demand (read+write) MSHR miss cycles 734system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 97811500 # number of demand (read+write) MSHR miss cycles 735system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97811500 # number of overall MSHR miss cycles 736system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97811500 # number of overall MSHR miss cycles 737system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.291304 # mshr miss rate for ReadReq accesses 738system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.291304 # mshr miss rate for ReadReq accesses 739system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for demand accesses 740system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.291288 # mshr miss rate for demand accesses 741system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for overall accesses 742system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.291288 # mshr miss rate for overall accesses 743system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average ReadReq mshr miss latency 744system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9213.592690 # average ReadReq mshr miss latency 745system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency 746system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency 747system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency 748system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency | 708system.cpu.itb_walker_cache.writebacks::writebacks 1936 # number of writebacks 709system.cpu.itb_walker_cache.writebacks::total 1936 # number of writebacks 710system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10488 # number of ReadReq MSHR misses 711system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10488 # number of ReadReq MSHR misses 712system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10488 # number of demand (read+write) MSHR misses 713system.cpu.itb_walker_cache.demand_mshr_misses::total 10488 # number of demand (read+write) MSHR misses 714system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10488 # number of overall MSHR misses 715system.cpu.itb_walker_cache.overall_mshr_misses::total 10488 # number of overall MSHR misses 716system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 95678500 # number of ReadReq MSHR miss cycles 717system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 95678500 # number of ReadReq MSHR miss cycles 718system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 95678500 # number of demand (read+write) MSHR miss cycles 719system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 95678500 # number of demand (read+write) MSHR miss cycles 720system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 95678500 # number of overall MSHR miss cycles 721system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 95678500 # number of overall MSHR miss cycles 722system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.289908 # mshr miss rate for ReadReq accesses 723system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.289908 # mshr miss rate for ReadReq accesses 724system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for demand accesses 725system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.289892 # mshr miss rate for demand accesses 726system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for overall accesses 727system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.289892 # mshr miss rate for overall accesses 728system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average ReadReq mshr miss latency 729system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9122.663997 # average ReadReq mshr miss latency 730system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency 731system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency 732system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency 733system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency |
| 749system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 734system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 750system.cpu.dtb_walker_cache.replacements 109067 # number of replacements 751system.cpu.dtb_walker_cache.tagsinuse 12.961436 # Cycle average of tags in use 752system.cpu.dtb_walker_cache.total_refs 135080 # Total number of references to valid blocks. 753system.cpu.dtb_walker_cache.sampled_refs 109080 # Sample count of references to valid blocks. 754system.cpu.dtb_walker_cache.avg_refs 1.238357 # Average number of references to valid blocks. 755system.cpu.dtb_walker_cache.warmup_cycle 5099784110000 # Cycle when the warmup percentage was hit. 756system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.961436 # Average occupied blocks per requestor 757system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810090 # Average percentage of cache occupancy 758system.cpu.dtb_walker_cache.occ_percent::total 0.810090 # Average percentage of cache occupancy 759system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135158 # number of ReadReq hits 760system.cpu.dtb_walker_cache.ReadReq_hits::total 135158 # number of ReadReq hits 761system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135158 # number of demand (read+write) hits 762system.cpu.dtb_walker_cache.demand_hits::total 135158 # number of demand (read+write) hits 763system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135158 # number of overall hits 764system.cpu.dtb_walker_cache.overall_hits::total 135158 # number of overall hits 765system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110111 # number of ReadReq misses 766system.cpu.dtb_walker_cache.ReadReq_misses::total 110111 # number of ReadReq misses 767system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110111 # number of demand (read+write) misses 768system.cpu.dtb_walker_cache.demand_misses::total 110111 # number of demand (read+write) misses 769system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110111 # number of overall misses 770system.cpu.dtb_walker_cache.overall_misses::total 110111 # number of overall misses 771system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1384932000 # number of ReadReq miss cycles 772system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1384932000 # number of ReadReq miss cycles 773system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1384932000 # number of demand (read+write) miss cycles 774system.cpu.dtb_walker_cache.demand_miss_latency::total 1384932000 # number of demand (read+write) miss cycles 775system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1384932000 # number of overall miss cycles 776system.cpu.dtb_walker_cache.overall_miss_latency::total 1384932000 # number of overall miss cycles 777system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245269 # number of ReadReq accesses(hits+misses) 778system.cpu.dtb_walker_cache.ReadReq_accesses::total 245269 # number of ReadReq accesses(hits+misses) 779system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245269 # number of demand (read+write) accesses 780system.cpu.dtb_walker_cache.demand_accesses::total 245269 # number of demand (read+write) accesses 781system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245269 # number of overall (read+write) accesses 782system.cpu.dtb_walker_cache.overall_accesses::total 245269 # number of overall (read+write) accesses 783system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.448940 # miss rate for ReadReq accesses 784system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.448940 # miss rate for ReadReq accesses 785system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.448940 # miss rate for demand accesses 786system.cpu.dtb_walker_cache.demand_miss_rate::total 0.448940 # miss rate for demand accesses 787system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.448940 # miss rate for overall accesses 788system.cpu.dtb_walker_cache.overall_miss_rate::total 0.448940 # miss rate for overall accesses 789system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12577.598968 # average ReadReq miss latency 790system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12577.598968 # average ReadReq miss latency 791system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency 792system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12577.598968 # average overall miss latency 793system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency 794system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12577.598968 # average overall miss latency | 735system.cpu.dtb_walker_cache.replacements 108181 # number of replacements 736system.cpu.dtb_walker_cache.tagsinuse 12.959012 # Cycle average of tags in use 737system.cpu.dtb_walker_cache.total_refs 134869 # Total number of references to valid blocks. 738system.cpu.dtb_walker_cache.sampled_refs 108196 # Sample count of references to valid blocks. 739system.cpu.dtb_walker_cache.avg_refs 1.246525 # Average number of references to valid blocks. 740system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. 741system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959012 # Average occupied blocks per requestor 742system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809938 # Average percentage of cache occupancy 743system.cpu.dtb_walker_cache.occ_percent::total 0.809938 # Average percentage of cache occupancy 744system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134886 # number of ReadReq hits 745system.cpu.dtb_walker_cache.ReadReq_hits::total 134886 # number of ReadReq hits 746system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134886 # number of demand (read+write) hits 747system.cpu.dtb_walker_cache.demand_hits::total 134886 # number of demand (read+write) hits 748system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134886 # number of overall hits 749system.cpu.dtb_walker_cache.overall_hits::total 134886 # number of overall hits 750system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109218 # number of ReadReq misses 751system.cpu.dtb_walker_cache.ReadReq_misses::total 109218 # number of ReadReq misses 752system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109218 # number of demand (read+write) misses 753system.cpu.dtb_walker_cache.demand_misses::total 109218 # number of demand (read+write) misses 754system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109218 # number of overall misses 755system.cpu.dtb_walker_cache.overall_misses::total 109218 # number of overall misses 756system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1375116000 # number of ReadReq miss cycles 757system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1375116000 # number of ReadReq miss cycles 758system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1375116000 # number of demand (read+write) miss cycles 759system.cpu.dtb_walker_cache.demand_miss_latency::total 1375116000 # number of demand (read+write) miss cycles 760system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1375116000 # number of overall miss cycles 761system.cpu.dtb_walker_cache.overall_miss_latency::total 1375116000 # number of overall miss cycles 762system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244104 # number of ReadReq accesses(hits+misses) 763system.cpu.dtb_walker_cache.ReadReq_accesses::total 244104 # number of ReadReq accesses(hits+misses) 764system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244104 # number of demand (read+write) accesses 765system.cpu.dtb_walker_cache.demand_accesses::total 244104 # number of demand (read+write) accesses 766system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244104 # number of overall (read+write) accesses 767system.cpu.dtb_walker_cache.overall_accesses::total 244104 # number of overall (read+write) accesses 768system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447424 # miss rate for ReadReq accesses 769system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447424 # miss rate for ReadReq accesses 770system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447424 # miss rate for demand accesses 771system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447424 # miss rate for demand accesses 772system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447424 # miss rate for overall accesses 773system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447424 # miss rate for overall accesses 774system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12590.561995 # average ReadReq miss latency 775system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12590.561995 # average ReadReq miss latency 776system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency 777system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12590.561995 # average overall miss latency 778system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency 779system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12590.561995 # average overall miss latency |
| 795system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 796system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 797system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 798system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 799system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 800system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 801system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 802system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 780system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 781system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 783system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 785system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 787system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 803system.cpu.dtb_walker_cache.writebacks::writebacks 36570 # number of writebacks 804system.cpu.dtb_walker_cache.writebacks::total 36570 # number of writebacks 805system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110111 # number of ReadReq MSHR misses 806system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110111 # number of ReadReq MSHR misses 807system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110111 # number of demand (read+write) MSHR misses 808system.cpu.dtb_walker_cache.demand_mshr_misses::total 110111 # number of demand (read+write) MSHR misses 809system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110111 # number of overall MSHR misses 810system.cpu.dtb_walker_cache.overall_mshr_misses::total 110111 # number of overall MSHR misses 811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of ReadReq MSHR miss cycles 812system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1164710000 # number of ReadReq MSHR miss cycles 813system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of demand (read+write) MSHR miss cycles 814system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1164710000 # number of demand (read+write) MSHR miss cycles 815system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of overall MSHR miss cycles 816system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1164710000 # number of overall MSHR miss cycles 817system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for ReadReq accesses 818system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.448940 # mshr miss rate for ReadReq accesses 819system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for demand accesses 820system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.448940 # mshr miss rate for demand accesses 821system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for overall accesses 822system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.448940 # mshr miss rate for overall accesses 823system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average ReadReq mshr miss latency 824system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10577.598968 # average ReadReq mshr miss latency 825system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency 826system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency 827system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency 828system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency | 788system.cpu.dtb_walker_cache.writebacks::writebacks 35252 # number of writebacks 789system.cpu.dtb_walker_cache.writebacks::total 35252 # number of writebacks 790system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109218 # number of ReadReq MSHR misses 791system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109218 # number of ReadReq MSHR misses 792system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109218 # number of demand (read+write) MSHR misses 793system.cpu.dtb_walker_cache.demand_mshr_misses::total 109218 # number of demand (read+write) MSHR misses 794system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109218 # number of overall MSHR misses 795system.cpu.dtb_walker_cache.overall_mshr_misses::total 109218 # number of overall MSHR misses 796system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of ReadReq MSHR miss cycles 797system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1156680000 # number of ReadReq MSHR miss cycles 798system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of demand (read+write) MSHR miss cycles 799system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1156680000 # number of demand (read+write) MSHR miss cycles 800system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of overall MSHR miss cycles 801system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1156680000 # number of overall MSHR miss cycles 802system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447424 # mshr miss rate for ReadReq accesses 804system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for demand accesses 805system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447424 # mshr miss rate for demand accesses 806system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for overall accesses 807system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447424 # mshr miss rate for overall accesses 808system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average ReadReq mshr miss latency 809system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10590.561995 # average ReadReq mshr miss latency 810system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency 811system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency 812system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency 813system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency |
| 829system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 814system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 830system.cpu.dcache.replacements 1659765 # number of replacements 831system.cpu.dcache.tagsinuse 511.990842 # Cycle average of tags in use 832system.cpu.dcache.total_refs 19082473 # Total number of references to valid blocks. 833system.cpu.dcache.sampled_refs 1660277 # Sample count of references to valid blocks. 834system.cpu.dcache.avg_refs 11.493548 # Average number of references to valid blocks. | 815system.cpu.dcache.replacements 1660118 # number of replacements 816system.cpu.dcache.tagsinuse 511.992206 # Cycle average of tags in use 817system.cpu.dcache.total_refs 19078637 # Total number of references to valid blocks. 818system.cpu.dcache.sampled_refs 1660630 # Sample count of references to valid blocks. 819system.cpu.dcache.avg_refs 11.488795 # Average number of references to valid blocks. |
| 835system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. | 820system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. |
| 836system.cpu.dcache.occ_blocks::cpu.data 511.990842 # Average occupied blocks per requestor 837system.cpu.dcache.occ_percent::cpu.data 0.999982 # Average percentage of cache occupancy 838system.cpu.dcache.occ_percent::total 0.999982 # Average percentage of cache occupancy 839system.cpu.dcache.ReadReq_hits::cpu.data 10992813 # number of ReadReq hits 840system.cpu.dcache.ReadReq_hits::total 10992813 # number of ReadReq hits 841system.cpu.dcache.WriteReq_hits::cpu.data 8084535 # number of WriteReq hits 842system.cpu.dcache.WriteReq_hits::total 8084535 # number of WriteReq hits 843system.cpu.dcache.demand_hits::cpu.data 19077348 # number of demand (read+write) hits 844system.cpu.dcache.demand_hits::total 19077348 # number of demand (read+write) hits 845system.cpu.dcache.overall_hits::cpu.data 19077348 # number of overall hits 846system.cpu.dcache.overall_hits::total 19077348 # number of overall hits 847system.cpu.dcache.ReadReq_misses::cpu.data 2235315 # number of ReadReq misses 848system.cpu.dcache.ReadReq_misses::total 2235315 # number of ReadReq misses 849system.cpu.dcache.WriteReq_misses::cpu.data 318075 # number of WriteReq misses 850system.cpu.dcache.WriteReq_misses::total 318075 # number of WriteReq misses 851system.cpu.dcache.demand_misses::cpu.data 2553390 # number of demand (read+write) misses 852system.cpu.dcache.demand_misses::total 2553390 # number of demand (read+write) misses 853system.cpu.dcache.overall_misses::cpu.data 2553390 # number of overall misses 854system.cpu.dcache.overall_misses::total 2553390 # number of overall misses 855system.cpu.dcache.ReadReq_miss_latency::cpu.data 32075751500 # number of ReadReq miss cycles 856system.cpu.dcache.ReadReq_miss_latency::total 32075751500 # number of ReadReq miss cycles 857system.cpu.dcache.WriteReq_miss_latency::cpu.data 9669659497 # number of WriteReq miss cycles 858system.cpu.dcache.WriteReq_miss_latency::total 9669659497 # number of WriteReq miss cycles 859system.cpu.dcache.demand_miss_latency::cpu.data 41745410997 # number of demand (read+write) miss cycles 860system.cpu.dcache.demand_miss_latency::total 41745410997 # number of demand (read+write) miss cycles 861system.cpu.dcache.overall_miss_latency::cpu.data 41745410997 # number of overall miss cycles 862system.cpu.dcache.overall_miss_latency::total 41745410997 # number of overall miss cycles 863system.cpu.dcache.ReadReq_accesses::cpu.data 13228128 # number of ReadReq accesses(hits+misses) 864system.cpu.dcache.ReadReq_accesses::total 13228128 # number of ReadReq accesses(hits+misses) 865system.cpu.dcache.WriteReq_accesses::cpu.data 8402610 # number of WriteReq accesses(hits+misses) 866system.cpu.dcache.WriteReq_accesses::total 8402610 # number of WriteReq accesses(hits+misses) 867system.cpu.dcache.demand_accesses::cpu.data 21630738 # number of demand (read+write) accesses 868system.cpu.dcache.demand_accesses::total 21630738 # number of demand (read+write) accesses 869system.cpu.dcache.overall_accesses::cpu.data 21630738 # number of overall (read+write) accesses 870system.cpu.dcache.overall_accesses::total 21630738 # number of overall (read+write) accesses 871system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168982 # miss rate for ReadReq accesses 872system.cpu.dcache.ReadReq_miss_rate::total 0.168982 # miss rate for ReadReq accesses 873system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037854 # miss rate for WriteReq accesses 874system.cpu.dcache.WriteReq_miss_rate::total 0.037854 # miss rate for WriteReq accesses 875system.cpu.dcache.demand_miss_rate::cpu.data 0.118045 # miss rate for demand accesses 876system.cpu.dcache.demand_miss_rate::total 0.118045 # miss rate for demand accesses 877system.cpu.dcache.overall_miss_rate::cpu.data 0.118045 # miss rate for overall accesses 878system.cpu.dcache.overall_miss_rate::total 0.118045 # miss rate for overall accesses 879system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14349.544248 # average ReadReq miss latency 880system.cpu.dcache.ReadReq_avg_miss_latency::total 14349.544248 # average ReadReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30400.564323 # average WriteReq miss latency 882system.cpu.dcache.WriteReq_avg_miss_latency::total 30400.564323 # average WriteReq miss latency 883system.cpu.dcache.demand_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency 884system.cpu.dcache.demand_avg_miss_latency::total 16349.014838 # average overall miss latency 885system.cpu.dcache.overall_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency 886system.cpu.dcache.overall_avg_miss_latency::total 16349.014838 # average overall miss latency 887system.cpu.dcache.blocked_cycles::no_mshrs 385443 # number of cycles access was blocked | 821system.cpu.dcache.occ_blocks::cpu.data 511.992206 # Average occupied blocks per requestor 822system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy 823system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy 824system.cpu.dcache.ReadReq_hits::cpu.data 10987895 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 10987895 # number of ReadReq hits 826system.cpu.dcache.WriteReq_hits::cpu.data 8085738 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 8085738 # number of WriteReq hits 828system.cpu.dcache.demand_hits::cpu.data 19073633 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 19073633 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 19073633 # number of overall hits 831system.cpu.dcache.overall_hits::total 19073633 # number of overall hits 832system.cpu.dcache.ReadReq_misses::cpu.data 2236252 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2236252 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 317957 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 317957 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2554209 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2554209 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2554209 # number of overall misses 839system.cpu.dcache.overall_misses::total 2554209 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 32134007500 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 32134007500 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 9664278994 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 9664278994 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 41798286494 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 41798286494 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 41798286494 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 41798286494 # number of overall miss cycles 848system.cpu.dcache.ReadReq_accesses::cpu.data 13224147 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 13224147 # number of ReadReq accesses(hits+misses) 850system.cpu.dcache.WriteReq_accesses::cpu.data 8403695 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 8403695 # number of WriteReq accesses(hits+misses) 852system.cpu.dcache.demand_accesses::cpu.data 21627842 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 21627842 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 21627842 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 21627842 # number of overall (read+write) accesses 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169104 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.169104 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037835 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.037835 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.118098 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.118098 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.118098 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.118098 # miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14369.582453 # average ReadReq miss latency 865system.cpu.dcache.ReadReq_avg_miss_latency::total 14369.582453 # average ReadReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30394.924452 # average WriteReq miss latency 867system.cpu.dcache.WriteReq_avg_miss_latency::total 30394.924452 # average WriteReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 16364.473892 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 16364.473892 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 400642 # number of cycles access was blocked |
| 888system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 889system.cpu.dcache.blocked::no_mshrs 42285 # number of cycles access was blocked | 874system.cpu.dcache.blocked::no_mshrs 42486 # number of cycles access was blocked |
| 890system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 891system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.115360 # average number of cycles each access was blocked | 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.429977 # average number of cycles each access was blocked |
| 892system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 893system.cpu.dcache.fast_writes 0 # number of fast writes performed 894system.cpu.dcache.cache_copies 0 # number of cache copies performed | 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 895system.cpu.dcache.writebacks::writebacks 1561573 # number of writebacks 896system.cpu.dcache.writebacks::total 1561573 # number of writebacks 897system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863477 # number of ReadReq MSHR hits 898system.cpu.dcache.ReadReq_mshr_hits::total 863477 # number of ReadReq MSHR hits 899system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24970 # number of WriteReq MSHR hits 900system.cpu.dcache.WriteReq_mshr_hits::total 24970 # number of WriteReq MSHR hits 901system.cpu.dcache.demand_mshr_hits::cpu.data 888447 # number of demand (read+write) MSHR hits 902system.cpu.dcache.demand_mshr_hits::total 888447 # number of demand (read+write) MSHR hits 903system.cpu.dcache.overall_mshr_hits::cpu.data 888447 # number of overall MSHR hits 904system.cpu.dcache.overall_mshr_hits::total 888447 # number of overall MSHR hits 905system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371838 # number of ReadReq MSHR misses 906system.cpu.dcache.ReadReq_mshr_misses::total 1371838 # number of ReadReq MSHR misses 907system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293105 # number of WriteReq MSHR misses 908system.cpu.dcache.WriteReq_mshr_misses::total 293105 # number of WriteReq MSHR misses 909system.cpu.dcache.demand_mshr_misses::cpu.data 1664943 # number of demand (read+write) MSHR misses 910system.cpu.dcache.demand_mshr_misses::total 1664943 # number of demand (read+write) MSHR misses 911system.cpu.dcache.overall_mshr_misses::cpu.data 1664943 # number of overall MSHR misses 912system.cpu.dcache.overall_mshr_misses::total 1664943 # number of overall MSHR misses 913system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17433703000 # number of ReadReq MSHR miss cycles 914system.cpu.dcache.ReadReq_mshr_miss_latency::total 17433703000 # number of ReadReq MSHR miss cycles 915system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8829680997 # number of WriteReq MSHR miss cycles 916system.cpu.dcache.WriteReq_mshr_miss_latency::total 8829680997 # number of WriteReq MSHR miss cycles 917system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26263383997 # number of demand (read+write) MSHR miss cycles 918system.cpu.dcache.demand_mshr_miss_latency::total 26263383997 # number of demand (read+write) MSHR miss cycles 919system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26263383997 # number of overall MSHR miss cycles 920system.cpu.dcache.overall_mshr_miss_latency::total 26263383997 # number of overall MSHR miss cycles 921system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296997000 # number of ReadReq MSHR uncacheable cycles 922system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296997000 # number of ReadReq MSHR uncacheable cycles 923system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470922500 # number of WriteReq MSHR uncacheable cycles 924system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470922500 # number of WriteReq MSHR uncacheable cycles 925system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767919500 # number of overall MSHR uncacheable cycles 926system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767919500 # number of overall MSHR uncacheable cycles 927system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103706 # mshr miss rate for ReadReq accesses 928system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103706 # mshr miss rate for ReadReq accesses 929system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034883 # mshr miss rate for WriteReq accesses 930system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034883 # mshr miss rate for WriteReq accesses 931system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076971 # mshr miss rate for demand accesses 932system.cpu.dcache.demand_mshr_miss_rate::total 0.076971 # mshr miss rate for demand accesses 933system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076971 # mshr miss rate for overall accesses 934system.cpu.dcache.overall_mshr_miss_rate::total 0.076971 # mshr miss rate for overall accesses 935system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12708.281153 # average ReadReq mshr miss latency 936system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12708.281153 # average ReadReq mshr miss latency 937system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30124.634506 # average WriteReq mshr miss latency 938system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30124.634506 # average WriteReq mshr miss latency 939system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15774.344225 # average overall mshr miss latency 940system.cpu.dcache.demand_avg_mshr_miss_latency::total 15774.344225 # average overall mshr miss latency 941system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15774.344225 # average overall mshr miss latency 942system.cpu.dcache.overall_avg_mshr_miss_latency::total 15774.344225 # average overall mshr miss latency | 880system.cpu.dcache.writebacks::writebacks 1561388 # number of writebacks 881system.cpu.dcache.writebacks::total 1561388 # number of writebacks 882system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864027 # number of ReadReq MSHR hits 883system.cpu.dcache.ReadReq_mshr_hits::total 864027 # number of ReadReq MSHR hits 884system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25006 # number of WriteReq MSHR hits 885system.cpu.dcache.WriteReq_mshr_hits::total 25006 # number of WriteReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 889033 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 889033 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 889033 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 889033 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1372225 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 1372225 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292951 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 292951 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 1665176 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 1665176 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 1665176 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 1665176 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17481793000 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 17481793000 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8820305494 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 8820305494 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26302098494 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 26302098494 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26302098494 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 26302098494 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296698500 # number of ReadReq MSHR uncacheable cycles 907system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296698500 # number of ReadReq MSHR uncacheable cycles 908system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470686500 # number of WriteReq MSHR uncacheable cycles 909system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470686500 # number of WriteReq MSHR uncacheable cycles 910system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767385000 # number of overall MSHR uncacheable cycles 911system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767385000 # number of overall MSHR uncacheable cycles 912system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103767 # mshr miss rate for ReadReq accesses 913system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103767 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034860 # mshr miss rate for WriteReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034860 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for demand accesses 917system.cpu.dcache.demand_mshr_miss_rate::total 0.076992 # mshr miss rate for demand accesses 918system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for overall accesses 919system.cpu.dcache.overall_mshr_miss_rate::total 0.076992 # mshr miss rate for overall accesses 920system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12739.742389 # average ReadReq mshr miss latency 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12739.742389 # average ReadReq mshr miss latency 922system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30108.466925 # average WriteReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30108.466925 # average WriteReq mshr miss latency 924system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency 926system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency |
| 943system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 944system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 945system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 946system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 947system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 948system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 949system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 928system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 929system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 930system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 931system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 932system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 933system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 950system.cpu.l2cache.replacements 113143 # number of replacements 951system.cpu.l2cache.tagsinuse 64828.008913 # Cycle average of tags in use 952system.cpu.l2cache.total_refs 3933194 # Total number of references to valid blocks. 953system.cpu.l2cache.sampled_refs 177289 # Sample count of references to valid blocks. 954system.cpu.l2cache.avg_refs 22.185212 # Average number of references to valid blocks. | 935system.cpu.l2cache.replacements 113561 # number of replacements 936system.cpu.l2cache.tagsinuse 64842.483679 # Cycle average of tags in use 937system.cpu.l2cache.total_refs 3930962 # Total number of references to valid blocks. 938system.cpu.l2cache.sampled_refs 177626 # Sample count of references to valid blocks. 939system.cpu.l2cache.avg_refs 22.130555 # Average number of references to valid blocks. |
| 955system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 940system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 956system.cpu.l2cache.occ_blocks::writebacks 50000.769302 # Average occupied blocks per requestor 957system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.826981 # Average occupied blocks per requestor 958system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.134900 # Average occupied blocks per requestor 959system.cpu.l2cache.occ_blocks::cpu.inst 3307.164355 # Average occupied blocks per requestor 960system.cpu.l2cache.occ_blocks::cpu.data 11509.113375 # Average occupied blocks per requestor 961system.cpu.l2cache.occ_percent::writebacks 0.762951 # Average percentage of cache occupancy 962system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000165 # Average percentage of cache occupancy | 941system.cpu.l2cache.occ_blocks::writebacks 50033.446344 # Average occupied blocks per requestor 942system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.888296 # Average occupied blocks per requestor 943system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133449 # Average occupied blocks per requestor 944system.cpu.l2cache.occ_blocks::cpu.inst 3280.677554 # Average occupied blocks per requestor 945system.cpu.l2cache.occ_blocks::cpu.data 11517.338036 # Average occupied blocks per requestor 946system.cpu.l2cache.occ_percent::writebacks 0.763450 # Average percentage of cache occupancy 947system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy |
| 963system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 948system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 964system.cpu.l2cache.occ_percent::cpu.inst 0.050463 # Average percentage of cache occupancy 965system.cpu.l2cache.occ_percent::cpu.data 0.175615 # Average percentage of cache occupancy 966system.cpu.l2cache.occ_percent::total 0.989197 # Average percentage of cache occupancy 967system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102962 # number of ReadReq hits 968system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8277 # number of ReadReq hits 969system.cpu.l2cache.ReadReq_hits::cpu.inst 1030819 # number of ReadReq hits 970system.cpu.l2cache.ReadReq_hits::cpu.data 1333964 # number of ReadReq hits 971system.cpu.l2cache.ReadReq_hits::total 2476022 # number of ReadReq hits 972system.cpu.l2cache.Writeback_hits::writebacks 1600174 # number of Writeback hits 973system.cpu.l2cache.Writeback_hits::total 1600174 # number of Writeback hits 974system.cpu.l2cache.UpgradeReq_hits::cpu.data 327 # number of UpgradeReq hits 975system.cpu.l2cache.UpgradeReq_hits::total 327 # number of UpgradeReq hits 976system.cpu.l2cache.ReadExReq_hits::cpu.data 156003 # number of ReadExReq hits 977system.cpu.l2cache.ReadExReq_hits::total 156003 # number of ReadExReq hits 978system.cpu.l2cache.demand_hits::cpu.dtb.walker 102962 # number of demand (read+write) hits 979system.cpu.l2cache.demand_hits::cpu.itb.walker 8277 # number of demand (read+write) hits 980system.cpu.l2cache.demand_hits::cpu.inst 1030819 # number of demand (read+write) hits 981system.cpu.l2cache.demand_hits::cpu.data 1489967 # number of demand (read+write) hits 982system.cpu.l2cache.demand_hits::total 2632025 # number of demand (read+write) hits 983system.cpu.l2cache.overall_hits::cpu.dtb.walker 102962 # number of overall hits 984system.cpu.l2cache.overall_hits::cpu.itb.walker 8277 # number of overall hits 985system.cpu.l2cache.overall_hits::cpu.inst 1030819 # number of overall hits 986system.cpu.l2cache.overall_hits::cpu.data 1489967 # number of overall hits 987system.cpu.l2cache.overall_hits::total 2632025 # number of overall hits 988system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses | 949system.cpu.l2cache.occ_percent::cpu.inst 0.050059 # Average percentage of cache occupancy 950system.cpu.l2cache.occ_percent::cpu.data 0.175741 # Average percentage of cache occupancy 951system.cpu.l2cache.occ_percent::total 0.989418 # Average percentage of cache occupancy 952system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102246 # number of ReadReq hits 953system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8058 # number of ReadReq hits 954system.cpu.l2cache.ReadReq_hits::cpu.inst 1029420 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.data 1334149 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 2473873 # number of ReadReq hits 957system.cpu.l2cache.Writeback_hits::writebacks 1598576 # number of Writeback hits 958system.cpu.l2cache.Writeback_hits::total 1598576 # number of Writeback hits 959system.cpu.l2cache.UpgradeReq_hits::cpu.data 345 # number of UpgradeReq hits 960system.cpu.l2cache.UpgradeReq_hits::total 345 # number of UpgradeReq hits 961system.cpu.l2cache.ReadExReq_hits::cpu.data 156103 # number of ReadExReq hits 962system.cpu.l2cache.ReadExReq_hits::total 156103 # number of ReadExReq hits 963system.cpu.l2cache.demand_hits::cpu.dtb.walker 102246 # number of demand (read+write) hits 964system.cpu.l2cache.demand_hits::cpu.itb.walker 8058 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.inst 1029420 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1490252 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2629976 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.dtb.walker 102246 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.itb.walker 8058 # number of overall hits 970system.cpu.l2cache.overall_hits::cpu.inst 1029420 # number of overall hits 971system.cpu.l2cache.overall_hits::cpu.data 1490252 # number of overall hits 972system.cpu.l2cache.overall_hits::total 2629976 # number of overall hits 973system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses |
| 989system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses | 974system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses |
| 990system.cpu.l2cache.ReadReq_misses::cpu.inst 16851 # number of ReadReq misses 991system.cpu.l2cache.ReadReq_misses::cpu.data 36698 # number of ReadReq misses 992system.cpu.l2cache.ReadReq_misses::total 53603 # number of ReadReq misses 993system.cpu.l2cache.UpgradeReq_misses::cpu.data 3825 # number of UpgradeReq misses 994system.cpu.l2cache.UpgradeReq_misses::total 3825 # number of UpgradeReq misses 995system.cpu.l2cache.ReadExReq_misses::cpu.data 133009 # number of ReadExReq misses 996system.cpu.l2cache.ReadExReq_misses::total 133009 # number of ReadExReq misses 997system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses | 975system.cpu.l2cache.ReadReq_misses::cpu.inst 16841 # number of ReadReq misses 976system.cpu.l2cache.ReadReq_misses::cpu.data 36881 # number of ReadReq misses 977system.cpu.l2cache.ReadReq_misses::total 53777 # number of ReadReq misses 978system.cpu.l2cache.UpgradeReq_misses::cpu.data 3693 # number of UpgradeReq misses 979system.cpu.l2cache.UpgradeReq_misses::total 3693 # number of UpgradeReq misses 980system.cpu.l2cache.ReadExReq_misses::cpu.data 132888 # number of ReadExReq misses 981system.cpu.l2cache.ReadExReq_misses::total 132888 # number of ReadExReq misses 982system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses |
| 998system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses | 983system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses |
| 999system.cpu.l2cache.demand_misses::cpu.inst 16851 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::cpu.data 169707 # number of demand (read+write) misses 1001system.cpu.l2cache.demand_misses::total 186612 # number of demand (read+write) misses 1002system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses | 984system.cpu.l2cache.demand_misses::cpu.inst 16841 # number of demand (read+write) misses 985system.cpu.l2cache.demand_misses::cpu.data 169769 # number of demand (read+write) misses 986system.cpu.l2cache.demand_misses::total 186665 # number of demand (read+write) misses 987system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses |
| 1003system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses | 988system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses |
| 1004system.cpu.l2cache.overall_misses::cpu.inst 16851 # number of overall misses 1005system.cpu.l2cache.overall_misses::cpu.data 169707 # number of overall misses 1006system.cpu.l2cache.overall_misses::total 186612 # number of overall misses 1007system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5800000 # number of ReadReq miss cycles | 989system.cpu.l2cache.overall_misses::cpu.inst 16841 # number of overall misses 990system.cpu.l2cache.overall_misses::cpu.data 169769 # number of overall misses 991system.cpu.l2cache.overall_misses::total 186665 # number of overall misses 992system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6312000 # number of ReadReq miss cycles |
| 1008system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles | 993system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles |
| 1009system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1177383500 # number of ReadReq miss cycles 1010system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2492698000 # number of ReadReq miss cycles 1011system.cpu.l2cache.ReadReq_miss_latency::total 3676271000 # number of ReadReq miss cycles 1012system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16893999 # number of UpgradeReq miss cycles 1013system.cpu.l2cache.UpgradeReq_miss_latency::total 16893999 # number of UpgradeReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6881289000 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadExReq_miss_latency::total 6881289000 # number of ReadExReq miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5800000 # number of demand (read+write) miss cycles | 994system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1177562500 # number of ReadReq miss cycles 995system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2538376499 # number of ReadReq miss cycles 996system.cpu.l2cache.ReadReq_miss_latency::total 3722640499 # number of ReadReq miss cycles 997system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16930000 # number of UpgradeReq miss cycles 998system.cpu.l2cache.UpgradeReq_miss_latency::total 16930000 # number of UpgradeReq miss cycles 999system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6874050999 # number of ReadExReq miss cycles 1000system.cpu.l2cache.ReadExReq_miss_latency::total 6874050999 # number of ReadExReq miss cycles 1001system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6312000 # number of demand (read+write) miss cycles |
| 1017system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles | 1002system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles |
| 1018system.cpu.l2cache.demand_miss_latency::cpu.inst 1177383500 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.demand_miss_latency::cpu.data 9373987000 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.demand_miss_latency::total 10557560000 # number of demand (read+write) miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5800000 # number of overall miss cycles | 1003system.cpu.l2cache.demand_miss_latency::cpu.inst 1177562500 # number of demand (read+write) miss cycles 1004system.cpu.l2cache.demand_miss_latency::cpu.data 9412427498 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.demand_miss_latency::total 10596691498 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6312000 # number of overall miss cycles |
| 1022system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles | 1007system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles |
| 1023system.cpu.l2cache.overall_miss_latency::cpu.inst 1177383500 # number of overall miss cycles 1024system.cpu.l2cache.overall_miss_latency::cpu.data 9373987000 # number of overall miss cycles 1025system.cpu.l2cache.overall_miss_latency::total 10557560000 # number of overall miss cycles 1026system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103010 # number of ReadReq accesses(hits+misses) 1027system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8283 # number of ReadReq accesses(hits+misses) 1028system.cpu.l2cache.ReadReq_accesses::cpu.inst 1047670 # number of ReadReq accesses(hits+misses) 1029system.cpu.l2cache.ReadReq_accesses::cpu.data 1370662 # number of ReadReq accesses(hits+misses) 1030system.cpu.l2cache.ReadReq_accesses::total 2529625 # number of ReadReq accesses(hits+misses) 1031system.cpu.l2cache.Writeback_accesses::writebacks 1600174 # number of Writeback accesses(hits+misses) 1032system.cpu.l2cache.Writeback_accesses::total 1600174 # number of Writeback accesses(hits+misses) 1033system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4152 # number of UpgradeReq accesses(hits+misses) 1034system.cpu.l2cache.UpgradeReq_accesses::total 4152 # number of UpgradeReq accesses(hits+misses) 1035system.cpu.l2cache.ReadExReq_accesses::cpu.data 289012 # number of ReadExReq accesses(hits+misses) 1036system.cpu.l2cache.ReadExReq_accesses::total 289012 # number of ReadExReq accesses(hits+misses) 1037system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103010 # number of demand (read+write) accesses 1038system.cpu.l2cache.demand_accesses::cpu.itb.walker 8283 # number of demand (read+write) accesses 1039system.cpu.l2cache.demand_accesses::cpu.inst 1047670 # number of demand (read+write) accesses 1040system.cpu.l2cache.demand_accesses::cpu.data 1659674 # number of demand (read+write) accesses 1041system.cpu.l2cache.demand_accesses::total 2818637 # number of demand (read+write) accesses 1042system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103010 # number of overall (read+write) accesses 1043system.cpu.l2cache.overall_accesses::cpu.itb.walker 8283 # number of overall (read+write) accesses 1044system.cpu.l2cache.overall_accesses::cpu.inst 1047670 # number of overall (read+write) accesses 1045system.cpu.l2cache.overall_accesses::cpu.data 1659674 # number of overall (read+write) accesses 1046system.cpu.l2cache.overall_accesses::total 2818637 # number of overall (read+write) accesses 1047system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000466 # miss rate for ReadReq accesses 1048system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000724 # miss rate for ReadReq accesses 1049system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016084 # miss rate for ReadReq accesses 1050system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026774 # miss rate for ReadReq accesses 1051system.cpu.l2cache.ReadReq_miss_rate::total 0.021190 # miss rate for ReadReq accesses 1052system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.921243 # miss rate for UpgradeReq accesses 1053system.cpu.l2cache.UpgradeReq_miss_rate::total 0.921243 # miss rate for UpgradeReq accesses 1054system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460220 # miss rate for ReadExReq accesses 1055system.cpu.l2cache.ReadExReq_miss_rate::total 0.460220 # miss rate for ReadExReq accesses 1056system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000466 # miss rate for demand accesses 1057system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000724 # miss rate for demand accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016084 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::cpu.data 0.102253 # miss rate for demand accesses 1060system.cpu.l2cache.demand_miss_rate::total 0.066206 # miss rate for demand accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000466 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000724 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016084 # miss rate for overall accesses 1064system.cpu.l2cache.overall_miss_rate::cpu.data 0.102253 # miss rate for overall accesses 1065system.cpu.l2cache.overall_miss_rate::total 0.066206 # miss rate for overall accesses 1066system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 120833.333333 # average ReadReq miss latency | 1008system.cpu.l2cache.overall_miss_latency::cpu.inst 1177562500 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.data 9412427498 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::total 10596691498 # number of overall miss cycles 1011system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 102295 # number of ReadReq accesses(hits+misses) 1012system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8064 # number of ReadReq accesses(hits+misses) 1013system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046261 # number of ReadReq accesses(hits+misses) 1014system.cpu.l2cache.ReadReq_accesses::cpu.data 1371030 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::total 2527650 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.Writeback_accesses::writebacks 1598576 # number of Writeback accesses(hits+misses) 1017system.cpu.l2cache.Writeback_accesses::total 1598576 # number of Writeback accesses(hits+misses) 1018system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4038 # number of UpgradeReq accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::total 4038 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.ReadExReq_accesses::cpu.data 288991 # number of ReadExReq accesses(hits+misses) 1021system.cpu.l2cache.ReadExReq_accesses::total 288991 # number of ReadExReq accesses(hits+misses) 1022system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102295 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::cpu.itb.walker 8064 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.inst 1046261 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 1660021 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 2816641 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102295 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.itb.walker 8064 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.inst 1046261 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::cpu.data 1660021 # number of overall (read+write) accesses 1031system.cpu.l2cache.overall_accesses::total 2816641 # number of overall (read+write) accesses 1032system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000479 # miss rate for ReadReq accesses 1033system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000744 # miss rate for ReadReq accesses 1034system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016096 # miss rate for ReadReq accesses 1035system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026900 # miss rate for ReadReq accesses 1036system.cpu.l2cache.ReadReq_miss_rate::total 0.021275 # miss rate for ReadReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.914562 # miss rate for UpgradeReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::total 0.914562 # miss rate for UpgradeReq accesses 1039system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459834 # miss rate for ReadExReq accesses 1040system.cpu.l2cache.ReadExReq_miss_rate::total 0.459834 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000479 # miss rate for demand accesses 1042system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000744 # miss rate for demand accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016096 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.data 0.102269 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::total 0.066272 # miss rate for demand accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000479 # miss rate for overall accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000744 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016096 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.data 0.102269 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::total 0.066272 # miss rate for overall accesses 1051system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 128816.326531 # average ReadReq miss latency |
| 1067system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency | 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency |
| 1068system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69870.245089 # average ReadReq miss latency 1069system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67924.628045 # average ReadReq miss latency 1070system.cpu.l2cache.ReadReq_avg_miss_latency::total 68583.306904 # average ReadReq miss latency 1071system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4416.731765 # average UpgradeReq miss latency 1072system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4416.731765 # average UpgradeReq miss latency 1073system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51735.514138 # average ReadExReq miss latency 1074system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51735.514138 # average ReadExReq miss latency 1075system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 120833.333333 # average overall miss latency | 1053system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69922.362093 # average ReadReq miss latency 1054system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68826.129959 # average ReadReq miss latency 1055system.cpu.l2cache.ReadReq_avg_miss_latency::total 69223.655076 # average ReadReq miss latency 1056system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4584.348768 # average UpgradeReq miss latency 1057system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4584.348768 # average UpgradeReq miss latency 1058system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51728.154529 # average ReadExReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51728.154529 # average ReadExReq miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency |
| 1076system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency | 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency |
| 1077system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69870.245089 # average overall miss latency 1078system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55236.301390 # average overall miss latency 1079system.cpu.l2cache.demand_avg_miss_latency::total 56574.925514 # average overall miss latency 1080system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 120833.333333 # average overall miss latency | 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency 1064system.cpu.l2cache.demand_avg_miss_latency::total 56768.497029 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency |
| 1081system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency | 1066system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency |
| 1082system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69870.245089 # average overall miss latency 1083system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55236.301390 # average overall miss latency 1084system.cpu.l2cache.overall_avg_miss_latency::total 56574.925514 # average overall miss latency | 1067system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency 1069system.cpu.l2cache.overall_avg_miss_latency::total 56768.497029 # average overall miss latency |
| 1085system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1086system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1087system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1088system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1089system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1090system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1091system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1092system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1070system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1077system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1093system.cpu.l2cache.writebacks::writebacks 102813 # number of writebacks 1094system.cpu.l2cache.writebacks::total 102813 # number of writebacks | 1078system.cpu.l2cache.writebacks::writebacks 102810 # number of writebacks 1079system.cpu.l2cache.writebacks::total 102810 # number of writebacks |
| 1095system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1096system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1097system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1098system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1099system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1100system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 1101system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1102system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1103system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits | 1080system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1081system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1082system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1083system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1084system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1085system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 1086system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1087system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1088system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits |
| 1104system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses | 1089system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses |
| 1105system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses | 1090system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses |
| 1106system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16850 # number of ReadReq MSHR misses 1107system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36697 # number of ReadReq MSHR misses 1108system.cpu.l2cache.ReadReq_mshr_misses::total 53601 # number of ReadReq MSHR misses 1109system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3825 # number of UpgradeReq MSHR misses 1110system.cpu.l2cache.UpgradeReq_mshr_misses::total 3825 # number of UpgradeReq MSHR misses 1111system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133009 # number of ReadExReq MSHR misses 1112system.cpu.l2cache.ReadExReq_mshr_misses::total 133009 # number of ReadExReq MSHR misses 1113system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses | 1091system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16840 # number of ReadReq MSHR misses 1092system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36880 # number of ReadReq MSHR misses 1093system.cpu.l2cache.ReadReq_mshr_misses::total 53775 # number of ReadReq MSHR misses 1094system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3693 # number of UpgradeReq MSHR misses 1095system.cpu.l2cache.UpgradeReq_mshr_misses::total 3693 # number of UpgradeReq MSHR misses 1096system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132888 # number of ReadExReq MSHR misses 1097system.cpu.l2cache.ReadExReq_mshr_misses::total 132888 # number of ReadExReq MSHR misses 1098system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses |
| 1114system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses | 1099system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses |
| 1115system.cpu.l2cache.demand_mshr_misses::cpu.inst 16850 # number of demand (read+write) MSHR misses 1116system.cpu.l2cache.demand_mshr_misses::cpu.data 169706 # number of demand (read+write) MSHR misses 1117system.cpu.l2cache.demand_mshr_misses::total 186610 # number of demand (read+write) MSHR misses 1118system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses | 1100system.cpu.l2cache.demand_mshr_misses::cpu.inst 16840 # number of demand (read+write) MSHR misses 1101system.cpu.l2cache.demand_mshr_misses::cpu.data 169768 # number of demand (read+write) MSHR misses 1102system.cpu.l2cache.demand_mshr_misses::total 186663 # number of demand (read+write) MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses |
| 1119system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses | 1104system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses |
| 1120system.cpu.l2cache.overall_mshr_misses::cpu.inst 16850 # number of overall MSHR misses 1121system.cpu.l2cache.overall_mshr_misses::cpu.data 169706 # number of overall MSHR misses 1122system.cpu.l2cache.overall_mshr_misses::total 186610 # number of overall MSHR misses 1123system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5203838 # number of ReadReq MSHR miss cycles 1124system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314260 # number of ReadReq MSHR miss cycles 1125system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967803547 # number of ReadReq MSHR miss cycles 1126system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2036732357 # number of ReadReq MSHR miss cycles 1127system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3010054002 # number of ReadReq MSHR miss cycles 1128system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39193303 # number of UpgradeReq MSHR miss cycles 1129system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39193303 # number of UpgradeReq MSHR miss cycles 1130system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5240927353 # number of ReadExReq MSHR miss cycles 1131system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5240927353 # number of ReadExReq MSHR miss cycles 1132system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5203838 # number of demand (read+write) MSHR miss cycles 1133system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314260 # number of demand (read+write) MSHR miss cycles 1134system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967803547 # number of demand (read+write) MSHR miss cycles 1135system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277659710 # number of demand (read+write) MSHR miss cycles 1136system.cpu.l2cache.demand_mshr_miss_latency::total 8250981355 # number of demand (read+write) MSHR miss cycles 1137system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5203838 # number of overall MSHR miss cycles 1138system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314260 # number of overall MSHR miss cycles 1139system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967803547 # number of overall MSHR miss cycles 1140system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277659710 # number of overall MSHR miss cycles 1141system.cpu.l2cache.overall_mshr_miss_latency::total 8250981355 # number of overall MSHR miss cycles 1142system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187688500 # number of ReadReq MSHR uncacheable cycles 1143system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187688500 # number of ReadReq MSHR uncacheable cycles 1144system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308713500 # number of WriteReq MSHR uncacheable cycles 1145system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308713500 # number of WriteReq MSHR uncacheable cycles 1146system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91496402000 # number of overall MSHR uncacheable cycles 1147system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91496402000 # number of overall MSHR uncacheable cycles 1148system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for ReadReq accesses 1149system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for ReadReq accesses 1150system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for ReadReq accesses 1151system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026773 # mshr miss rate for ReadReq accesses 1152system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021189 # mshr miss rate for ReadReq accesses 1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.921243 # mshr miss rate for UpgradeReq accesses 1154system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.921243 # mshr miss rate for UpgradeReq accesses 1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460220 # mshr miss rate for ReadExReq accesses 1156system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460220 # mshr miss rate for ReadExReq accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for demand accesses 1159system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for demand accesses 1160system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102253 # mshr miss rate for demand accesses 1161system.cpu.l2cache.demand_mshr_miss_rate::total 0.066206 # mshr miss rate for demand accesses 1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for overall accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for overall accesses 1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for overall accesses 1165system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102253 # mshr miss rate for overall accesses 1166system.cpu.l2cache.overall_mshr_miss_rate::total 0.066206 # mshr miss rate for overall accesses 1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average ReadReq mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average ReadReq mshr miss latency 1169system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57436.412285 # average ReadReq mshr miss latency 1170system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55501.331362 # average ReadReq mshr miss latency 1171system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56156.676219 # average ReadReq mshr miss latency 1172system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10246.615163 # average UpgradeReq mshr miss latency 1173system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10246.615163 # average UpgradeReq mshr miss latency 1174system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39402.802464 # average ReadExReq mshr miss latency 1175system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39402.802464 # average ReadExReq mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average overall mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average overall mshr miss latency 1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57436.412285 # average overall mshr miss latency 1179system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42883.926968 # average overall mshr miss latency 1180system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44215.108274 # average overall mshr miss latency 1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57436.412285 # average overall mshr miss latency 1184system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42883.926968 # average overall mshr miss latency 1185system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44215.108274 # average overall mshr miss latency | 1105system.cpu.l2cache.overall_mshr_misses::cpu.inst 16840 # number of overall MSHR misses 1106system.cpu.l2cache.overall_mshr_misses::cpu.data 169768 # number of overall MSHR misses 1107system.cpu.l2cache.overall_mshr_misses::total 186663 # number of overall MSHR misses 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5701045 # number of ReadReq MSHR miss cycles 1109system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles 1110system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 968087231 # number of ReadReq MSHR miss cycles 1111system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2080048452 # number of ReadReq MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3054150983 # number of ReadReq MSHR miss cycles 1113system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37901173 # number of UpgradeReq MSHR miss cycles 1114system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37901173 # number of UpgradeReq MSHR miss cycles 1115system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235111902 # number of ReadExReq MSHR miss cycles 1116system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235111902 # number of ReadExReq MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5701045 # number of demand (read+write) MSHR miss cycles 1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles 1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 968087231 # number of demand (read+write) MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7315160354 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.demand_mshr_miss_latency::total 8289262885 # number of demand (read+write) MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5701045 # number of overall MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles 1124system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 968087231 # number of overall MSHR miss cycles 1125system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7315160354 # number of overall MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::total 8289262885 # number of overall MSHR miss cycles 1127system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187415500 # number of ReadReq MSHR uncacheable cycles 1128system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187415500 # number of ReadReq MSHR uncacheable cycles 1129system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308505000 # number of WriteReq MSHR uncacheable cycles 1130system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308505000 # number of WriteReq MSHR uncacheable cycles 1131system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495920500 # number of overall MSHR uncacheable cycles 1132system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495920500 # number of overall MSHR uncacheable cycles 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for ReadReq accesses 1135system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for ReadReq accesses 1136system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026899 # mshr miss rate for ReadReq accesses 1137system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021275 # mshr miss rate for ReadReq accesses 1138system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.914562 # mshr miss rate for UpgradeReq accesses 1139system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.914562 # mshr miss rate for UpgradeReq accesses 1140system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459834 # mshr miss rate for ReadExReq accesses 1141system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459834 # mshr miss rate for ReadExReq accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for demand accesses 1145system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for demand accesses 1146system.cpu.l2cache.demand_mshr_miss_rate::total 0.066271 # mshr miss rate for demand accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for overall accesses 1149system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for overall accesses 1150system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for overall accesses 1151system.cpu.l2cache.overall_mshr_miss_rate::total 0.066271 # mshr miss rate for overall accesses 1152system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average ReadReq mshr miss latency 1153system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency 1154system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57487.365261 # average ReadReq mshr miss latency 1155system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56400.446095 # average ReadReq mshr miss latency 1156system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56794.997359 # average ReadReq mshr miss latency 1157system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.976713 # average UpgradeReq mshr miss latency 1158system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.976713 # average UpgradeReq mshr miss latency 1159system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39394.918292 # average ReadExReq mshr miss latency 1160system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39394.918292 # average ReadExReq mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency 1163system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency 1164system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency 1165system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency 1169system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency 1170system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency |
| 1186system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1187system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1188system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1189system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1190system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1191system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1192system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1193system.cpu.kern.inst.arm 0 # number of arm instructions executed 1194system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1195 1196---------- End Simulation Statistics ---------- | 1171system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1172system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1173system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1174system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1175system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1176system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1177system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1178system.cpu.kern.inst.arm 0 # number of arm instructions executed 1179system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1180 1181---------- End Simulation Statistics ---------- |