| stats.txt (9449:56610ab73040) | stats.txt (9474:23c3e1c0e9e4) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.136797 # Number of seconds simulated 4sim_ticks 5136797077000 # Number of ticks simulated 5final_tick 5136797077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.136818 # Number of seconds simulated 4sim_ticks 5136817990000 # Number of ticks simulated 5final_tick 5136817990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 59794 # Simulator instruction rate (inst/s) 8host_op_rate 118197 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 752889080 # Simulator tick rate (ticks/s) 10host_mem_usage 765888 # Number of bytes of host memory used 11host_seconds 6822.78 # Real time elapsed on the host 12sim_insts 407963976 # Number of instructions simulated 13sim_ops 806432115 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2490112 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory | 7host_inst_rate 178524 # Simulator instruction rate (inst/s) 8host_op_rate 352888 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2247974016 # Simulator tick rate (ticks/s) 10host_mem_usage 798352 # Number of bytes of host memory used 11host_seconds 2285.09 # Real time elapsed on the host 12sim_insts 407944006 # Number of instructions simulated 13sim_ops 806380994 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2472512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 1077440 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10840448 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14411520 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1077440 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1077440 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9595008 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9595008 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38908 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 1073088 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10819392 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14368384 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1073088 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1073088 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9566592 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9566592 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38633 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.inst 16835 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 169382 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 225180 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149922 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149922 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 484760 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::cpu.inst 16767 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 169053 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 224506 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149478 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149478 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 481331 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 586 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.inst 209749 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2110352 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2805546 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 209749 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 209749 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1867897 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1867897 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1867897 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 484760 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) | 35system.physmem.bw_read::cpu.inst 208901 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2106244 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2797137 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 208901 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 208901 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1862358 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1862358 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1862358 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 481331 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 586 # Total bandwidth to/from this memory (bytes/s) |
| 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.inst 209749 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2110352 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4673443 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 225180 # Total number of read requests seen 50system.physmem.writeReqs 149922 # Total number of write requests seen 51system.physmem.cpureqs 389082 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14411520 # Total number of bytes read from memory 53system.physmem.bytesWritten 9595008 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14411520 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9595008 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 4150 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 13684 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 14849 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 12992 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 15044 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13538 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 14702 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13271 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 14556 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13423 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 14638 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13867 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 14842 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13112 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 14582 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 12817 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15188 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 8767 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 10396 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8323 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 10488 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8797 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 10117 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8482 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 9956 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8780 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 9930 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 9138 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 10179 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8298 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 9881 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8122 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 10268 # Track writes on a per bank basis | 46system.physmem.bw_total::cpu.inst 208901 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2106244 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4659495 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 224506 # Total number of read requests seen 50system.physmem.writeReqs 149478 # Total number of write requests seen 51system.physmem.cpureqs 388421 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14368384 # Total number of bytes read from memory 53system.physmem.bytesWritten 9566592 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14368384 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9566592 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 103 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 4169 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 13472 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 14748 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 12720 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 14632 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13467 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 14703 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13182 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 14524 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13510 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 15204 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 14041 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 14883 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13300 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 14411 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 12663 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 14943 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 8673 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8057 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 10082 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8656 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 10024 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8415 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 9887 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8846 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 10505 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 9296 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 10166 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8640 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 9822 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8034 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 10163 # Track writes on a per bank basis |
| 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 91system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5136797025000 # Total gap between requests | 91system.physmem.numWrRetry 164 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5136817938000 # Total gap between requests |
| 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes | 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 99system.physmem.readPktSize::6 225180 # Categorize read packet sizes | 99system.physmem.readPktSize::6 224506 # Categorize read packet sizes |
| 100system.physmem.readPktSize::7 0 # Categorize read packet sizes 101system.physmem.readPktSize::8 0 # Categorize read packet sizes 102system.physmem.writePktSize::0 0 # categorize write packet sizes 103system.physmem.writePktSize::1 0 # categorize write packet sizes 104system.physmem.writePktSize::2 0 # categorize write packet sizes 105system.physmem.writePktSize::3 0 # categorize write packet sizes 106system.physmem.writePktSize::4 0 # categorize write packet sizes 107system.physmem.writePktSize::5 0 # categorize write packet sizes | 100system.physmem.readPktSize::7 0 # Categorize read packet sizes 101system.physmem.readPktSize::8 0 # Categorize read packet sizes 102system.physmem.writePktSize::0 0 # categorize write packet sizes 103system.physmem.writePktSize::1 0 # categorize write packet sizes 104system.physmem.writePktSize::2 0 # categorize write packet sizes 105system.physmem.writePktSize::3 0 # categorize write packet sizes 106system.physmem.writePktSize::4 0 # categorize write packet sizes 107system.physmem.writePktSize::5 0 # categorize write packet sizes |
| 108system.physmem.writePktSize::6 149922 # categorize write packet sizes | 108system.physmem.writePktSize::6 149642 # categorize write packet sizes |
| 109system.physmem.writePktSize::7 0 # categorize write packet sizes 110system.physmem.writePktSize::8 0 # categorize write packet sizes 111system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 112system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 113system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::5 0 # categorize neither packet sizes | 109system.physmem.writePktSize::7 0 # categorize write packet sizes 110system.physmem.writePktSize::8 0 # categorize write packet sizes 111system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 112system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 113system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::5 0 # categorize neither packet sizes |
| 117system.physmem.neitherpktsize::6 4150 # categorize neither packet sizes | 117system.physmem.neitherpktsize::6 4169 # categorize neither packet sizes |
| 118system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 118system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 120system.physmem.rdQLenPdf::0 176541 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::1 21572 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::2 8228 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::3 2861 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::4 2837 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::5 2184 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::6 1343 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::7 1492 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::8 1352 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::9 1282 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::10 1193 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::11 1108 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::14 445 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::15 257 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see | 120system.physmem.rdQLenPdf::0 176041 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::1 21421 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::2 8452 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::3 2850 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::4 2802 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::5 2098 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::6 1307 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::7 1461 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::9 1298 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::10 1186 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::11 1137 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::12 1093 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::13 856 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::14 418 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::15 228 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::16 159 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::17 108 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| 144system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see | 144system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see |
| 153system.physmem.wrQLenPdf::0 5678 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::1 6373 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::2 6463 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::3 6497 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::4 6506 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::5 6513 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::6 6514 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::7 6514 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::8 6516 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::9 6518 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::10 6518 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::11 6518 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::12 6518 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::13 6518 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::14 6518 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::15 6518 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::16 6518 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::17 6518 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::18 6518 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::19 6518 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::20 6518 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::21 6518 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::22 6518 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::23 841 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::24 146 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::25 56 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see | 153system.physmem.wrQLenPdf::0 5671 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::1 6355 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::2 6462 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::3 6480 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::4 6488 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::5 6495 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::6 6496 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::7 6497 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::8 6498 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::23 829 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::24 144 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see |
| 185system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 185system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 186system.physmem.totQLat 3390959114 # Total cycles spent in queuing delays 187system.physmem.totMemAccLat 7646017114 # Sum of mem lat for all requests 188system.physmem.totBusLat 900420000 # Total cycles spent in databus access 189system.physmem.totBankLat 3354638000 # Total cycles spent in bank access 190system.physmem.avgQLat 15063.90 # Average queueing delay per request 191system.physmem.avgBankLat 14902.55 # Average bank access latency per request | 186system.physmem.totQLat 3338682949 # Total cycles spent in queuing delays 187system.physmem.totMemAccLat 7589868949 # Sum of mem lat for all requests 188system.physmem.totBusLat 897612000 # Total cycles spent in databus access 189system.physmem.totBankLat 3353574000 # Total cycles spent in bank access 190system.physmem.avgQLat 14878.07 # Average queueing delay per request 191system.physmem.avgBankLat 14944.43 # Average bank access latency per request |
| 192system.physmem.avgBusLat 4000.00 # Average bus latency per request | 192system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 193system.physmem.avgMemAccLat 33966.45 # Average memory access latency 194system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s 195system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s 196system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s 197system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s | 193system.physmem.avgMemAccLat 33822.49 # Average memory access latency 194system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s 195system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s 196system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s 197system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s |
| 198system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 199system.physmem.busUtil 0.03 # Data bus utilization in percentage 200system.physmem.avgRdQLen 0.00 # Average read queue length over time | 198system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 199system.physmem.busUtil 0.03 # Data bus utilization in percentage 200system.physmem.avgRdQLen 0.00 # Average read queue length over time |
| 201system.physmem.avgWrQLen 11.93 # Average write queue length over time 202system.physmem.readRowHits 198524 # Number of row buffer hits during reads 203system.physmem.writeRowHits 88099 # Number of row buffer hits during writes 204system.physmem.readRowHitRate 88.19 # Row buffer hit rate for reads 205system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes 206system.physmem.avgGap 13694400.52 # Average gap between requests 207system.iocache.replacements 47577 # number of replacements 208system.iocache.tagsinuse 0.116411 # Cycle average of tags in use | 201system.physmem.avgWrQLen 11.19 # Average write queue length over time 202system.physmem.readRowHits 197567 # Number of row buffer hits during reads 203system.physmem.writeRowHits 87961 # Number of row buffer hits during writes 204system.physmem.readRowHitRate 88.04 # Row buffer hit rate for reads 205system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes 206system.physmem.avgGap 13735394.93 # Average gap between requests 207system.iocache.replacements 47579 # number of replacements 208system.iocache.tagsinuse 0.116428 # Cycle average of tags in use |
| 209system.iocache.total_refs 0 # Total number of references to valid blocks. | 209system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 210system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. | 210system.iocache.sampled_refs 47595 # Sample count of references to valid blocks. |
| 211system.iocache.avg_refs 0 # Average number of references to valid blocks. | 211system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 212system.iocache.warmup_cycle 4991829125000 # Cycle when the warmup percentage was hit. 213system.iocache.occ_blocks::pc.south_bridge.ide 0.116411 # Average occupied blocks per requestor 214system.iocache.occ_percent::pc.south_bridge.ide 0.007276 # Average percentage of cache occupancy 215system.iocache.occ_percent::total 0.007276 # Average percentage of cache occupancy 216system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses 217system.iocache.ReadReq_misses::total 912 # number of ReadReq misses | 212system.iocache.warmup_cycle 4991841370000 # Cycle when the warmup percentage was hit. 213system.iocache.occ_blocks::pc.south_bridge.ide 0.116428 # Average occupied blocks per requestor 214system.iocache.occ_percent::pc.south_bridge.ide 0.007277 # Average percentage of cache occupancy 215system.iocache.occ_percent::total 0.007277 # Average percentage of cache occupancy 216system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses 217system.iocache.ReadReq_misses::total 914 # number of ReadReq misses |
| 218system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 219system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses | 218system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 219system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses |
| 220system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses 221system.iocache.demand_misses::total 47632 # number of demand (read+write) misses 222system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses 223system.iocache.overall_misses::total 47632 # number of overall misses 224system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146446932 # number of ReadReq miss cycles 225system.iocache.ReadReq_miss_latency::total 146446932 # number of ReadReq miss cycles 226system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9011912160 # number of WriteReq miss cycles 227system.iocache.WriteReq_miss_latency::total 9011912160 # number of WriteReq miss cycles 228system.iocache.demand_miss_latency::pc.south_bridge.ide 9158359092 # number of demand (read+write) miss cycles 229system.iocache.demand_miss_latency::total 9158359092 # number of demand (read+write) miss cycles 230system.iocache.overall_miss_latency::pc.south_bridge.ide 9158359092 # number of overall miss cycles 231system.iocache.overall_miss_latency::total 9158359092 # number of overall miss cycles 232system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) 233system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) | 220system.iocache.demand_misses::pc.south_bridge.ide 47634 # number of demand (read+write) misses 221system.iocache.demand_misses::total 47634 # number of demand (read+write) misses 222system.iocache.overall_misses::pc.south_bridge.ide 47634 # number of overall misses 223system.iocache.overall_misses::total 47634 # number of overall misses 224system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143641932 # number of ReadReq miss cycles 225system.iocache.ReadReq_miss_latency::total 143641932 # number of ReadReq miss cycles 226system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8950549160 # number of WriteReq miss cycles 227system.iocache.WriteReq_miss_latency::total 8950549160 # number of WriteReq miss cycles 228system.iocache.demand_miss_latency::pc.south_bridge.ide 9094191092 # number of demand (read+write) miss cycles 229system.iocache.demand_miss_latency::total 9094191092 # number of demand (read+write) miss cycles 230system.iocache.overall_miss_latency::pc.south_bridge.ide 9094191092 # number of overall miss cycles 231system.iocache.overall_miss_latency::total 9094191092 # number of overall miss cycles 232system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) 233system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) |
| 234system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 235system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) | 234system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 235system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) |
| 236system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses 237system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses 238system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses 239system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses | 236system.iocache.demand_accesses::pc.south_bridge.ide 47634 # number of demand (read+write) accesses 237system.iocache.demand_accesses::total 47634 # number of demand (read+write) accesses 238system.iocache.overall_accesses::pc.south_bridge.ide 47634 # number of overall (read+write) accesses 239system.iocache.overall_accesses::total 47634 # number of overall (read+write) accesses |
| 240system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 241system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 242system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 243system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 244system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 245system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 246system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 247system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 240system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 241system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 242system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 243system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 244system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 245system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 246system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 247system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 248system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160577.776316 # average ReadReq miss latency 249system.iocache.ReadReq_avg_miss_latency::total 160577.776316 # average ReadReq miss latency 250system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192891.955479 # average WriteReq miss latency 251system.iocache.WriteReq_avg_miss_latency::total 192891.955479 # average WriteReq miss latency 252system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency 253system.iocache.demand_avg_miss_latency::total 192273.242610 # average overall miss latency 254system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency 255system.iocache.overall_avg_miss_latency::total 192273.242610 # average overall miss latency 256system.iocache.blocked_cycles::no_mshrs 57584 # number of cycles access was blocked | 248system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157157.474836 # average ReadReq miss latency 249system.iocache.ReadReq_avg_miss_latency::total 157157.474836 # average ReadReq miss latency 250system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191578.535103 # average WriteReq miss latency 251system.iocache.WriteReq_avg_miss_latency::total 191578.535103 # average WriteReq miss latency 252system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 190918.064660 # average overall miss latency 253system.iocache.demand_avg_miss_latency::total 190918.064660 # average overall miss latency 254system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 190918.064660 # average overall miss latency 255system.iocache.overall_avg_miss_latency::total 190918.064660 # average overall miss latency 256system.iocache.blocked_cycles::no_mshrs 54662 # number of cycles access was blocked |
| 257system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 257system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 258system.iocache.blocked::no_mshrs 7533 # number of cycles access was blocked | 258system.iocache.blocked::no_mshrs 7510 # number of cycles access was blocked |
| 259system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 259system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 260system.iocache.avg_blocked_cycles::no_mshrs 7.644232 # average number of cycles each access was blocked | 260system.iocache.avg_blocked_cycles::no_mshrs 7.278562 # average number of cycles each access was blocked |
| 261system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 262system.iocache.fast_writes 0 # number of fast writes performed 263system.iocache.cache_copies 0 # number of cache copies performed 264system.iocache.writebacks::writebacks 46667 # number of writebacks 265system.iocache.writebacks::total 46667 # number of writebacks | 261system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 262system.iocache.fast_writes 0 # number of fast writes performed 263system.iocache.cache_copies 0 # number of cache copies performed 264system.iocache.writebacks::writebacks 46667 # number of writebacks 265system.iocache.writebacks::total 46667 # number of writebacks |
| 266system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses 267system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses | 266system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses 267system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses |
| 268system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 269system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses | 268system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 269system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses |
| 270system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses 271system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses 272system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses 273system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses 274system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98991992 # number of ReadReq MSHR miss cycles 275system.iocache.ReadReq_mshr_miss_latency::total 98991992 # number of ReadReq MSHR miss cycles 276system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6580127962 # number of WriteReq MSHR miss cycles 277system.iocache.WriteReq_mshr_miss_latency::total 6580127962 # number of WriteReq MSHR miss cycles 278system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of demand (read+write) MSHR miss cycles 279system.iocache.demand_mshr_miss_latency::total 6679119954 # number of demand (read+write) MSHR miss cycles 280system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of overall MSHR miss cycles 281system.iocache.overall_mshr_miss_latency::total 6679119954 # number of overall MSHR miss cycles | 270system.iocache.demand_mshr_misses::pc.south_bridge.ide 47634 # number of demand (read+write) MSHR misses 271system.iocache.demand_mshr_misses::total 47634 # number of demand (read+write) MSHR misses 272system.iocache.overall_mshr_misses::pc.south_bridge.ide 47634 # number of overall MSHR misses 273system.iocache.overall_mshr_misses::total 47634 # number of overall MSHR misses 274system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96083990 # number of ReadReq MSHR miss cycles 275system.iocache.ReadReq_mshr_miss_latency::total 96083990 # number of ReadReq MSHR miss cycles 276system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6518807893 # number of WriteReq MSHR miss cycles 277system.iocache.WriteReq_mshr_miss_latency::total 6518807893 # number of WriteReq MSHR miss cycles 278system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6614891883 # number of demand (read+write) MSHR miss cycles 279system.iocache.demand_mshr_miss_latency::total 6614891883 # number of demand (read+write) MSHR miss cycles 280system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6614891883 # number of overall MSHR miss cycles 281system.iocache.overall_mshr_miss_latency::total 6614891883 # number of overall MSHR miss cycles |
| 282system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 283system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 284system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 285system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 286system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 287system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 288system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 289system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 282system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 283system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 284system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 285system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 286system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 287system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 288system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 289system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 290system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108543.850877 # average ReadReq mshr miss latency 291system.iocache.ReadReq_avg_mshr_miss_latency::total 108543.850877 # average ReadReq mshr miss latency 292system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140841.780009 # average WriteReq mshr miss latency 293system.iocache.WriteReq_avg_mshr_miss_latency::total 140841.780009 # average WriteReq mshr miss latency 294system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency 295system.iocache.demand_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency 296system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency 297system.iocache.overall_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency | 290system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105124.715536 # average ReadReq mshr miss latency 291system.iocache.ReadReq_avg_mshr_miss_latency::total 105124.715536 # average ReadReq mshr miss latency 292system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139529.278532 # average WriteReq mshr miss latency 293system.iocache.WriteReq_avg_mshr_miss_latency::total 139529.278532 # average WriteReq mshr miss latency 294system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 138869.124638 # average overall mshr miss latency 295system.iocache.demand_avg_mshr_miss_latency::total 138869.124638 # average overall mshr miss latency 296system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 138869.124638 # average overall mshr miss latency 297system.iocache.overall_avg_mshr_miss_latency::total 138869.124638 # average overall mshr miss latency |
| 298system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 299system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 300system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). | 298system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 299system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 300system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |
| 301system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). | 301system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). |
| 302system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 303system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 304system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 305system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 306system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 307system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 308system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 309system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 310system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 302system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 303system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 304system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 305system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 306system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 307system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 308system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 309system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 310system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 311system.cpu.numCycles 447871414 # number of cpu cycles simulated | 311system.cpu.numCycles 447901761 # number of cpu cycles simulated |
| 312system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 313system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 312system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 313system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 314system.cpu.BPredUnit.lookups 86248524 # Number of BP lookups 315system.cpu.BPredUnit.condPredicted 86248524 # Number of conditional branches predicted 316system.cpu.BPredUnit.condIncorrect 1109719 # Number of conditional branches incorrect 317system.cpu.BPredUnit.BTBLookups 81324372 # Number of BTB lookups 318system.cpu.BPredUnit.BTBHits 79248318 # Number of BTB hits | 314system.cpu.BPredUnit.lookups 86252881 # Number of BP lookups 315system.cpu.BPredUnit.condPredicted 86252881 # Number of conditional branches predicted 316system.cpu.BPredUnit.condIncorrect 1115345 # Number of conditional branches incorrect 317system.cpu.BPredUnit.BTBLookups 81384938 # Number of BTB lookups 318system.cpu.BPredUnit.BTBHits 79240101 # Number of BTB hits |
| 319system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 320system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 321system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. | 319system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 320system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 321system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 322system.cpu.fetch.icacheStallCycles 27555812 # Number of cycles fetch is stalled on an Icache miss 323system.cpu.fetch.Insts 426098303 # Number of instructions fetch has processed 324system.cpu.fetch.Branches 86248524 # Number of branches that fetch encountered 325system.cpu.fetch.predictedBranches 79248318 # Number of branches that fetch has predicted taken 326system.cpu.fetch.Cycles 163629889 # Number of cycles fetch has run and was not squashing or blocked 327system.cpu.fetch.SquashCycles 4731856 # Number of cycles fetch has spent squashing 328system.cpu.fetch.TlbCycles 116400 # Number of cycles fetch has spent waiting for tlb 329system.cpu.fetch.BlockedCycles 62921622 # Number of cycles fetch has spent blocked 330system.cpu.fetch.MiscStallCycles 35870 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 331system.cpu.fetch.PendingTrapStallCycles 52533 # Number of stall cycles due to pending traps 332system.cpu.fetch.IcacheWaitRetryStallCycles 368 # Number of stall cycles due to full MSHR 333system.cpu.fetch.CacheLines 9034264 # Number of cache lines fetched 334system.cpu.fetch.IcacheSquashes 488269 # Number of outstanding Icache misses that were squashed 335system.cpu.fetch.ItlbSquashes 3183 # Number of outstanding ITLB misses that were squashed 336system.cpu.fetch.rateDist::samples 257896503 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::mean 3.261731 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::stdev 3.418044 # Number of instructions fetched each cycle (Total) | 322system.cpu.fetch.icacheStallCycles 27570299 # Number of cycles fetch is stalled on an Icache miss 323system.cpu.fetch.Insts 426189548 # Number of instructions fetch has processed 324system.cpu.fetch.Branches 86252881 # Number of branches that fetch encountered 325system.cpu.fetch.predictedBranches 79240101 # Number of branches that fetch has predicted taken 326system.cpu.fetch.Cycles 163642808 # Number of cycles fetch has run and was not squashing or blocked 327system.cpu.fetch.SquashCycles 4755358 # Number of cycles fetch has spent squashing 328system.cpu.fetch.TlbCycles 112288 # Number of cycles fetch has spent waiting for tlb 329system.cpu.fetch.BlockedCycles 62866127 # Number of cycles fetch has spent blocked 330system.cpu.fetch.MiscStallCycles 37152 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 331system.cpu.fetch.PendingTrapStallCycles 52962 # Number of stall cycles due to pending traps 332system.cpu.fetch.IcacheWaitRetryStallCycles 398 # Number of stall cycles due to full MSHR 333system.cpu.fetch.CacheLines 9042653 # Number of cache lines fetched 334system.cpu.fetch.IcacheSquashes 488997 # Number of outstanding Icache misses that were squashed 335system.cpu.fetch.ItlbSquashes 3194 # Number of outstanding ITLB misses that were squashed 336system.cpu.fetch.rateDist::samples 257883656 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::mean 3.262433 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::stdev 3.418145 # Number of instructions fetched each cycle (Total) |
| 339system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 339system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 340system.cpu.fetch.rateDist::0 94692515 36.72% 36.72% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::1 1566812 0.61% 37.32% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::2 71928839 27.89% 65.22% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::3 936780 0.36% 65.58% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::4 1600320 0.62% 66.20% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::5 2427387 0.94% 67.14% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::6 1078261 0.42% 67.56% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::7 1378215 0.53% 68.09% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::8 82287374 31.91% 100.00% # Number of instructions fetched each cycle (Total) | 340system.cpu.fetch.rateDist::0 94667319 36.71% 36.71% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::1 1563412 0.61% 37.32% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::2 71921029 27.89% 65.20% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::3 936098 0.36% 65.57% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::4 1601572 0.62% 66.19% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::5 2435088 0.94% 67.13% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::6 1080780 0.42% 67.55% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::7 1378788 0.53% 68.09% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::8 82299570 31.91% 100.00% # Number of instructions fetched each cycle (Total) |
| 349system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 349system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 352system.cpu.fetch.rateDist::total 257896503 # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.branchRate 0.192574 # Number of branch fetches per cycle 354system.cpu.fetch.rate 0.951385 # Number of inst fetches per cycle 355system.cpu.decode.IdleCycles 31239529 # Number of cycles decode is idle 356system.cpu.decode.BlockedCycles 60388203 # Number of cycles decode is blocked 357system.cpu.decode.RunCycles 159435692 # Number of cycles decode is running 358system.cpu.decode.UnblockCycles 3249070 # Number of cycles decode is unblocking 359system.cpu.decode.SquashCycles 3584009 # Number of cycles decode is squashing 360system.cpu.decode.DecodedInsts 838053376 # Number of instructions handled by decode 361system.cpu.decode.SquashedInsts 983 # Number of squashed instructions handled by decode 362system.cpu.rename.SquashCycles 3584009 # Number of cycles rename is squashing 363system.cpu.rename.IdleCycles 33976924 # Number of cycles rename is idle 364system.cpu.rename.BlockCycles 37367105 # Number of cycles rename is blocking 365system.cpu.rename.serializeStallCycles 10941861 # count of cycles rename stalled for serializing inst 366system.cpu.rename.RunCycles 159620502 # Number of cycles rename is running 367system.cpu.rename.UnblockCycles 12406102 # Number of cycles rename is unblocking 368system.cpu.rename.RenamedInsts 834408692 # Number of instructions processed by rename 369system.cpu.rename.ROBFullEvents 19434 # Number of times rename has blocked due to ROB full 370system.cpu.rename.IQFullEvents 5810292 # Number of times rename has blocked due to IQ full 371system.cpu.rename.LSQFullEvents 4754441 # Number of times rename has blocked due to LSQ full 372system.cpu.rename.FullRegisterEvents 7847 # Number of times there has been no free registers 373system.cpu.rename.RenamedOperands 995994396 # Number of destination operands rename has renamed 374system.cpu.rename.RenameLookups 1811420133 # Number of register rename lookups that rename has made 375system.cpu.rename.int_rename_lookups 1811419405 # Number of integer rename lookups 376system.cpu.rename.fp_rename_lookups 728 # Number of floating rename lookups 377system.cpu.rename.CommittedMaps 964426992 # Number of HB maps that are committed 378system.cpu.rename.UndoneMaps 31567397 # Number of HB maps that are undone due to squashing 379system.cpu.rename.serializingInsts 458567 # count of serializing insts renamed 380system.cpu.rename.tempSerializingInsts 466421 # count of temporary serializing insts renamed 381system.cpu.rename.skidInsts 28739056 # count of insts added to the skid buffer 382system.cpu.memDep0.insertedLoads 17094362 # Number of loads inserted to the mem dependence unit. 383system.cpu.memDep0.insertedStores 10134243 # Number of stores inserted to the mem dependence unit. 384system.cpu.memDep0.conflictingLoads 1234841 # Number of conflicting loads. 385system.cpu.memDep0.conflictingStores 965780 # Number of conflicting stores. 386system.cpu.iq.iqInstsAdded 828292865 # Number of instructions added to the IQ (excludes non-spec) 387system.cpu.iq.iqNonSpecInstsAdded 1249354 # Number of non-speculative instructions added to the IQ 388system.cpu.iq.iqInstsIssued 823298492 # Number of instructions issued 389system.cpu.iq.iqSquashedInstsIssued 149694 # Number of squashed instructions issued 390system.cpu.iq.iqSquashedInstsExamined 22192286 # Number of squashed instructions iterated over during squash; mainly for profiling 391system.cpu.iq.iqSquashedOperandsExamined 33736795 # Number of squashed operands that are examined and possibly removed from graph 392system.cpu.iq.iqSquashedNonSpecRemoved 196434 # Number of squashed non-spec instructions that were removed 393system.cpu.iq.issued_per_cycle::samples 257896503 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::mean 3.192360 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::stdev 2.384089 # Number of insts issued each cycle | 352system.cpu.fetch.rateDist::total 257883656 # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.branchRate 0.192571 # Number of branch fetches per cycle 354system.cpu.fetch.rate 0.951525 # Number of inst fetches per cycle 355system.cpu.decode.IdleCycles 31254353 # Number of cycles decode is idle 356system.cpu.decode.BlockedCycles 60335803 # Number of cycles decode is blocked 357system.cpu.decode.RunCycles 159451505 # Number of cycles decode is running 358system.cpu.decode.UnblockCycles 3240373 # Number of cycles decode is unblocking 359system.cpu.decode.SquashCycles 3601622 # Number of cycles decode is squashing 360system.cpu.decode.DecodedInsts 838158125 # Number of instructions handled by decode 361system.cpu.decode.SquashedInsts 957 # Number of squashed instructions handled by decode 362system.cpu.rename.SquashCycles 3601622 # Number of cycles rename is squashing 363system.cpu.rename.IdleCycles 34003643 # Number of cycles rename is idle 364system.cpu.rename.BlockCycles 37352024 # Number of cycles rename is blocking 365system.cpu.rename.serializeStallCycles 10890553 # count of cycles rename stalled for serializing inst 366system.cpu.rename.RunCycles 159616474 # Number of cycles rename is running 367system.cpu.rename.UnblockCycles 12419340 # Number of cycles rename is unblocking 368system.cpu.rename.RenamedInsts 834485567 # Number of instructions processed by rename 369system.cpu.rename.ROBFullEvents 19816 # Number of times rename has blocked due to ROB full 370system.cpu.rename.IQFullEvents 5811427 # Number of times rename has blocked due to IQ full 371system.cpu.rename.LSQFullEvents 4758263 # Number of times rename has blocked due to LSQ full 372system.cpu.rename.FullRegisterEvents 7797 # Number of times there has been no free registers 373system.cpu.rename.RenamedOperands 996045264 # Number of destination operands rename has renamed 374system.cpu.rename.RenameLookups 1811616758 # Number of register rename lookups that rename has made 375system.cpu.rename.int_rename_lookups 1811616222 # Number of integer rename lookups 376system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups 377system.cpu.rename.CommittedMaps 964358369 # Number of HB maps that are committed 378system.cpu.rename.UndoneMaps 31686888 # Number of HB maps that are undone due to squashing 379system.cpu.rename.serializingInsts 460019 # count of serializing insts renamed 380system.cpu.rename.tempSerializingInsts 467360 # count of temporary serializing insts renamed 381system.cpu.rename.skidInsts 28800044 # count of insts added to the skid buffer 382system.cpu.memDep0.insertedLoads 17105540 # Number of loads inserted to the mem dependence unit. 383system.cpu.memDep0.insertedStores 10151316 # Number of stores inserted to the mem dependence unit. 384system.cpu.memDep0.conflictingLoads 1164746 # Number of conflicting loads. 385system.cpu.memDep0.conflictingStores 891886 # Number of conflicting stores. 386system.cpu.iq.iqInstsAdded 828333374 # Number of instructions added to the IQ (excludes non-spec) 387system.cpu.iq.iqNonSpecInstsAdded 1249979 # Number of non-speculative instructions added to the IQ 388system.cpu.iq.iqInstsIssued 823307593 # Number of instructions issued 389system.cpu.iq.iqSquashedInstsIssued 149787 # Number of squashed instructions issued 390system.cpu.iq.iqSquashedInstsExamined 22280168 # Number of squashed instructions iterated over during squash; mainly for profiling 391system.cpu.iq.iqSquashedOperandsExamined 33846252 # Number of squashed operands that are examined and possibly removed from graph 392system.cpu.iq.iqSquashedNonSpecRemoved 197115 # Number of squashed non-spec instructions that were removed 393system.cpu.iq.issued_per_cycle::samples 257883656 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::mean 3.192554 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::stdev 2.383898 # Number of insts issued each cycle |
| 396system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 396system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 397system.cpu.iq.issued_per_cycle::0 71417814 27.69% 27.69% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::1 15473003 6.00% 33.69% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::2 10302554 3.99% 37.69% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::3 7467952 2.90% 40.58% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::4 75909427 29.43% 70.02% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::5 3864522 1.50% 71.52% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::6 72522780 28.12% 99.64% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::7 788081 0.31% 99.94% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::8 150370 0.06% 100.00% # Number of insts issued each cycle | 397system.cpu.iq.issued_per_cycle::0 71395205 27.69% 27.69% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::1 15462696 6.00% 33.68% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::2 10317630 4.00% 37.68% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::3 7483312 2.90% 40.58% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::4 75909298 29.44% 70.02% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::5 3861835 1.50% 71.52% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::6 72513968 28.12% 99.64% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::7 788170 0.31% 99.94% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::8 151542 0.06% 100.00% # Number of insts issued each cycle |
| 406system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 406system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 409system.cpu.iq.issued_per_cycle::total 257896503 # Number of insts issued each cycle | 409system.cpu.iq.issued_per_cycle::total 257883656 # Number of insts issued each cycle |
| 410system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 410system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 411system.cpu.iq.fu_full::IntAlu 363959 34.09% 34.09% # attempts to use FU when none available 412system.cpu.iq.fu_full::IntMult 0 0.00% 34.09% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntDiv 0 0.00% 34.09% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.09% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.09% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.09% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatMult 0 0.00% 34.09% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.09% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.09% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.09% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.09% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.09% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.09% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.09% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.09% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMult 0 0.00% 34.09% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.09% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdShift 0 0.00% 34.09% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.09% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.09% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.09% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.09% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.09% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.09% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.09% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.09% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.09% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.09% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.09% # attempts to use FU when none available 440system.cpu.iq.fu_full::MemRead 552647 51.76% 85.85% # attempts to use FU when none available 441system.cpu.iq.fu_full::MemWrite 151055 14.15% 100.00% # attempts to use FU when none available | 411system.cpu.iq.fu_full::IntAlu 365240 34.17% 34.17% # attempts to use FU when none available 412system.cpu.iq.fu_full::IntMult 0 0.00% 34.17% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntDiv 0 0.00% 34.17% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.17% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.17% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.17% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatMult 0 0.00% 34.17% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.17% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.17% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.17% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.17% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.17% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.17% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.17% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.17% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMult 0 0.00% 34.17% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.17% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdShift 0 0.00% 34.17% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.17% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.17% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.17% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.17% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.17% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.17% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.17% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.17% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.17% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.17% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.17% # attempts to use FU when none available 440system.cpu.iq.fu_full::MemRead 553441 51.78% 85.95% # attempts to use FU when none available 441system.cpu.iq.fu_full::MemWrite 150145 14.05% 100.00% # attempts to use FU when none available |
| 442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 444system.cpu.iq.FU_type_0::No_OpClass 310624 0.04% 0.04% # Type of FU issued 445system.cpu.iq.FU_type_0::IntAlu 795733525 96.65% 96.69% # Type of FU issued | 444system.cpu.iq.FU_type_0::No_OpClass 311438 0.04% 0.04% # Type of FU issued 445system.cpu.iq.FU_type_0::IntAlu 795721586 96.65% 96.69% # Type of FU issued |
| 446system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued 447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 466system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued | 446system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued 447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 466system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued |
| 474system.cpu.iq.FU_type_0::MemRead 17867181 2.17% 98.86% # Type of FU issued 475system.cpu.iq.FU_type_0::MemWrite 9387162 1.14% 100.00% # Type of FU issued | 474system.cpu.iq.FU_type_0::MemRead 17876340 2.17% 98.86% # Type of FU issued 475system.cpu.iq.FU_type_0::MemWrite 9398229 1.14% 100.00% # Type of FU issued |
| 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 478system.cpu.iq.FU_type_0::total 823298492 # Type of FU issued 479system.cpu.iq.rate 1.838247 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 1067661 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) 482system.cpu.iq.int_inst_queue_reads 1905840686 # Number of integer instruction queue reads 483system.cpu.iq.int_inst_queue_writes 851744345 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 818819585 # Number of integer instruction queue wakeup accesses 485system.cpu.iq.fp_inst_queue_reads 303 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 346 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses 488system.cpu.iq.int_alu_accesses 824055392 # Number of integer alu accesses 489system.cpu.iq.fp_alu_accesses 137 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 1644579 # Number of loads that had data forwarded from stores | 478system.cpu.iq.FU_type_0::total 823307593 # Type of FU issued 479system.cpu.iq.rate 1.838143 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 1068826 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.001298 # FU busy rate (busy events/executed inst) 482system.cpu.iq.int_inst_queue_reads 1905849140 # Number of integer instruction queue reads 483system.cpu.iq.int_inst_queue_writes 851873423 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 818806890 # Number of integer instruction queue wakeup accesses 485system.cpu.iq.fp_inst_queue_reads 220 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses 488system.cpu.iq.int_alu_accesses 824064883 # Number of integer alu accesses 489system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 1642369 # Number of loads that had data forwarded from stores |
| 491system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 491system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 492system.cpu.iew.lsq.thread0.squashedLoads 3112367 # Number of loads squashed 493system.cpu.iew.lsq.thread0.ignoredResponses 23963 # Number of memory responses ignored because the instruction is squashed 494system.cpu.iew.lsq.thread0.memOrderViolation 11499 # Number of memory ordering violations 495system.cpu.iew.lsq.thread0.squashedStores 1716857 # Number of stores squashed | 492system.cpu.iew.lsq.thread0.squashedLoads 3123872 # Number of loads squashed 493system.cpu.iew.lsq.thread0.ignoredResponses 22910 # Number of memory responses ignored because the instruction is squashed 494system.cpu.iew.lsq.thread0.memOrderViolation 11412 # Number of memory ordering violations 495system.cpu.iew.lsq.thread0.squashedStores 1729878 # Number of stores squashed |
| 496system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 497system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 496system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 497system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 498system.cpu.iew.lsq.thread0.rescheduledLoads 1932401 # Number of loads that were rescheduled 499system.cpu.iew.lsq.thread0.cacheBlocked 11954 # Number of times an access to memory failed due to the cache being blocked | 498system.cpu.iew.lsq.thread0.rescheduledLoads 1932382 # Number of loads that were rescheduled 499system.cpu.iew.lsq.thread0.cacheBlocked 12176 # Number of times an access to memory failed due to the cache being blocked |
| 500system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 500system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 501system.cpu.iew.iewSquashCycles 3584009 # Number of cycles IEW is squashing 502system.cpu.iew.iewBlockCycles 26166561 # Number of cycles IEW is blocking 503system.cpu.iew.iewUnblockCycles 2112396 # Number of cycles IEW is unblocking 504system.cpu.iew.iewDispatchedInsts 829542219 # Number of instructions dispatched to IQ 505system.cpu.iew.iewDispSquashedInsts 307602 # Number of squashed instructions skipped by dispatch 506system.cpu.iew.iewDispLoadInsts 17094362 # Number of dispatched load instructions 507system.cpu.iew.iewDispStoreInsts 10134243 # Number of dispatched store instructions 508system.cpu.iew.iewDispNonSpecInsts 718774 # Number of dispatched non-speculative instructions 509system.cpu.iew.iewIQFullEvents 1614614 # Number of times the IQ has become full, causing a stall 510system.cpu.iew.iewLSQFullEvents 11947 # Number of times the LSQ has become full, causing a stall 511system.cpu.iew.memOrderViolationEvents 11499 # Number of memory order violations 512system.cpu.iew.predictedTakenIncorrect 653687 # Number of branches that were predicted taken incorrectly 513system.cpu.iew.predictedNotTakenIncorrect 591965 # Number of branches that were predicted not taken incorrectly 514system.cpu.iew.branchMispredicts 1245652 # Number of branch mispredicts detected at execute 515system.cpu.iew.iewExecutedInsts 821416518 # Number of executed instructions 516system.cpu.iew.iewExecLoadInsts 17449825 # Number of load instructions executed 517system.cpu.iew.iewExecSquashedInsts 1881973 # Number of squashed instructions skipped in execute | 501system.cpu.iew.iewSquashCycles 3601622 # Number of cycles IEW is squashing 502system.cpu.iew.iewBlockCycles 26144135 # Number of cycles IEW is blocking 503system.cpu.iew.iewUnblockCycles 2117005 # Number of cycles IEW is unblocking 504system.cpu.iew.iewDispatchedInsts 829583353 # Number of instructions dispatched to IQ 505system.cpu.iew.iewDispSquashedInsts 307079 # Number of squashed instructions skipped by dispatch 506system.cpu.iew.iewDispLoadInsts 17105540 # Number of dispatched load instructions 507system.cpu.iew.iewDispStoreInsts 10151316 # Number of dispatched store instructions 508system.cpu.iew.iewDispNonSpecInsts 719112 # Number of dispatched non-speculative instructions 509system.cpu.iew.iewIQFullEvents 1614713 # Number of times the IQ has become full, causing a stall 510system.cpu.iew.iewLSQFullEvents 12810 # Number of times the LSQ has become full, causing a stall 511system.cpu.iew.memOrderViolationEvents 11412 # Number of memory order violations 512system.cpu.iew.predictedTakenIncorrect 656230 # Number of branches that were predicted taken incorrectly 513system.cpu.iew.predictedNotTakenIncorrect 596856 # Number of branches that were predicted not taken incorrectly 514system.cpu.iew.branchMispredicts 1253086 # Number of branch mispredicts detected at execute 515system.cpu.iew.iewExecutedInsts 821409782 # Number of executed instructions 516system.cpu.iew.iewExecLoadInsts 17457108 # Number of load instructions executed 517system.cpu.iew.iewExecSquashedInsts 1897810 # Number of squashed instructions skipped in execute |
| 518system.cpu.iew.exec_swp 0 # number of swp insts executed 519system.cpu.iew.exec_nop 0 # number of nop insts executed | 518system.cpu.iew.exec_swp 0 # number of swp insts executed 519system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 520system.cpu.iew.exec_refs 26604955 # number of memory reference insts executed 521system.cpu.iew.exec_branches 83223788 # Number of branches executed 522system.cpu.iew.exec_stores 9155130 # Number of stores executed 523system.cpu.iew.exec_rate 1.834045 # Inst execution rate 524system.cpu.iew.wb_sent 820955265 # cumulative count of insts sent to commit 525system.cpu.iew.wb_count 818819659 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 639977790 # num instructions producing a value 527system.cpu.iew.wb_consumers 1045837145 # num instructions consuming a value | 520system.cpu.iew.exec_refs 26622226 # number of memory reference insts executed 521system.cpu.iew.exec_branches 83220659 # Number of branches executed 522system.cpu.iew.exec_stores 9165118 # Number of stores executed 523system.cpu.iew.exec_rate 1.833906 # Inst execution rate 524system.cpu.iew.wb_sent 820945177 # cumulative count of insts sent to commit 525system.cpu.iew.wb_count 818806944 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 639956313 # num instructions producing a value 527system.cpu.iew.wb_consumers 1045834424 # num instructions consuming a value |
| 528system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 528system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 529system.cpu.iew.wb_rate 1.828247 # insts written-back per cycle 530system.cpu.iew.wb_fanout 0.611929 # average fanout of values written-back | 529system.cpu.iew.wb_rate 1.828095 # insts written-back per cycle 530system.cpu.iew.wb_fanout 0.611910 # average fanout of values written-back |
| 531system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 531system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 532system.cpu.commit.commitSquashedInsts 23003299 # The number of squashed insts skipped by commit 533system.cpu.commit.commitNonSpecStalls 1052918 # The number of times commit has been forced to stall to communicate backwards 534system.cpu.commit.branchMispredicts 1114308 # The number of times a branch was mispredicted 535system.cpu.commit.committed_per_cycle::samples 254312494 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::mean 3.171028 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::stdev 2.854625 # Number of insts commited each cycle | 532system.cpu.commit.commitSquashedInsts 23092364 # The number of squashed insts skipped by commit 533system.cpu.commit.commitNonSpecStalls 1052862 # The number of times commit has been forced to stall to communicate backwards 534system.cpu.commit.branchMispredicts 1120067 # The number of times a branch was mispredicted 535system.cpu.commit.committed_per_cycle::samples 254282034 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::mean 3.171207 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::stdev 2.854640 # Number of insts commited each cycle |
| 538system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 538system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 539system.cpu.commit.committed_per_cycle::0 82565112 32.47% 32.47% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::1 11801317 4.64% 37.11% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::2 3875007 1.52% 38.63% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::3 74957575 29.47% 68.10% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::4 2434316 0.96% 69.06% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::5 1480794 0.58% 69.64% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::6 899910 0.35% 70.00% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::7 70920339 27.89% 97.89% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::8 5378124 2.11% 100.00% # Number of insts commited each cycle | 539system.cpu.commit.committed_per_cycle::0 82542979 32.46% 32.46% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::1 11813450 4.65% 37.11% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::2 3859102 1.52% 38.62% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::3 74953678 29.48% 68.10% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::4 2443754 0.96% 69.06% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::5 1483333 0.58% 69.65% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::6 886403 0.35% 69.99% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::7 70916473 27.89% 97.88% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::8 5382862 2.12% 100.00% # Number of insts commited each cycle |
| 548system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 548system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 551system.cpu.commit.committed_per_cycle::total 254312494 # Number of insts commited each cycle 552system.cpu.commit.committedInsts 407963976 # Number of instructions committed 553system.cpu.commit.committedOps 806432115 # Number of ops (including micro ops) committed | 551system.cpu.commit.committed_per_cycle::total 254282034 # Number of insts commited each cycle 552system.cpu.commit.committedInsts 407944006 # Number of instructions committed 553system.cpu.commit.committedOps 806380994 # Number of ops (including micro ops) committed |
| 554system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 554system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 555system.cpu.commit.refs 22399378 # Number of memory references committed 556system.cpu.commit.loads 13981992 # Number of loads committed 557system.cpu.commit.membars 473513 # Number of memory barriers committed 558system.cpu.commit.branches 82199908 # Number of branches committed | 555system.cpu.commit.refs 22403103 # Number of memory references committed 556system.cpu.commit.loads 13981665 # Number of loads committed 557system.cpu.commit.membars 473467 # Number of memory barriers committed 558system.cpu.commit.branches 82194070 # Number of branches committed |
| 559system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 559system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 560system.cpu.commit.int_insts 735371295 # Number of committed integer instructions. | 560system.cpu.commit.int_insts 735324556 # Number of committed integer instructions. |
| 561system.cpu.commit.function_calls 0 # Number of function calls committed. | 561system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 562system.cpu.commit.bw_lim_events 5378124 # number cycles where commit BW limit reached | 562system.cpu.commit.bw_lim_events 5382862 # number cycles where commit BW limit reached |
| 563system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 563system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 564system.cpu.rob.rob_reads 1078291467 # The number of ROB reads 565system.cpu.rob.rob_writes 1662473587 # The number of ROB writes 566system.cpu.timesIdled 1221266 # Number of times that the entire CPU went into an idle state and unscheduled itself 567system.cpu.idleCycles 189974911 # Total number of cycles that the CPU has spent unscheduled due to idling 568system.cpu.quiesceCycles 9825720160 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 569system.cpu.committedInsts 407963976 # Number of Instructions Simulated 570system.cpu.committedOps 806432115 # Number of Ops (including micro ops) Simulated 571system.cpu.committedInsts_total 407963976 # Number of Instructions Simulated 572system.cpu.cpi 1.097821 # CPI: Cycles Per Instruction 573system.cpu.cpi_total 1.097821 # CPI: Total CPI of All Threads 574system.cpu.ipc 0.910895 # IPC: Instructions Per Cycle 575system.cpu.ipc_total 0.910895 # IPC: Total IPC of All Threads 576system.cpu.int_regfile_reads 1507038080 # number of integer regfile reads 577system.cpu.int_regfile_writes 977032757 # number of integer regfile writes 578system.cpu.fp_regfile_reads 74 # number of floating regfile reads 579system.cpu.misc_regfile_reads 264726295 # number of misc regfile reads 580system.cpu.misc_regfile_writes 402502 # number of misc regfile writes 581system.cpu.icache.replacements 1052817 # number of replacements 582system.cpu.icache.tagsinuse 510.984184 # Cycle average of tags in use 583system.cpu.icache.total_refs 7916649 # Total number of references to valid blocks. 584system.cpu.icache.sampled_refs 1053329 # Sample count of references to valid blocks. 585system.cpu.icache.avg_refs 7.515837 # Average number of references to valid blocks. 586system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit. 587system.cpu.icache.occ_blocks::cpu.inst 510.984184 # Average occupied blocks per requestor 588system.cpu.icache.occ_percent::cpu.inst 0.998016 # Average percentage of cache occupancy 589system.cpu.icache.occ_percent::total 0.998016 # Average percentage of cache occupancy 590system.cpu.icache.ReadReq_hits::cpu.inst 7916649 # number of ReadReq hits 591system.cpu.icache.ReadReq_hits::total 7916649 # number of ReadReq hits 592system.cpu.icache.demand_hits::cpu.inst 7916649 # number of demand (read+write) hits 593system.cpu.icache.demand_hits::total 7916649 # number of demand (read+write) hits 594system.cpu.icache.overall_hits::cpu.inst 7916649 # number of overall hits 595system.cpu.icache.overall_hits::total 7916649 # number of overall hits 596system.cpu.icache.ReadReq_misses::cpu.inst 1117614 # number of ReadReq misses 597system.cpu.icache.ReadReq_misses::total 1117614 # number of ReadReq misses 598system.cpu.icache.demand_misses::cpu.inst 1117614 # number of demand (read+write) misses 599system.cpu.icache.demand_misses::total 1117614 # number of demand (read+write) misses 600system.cpu.icache.overall_misses::cpu.inst 1117614 # number of overall misses 601system.cpu.icache.overall_misses::total 1117614 # number of overall misses 602system.cpu.icache.ReadReq_miss_latency::cpu.inst 15123913488 # number of ReadReq miss cycles 603system.cpu.icache.ReadReq_miss_latency::total 15123913488 # number of ReadReq miss cycles 604system.cpu.icache.demand_miss_latency::cpu.inst 15123913488 # number of demand (read+write) miss cycles 605system.cpu.icache.demand_miss_latency::total 15123913488 # number of demand (read+write) miss cycles 606system.cpu.icache.overall_miss_latency::cpu.inst 15123913488 # number of overall miss cycles 607system.cpu.icache.overall_miss_latency::total 15123913488 # number of overall miss cycles 608system.cpu.icache.ReadReq_accesses::cpu.inst 9034263 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.ReadReq_accesses::total 9034263 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.demand_accesses::cpu.inst 9034263 # number of demand (read+write) accesses 611system.cpu.icache.demand_accesses::total 9034263 # number of demand (read+write) accesses 612system.cpu.icache.overall_accesses::cpu.inst 9034263 # number of overall (read+write) accesses 613system.cpu.icache.overall_accesses::total 9034263 # number of overall (read+write) accesses 614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123708 # miss rate for ReadReq accesses 615system.cpu.icache.ReadReq_miss_rate::total 0.123708 # miss rate for ReadReq accesses 616system.cpu.icache.demand_miss_rate::cpu.inst 0.123708 # miss rate for demand accesses 617system.cpu.icache.demand_miss_rate::total 0.123708 # miss rate for demand accesses 618system.cpu.icache.overall_miss_rate::cpu.inst 0.123708 # miss rate for overall accesses 619system.cpu.icache.overall_miss_rate::total 0.123708 # miss rate for overall accesses 620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13532.322866 # average ReadReq miss latency 621system.cpu.icache.ReadReq_avg_miss_latency::total 13532.322866 # average ReadReq miss latency 622system.cpu.icache.demand_avg_miss_latency::cpu.inst 13532.322866 # average overall miss latency 623system.cpu.icache.demand_avg_miss_latency::total 13532.322866 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::cpu.inst 13532.322866 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::total 13532.322866 # average overall miss latency 626system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked | 564system.cpu.rob.rob_reads 1078294199 # The number of ROB reads 565system.cpu.rob.rob_writes 1662567045 # The number of ROB writes 566system.cpu.timesIdled 1221565 # Number of times that the entire CPU went into an idle state and unscheduled itself 567system.cpu.idleCycles 190018105 # Total number of cycles that the CPU has spent unscheduled due to idling 568system.cpu.quiesceCycles 9825731637 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 569system.cpu.committedInsts 407944006 # Number of Instructions Simulated 570system.cpu.committedOps 806380994 # Number of Ops (including micro ops) Simulated 571system.cpu.committedInsts_total 407944006 # Number of Instructions Simulated 572system.cpu.cpi 1.097949 # CPI: Cycles Per Instruction 573system.cpu.cpi_total 1.097949 # CPI: Total CPI of All Threads 574system.cpu.ipc 0.910789 # IPC: Instructions Per Cycle 575system.cpu.ipc_total 0.910789 # IPC: Total IPC of All Threads 576system.cpu.int_regfile_reads 1507043995 # number of integer regfile reads 577system.cpu.int_regfile_writes 976998949 # number of integer regfile writes 578system.cpu.fp_regfile_reads 54 # number of floating regfile reads 579system.cpu.misc_regfile_reads 264734619 # number of misc regfile reads 580system.cpu.misc_regfile_writes 402509 # number of misc regfile writes 581system.cpu.icache.replacements 1054256 # number of replacements 582system.cpu.icache.tagsinuse 510.988943 # Cycle average of tags in use 583system.cpu.icache.total_refs 7923866 # Total number of references to valid blocks. 584system.cpu.icache.sampled_refs 1054768 # Sample count of references to valid blocks. 585system.cpu.icache.avg_refs 7.512425 # Average number of references to valid blocks. 586system.cpu.icache.warmup_cycle 56004276000 # Cycle when the warmup percentage was hit. 587system.cpu.icache.occ_blocks::cpu.inst 510.988943 # Average occupied blocks per requestor 588system.cpu.icache.occ_percent::cpu.inst 0.998025 # Average percentage of cache occupancy 589system.cpu.icache.occ_percent::total 0.998025 # Average percentage of cache occupancy 590system.cpu.icache.ReadReq_hits::cpu.inst 7923866 # number of ReadReq hits 591system.cpu.icache.ReadReq_hits::total 7923866 # number of ReadReq hits 592system.cpu.icache.demand_hits::cpu.inst 7923866 # number of demand (read+write) hits 593system.cpu.icache.demand_hits::total 7923866 # number of demand (read+write) hits 594system.cpu.icache.overall_hits::cpu.inst 7923866 # number of overall hits 595system.cpu.icache.overall_hits::total 7923866 # number of overall hits 596system.cpu.icache.ReadReq_misses::cpu.inst 1118784 # number of ReadReq misses 597system.cpu.icache.ReadReq_misses::total 1118784 # number of ReadReq misses 598system.cpu.icache.demand_misses::cpu.inst 1118784 # number of demand (read+write) misses 599system.cpu.icache.demand_misses::total 1118784 # number of demand (read+write) misses 600system.cpu.icache.overall_misses::cpu.inst 1118784 # number of overall misses 601system.cpu.icache.overall_misses::total 1118784 # number of overall misses 602system.cpu.icache.ReadReq_miss_latency::cpu.inst 15167301487 # number of ReadReq miss cycles 603system.cpu.icache.ReadReq_miss_latency::total 15167301487 # number of ReadReq miss cycles 604system.cpu.icache.demand_miss_latency::cpu.inst 15167301487 # number of demand (read+write) miss cycles 605system.cpu.icache.demand_miss_latency::total 15167301487 # number of demand (read+write) miss cycles 606system.cpu.icache.overall_miss_latency::cpu.inst 15167301487 # number of overall miss cycles 607system.cpu.icache.overall_miss_latency::total 15167301487 # number of overall miss cycles 608system.cpu.icache.ReadReq_accesses::cpu.inst 9042650 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.ReadReq_accesses::total 9042650 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.demand_accesses::cpu.inst 9042650 # number of demand (read+write) accesses 611system.cpu.icache.demand_accesses::total 9042650 # number of demand (read+write) accesses 612system.cpu.icache.overall_accesses::cpu.inst 9042650 # number of overall (read+write) accesses 613system.cpu.icache.overall_accesses::total 9042650 # number of overall (read+write) accesses 614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123723 # miss rate for ReadReq accesses 615system.cpu.icache.ReadReq_miss_rate::total 0.123723 # miss rate for ReadReq accesses 616system.cpu.icache.demand_miss_rate::cpu.inst 0.123723 # miss rate for demand accesses 617system.cpu.icache.demand_miss_rate::total 0.123723 # miss rate for demand accesses 618system.cpu.icache.overall_miss_rate::cpu.inst 0.123723 # miss rate for overall accesses 619system.cpu.icache.overall_miss_rate::total 0.123723 # miss rate for overall accesses 620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13556.952447 # average ReadReq miss latency 621system.cpu.icache.ReadReq_avg_miss_latency::total 13556.952447 # average ReadReq miss latency 622system.cpu.icache.demand_avg_miss_latency::cpu.inst 13556.952447 # average overall miss latency 623system.cpu.icache.demand_avg_miss_latency::total 13556.952447 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::cpu.inst 13556.952447 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::total 13556.952447 # average overall miss latency 626system.cpu.icache.blocked_cycles::no_mshrs 9830 # number of cycles access was blocked |
| 627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 628system.cpu.icache.blocked::no_mshrs 267 # number of cycles access was blocked | 628system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked |
| 629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 630system.cpu.icache.avg_blocked_cycles::no_mshrs 25.737828 # average number of cycles each access was blocked | 630system.cpu.icache.avg_blocked_cycles::no_mshrs 33.664384 # average number of cycles each access was blocked |
| 631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.icache.fast_writes 0 # number of fast writes performed 633system.cpu.icache.cache_copies 0 # number of cache copies performed | 631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.icache.fast_writes 0 # number of fast writes performed 633system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 634system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61803 # number of ReadReq MSHR hits 635system.cpu.icache.ReadReq_mshr_hits::total 61803 # number of ReadReq MSHR hits 636system.cpu.icache.demand_mshr_hits::cpu.inst 61803 # number of demand (read+write) MSHR hits 637system.cpu.icache.demand_mshr_hits::total 61803 # number of demand (read+write) MSHR hits 638system.cpu.icache.overall_mshr_hits::cpu.inst 61803 # number of overall MSHR hits 639system.cpu.icache.overall_mshr_hits::total 61803 # number of overall MSHR hits 640system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1055811 # number of ReadReq MSHR misses 641system.cpu.icache.ReadReq_mshr_misses::total 1055811 # number of ReadReq MSHR misses 642system.cpu.icache.demand_mshr_misses::cpu.inst 1055811 # number of demand (read+write) MSHR misses 643system.cpu.icache.demand_mshr_misses::total 1055811 # number of demand (read+write) MSHR misses 644system.cpu.icache.overall_mshr_misses::cpu.inst 1055811 # number of overall MSHR misses 645system.cpu.icache.overall_mshr_misses::total 1055811 # number of overall MSHR misses 646system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12467027488 # number of ReadReq MSHR miss cycles 647system.cpu.icache.ReadReq_mshr_miss_latency::total 12467027488 # number of ReadReq MSHR miss cycles 648system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12467027488 # number of demand (read+write) MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::total 12467027488 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12467027488 # number of overall MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::total 12467027488 # number of overall MSHR miss cycles 652system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for ReadReq accesses 653system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116867 # mshr miss rate for ReadReq accesses 654system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for demand accesses 655system.cpu.icache.demand_mshr_miss_rate::total 0.116867 # mshr miss rate for demand accesses 656system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for overall accesses 657system.cpu.icache.overall_mshr_miss_rate::total 0.116867 # mshr miss rate for overall accesses 658system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.010608 # average ReadReq mshr miss latency 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.010608 # average ReadReq mshr miss latency 660system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.010608 # average overall mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.010608 # average overall mshr miss latency 662system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.010608 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.010608 # average overall mshr miss latency | 634system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61527 # number of ReadReq MSHR hits 635system.cpu.icache.ReadReq_mshr_hits::total 61527 # number of ReadReq MSHR hits 636system.cpu.icache.demand_mshr_hits::cpu.inst 61527 # number of demand (read+write) MSHR hits 637system.cpu.icache.demand_mshr_hits::total 61527 # number of demand (read+write) MSHR hits 638system.cpu.icache.overall_mshr_hits::cpu.inst 61527 # number of overall MSHR hits 639system.cpu.icache.overall_mshr_hits::total 61527 # number of overall MSHR hits 640system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1057257 # number of ReadReq MSHR misses 641system.cpu.icache.ReadReq_mshr_misses::total 1057257 # number of ReadReq MSHR misses 642system.cpu.icache.demand_mshr_misses::cpu.inst 1057257 # number of demand (read+write) MSHR misses 643system.cpu.icache.demand_mshr_misses::total 1057257 # number of demand (read+write) MSHR misses 644system.cpu.icache.overall_mshr_misses::cpu.inst 1057257 # number of overall MSHR misses 645system.cpu.icache.overall_mshr_misses::total 1057257 # number of overall MSHR misses 646system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12498307487 # number of ReadReq MSHR miss cycles 647system.cpu.icache.ReadReq_mshr_miss_latency::total 12498307487 # number of ReadReq MSHR miss cycles 648system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12498307487 # number of demand (read+write) MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::total 12498307487 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12498307487 # number of overall MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::total 12498307487 # number of overall MSHR miss cycles 652system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for ReadReq accesses 653system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116919 # mshr miss rate for ReadReq accesses 654system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for demand accesses 655system.cpu.icache.demand_mshr_miss_rate::total 0.116919 # mshr miss rate for demand accesses 656system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for overall accesses 657system.cpu.icache.overall_mshr_miss_rate::total 0.116919 # mshr miss rate for overall accesses 658system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11821.446902 # average ReadReq mshr miss latency 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11821.446902 # average ReadReq mshr miss latency 660system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11821.446902 # average overall mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::total 11821.446902 # average overall mshr miss latency 662system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11821.446902 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::total 11821.446902 # average overall mshr miss latency |
| 664system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 664system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 665system.cpu.itb_walker_cache.replacements 9172 # number of replacements 666system.cpu.itb_walker_cache.tagsinuse 6.015892 # Cycle average of tags in use 667system.cpu.itb_walker_cache.total_refs 26549 # Total number of references to valid blocks. 668system.cpu.itb_walker_cache.sampled_refs 9185 # Sample count of references to valid blocks. 669system.cpu.itb_walker_cache.avg_refs 2.890474 # Average number of references to valid blocks. 670system.cpu.itb_walker_cache.warmup_cycle 5104159763000 # Cycle when the warmup percentage was hit. 671system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.015892 # Average occupied blocks per requestor 672system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375993 # Average percentage of cache occupancy 673system.cpu.itb_walker_cache.occ_percent::total 0.375993 # Average percentage of cache occupancy 674system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26666 # number of ReadReq hits 675system.cpu.itb_walker_cache.ReadReq_hits::total 26666 # number of ReadReq hits | 665system.cpu.itb_walker_cache.replacements 9287 # number of replacements 666system.cpu.itb_walker_cache.tagsinuse 6.016215 # Cycle average of tags in use 667system.cpu.itb_walker_cache.total_refs 26989 # Total number of references to valid blocks. 668system.cpu.itb_walker_cache.sampled_refs 9300 # Sample count of references to valid blocks. 669system.cpu.itb_walker_cache.avg_refs 2.902043 # Average number of references to valid blocks. 670system.cpu.itb_walker_cache.warmup_cycle 5102704183500 # Cycle when the warmup percentage was hit. 671system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016215 # Average occupied blocks per requestor 672system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376013 # Average percentage of cache occupancy 673system.cpu.itb_walker_cache.occ_percent::total 0.376013 # Average percentage of cache occupancy 674system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27015 # number of ReadReq hits 675system.cpu.itb_walker_cache.ReadReq_hits::total 27015 # number of ReadReq hits |
| 676system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 677system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 676system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 677system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 678system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26668 # number of demand (read+write) hits 679system.cpu.itb_walker_cache.demand_hits::total 26668 # number of demand (read+write) hits 680system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26668 # number of overall hits 681system.cpu.itb_walker_cache.overall_hits::total 26668 # number of overall hits 682system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10048 # number of ReadReq misses 683system.cpu.itb_walker_cache.ReadReq_misses::total 10048 # number of ReadReq misses 684system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10048 # number of demand (read+write) misses 685system.cpu.itb_walker_cache.demand_misses::total 10048 # number of demand (read+write) misses 686system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10048 # number of overall misses 687system.cpu.itb_walker_cache.overall_misses::total 10048 # number of overall misses 688system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 111185500 # number of ReadReq miss cycles 689system.cpu.itb_walker_cache.ReadReq_miss_latency::total 111185500 # number of ReadReq miss cycles 690system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 111185500 # number of demand (read+write) miss cycles 691system.cpu.itb_walker_cache.demand_miss_latency::total 111185500 # number of demand (read+write) miss cycles 692system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 111185500 # number of overall miss cycles 693system.cpu.itb_walker_cache.overall_miss_latency::total 111185500 # number of overall miss cycles 694system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36714 # number of ReadReq accesses(hits+misses) 695system.cpu.itb_walker_cache.ReadReq_accesses::total 36714 # number of ReadReq accesses(hits+misses) | 678system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27017 # number of demand (read+write) hits 679system.cpu.itb_walker_cache.demand_hits::total 27017 # number of demand (read+write) hits 680system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27017 # number of overall hits 681system.cpu.itb_walker_cache.overall_hits::total 27017 # number of overall hits 682system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10179 # number of ReadReq misses 683system.cpu.itb_walker_cache.ReadReq_misses::total 10179 # number of ReadReq misses 684system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10179 # number of demand (read+write) misses 685system.cpu.itb_walker_cache.demand_misses::total 10179 # number of demand (read+write) misses 686system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10179 # number of overall misses 687system.cpu.itb_walker_cache.overall_misses::total 10179 # number of overall misses 688system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 111301500 # number of ReadReq miss cycles 689system.cpu.itb_walker_cache.ReadReq_miss_latency::total 111301500 # number of ReadReq miss cycles 690system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 111301500 # number of demand (read+write) miss cycles 691system.cpu.itb_walker_cache.demand_miss_latency::total 111301500 # number of demand (read+write) miss cycles 692system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 111301500 # number of overall miss cycles 693system.cpu.itb_walker_cache.overall_miss_latency::total 111301500 # number of overall miss cycles 694system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37194 # number of ReadReq accesses(hits+misses) 695system.cpu.itb_walker_cache.ReadReq_accesses::total 37194 # number of ReadReq accesses(hits+misses) |
| 696system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 697system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 696system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 697system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 698system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36716 # number of demand (read+write) accesses 699system.cpu.itb_walker_cache.demand_accesses::total 36716 # number of demand (read+write) accesses 700system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36716 # number of overall (read+write) accesses 701system.cpu.itb_walker_cache.overall_accesses::total 36716 # number of overall (read+write) accesses 702system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.273683 # miss rate for ReadReq accesses 703system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.273683 # miss rate for ReadReq accesses 704system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.273668 # miss rate for demand accesses 705system.cpu.itb_walker_cache.demand_miss_rate::total 0.273668 # miss rate for demand accesses 706system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.273668 # miss rate for overall accesses 707system.cpu.itb_walker_cache.overall_miss_rate::total 0.273668 # miss rate for overall accesses 708system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11065.435908 # average ReadReq miss latency 709system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11065.435908 # average ReadReq miss latency 710system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11065.435908 # average overall miss latency 711system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11065.435908 # average overall miss latency 712system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11065.435908 # average overall miss latency 713system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11065.435908 # average overall miss latency | 698system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37196 # number of demand (read+write) accesses 699system.cpu.itb_walker_cache.demand_accesses::total 37196 # number of demand (read+write) accesses 700system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37196 # number of overall (read+write) accesses 701system.cpu.itb_walker_cache.overall_accesses::total 37196 # number of overall (read+write) accesses 702system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.273673 # miss rate for ReadReq accesses 703system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.273673 # miss rate for ReadReq accesses 704system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.273658 # miss rate for demand accesses 705system.cpu.itb_walker_cache.demand_miss_rate::total 0.273658 # miss rate for demand accesses 706system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.273658 # miss rate for overall accesses 707system.cpu.itb_walker_cache.overall_miss_rate::total 0.273658 # miss rate for overall accesses 708system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10934.423814 # average ReadReq miss latency 709system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10934.423814 # average ReadReq miss latency 710system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10934.423814 # average overall miss latency 711system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10934.423814 # average overall miss latency 712system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10934.423814 # average overall miss latency 713system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10934.423814 # average overall miss latency |
| 714system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 715system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 716system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 717system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 718system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 719system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 720system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 721system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 714system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 715system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 716system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 717system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 718system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 719system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 720system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 721system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 722system.cpu.itb_walker_cache.writebacks::writebacks 1844 # number of writebacks 723system.cpu.itb_walker_cache.writebacks::total 1844 # number of writebacks 724system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10048 # number of ReadReq MSHR misses 725system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10048 # number of ReadReq MSHR misses 726system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10048 # number of demand (read+write) MSHR misses 727system.cpu.itb_walker_cache.demand_mshr_misses::total 10048 # number of demand (read+write) MSHR misses 728system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10048 # number of overall MSHR misses 729system.cpu.itb_walker_cache.overall_mshr_misses::total 10048 # number of overall MSHR misses 730system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 91089500 # number of ReadReq MSHR miss cycles 731system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 91089500 # number of ReadReq MSHR miss cycles 732system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 91089500 # number of demand (read+write) MSHR miss cycles 733system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 91089500 # number of demand (read+write) MSHR miss cycles 734system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 91089500 # number of overall MSHR miss cycles 735system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 91089500 # number of overall MSHR miss cycles 736system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.273683 # mshr miss rate for ReadReq accesses 737system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.273683 # mshr miss rate for ReadReq accesses 738system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.273668 # mshr miss rate for demand accesses 739system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.273668 # mshr miss rate for demand accesses 740system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.273668 # mshr miss rate for overall accesses 741system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.273668 # mshr miss rate for overall accesses 742system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average ReadReq mshr miss latency 743system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9065.435908 # average ReadReq mshr miss latency 744system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency 745system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9065.435908 # average overall mshr miss latency 746system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency 747system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9065.435908 # average overall mshr miss latency | 722system.cpu.itb_walker_cache.writebacks::writebacks 1896 # number of writebacks 723system.cpu.itb_walker_cache.writebacks::total 1896 # number of writebacks 724system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10179 # number of ReadReq MSHR misses 725system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10179 # number of ReadReq MSHR misses 726system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10179 # number of demand (read+write) MSHR misses 727system.cpu.itb_walker_cache.demand_mshr_misses::total 10179 # number of demand (read+write) MSHR misses 728system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10179 # number of overall MSHR misses 729system.cpu.itb_walker_cache.overall_mshr_misses::total 10179 # number of overall MSHR misses 730system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 90943500 # number of ReadReq MSHR miss cycles 731system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 90943500 # number of ReadReq MSHR miss cycles 732system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 90943500 # number of demand (read+write) MSHR miss cycles 733system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 90943500 # number of demand (read+write) MSHR miss cycles 734system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 90943500 # number of overall MSHR miss cycles 735system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 90943500 # number of overall MSHR miss cycles 736system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.273673 # mshr miss rate for ReadReq accesses 737system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.273673 # mshr miss rate for ReadReq accesses 738system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.273658 # mshr miss rate for demand accesses 739system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.273658 # mshr miss rate for demand accesses 740system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.273658 # mshr miss rate for overall accesses 741system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.273658 # mshr miss rate for overall accesses 742system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average ReadReq mshr miss latency 743system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8934.423814 # average ReadReq mshr miss latency 744system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average overall mshr miss latency 745system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8934.423814 # average overall mshr miss latency 746system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average overall mshr miss latency 747system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8934.423814 # average overall mshr miss latency |
| 748system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 748system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 749system.cpu.dtb_walker_cache.replacements 111590 # number of replacements 750system.cpu.dtb_walker_cache.tagsinuse 11.995325 # Cycle average of tags in use 751system.cpu.dtb_walker_cache.total_refs 130038 # Total number of references to valid blocks. 752system.cpu.dtb_walker_cache.sampled_refs 111605 # Sample count of references to valid blocks. 753system.cpu.dtb_walker_cache.avg_refs 1.165163 # Average number of references to valid blocks. 754system.cpu.dtb_walker_cache.warmup_cycle 5100439779500 # Cycle when the warmup percentage was hit. 755system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.995325 # Average occupied blocks per requestor 756system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749708 # Average percentage of cache occupancy 757system.cpu.dtb_walker_cache.occ_percent::total 0.749708 # Average percentage of cache occupancy 758system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130049 # number of ReadReq hits 759system.cpu.dtb_walker_cache.ReadReq_hits::total 130049 # number of ReadReq hits 760system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130049 # number of demand (read+write) hits 761system.cpu.dtb_walker_cache.demand_hits::total 130049 # number of demand (read+write) hits 762system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130049 # number of overall hits 763system.cpu.dtb_walker_cache.overall_hits::total 130049 # number of overall hits 764system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 112651 # number of ReadReq misses 765system.cpu.dtb_walker_cache.ReadReq_misses::total 112651 # number of ReadReq misses 766system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 112651 # number of demand (read+write) misses 767system.cpu.dtb_walker_cache.demand_misses::total 112651 # number of demand (read+write) misses 768system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 112651 # number of overall misses 769system.cpu.dtb_walker_cache.overall_misses::total 112651 # number of overall misses 770system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1400311500 # number of ReadReq miss cycles 771system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1400311500 # number of ReadReq miss cycles 772system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1400311500 # number of demand (read+write) miss cycles 773system.cpu.dtb_walker_cache.demand_miss_latency::total 1400311500 # number of demand (read+write) miss cycles 774system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1400311500 # number of overall miss cycles 775system.cpu.dtb_walker_cache.overall_miss_latency::total 1400311500 # number of overall miss cycles 776system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 242700 # number of ReadReq accesses(hits+misses) 777system.cpu.dtb_walker_cache.ReadReq_accesses::total 242700 # number of ReadReq accesses(hits+misses) 778system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 242700 # number of demand (read+write) accesses 779system.cpu.dtb_walker_cache.demand_accesses::total 242700 # number of demand (read+write) accesses 780system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 242700 # number of overall (read+write) accesses 781system.cpu.dtb_walker_cache.overall_accesses::total 242700 # number of overall (read+write) accesses 782system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.464157 # miss rate for ReadReq accesses 783system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.464157 # miss rate for ReadReq accesses 784system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.464157 # miss rate for demand accesses 785system.cpu.dtb_walker_cache.demand_miss_rate::total 0.464157 # miss rate for demand accesses 786system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.464157 # miss rate for overall accesses 787system.cpu.dtb_walker_cache.overall_miss_rate::total 0.464157 # miss rate for overall accesses 788system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12430.528801 # average ReadReq miss latency 789system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12430.528801 # average ReadReq miss latency 790system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency 791system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12430.528801 # average overall miss latency 792system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency 793system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12430.528801 # average overall miss latency | 749system.cpu.dtb_walker_cache.replacements 108224 # number of replacements 750system.cpu.dtb_walker_cache.tagsinuse 12.929654 # Cycle average of tags in use 751system.cpu.dtb_walker_cache.total_refs 137412 # Total number of references to valid blocks. 752system.cpu.dtb_walker_cache.sampled_refs 108239 # Sample count of references to valid blocks. 753system.cpu.dtb_walker_cache.avg_refs 1.269524 # Average number of references to valid blocks. 754system.cpu.dtb_walker_cache.warmup_cycle 5100455706500 # Cycle when the warmup percentage was hit. 755system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.929654 # Average occupied blocks per requestor 756system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808103 # Average percentage of cache occupancy 757system.cpu.dtb_walker_cache.occ_percent::total 0.808103 # Average percentage of cache occupancy 758system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137417 # number of ReadReq hits 759system.cpu.dtb_walker_cache.ReadReq_hits::total 137417 # number of ReadReq hits 760system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137417 # number of demand (read+write) hits 761system.cpu.dtb_walker_cache.demand_hits::total 137417 # number of demand (read+write) hits 762system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137417 # number of overall hits 763system.cpu.dtb_walker_cache.overall_hits::total 137417 # number of overall hits 764system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109249 # number of ReadReq misses 765system.cpu.dtb_walker_cache.ReadReq_misses::total 109249 # number of ReadReq misses 766system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109249 # number of demand (read+write) misses 767system.cpu.dtb_walker_cache.demand_misses::total 109249 # number of demand (read+write) misses 768system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109249 # number of overall misses 769system.cpu.dtb_walker_cache.overall_misses::total 109249 # number of overall misses 770system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1361810000 # number of ReadReq miss cycles 771system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1361810000 # number of ReadReq miss cycles 772system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1361810000 # number of demand (read+write) miss cycles 773system.cpu.dtb_walker_cache.demand_miss_latency::total 1361810000 # number of demand (read+write) miss cycles 774system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1361810000 # number of overall miss cycles 775system.cpu.dtb_walker_cache.overall_miss_latency::total 1361810000 # number of overall miss cycles 776system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 246666 # number of ReadReq accesses(hits+misses) 777system.cpu.dtb_walker_cache.ReadReq_accesses::total 246666 # number of ReadReq accesses(hits+misses) 778system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 246666 # number of demand (read+write) accesses 779system.cpu.dtb_walker_cache.demand_accesses::total 246666 # number of demand (read+write) accesses 780system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 246666 # number of overall (read+write) accesses 781system.cpu.dtb_walker_cache.overall_accesses::total 246666 # number of overall (read+write) accesses 782system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442903 # miss rate for ReadReq accesses 783system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442903 # miss rate for ReadReq accesses 784system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442903 # miss rate for demand accesses 785system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442903 # miss rate for demand accesses 786system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442903 # miss rate for overall accesses 787system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442903 # miss rate for overall accesses 788system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.194189 # average ReadReq miss latency 789system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.194189 # average ReadReq miss latency 790system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.194189 # average overall miss latency 791system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.194189 # average overall miss latency 792system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.194189 # average overall miss latency 793system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.194189 # average overall miss latency |
| 794system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 795system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 796system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 797system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 798system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 799system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 800system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 801system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 794system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 795system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 796system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 797system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 798system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 799system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 800system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 801system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 802system.cpu.dtb_walker_cache.writebacks::writebacks 35078 # number of writebacks 803system.cpu.dtb_walker_cache.writebacks::total 35078 # number of writebacks 804system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 112651 # number of ReadReq MSHR misses 805system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 112651 # number of ReadReq MSHR misses 806system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 112651 # number of demand (read+write) MSHR misses 807system.cpu.dtb_walker_cache.demand_mshr_misses::total 112651 # number of demand (read+write) MSHR misses 808system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 112651 # number of overall MSHR misses 809system.cpu.dtb_walker_cache.overall_mshr_misses::total 112651 # number of overall MSHR misses 810system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of ReadReq MSHR miss cycles 811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1175009500 # number of ReadReq MSHR miss cycles 812system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of demand (read+write) MSHR miss cycles 813system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1175009500 # number of demand (read+write) MSHR miss cycles 814system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of overall MSHR miss cycles 815system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1175009500 # number of overall MSHR miss cycles 816system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for ReadReq accesses 817system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.464157 # mshr miss rate for ReadReq accesses 818system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for demand accesses 819system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.464157 # mshr miss rate for demand accesses 820system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for overall accesses 821system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.464157 # mshr miss rate for overall accesses 822system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average ReadReq mshr miss latency 823system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10430.528801 # average ReadReq mshr miss latency 824system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency 825system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency 826system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency 827system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency | 802system.cpu.dtb_walker_cache.writebacks::writebacks 34685 # number of writebacks 803system.cpu.dtb_walker_cache.writebacks::total 34685 # number of writebacks 804system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109249 # number of ReadReq MSHR misses 805system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109249 # number of ReadReq MSHR misses 806system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109249 # number of demand (read+write) MSHR misses 807system.cpu.dtb_walker_cache.demand_mshr_misses::total 109249 # number of demand (read+write) MSHR misses 808system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109249 # number of overall MSHR misses 809system.cpu.dtb_walker_cache.overall_mshr_misses::total 109249 # number of overall MSHR misses 810system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of ReadReq MSHR miss cycles 811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1143312000 # number of ReadReq MSHR miss cycles 812system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of demand (read+write) MSHR miss cycles 813system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1143312000 # number of demand (read+write) MSHR miss cycles 814system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of overall MSHR miss cycles 815system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1143312000 # number of overall MSHR miss cycles 816system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for ReadReq accesses 817system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442903 # mshr miss rate for ReadReq accesses 818system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for demand accesses 819system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442903 # mshr miss rate for demand accesses 820system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for overall accesses 821system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442903 # mshr miss rate for overall accesses 822system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average ReadReq mshr miss latency 823system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.194189 # average ReadReq mshr miss latency 824system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average overall mshr miss latency 825system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.194189 # average overall mshr miss latency 826system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average overall mshr miss latency 827system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.194189 # average overall mshr miss latency |
| 828system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 828system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 829system.cpu.dcache.replacements 1661569 # number of replacements 830system.cpu.dcache.tagsinuse 511.994847 # Cycle average of tags in use 831system.cpu.dcache.total_refs 19098471 # Total number of references to valid blocks. 832system.cpu.dcache.sampled_refs 1662081 # Sample count of references to valid blocks. 833system.cpu.dcache.avg_refs 11.490698 # Average number of references to valid blocks. | 829system.cpu.dcache.replacements 1662857 # number of replacements 830system.cpu.dcache.tagsinuse 511.994597 # Cycle average of tags in use 831system.cpu.dcache.total_refs 19099158 # Total number of references to valid blocks. 832system.cpu.dcache.sampled_refs 1663369 # Sample count of references to valid blocks. 833system.cpu.dcache.avg_refs 11.482214 # Average number of references to valid blocks. |
| 834system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. | 834system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. |
| 835system.cpu.dcache.occ_blocks::cpu.data 511.994847 # Average occupied blocks per requestor 836system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 837system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy 838system.cpu.dcache.ReadReq_hits::cpu.data 11004011 # number of ReadReq hits 839system.cpu.dcache.ReadReq_hits::total 11004011 # number of ReadReq hits 840system.cpu.dcache.WriteReq_hits::cpu.data 8089317 # number of WriteReq hits 841system.cpu.dcache.WriteReq_hits::total 8089317 # number of WriteReq hits 842system.cpu.dcache.demand_hits::cpu.data 19093328 # number of demand (read+write) hits 843system.cpu.dcache.demand_hits::total 19093328 # number of demand (read+write) hits 844system.cpu.dcache.overall_hits::cpu.data 19093328 # number of overall hits 845system.cpu.dcache.overall_hits::total 19093328 # number of overall hits 846system.cpu.dcache.ReadReq_misses::cpu.data 2239016 # number of ReadReq misses 847system.cpu.dcache.ReadReq_misses::total 2239016 # number of ReadReq misses 848system.cpu.dcache.WriteReq_misses::cpu.data 318822 # number of WriteReq misses 849system.cpu.dcache.WriteReq_misses::total 318822 # number of WriteReq misses 850system.cpu.dcache.demand_misses::cpu.data 2557838 # number of demand (read+write) misses 851system.cpu.dcache.demand_misses::total 2557838 # number of demand (read+write) misses 852system.cpu.dcache.overall_misses::cpu.data 2557838 # number of overall misses 853system.cpu.dcache.overall_misses::total 2557838 # number of overall misses 854system.cpu.dcache.ReadReq_miss_latency::cpu.data 31972900500 # number of ReadReq miss cycles 855system.cpu.dcache.ReadReq_miss_latency::total 31972900500 # number of ReadReq miss cycles 856system.cpu.dcache.WriteReq_miss_latency::cpu.data 9624592994 # number of WriteReq miss cycles 857system.cpu.dcache.WriteReq_miss_latency::total 9624592994 # number of WriteReq miss cycles 858system.cpu.dcache.demand_miss_latency::cpu.data 41597493494 # number of demand (read+write) miss cycles 859system.cpu.dcache.demand_miss_latency::total 41597493494 # number of demand (read+write) miss cycles 860system.cpu.dcache.overall_miss_latency::cpu.data 41597493494 # number of overall miss cycles 861system.cpu.dcache.overall_miss_latency::total 41597493494 # number of overall miss cycles 862system.cpu.dcache.ReadReq_accesses::cpu.data 13243027 # number of ReadReq accesses(hits+misses) 863system.cpu.dcache.ReadReq_accesses::total 13243027 # number of ReadReq accesses(hits+misses) 864system.cpu.dcache.WriteReq_accesses::cpu.data 8408139 # number of WriteReq accesses(hits+misses) 865system.cpu.dcache.WriteReq_accesses::total 8408139 # number of WriteReq accesses(hits+misses) 866system.cpu.dcache.demand_accesses::cpu.data 21651166 # number of demand (read+write) accesses 867system.cpu.dcache.demand_accesses::total 21651166 # number of demand (read+write) accesses 868system.cpu.dcache.overall_accesses::cpu.data 21651166 # number of overall (read+write) accesses 869system.cpu.dcache.overall_accesses::total 21651166 # number of overall (read+write) accesses 870system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169071 # miss rate for ReadReq accesses 871system.cpu.dcache.ReadReq_miss_rate::total 0.169071 # miss rate for ReadReq accesses 872system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037918 # miss rate for WriteReq accesses 873system.cpu.dcache.WriteReq_miss_rate::total 0.037918 # miss rate for WriteReq accesses 874system.cpu.dcache.demand_miss_rate::cpu.data 0.118139 # miss rate for demand accesses 875system.cpu.dcache.demand_miss_rate::total 0.118139 # miss rate for demand accesses 876system.cpu.dcache.overall_miss_rate::cpu.data 0.118139 # miss rate for overall accesses 877system.cpu.dcache.overall_miss_rate::total 0.118139 # miss rate for overall accesses 878system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14279.889246 # average ReadReq miss latency 879system.cpu.dcache.ReadReq_avg_miss_latency::total 14279.889246 # average ReadReq miss latency 880system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30187.982617 # average WriteReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::total 30187.982617 # average WriteReq miss latency 882system.cpu.dcache.demand_avg_miss_latency::cpu.data 16262.755301 # average overall miss latency 883system.cpu.dcache.demand_avg_miss_latency::total 16262.755301 # average overall miss latency 884system.cpu.dcache.overall_avg_miss_latency::cpu.data 16262.755301 # average overall miss latency 885system.cpu.dcache.overall_avg_miss_latency::total 16262.755301 # average overall miss latency 886system.cpu.dcache.blocked_cycles::no_mshrs 404649 # number of cycles access was blocked | 835system.cpu.dcache.occ_blocks::cpu.data 511.994597 # Average occupied blocks per requestor 836system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 837system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy 838system.cpu.dcache.ReadReq_hits::cpu.data 11001158 # number of ReadReq hits 839system.cpu.dcache.ReadReq_hits::total 11001158 # number of ReadReq hits 840system.cpu.dcache.WriteReq_hits::cpu.data 8092803 # number of WriteReq hits 841system.cpu.dcache.WriteReq_hits::total 8092803 # number of WriteReq hits 842system.cpu.dcache.demand_hits::cpu.data 19093961 # number of demand (read+write) hits 843system.cpu.dcache.demand_hits::total 19093961 # number of demand (read+write) hits 844system.cpu.dcache.overall_hits::cpu.data 19093961 # number of overall hits 845system.cpu.dcache.overall_hits::total 19093961 # number of overall hits 846system.cpu.dcache.ReadReq_misses::cpu.data 2250786 # number of ReadReq misses 847system.cpu.dcache.ReadReq_misses::total 2250786 # number of ReadReq misses 848system.cpu.dcache.WriteReq_misses::cpu.data 319407 # number of WriteReq misses 849system.cpu.dcache.WriteReq_misses::total 319407 # number of WriteReq misses 850system.cpu.dcache.demand_misses::cpu.data 2570193 # number of demand (read+write) misses 851system.cpu.dcache.demand_misses::total 2570193 # number of demand (read+write) misses 852system.cpu.dcache.overall_misses::cpu.data 2570193 # number of overall misses 853system.cpu.dcache.overall_misses::total 2570193 # number of overall misses 854system.cpu.dcache.ReadReq_miss_latency::cpu.data 32047872500 # number of ReadReq miss cycles 855system.cpu.dcache.ReadReq_miss_latency::total 32047872500 # number of ReadReq miss cycles 856system.cpu.dcache.WriteReq_miss_latency::cpu.data 9644777995 # number of WriteReq miss cycles 857system.cpu.dcache.WriteReq_miss_latency::total 9644777995 # number of WriteReq miss cycles 858system.cpu.dcache.demand_miss_latency::cpu.data 41692650495 # number of demand (read+write) miss cycles 859system.cpu.dcache.demand_miss_latency::total 41692650495 # number of demand (read+write) miss cycles 860system.cpu.dcache.overall_miss_latency::cpu.data 41692650495 # number of overall miss cycles 861system.cpu.dcache.overall_miss_latency::total 41692650495 # number of overall miss cycles 862system.cpu.dcache.ReadReq_accesses::cpu.data 13251944 # number of ReadReq accesses(hits+misses) 863system.cpu.dcache.ReadReq_accesses::total 13251944 # number of ReadReq accesses(hits+misses) 864system.cpu.dcache.WriteReq_accesses::cpu.data 8412210 # number of WriteReq accesses(hits+misses) 865system.cpu.dcache.WriteReq_accesses::total 8412210 # number of WriteReq accesses(hits+misses) 866system.cpu.dcache.demand_accesses::cpu.data 21664154 # number of demand (read+write) accesses 867system.cpu.dcache.demand_accesses::total 21664154 # number of demand (read+write) accesses 868system.cpu.dcache.overall_accesses::cpu.data 21664154 # number of overall (read+write) accesses 869system.cpu.dcache.overall_accesses::total 21664154 # number of overall (read+write) accesses 870system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169846 # miss rate for ReadReq accesses 871system.cpu.dcache.ReadReq_miss_rate::total 0.169846 # miss rate for ReadReq accesses 872system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037969 # miss rate for WriteReq accesses 873system.cpu.dcache.WriteReq_miss_rate::total 0.037969 # miss rate for WriteReq accesses 874system.cpu.dcache.demand_miss_rate::cpu.data 0.118638 # miss rate for demand accesses 875system.cpu.dcache.demand_miss_rate::total 0.118638 # miss rate for demand accesses 876system.cpu.dcache.overall_miss_rate::cpu.data 0.118638 # miss rate for overall accesses 877system.cpu.dcache.overall_miss_rate::total 0.118638 # miss rate for overall accesses 878system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14238.524898 # average ReadReq miss latency 879system.cpu.dcache.ReadReq_avg_miss_latency::total 14238.524898 # average ReadReq miss latency 880system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30195.887989 # average WriteReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::total 30195.887989 # average WriteReq miss latency 882system.cpu.dcache.demand_avg_miss_latency::cpu.data 16221.603006 # average overall miss latency 883system.cpu.dcache.demand_avg_miss_latency::total 16221.603006 # average overall miss latency 884system.cpu.dcache.overall_avg_miss_latency::cpu.data 16221.603006 # average overall miss latency 885system.cpu.dcache.overall_avg_miss_latency::total 16221.603006 # average overall miss latency 886system.cpu.dcache.blocked_cycles::no_mshrs 397855 # number of cycles access was blocked |
| 887system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 887system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 888system.cpu.dcache.blocked::no_mshrs 42429 # number of cycles access was blocked | 888system.cpu.dcache.blocked::no_mshrs 42661 # number of cycles access was blocked |
| 889system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 889system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 890system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.537085 # average number of cycles each access was blocked | 890system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.325965 # average number of cycles each access was blocked |
| 891system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu.dcache.fast_writes 0 # number of fast writes performed 893system.cpu.dcache.cache_copies 0 # number of cache copies performed | 891system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu.dcache.fast_writes 0 # number of fast writes performed 893system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 894system.cpu.dcache.writebacks::writebacks 1562908 # number of writebacks 895system.cpu.dcache.writebacks::total 1562908 # number of writebacks 896system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864676 # number of ReadReq MSHR hits 897system.cpu.dcache.ReadReq_mshr_hits::total 864676 # number of ReadReq MSHR hits 898system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26384 # number of WriteReq MSHR hits 899system.cpu.dcache.WriteReq_mshr_hits::total 26384 # number of WriteReq MSHR hits 900system.cpu.dcache.demand_mshr_hits::cpu.data 891060 # number of demand (read+write) MSHR hits 901system.cpu.dcache.demand_mshr_hits::total 891060 # number of demand (read+write) MSHR hits 902system.cpu.dcache.overall_mshr_hits::cpu.data 891060 # number of overall MSHR hits 903system.cpu.dcache.overall_mshr_hits::total 891060 # number of overall MSHR hits 904system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1374340 # number of ReadReq MSHR misses 905system.cpu.dcache.ReadReq_mshr_misses::total 1374340 # number of ReadReq MSHR misses 906system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292438 # number of WriteReq MSHR misses 907system.cpu.dcache.WriteReq_mshr_misses::total 292438 # number of WriteReq MSHR misses 908system.cpu.dcache.demand_mshr_misses::cpu.data 1666778 # number of demand (read+write) MSHR misses 909system.cpu.dcache.demand_mshr_misses::total 1666778 # number of demand (read+write) MSHR misses 910system.cpu.dcache.overall_mshr_misses::cpu.data 1666778 # number of overall MSHR misses 911system.cpu.dcache.overall_mshr_misses::total 1666778 # number of overall MSHR misses 912system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17366494500 # number of ReadReq MSHR miss cycles 913system.cpu.dcache.ReadReq_mshr_miss_latency::total 17366494500 # number of ReadReq MSHR miss cycles 914system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8784809994 # number of WriteReq MSHR miss cycles 915system.cpu.dcache.WriteReq_mshr_miss_latency::total 8784809994 # number of WriteReq MSHR miss cycles 916system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26151304494 # number of demand (read+write) MSHR miss cycles 917system.cpu.dcache.demand_mshr_miss_latency::total 26151304494 # number of demand (read+write) MSHR miss cycles 918system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26151304494 # number of overall MSHR miss cycles 919system.cpu.dcache.overall_mshr_miss_latency::total 26151304494 # number of overall MSHR miss cycles 920system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97298090500 # number of ReadReq MSHR uncacheable cycles 921system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97298090500 # number of ReadReq MSHR uncacheable cycles 922system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473113000 # number of WriteReq MSHR uncacheable cycles 923system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473113000 # number of WriteReq MSHR uncacheable cycles 924system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99771203500 # number of overall MSHR uncacheable cycles 925system.cpu.dcache.overall_mshr_uncacheable_latency::total 99771203500 # number of overall MSHR uncacheable cycles 926system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103778 # mshr miss rate for ReadReq accesses 927system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103778 # mshr miss rate for ReadReq accesses 928system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034780 # mshr miss rate for WriteReq accesses 929system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034780 # mshr miss rate for WriteReq accesses 930system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076983 # mshr miss rate for demand accesses 931system.cpu.dcache.demand_mshr_miss_rate::total 0.076983 # mshr miss rate for demand accesses 932system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076983 # mshr miss rate for overall accesses 933system.cpu.dcache.overall_mshr_miss_rate::total 0.076983 # mshr miss rate for overall accesses 934system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.243215 # average ReadReq mshr miss latency 935system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.243215 # average ReadReq mshr miss latency 936system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30039.905874 # average WriteReq mshr miss latency 937system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30039.905874 # average WriteReq mshr miss latency 938system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15689.734622 # average overall mshr miss latency 939system.cpu.dcache.demand_avg_mshr_miss_latency::total 15689.734622 # average overall mshr miss latency 940system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15689.734622 # average overall mshr miss latency 941system.cpu.dcache.overall_avg_mshr_miss_latency::total 15689.734622 # average overall mshr miss latency | 894system.cpu.dcache.writebacks::writebacks 1564276 # number of writebacks 895system.cpu.dcache.writebacks::total 1564276 # number of writebacks 896system.cpu.dcache.ReadReq_mshr_hits::cpu.data 877119 # number of ReadReq MSHR hits 897system.cpu.dcache.ReadReq_mshr_hits::total 877119 # number of ReadReq MSHR hits 898system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25009 # number of WriteReq MSHR hits 899system.cpu.dcache.WriteReq_mshr_hits::total 25009 # number of WriteReq MSHR hits 900system.cpu.dcache.demand_mshr_hits::cpu.data 902128 # number of demand (read+write) MSHR hits 901system.cpu.dcache.demand_mshr_hits::total 902128 # number of demand (read+write) MSHR hits 902system.cpu.dcache.overall_mshr_hits::cpu.data 902128 # number of overall MSHR hits 903system.cpu.dcache.overall_mshr_hits::total 902128 # number of overall MSHR hits 904system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1373667 # number of ReadReq MSHR misses 905system.cpu.dcache.ReadReq_mshr_misses::total 1373667 # number of ReadReq MSHR misses 906system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294398 # number of WriteReq MSHR misses 907system.cpu.dcache.WriteReq_mshr_misses::total 294398 # number of WriteReq MSHR misses 908system.cpu.dcache.demand_mshr_misses::cpu.data 1668065 # number of demand (read+write) MSHR misses 909system.cpu.dcache.demand_mshr_misses::total 1668065 # number of demand (read+write) MSHR misses 910system.cpu.dcache.overall_mshr_misses::cpu.data 1668065 # number of overall MSHR misses 911system.cpu.dcache.overall_mshr_misses::total 1668065 # number of overall MSHR misses 912system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17358648500 # number of ReadReq MSHR miss cycles 913system.cpu.dcache.ReadReq_mshr_miss_latency::total 17358648500 # number of ReadReq MSHR miss cycles 914system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800545995 # number of WriteReq MSHR miss cycles 915system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800545995 # number of WriteReq MSHR miss cycles 916system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26159194495 # number of demand (read+write) MSHR miss cycles 917system.cpu.dcache.demand_mshr_miss_latency::total 26159194495 # number of demand (read+write) MSHR miss cycles 918system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26159194495 # number of overall MSHR miss cycles 919system.cpu.dcache.overall_mshr_miss_latency::total 26159194495 # number of overall MSHR miss cycles 920system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296699500 # number of ReadReq MSHR uncacheable cycles 921system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296699500 # number of ReadReq MSHR uncacheable cycles 922system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470652500 # number of WriteReq MSHR uncacheable cycles 923system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470652500 # number of WriteReq MSHR uncacheable cycles 924system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767352000 # number of overall MSHR uncacheable cycles 925system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767352000 # number of overall MSHR uncacheable cycles 926system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103658 # mshr miss rate for ReadReq accesses 927system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103658 # mshr miss rate for ReadReq accesses 928system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034997 # mshr miss rate for WriteReq accesses 929system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034997 # mshr miss rate for WriteReq accesses 930system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076997 # mshr miss rate for demand accesses 931system.cpu.dcache.demand_mshr_miss_rate::total 0.076997 # mshr miss rate for demand accesses 932system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076997 # mshr miss rate for overall accesses 933system.cpu.dcache.overall_mshr_miss_rate::total 0.076997 # mshr miss rate for overall accesses 934system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.722364 # average ReadReq mshr miss latency 935system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.722364 # average ReadReq mshr miss latency 936system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29893.362030 # average WriteReq mshr miss latency 937system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29893.362030 # average WriteReq mshr miss latency 938system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15682.359198 # average overall mshr miss latency 939system.cpu.dcache.demand_avg_mshr_miss_latency::total 15682.359198 # average overall mshr miss latency 940system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15682.359198 # average overall mshr miss latency 941system.cpu.dcache.overall_avg_mshr_miss_latency::total 15682.359198 # average overall mshr miss latency |
| 942system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 943system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 944system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 945system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 946system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 947system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 948system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 942system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 943system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 944system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 945system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 946system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 947system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 948system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 949system.cpu.l2cache.replacements 114048 # number of replacements 950system.cpu.l2cache.tagsinuse 64828.781789 # Cycle average of tags in use 951system.cpu.l2cache.total_refs 3943145 # Total number of references to valid blocks. 952system.cpu.l2cache.sampled_refs 178083 # Sample count of references to valid blocks. 953system.cpu.l2cache.avg_refs 22.142175 # Average number of references to valid blocks. | 949system.cpu.l2cache.replacements 113558 # number of replacements 950system.cpu.l2cache.tagsinuse 64830.425237 # Cycle average of tags in use 951system.cpu.l2cache.total_refs 3942801 # Total number of references to valid blocks. 952system.cpu.l2cache.sampled_refs 177506 # Sample count of references to valid blocks. 953system.cpu.l2cache.avg_refs 22.212213 # Average number of references to valid blocks. |
| 954system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 954system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 955system.cpu.l2cache.occ_blocks::writebacks 50215.061729 # Average occupied blocks per requestor 956system.cpu.l2cache.occ_blocks::cpu.dtb.walker 7.199221 # Average occupied blocks per requestor 957system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133392 # Average occupied blocks per requestor 958system.cpu.l2cache.occ_blocks::cpu.inst 3209.208803 # Average occupied blocks per requestor 959system.cpu.l2cache.occ_blocks::cpu.data 11397.178643 # Average occupied blocks per requestor 960system.cpu.l2cache.occ_percent::writebacks 0.766221 # Average percentage of cache occupancy 961system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000110 # Average percentage of cache occupancy | 955system.cpu.l2cache.occ_blocks::writebacks 50104.773483 # Average occupied blocks per requestor 956system.cpu.l2cache.occ_blocks::cpu.dtb.walker 12.386832 # Average occupied blocks per requestor 957system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133410 # Average occupied blocks per requestor 958system.cpu.l2cache.occ_blocks::cpu.inst 3229.258620 # Average occupied blocks per requestor 959system.cpu.l2cache.occ_blocks::cpu.data 11483.872893 # Average occupied blocks per requestor 960system.cpu.l2cache.occ_percent::writebacks 0.764538 # Average percentage of cache occupancy 961system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000189 # Average percentage of cache occupancy |
| 962system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 962system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 963system.cpu.l2cache.occ_percent::cpu.inst 0.048969 # Average percentage of cache occupancy 964system.cpu.l2cache.occ_percent::cpu.data 0.173907 # Average percentage of cache occupancy 965system.cpu.l2cache.occ_percent::total 0.989209 # Average percentage of cache occupancy 966system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103777 # number of ReadReq hits 967system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7654 # number of ReadReq hits 968system.cpu.l2cache.ReadReq_hits::cpu.inst 1036447 # number of ReadReq hits 969system.cpu.l2cache.ReadReq_hits::cpu.data 1336423 # number of ReadReq hits 970system.cpu.l2cache.ReadReq_hits::total 2484301 # number of ReadReq hits 971system.cpu.l2cache.Writeback_hits::writebacks 1599830 # number of Writeback hits 972system.cpu.l2cache.Writeback_hits::total 1599830 # number of Writeback hits 973system.cpu.l2cache.UpgradeReq_hits::cpu.data 336 # number of UpgradeReq hits 974system.cpu.l2cache.UpgradeReq_hits::total 336 # number of UpgradeReq hits 975system.cpu.l2cache.ReadExReq_hits::cpu.data 154761 # number of ReadExReq hits 976system.cpu.l2cache.ReadExReq_hits::total 154761 # number of ReadExReq hits 977system.cpu.l2cache.demand_hits::cpu.dtb.walker 103777 # number of demand (read+write) hits 978system.cpu.l2cache.demand_hits::cpu.itb.walker 7654 # number of demand (read+write) hits 979system.cpu.l2cache.demand_hits::cpu.inst 1036447 # number of demand (read+write) hits 980system.cpu.l2cache.demand_hits::cpu.data 1491184 # number of demand (read+write) hits 981system.cpu.l2cache.demand_hits::total 2639062 # number of demand (read+write) hits 982system.cpu.l2cache.overall_hits::cpu.dtb.walker 103777 # number of overall hits 983system.cpu.l2cache.overall_hits::cpu.itb.walker 7654 # number of overall hits 984system.cpu.l2cache.overall_hits::cpu.inst 1036447 # number of overall hits 985system.cpu.l2cache.overall_hits::cpu.data 1491184 # number of overall hits 986system.cpu.l2cache.overall_hits::total 2639062 # number of overall hits 987system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses | 963system.cpu.l2cache.occ_percent::cpu.inst 0.049275 # Average percentage of cache occupancy 964system.cpu.l2cache.occ_percent::cpu.data 0.175230 # Average percentage of cache occupancy 965system.cpu.l2cache.occ_percent::total 0.989234 # Average percentage of cache occupancy 966system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101071 # number of ReadReq hits 967system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7595 # number of ReadReq hits 968system.cpu.l2cache.ReadReq_hits::cpu.inst 1037956 # number of ReadReq hits 969system.cpu.l2cache.ReadReq_hits::cpu.data 1335698 # number of ReadReq hits 970system.cpu.l2cache.ReadReq_hits::total 2482320 # number of ReadReq hits 971system.cpu.l2cache.Writeback_hits::writebacks 1600857 # number of Writeback hits 972system.cpu.l2cache.Writeback_hits::total 1600857 # number of Writeback hits 973system.cpu.l2cache.UpgradeReq_hits::cpu.data 332 # number of UpgradeReq hits 974system.cpu.l2cache.UpgradeReq_hits::total 332 # number of UpgradeReq hits 975system.cpu.l2cache.ReadExReq_hits::cpu.data 156999 # number of ReadExReq hits 976system.cpu.l2cache.ReadExReq_hits::total 156999 # number of ReadExReq hits 977system.cpu.l2cache.demand_hits::cpu.dtb.walker 101071 # number of demand (read+write) hits 978system.cpu.l2cache.demand_hits::cpu.itb.walker 7595 # number of demand (read+write) hits 979system.cpu.l2cache.demand_hits::cpu.inst 1037956 # number of demand (read+write) hits 980system.cpu.l2cache.demand_hits::cpu.data 1492697 # number of demand (read+write) hits 981system.cpu.l2cache.demand_hits::total 2639319 # number of demand (read+write) hits 982system.cpu.l2cache.overall_hits::cpu.dtb.walker 101071 # number of overall hits 983system.cpu.l2cache.overall_hits::cpu.itb.walker 7595 # number of overall hits 984system.cpu.l2cache.overall_hits::cpu.inst 1037956 # number of overall hits 985system.cpu.l2cache.overall_hits::cpu.data 1492697 # number of overall hits 986system.cpu.l2cache.overall_hits::total 2639319 # number of overall hits 987system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 47 # number of ReadReq misses |
| 988system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses | 988system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses |
| 989system.cpu.l2cache.ReadReq_misses::cpu.inst 16836 # number of ReadReq misses 990system.cpu.l2cache.ReadReq_misses::cpu.data 36777 # number of ReadReq misses 991system.cpu.l2cache.ReadReq_misses::total 53668 # number of ReadReq misses 992system.cpu.l2cache.UpgradeReq_misses::cpu.data 3876 # number of UpgradeReq misses 993system.cpu.l2cache.UpgradeReq_misses::total 3876 # number of UpgradeReq misses 994system.cpu.l2cache.ReadExReq_misses::cpu.data 133549 # number of ReadExReq misses 995system.cpu.l2cache.ReadExReq_misses::total 133549 # number of ReadExReq misses 996system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses | 989system.cpu.l2cache.ReadReq_misses::cpu.inst 16768 # number of ReadReq misses 990system.cpu.l2cache.ReadReq_misses::cpu.data 36730 # number of ReadReq misses 991system.cpu.l2cache.ReadReq_misses::total 53551 # number of ReadReq misses 992system.cpu.l2cache.UpgradeReq_misses::cpu.data 3897 # number of UpgradeReq misses 993system.cpu.l2cache.UpgradeReq_misses::total 3897 # number of UpgradeReq misses 994system.cpu.l2cache.ReadExReq_misses::cpu.data 133267 # number of ReadExReq misses 995system.cpu.l2cache.ReadExReq_misses::total 133267 # number of ReadExReq misses 996system.cpu.l2cache.demand_misses::cpu.dtb.walker 47 # number of demand (read+write) misses |
| 997system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses | 997system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses |
| 998system.cpu.l2cache.demand_misses::cpu.inst 16836 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::cpu.data 170326 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::total 187217 # number of demand (read+write) misses 1001system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses | 998system.cpu.l2cache.demand_misses::cpu.inst 16768 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::cpu.data 169997 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::total 186818 # number of demand (read+write) misses 1001system.cpu.l2cache.overall_misses::cpu.dtb.walker 47 # number of overall misses |
| 1002system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses | 1002system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses |
| 1003system.cpu.l2cache.overall_misses::cpu.inst 16836 # number of overall misses 1004system.cpu.l2cache.overall_misses::cpu.data 170326 # number of overall misses 1005system.cpu.l2cache.overall_misses::total 187217 # number of overall misses 1006system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3729000 # number of ReadReq miss cycles 1007system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 431500 # number of ReadReq miss cycles 1008system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 993413500 # number of ReadReq miss cycles 1009system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2399373497 # number of ReadReq miss cycles 1010system.cpu.l2cache.ReadReq_miss_latency::total 3396947497 # number of ReadReq miss cycles 1011system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17629499 # number of UpgradeReq miss cycles 1012system.cpu.l2cache.UpgradeReq_miss_latency::total 17629499 # number of UpgradeReq miss cycles 1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6849048000 # number of ReadExReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::total 6849048000 # number of ReadExReq miss cycles 1015system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3729000 # number of demand (read+write) miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 431500 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.inst 993413500 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::cpu.data 9248421497 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.demand_miss_latency::total 10245995497 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3729000 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 431500 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::cpu.inst 993413500 # number of overall miss cycles 1023system.cpu.l2cache.overall_miss_latency::cpu.data 9248421497 # number of overall miss cycles 1024system.cpu.l2cache.overall_miss_latency::total 10245995497 # number of overall miss cycles 1025system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103826 # number of ReadReq accesses(hits+misses) 1026system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7660 # number of ReadReq accesses(hits+misses) 1027system.cpu.l2cache.ReadReq_accesses::cpu.inst 1053283 # number of ReadReq accesses(hits+misses) 1028system.cpu.l2cache.ReadReq_accesses::cpu.data 1373200 # number of ReadReq accesses(hits+misses) 1029system.cpu.l2cache.ReadReq_accesses::total 2537969 # number of ReadReq accesses(hits+misses) 1030system.cpu.l2cache.Writeback_accesses::writebacks 1599830 # number of Writeback accesses(hits+misses) 1031system.cpu.l2cache.Writeback_accesses::total 1599830 # number of Writeback accesses(hits+misses) 1032system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4212 # number of UpgradeReq accesses(hits+misses) 1033system.cpu.l2cache.UpgradeReq_accesses::total 4212 # number of UpgradeReq accesses(hits+misses) 1034system.cpu.l2cache.ReadExReq_accesses::cpu.data 288310 # number of ReadExReq accesses(hits+misses) 1035system.cpu.l2cache.ReadExReq_accesses::total 288310 # number of ReadExReq accesses(hits+misses) 1036system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103826 # number of demand (read+write) accesses 1037system.cpu.l2cache.demand_accesses::cpu.itb.walker 7660 # number of demand (read+write) accesses 1038system.cpu.l2cache.demand_accesses::cpu.inst 1053283 # number of demand (read+write) accesses 1039system.cpu.l2cache.demand_accesses::cpu.data 1661510 # number of demand (read+write) accesses 1040system.cpu.l2cache.demand_accesses::total 2826279 # number of demand (read+write) accesses 1041system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103826 # number of overall (read+write) accesses 1042system.cpu.l2cache.overall_accesses::cpu.itb.walker 7660 # number of overall (read+write) accesses 1043system.cpu.l2cache.overall_accesses::cpu.inst 1053283 # number of overall (read+write) accesses 1044system.cpu.l2cache.overall_accesses::cpu.data 1661510 # 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number of overall MSHR miss cycles 1139system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7060480254 # number of overall MSHR miss cycles 1140system.cpu.l2cache.overall_mshr_miss_latency::total 7844369169 # number of overall MSHR miss cycles 1141system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89188692000 # number of ReadReq MSHR uncacheable cycles 1142system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89188692000 # number of ReadReq MSHR uncacheable cycles 1143system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2310744000 # number of WriteReq MSHR uncacheable cycles 1144system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2310744000 # number of WriteReq MSHR uncacheable cycles 1145system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91499436000 # number of overall MSHR uncacheable cycles 1146system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91499436000 # number of overall MSHR uncacheable cycles 1147system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000472 # mshr miss rate for ReadReq accesses 1148system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000783 # mshr miss rate for ReadReq accesses 1149system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for ReadReq accesses 1150system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026781 # mshr miss rate for ReadReq accesses 1151system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021145 # mshr miss rate for ReadReq accesses 1152system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.920228 # mshr miss rate for UpgradeReq accesses 1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.920228 # mshr miss rate for UpgradeReq accesses 1154system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463213 # mshr miss rate for ReadExReq accesses 1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463213 # mshr miss rate for ReadExReq accesses 1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000472 # mshr miss rate for demand accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000783 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for demand accesses 1159system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102512 # mshr miss rate for demand accesses 1160system.cpu.l2cache.demand_mshr_miss_rate::total 0.066241 # mshr miss rate for demand accesses 1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000472 # mshr miss rate for overall accesses 1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000783 # mshr miss rate for overall accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for overall accesses 1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102512 # mshr miss rate for overall accesses 1165system.cpu.l2cache.overall_mshr_miss_rate::total 0.066241 # mshr miss rate for overall accesses 1166system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 63338.591837 # average ReadReq mshr miss latency 1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 59001.833333 # average ReadReq mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46357.666350 # average ReadReq mshr miss latency 1169system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52655.621547 # average ReadReq mshr miss latency 1170system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50690.419502 # average ReadReq mshr miss latency 1171system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10287.887513 # average UpgradeReq mshr miss latency 1172system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10287.887513 # average UpgradeReq mshr miss latency 1173system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38368.068020 # average ReadExReq mshr miss latency 1174system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38368.068020 # average ReadExReq mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 63338.591837 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 59001.833333 # average overall mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46357.666350 # average overall mshr miss latency 1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41452.988428 # average overall mshr miss latency 1179system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41900.324061 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 63338.591837 # average overall mshr miss latency 1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 59001.833333 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46357.666350 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41452.988428 # average overall mshr miss latency 1184system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41900.324061 # average overall mshr miss latency | 1119system.cpu.l2cache.overall_mshr_misses::cpu.inst 16767 # number of overall MSHR misses 1120system.cpu.l2cache.overall_mshr_misses::cpu.data 169995 # number of overall MSHR misses 1121system.cpu.l2cache.overall_mshr_misses::total 186815 # number of overall MSHR misses 1122system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2640091 # number of ReadReq MSHR miss cycles 1123system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 634512 # number of ReadReq MSHR miss cycles 1124system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 794953055 # number of ReadReq MSHR miss cycles 1125system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1935935400 # number of ReadReq MSHR miss cycles 1126system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2734163058 # number of ReadReq MSHR miss cycles 1127system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 40037376 # number of UpgradeReq MSHR miss cycles 1128system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 40037376 # number of UpgradeReq MSHR miss cycles 1129system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5118804681 # number of ReadExReq MSHR miss cycles 1130system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5118804681 # number of ReadExReq MSHR miss cycles 1131system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2640091 # number of demand (read+write) MSHR miss cycles 1132system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 634512 # number of demand (read+write) MSHR miss cycles 1133system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 794953055 # number of demand (read+write) MSHR miss cycles 1134system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7054740081 # number of demand (read+write) MSHR miss cycles 1135system.cpu.l2cache.demand_mshr_miss_latency::total 7852967739 # number of demand (read+write) MSHR miss cycles 1136system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2640091 # number of overall MSHR miss cycles 1137system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 634512 # number of overall MSHR miss cycles 1138system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 794953055 # number of overall MSHR miss cycles 1139system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7054740081 # number of overall MSHR miss cycles 1140system.cpu.l2cache.overall_mshr_miss_latency::total 7852967739 # number of overall MSHR miss cycles 1141system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187414000 # number of ReadReq MSHR uncacheable cycles 1142system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187414000 # number of ReadReq MSHR uncacheable cycles 1143system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308511500 # number of WriteReq MSHR uncacheable cycles 1144system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308511500 # number of WriteReq MSHR uncacheable cycles 1145system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495925500 # number of overall MSHR uncacheable cycles 1146system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495925500 # number of overall MSHR uncacheable cycles 1147system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000465 # mshr miss rate for ReadReq accesses 1148system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000789 # mshr miss rate for ReadReq accesses 1149system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for ReadReq accesses 1150system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026761 # mshr miss rate for ReadReq accesses 1151system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021116 # mshr miss rate for ReadReq accesses 1152system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.921494 # mshr miss rate for UpgradeReq accesses 1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.921494 # mshr miss rate for UpgradeReq accesses 1154system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459120 # mshr miss rate for ReadExReq accesses 1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459120 # mshr miss rate for ReadExReq accesses 1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000465 # mshr miss rate for demand accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000789 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for demand accesses 1159system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102241 # mshr miss rate for demand accesses 1160system.cpu.l2cache.demand_mshr_miss_rate::total 0.066103 # mshr miss rate for demand accesses 1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000465 # mshr miss rate for overall accesses 1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000789 # mshr miss rate for overall accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for overall accesses 1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102241 # mshr miss rate for overall accesses 1165system.cpu.l2cache.overall_mshr_miss_rate::total 0.066103 # mshr miss rate for overall accesses 1166system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average ReadReq mshr miss latency 1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 105752 # average ReadReq mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47411.764478 # average ReadReq mshr miss latency 1169system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52710.068613 # average ReadReq mshr miss latency 1170system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51060.040674 # average ReadReq mshr miss latency 1171system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10273.896844 # average UpgradeReq mshr miss latency 1172system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10273.896844 # average UpgradeReq mshr miss latency 1173system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38410.144154 # average ReadExReq mshr miss latency 1174system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38410.144154 # average ReadExReq mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 105752 # average overall mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47411.764478 # average overall mshr miss latency 1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41499.691644 # average overall mshr miss latency 1179system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42036.066370 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average overall mshr miss latency 1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 105752 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47411.764478 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41499.691644 # average overall mshr miss latency 1184system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42036.066370 # average overall mshr miss latency |
| 1185system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1186system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1187system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1188system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1189system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1190system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1191system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1192system.cpu.kern.inst.arm 0 # number of arm instructions executed 1193system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1194 1195---------- End Simulation Statistics ---------- | 1185system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1186system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1187system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1188system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1189system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1190system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1191system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1192system.cpu.kern.inst.arm 0 # number of arm instructions executed 1193system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1194 1195---------- End Simulation Statistics ---------- |