Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 5.132866 # Number of seconds simulated
4sim_ticks 5132866386000 # Number of ticks simulated
5final_tick 5132866386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 5.132790 # Number of seconds simulated
4sim_ticks 5132789913000 # Number of ticks simulated
5final_tick 5132789913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 195837 # Simulator instruction rate (inst/s)
8host_op_rate 387119 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2464119438 # Simulator tick rate (ticks/s)
10host_mem_usage 403620 # Number of bytes of host memory used
11host_seconds 2083.04 # Real time elapsed on the host
12sim_insts 407937545 # Number of instructions simulated
13sim_ops 806384911 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2474752 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 1081536 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 10883712 # Number of bytes read from this memory
19system.physmem.bytes_read::total 14443712 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 1081536 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 1081536 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 9597376 # Number of bytes written to this memory
23system.physmem.bytes_written::total 9597376 # Number of bytes written to this memory
24system.physmem.num_reads::pc.south_bridge.ide 38668 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.inst 16899 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.data 170058 # Number of read requests responded to by this memory
29system.physmem.num_reads::total 225683 # Number of read requests responded to by this memory
30system.physmem.num_writes::writebacks 149959 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 149959 # Number of write requests responded to by this memory
32system.physmem.bw_read::pc.south_bridge.ide 482138 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.inst 210708 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.data 2120397 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::total 2813966 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_inst_read::cpu.inst 210708 # Instruction read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::total 210708 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_write::writebacks 1869789 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_write::total 1869789 # Write bandwidth from this memory (bytes/s)
42system.physmem.bw_total::writebacks 1869789 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::pc.south_bridge.ide 482138 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.inst 210708 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.data 2120397 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 4683755 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.readReqs 225683 # Total number of read requests seen
50system.physmem.writeReqs 149959 # Total number of write requests seen
51system.physmem.cpureqs 389568 # Reqs generatd by CPU via cache - shady
52system.physmem.bytesRead 14443712 # Total number of bytes read from memory
53system.physmem.bytesWritten 9597376 # Total number of bytes written to memory
54system.physmem.bytesConsumedRd 14443712 # bytesRead derated as per pkt->getSize()
55system.physmem.bytesConsumedWr 9597376 # bytesWritten derated as per pkt->getSize()
56system.physmem.servicedByWrQ 89 # Number of read reqs serviced by write Q
57system.physmem.neitherReadNorWrite 3846 # Reqs where no action is needed
58system.physmem.perBankRdReqs::0 13634 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::1 14670 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::2 13077 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::3 15197 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::4 13869 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::5 14751 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::6 12899 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::7 14175 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::8 13762 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::9 14847 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::10 14072 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::11 14685 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::12 13809 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::13 14671 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::14 12718 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::15 14758 # Track reads on a per bank basis
74system.physmem.perBankWrReqs::0 8656 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::1 10128 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::2 8462 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::3 10559 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::4 9080 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::5 10102 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::6 8151 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::7 9598 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::8 8927 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::9 10197 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::10 9260 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::11 9975 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::12 8913 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::13 9909 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::14 8139 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::15 9903 # Track writes on a per bank basis

7host_inst_rate 148899 # Simulator instruction rate (inst/s)
8host_op_rate 294332 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1873578722 # Simulator tick rate (ticks/s)
10host_mem_usage 406892 # Number of bytes of host memory used
11host_seconds 2739.56 # Real time elapsed on the host
12sim_insts 407917143 # Number of instructions simulated
13sim_ops 806342485 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2491072 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 1075264 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 10835456 # Number of bytes read from this memory
19system.physmem.bytes_read::total 14405312 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 1075264 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 1075264 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 9578880 # Number of bytes written to this memory
23system.physmem.bytes_written::total 9578880 # Number of bytes written to this memory
24system.physmem.num_reads::pc.south_bridge.ide 38923 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.inst 16801 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.data 169304 # Number of read requests responded to by this memory
29system.physmem.num_reads::total 225083 # Number of read requests responded to by this memory
30system.physmem.num_writes::writebacks 149670 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 149670 # Number of write requests responded to by this memory
32system.physmem.bw_read::pc.south_bridge.ide 485325 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.dtb.walker 599 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.inst 209489 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.data 2111027 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::total 2806527 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_inst_read::cpu.inst 209489 # Instruction read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::total 209489 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_write::writebacks 1866213 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_write::total 1866213 # Write bandwidth from this memory (bytes/s)
42system.physmem.bw_total::writebacks 1866213 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::pc.south_bridge.ide 485325 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 599 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.inst 209489 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.data 2111027 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 4672740 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.readReqs 225083 # Total number of read requests seen
50system.physmem.writeReqs 149670 # Total number of write requests seen
51system.physmem.cpureqs 388719 # Reqs generatd by CPU via cache - shady
52system.physmem.bytesRead 14405312 # Total number of bytes read from memory
53system.physmem.bytesWritten 9578880 # Total number of bytes written to memory
54system.physmem.bytesConsumedRd 14405312 # bytesRead derated as per pkt->getSize()
55system.physmem.bytesConsumedWr 9578880 # bytesWritten derated as per pkt->getSize()
56system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
57system.physmem.neitherReadNorWrite 4102 # Reqs where no action is needed
58system.physmem.perBankRdReqs::0 13654 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::1 14948 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::2 12919 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::3 15106 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::4 13327 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::5 14545 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::6 13326 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::7 14277 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::8 13582 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::9 14874 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::10 14098 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::11 14962 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::12 13282 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::13 14549 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::14 12658 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::15 14901 # Track reads on a per bank basis
74system.physmem.perBankWrReqs::0 8775 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::1 10390 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::2 8311 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::3 10526 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::4 8491 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::5 9845 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::6 8546 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::7 9654 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::8 8818 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::9 10118 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::10 9236 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::11 10295 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::12 8519 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::13 9932 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::14 8008 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::15 10206 # Track writes on a per bank basis

90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry

91system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
92system.physmem.totGap 5132866305000 # Total gap between requests

91system.physmem.numWrRetry 49 # Number of times wr buffer was full causing retry
92system.physmem.totGap 5132789860500 # Total gap between requests

93system.physmem.readPktSize::0 0 # Categorize read packet sizes
94system.physmem.readPktSize::1 0 # Categorize read packet sizes
95system.physmem.readPktSize::2 0 # Categorize read packet sizes
96system.physmem.readPktSize::3 0 # Categorize read packet sizes
97system.physmem.readPktSize::4 0 # Categorize read packet sizes
98system.physmem.readPktSize::5 0 # Categorize read packet sizes

99system.physmem.readPktSize::6 225683 # Categorize read packet sizes

99system.physmem.readPktSize::6 225083 # Categorize read packet sizes

100system.physmem.readPktSize::7 0 # Categorize read packet sizes
101system.physmem.readPktSize::8 0 # Categorize read packet sizes
102system.physmem.writePktSize::0 0 # categorize write packet sizes
103system.physmem.writePktSize::1 0 # categorize write packet sizes
104system.physmem.writePktSize::2 0 # categorize write packet sizes
105system.physmem.writePktSize::3 0 # categorize write packet sizes
106system.physmem.writePktSize::4 0 # categorize write packet sizes
107system.physmem.writePktSize::5 0 # categorize write packet sizes

108system.physmem.writePktSize::6 149959 # categorize write packet sizes

108system.physmem.writePktSize::6 149719 # categorize write packet sizes

109system.physmem.writePktSize::7 0 # categorize write packet sizes
110system.physmem.writePktSize::8 0 # categorize write packet sizes
111system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
112system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
113system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
114system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
115system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
116system.physmem.neitherpktsize::5 0 # categorize neither packet sizes

117system.physmem.neitherpktsize::6 3846 # categorize neither packet sizes

117system.physmem.neitherpktsize::6 4102 # categorize neither packet sizes

118system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
119system.physmem.neitherpktsize::8 0 # categorize neither packet sizes

120system.physmem.rdQLenPdf::0 177236 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::1 21627 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::2 8107 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::3 2832 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::4 2887 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::5 2147 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::6 1315 # What read queue length does an incoming req see

120system.physmem.rdQLenPdf::0 176543 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::1 21526 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::2 8299 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::3 2898 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::4 2824 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::5 2164 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see

127system.physmem.rdQLenPdf::7 1517 # What read queue length does an incoming req see

128system.physmem.rdQLenPdf::8 1334 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::9 1287 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::10 1161 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::11 1104 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::12 1045 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::13 846 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::15 235 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::16 188 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::17 132 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see

128system.physmem.rdQLenPdf::8 1378 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::10 1195 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::11 1112 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::13 826 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::14 390 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::15 237 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see

142system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see

153system.physmem.wrQLenPdf::0 5741 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::1 6370 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::2 6482 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::3 6504 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::4 6513 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::5 6518 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::6 6520 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::7 6520 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::8 6520 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::9 6520 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::10 6520 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::11 6520 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::12 6520 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::13 6520 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::14 6520 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::15 6520 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::16 6520 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::17 6520 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::18 6520 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::19 6520 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::20 6520 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::21 6520 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::22 6519 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::23 779 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::24 150 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::25 38 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see

153system.physmem.wrQLenPdf::0 5656 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::1 6362 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::2 6464 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::3 6486 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::4 6500 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::5 6503 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::6 6505 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::7 6506 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::8 6506 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::9 6507 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::10 6507 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::11 6507 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::12 6507 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::13 6507 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::14 6507 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::15 6507 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::16 6507 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::17 6507 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::18 6507 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::19 6507 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::20 6507 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::21 6507 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::22 6507 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::23 852 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::24 146 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see

185system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

186system.physmem.totQLat 3339090244 # Total cycles spent in queuing delays
187system.physmem.totMemAccLat 7604182244 # Sum of mem lat for all requests
188system.physmem.totBusLat 902376000 # Total cycles spent in databus access
189system.physmem.totBankLat 3362716000 # Total cycles spent in bank access
190system.physmem.avgQLat 14801.33 # Average queueing delay per request
191system.physmem.avgBankLat 14906.05 # Average bank access latency per request

186system.physmem.totQLat 3269589754 # Total cycles spent in queuing delays
187system.physmem.totMemAccLat 7518085754 # Sum of mem lat for all requests
188system.physmem.totBusLat 900032000 # Total cycles spent in databus access
189system.physmem.totBankLat 3348464000 # Total cycles spent in bank access
190system.physmem.avgQLat 14530.99 # Average queueing delay per request
191system.physmem.avgBankLat 14881.53 # Average bank access latency per request

192system.physmem.avgBusLat 4000.00 # Average bus latency per request

193system.physmem.avgMemAccLat 33707.38 # Average memory access latency

193system.physmem.avgMemAccLat 33412.53 # Average memory access latency

194system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s
195system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s
196system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s
197system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s
198system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
199system.physmem.busUtil 0.03 # Data bus utilization in percentage
200system.physmem.avgRdQLen 0.00 # Average read queue length over time

201system.physmem.avgWrQLen 10.11 # Average write queue length over time
202system.physmem.readRowHits 199074 # Number of row buffer hits during reads
203system.physmem.writeRowHits 88511 # Number of row buffer hits during writes
204system.physmem.readRowHitRate 88.24 # Row buffer hit rate for reads
205system.physmem.writeRowHitRate 59.02 # Row buffer hit rate for writes
206system.physmem.avgGap 13664250.28 # Average gap between requests
207system.iocache.replacements 47575 # number of replacements
208system.iocache.tagsinuse 0.103977 # Cycle average of tags in use

201system.physmem.avgWrQLen 11.37 # Average write queue length over time
202system.physmem.readRowHits 198566 # Number of row buffer hits during reads
203system.physmem.writeRowHits 87960 # Number of row buffer hits during writes
204system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads
205system.physmem.writeRowHitRate 58.77 # Row buffer hit rate for writes
206system.physmem.avgGap 13696461.03 # Average gap between requests
207system.iocache.replacements 47576 # number of replacements
208system.iocache.tagsinuse 0.103964 # Cycle average of tags in use

209system.iocache.total_refs 0 # Total number of references to valid blocks.

210system.iocache.sampled_refs 47591 # Sample count of references to valid blocks.

210system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.

211system.iocache.avg_refs 0 # Average number of references to valid blocks.

212system.iocache.warmup_cycle 4991894063000 # Cycle when the warmup percentage was hit.
213system.iocache.occ_blocks::pc.south_bridge.ide 0.103977 # Average occupied blocks per requestor
214system.iocache.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy
215system.iocache.occ_percent::total 0.006499 # Average percentage of cache occupancy
216system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
217system.iocache.ReadReq_misses::total 910 # number of ReadReq misses

212system.iocache.warmup_cycle 4991828572000 # Cycle when the warmup percentage was hit.
213system.iocache.occ_blocks::pc.south_bridge.ide 0.103964 # Average occupied blocks per requestor
214system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy
215system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy
216system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
217system.iocache.ReadReq_misses::total 911 # number of ReadReq misses

218system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
219system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses

220system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses
221system.iocache.demand_misses::total 47630 # number of demand (read+write) misses
222system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses
223system.iocache.overall_misses::total 47630 # number of overall misses
224system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143902932 # number of ReadReq miss cycles
225system.iocache.ReadReq_miss_latency::total 143902932 # number of ReadReq miss cycles
226system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9034164160 # number of WriteReq miss cycles
227system.iocache.WriteReq_miss_latency::total 9034164160 # number of WriteReq miss cycles
228system.iocache.demand_miss_latency::pc.south_bridge.ide 9178067092 # number of demand (read+write) miss cycles
229system.iocache.demand_miss_latency::total 9178067092 # number of demand (read+write) miss cycles
230system.iocache.overall_miss_latency::pc.south_bridge.ide 9178067092 # number of overall miss cycles
231system.iocache.overall_miss_latency::total 9178067092 # number of overall miss cycles
232system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
233system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)

220system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
221system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
222system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
223system.iocache.overall_misses::total 47631 # number of overall misses
224system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146267932 # number of ReadReq miss cycles
225system.iocache.ReadReq_miss_latency::total 146267932 # number of ReadReq miss cycles
226system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8962382160 # number of WriteReq miss cycles
227system.iocache.WriteReq_miss_latency::total 8962382160 # number of WriteReq miss cycles
228system.iocache.demand_miss_latency::pc.south_bridge.ide 9108650092 # number of demand (read+write) miss cycles
229system.iocache.demand_miss_latency::total 9108650092 # number of demand (read+write) miss cycles
230system.iocache.overall_miss_latency::pc.south_bridge.ide 9108650092 # number of overall miss cycles
231system.iocache.overall_miss_latency::total 9108650092 # number of overall miss cycles
232system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
233system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)

234system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
235system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)

236system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses
237system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses
238system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses
239system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses

236system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
237system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
238system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
239system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses

240system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
241system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
242system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
243system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
244system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
245system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
246system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
247system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses

248system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158135.090110 # average ReadReq miss latency
249system.iocache.ReadReq_avg_miss_latency::total 158135.090110 # average ReadReq miss latency
250system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 193368.239726 # average WriteReq miss latency
251system.iocache.WriteReq_avg_miss_latency::total 193368.239726 # average WriteReq miss latency
252system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency
253system.iocache.demand_avg_miss_latency::total 192695.089062 # average overall miss latency
254system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency
255system.iocache.overall_avg_miss_latency::total 192695.089062 # average overall miss latency
256system.iocache.blocked_cycles::no_mshrs 60674 # number of cycles access was blocked

248system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160557.554336 # average ReadReq miss latency
249system.iocache.ReadReq_avg_miss_latency::total 160557.554336 # average ReadReq miss latency
250system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191831.809932 # average WriteReq miss latency
251system.iocache.WriteReq_avg_miss_latency::total 191831.809932 # average WriteReq miss latency
252system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency
253system.iocache.demand_avg_miss_latency::total 191233.652285 # average overall miss latency
254system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency
255system.iocache.overall_avg_miss_latency::total 191233.652285 # average overall miss latency
256system.iocache.blocked_cycles::no_mshrs 51554 # number of cycles access was blocked

257system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked

258system.iocache.blocked::no_mshrs 7530 # number of cycles access was blocked

258system.iocache.blocked::no_mshrs 7256 # number of cycles access was blocked

259system.iocache.blocked::no_targets 0 # number of cycles access was blocked

260system.iocache.avg_blocked_cycles::no_mshrs 8.057636 # average number of cycles each access was blocked

260system.iocache.avg_blocked_cycles::no_mshrs 7.105017 # average number of cycles each access was blocked

261system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
262system.iocache.fast_writes 0 # number of fast writes performed
263system.iocache.cache_copies 0 # number of cache copies performed
264system.iocache.writebacks::writebacks 46667 # number of writebacks
265system.iocache.writebacks::total 46667 # number of writebacks

266system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
267system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses

266system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
267system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses

268system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
269system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses

270system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses
271system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses
272system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses
273system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses
274system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96552990 # number of ReadReq MSHR miss cycles
275system.iocache.ReadReq_mshr_miss_latency::total 96552990 # number of ReadReq MSHR miss cycles
276system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6602427338 # number of WriteReq MSHR miss cycles
277system.iocache.WriteReq_mshr_miss_latency::total 6602427338 # number of WriteReq MSHR miss cycles
278system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of demand (read+write) MSHR miss cycles
279system.iocache.demand_mshr_miss_latency::total 6698980328 # number of demand (read+write) MSHR miss cycles
280system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of overall MSHR miss cycles
281system.iocache.overall_mshr_miss_latency::total 6698980328 # number of overall MSHR miss cycles

270system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
271system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
272system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
273system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
274system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98865990 # number of ReadReq MSHR miss cycles
275system.iocache.ReadReq_mshr_miss_latency::total 98865990 # number of ReadReq MSHR miss cycles
276system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6530591975 # number of WriteReq MSHR miss cycles
277system.iocache.WriteReq_mshr_miss_latency::total 6530591975 # number of WriteReq MSHR miss cycles
278system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of demand (read+write) MSHR miss cycles
279system.iocache.demand_mshr_miss_latency::total 6629457965 # number of demand (read+write) MSHR miss cycles
280system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of overall MSHR miss cycles
281system.iocache.overall_mshr_miss_latency::total 6629457965 # number of overall MSHR miss cycles

282system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
283system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
284system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
285system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
286system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
287system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
288system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
289system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses

290system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106102.186813 # average ReadReq mshr miss latency
291system.iocache.ReadReq_avg_mshr_miss_latency::total 106102.186813 # average ReadReq mshr miss latency
292system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 141319.078296 # average WriteReq mshr miss latency
293system.iocache.WriteReq_avg_mshr_miss_latency::total 141319.078296 # average WriteReq mshr miss latency
294system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency
295system.iocache.demand_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency
296system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency
297system.iocache.overall_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency

290system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108524.687157 # average ReadReq mshr miss latency
291system.iocache.ReadReq_avg_mshr_miss_latency::total 108524.687157 # average ReadReq mshr miss latency
292system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139781.506314 # average WriteReq mshr miss latency
293system.iocache.WriteReq_avg_mshr_miss_latency::total 139781.506314 # average WriteReq mshr miss latency
294system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency
295system.iocache.demand_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency
296system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency
297system.iocache.overall_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency

298system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
299system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
300system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
301system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
302system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
303system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
304system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
305system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
306system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
307system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
308system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
309system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
310system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.

311system.cpu.numCycles 448858777 # number of cpu cycles simulated

311system.cpu.numCycles 447650408 # number of cpu cycles simulated

312system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
313system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

314system.cpu.BPredUnit.lookups 86511552 # Number of BP lookups
315system.cpu.BPredUnit.condPredicted 86511552 # Number of conditional branches predicted
316system.cpu.BPredUnit.condIncorrect 1187540 # Number of conditional branches incorrect
317system.cpu.BPredUnit.BTBLookups 81908216 # Number of BTB lookups
318system.cpu.BPredUnit.BTBHits 79448034 # Number of BTB hits

314system.cpu.BPredUnit.lookups 86252473 # Number of BP lookups
315system.cpu.BPredUnit.condPredicted 86252473 # Number of conditional branches predicted
316system.cpu.BPredUnit.condIncorrect 1112360 # Number of conditional branches incorrect
317system.cpu.BPredUnit.BTBLookups 81440812 # Number of BTB lookups
318system.cpu.BPredUnit.BTBHits 79250759 # Number of BTB hits

319system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
320system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
321system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.

322system.cpu.fetch.icacheStallCycles 28014488 # Number of cycles fetch is stalled on an Icache miss
323system.cpu.fetch.Insts 427358956 # Number of instructions fetch has processed
324system.cpu.fetch.Branches 86511552 # Number of branches that fetch encountered
325system.cpu.fetch.predictedBranches 79448034 # Number of branches that fetch has predicted taken
326system.cpu.fetch.Cycles 164036376 # Number of cycles fetch has run and was not squashing or blocked
327system.cpu.fetch.SquashCycles 5076610 # Number of cycles fetch has spent squashing
328system.cpu.fetch.TlbCycles 125788 # Number of cycles fetch has spent waiting for tlb
329system.cpu.fetch.BlockedCycles 62760738 # Number of cycles fetch has spent blocked
330system.cpu.fetch.MiscStallCycles 36372 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
331system.cpu.fetch.PendingTrapStallCycles 61645 # Number of stall cycles due to pending traps
332system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR
333system.cpu.fetch.CacheLines 9269515 # Number of cache lines fetched
334system.cpu.fetch.IcacheSquashes 518863 # Number of outstanding Icache misses that were squashed
335system.cpu.fetch.ItlbSquashes 3783 # Number of outstanding ITLB misses that were squashed
336system.cpu.fetch.rateDist::samples 258886753 # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::mean 3.258580 # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::stdev 3.418024 # Number of instructions fetched each cycle (Total)

322system.cpu.fetch.icacheStallCycles 27455337 # Number of cycles fetch is stalled on an Icache miss
323system.cpu.fetch.Insts 426133339 # Number of instructions fetch has processed
324system.cpu.fetch.Branches 86252473 # Number of branches that fetch encountered
325system.cpu.fetch.predictedBranches 79250759 # Number of branches that fetch has predicted taken
326system.cpu.fetch.Cycles 163637491 # Number of cycles fetch has run and was not squashing or blocked
327system.cpu.fetch.SquashCycles 4749598 # Number of cycles fetch has spent squashing
328system.cpu.fetch.TlbCycles 117040 # Number of cycles fetch has spent waiting for tlb
329system.cpu.fetch.BlockedCycles 62764723 # Number of cycles fetch has spent blocked
330system.cpu.fetch.MiscStallCycles 36355 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
331system.cpu.fetch.PendingTrapStallCycles 51011 # Number of stall cycles due to pending traps
332system.cpu.fetch.IcacheWaitRetryStallCycles 275 # Number of stall cycles due to full MSHR
333system.cpu.fetch.CacheLines 9043493 # Number of cache lines fetched
334system.cpu.fetch.IcacheSquashes 487667 # Number of outstanding Icache misses that were squashed
335system.cpu.fetch.ItlbSquashes 3497 # Number of outstanding ITLB misses that were squashed
336system.cpu.fetch.rateDist::samples 257661797 # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::mean 3.265027 # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::stdev 3.418216 # Number of instructions fetched each cycle (Total)

339system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

340system.cpu.fetch.rateDist::0 95280988 36.80% 36.80% # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::1 1593075 0.62% 37.42% # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.rateDist::2 71954141 27.79% 65.21% # Number of instructions fetched each cycle (Total)
343system.cpu.fetch.rateDist::3 971709 0.38% 65.59% # Number of instructions fetched each cycle (Total)
344system.cpu.fetch.rateDist::4 1620643 0.63% 66.21% # Number of instructions fetched each cycle (Total)
345system.cpu.fetch.rateDist::5 2451488 0.95% 67.16% # Number of instructions fetched each cycle (Total)
346system.cpu.fetch.rateDist::6 1122205 0.43% 67.59% # Number of instructions fetched each cycle (Total)
347system.cpu.fetch.rateDist::7 1426657 0.55% 68.15% # Number of instructions fetched each cycle (Total)
348system.cpu.fetch.rateDist::8 82465847 31.85% 100.00% # Number of instructions fetched each cycle (Total)

340system.cpu.fetch.rateDist::0 94448905 36.66% 36.66% # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::1 1567012 0.61% 37.26% # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.rateDist::2 71922195 27.91% 65.18% # Number of instructions fetched each cycle (Total)
343system.cpu.fetch.rateDist::3 935544 0.36% 65.54% # Number of instructions fetched each cycle (Total)
344system.cpu.fetch.rateDist::4 1602565 0.62% 66.16% # Number of instructions fetched each cycle (Total)
345system.cpu.fetch.rateDist::5 2433530 0.94% 67.11% # Number of instructions fetched each cycle (Total)
346system.cpu.fetch.rateDist::6 1078893 0.42% 67.53% # Number of instructions fetched each cycle (Total)
347system.cpu.fetch.rateDist::7 1381790 0.54% 68.06% # Number of instructions fetched each cycle (Total)
348system.cpu.fetch.rateDist::8 82291363 31.94% 100.00% # Number of instructions fetched each cycle (Total)

349system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
350system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
351system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

352system.cpu.fetch.rateDist::total 258886753 # Number of instructions fetched each cycle (Total)
353system.cpu.fetch.branchRate 0.192737 # Number of branch fetches per cycle
354system.cpu.fetch.rate 0.952101 # Number of inst fetches per cycle
355system.cpu.decode.IdleCycles 31742461 # Number of cycles decode is idle
356system.cpu.decode.BlockedCycles 60237035 # Number of cycles decode is blocked
357system.cpu.decode.RunCycles 159788942 # Number of cycles decode is running
358system.cpu.decode.UnblockCycles 3267328 # Number of cycles decode is unblocking
359system.cpu.decode.SquashCycles 3850987 # Number of cycles decode is squashing
360system.cpu.decode.DecodedInsts 840289565 # Number of instructions handled by decode
361system.cpu.decode.SquashedInsts 1231 # Number of squashed instructions handled by decode
362system.cpu.rename.SquashCycles 3850987 # Number of cycles rename is squashing
363system.cpu.rename.IdleCycles 34512001 # Number of cycles rename is idle
364system.cpu.rename.BlockCycles 37373607 # Number of cycles rename is blocking
365system.cpu.rename.serializeStallCycles 10738522 # count of cycles rename stalled for serializing inst
366system.cpu.rename.RunCycles 159961860 # Number of cycles rename is running
367system.cpu.rename.UnblockCycles 12449776 # Number of cycles rename is unblocking
368system.cpu.rename.RenamedInsts 836423195 # Number of instructions processed by rename
369system.cpu.rename.ROBFullEvents 19229 # Number of times rename has blocked due to ROB full
370system.cpu.rename.IQFullEvents 5893988 # Number of times rename has blocked due to IQ full
371system.cpu.rename.LSQFullEvents 4723761 # Number of times rename has blocked due to LSQ full
372system.cpu.rename.FullRegisterEvents 7727 # Number of times there has been no free registers
373system.cpu.rename.RenamedOperands 998196840 # Number of destination operands rename has renamed
374system.cpu.rename.RenameLookups 1816454110 # Number of register rename lookups that rename has made
375system.cpu.rename.int_rename_lookups 1816453462 # Number of integer rename lookups
376system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups
377system.cpu.rename.CommittedMaps 964349930 # Number of HB maps that are committed
378system.cpu.rename.UndoneMaps 33846903 # Number of HB maps that are undone due to squashing
379system.cpu.rename.serializingInsts 467065 # count of serializing insts renamed
380system.cpu.rename.tempSerializingInsts 474165 # count of temporary serializing insts renamed
381system.cpu.rename.skidInsts 28825004 # count of insts added to the skid buffer
382system.cpu.memDep0.insertedLoads 17330743 # Number of loads inserted to the mem dependence unit.
383system.cpu.memDep0.insertedStores 10271430 # Number of stores inserted to the mem dependence unit.
384system.cpu.memDep0.conflictingLoads 1207742 # Number of conflicting loads.
385system.cpu.memDep0.conflictingStores 944493 # Number of conflicting stores.
386system.cpu.iq.iqInstsAdded 829965735 # Number of instructions added to the IQ (excludes non-spec)
387system.cpu.iq.iqNonSpecInstsAdded 1256270 # Number of non-speculative instructions added to the IQ
388system.cpu.iq.iqInstsIssued 824405499 # Number of instructions issued
389system.cpu.iq.iqSquashedInstsIssued 167750 # Number of squashed instructions issued
390system.cpu.iq.iqSquashedInstsExamined 23821216 # Number of squashed instructions iterated over during squash; mainly for profiling
391system.cpu.iq.iqSquashedOperandsExamined 36350655 # Number of squashed operands that are examined and possibly removed from graph
392system.cpu.iq.iqSquashedNonSpecRemoved 203504 # Number of squashed non-spec instructions that were removed
393system.cpu.iq.issued_per_cycle::samples 258886753 # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::mean 3.184425 # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::stdev 2.385403 # Number of insts issued each cycle

352system.cpu.fetch.rateDist::total 257661797 # Number of instructions fetched each cycle (Total)
353system.cpu.fetch.branchRate 0.192678 # Number of branch fetches per cycle
354system.cpu.fetch.rate 0.951933 # Number of inst fetches per cycle
355system.cpu.decode.IdleCycles 31146269 # Number of cycles decode is idle
356system.cpu.decode.BlockedCycles 60227421 # Number of cycles decode is blocked
357system.cpu.decode.RunCycles 159444515 # Number of cycles decode is running
358system.cpu.decode.UnblockCycles 3244027 # Number of cycles decode is unblocking
359system.cpu.decode.SquashCycles 3599565 # Number of cycles decode is squashing
360system.cpu.decode.DecodedInsts 838112106 # Number of instructions handled by decode
361system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode
362system.cpu.rename.SquashCycles 3599565 # Number of cycles rename is squashing
363system.cpu.rename.IdleCycles 33887749 # Number of cycles rename is idle
364system.cpu.rename.BlockCycles 37302672 # Number of cycles rename is blocking
365system.cpu.rename.serializeStallCycles 10848429 # count of cycles rename stalled for serializing inst
366system.cpu.rename.RunCycles 159621170 # Number of cycles rename is running
367system.cpu.rename.UnblockCycles 12402212 # Number of cycles rename is unblocking
368system.cpu.rename.RenamedInsts 834448767 # Number of instructions processed by rename
369system.cpu.rename.ROBFullEvents 20383 # Number of times rename has blocked due to ROB full
370system.cpu.rename.IQFullEvents 5810954 # Number of times rename has blocked due to IQ full
371system.cpu.rename.LSQFullEvents 4749020 # Number of times rename has blocked due to LSQ full
372system.cpu.rename.FullRegisterEvents 7935 # Number of times there has been no free registers
373system.cpu.rename.RenamedOperands 996003699 # Number of destination operands rename has renamed
374system.cpu.rename.RenameLookups 1811552283 # Number of register rename lookups that rename has made
375system.cpu.rename.int_rename_lookups 1811551779 # Number of integer rename lookups
376system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups
377system.cpu.rename.CommittedMaps 964308271 # Number of HB maps that are committed
378system.cpu.rename.UndoneMaps 31695421 # Number of HB maps that are undone due to squashing
379system.cpu.rename.serializingInsts 457655 # count of serializing insts renamed
380system.cpu.rename.tempSerializingInsts 465271 # count of temporary serializing insts renamed
381system.cpu.rename.skidInsts 28736743 # count of insts added to the skid buffer
382system.cpu.memDep0.insertedLoads 17096853 # Number of loads inserted to the mem dependence unit.
383system.cpu.memDep0.insertedStores 10140380 # Number of stores inserted to the mem dependence unit.
384system.cpu.memDep0.conflictingLoads 1243307 # Number of conflicting loads.
385system.cpu.memDep0.conflictingStores 975146 # Number of conflicting stores.
386system.cpu.iq.iqInstsAdded 828306292 # Number of instructions added to the IQ (excludes non-spec)
387system.cpu.iq.iqNonSpecInstsAdded 1248163 # Number of non-speculative instructions added to the IQ
388system.cpu.iq.iqInstsIssued 823283697 # Number of instructions issued
389system.cpu.iq.iqSquashedInstsIssued 148415 # Number of squashed instructions issued
390system.cpu.iq.iqSquashedInstsExamined 22289625 # Number of squashed instructions iterated over during squash; mainly for profiling
391system.cpu.iq.iqSquashedOperandsExamined 33892420 # Number of squashed operands that are examined and possibly removed from graph
392system.cpu.iq.iqSquashedNonSpecRemoved 195525 # Number of squashed non-spec instructions that were removed
393system.cpu.iq.issued_per_cycle::samples 257661797 # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::mean 3.195211 # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::stdev 2.383294 # Number of insts issued each cycle

396system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

397system.cpu.iq.issued_per_cycle::0 72013044 27.82% 27.82% # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::1 15598777 6.03% 33.84% # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::2 10365143 4.00% 37.85% # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::3 7553925 2.92% 40.76% # Number of insts issued each cycle
401system.cpu.iq.issued_per_cycle::4 75959659 29.34% 70.10% # Number of insts issued each cycle
402system.cpu.iq.issued_per_cycle::5 3903196 1.51% 71.61% # Number of insts issued each cycle
403system.cpu.iq.issued_per_cycle::6 72545029 28.02% 99.63% # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::7 793969 0.31% 99.94% # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::8 154011 0.06% 100.00% # Number of insts issued each cycle

397system.cpu.iq.issued_per_cycle::0 71201357 27.63% 27.63% # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::1 15459797 6.00% 33.63% # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::2 10286150 3.99% 37.63% # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::3 7472850 2.90% 40.53% # Number of insts issued each cycle
401system.cpu.iq.issued_per_cycle::4 75924697 29.47% 69.99% # Number of insts issued each cycle
402system.cpu.iq.issued_per_cycle::5 3857138 1.50% 71.49% # Number of insts issued each cycle
403system.cpu.iq.issued_per_cycle::6 72522119 28.15% 99.64% # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::7 785654 0.30% 99.94% # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::8 152035 0.06% 100.00% # Number of insts issued each cycle

406system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
407system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
408system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

409system.cpu.iq.issued_per_cycle::total 258886753 # Number of insts issued each cycle

409system.cpu.iq.issued_per_cycle::total 257661797 # Number of insts issued each cycle

410system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

411system.cpu.iq.fu_full::IntAlu 353413 33.31% 33.31% # attempts to use FU when none available
412system.cpu.iq.fu_full::IntMult 0 0.00% 33.31% # attempts to use FU when none available
413system.cpu.iq.fu_full::IntDiv 0 0.00% 33.31% # attempts to use FU when none available
414system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.31% # attempts to use FU when none available
415system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.31% # attempts to use FU when none available
416system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.31% # attempts to use FU when none available
417system.cpu.iq.fu_full::FloatMult 0 0.00% 33.31% # attempts to use FU when none available
418system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.31% # attempts to use FU when none available
419system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.31% # attempts to use FU when none available
420system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.31% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.31% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.31% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.31% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.31% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.31% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdMult 0 0.00% 33.31% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.31% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdShift 0 0.00% 33.31% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.31% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.31% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.31% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.31% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.31% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.31% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.31% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.31% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.31% # attempts to use FU when none available
438system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.31% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.31% # attempts to use FU when none available
440system.cpu.iq.fu_full::MemRead 554407 52.25% 85.55% # attempts to use FU when none available
441system.cpu.iq.fu_full::MemWrite 153287 14.45% 100.00% # attempts to use FU when none available

411system.cpu.iq.fu_full::IntAlu 364358 34.12% 34.12% # attempts to use FU when none available
412system.cpu.iq.fu_full::IntMult 0 0.00% 34.12% # attempts to use FU when none available
413system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available
414system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available
415system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available
416system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available
417system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available
418system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available
419system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available
420system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available
438system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available
440system.cpu.iq.fu_full::MemRead 552545 51.74% 85.86% # attempts to use FU when none available
441system.cpu.iq.fu_full::MemWrite 150975 14.14% 100.00% # attempts to use FU when none available

442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available

444system.cpu.iq.FU_type_0::No_OpClass 307308 0.04% 0.04% # Type of FU issued
445system.cpu.iq.FU_type_0::IntAlu 796584719 96.63% 96.66% # Type of FU issued
446system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued
447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued
448system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued
449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued
450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued
451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued
452system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued
453system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued
454system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued
455system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued
474system.cpu.iq.FU_type_0::MemRead 18039231 2.19% 98.85% # Type of FU issued
475system.cpu.iq.FU_type_0::MemWrite 9474241 1.15% 100.00% # Type of FU issued

444system.cpu.iq.FU_type_0::No_OpClass 312887 0.04% 0.04% # Type of FU issued
445system.cpu.iq.FU_type_0::IntAlu 795710532 96.65% 96.69% # Type of FU issued
446system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
448system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued
450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued
451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued
452system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued
453system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued
454system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued
455system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
474system.cpu.iq.FU_type_0::MemRead 17869782 2.17% 98.86% # Type of FU issued
475system.cpu.iq.FU_type_0::MemWrite 9390496 1.14% 100.00% # Type of FU issued

476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

478system.cpu.iq.FU_type_0::total 824405499 # Type of FU issued
479system.cpu.iq.rate 1.836670 # Inst issue rate
480system.cpu.iq.fu_busy_cnt 1061107 # FU busy when requested
481system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst)
482system.cpu.iq.int_inst_queue_reads 1909060731 # Number of integer instruction queue reads
483system.cpu.iq.int_inst_queue_writes 855053110 # Number of integer instruction queue writes
484system.cpu.iq.int_inst_queue_wakeup_accesses 819712115 # Number of integer instruction queue wakeup accesses
485system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads
486system.cpu.iq.fp_inst_queue_writes 306 # Number of floating instruction queue writes
487system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
488system.cpu.iq.int_alu_accesses 825159176 # Number of integer alu accesses
489system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses
490system.cpu.iew.lsq.thread0.forwLoads 1650601 # Number of loads that had data forwarded from stores

478system.cpu.iq.FU_type_0::total 823283697 # Type of FU issued
479system.cpu.iq.rate 1.839122 # Inst issue rate
480system.cpu.iq.fu_busy_cnt 1067878 # FU busy when requested
481system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst)
482system.cpu.iq.int_inst_queue_reads 1905576298 # Number of integer instruction queue reads
483system.cpu.iq.int_inst_queue_writes 851854038 # Number of integer instruction queue writes
484system.cpu.iq.int_inst_queue_wakeup_accesses 818789401 # Number of integer instruction queue wakeup accesses
485system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads
486system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes
487system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
488system.cpu.iq.int_alu_accesses 824038596 # Number of integer alu accesses
489system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses
490system.cpu.iew.lsq.thread0.forwLoads 1642479 # Number of loads that had data forwarded from stores

491system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

492system.cpu.iew.lsq.thread0.squashedLoads 3355072 # Number of loads squashed
493system.cpu.iew.lsq.thread0.ignoredResponses 26592 # Number of memory responses ignored because the instruction is squashed
494system.cpu.iew.lsq.thread0.memOrderViolation 11367 # Number of memory ordering violations
495system.cpu.iew.lsq.thread0.squashedStores 1855422 # Number of stores squashed

492system.cpu.iew.lsq.thread0.squashedLoads 3121524 # Number of loads squashed
493system.cpu.iew.lsq.thread0.ignoredResponses 22243 # Number of memory responses ignored because the instruction is squashed
494system.cpu.iew.lsq.thread0.memOrderViolation 11430 # Number of memory ordering violations
495system.cpu.iew.lsq.thread0.squashedStores 1726583 # Number of stores squashed

496system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
497system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

498system.cpu.iew.lsq.thread0.rescheduledLoads 1932171 # Number of loads that were rescheduled
499system.cpu.iew.lsq.thread0.cacheBlocked 11828 # Number of times an access to memory failed due to the cache being blocked

498system.cpu.iew.lsq.thread0.rescheduledLoads 1932632 # Number of loads that were rescheduled
499system.cpu.iew.lsq.thread0.cacheBlocked 11779 # Number of times an access to memory failed due to the cache being blocked

500system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

501system.cpu.iew.iewSquashCycles 3850987 # Number of cycles IEW is squashing
502system.cpu.iew.iewBlockCycles 26145840 # Number of cycles IEW is blocking
503system.cpu.iew.iewUnblockCycles 2117101 # Number of cycles IEW is unblocking
504system.cpu.iew.iewDispatchedInsts 831222005 # Number of instructions dispatched to IQ
505system.cpu.iew.iewDispSquashedInsts 328364 # Number of squashed instructions skipped by dispatch
506system.cpu.iew.iewDispLoadInsts 17330743 # Number of dispatched load instructions
507system.cpu.iew.iewDispStoreInsts 10271430 # Number of dispatched store instructions
508system.cpu.iew.iewDispNonSpecInsts 725551 # Number of dispatched non-speculative instructions
509system.cpu.iew.iewIQFullEvents 1616789 # Number of times the IQ has become full, causing a stall
510system.cpu.iew.iewLSQFullEvents 12654 # Number of times the LSQ has become full, causing a stall
511system.cpu.iew.memOrderViolationEvents 11367 # Number of memory order violations
512system.cpu.iew.predictedTakenIncorrect 710665 # Number of branches that were predicted taken incorrectly
513system.cpu.iew.predictedNotTakenIncorrect 625080 # Number of branches that were predicted not taken incorrectly
514system.cpu.iew.branchMispredicts 1335745 # Number of branch mispredicts detected at execute
515system.cpu.iew.iewExecutedInsts 822377334 # Number of executed instructions
516system.cpu.iew.iewExecLoadInsts 17606524 # Number of load instructions executed
517system.cpu.iew.iewExecSquashedInsts 2028164 # Number of squashed instructions skipped in execute

501system.cpu.iew.iewSquashCycles 3599565 # Number of cycles IEW is squashing
502system.cpu.iew.iewBlockCycles 26096083 # Number of cycles IEW is blocking
503system.cpu.iew.iewUnblockCycles 2112224 # Number of cycles IEW is unblocking
504system.cpu.iew.iewDispatchedInsts 829554455 # Number of instructions dispatched to IQ
505system.cpu.iew.iewDispSquashedInsts 302739 # Number of squashed instructions skipped by dispatch
506system.cpu.iew.iewDispLoadInsts 17096853 # Number of dispatched load instructions
507system.cpu.iew.iewDispStoreInsts 10140380 # Number of dispatched store instructions
508system.cpu.iew.iewDispNonSpecInsts 717341 # Number of dispatched non-speculative instructions
509system.cpu.iew.iewIQFullEvents 1614771 # Number of times the IQ has become full, causing a stall
510system.cpu.iew.iewLSQFullEvents 11695 # Number of times the LSQ has become full, causing a stall
511system.cpu.iew.memOrderViolationEvents 11430 # Number of memory order violations
512system.cpu.iew.predictedTakenIncorrect 654771 # Number of branches that were predicted taken incorrectly
513system.cpu.iew.predictedNotTakenIncorrect 594016 # Number of branches that were predicted not taken incorrectly
514system.cpu.iew.branchMispredicts 1248787 # Number of branch mispredicts detected at execute
515system.cpu.iew.iewExecutedInsts 821389011 # Number of executed instructions
516system.cpu.iew.iewExecLoadInsts 17449263 # Number of load instructions executed
517system.cpu.iew.iewExecSquashedInsts 1894685 # Number of squashed instructions skipped in execute

518system.cpu.iew.exec_swp 0 # number of swp insts executed
519system.cpu.iew.exec_nop 0 # number of nop insts executed

520system.cpu.iew.exec_refs 26829889 # number of memory reference insts executed
521system.cpu.iew.exec_branches 83279279 # Number of branches executed
522system.cpu.iew.exec_stores 9223365 # Number of stores executed
523system.cpu.iew.exec_rate 1.832152 # Inst execution rate
524system.cpu.iew.wb_sent 821869918 # cumulative count of insts sent to commit
525system.cpu.iew.wb_count 819712181 # cumulative count of insts written-back
526system.cpu.iew.wb_producers 640562059 # num instructions producing a value
527system.cpu.iew.wb_consumers 1046574799 # num instructions consuming a value

520system.cpu.iew.exec_refs 26607287 # number of memory reference insts executed
521system.cpu.iew.exec_branches 83217289 # Number of branches executed
522system.cpu.iew.exec_stores 9158024 # Number of stores executed
523system.cpu.iew.exec_rate 1.834889 # Inst execution rate
524system.cpu.iew.wb_sent 820925784 # cumulative count of insts sent to commit
525system.cpu.iew.wb_count 818789455 # cumulative count of insts written-back
526system.cpu.iew.wb_producers 639951171 # num instructions producing a value
527system.cpu.iew.wb_consumers 1045809475 # num instructions consuming a value

528system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

529system.cpu.iew.wb_rate 1.826214 # insts written-back per cycle
530system.cpu.iew.wb_fanout 0.612056 # average fanout of values written-back

529system.cpu.iew.wb_rate 1.829082 # insts written-back per cycle
530system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back

531system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

532system.cpu.commit.commitSquashedInsts 24730610 # The number of squashed insts skipped by commit
533system.cpu.commit.commitNonSpecStalls 1052764 # The number of times commit has been forced to stall to communicate backwards
534system.cpu.commit.branchMispredicts 1192382 # The number of times a branch was mispredicted
535system.cpu.commit.committed_per_cycle::samples 255051171 # Number of insts commited each cycle
536system.cpu.commit.committed_per_cycle::mean 3.161659 # Number of insts commited each cycle
537system.cpu.commit.committed_per_cycle::stdev 2.853306 # Number of insts commited each cycle

532system.cpu.commit.commitSquashedInsts 23105687 # The number of squashed insts skipped by commit
533system.cpu.commit.commitNonSpecStalls 1052636 # The number of times commit has been forced to stall to communicate backwards
534system.cpu.commit.branchMispredicts 1116569 # The number of times a branch was mispredicted
535system.cpu.commit.committed_per_cycle::samples 254077625 # Number of insts commited each cycle
536system.cpu.commit.committed_per_cycle::mean 3.173607 # Number of insts commited each cycle
537system.cpu.commit.committed_per_cycle::stdev 2.854352 # Number of insts commited each cycle

538system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

539system.cpu.commit.committed_per_cycle::0 83143291 32.60% 32.60% # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::1 11860450 4.65% 37.25% # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::2 3961812 1.55% 38.80% # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::3 74971665 29.39% 68.20% # Number of insts commited each cycle
543system.cpu.commit.committed_per_cycle::4 2481439 0.97% 69.17% # Number of insts commited each cycle
544system.cpu.commit.committed_per_cycle::5 1489878 0.58% 69.75% # Number of insts commited each cycle
545system.cpu.commit.committed_per_cycle::6 950647 0.37% 70.13% # Number of insts commited each cycle
546system.cpu.commit.committed_per_cycle::7 70929098 27.81% 97.94% # Number of insts commited each cycle
547system.cpu.commit.committed_per_cycle::8 5262891 2.06% 100.00% # Number of insts commited each cycle

539system.cpu.commit.committed_per_cycle::0 82352974 32.41% 32.41% # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::1 11796837 4.64% 37.06% # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::2 3872314 1.52% 38.58% # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::3 74949594 29.50% 68.08% # Number of insts commited each cycle
543system.cpu.commit.committed_per_cycle::4 2433419 0.96% 69.04% # Number of insts commited each cycle
544system.cpu.commit.committed_per_cycle::5 1479159 0.58% 69.62% # Number of insts commited each cycle
545system.cpu.commit.committed_per_cycle::6 902635 0.36% 69.97% # Number of insts commited each cycle
546system.cpu.commit.committed_per_cycle::7 70918587 27.91% 97.89% # Number of insts commited each cycle
547system.cpu.commit.committed_per_cycle::8 5372106 2.11% 100.00% # Number of insts commited each cycle

548system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
549system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
550system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

551system.cpu.commit.committed_per_cycle::total 255051171 # Number of insts commited each cycle
552system.cpu.commit.committedInsts 407937545 # Number of instructions committed
553system.cpu.commit.committedOps 806384911 # Number of ops (including micro ops) committed

551system.cpu.commit.committed_per_cycle::total 254077625 # Number of insts commited each cycle
552system.cpu.commit.committedInsts 407917143 # Number of instructions committed
553system.cpu.commit.committedOps 806342485 # Number of ops (including micro ops) committed

554system.cpu.commit.swp_count 0 # Number of s/w prefetches committed

555system.cpu.commit.refs 22391676 # Number of memory references committed
556system.cpu.commit.loads 13975668 # Number of loads committed
557system.cpu.commit.membars 473465 # Number of memory barriers committed
558system.cpu.commit.branches 82190309 # Number of branches committed

555system.cpu.commit.refs 22389123 # Number of memory references committed
556system.cpu.commit.loads 13975326 # Number of loads committed
557system.cpu.commit.membars 473463 # Number of memory barriers committed
558system.cpu.commit.branches 82187715 # Number of branches committed

559system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.

560system.cpu.commit.int_insts 735319938 # Number of committed integer instructions.

560system.cpu.commit.int_insts 735283087 # Number of committed integer instructions.

561system.cpu.commit.function_calls 0 # Number of function calls committed.

562system.cpu.commit.bw_lim_events 5262891 # number cycles where commit BW limit reached

562system.cpu.commit.bw_lim_events 5372106 # number cycles where commit BW limit reached

563system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

564system.cpu.rob.rob_reads 1080825517 # The number of ROB reads
565system.cpu.rob.rob_writes 1666103017 # The number of ROB writes
566system.cpu.timesIdled 1222907 # Number of times that the entire CPU went into an idle state and unscheduled itself
567system.cpu.idleCycles 189972024 # Total number of cycles that the CPU has spent unscheduled due to idling
568system.cpu.quiesceCycles 9816871415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
569system.cpu.committedInsts 407937545 # Number of Instructions Simulated
570system.cpu.committedOps 806384911 # Number of Ops (including micro ops) Simulated
571system.cpu.committedInsts_total 407937545 # Number of Instructions Simulated
572system.cpu.cpi 1.100312 # CPI: Cycles Per Instruction
573system.cpu.cpi_total 1.100312 # CPI: Total CPI of All Threads
574system.cpu.ipc 0.908833 # IPC: Instructions Per Cycle
575system.cpu.ipc_total 0.908833 # IPC: Total IPC of All Threads
576system.cpu.int_regfile_reads 1508250980 # number of integer regfile reads
577system.cpu.int_regfile_writes 977858997 # number of integer regfile writes
578system.cpu.fp_regfile_reads 66 # number of floating regfile reads
579system.cpu.misc_regfile_reads 265171411 # number of misc regfile reads
580system.cpu.misc_regfile_writes 402390 # number of misc regfile writes
581system.cpu.icache.replacements 1072344 # number of replacements
582system.cpu.icache.tagsinuse 510.326715 # Cycle average of tags in use
583system.cpu.icache.total_refs 8127499 # Total number of references to valid blocks.
584system.cpu.icache.sampled_refs 1072855 # Sample count of references to valid blocks.
585system.cpu.icache.avg_refs 7.575580 # Average number of references to valid blocks.
586system.cpu.icache.warmup_cycle 56079311000 # Cycle when the warmup percentage was hit.
587system.cpu.icache.occ_blocks::cpu.inst 510.326715 # Average occupied blocks per requestor
588system.cpu.icache.occ_percent::cpu.inst 0.996732 # Average percentage of cache occupancy
589system.cpu.icache.occ_percent::total 0.996732 # Average percentage of cache occupancy
590system.cpu.icache.ReadReq_hits::cpu.inst 8127499 # number of ReadReq hits
591system.cpu.icache.ReadReq_hits::total 8127499 # number of ReadReq hits
592system.cpu.icache.demand_hits::cpu.inst 8127499 # number of demand (read+write) hits
593system.cpu.icache.demand_hits::total 8127499 # number of demand (read+write) hits
594system.cpu.icache.overall_hits::cpu.inst 8127499 # number of overall hits
595system.cpu.icache.overall_hits::total 8127499 # number of overall hits
596system.cpu.icache.ReadReq_misses::cpu.inst 1142014 # number of ReadReq misses
597system.cpu.icache.ReadReq_misses::total 1142014 # number of ReadReq misses
598system.cpu.icache.demand_misses::cpu.inst 1142014 # number of demand (read+write) misses
599system.cpu.icache.demand_misses::total 1142014 # number of demand (read+write) misses
600system.cpu.icache.overall_misses::cpu.inst 1142014 # number of overall misses
601system.cpu.icache.overall_misses::total 1142014 # number of overall misses
602system.cpu.icache.ReadReq_miss_latency::cpu.inst 15424181989 # number of ReadReq miss cycles
603system.cpu.icache.ReadReq_miss_latency::total 15424181989 # number of ReadReq miss cycles
604system.cpu.icache.demand_miss_latency::cpu.inst 15424181989 # number of demand (read+write) miss cycles
605system.cpu.icache.demand_miss_latency::total 15424181989 # number of demand (read+write) miss cycles
606system.cpu.icache.overall_miss_latency::cpu.inst 15424181989 # number of overall miss cycles
607system.cpu.icache.overall_miss_latency::total 15424181989 # number of overall miss cycles
608system.cpu.icache.ReadReq_accesses::cpu.inst 9269513 # number of ReadReq accesses(hits+misses)
609system.cpu.icache.ReadReq_accesses::total 9269513 # number of ReadReq accesses(hits+misses)
610system.cpu.icache.demand_accesses::cpu.inst 9269513 # number of demand (read+write) accesses
611system.cpu.icache.demand_accesses::total 9269513 # number of demand (read+write) accesses
612system.cpu.icache.overall_accesses::cpu.inst 9269513 # number of overall (read+write) accesses
613system.cpu.icache.overall_accesses::total 9269513 # number of overall (read+write) accesses
614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123201 # miss rate for ReadReq accesses
615system.cpu.icache.ReadReq_miss_rate::total 0.123201 # miss rate for ReadReq accesses
616system.cpu.icache.demand_miss_rate::cpu.inst 0.123201 # miss rate for demand accesses
617system.cpu.icache.demand_miss_rate::total 0.123201 # miss rate for demand accesses
618system.cpu.icache.overall_miss_rate::cpu.inst 0.123201 # miss rate for overall accesses
619system.cpu.icache.overall_miss_rate::total 0.123201 # miss rate for overall accesses
620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.123383 # average ReadReq miss latency
621system.cpu.icache.ReadReq_avg_miss_latency::total 13506.123383 # average ReadReq miss latency
622system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency
623system.cpu.icache.demand_avg_miss_latency::total 13506.123383 # average overall miss latency
624system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency
625system.cpu.icache.overall_avg_miss_latency::total 13506.123383 # average overall miss latency
626system.cpu.icache.blocked_cycles::no_mshrs 7378 # number of cycles access was blocked

564system.cpu.rob.rob_reads 1078075497 # The number of ROB reads
565system.cpu.rob.rob_writes 1662514782 # The number of ROB writes
566system.cpu.timesIdled 1218897 # Number of times that the entire CPU went into an idle state and unscheduled itself
567system.cpu.idleCycles 189988611 # Total number of cycles that the CPU has spent unscheduled due to idling
568system.cpu.quiesceCycles 9817926834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
569system.cpu.committedInsts 407917143 # Number of Instructions Simulated
570system.cpu.committedOps 806342485 # Number of Ops (including micro ops) Simulated
571system.cpu.committedInsts_total 407917143 # Number of Instructions Simulated
572system.cpu.cpi 1.097405 # CPI: Cycles Per Instruction
573system.cpu.cpi_total 1.097405 # CPI: Total CPI of All Threads
574system.cpu.ipc 0.911240 # IPC: Instructions Per Cycle
575system.cpu.ipc_total 0.911240 # IPC: Total IPC of All Threads
576system.cpu.int_regfile_reads 1506960736 # number of integer regfile reads
577system.cpu.int_regfile_writes 976968921 # number of integer regfile writes
578system.cpu.fp_regfile_reads 54 # number of floating regfile reads
579system.cpu.misc_regfile_reads 264713842 # number of misc regfile reads
580system.cpu.misc_regfile_writes 402218 # number of misc regfile writes
581system.cpu.icache.replacements 1046081 # number of replacements
582system.cpu.icache.tagsinuse 510.992308 # Cycle average of tags in use
583system.cpu.icache.total_refs 7932749 # Total number of references to valid blocks.
584system.cpu.icache.sampled_refs 1046593 # Sample count of references to valid blocks.
585system.cpu.icache.avg_refs 7.579593 # Average number of references to valid blocks.
586system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit.
587system.cpu.icache.occ_blocks::cpu.inst 510.992308 # Average occupied blocks per requestor
588system.cpu.icache.occ_percent::cpu.inst 0.998032 # Average percentage of cache occupancy
589system.cpu.icache.occ_percent::total 0.998032 # Average percentage of cache occupancy
590system.cpu.icache.ReadReq_hits::cpu.inst 7932749 # number of ReadReq hits
591system.cpu.icache.ReadReq_hits::total 7932749 # number of ReadReq hits
592system.cpu.icache.demand_hits::cpu.inst 7932749 # number of demand (read+write) hits
593system.cpu.icache.demand_hits::total 7932749 # number of demand (read+write) hits
594system.cpu.icache.overall_hits::cpu.inst 7932749 # number of overall hits
595system.cpu.icache.overall_hits::total 7932749 # number of overall hits
596system.cpu.icache.ReadReq_misses::cpu.inst 1110744 # number of ReadReq misses
597system.cpu.icache.ReadReq_misses::total 1110744 # number of ReadReq misses
598system.cpu.icache.demand_misses::cpu.inst 1110744 # number of demand (read+write) misses
599system.cpu.icache.demand_misses::total 1110744 # number of demand (read+write) misses
600system.cpu.icache.overall_misses::cpu.inst 1110744 # number of overall misses
601system.cpu.icache.overall_misses::total 1110744 # number of overall misses
602system.cpu.icache.ReadReq_miss_latency::cpu.inst 15035266490 # number of ReadReq miss cycles
603system.cpu.icache.ReadReq_miss_latency::total 15035266490 # number of ReadReq miss cycles
604system.cpu.icache.demand_miss_latency::cpu.inst 15035266490 # number of demand (read+write) miss cycles
605system.cpu.icache.demand_miss_latency::total 15035266490 # number of demand (read+write) miss cycles
606system.cpu.icache.overall_miss_latency::cpu.inst 15035266490 # number of overall miss cycles
607system.cpu.icache.overall_miss_latency::total 15035266490 # number of overall miss cycles
608system.cpu.icache.ReadReq_accesses::cpu.inst 9043493 # number of ReadReq accesses(hits+misses)
609system.cpu.icache.ReadReq_accesses::total 9043493 # number of ReadReq accesses(hits+misses)
610system.cpu.icache.demand_accesses::cpu.inst 9043493 # number of demand (read+write) accesses
611system.cpu.icache.demand_accesses::total 9043493 # number of demand (read+write) accesses
612system.cpu.icache.overall_accesses::cpu.inst 9043493 # number of overall (read+write) accesses
613system.cpu.icache.overall_accesses::total 9043493 # number of overall (read+write) accesses
614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122822 # miss rate for ReadReq accesses
615system.cpu.icache.ReadReq_miss_rate::total 0.122822 # miss rate for ReadReq accesses
616system.cpu.icache.demand_miss_rate::cpu.inst 0.122822 # miss rate for demand accesses
617system.cpu.icache.demand_miss_rate::total 0.122822 # miss rate for demand accesses
618system.cpu.icache.overall_miss_rate::cpu.inst 0.122822 # miss rate for overall accesses
619system.cpu.icache.overall_miss_rate::total 0.122822 # miss rate for overall accesses
620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13536.212206 # average ReadReq miss latency
621system.cpu.icache.ReadReq_avg_miss_latency::total 13536.212206 # average ReadReq miss latency
622system.cpu.icache.demand_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency
623system.cpu.icache.demand_avg_miss_latency::total 13536.212206 # average overall miss latency
624system.cpu.icache.overall_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency
625system.cpu.icache.overall_avg_miss_latency::total 13536.212206 # average overall miss latency
626system.cpu.icache.blocked_cycles::no_mshrs 5934 # number of cycles access was blocked

627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked

628system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked

628system.cpu.icache.blocked::no_mshrs 274 # number of cycles access was blocked

629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

630system.cpu.icache.avg_blocked_cycles::no_mshrs 29.047244 # average number of cycles each access was blocked

630system.cpu.icache.avg_blocked_cycles::no_mshrs 21.656934 # average number of cycles each access was blocked

631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
632system.cpu.icache.fast_writes 0 # number of fast writes performed
633system.cpu.icache.cache_copies 0 # number of cache copies performed

634system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66936 # number of ReadReq MSHR hits
635system.cpu.icache.ReadReq_mshr_hits::total 66936 # number of ReadReq MSHR hits
636system.cpu.icache.demand_mshr_hits::cpu.inst 66936 # number of demand (read+write) MSHR hits
637system.cpu.icache.demand_mshr_hits::total 66936 # number of demand (read+write) MSHR hits
638system.cpu.icache.overall_mshr_hits::cpu.inst 66936 # number of overall MSHR hits
639system.cpu.icache.overall_mshr_hits::total 66936 # number of overall MSHR hits
640system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075078 # number of ReadReq MSHR misses
641system.cpu.icache.ReadReq_mshr_misses::total 1075078 # number of ReadReq MSHR misses
642system.cpu.icache.demand_mshr_misses::cpu.inst 1075078 # number of demand (read+write) MSHR misses
643system.cpu.icache.demand_mshr_misses::total 1075078 # number of demand (read+write) MSHR misses
644system.cpu.icache.overall_mshr_misses::cpu.inst 1075078 # number of overall MSHR misses
645system.cpu.icache.overall_mshr_misses::total 1075078 # number of overall MSHR misses
646system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12692625989 # number of ReadReq MSHR miss cycles
647system.cpu.icache.ReadReq_mshr_miss_latency::total 12692625989 # number of ReadReq MSHR miss cycles
648system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12692625989 # number of demand (read+write) MSHR miss cycles
649system.cpu.icache.demand_mshr_miss_latency::total 12692625989 # number of demand (read+write) MSHR miss cycles
650system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12692625989 # number of overall MSHR miss cycles
651system.cpu.icache.overall_mshr_miss_latency::total 12692625989 # number of overall MSHR miss cycles
652system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for ReadReq accesses
653system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115980 # mshr miss rate for ReadReq accesses
654system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for demand accesses
655system.cpu.icache.demand_mshr_miss_rate::total 0.115980 # mshr miss rate for demand accesses
656system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for overall accesses
657system.cpu.icache.overall_mshr_miss_rate::total 0.115980 # mshr miss rate for overall accesses
658system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.237305 # average ReadReq mshr miss latency
659system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.237305 # average ReadReq mshr miss latency
660system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.237305 # average overall mshr miss latency
661system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.237305 # average overall mshr miss latency
662system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.237305 # average overall mshr miss latency
663system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.237305 # average overall mshr miss latency

634system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61679 # number of ReadReq MSHR hits
635system.cpu.icache.ReadReq_mshr_hits::total 61679 # number of ReadReq MSHR hits
636system.cpu.icache.demand_mshr_hits::cpu.inst 61679 # number of demand (read+write) MSHR hits
637system.cpu.icache.demand_mshr_hits::total 61679 # number of demand (read+write) MSHR hits
638system.cpu.icache.overall_mshr_hits::cpu.inst 61679 # number of overall MSHR hits
639system.cpu.icache.overall_mshr_hits::total 61679 # number of overall MSHR hits
640system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1049065 # number of ReadReq MSHR misses
641system.cpu.icache.ReadReq_mshr_misses::total 1049065 # number of ReadReq MSHR misses
642system.cpu.icache.demand_mshr_misses::cpu.inst 1049065 # number of demand (read+write) MSHR misses
643system.cpu.icache.demand_mshr_misses::total 1049065 # number of demand (read+write) MSHR misses
644system.cpu.icache.overall_mshr_misses::cpu.inst 1049065 # number of overall MSHR misses
645system.cpu.icache.overall_mshr_misses::total 1049065 # number of overall MSHR misses
646system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12388903990 # number of ReadReq MSHR miss cycles
647system.cpu.icache.ReadReq_mshr_miss_latency::total 12388903990 # number of ReadReq MSHR miss cycles
648system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12388903990 # number of demand (read+write) MSHR miss cycles
649system.cpu.icache.demand_mshr_miss_latency::total 12388903990 # number of demand (read+write) MSHR miss cycles
650system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12388903990 # number of overall MSHR miss cycles
651system.cpu.icache.overall_mshr_miss_latency::total 12388903990 # number of overall MSHR miss cycles
652system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for ReadReq accesses
653system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116002 # mshr miss rate for ReadReq accesses
654system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for demand accesses
655system.cpu.icache.demand_mshr_miss_rate::total 0.116002 # mshr miss rate for demand accesses
656system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for overall accesses
657system.cpu.icache.overall_mshr_miss_rate::total 0.116002 # mshr miss rate for overall accesses
658system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11809.472235 # average ReadReq mshr miss latency
659system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11809.472235 # average ReadReq mshr miss latency
660system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency
661system.cpu.icache.demand_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency
662system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency
663system.cpu.icache.overall_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency

664system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

665system.cpu.itb_walker_cache.replacements 10190 # number of replacements
666system.cpu.itb_walker_cache.tagsinuse 6.008148 # Cycle average of tags in use
667system.cpu.itb_walker_cache.total_refs 29715 # Total number of references to valid blocks.
668system.cpu.itb_walker_cache.sampled_refs 10203 # Sample count of references to valid blocks.
669system.cpu.itb_walker_cache.avg_refs 2.912379 # Average number of references to valid blocks.
670system.cpu.itb_walker_cache.warmup_cycle 5103977180500 # Cycle when the warmup percentage was hit.
671system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008148 # Average occupied blocks per requestor
672system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375509 # Average percentage of cache occupancy
673system.cpu.itb_walker_cache.occ_percent::total 0.375509 # Average percentage of cache occupancy
674system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 29719 # number of ReadReq hits
675system.cpu.itb_walker_cache.ReadReq_hits::total 29719 # number of ReadReq hits

665system.cpu.itb_walker_cache.replacements 9937 # number of replacements
666system.cpu.itb_walker_cache.tagsinuse 6.006130 # Cycle average of tags in use
667system.cpu.itb_walker_cache.total_refs 26086 # Total number of references to valid blocks.
668system.cpu.itb_walker_cache.sampled_refs 9951 # Sample count of references to valid blocks.
669system.cpu.itb_walker_cache.avg_refs 2.621445 # Average number of references to valid blocks.
670system.cpu.itb_walker_cache.warmup_cycle 5106893785000 # Cycle when the warmup percentage was hit.
671system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006130 # Average occupied blocks per requestor
672system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375383 # Average percentage of cache occupancy
673system.cpu.itb_walker_cache.occ_percent::total 0.375383 # Average percentage of cache occupancy
674system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26219 # number of ReadReq hits
675system.cpu.itb_walker_cache.ReadReq_hits::total 26219 # number of ReadReq hits

676system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
677system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits

678system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29722 # number of demand (read+write) hits
679system.cpu.itb_walker_cache.demand_hits::total 29722 # number of demand (read+write) hits
680system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29722 # number of overall hits
681system.cpu.itb_walker_cache.overall_hits::total 29722 # number of overall hits
682system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11072 # number of ReadReq misses
683system.cpu.itb_walker_cache.ReadReq_misses::total 11072 # number of ReadReq misses
684system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11072 # number of demand (read+write) misses
685system.cpu.itb_walker_cache.demand_misses::total 11072 # number of demand (read+write) misses
686system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11072 # number of overall misses
687system.cpu.itb_walker_cache.overall_misses::total 11072 # number of overall misses
688system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 125220500 # number of ReadReq miss cycles
689system.cpu.itb_walker_cache.ReadReq_miss_latency::total 125220500 # number of ReadReq miss cycles
690system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 125220500 # number of demand (read+write) miss cycles
691system.cpu.itb_walker_cache.demand_miss_latency::total 125220500 # number of demand (read+write) miss cycles
692system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 125220500 # number of overall miss cycles
693system.cpu.itb_walker_cache.overall_miss_latency::total 125220500 # number of overall miss cycles
694system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40791 # number of ReadReq accesses(hits+misses)
695system.cpu.itb_walker_cache.ReadReq_accesses::total 40791 # number of ReadReq accesses(hits+misses)

678system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26222 # number of demand (read+write) hits
679system.cpu.itb_walker_cache.demand_hits::total 26222 # number of demand (read+write) hits
680system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26222 # number of overall hits
681system.cpu.itb_walker_cache.overall_hits::total 26222 # number of overall hits
682system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10817 # number of ReadReq misses
683system.cpu.itb_walker_cache.ReadReq_misses::total 10817 # number of ReadReq misses
684system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10817 # number of demand (read+write) misses
685system.cpu.itb_walker_cache.demand_misses::total 10817 # number of demand (read+write) misses
686system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10817 # number of overall misses
687system.cpu.itb_walker_cache.overall_misses::total 10817 # number of overall misses
688system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116537500 # number of ReadReq miss cycles
689system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116537500 # number of ReadReq miss cycles
690system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116537500 # number of demand (read+write) miss cycles
691system.cpu.itb_walker_cache.demand_miss_latency::total 116537500 # number of demand (read+write) miss cycles
692system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116537500 # number of overall miss cycles
693system.cpu.itb_walker_cache.overall_miss_latency::total 116537500 # number of overall miss cycles
694system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37036 # number of ReadReq accesses(hits+misses)
695system.cpu.itb_walker_cache.ReadReq_accesses::total 37036 # number of ReadReq accesses(hits+misses)

696system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
697system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)

698system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40794 # number of demand (read+write) accesses
699system.cpu.itb_walker_cache.demand_accesses::total 40794 # number of demand (read+write) accesses
700system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40794 # number of overall (read+write) accesses
701system.cpu.itb_walker_cache.overall_accesses::total 40794 # number of overall (read+write) accesses
702system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.271432 # miss rate for ReadReq accesses
703system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.271432 # miss rate for ReadReq accesses
704system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.271412 # miss rate for demand accesses
705system.cpu.itb_walker_cache.demand_miss_rate::total 0.271412 # miss rate for demand accesses
706system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.271412 # miss rate for overall accesses
707system.cpu.itb_walker_cache.overall_miss_rate::total 0.271412 # miss rate for overall accesses
708system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11309.654986 # average ReadReq miss latency
709system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11309.654986 # average ReadReq miss latency
710system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency
711system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11309.654986 # average overall miss latency
712system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency
713system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11309.654986 # average overall miss latency

698system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37039 # number of demand (read+write) accesses
699system.cpu.itb_walker_cache.demand_accesses::total 37039 # number of demand (read+write) accesses
700system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37039 # number of overall (read+write) accesses
701system.cpu.itb_walker_cache.overall_accesses::total 37039 # number of overall (read+write) accesses
702system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.292067 # miss rate for ReadReq accesses
703system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.292067 # miss rate for ReadReq accesses
704system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.292044 # miss rate for demand accesses
705system.cpu.itb_walker_cache.demand_miss_rate::total 0.292044 # miss rate for demand accesses
706system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.292044 # miss rate for overall accesses
707system.cpu.itb_walker_cache.overall_miss_rate::total 0.292044 # miss rate for overall accesses
708system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10773.550892 # average ReadReq miss latency
709system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10773.550892 # average ReadReq miss latency
710system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10773.550892 # average overall miss latency
711system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10773.550892 # average overall miss latency
712system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10773.550892 # average overall miss latency
713system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10773.550892 # average overall miss latency

714system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
715system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
716system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
717system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
718system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
719system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
720system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
721system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed

722system.cpu.itb_walker_cache.writebacks::writebacks 1966 # number of writebacks
723system.cpu.itb_walker_cache.writebacks::total 1966 # number of writebacks
724system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11072 # number of ReadReq MSHR misses
725system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11072 # number of ReadReq MSHR misses
726system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11072 # number of demand (read+write) MSHR misses
727system.cpu.itb_walker_cache.demand_mshr_misses::total 11072 # number of demand (read+write) MSHR misses
728system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11072 # number of overall MSHR misses
729system.cpu.itb_walker_cache.overall_mshr_misses::total 11072 # number of overall MSHR misses
730system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 103076500 # number of ReadReq MSHR miss cycles
731system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 103076500 # number of ReadReq MSHR miss cycles
732system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 103076500 # number of demand (read+write) MSHR miss cycles
733system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 103076500 # number of demand (read+write) MSHR miss cycles
734system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 103076500 # number of overall MSHR miss cycles
735system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 103076500 # number of overall MSHR miss cycles
736system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.271432 # mshr miss rate for ReadReq accesses
737system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.271432 # mshr miss rate for ReadReq accesses
738system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for demand accesses
739system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.271412 # mshr miss rate for demand accesses
740system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for overall accesses
741system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.271412 # mshr miss rate for overall accesses
742system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average ReadReq mshr miss latency
743system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9309.654986 # average ReadReq mshr miss latency
744system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency
745system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency
746system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency
747system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency

722system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks
723system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks
724system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10817 # number of ReadReq MSHR misses
725system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10817 # number of ReadReq MSHR misses
726system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10817 # number of demand (read+write) MSHR misses
727system.cpu.itb_walker_cache.demand_mshr_misses::total 10817 # number of demand (read+write) MSHR misses
728system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10817 # number of overall MSHR misses
729system.cpu.itb_walker_cache.overall_mshr_misses::total 10817 # number of overall MSHR misses
730system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94903500 # number of ReadReq MSHR miss cycles
731system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94903500 # number of ReadReq MSHR miss cycles
732system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94903500 # number of demand (read+write) MSHR miss cycles
733system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94903500 # number of demand (read+write) MSHR miss cycles
734system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94903500 # number of overall MSHR miss cycles
735system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94903500 # number of overall MSHR miss cycles
736system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.292067 # mshr miss rate for ReadReq accesses
737system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.292067 # mshr miss rate for ReadReq accesses
738system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for demand accesses
739system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.292044 # mshr miss rate for demand accesses
740system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for overall accesses
741system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.292044 # mshr miss rate for overall accesses
742system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average ReadReq mshr miss latency
743system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8773.550892 # average ReadReq mshr miss latency
744system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency
745system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency
746system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency
747system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency

748system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate

749system.cpu.dtb_walker_cache.replacements 112521 # number of replacements
750system.cpu.dtb_walker_cache.tagsinuse 12.957581 # Cycle average of tags in use
751system.cpu.dtb_walker_cache.total_refs 137445 # Total number of references to valid blocks.
752system.cpu.dtb_walker_cache.sampled_refs 112536 # Sample count of references to valid blocks.
753system.cpu.dtb_walker_cache.avg_refs 1.221343 # Average number of references to valid blocks.
754system.cpu.dtb_walker_cache.warmup_cycle 5100518873000 # Cycle when the warmup percentage was hit.
755system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.957581 # Average occupied blocks per requestor
756system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809849 # Average percentage of cache occupancy
757system.cpu.dtb_walker_cache.occ_percent::total 0.809849 # Average percentage of cache occupancy
758system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137452 # number of ReadReq hits
759system.cpu.dtb_walker_cache.ReadReq_hits::total 137452 # number of ReadReq hits
760system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137452 # number of demand (read+write) hits
761system.cpu.dtb_walker_cache.demand_hits::total 137452 # number of demand (read+write) hits
762system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137452 # number of overall hits
763system.cpu.dtb_walker_cache.overall_hits::total 137452 # number of overall hits
764system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 113500 # number of ReadReq misses
765system.cpu.dtb_walker_cache.ReadReq_misses::total 113500 # number of ReadReq misses
766system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 113500 # number of demand (read+write) misses
767system.cpu.dtb_walker_cache.demand_misses::total 113500 # number of demand (read+write) misses
768system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113500 # number of overall misses
769system.cpu.dtb_walker_cache.overall_misses::total 113500 # number of overall misses
770system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1432388500 # number of ReadReq miss cycles
771system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1432388500 # number of ReadReq miss cycles
772system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1432388500 # number of demand (read+write) miss cycles
773system.cpu.dtb_walker_cache.demand_miss_latency::total 1432388500 # number of demand (read+write) miss cycles
774system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1432388500 # number of overall miss cycles
775system.cpu.dtb_walker_cache.overall_miss_latency::total 1432388500 # number of overall miss cycles
776system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 250952 # number of ReadReq accesses(hits+misses)
777system.cpu.dtb_walker_cache.ReadReq_accesses::total 250952 # number of ReadReq accesses(hits+misses)
778system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 250952 # number of demand (read+write) accesses
779system.cpu.dtb_walker_cache.demand_accesses::total 250952 # number of demand (read+write) accesses
780system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 250952 # number of overall (read+write) accesses
781system.cpu.dtb_walker_cache.overall_accesses::total 250952 # number of overall (read+write) accesses
782system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452278 # miss rate for ReadReq accesses
783system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452278 # miss rate for ReadReq accesses
784system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452278 # miss rate for demand accesses
785system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452278 # miss rate for demand accesses
786system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452278 # miss rate for overall accesses
787system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452278 # miss rate for overall accesses
788system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12620.162996 # average ReadReq miss latency
789system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12620.162996 # average ReadReq miss latency
790system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency
791system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12620.162996 # average overall miss latency
792system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency
793system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12620.162996 # average overall miss latency

749system.cpu.dtb_walker_cache.replacements 113923 # number of replacements
750system.cpu.dtb_walker_cache.tagsinuse 12.921985 # Cycle average of tags in use
751system.cpu.dtb_walker_cache.total_refs 130116 # Total number of references to valid blocks.
752system.cpu.dtb_walker_cache.sampled_refs 113938 # Sample count of references to valid blocks.
753system.cpu.dtb_walker_cache.avg_refs 1.141990 # Average number of references to valid blocks.
754system.cpu.dtb_walker_cache.warmup_cycle 5100448688500 # Cycle when the warmup percentage was hit.
755system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.921985 # Average occupied blocks per requestor
756system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.807624 # Average percentage of cache occupancy
757system.cpu.dtb_walker_cache.occ_percent::total 0.807624 # Average percentage of cache occupancy
758system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130138 # number of ReadReq hits
759system.cpu.dtb_walker_cache.ReadReq_hits::total 130138 # number of ReadReq hits
760system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130138 # number of demand (read+write) hits
761system.cpu.dtb_walker_cache.demand_hits::total 130138 # number of demand (read+write) hits
762system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130138 # number of overall hits
763system.cpu.dtb_walker_cache.overall_hits::total 130138 # number of overall hits
764system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 114896 # number of ReadReq misses
765system.cpu.dtb_walker_cache.ReadReq_misses::total 114896 # number of ReadReq misses
766system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 114896 # number of demand (read+write) misses
767system.cpu.dtb_walker_cache.demand_misses::total 114896 # number of demand (read+write) misses
768system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 114896 # number of overall misses
769system.cpu.dtb_walker_cache.overall_misses::total 114896 # number of overall misses
770system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1427497500 # number of ReadReq miss cycles
771system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1427497500 # number of ReadReq miss cycles
772system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1427497500 # number of demand (read+write) miss cycles
773system.cpu.dtb_walker_cache.demand_miss_latency::total 1427497500 # number of demand (read+write) miss cycles
774system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1427497500 # number of overall miss cycles
775system.cpu.dtb_walker_cache.overall_miss_latency::total 1427497500 # number of overall miss cycles
776system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245034 # number of ReadReq accesses(hits+misses)
777system.cpu.dtb_walker_cache.ReadReq_accesses::total 245034 # number of ReadReq accesses(hits+misses)
778system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245034 # number of demand (read+write) accesses
779system.cpu.dtb_walker_cache.demand_accesses::total 245034 # number of demand (read+write) accesses
780system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245034 # number of overall (read+write) accesses
781system.cpu.dtb_walker_cache.overall_accesses::total 245034 # number of overall (read+write) accesses
782system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.468898 # miss rate for ReadReq accesses
783system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.468898 # miss rate for ReadReq accesses
784system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.468898 # miss rate for demand accesses
785system.cpu.dtb_walker_cache.demand_miss_rate::total 0.468898 # miss rate for demand accesses
786system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468898 # miss rate for overall accesses
787system.cpu.dtb_walker_cache.overall_miss_rate::total 0.468898 # miss rate for overall accesses
788system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.257589 # average ReadReq miss latency
789system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.257589 # average ReadReq miss latency
790system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency
791system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.257589 # average overall miss latency
792system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency
793system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.257589 # average overall miss latency

794system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
795system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
796system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
797system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
798system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
799system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
800system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
801system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed

802system.cpu.dtb_walker_cache.writebacks::writebacks 37324 # number of writebacks
803system.cpu.dtb_walker_cache.writebacks::total 37324 # number of writebacks
804system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 113500 # number of ReadReq MSHR misses
805system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 113500 # number of ReadReq MSHR misses
806system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 113500 # number of demand (read+write) MSHR misses
807system.cpu.dtb_walker_cache.demand_mshr_misses::total 113500 # number of demand (read+write) MSHR misses
808system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 113500 # number of overall MSHR misses
809system.cpu.dtb_walker_cache.overall_mshr_misses::total 113500 # number of overall MSHR misses
810system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of ReadReq MSHR miss cycles
811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1205388500 # number of ReadReq MSHR miss cycles
812system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of demand (read+write) MSHR miss cycles
813system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1205388500 # number of demand (read+write) MSHR miss cycles
814system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of overall MSHR miss cycles
815system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1205388500 # number of overall MSHR miss cycles
816system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for ReadReq accesses
817system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452278 # mshr miss rate for ReadReq accesses
818system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for demand accesses
819system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452278 # mshr miss rate for demand accesses
820system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for overall accesses
821system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452278 # mshr miss rate for overall accesses
822system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average ReadReq mshr miss latency
823system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10620.162996 # average ReadReq mshr miss latency
824system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency
825system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency
826system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency
827system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency

802system.cpu.dtb_walker_cache.writebacks::writebacks 35555 # number of writebacks
803system.cpu.dtb_walker_cache.writebacks::total 35555 # number of writebacks
804system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 114896 # number of ReadReq MSHR misses
805system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 114896 # number of ReadReq MSHR misses
806system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 114896 # number of demand (read+write) MSHR misses
807system.cpu.dtb_walker_cache.demand_mshr_misses::total 114896 # number of demand (read+write) MSHR misses
808system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 114896 # number of overall MSHR misses
809system.cpu.dtb_walker_cache.overall_mshr_misses::total 114896 # number of overall MSHR misses
810system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of ReadReq MSHR miss cycles
811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1197705500 # number of ReadReq MSHR miss cycles
812system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of demand (read+write) MSHR miss cycles
813system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1197705500 # number of demand (read+write) MSHR miss cycles
814system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of overall MSHR miss cycles
815system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1197705500 # number of overall MSHR miss cycles
816system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for ReadReq accesses
817system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.468898 # mshr miss rate for ReadReq accesses
818system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for demand accesses
819system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.468898 # mshr miss rate for demand accesses
820system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for overall accesses
821system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.468898 # mshr miss rate for overall accesses
822system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average ReadReq mshr miss latency
823system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10424.257589 # average ReadReq mshr miss latency
824system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency
825system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency
826system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency
827system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency

828system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate

829system.cpu.dcache.replacements 1671903 # number of replacements
830system.cpu.dcache.tagsinuse 511.996701 # Cycle average of tags in use
831system.cpu.dcache.total_refs 19219910 # Total number of references to valid blocks.
832system.cpu.dcache.sampled_refs 1672415 # Sample count of references to valid blocks.
833system.cpu.dcache.avg_refs 11.492309 # Average number of references to valid blocks.
834system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit.
835system.cpu.dcache.occ_blocks::cpu.data 511.996701 # Average occupied blocks per requestor
836system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
837system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
838system.cpu.dcache.ReadReq_hits::cpu.data 11126974 # number of ReadReq hits
839system.cpu.dcache.ReadReq_hits::total 11126974 # number of ReadReq hits
840system.cpu.dcache.WriteReq_hits::cpu.data 8088054 # number of WriteReq hits
841system.cpu.dcache.WriteReq_hits::total 8088054 # number of WriteReq hits
842system.cpu.dcache.demand_hits::cpu.data 19215028 # number of demand (read+write) hits
843system.cpu.dcache.demand_hits::total 19215028 # number of demand (read+write) hits
844system.cpu.dcache.overall_hits::cpu.data 19215028 # number of overall hits
845system.cpu.dcache.overall_hits::total 19215028 # number of overall hits
846system.cpu.dcache.ReadReq_misses::cpu.data 2267052 # number of ReadReq misses
847system.cpu.dcache.ReadReq_misses::total 2267052 # number of ReadReq misses
848system.cpu.dcache.WriteReq_misses::cpu.data 318719 # number of WriteReq misses
849system.cpu.dcache.WriteReq_misses::total 318719 # number of WriteReq misses
850system.cpu.dcache.demand_misses::cpu.data 2585771 # number of demand (read+write) misses
851system.cpu.dcache.demand_misses::total 2585771 # number of demand (read+write) misses
852system.cpu.dcache.overall_misses::cpu.data 2585771 # number of overall misses
853system.cpu.dcache.overall_misses::total 2585771 # number of overall misses
854system.cpu.dcache.ReadReq_miss_latency::cpu.data 32362735000 # number of ReadReq miss cycles
855system.cpu.dcache.ReadReq_miss_latency::total 32362735000 # number of ReadReq miss cycles
856system.cpu.dcache.WriteReq_miss_latency::cpu.data 9617362993 # number of WriteReq miss cycles
857system.cpu.dcache.WriteReq_miss_latency::total 9617362993 # number of WriteReq miss cycles
858system.cpu.dcache.demand_miss_latency::cpu.data 41980097993 # number of demand (read+write) miss cycles
859system.cpu.dcache.demand_miss_latency::total 41980097993 # number of demand (read+write) miss cycles
860system.cpu.dcache.overall_miss_latency::cpu.data 41980097993 # number of overall miss cycles
861system.cpu.dcache.overall_miss_latency::total 41980097993 # number of overall miss cycles
862system.cpu.dcache.ReadReq_accesses::cpu.data 13394026 # number of ReadReq accesses(hits+misses)
863system.cpu.dcache.ReadReq_accesses::total 13394026 # number of ReadReq accesses(hits+misses)
864system.cpu.dcache.WriteReq_accesses::cpu.data 8406773 # number of WriteReq accesses(hits+misses)
865system.cpu.dcache.WriteReq_accesses::total 8406773 # number of WriteReq accesses(hits+misses)
866system.cpu.dcache.demand_accesses::cpu.data 21800799 # number of demand (read+write) accesses
867system.cpu.dcache.demand_accesses::total 21800799 # number of demand (read+write) accesses
868system.cpu.dcache.overall_accesses::cpu.data 21800799 # number of overall (read+write) accesses
869system.cpu.dcache.overall_accesses::total 21800799 # number of overall (read+write) accesses
870system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169258 # miss rate for ReadReq accesses
871system.cpu.dcache.ReadReq_miss_rate::total 0.169258 # miss rate for ReadReq accesses
872system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037912 # miss rate for WriteReq accesses
873system.cpu.dcache.WriteReq_miss_rate::total 0.037912 # miss rate for WriteReq accesses
874system.cpu.dcache.demand_miss_rate::cpu.data 0.118609 # miss rate for demand accesses
875system.cpu.dcache.demand_miss_rate::total 0.118609 # miss rate for demand accesses
876system.cpu.dcache.overall_miss_rate::cpu.data 0.118609 # miss rate for overall accesses
877system.cpu.dcache.overall_miss_rate::total 0.118609 # miss rate for overall accesses
878system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14275.250413 # average ReadReq miss latency
879system.cpu.dcache.ReadReq_avg_miss_latency::total 14275.250413 # average ReadReq miss latency
880system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30175.053866 # average WriteReq miss latency
881system.cpu.dcache.WriteReq_avg_miss_latency::total 30175.053866 # average WriteReq miss latency
882system.cpu.dcache.demand_avg_miss_latency::cpu.data 16235.040919 # average overall miss latency
883system.cpu.dcache.demand_avg_miss_latency::total 16235.040919 # average overall miss latency
884system.cpu.dcache.overall_avg_miss_latency::cpu.data 16235.040919 # average overall miss latency
885system.cpu.dcache.overall_avg_miss_latency::total 16235.040919 # average overall miss latency
886system.cpu.dcache.blocked_cycles::no_mshrs 395929 # number of cycles access was blocked

829system.cpu.dcache.replacements 1657882 # number of replacements
830system.cpu.dcache.tagsinuse 511.998105 # Cycle average of tags in use
831system.cpu.dcache.total_refs 19102953 # Total number of references to valid blocks.
832system.cpu.dcache.sampled_refs 1658394 # Sample count of references to valid blocks.
833system.cpu.dcache.avg_refs 11.518947 # Average number of references to valid blocks.
834system.cpu.dcache.warmup_cycle 27815000 # Cycle when the warmup percentage was hit.
835system.cpu.dcache.occ_blocks::cpu.data 511.998105 # Average occupied blocks per requestor
836system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
837system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
838system.cpu.dcache.ReadReq_hits::cpu.data 11010989 # number of ReadReq hits
839system.cpu.dcache.ReadReq_hits::total 11010989 # number of ReadReq hits
840system.cpu.dcache.WriteReq_hits::cpu.data 8086819 # number of WriteReq hits
841system.cpu.dcache.WriteReq_hits::total 8086819 # number of WriteReq hits
842system.cpu.dcache.demand_hits::cpu.data 19097808 # number of demand (read+write) hits
843system.cpu.dcache.demand_hits::total 19097808 # number of demand (read+write) hits
844system.cpu.dcache.overall_hits::cpu.data 19097808 # number of overall hits
845system.cpu.dcache.overall_hits::total 19097808 # number of overall hits
846system.cpu.dcache.ReadReq_misses::cpu.data 2233987 # number of ReadReq misses
847system.cpu.dcache.ReadReq_misses::total 2233987 # number of ReadReq misses
848system.cpu.dcache.WriteReq_misses::cpu.data 317747 # number of WriteReq misses
849system.cpu.dcache.WriteReq_misses::total 317747 # number of WriteReq misses
850system.cpu.dcache.demand_misses::cpu.data 2551734 # number of demand (read+write) misses
851system.cpu.dcache.demand_misses::total 2551734 # number of demand (read+write) misses
852system.cpu.dcache.overall_misses::cpu.data 2551734 # number of overall misses
853system.cpu.dcache.overall_misses::total 2551734 # number of overall misses
854system.cpu.dcache.ReadReq_miss_latency::cpu.data 31818004500 # number of ReadReq miss cycles
855system.cpu.dcache.ReadReq_miss_latency::total 31818004500 # number of ReadReq miss cycles
856system.cpu.dcache.WriteReq_miss_latency::cpu.data 9564256493 # number of WriteReq miss cycles
857system.cpu.dcache.WriteReq_miss_latency::total 9564256493 # number of WriteReq miss cycles
858system.cpu.dcache.demand_miss_latency::cpu.data 41382260993 # number of demand (read+write) miss cycles
859system.cpu.dcache.demand_miss_latency::total 41382260993 # number of demand (read+write) miss cycles
860system.cpu.dcache.overall_miss_latency::cpu.data 41382260993 # number of overall miss cycles
861system.cpu.dcache.overall_miss_latency::total 41382260993 # number of overall miss cycles
862system.cpu.dcache.ReadReq_accesses::cpu.data 13244976 # number of ReadReq accesses(hits+misses)
863system.cpu.dcache.ReadReq_accesses::total 13244976 # number of ReadReq accesses(hits+misses)
864system.cpu.dcache.WriteReq_accesses::cpu.data 8404566 # number of WriteReq accesses(hits+misses)
865system.cpu.dcache.WriteReq_accesses::total 8404566 # number of WriteReq accesses(hits+misses)
866system.cpu.dcache.demand_accesses::cpu.data 21649542 # number of demand (read+write) accesses
867system.cpu.dcache.demand_accesses::total 21649542 # number of demand (read+write) accesses
868system.cpu.dcache.overall_accesses::cpu.data 21649542 # number of overall (read+write) accesses
869system.cpu.dcache.overall_accesses::total 21649542 # number of overall (read+write) accesses
870system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168667 # miss rate for ReadReq accesses
871system.cpu.dcache.ReadReq_miss_rate::total 0.168667 # miss rate for ReadReq accesses
872system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037806 # miss rate for WriteReq accesses
873system.cpu.dcache.WriteReq_miss_rate::total 0.037806 # miss rate for WriteReq accesses
874system.cpu.dcache.demand_miss_rate::cpu.data 0.117865 # miss rate for demand accesses
875system.cpu.dcache.demand_miss_rate::total 0.117865 # miss rate for demand accesses
876system.cpu.dcache.overall_miss_rate::cpu.data 0.117865 # miss rate for overall accesses
877system.cpu.dcache.overall_miss_rate::total 0.117865 # miss rate for overall accesses
878system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14242.699040 # average ReadReq miss latency
879system.cpu.dcache.ReadReq_avg_miss_latency::total 14242.699040 # average ReadReq miss latency
880system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30100.225944 # average WriteReq miss latency
881system.cpu.dcache.WriteReq_avg_miss_latency::total 30100.225944 # average WriteReq miss latency
882system.cpu.dcache.demand_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency
883system.cpu.dcache.demand_avg_miss_latency::total 16217.309874 # average overall miss latency
884system.cpu.dcache.overall_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency
885system.cpu.dcache.overall_avg_miss_latency::total 16217.309874 # average overall miss latency
886system.cpu.dcache.blocked_cycles::no_mshrs 396326 # number of cycles access was blocked

887system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

888system.cpu.dcache.blocked::no_mshrs 42571 # number of cycles access was blocked

888system.cpu.dcache.blocked::no_mshrs 42512 # number of cycles access was blocked

889system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

890system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.300439 # average number of cycles each access was blocked

890system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.322685 # average number of cycles each access was blocked

891system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
892system.cpu.dcache.fast_writes 0 # number of fast writes performed
893system.cpu.dcache.cache_copies 0 # number of cache copies performed

894system.cpu.dcache.writebacks::writebacks 1571444 # number of writebacks
895system.cpu.dcache.writebacks::total 1571444 # number of writebacks
896system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884224 # number of ReadReq MSHR hits
897system.cpu.dcache.ReadReq_mshr_hits::total 884224 # number of ReadReq MSHR hits
898system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24733 # number of WriteReq MSHR hits
899system.cpu.dcache.WriteReq_mshr_hits::total 24733 # number of WriteReq MSHR hits
900system.cpu.dcache.demand_mshr_hits::cpu.data 908957 # number of demand (read+write) MSHR hits
901system.cpu.dcache.demand_mshr_hits::total 908957 # number of demand (read+write) MSHR hits
902system.cpu.dcache.overall_mshr_hits::cpu.data 908957 # number of overall MSHR hits
903system.cpu.dcache.overall_mshr_hits::total 908957 # number of overall MSHR hits
904system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1382828 # number of ReadReq MSHR misses
905system.cpu.dcache.ReadReq_mshr_misses::total 1382828 # number of ReadReq MSHR misses
906system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293986 # number of WriteReq MSHR misses
907system.cpu.dcache.WriteReq_mshr_misses::total 293986 # number of WriteReq MSHR misses
908system.cpu.dcache.demand_mshr_misses::cpu.data 1676814 # number of demand (read+write) MSHR misses
909system.cpu.dcache.demand_mshr_misses::total 1676814 # number of demand (read+write) MSHR misses
910system.cpu.dcache.overall_mshr_misses::cpu.data 1676814 # number of overall MSHR misses
911system.cpu.dcache.overall_mshr_misses::total 1676814 # number of overall MSHR misses
912system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17466154000 # number of ReadReq MSHR miss cycles
913system.cpu.dcache.ReadReq_mshr_miss_latency::total 17466154000 # number of ReadReq MSHR miss cycles
914system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8776924993 # number of WriteReq MSHR miss cycles
915system.cpu.dcache.WriteReq_mshr_miss_latency::total 8776924993 # number of WriteReq MSHR miss cycles
916system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26243078993 # number of demand (read+write) MSHR miss cycles
917system.cpu.dcache.demand_mshr_miss_latency::total 26243078993 # number of demand (read+write) MSHR miss cycles
918system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26243078993 # number of overall MSHR miss cycles
919system.cpu.dcache.overall_mshr_miss_latency::total 26243078993 # number of overall MSHR miss cycles
920system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296687500 # number of ReadReq MSHR uncacheable cycles
921system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296687500 # number of ReadReq MSHR uncacheable cycles
922system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470134500 # number of WriteReq MSHR uncacheable cycles
923system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470134500 # number of WriteReq MSHR uncacheable cycles
924system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766822000 # number of overall MSHR uncacheable cycles
925system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766822000 # number of overall MSHR uncacheable cycles
926system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103242 # mshr miss rate for ReadReq accesses
927system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103242 # mshr miss rate for ReadReq accesses
928system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034970 # mshr miss rate for WriteReq accesses
929system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034970 # mshr miss rate for WriteReq accesses
930system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076915 # mshr miss rate for demand accesses
931system.cpu.dcache.demand_mshr_miss_rate::total 0.076915 # mshr miss rate for demand accesses
932system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076915 # mshr miss rate for overall accesses
933system.cpu.dcache.overall_mshr_miss_rate::total 0.076915 # mshr miss rate for overall accesses
934system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12630.749450 # average ReadReq mshr miss latency
935system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12630.749450 # average ReadReq mshr miss latency
936system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29854.908033 # average WriteReq mshr miss latency
937system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29854.908033 # average WriteReq mshr miss latency
938system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency
939system.cpu.dcache.demand_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency
940system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency
941system.cpu.dcache.overall_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency

894system.cpu.dcache.writebacks::writebacks 1559612 # number of writebacks
895system.cpu.dcache.writebacks::total 1559612 # number of writebacks
896system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862458 # number of ReadReq MSHR hits
897system.cpu.dcache.ReadReq_mshr_hits::total 862458 # number of ReadReq MSHR hits
898system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26265 # number of WriteReq MSHR hits
899system.cpu.dcache.WriteReq_mshr_hits::total 26265 # number of WriteReq MSHR hits
900system.cpu.dcache.demand_mshr_hits::cpu.data 888723 # number of demand (read+write) MSHR hits
901system.cpu.dcache.demand_mshr_hits::total 888723 # number of demand (read+write) MSHR hits
902system.cpu.dcache.overall_mshr_hits::cpu.data 888723 # number of overall MSHR hits
903system.cpu.dcache.overall_mshr_hits::total 888723 # number of overall MSHR hits
904system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371529 # number of ReadReq MSHR misses
905system.cpu.dcache.ReadReq_mshr_misses::total 1371529 # number of ReadReq MSHR misses
906system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291482 # number of WriteReq MSHR misses
907system.cpu.dcache.WriteReq_mshr_misses::total 291482 # number of WriteReq MSHR misses
908system.cpu.dcache.demand_mshr_misses::cpu.data 1663011 # number of demand (read+write) MSHR misses
909system.cpu.dcache.demand_mshr_misses::total 1663011 # number of demand (read+write) MSHR misses
910system.cpu.dcache.overall_mshr_misses::cpu.data 1663011 # number of overall MSHR misses
911system.cpu.dcache.overall_mshr_misses::total 1663011 # number of overall MSHR misses
912system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17298488500 # number of ReadReq MSHR miss cycles
913system.cpu.dcache.ReadReq_mshr_miss_latency::total 17298488500 # number of ReadReq MSHR miss cycles
914system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8726866493 # number of WriteReq MSHR miss cycles
915system.cpu.dcache.WriteReq_mshr_miss_latency::total 8726866493 # number of WriteReq MSHR miss cycles
916system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26025354993 # number of demand (read+write) MSHR miss cycles
917system.cpu.dcache.demand_mshr_miss_latency::total 26025354993 # number of demand (read+write) MSHR miss cycles
918system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26025354993 # number of overall MSHR miss cycles
919system.cpu.dcache.overall_mshr_miss_latency::total 26025354993 # number of overall MSHR miss cycles
920system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296677500 # number of ReadReq MSHR uncacheable cycles
921system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296677500 # number of ReadReq MSHR uncacheable cycles
922system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469996000 # number of WriteReq MSHR uncacheable cycles
923system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469996000 # number of WriteReq MSHR uncacheable cycles
924system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766673500 # number of overall MSHR uncacheable cycles
925system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766673500 # number of overall MSHR uncacheable cycles
926system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103551 # mshr miss rate for ReadReq accesses
927system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103551 # mshr miss rate for ReadReq accesses
928system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034681 # mshr miss rate for WriteReq accesses
929system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034681 # mshr miss rate for WriteReq accesses
930system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for demand accesses
931system.cpu.dcache.demand_mshr_miss_rate::total 0.076815 # mshr miss rate for demand accesses
932system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for overall accesses
933system.cpu.dcache.overall_mshr_miss_rate::total 0.076815 # mshr miss rate for overall accesses
934system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12612.557591 # average ReadReq mshr miss latency
935system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12612.557591 # average ReadReq mshr miss latency
936system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29939.641189 # average WriteReq mshr miss latency
937system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29939.641189 # average WriteReq mshr miss latency
938system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency
939system.cpu.dcache.demand_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency
940system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency
941system.cpu.dcache.overall_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency

942system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
943system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
944system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
945system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
946system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
947system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
948system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

949system.cpu.l2cache.replacements 114477 # number of replacements
950system.cpu.l2cache.tagsinuse 64832.099181 # Cycle average of tags in use
951system.cpu.l2cache.total_refs 3982953 # Total number of references to valid blocks.
952system.cpu.l2cache.sampled_refs 178625 # Sample count of references to valid blocks.
953system.cpu.l2cache.avg_refs 22.297847 # Average number of references to valid blocks.

949system.cpu.l2cache.replacements 113761 # number of replacements
950system.cpu.l2cache.tagsinuse 64829.122340 # Cycle average of tags in use
951system.cpu.l2cache.total_refs 3920006 # Total number of references to valid blocks.
952system.cpu.l2cache.sampled_refs 178006 # Sample count of references to valid blocks.
953system.cpu.l2cache.avg_refs 22.021763 # Average number of references to valid blocks.

954system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

955system.cpu.l2cache.occ_blocks::writebacks 50137.283412 # Average occupied blocks per requestor
956system.cpu.l2cache.occ_blocks::cpu.dtb.walker 9.875444 # Average occupied blocks per requestor
957system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.154438 # Average occupied blocks per requestor
958system.cpu.l2cache.occ_blocks::cpu.inst 3167.346365 # Average occupied blocks per requestor
959system.cpu.l2cache.occ_blocks::cpu.data 11517.439521 # Average occupied blocks per requestor
960system.cpu.l2cache.occ_percent::writebacks 0.765034 # Average percentage of cache occupancy
961system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000151 # Average percentage of cache occupancy

955system.cpu.l2cache.occ_blocks::writebacks 50212.838916 # Average occupied blocks per requestor
956system.cpu.l2cache.occ_blocks::cpu.dtb.walker 12.458733 # Average occupied blocks per requestor
957system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.160012 # Average occupied blocks per requestor
958system.cpu.l2cache.occ_blocks::cpu.inst 3172.410316 # Average occupied blocks per requestor
959system.cpu.l2cache.occ_blocks::cpu.data 11431.254363 # Average occupied blocks per requestor
960system.cpu.l2cache.occ_percent::writebacks 0.766187 # Average percentage of cache occupancy
961system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000190 # Average percentage of cache occupancy

962system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy

963system.cpu.l2cache.occ_percent::cpu.inst 0.048330 # Average percentage of cache occupancy
964system.cpu.l2cache.occ_percent::cpu.data 0.175742 # Average percentage of cache occupancy
965system.cpu.l2cache.occ_percent::total 0.989259 # Average percentage of cache occupancy
966system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 106895 # number of ReadReq hits
967system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8720 # number of ReadReq hits
968system.cpu.l2cache.ReadReq_hits::cpu.inst 1055914 # number of ReadReq hits
969system.cpu.l2cache.ReadReq_hits::cpu.data 1344492 # number of ReadReq hits
970system.cpu.l2cache.ReadReq_hits::total 2516021 # number of ReadReq hits
971system.cpu.l2cache.Writeback_hits::writebacks 1610734 # number of Writeback hits
972system.cpu.l2cache.Writeback_hits::total 1610734 # number of Writeback hits
973system.cpu.l2cache.UpgradeReq_hits::cpu.data 350 # number of UpgradeReq hits
974system.cpu.l2cache.UpgradeReq_hits::total 350 # number of UpgradeReq hits
975system.cpu.l2cache.ReadExReq_hits::cpu.data 156374 # number of ReadExReq hits
976system.cpu.l2cache.ReadExReq_hits::total 156374 # number of ReadExReq hits
977system.cpu.l2cache.demand_hits::cpu.dtb.walker 106895 # number of demand (read+write) hits
978system.cpu.l2cache.demand_hits::cpu.itb.walker 8720 # number of demand (read+write) hits
979system.cpu.l2cache.demand_hits::cpu.inst 1055914 # number of demand (read+write) hits
980system.cpu.l2cache.demand_hits::cpu.data 1500866 # number of demand (read+write) hits
981system.cpu.l2cache.demand_hits::total 2672395 # number of demand (read+write) hits
982system.cpu.l2cache.overall_hits::cpu.dtb.walker 106895 # number of overall hits
983system.cpu.l2cache.overall_hits::cpu.itb.walker 8720 # number of overall hits
984system.cpu.l2cache.overall_hits::cpu.inst 1055914 # number of overall hits
985system.cpu.l2cache.overall_hits::cpu.data 1500866 # number of overall hits
986system.cpu.l2cache.overall_hits::total 2672395 # number of overall hits
987system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses
988system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
989system.cpu.l2cache.ReadReq_misses::cpu.inst 16902 # number of ReadReq misses
990system.cpu.l2cache.ReadReq_misses::cpu.data 37251 # number of ReadReq misses
991system.cpu.l2cache.ReadReq_misses::total 54211 # number of ReadReq misses
992system.cpu.l2cache.UpgradeReq_misses::cpu.data 3576 # number of UpgradeReq misses
993system.cpu.l2cache.UpgradeReq_misses::total 3576 # number of UpgradeReq misses
994system.cpu.l2cache.ReadExReq_misses::cpu.data 133749 # number of ReadExReq misses
995system.cpu.l2cache.ReadExReq_misses::total 133749 # number of ReadExReq misses
996system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses
997system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
998system.cpu.l2cache.demand_misses::cpu.inst 16902 # number of demand (read+write) misses
999system.cpu.l2cache.demand_misses::cpu.data 171000 # number of demand (read+write) misses
1000system.cpu.l2cache.demand_misses::total 187960 # number of demand (read+write) misses
1001system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses
1002system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
1003system.cpu.l2cache.overall_misses::cpu.inst 16902 # number of overall misses
1004system.cpu.l2cache.overall_misses::cpu.data 171000 # number of overall misses
1005system.cpu.l2cache.overall_misses::total 187960 # number of overall misses
1006system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4573500 # number of ReadReq miss cycles
1007system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 414000 # number of ReadReq miss cycles
1008system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1004010500 # number of ReadReq miss cycles
1009system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2406198500 # number of ReadReq miss cycles
1010system.cpu.l2cache.ReadReq_miss_latency::total 3415196500 # number of ReadReq miss cycles
1011system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17041499 # number of UpgradeReq miss cycles
1012system.cpu.l2cache.UpgradeReq_miss_latency::total 17041499 # number of UpgradeReq miss cycles
1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6830930000 # number of ReadExReq miss cycles
1014system.cpu.l2cache.ReadExReq_miss_latency::total 6830930000 # number of ReadExReq miss cycles
1015system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4573500 # number of demand (read+write) miss cycles
1016system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 414000 # number of demand (read+write) miss cycles
1017system.cpu.l2cache.demand_miss_latency::cpu.inst 1004010500 # number of demand (read+write) miss cycles
1018system.cpu.l2cache.demand_miss_latency::cpu.data 9237128500 # number of demand (read+write) miss cycles
1019system.cpu.l2cache.demand_miss_latency::total 10246126500 # number of demand (read+write) miss cycles
1020system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4573500 # number of overall miss cycles
1021system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 414000 # number of overall miss cycles
1022system.cpu.l2cache.overall_miss_latency::cpu.inst 1004010500 # number of overall miss cycles
1023system.cpu.l2cache.overall_miss_latency::cpu.data 9237128500 # number of overall miss cycles
1024system.cpu.l2cache.overall_miss_latency::total 10246126500 # number of overall miss cycles
1025system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 106947 # number of ReadReq accesses(hits+misses)
1026system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8726 # number of ReadReq accesses(hits+misses)
1027system.cpu.l2cache.ReadReq_accesses::cpu.inst 1072816 # number of ReadReq accesses(hits+misses)
1028system.cpu.l2cache.ReadReq_accesses::cpu.data 1381743 # number of ReadReq accesses(hits+misses)
1029system.cpu.l2cache.ReadReq_accesses::total 2570232 # number of ReadReq accesses(hits+misses)
1030system.cpu.l2cache.Writeback_accesses::writebacks 1610734 # number of Writeback accesses(hits+misses)
1031system.cpu.l2cache.Writeback_accesses::total 1610734 # number of Writeback accesses(hits+misses)
1032system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3926 # number of UpgradeReq accesses(hits+misses)
1033system.cpu.l2cache.UpgradeReq_accesses::total 3926 # number of UpgradeReq accesses(hits+misses)
1034system.cpu.l2cache.ReadExReq_accesses::cpu.data 290123 # number of ReadExReq accesses(hits+misses)
1035system.cpu.l2cache.ReadExReq_accesses::total 290123 # number of ReadExReq accesses(hits+misses)
1036system.cpu.l2cache.demand_accesses::cpu.dtb.walker 106947 # number of demand (read+write) accesses
1037system.cpu.l2cache.demand_accesses::cpu.itb.walker 8726 # number of demand (read+write) accesses
1038system.cpu.l2cache.demand_accesses::cpu.inst 1072816 # number of demand (read+write) accesses
1039system.cpu.l2cache.demand_accesses::cpu.data 1671866 # number of demand (read+write) accesses
1040system.cpu.l2cache.demand_accesses::total 2860355 # number of demand (read+write) accesses
1041system.cpu.l2cache.overall_accesses::cpu.dtb.walker 106947 # number of overall (read+write) accesses
1042system.cpu.l2cache.overall_accesses::cpu.itb.walker 8726 # number of overall (read+write) accesses
1043system.cpu.l2cache.overall_accesses::cpu.inst 1072816 # number of overall (read+write) accesses
1044system.cpu.l2cache.overall_accesses::cpu.data 1671866 # number of overall (read+write) accesses
1045system.cpu.l2cache.overall_accesses::total 2860355 # number of overall (read+write) accesses
1046system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000486 # miss rate for ReadReq accesses
1047system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000688 # miss rate for ReadReq accesses
1048system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015755 # miss rate for ReadReq accesses
1049system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026959 # miss rate for ReadReq accesses
1050system.cpu.l2cache.ReadReq_miss_rate::total 0.021092 # miss rate for ReadReq accesses
1051system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.910851 # miss rate for UpgradeReq accesses
1052system.cpu.l2cache.UpgradeReq_miss_rate::total 0.910851 # miss rate for UpgradeReq accesses
1053system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461008 # miss rate for ReadExReq accesses
1054system.cpu.l2cache.ReadExReq_miss_rate::total 0.461008 # miss rate for ReadExReq accesses
1055system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000486 # miss rate for demand accesses
1056system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000688 # miss rate for demand accesses
1057system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015755 # miss rate for demand accesses
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1062system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015755 # miss rate for overall accesses
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971system.cpu.l2cache.Writeback_hits::writebacks 1597039 # number of Writeback hits
972system.cpu.l2cache.Writeback_hits::total 1597039 # number of Writeback hits
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974system.cpu.l2cache.UpgradeReq_hits::total 343 # number of UpgradeReq hits
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1014system.cpu.l2cache.ReadExReq_miss_latency::total 6803302500 # number of ReadExReq miss cycles
1015system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3370500 # number of demand (read+write) miss cycles
1016system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 483000 # number of demand (read+write) miss cycles
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1020system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3370500 # number of overall miss cycles
1021system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 483000 # number of overall miss cycles
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1030system.cpu.l2cache.Writeback_accesses::writebacks 1597039 # number of Writeback accesses(hits+misses)
1031system.cpu.l2cache.Writeback_accesses::total 1597039 # number of Writeback accesses(hits+misses)
1032system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4172 # number of UpgradeReq accesses(hits+misses)
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1035system.cpu.l2cache.ReadExReq_accesses::total 287400 # number of ReadExReq accesses(hits+misses)
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1046system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000453 # miss rate for ReadReq accesses
1047system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000889 # miss rate for ReadReq accesses
1048system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016055 # miss rate for ReadReq accesses
1049system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026801 # miss rate for ReadReq accesses
1050system.cpu.l2cache.ReadReq_miss_rate::total 0.021174 # miss rate for ReadReq accesses
1051system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.917785 # miss rate for UpgradeReq accesses
1052system.cpu.l2cache.UpgradeReq_miss_rate::total 0.917785 # miss rate for UpgradeReq accesses
1053system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464569 # miss rate for ReadExReq accesses
1054system.cpu.l2cache.ReadExReq_miss_rate::total 0.464569 # miss rate for ReadExReq accesses
1055system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000453 # miss rate for demand accesses
1056system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000889 # miss rate for demand accesses
1057system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016055 # miss rate for demand accesses
1058system.cpu.l2cache.demand_miss_rate::cpu.data 0.102691 # miss rate for demand accesses
1059system.cpu.l2cache.demand_miss_rate::total 0.066392 # miss rate for demand accesses
1060system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000453 # miss rate for overall accesses
1061system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000889 # miss rate for overall accesses
1062system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016055 # miss rate for overall accesses
1063system.cpu.l2cache.overall_miss_rate::cpu.data 0.102691 # miss rate for overall accesses
1064system.cpu.l2cache.overall_miss_rate::total 0.066392 # miss rate for overall accesses
1065system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70218.750000 # average ReadReq miss latency

1066system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency

1067system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59401.875518 # average ReadReq miss latency
1068system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.198813 # average ReadReq miss latency
1069system.cpu.l2cache.ReadReq_avg_miss_latency::total 62998.219918 # average ReadReq miss latency
1070system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4765.519855 # average UpgradeReq miss latency
1071system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4765.519855 # average UpgradeReq miss latency
1072system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51072.755684 # average ReadExReq miss latency
1073system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51072.755684 # average ReadExReq miss latency
1074system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87951.923077 # average overall miss latency

1067system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58908.760862 # average ReadReq miss latency
1068system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64294.549212 # average ReadReq miss latency
1069system.cpu.l2cache.ReadReq_avg_miss_latency::total 62611.745568 # average ReadReq miss latency
1070system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4613.737007 # average UpgradeReq miss latency
1071system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4613.737007 # average UpgradeReq miss latency
1072system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50954.578818 # average ReadExReq miss latency
1073system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50954.578818 # average ReadExReq miss latency
1074system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70218.750000 # average overall miss latency

1075system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency

1076system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59401.875518 # average overall miss latency
1077system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54018.295322 # average overall miss latency
1078system.cpu.l2cache.demand_avg_miss_latency::total 54512.271228 # average overall miss latency
1079system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87951.923077 # average overall miss latency

1076system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58908.760862 # average overall miss latency
1077system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53832.554057 # average overall miss latency
1078system.cpu.l2cache.demand_avg_miss_latency::total 54293.172734 # average overall miss latency
1079system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70218.750000 # average overall miss latency

1080system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency

1081system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59401.875518 # average overall miss latency
1082system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54018.295322 # average overall miss latency
1083system.cpu.l2cache.overall_avg_miss_latency::total 54512.271228 # average overall miss latency

1081system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58908.760862 # average overall miss latency
1082system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53832.554057 # average overall miss latency
1083system.cpu.l2cache.overall_avg_miss_latency::total 54293.172734 # average overall miss latency

1084system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1085system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1086system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1087system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1088system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1089system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1090system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1091system.cpu.l2cache.cache_copies 0 # number of cache copies performed

1092system.cpu.l2cache.writebacks::writebacks 103292 # number of writebacks
1093system.cpu.l2cache.writebacks::total 103292 # number of writebacks
1094system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
1095system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
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1103system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses
1104system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
1105system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16899 # number of ReadReq MSHR misses
1106system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 37249 # number of ReadReq MSHR misses
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1108system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3576 # number of UpgradeReq MSHR misses
1109system.cpu.l2cache.UpgradeReq_mshr_misses::total 3576 # number of UpgradeReq MSHR misses
1110system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133749 # number of ReadExReq MSHR misses
1111system.cpu.l2cache.ReadExReq_mshr_misses::total 133749 # number of ReadExReq MSHR misses
1112system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses
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1114system.cpu.l2cache.demand_mshr_misses::cpu.inst 16899 # number of demand (read+write) MSHR misses
1115system.cpu.l2cache.demand_mshr_misses::cpu.data 170998 # number of demand (read+write) MSHR misses
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1117system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses
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1119system.cpu.l2cache.overall_mshr_misses::cpu.inst 16899 # number of overall MSHR misses
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1123system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 336012 # number of ReadReq MSHR miss cycles
1124system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 790231830 # number of ReadReq MSHR miss cycles
1125system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936968675 # number of ReadReq MSHR miss cycles
1126system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2731448614 # number of ReadReq MSHR miss cycles
1127system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 36681056 # number of UpgradeReq MSHR miss cycles
1128system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 36681056 # number of UpgradeReq MSHR miss cycles
1129system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5103303450 # number of ReadExReq MSHR miss cycles
1130system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5103303450 # number of ReadExReq MSHR miss cycles
1131system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3912097 # number of demand (read+write) MSHR miss cycles
1132system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 336012 # number of demand (read+write) MSHR miss cycles
1133system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 790231830 # number of demand (read+write) MSHR miss cycles
1134system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7040272125 # number of demand (read+write) MSHR miss cycles
1135system.cpu.l2cache.demand_mshr_miss_latency::total 7834752064 # number of demand (read+write) MSHR miss cycles
1136system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3912097 # number of overall MSHR miss cycles
1137system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 336012 # number of overall MSHR miss cycles
1138system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 790231830 # number of overall MSHR miss cycles
1139system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7040272125 # number of overall MSHR miss cycles
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1141system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187406500 # number of ReadReq MSHR uncacheable cycles
1142system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187406500 # number of ReadReq MSHR uncacheable cycles
1143system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308380500 # number of WriteReq MSHR uncacheable cycles
1144system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308380500 # number of WriteReq MSHR uncacheable cycles
1145system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495787000 # number of overall MSHR uncacheable cycles
1146system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495787000 # number of overall MSHR uncacheable cycles
1147system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000486 # mshr miss rate for ReadReq accesses
1148system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000688 # mshr miss rate for ReadReq accesses
1149system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015752 # mshr miss rate for ReadReq accesses
1150system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026958 # mshr miss rate for ReadReq accesses
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1152system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.910851 # mshr miss rate for UpgradeReq accesses
1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.910851 # mshr miss rate for UpgradeReq accesses
1154system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461008 # mshr miss rate for ReadExReq accesses
1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461008 # mshr miss rate for ReadExReq accesses
1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000486 # mshr miss rate for demand accesses
1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000688 # mshr miss rate for demand accesses
1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015752 # mshr miss rate for demand accesses
1159system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102280 # mshr miss rate for demand accesses
1160system.cpu.l2cache.demand_mshr_miss_rate::total 0.065710 # mshr miss rate for demand accesses
1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000486 # mshr miss rate for overall accesses
1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000688 # mshr miss rate for overall accesses
1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015752 # mshr miss rate for overall accesses
1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102280 # mshr miss rate for overall accesses
1165system.cpu.l2cache.overall_mshr_miss_rate::total 0.065710 # mshr miss rate for overall accesses
1166system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75232.634615 # average ReadReq mshr miss latency
1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency
1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46762.046867 # average ReadReq mshr miss latency
1169system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52000.555048 # average ReadReq mshr miss latency
1170system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50390.152640 # average ReadReq mshr miss latency
1171system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10257.565996 # average UpgradeReq mshr miss latency
1172system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10257.565996 # average UpgradeReq mshr miss latency
1173system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38155.825090 # average ReadExReq mshr miss latency
1174system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38155.825090 # average ReadExReq mshr miss latency
1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75232.634615 # average overall mshr miss latency
1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46762.046867 # average overall mshr miss latency
1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.663557 # average overall mshr miss latency
1179system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41684.190705 # average overall mshr miss latency
1180system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75232.634615 # average overall mshr miss latency
1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46762.046867 # average overall mshr miss latency
1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.663557 # average overall mshr miss latency
1184system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41684.190705 # average overall mshr miss latency

1092system.cpu.l2cache.writebacks::writebacks 103003 # number of writebacks
1093system.cpu.l2cache.writebacks::total 103003 # number of writebacks
1094system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
1095system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1096system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
1097system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1098system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1099system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
1100system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1101system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1102system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
1103system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses
1104system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
1105system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16801 # number of ReadReq MSHR misses
1106system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36728 # number of ReadReq MSHR misses
1107system.cpu.l2cache.ReadReq_mshr_misses::total 53584 # number of ReadReq MSHR misses
1108system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3829 # number of UpgradeReq MSHR misses
1109system.cpu.l2cache.UpgradeReq_mshr_misses::total 3829 # number of UpgradeReq MSHR misses
1110system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133517 # number of ReadExReq MSHR misses
1111system.cpu.l2cache.ReadExReq_mshr_misses::total 133517 # number of ReadExReq MSHR misses
1112system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses
1113system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1114system.cpu.l2cache.demand_mshr_misses::cpu.inst 16801 # number of demand (read+write) MSHR misses
1115system.cpu.l2cache.demand_mshr_misses::cpu.data 170245 # number of demand (read+write) MSHR misses
1116system.cpu.l2cache.demand_mshr_misses::total 187101 # number of demand (read+write) MSHR misses
1117system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses
1118system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1119system.cpu.l2cache.overall_mshr_misses::cpu.inst 16801 # number of overall MSHR misses
1120system.cpu.l2cache.overall_mshr_misses::cpu.data 170245 # number of overall MSHR misses
1121system.cpu.l2cache.overall_mshr_misses::total 187101 # number of overall MSHR misses
1122system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2762092 # number of ReadReq MSHR miss cycles
1123system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 393014 # number of ReadReq MSHR miss cycles
1124system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 777293164 # number of ReadReq MSHR miss cycles
1125system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1899198022 # number of ReadReq MSHR miss cycles
1126system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2679646292 # number of ReadReq MSHR miss cycles
1127system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39323307 # number of UpgradeReq MSHR miss cycles
1128system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39323307 # number of UpgradeReq MSHR miss cycles
1129system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5078674654 # number of ReadExReq MSHR miss cycles
1130system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5078674654 # number of ReadExReq MSHR miss cycles
1131system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2762092 # number of demand (read+write) MSHR miss cycles
1132system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 393014 # number of demand (read+write) MSHR miss cycles
1133system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 777293164 # number of demand (read+write) MSHR miss cycles
1134system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6977872676 # number of demand (read+write) MSHR miss cycles
1135system.cpu.l2cache.demand_mshr_miss_latency::total 7758320946 # number of demand (read+write) MSHR miss cycles
1136system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2762092 # number of overall MSHR miss cycles
1137system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 393014 # number of overall MSHR miss cycles
1138system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 777293164 # number of overall MSHR miss cycles
1139system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6977872676 # number of overall MSHR miss cycles
1140system.cpu.l2cache.overall_mshr_miss_latency::total 7758320946 # number of overall MSHR miss cycles
1141system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187395500 # number of ReadReq MSHR uncacheable cycles
1142system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187395500 # number of ReadReq MSHR uncacheable cycles
1143system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308293000 # number of WriteReq MSHR uncacheable cycles
1144system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308293000 # number of WriteReq MSHR uncacheable cycles
1145system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495688500 # number of overall MSHR uncacheable cycles
1146system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495688500 # number of overall MSHR uncacheable cycles
1147system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for ReadReq accesses
1148system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for ReadReq accesses
1149system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for ReadReq accesses
1150system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026800 # mshr miss rate for ReadReq accesses
1151system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021173 # mshr miss rate for ReadReq accesses
1152system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.917785 # mshr miss rate for UpgradeReq accesses
1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.917785 # mshr miss rate for UpgradeReq accesses
1154system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464569 # mshr miss rate for ReadExReq accesses
1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464569 # mshr miss rate for ReadExReq accesses
1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for demand accesses
1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for demand accesses
1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for demand accesses
1159system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102691 # mshr miss rate for demand accesses
1160system.cpu.l2cache.demand_mshr_miss_rate::total 0.066391 # mshr miss rate for demand accesses
1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for overall accesses
1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for overall accesses
1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for overall accesses
1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102691 # mshr miss rate for overall accesses
1165system.cpu.l2cache.overall_mshr_miss_rate::total 0.066391 # mshr miss rate for overall accesses
1166system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average ReadReq mshr miss latency
1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average ReadReq mshr miss latency
1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46264.696387 # average ReadReq mshr miss latency
1169system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51709.813276 # average ReadReq mshr miss latency
1170system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50008.328830 # average ReadReq mshr miss latency
1171system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10269.863411 # average UpgradeReq mshr miss latency
1172system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10269.863411 # average UpgradeReq mshr miss latency
1173system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38037.663024 # average ReadExReq mshr miss latency
1174system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38037.663024 # average ReadExReq mshr miss latency
1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average overall mshr miss latency
1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average overall mshr miss latency
1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46264.696387 # average overall mshr miss latency
1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40987.240013 # average overall mshr miss latency
1179system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41465.951256 # average overall mshr miss latency
1180system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average overall mshr miss latency
1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average overall mshr miss latency
1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46264.696387 # average overall mshr miss latency
1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40987.240013 # average overall mshr miss latency
1184system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41465.951256 # average overall mshr miss latency