| stats.txt (9039:9a22621c741c) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.157514 # Number of seconds simulated 4sim_ticks 5157514159500 # Number of ticks simulated 5final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.157514 # Number of seconds simulated 4sim_ticks 5157514159500 # Number of ticks simulated 5final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 128842 # Simulator instruction rate (inst/s) 8host_op_rate 253899 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1558019011 # Simulator tick rate (ticks/s) 10host_mem_usage 389972 # Number of bytes of host memory used 11host_seconds 3310.30 # Real time elapsed on the host | 7host_inst_rate 123762 # Simulator instruction rate (inst/s) 8host_op_rate 243888 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1496586873 # Simulator tick rate (ticks/s) 10host_mem_usage 369148 # Number of bytes of host memory used 11host_seconds 3446.18 # Real time elapsed on the host |
| 12sim_insts 426506235 # Number of instructions simulated 13sim_ops 840483958 # Number of ops (including micro ops) simulated | 12sim_insts 426506235 # Number of instructions simulated 13sim_ops 840483958 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 15959488 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1257664 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 12050112 # Number of bytes written to this memory 17system.physmem.num_reads 249367 # Number of read requests responded to by this memory 18system.physmem.num_writes 188283 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 3094415 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 243851 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 2336419 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 5430833 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory 19system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory 23system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s) |
| 24system.l2c.replacements 167142 # number of replacements 25system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use 26system.l2c.total_refs 3843284 # Total number of references to valid blocks. 27system.l2c.sampled_refs 202399 # Sample count of references to valid blocks. 28system.l2c.avg_refs 18.988651 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 26702.073389 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu.dtb.walker 8.025761 # Average occupied blocks per requestor --- 85 unchanged lines hidden (view full) --- 117system.l2c.overall_accesses::cpu.itb.walker 8821 # number of overall (read+write) accesses 118system.l2c.overall_accesses::cpu.inst 1083600 # number of overall (read+write) accesses 119system.l2c.overall_accesses::cpu.data 1673275 # number of overall (read+write) accesses 120system.l2c.overall_accesses::total 2875366 # number of overall (read+write) accesses 121system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957 # miss rate for ReadReq accesses 122system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses 123system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses 124system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses | 49system.l2c.replacements 167142 # number of replacements 50system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use 51system.l2c.total_refs 3843284 # Total number of references to valid blocks. 52system.l2c.sampled_refs 202399 # Sample count of references to valid blocks. 53system.l2c.avg_refs 18.988651 # Average number of references to valid blocks. 54system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55system.l2c.occ_blocks::writebacks 26702.073389 # Average occupied blocks per requestor 56system.l2c.occ_blocks::cpu.dtb.walker 8.025761 # Average occupied blocks per requestor --- 85 unchanged lines hidden (view full) --- 142system.l2c.overall_accesses::cpu.itb.walker 8821 # number of overall (read+write) accesses 143system.l2c.overall_accesses::cpu.inst 1083600 # number of overall (read+write) accesses 144system.l2c.overall_accesses::cpu.data 1673275 # number of overall (read+write) accesses 145system.l2c.overall_accesses::total 2875366 # number of overall (read+write) accesses 146system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957 # miss rate for ReadReq accesses 147system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses 148system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses 149system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses |
| 150system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses |
|
| 125system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses | 151system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses |
| 152system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses |
|
| 126system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses | 153system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses |
| 154system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses |
|
| 127system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses 128system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses 129system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses 130system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses | 155system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses 156system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses 157system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses 158system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses |
| 159system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses |
|
| 131system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses 132system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses 133system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses 134system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses | 160system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses 161system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses 162system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses 163system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses |
| 164system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses |
|
| 135system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency 136system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency 137system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency 138system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency | 165system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency 166system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency 167system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency 168system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency |
| 169system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency |
|
| 139system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency | 170system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency |
| 171system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency |
|
| 140system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency | 172system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency |
| 173system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency |
|
| 141system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency 142system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency 143system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency 144system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency | 174system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency 175system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency 176system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency 177system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency |
| 178system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency |
|
| 145system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency 146system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency 147system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency 148system.l2c.overall_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency | 179system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency 180system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency 181system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency 182system.l2c.overall_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency |
| 183system.l2c.overall_avg_miss_latency::total 52201.292100 # average overall miss latency |
|
| 149system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 150system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 151system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 152system.l2c.blocked::no_targets 0 # number of cycles access was blocked 153system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 154system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 155system.l2c.fast_writes 0 # number of fast writes performed 156system.l2c.cache_copies 0 # number of cache copies performed --- 51 unchanged lines hidden (view full) --- 208system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1229367500 # number of WriteReq MSHR uncacheable cycles 209system.l2c.WriteReq_mshr_uncacheable_latency::total 1229367500 # number of WriteReq MSHR uncacheable cycles 210system.l2c.overall_mshr_uncacheable_latency::cpu.data 61204770000 # number of overall MSHR uncacheable cycles 211system.l2c.overall_mshr_uncacheable_latency::total 61204770000 # number of overall MSHR uncacheable cycles 212system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for ReadReq accesses 213system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for ReadReq accesses 214system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for ReadReq accesses 215system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.033076 # mshr miss rate for ReadReq accesses | 184system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 185system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 186system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 187system.l2c.blocked::no_targets 0 # number of cycles access was blocked 188system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 190system.l2c.fast_writes 0 # number of fast writes performed 191system.l2c.cache_copies 0 # number of cache copies performed --- 51 unchanged lines hidden (view full) --- 243system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1229367500 # number of WriteReq MSHR uncacheable cycles 244system.l2c.WriteReq_mshr_uncacheable_latency::total 1229367500 # number of WriteReq MSHR uncacheable cycles 245system.l2c.overall_mshr_uncacheable_latency::cpu.data 61204770000 # number of overall MSHR uncacheable cycles 246system.l2c.overall_mshr_uncacheable_latency::total 61204770000 # number of overall MSHR uncacheable cycles 247system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for ReadReq accesses 248system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for ReadReq accesses 249system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for ReadReq accesses 250system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.033076 # mshr miss rate for ReadReq accesses |
| 251system.l2c.ReadReq_mshr_miss_rate::total 0.025337 # mshr miss rate for ReadReq accesses |
|
| 216system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.882394 # mshr miss rate for UpgradeReq accesses | 252system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.882394 # mshr miss rate for UpgradeReq accesses |
| 253system.l2c.UpgradeReq_mshr_miss_rate::total 0.882394 # mshr miss rate for UpgradeReq accesses |
|
| 217system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.481904 # mshr miss rate for ReadExReq accesses | 254system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.481904 # mshr miss rate for ReadExReq accesses |
| 255system.l2c.ReadExReq_mshr_miss_rate::total 0.481904 # mshr miss rate for ReadExReq accesses |
|
| 218system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for demand accesses 219system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for demand accesses 220system.l2c.demand_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for demand accesses 221system.l2c.demand_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for demand accesses | 256system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for demand accesses 257system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for demand accesses 258system.l2c.demand_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for demand accesses 259system.l2c.demand_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for demand accesses |
| 260system.l2c.demand_mshr_miss_rate::total 0.071838 # mshr miss rate for demand accesses |
|
| 222system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for overall accesses 223system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for overall accesses 224system.l2c.overall_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for overall accesses 225system.l2c.overall_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for overall accesses | 261system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for overall accesses 262system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for overall accesses 263system.l2c.overall_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for overall accesses 264system.l2c.overall_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for overall accesses |
| 265system.l2c.overall_mshr_miss_rate::total 0.071838 # mshr miss rate for overall accesses |
|
| 226system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average ReadReq mshr miss latency 227system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 228system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency 229system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency | 266system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average ReadReq mshr miss latency 267system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 268system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency 269system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency |
| 270system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency |
|
| 230system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency | 271system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency |
| 272system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency |
|
| 231system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency | 273system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency |
| 274system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency |
|
| 232system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency 233system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 234system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency 235system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency | 275system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency 276system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 277system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency 278system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency |
| 279system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency |
|
| 236system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency 237system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 238system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency 239system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency | 280system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency 281system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 282system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency 283system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency |
| 284system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency |
|
| 240system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency | 285system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency |
| 286system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 241system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency | 287system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |
| 288system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 242system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency | 289system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency |
| 290system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 243system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 244system.iocache.replacements 47578 # number of replacements 245system.iocache.tagsinuse 0.166155 # Cycle average of tags in use 246system.iocache.total_refs 0 # Total number of references to valid blocks. 247system.iocache.sampled_refs 47594 # Sample count of references to valid blocks. 248system.iocache.avg_refs 0 # Average number of references to valid blocks. 249system.iocache.warmup_cycle 4996370640000 # Cycle when the warmup percentage was hit. 250system.iocache.occ_blocks::pc.south_bridge.ide 0.166155 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 270system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) 271system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 272system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 273system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses 274system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses 275system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses 276system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses 277system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses | 291system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 292system.iocache.replacements 47578 # number of replacements 293system.iocache.tagsinuse 0.166155 # Cycle average of tags in use 294system.iocache.total_refs 0 # Total number of references to valid blocks. 295system.iocache.sampled_refs 47594 # Sample count of references to valid blocks. 296system.iocache.avg_refs 0 # Average number of references to valid blocks. 297system.iocache.warmup_cycle 4996370640000 # Cycle when the warmup percentage was hit. 298system.iocache.occ_blocks::pc.south_bridge.ide 0.166155 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 318system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) 319system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 320system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 321system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses 322system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses 323system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses 324system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses 325system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses |
| 326system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
|
| 278system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses | 327system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses |
| 328system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses |
|
| 279system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses | 329system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses |
| 330system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses |
|
| 280system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses | 331system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses |
| 332system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
|
| 281system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency | 333system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency |
| 334system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency |
|
| 282system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency | 335system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency |
| 336system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency |
|
| 283system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency | 337system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency |
| 338system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency |
|
| 284system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency | 339system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency |
| 340system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency |
|
| 285system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked 286system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 287system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked 288system.iocache.blocked::no_targets 0 # number of cycles access was blocked 289system.iocache.avg_blocked_cycles::no_mshrs 6125.258142 # average number of cycles each access was blocked 290system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 291system.iocache.fast_writes 0 # number of fast writes performed 292system.iocache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 304system.iocache.ReadReq_mshr_miss_latency::total 66880982 # number of ReadReq MSHR miss cycles 305system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3943643878 # number of WriteReq MSHR miss cycles 306system.iocache.WriteReq_mshr_miss_latency::total 3943643878 # number of WriteReq MSHR miss cycles 307system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of demand (read+write) MSHR miss cycles 308system.iocache.demand_mshr_miss_latency::total 4010524860 # number of demand (read+write) MSHR miss cycles 309system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles 310system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles 311system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses | 341system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked 342system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked 344system.iocache.blocked::no_targets 0 # number of cycles access was blocked 345system.iocache.avg_blocked_cycles::no_mshrs 6125.258142 # average number of cycles each access was blocked 346system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.iocache.fast_writes 0 # number of fast writes performed 348system.iocache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 360system.iocache.ReadReq_mshr_miss_latency::total 66880982 # number of ReadReq MSHR miss cycles 361system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3943643878 # number of WriteReq MSHR miss cycles 362system.iocache.WriteReq_mshr_miss_latency::total 3943643878 # number of WriteReq MSHR miss cycles 363system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of demand (read+write) MSHR miss cycles 364system.iocache.demand_mshr_miss_latency::total 4010524860 # number of demand (read+write) MSHR miss cycles 365system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles 366system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles 367system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses |
| 368system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
|
| 312system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses | 369system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses |
| 370system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses |
|
| 313system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses | 371system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses |
| 372system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses |
|
| 314system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses | 373system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses |
| 374system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
|
| 315system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency | 375system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency |
| 376system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency |
|
| 316system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency | 377system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency |
| 378system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency |
|
| 317system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency | 379system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency |
| 380system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency |
|
| 318system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency | 381system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency |
| 382system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency |
|
| 319system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 320system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 321system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 322system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 323system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 324system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 325system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 326system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 303 unchanged lines hidden (view full) --- 630system.cpu.icache.overall_miss_latency::total 17226505491 # number of overall miss cycles 631system.cpu.icache.ReadReq_accesses::cpu.inst 9366799 # number of ReadReq accesses(hits+misses) 632system.cpu.icache.ReadReq_accesses::total 9366799 # number of ReadReq accesses(hits+misses) 633system.cpu.icache.demand_accesses::cpu.inst 9366799 # number of demand (read+write) accesses 634system.cpu.icache.demand_accesses::total 9366799 # number of demand (read+write) accesses 635system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses 636system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses 637system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses | 383system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 384system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 385system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 386system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 387system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 388system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 389system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 390system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 303 unchanged lines hidden (view full) --- 694system.cpu.icache.overall_miss_latency::total 17226505491 # number of overall miss cycles 695system.cpu.icache.ReadReq_accesses::cpu.inst 9366799 # number of ReadReq accesses(hits+misses) 696system.cpu.icache.ReadReq_accesses::total 9366799 # number of ReadReq accesses(hits+misses) 697system.cpu.icache.demand_accesses::cpu.inst 9366799 # number of demand (read+write) accesses 698system.cpu.icache.demand_accesses::total 9366799 # number of demand (read+write) accesses 699system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses 700system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses 701system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses |
| 702system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses |
|
| 638system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses | 703system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses |
| 704system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses |
|
| 639system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses | 705system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses |
| 706system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses |
|
| 640system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency | 707system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency |
| 708system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency |
|
| 641system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency | 709system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency |
| 710system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency |
|
| 642system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency | 711system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency |
| 712system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency |
|
| 643system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked 644system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked 646system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 647system.cpu.icache.avg_blocked_cycles::no_mshrs 10077.826990 # average number of cycles each access was blocked 648system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.cpu.icache.fast_writes 0 # number of fast writes performed 650system.cpu.icache.cache_copies 0 # number of cache copies performed --- 13 unchanged lines hidden (view full) --- 664system.cpu.icache.overall_mshr_misses::total 1084802 # number of overall MSHR misses 665system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13093471492 # number of ReadReq MSHR miss cycles 666system.cpu.icache.ReadReq_mshr_miss_latency::total 13093471492 # number of ReadReq MSHR miss cycles 667system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13093471492 # number of demand (read+write) MSHR miss cycles 668system.cpu.icache.demand_mshr_miss_latency::total 13093471492 # number of demand (read+write) MSHR miss cycles 669system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles 670system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # number of overall MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for ReadReq accesses | 713system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked 714system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 715system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked 716system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 717system.cpu.icache.avg_blocked_cycles::no_mshrs 10077.826990 # average number of cycles each access was blocked 718system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 719system.cpu.icache.fast_writes 0 # number of fast writes performed 720system.cpu.icache.cache_copies 0 # number of cache copies performed --- 13 unchanged lines hidden (view full) --- 734system.cpu.icache.overall_mshr_misses::total 1084802 # number of overall MSHR misses 735system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13093471492 # number of ReadReq MSHR miss cycles 736system.cpu.icache.ReadReq_mshr_miss_latency::total 13093471492 # number of ReadReq MSHR miss cycles 737system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13093471492 # number of demand (read+write) MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::total 13093471492 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # number of overall MSHR miss cycles 741system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for ReadReq accesses |
| 742system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115814 # mshr miss rate for ReadReq accesses |
|
| 672system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for demand accesses | 743system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for demand accesses |
| 744system.cpu.icache.demand_mshr_miss_rate::total 0.115814 # mshr miss rate for demand accesses |
|
| 673system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for overall accesses | 745system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for overall accesses |
| 746system.cpu.icache.overall_mshr_miss_rate::total 0.115814 # mshr miss rate for overall accesses |
|
| 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282 # average ReadReq mshr miss latency | 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282 # average ReadReq mshr miss latency |
| 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282 # average ReadReq mshr miss latency |
|
| 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency | 749system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency |
| 750system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency |
|
| 676system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency | 751system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency |
| 752system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency |
|
| 677system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 678system.cpu.itb_walker_cache.replacements 10825 # number of replacements 679system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use 680system.cpu.itb_walker_cache.total_refs 27185 # Total number of references to valid blocks. 681system.cpu.itb_walker_cache.sampled_refs 10834 # Sample count of references to valid blocks. 682system.cpu.itb_walker_cache.avg_refs 2.509230 # Average number of references to valid blocks. 683system.cpu.itb_walker_cache.warmup_cycle 5135028893000 # Cycle when the warmup percentage was hit. 684system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.011393 # Average occupied blocks per requestor --- 23 unchanged lines hidden (view full) --- 708system.cpu.itb_walker_cache.ReadReq_accesses::total 39094 # number of ReadReq accesses(hits+misses) 709system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) 710system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 711system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39097 # number of demand (read+write) accesses 712system.cpu.itb_walker_cache.demand_accesses::total 39097 # number of demand (read+write) accesses 713system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39097 # number of overall (read+write) accesses 714system.cpu.itb_walker_cache.overall_accesses::total 39097 # number of overall (read+write) accesses 715system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298946 # miss rate for ReadReq accesses | 753system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 754system.cpu.itb_walker_cache.replacements 10825 # number of replacements 755system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use 756system.cpu.itb_walker_cache.total_refs 27185 # Total number of references to valid blocks. 757system.cpu.itb_walker_cache.sampled_refs 10834 # Sample count of references to valid blocks. 758system.cpu.itb_walker_cache.avg_refs 2.509230 # Average number of references to valid blocks. 759system.cpu.itb_walker_cache.warmup_cycle 5135028893000 # Cycle when the warmup percentage was hit. 760system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.011393 # Average occupied blocks per requestor --- 23 unchanged lines hidden (view full) --- 784system.cpu.itb_walker_cache.ReadReq_accesses::total 39094 # number of ReadReq accesses(hits+misses) 785system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) 786system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 787system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39097 # number of demand (read+write) accesses 788system.cpu.itb_walker_cache.demand_accesses::total 39097 # number of demand (read+write) accesses 789system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39097 # number of overall (read+write) accesses 790system.cpu.itb_walker_cache.overall_accesses::total 39097 # number of overall (read+write) accesses 791system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298946 # miss rate for ReadReq accesses |
| 792system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298946 # miss rate for ReadReq accesses |
|
| 716system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298923 # miss rate for demand accesses | 793system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298923 # miss rate for demand accesses |
| 794system.cpu.itb_walker_cache.demand_miss_rate::total 0.298923 # miss rate for demand accesses |
|
| 717system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298923 # miss rate for overall accesses | 795system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298923 # miss rate for overall accesses |
| 796system.cpu.itb_walker_cache.overall_miss_rate::total 0.298923 # miss rate for overall accesses |
|
| 718system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308 # average ReadReq miss latency | 797system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308 # average ReadReq miss latency |
| 798system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308 # average ReadReq miss latency |
|
| 719system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency | 799system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency |
| 800system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308 # average overall miss latency |
|
| 720system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency | 801system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency |
| 802system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308 # average overall miss latency |
|
| 721system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 722system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 725system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 728system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 736system.cpu.itb_walker_cache.overall_mshr_misses::total 11687 # number of overall MSHR misses 737system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 112719500 # number of ReadReq MSHR miss cycles 738system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 112719500 # number of ReadReq MSHR miss cycles 739system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 112719500 # number of demand (read+write) MSHR miss cycles 740system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500 # number of demand (read+write) MSHR miss cycles 741system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles 742system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles 743system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses | 803system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 804system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 805system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 806system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 807system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 808system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 809system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 810system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 818system.cpu.itb_walker_cache.overall_mshr_misses::total 11687 # number of overall MSHR misses 819system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 112719500 # number of ReadReq MSHR miss cycles 820system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 112719500 # number of ReadReq MSHR miss cycles 821system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 112719500 # number of demand (read+write) MSHR miss cycles 822system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500 # number of demand (read+write) MSHR miss cycles 823system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles 824system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles 825system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses |
| 826system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses |
|
| 744system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses | 827system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses |
| 828system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses |
|
| 745system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses | 829system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses |
| 830system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses |
|
| 746system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency | 831system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency |
| 832system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency |
|
| 747system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency | 833system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency |
| 834system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency |
|
| 748system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency | 835system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency |
| 836system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency |
|
| 749system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 750system.cpu.dtb_walker_cache.replacements 116553 # number of replacements 751system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use 752system.cpu.dtb_walker_cache.total_refs 135956 # Total number of references to valid blocks. 753system.cpu.dtb_walker_cache.sampled_refs 116568 # Sample count of references to valid blocks. 754system.cpu.dtb_walker_cache.avg_refs 1.166324 # Average number of references to valid blocks. 755system.cpu.dtb_walker_cache.warmup_cycle 5108641793000 # Cycle when the warmup percentage was hit. 756system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.859632 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 776system.cpu.dtb_walker_cache.overall_miss_latency::total 1642151000 # number of overall miss cycles 777system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 253531 # number of ReadReq accesses(hits+misses) 778system.cpu.dtb_walker_cache.ReadReq_accesses::total 253531 # number of ReadReq accesses(hits+misses) 779system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 253531 # number of demand (read+write) accesses 780system.cpu.dtb_walker_cache.demand_accesses::total 253531 # number of demand (read+write) accesses 781system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses 782system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses 783system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses | 837system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 838system.cpu.dtb_walker_cache.replacements 116553 # number of replacements 839system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use 840system.cpu.dtb_walker_cache.total_refs 135956 # Total number of references to valid blocks. 841system.cpu.dtb_walker_cache.sampled_refs 116568 # Sample count of references to valid blocks. 842system.cpu.dtb_walker_cache.avg_refs 1.166324 # Average number of references to valid blocks. 843system.cpu.dtb_walker_cache.warmup_cycle 5108641793000 # Cycle when the warmup percentage was hit. 844system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.859632 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 864system.cpu.dtb_walker_cache.overall_miss_latency::total 1642151000 # number of overall miss cycles 865system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 253531 # number of ReadReq accesses(hits+misses) 866system.cpu.dtb_walker_cache.ReadReq_accesses::total 253531 # number of ReadReq accesses(hits+misses) 867system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 253531 # number of demand (read+write) accesses 868system.cpu.dtb_walker_cache.demand_accesses::total 253531 # number of demand (read+write) accesses 869system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses 870system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses 871system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses |
| 872system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses |
|
| 784system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses | 873system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses |
| 874system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses |
|
| 785system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses | 875system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses |
| 876system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses |
|
| 786system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency | 877system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency |
| 878system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency |
|
| 787system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency | 879system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency |
| 880system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency |
|
| 788system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency | 881system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency |
| 882system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency |
|
| 789system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 790system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 791system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 792system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 793system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 794system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 795system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 796system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 804system.cpu.dtb_walker_cache.overall_mshr_misses::total 117570 # number of overall MSHR misses 805system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of ReadReq MSHR miss cycles 806system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1286519500 # number of ReadReq MSHR miss cycles 807system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of demand (read+write) MSHR miss cycles 808system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500 # number of demand (read+write) MSHR miss cycles 809system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles 810system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles 811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses | 883system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 884system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 885system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 886system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 887system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 888system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 889system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 890system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 898system.cpu.dtb_walker_cache.overall_mshr_misses::total 117570 # number of overall MSHR misses 899system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of ReadReq MSHR miss cycles 900system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1286519500 # number of ReadReq MSHR miss cycles 901system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of demand (read+write) MSHR miss cycles 902system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500 # number of demand (read+write) MSHR miss cycles 903system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles 904system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles 905system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses |
| 906system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses |
|
| 812system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses | 907system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses |
| 908system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses |
|
| 813system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses | 909system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses |
| 910system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses |
|
| 814system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency | 911system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency |
| 912system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency |
|
| 815system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency | 913system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency |
| 914system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency |
|
| 816system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency | 915system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency |
| 916system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency |
|
| 817system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 818system.cpu.dcache.replacements 1673290 # number of replacements 819system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use 820system.cpu.dcache.total_refs 19026186 # Total number of references to valid blocks. 821system.cpu.dcache.sampled_refs 1673802 # Sample count of references to valid blocks. 822system.cpu.dcache.avg_refs 11.367047 # Average number of references to valid blocks. 823system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. 824system.cpu.dcache.occ_blocks::cpu.data 511.997033 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 852system.cpu.dcache.ReadReq_accesses::total 13354746 # number of ReadReq accesses(hits+misses) 853system.cpu.dcache.WriteReq_accesses::cpu.data 8397244 # number of WriteReq accesses(hits+misses) 854system.cpu.dcache.WriteReq_accesses::total 8397244 # number of WriteReq accesses(hits+misses) 855system.cpu.dcache.demand_accesses::cpu.data 21751990 # number of demand (read+write) accesses 856system.cpu.dcache.demand_accesses::total 21751990 # number of demand (read+write) accesses 857system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses 858system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses 859system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses | 917system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 918system.cpu.dcache.replacements 1673290 # number of replacements 919system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use 920system.cpu.dcache.total_refs 19026186 # Total number of references to valid blocks. 921system.cpu.dcache.sampled_refs 1673802 # Sample count of references to valid blocks. 922system.cpu.dcache.avg_refs 11.367047 # Average number of references to valid blocks. 923system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. 924system.cpu.dcache.occ_blocks::cpu.data 511.997033 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 952system.cpu.dcache.ReadReq_accesses::total 13354746 # number of ReadReq accesses(hits+misses) 953system.cpu.dcache.WriteReq_accesses::cpu.data 8397244 # number of WriteReq accesses(hits+misses) 954system.cpu.dcache.WriteReq_accesses::total 8397244 # number of WriteReq accesses(hits+misses) 955system.cpu.dcache.demand_accesses::cpu.data 21751990 # number of demand (read+write) accesses 956system.cpu.dcache.demand_accesses::total 21751990 # number of demand (read+write) accesses 957system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses 958system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses 959system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses |
| 960system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses |
|
| 860system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses | 961system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses |
| 962system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses |
|
| 861system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses | 963system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses |
| 964system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses |
|
| 862system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses | 965system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses |
| 966system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses |
|
| 863system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency | 967system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency |
| 968system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency |
|
| 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency | 969system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency |
| 970system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency |
|
| 865system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency | 971system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency |
| 972system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency |
|
| 866system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency | 973system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency |
| 974system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency |
|
| 867system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked 868system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 869system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked 870system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 871system.cpu.dcache.avg_blocked_cycles::no_mshrs 6822.145924 # average number of cycles each access was blocked 872system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 873system.cpu.dcache.fast_writes 0 # number of fast writes performed 874system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 25 unchanged lines hidden (view full) --- 900system.cpu.dcache.overall_mshr_miss_latency::total 27527126997 # number of overall MSHR miss cycles 901system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207754500 # number of ReadReq MSHR uncacheable cycles 902system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207754500 # number of ReadReq MSHR uncacheable cycles 903system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392930500 # number of WriteReq MSHR uncacheable cycles 904system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500 # number of WriteReq MSHR uncacheable cycles 905system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles 906system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles 907system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses | 975system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked 976system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 977system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked 978system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 979system.cpu.dcache.avg_blocked_cycles::no_mshrs 6822.145924 # average number of cycles each access was blocked 980system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 981system.cpu.dcache.fast_writes 0 # number of fast writes performed 982system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 25 unchanged lines hidden (view full) --- 1008system.cpu.dcache.overall_mshr_miss_latency::total 27527126997 # number of overall MSHR miss cycles 1009system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207754500 # number of ReadReq MSHR uncacheable cycles 1010system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207754500 # number of ReadReq MSHR uncacheable cycles 1011system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392930500 # number of WriteReq MSHR uncacheable cycles 1012system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500 # number of WriteReq MSHR uncacheable cycles 1013system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles 1014system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles 1015system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses |
| 1016system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses |
|
| 908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses | 1017system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses |
| 1018system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses |
|
| 909system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses | 1019system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses |
| 1020system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses |
|
| 910system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses | 1021system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses |
| 1022system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses |
|
| 911system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency | 1023system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency |
| 1024system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency |
|
| 912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency | 1025system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency |
| 1026system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency |
|
| 913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency | 1027system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency |
| 1028system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency |
|
| 914system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency | 1029system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency |
| 1030system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency |
|
| 915system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency | 1031system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency |
| 1032system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 916system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency | 1033system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |
| 1034system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 917system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency | 1035system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency |
| 1036system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 918system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 919system.cpu.kern.inst.arm 0 # number of arm instructions executed 920system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 921 922---------- End Simulation Statistics ---------- | 1037system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1038system.cpu.kern.inst.arm 0 # number of arm instructions executed 1039system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1040 1041---------- End Simulation Statistics ---------- |