| stats.txt (8963:91a6f8f07074) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.169500 # Number of seconds simulated 4sim_ticks 5169499540500 # Number of ticks simulated 5final_tick 5169499540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.169500 # Number of seconds simulated 4sim_ticks 5169499540500 # Number of ticks simulated 5final_tick 5169499540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 164266 # Simulator instruction rate (inst/s) 8host_op_rate 323704 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1990886287 # Simulator tick rate (ticks/s) 10host_mem_usage 388036 # Number of bytes of host memory used 11host_seconds 2596.58 # Real time elapsed on the host | 7host_inst_rate 77808 # Simulator instruction rate (inst/s) 8host_op_rate 153328 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 943017240 # Simulator tick rate (ticks/s) 10host_mem_usage 366644 # Number of bytes of host memory used 11host_seconds 5481.87 # Real time elapsed on the host |
| 12sim_insts 426530860 # Number of instructions simulated 13sim_ops 840523890 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 15909184 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1237824 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 12067392 # Number of bytes written to this memory 17system.physmem.num_reads 248581 # Number of read requests responded to by this memory 18system.physmem.num_writes 188553 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 125 unchanged lines hidden (view full) --- 145system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency 146system.l2c.overall_avg_miss_latency::cpu.itb.walker 52136.363636 # average overall miss latency 147system.l2c.overall_avg_miss_latency::cpu.inst 52254.704788 # average overall miss latency 148system.l2c.overall_avg_miss_latency::cpu.data 52195.630938 # average overall miss latency 149system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 150system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 151system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 152system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 426530860 # Number of instructions simulated 13sim_ops 840523890 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 15909184 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1237824 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 12067392 # Number of bytes written to this memory 17system.physmem.num_reads 248581 # Number of read requests responded to by this memory 18system.physmem.num_writes 188553 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 125 unchanged lines hidden (view full) --- 145system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency 146system.l2c.overall_avg_miss_latency::cpu.itb.walker 52136.363636 # average overall miss latency 147system.l2c.overall_avg_miss_latency::cpu.inst 52254.704788 # average overall miss latency 148system.l2c.overall_avg_miss_latency::cpu.data 52195.630938 # average overall miss latency 149system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 150system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 151system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 152system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 153system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 154system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 153system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 154system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 155system.l2c.fast_writes 0 # number of fast writes performed 156system.l2c.cache_copies 0 # number of cache copies performed 157system.l2c.writebacks::writebacks 141885 # number of writebacks 158system.l2c.writebacks::total 141885 # number of writebacks 159system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 160system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 161system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 162system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits --- 119 unchanged lines hidden (view full) --- 282system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136430.889555 # average WriteReq miss latency 283system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136217.759274 # average overall miss latency 284system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136217.759274 # average overall miss latency 285system.iocache.blocked_cycles::no_mshrs 68852524 # number of cycles access was blocked 286system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 287system.iocache.blocked::no_mshrs 11251 # number of cycles access was blocked 288system.iocache.blocked::no_targets 0 # number of cycles access was blocked 289system.iocache.avg_blocked_cycles::no_mshrs 6119.680384 # average number of cycles each access was blocked | 155system.l2c.fast_writes 0 # number of fast writes performed 156system.l2c.cache_copies 0 # number of cache copies performed 157system.l2c.writebacks::writebacks 141885 # number of writebacks 158system.l2c.writebacks::total 141885 # number of writebacks 159system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 160system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 161system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 162system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits --- 119 unchanged lines hidden (view full) --- 282system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136430.889555 # average WriteReq miss latency 283system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136217.759274 # average overall miss latency 284system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136217.759274 # average overall miss latency 285system.iocache.blocked_cycles::no_mshrs 68852524 # number of cycles access was blocked 286system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 287system.iocache.blocked::no_mshrs 11251 # number of cycles access was blocked 288system.iocache.blocked::no_targets 0 # number of cycles access was blocked 289system.iocache.avg_blocked_cycles::no_mshrs 6119.680384 # average number of cycles each access was blocked |
| 290system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 290system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 291system.iocache.fast_writes 0 # number of fast writes performed 292system.iocache.cache_copies 0 # number of cache copies performed 293system.iocache.writebacks::writebacks 46668 # number of writebacks 294system.iocache.writebacks::total 46668 # number of writebacks 295system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 296system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses 297system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 298system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses --- 341 unchanged lines hidden (view full) --- 640system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14917.938858 # average ReadReq miss latency 641system.cpu.icache.demand_avg_miss_latency::cpu.inst 14917.938858 # average overall miss latency 642system.cpu.icache.overall_avg_miss_latency::cpu.inst 14917.938858 # average overall miss latency 643system.cpu.icache.blocked_cycles::no_mshrs 2880990 # number of cycles access was blocked 644system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked 646system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 647system.cpu.icache.avg_blocked_cycles::no_mshrs 9866.404110 # average number of cycles each access was blocked | 291system.iocache.fast_writes 0 # number of fast writes performed 292system.iocache.cache_copies 0 # number of cache copies performed 293system.iocache.writebacks::writebacks 46668 # number of writebacks 294system.iocache.writebacks::total 46668 # number of writebacks 295system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 296system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses 297system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 298system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses --- 341 unchanged lines hidden (view full) --- 640system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14917.938858 # average ReadReq miss latency 641system.cpu.icache.demand_avg_miss_latency::cpu.inst 14917.938858 # average overall miss latency 642system.cpu.icache.overall_avg_miss_latency::cpu.inst 14917.938858 # average overall miss latency 643system.cpu.icache.blocked_cycles::no_mshrs 2880990 # number of cycles access was blocked 644system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked 646system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 647system.cpu.icache.avg_blocked_cycles::no_mshrs 9866.404110 # average number of cycles each access was blocked |
| 648system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 648system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 649system.cpu.icache.fast_writes 0 # number of fast writes performed 650system.cpu.icache.cache_copies 0 # number of cache copies performed 651system.cpu.icache.writebacks::writebacks 1570 # number of writebacks 652system.cpu.icache.writebacks::total 1570 # number of writebacks 653system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69061 # number of ReadReq MSHR hits 654system.cpu.icache.ReadReq_mshr_hits::total 69061 # number of ReadReq MSHR hits 655system.cpu.icache.demand_mshr_hits::cpu.inst 69061 # number of demand (read+write) MSHR hits 656system.cpu.icache.demand_mshr_hits::total 69061 # number of demand (read+write) MSHR hits --- 60 unchanged lines hidden (view full) --- 717system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298447 # miss rate for overall accesses 718system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12732.840115 # average ReadReq miss latency 719system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12732.840115 # average overall miss latency 720system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12732.840115 # average overall miss latency 721system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 722system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked | 649system.cpu.icache.fast_writes 0 # number of fast writes performed 650system.cpu.icache.cache_copies 0 # number of cache copies performed 651system.cpu.icache.writebacks::writebacks 1570 # number of writebacks 652system.cpu.icache.writebacks::total 1570 # number of writebacks 653system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69061 # number of ReadReq MSHR hits 654system.cpu.icache.ReadReq_mshr_hits::total 69061 # number of ReadReq MSHR hits 655system.cpu.icache.demand_mshr_hits::cpu.inst 69061 # number of demand (read+write) MSHR hits 656system.cpu.icache.demand_mshr_hits::total 69061 # number of demand (read+write) MSHR hits --- 60 unchanged lines hidden (view full) --- 717system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298447 # miss rate for overall accesses 718system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12732.840115 # average ReadReq miss latency 719system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12732.840115 # average overall miss latency 720system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12732.840115 # average overall miss latency 721system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 722system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked |
| 725system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 726system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 725system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 727system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 728system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 729system.cpu.itb_walker_cache.writebacks::writebacks 1487 # number of writebacks 730system.cpu.itb_walker_cache.writebacks::total 1487 # number of writebacks 731system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12165 # number of ReadReq MSHR misses 732system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12165 # number of ReadReq MSHR misses 733system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12165 # number of demand (read+write) MSHR misses 734system.cpu.itb_walker_cache.demand_mshr_misses::total 12165 # number of demand (read+write) MSHR misses --- 50 unchanged lines hidden (view full) --- 785system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468686 # miss rate for overall accesses 786system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13905.299553 # average ReadReq miss latency 787system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13905.299553 # average overall miss latency 788system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13905.299553 # average overall miss latency 789system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 790system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 791system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 792system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked | 727system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 728system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 729system.cpu.itb_walker_cache.writebacks::writebacks 1487 # number of writebacks 730system.cpu.itb_walker_cache.writebacks::total 1487 # number of writebacks 731system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12165 # number of ReadReq MSHR misses 732system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12165 # number of ReadReq MSHR misses 733system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12165 # number of demand (read+write) MSHR misses 734system.cpu.itb_walker_cache.demand_mshr_misses::total 12165 # number of demand (read+write) MSHR misses --- 50 unchanged lines hidden (view full) --- 785system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468686 # miss rate for overall accesses 786system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13905.299553 # average ReadReq miss latency 787system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13905.299553 # average overall miss latency 788system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13905.299553 # average overall miss latency 789system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 790system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 791system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 792system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked |
| 793system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 794system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 793system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 794system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 795system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 796system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 797system.cpu.dtb_walker_cache.writebacks::writebacks 34129 # number of writebacks 798system.cpu.dtb_walker_cache.writebacks::total 34129 # number of writebacks 799system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118727 # number of ReadReq MSHR misses 800system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118727 # number of ReadReq MSHR misses 801system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118727 # number of demand (read+write) MSHR misses 802system.cpu.dtb_walker_cache.demand_mshr_misses::total 118727 # number of demand (read+write) MSHR misses --- 61 unchanged lines hidden (view full) --- 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33240.856104 # average WriteReq miss latency 865system.cpu.dcache.demand_avg_miss_latency::cpu.data 17118.025524 # average overall miss latency 866system.cpu.dcache.overall_avg_miss_latency::cpu.data 17118.025524 # average overall miss latency 867system.cpu.dcache.blocked_cycles::no_mshrs 23782481 # number of cycles access was blocked 868system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 869system.cpu.dcache.blocked::no_mshrs 3499 # number of cycles access was blocked 870system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 871system.cpu.dcache.avg_blocked_cycles::no_mshrs 6796.936553 # average number of cycles each access was blocked | 795system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 796system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 797system.cpu.dtb_walker_cache.writebacks::writebacks 34129 # number of writebacks 798system.cpu.dtb_walker_cache.writebacks::total 34129 # number of writebacks 799system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118727 # number of ReadReq MSHR misses 800system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118727 # number of ReadReq MSHR misses 801system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118727 # number of demand (read+write) MSHR misses 802system.cpu.dtb_walker_cache.demand_mshr_misses::total 118727 # number of demand (read+write) MSHR misses --- 61 unchanged lines hidden (view full) --- 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33240.856104 # average WriteReq miss latency 865system.cpu.dcache.demand_avg_miss_latency::cpu.data 17118.025524 # average overall miss latency 866system.cpu.dcache.overall_avg_miss_latency::cpu.data 17118.025524 # average overall miss latency 867system.cpu.dcache.blocked_cycles::no_mshrs 23782481 # number of cycles access was blocked 868system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 869system.cpu.dcache.blocked::no_mshrs 3499 # number of cycles access was blocked 870system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 871system.cpu.dcache.avg_blocked_cycles::no_mshrs 6796.936553 # average number of cycles each access was blocked |
| 872system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 872system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 873system.cpu.dcache.fast_writes 0 # number of fast writes performed 874system.cpu.dcache.cache_copies 0 # number of cache copies performed 875system.cpu.dcache.writebacks::writebacks 1561356 # number of writebacks 876system.cpu.dcache.writebacks::total 1561356 # number of writebacks 877system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1030690 # number of ReadReq MSHR hits 878system.cpu.dcache.ReadReq_mshr_hits::total 1030690 # number of ReadReq MSHR hits 879system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22348 # number of WriteReq MSHR hits 880system.cpu.dcache.WriteReq_mshr_hits::total 22348 # number of WriteReq MSHR hits --- 42 unchanged lines hidden --- | 873system.cpu.dcache.fast_writes 0 # number of fast writes performed 874system.cpu.dcache.cache_copies 0 # number of cache copies performed 875system.cpu.dcache.writebacks::writebacks 1561356 # number of writebacks 876system.cpu.dcache.writebacks::total 1561356 # number of writebacks 877system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1030690 # number of ReadReq MSHR hits 878system.cpu.dcache.ReadReq_mshr_hits::total 1030690 # number of ReadReq MSHR hits 879system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22348 # number of WriteReq MSHR hits 880system.cpu.dcache.WriteReq_mshr_hits::total 22348 # number of WriteReq MSHR hits --- 42 unchanged lines hidden --- |