| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.230834 # Number of seconds simulated 4sim_ticks 5230834315000 # Number of ticks simulated 5final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.230834 # Number of seconds simulated 4sim_ticks 5230834315000 # Number of ticks simulated 5final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 192642 # Simulator instruction rate (inst/s) 8host_op_rate 380808 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2470040631 # Simulator tick rate (ticks/s) 10host_mem_usage 757076 # Number of bytes of host memory used 11host_seconds 2117.71 # Real time elapsed on the host | 7host_inst_rate 185450 # Simulator instruction rate (inst/s) 8host_op_rate 366593 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2377836678 # Simulator tick rate (ticks/s) 10host_mem_usage 757080 # Number of bytes of host memory used 11host_seconds 2199.83 # Real time elapsed on the host |
| 12sim_insts 407959263 # Number of instructions simulated 13sim_ops 806441023 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory --- 673 unchanged lines hidden (view full) --- 693system.cpu.dcache.overall_avg_miss_latency::cpu.data 19891.968592 # average overall miss latency 694system.cpu.dcache.overall_avg_miss_latency::total 19891.968592 # average overall miss latency 695system.cpu.dcache.blocked_cycles::no_mshrs 529664 # number of cycles access was blocked 696system.cpu.dcache.blocked_cycles::no_targets 193 # number of cycles access was blocked 697system.cpu.dcache.blocked::no_mshrs 52278 # number of cycles access was blocked 698system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 699system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.131681 # average number of cycles each access was blocked 700system.cpu.dcache.avg_blocked_cycles::no_targets 96.500000 # average number of cycles each access was blocked | 12sim_insts 407959263 # Number of instructions simulated 13sim_ops 806441023 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory --- 673 unchanged lines hidden (view full) --- 693system.cpu.dcache.overall_avg_miss_latency::cpu.data 19891.968592 # average overall miss latency 694system.cpu.dcache.overall_avg_miss_latency::total 19891.968592 # average overall miss latency 695system.cpu.dcache.blocked_cycles::no_mshrs 529664 # number of cycles access was blocked 696system.cpu.dcache.blocked_cycles::no_targets 193 # number of cycles access was blocked 697system.cpu.dcache.blocked::no_mshrs 52278 # number of cycles access was blocked 698system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 699system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.131681 # average number of cycles each access was blocked 700system.cpu.dcache.avg_blocked_cycles::no_targets 96.500000 # average number of cycles each access was blocked |
| 701system.cpu.dcache.fast_writes 0 # number of fast writes performed 702system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 703system.cpu.dcache.writebacks::writebacks 1592887 # number of writebacks 704system.cpu.dcache.writebacks::total 1592887 # number of writebacks 705system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868287 # number of ReadReq MSHR hits 706system.cpu.dcache.ReadReq_mshr_hits::total 868287 # number of ReadReq MSHR hits 707system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42120 # number of WriteReq MSHR hits 708system.cpu.dcache.WriteReq_mshr_hits::total 42120 # number of WriteReq MSHR hits 709system.cpu.dcache.demand_mshr_hits::cpu.data 910407 # number of demand (read+write) MSHR hits 710system.cpu.dcache.demand_mshr_hits::total 910407 # number of demand (read+write) MSHR hits --- 22 unchanged lines hidden (view full) --- 733system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6777922000 # number of SoftPFReq MSHR miss cycles 734system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6777922000 # number of SoftPFReq MSHR miss cycles 735system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33796984244 # number of demand (read+write) MSHR miss cycles 736system.cpu.dcache.demand_mshr_miss_latency::total 33796984244 # number of demand (read+write) MSHR miss cycles 737system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244 # number of overall MSHR miss cycles 738system.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles 739system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles 740system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles | 701system.cpu.dcache.writebacks::writebacks 1592887 # number of writebacks 702system.cpu.dcache.writebacks::total 1592887 # number of writebacks 703system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868287 # number of ReadReq MSHR hits 704system.cpu.dcache.ReadReq_mshr_hits::total 868287 # number of ReadReq MSHR hits 705system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42120 # number of WriteReq MSHR hits 706system.cpu.dcache.WriteReq_mshr_hits::total 42120 # number of WriteReq MSHR hits 707system.cpu.dcache.demand_mshr_hits::cpu.data 910407 # number of demand (read+write) MSHR hits 708system.cpu.dcache.demand_mshr_hits::total 910407 # number of demand (read+write) MSHR hits --- 22 unchanged lines hidden (view full) --- 731system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6777922000 # number of SoftPFReq MSHR miss cycles 732system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6777922000 # number of SoftPFReq MSHR miss cycles 733system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33796984244 # number of demand (read+write) MSHR miss cycles 734system.cpu.dcache.demand_mshr_miss_latency::total 33796984244 # number of demand (read+write) MSHR miss cycles 735system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244 # number of overall MSHR miss cycles 736system.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles 737system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles 738system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles |
| 741system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2788550500 # number of WriteReq MSHR uncacheable cycles 742system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2788550500 # number of WriteReq MSHR uncacheable cycles 743system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100905771500 # number of overall MSHR uncacheable cycles 744system.cpu.dcache.overall_mshr_uncacheable_latency::total 100905771500 # number of overall MSHR uncacheable cycles | 739system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles 740system.cpu.dcache.overall_mshr_uncacheable_latency::total 98117221000 # number of overall MSHR uncacheable cycles |
| 745system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses 746system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses 747system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses 748system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034152 # mshr miss rate for WriteReq accesses 749system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.844571 # mshr miss rate for SoftPFReq accesses 750system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.844571 # mshr miss rate for SoftPFReq accesses 751system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055520 # mshr miss rate for demand accesses 752system.cpu.dcache.demand_mshr_miss_rate::total 0.055520 # mshr miss rate for demand accesses --- 6 unchanged lines hidden (view full) --- 759system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency 760system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency 761system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency 762system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency 763system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency 764system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency 765system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency 766system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency | 741system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses 742system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses 743system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses 744system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034152 # mshr miss rate for WriteReq accesses 745system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.844571 # mshr miss rate for SoftPFReq accesses 746system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.844571 # mshr miss rate for SoftPFReq accesses 747system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055520 # mshr miss rate for demand accesses 748system.cpu.dcache.demand_mshr_miss_rate::total 0.055520 # mshr miss rate for demand accesses --- 6 unchanged lines hidden (view full) --- 755system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency 756system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency 757system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency 758system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency 759system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency 760system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency 761system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency 762system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency |
| 767system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199552.776585 # average WriteReq mshr uncacheable latency 768system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199552.776585 # average WriteReq mshr uncacheable latency 769system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171769.123330 # average overall mshr uncacheable latency 770system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171769.123330 # average overall mshr uncacheable latency 771system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 763system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency 764system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency |
| 772system.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements 773system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use 774system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks. 775system.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks. 776system.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks. 777system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit. 778system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor 779system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.991584 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 822system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency 823system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544 # average overall miss latency 824system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 825system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 826system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 827system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 828system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 829system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 765system.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements 766system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use 767system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks. 768system.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks. 769system.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks. 770system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit. 771system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor 772system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.991584 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 815system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency 816system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544 # average overall miss latency 817system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 818system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 819system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 820system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 821system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 822system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 830system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 831system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | |
| 832system.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks 833system.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks 834system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses 835system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 149314 # number of ReadReq MSHR misses 836system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 149314 # number of demand (read+write) MSHR misses 837system.cpu.dtb_walker_cache.demand_mshr_misses::total 149314 # number of demand (read+write) MSHR misses 838system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 149314 # number of overall MSHR misses 839system.cpu.dtb_walker_cache.overall_mshr_misses::total 149314 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 850system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for overall accesses 851system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.318740 # mshr miss rate for overall accesses 852system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average ReadReq mshr miss latency 853system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544 # average ReadReq mshr miss latency 854system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency 855system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency 856system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency 857system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency | 823system.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks 824system.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks 825system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses 826system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 149314 # number of ReadReq MSHR misses 827system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 149314 # number of demand (read+write) MSHR misses 828system.cpu.dtb_walker_cache.demand_mshr_misses::total 149314 # number of demand (read+write) MSHR misses 829system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 149314 # number of overall MSHR misses 830system.cpu.dtb_walker_cache.overall_mshr_misses::total 149314 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 841system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for overall accesses 842system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.318740 # mshr miss rate for overall accesses 843system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average ReadReq mshr miss latency 844system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544 # average ReadReq mshr miss latency 845system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency 846system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency 847system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency 848system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency |
| 858system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 859system.cpu.icache.tags.replacements 1273398 # number of replacements 860system.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use 861system.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks. 862system.cpu.icache.tags.sampled_refs 1273910 # Sample count of references to valid blocks. 863system.cpu.icache.tags.avg_refs 8.881310 # Average number of references to valid blocks. 864system.cpu.icache.tags.warmup_cycle 150946764500 # Cycle when the warmup percentage was hit. 865system.cpu.icache.tags.occ_blocks::cpu.inst 510.770567 # Average occupied blocks per requestor 866system.cpu.icache.tags.occ_percent::cpu.inst 0.997599 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 910system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency 911system.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency 912system.cpu.icache.blocked_cycles::no_mshrs 10512 # number of cycles access was blocked 913system.cpu.icache.blocked_cycles::no_targets 700 # number of cycles access was blocked 914system.cpu.icache.blocked::no_mshrs 591 # number of cycles access was blocked 915system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 916system.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked 917system.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked | 849system.cpu.icache.tags.replacements 1273398 # number of replacements 850system.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use 851system.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks. 852system.cpu.icache.tags.sampled_refs 1273910 # Sample count of references to valid blocks. 853system.cpu.icache.tags.avg_refs 8.881310 # Average number of references to valid blocks. 854system.cpu.icache.tags.warmup_cycle 150946764500 # Cycle when the warmup percentage was hit. 855system.cpu.icache.tags.occ_blocks::cpu.inst 510.770567 # Average occupied blocks per requestor 856system.cpu.icache.tags.occ_percent::cpu.inst 0.997599 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 900system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency 901system.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency 902system.cpu.icache.blocked_cycles::no_mshrs 10512 # number of cycles access was blocked 903system.cpu.icache.blocked_cycles::no_targets 700 # number of cycles access was blocked 904system.cpu.icache.blocked::no_mshrs 591 # number of cycles access was blocked 905system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 906system.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked 907system.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked |
| 918system.cpu.icache.fast_writes 0 # number of fast writes performed 919system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 920system.cpu.icache.writebacks::writebacks 1273398 # number of writebacks 921system.cpu.icache.writebacks::total 1273398 # number of writebacks 922system.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits 923system.cpu.icache.ReadReq_mshr_hits::total 169776 # number of ReadReq MSHR hits 924system.cpu.icache.demand_mshr_hits::cpu.inst 169776 # number of demand (read+write) MSHR hits 925system.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits 926system.cpu.icache.overall_mshr_hits::cpu.inst 169776 # number of overall MSHR hits 927system.cpu.icache.overall_mshr_hits::total 169776 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 944system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses 945system.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses 946system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency 947system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency 948system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency 949system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency 950system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency 951system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency | 908system.cpu.icache.writebacks::writebacks 1273398 # number of writebacks 909system.cpu.icache.writebacks::total 1273398 # number of writebacks 910system.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits 911system.cpu.icache.ReadReq_mshr_hits::total 169776 # number of ReadReq MSHR hits 912system.cpu.icache.demand_mshr_hits::cpu.inst 169776 # number of demand (read+write) MSHR hits 913system.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits 914system.cpu.icache.overall_mshr_hits::cpu.inst 169776 # number of overall MSHR hits 915system.cpu.icache.overall_mshr_hits::total 169776 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 932system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses 933system.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses 934system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency 935system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency 936system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency 937system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency 938system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency 939system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency |
| 952system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 953system.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements 954system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use 955system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks. 956system.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks. 957system.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks. 958system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit. 959system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor 960system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy --- 47 unchanged lines hidden (view full) --- 1008system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency 1009system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510 # average overall miss latency 1010system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1011system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1012system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1013system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1014system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1015system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 940system.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements 941system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use 942system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks. 943system.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks. 944system.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks. 945system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit. 946system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor 947system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy --- 47 unchanged lines hidden (view full) --- 995system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency 996system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510 # average overall miss latency 997system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 998system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 999system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1000system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1001system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1002system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1016system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1017system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | |
| 1018system.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks 1019system.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks 1020system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses 1021system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses 1022system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15914 # number of demand (read+write) MSHR misses 1023system.cpu.itb_walker_cache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses 1024system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15914 # number of overall MSHR misses 1025system.cpu.itb_walker_cache.overall_mshr_misses::total 15914 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 1036system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses 1037system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.243501 # mshr miss rate for overall accesses 1038system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average ReadReq mshr miss latency 1039system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency 1040system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency 1041system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency 1042system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency 1043system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency | 1003system.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks 1004system.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks 1005system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses 1006system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses 1007system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15914 # number of demand (read+write) MSHR misses 1008system.cpu.itb_walker_cache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses 1009system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15914 # number of overall MSHR misses 1010system.cpu.itb_walker_cache.overall_mshr_misses::total 15914 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 1021system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses 1022system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.243501 # mshr miss rate for overall accesses 1023system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average ReadReq mshr miss latency 1024system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency 1025system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency 1026system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency 1027system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency 1028system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency |
| 1044system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1045system.cpu.l2cache.tags.replacements 108236 # number of replacements 1046system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use 1047system.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks. 1048system.cpu.l2cache.tags.sampled_refs 172394 # Sample count of references to valid blocks. 1049system.cpu.l2cache.tags.avg_refs 33.136246 # Average number of references to valid blocks. 1050system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1051system.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804 # Average occupied blocks per requestor 1052system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 58.288371 # Average occupied blocks per requestor --- 144 unchanged lines hidden (view full) --- 1197system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency 1198system.cpu.l2cache.overall_avg_miss_latency::total 129143.498740 # average overall miss latency 1199system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1200system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1201system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1202system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1203system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1204system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1029system.cpu.l2cache.tags.replacements 108236 # number of replacements 1030system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use 1031system.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks. 1032system.cpu.l2cache.tags.sampled_refs 172394 # Sample count of references to valid blocks. 1033system.cpu.l2cache.tags.avg_refs 33.136246 # Average number of references to valid blocks. 1034system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1035system.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804 # Average occupied blocks per requestor 1036system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 58.288371 # Average occupied blocks per requestor --- 144 unchanged lines hidden (view full) --- 1181system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency 1182system.cpu.l2cache.overall_avg_miss_latency::total 129143.498740 # average overall miss latency 1183system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1205system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1206system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1207system.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks 1208system.cpu.l2cache.writebacks::total 98548 # number of writebacks 1209system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 1210system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 1211system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.dtb.walker 1 # number of ReadSharedReq MSHR hits 1212system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits 1213system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits 1214system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits --- 46 unchanged lines hidden (view full) --- 1261system.cpu.l2cache.demand_mshr_miss_latency::total 21832221513 # number of demand (read+write) MSHR miss cycles 1262system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15740000 # number of overall MSHR miss cycles 1263system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 875500 # number of overall MSHR miss cycles 1264system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1975642505 # number of overall MSHR miss cycles 1265system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508 # number of overall MSHR miss cycles 1266system.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles 1267system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles 1268system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles | 1189system.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks 1190system.cpu.l2cache.writebacks::total 98548 # number of writebacks 1191system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 1192system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 1193system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.dtb.walker 1 # number of ReadSharedReq MSHR hits 1194system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits 1195system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits 1196system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits --- 46 unchanged lines hidden (view full) --- 1243system.cpu.l2cache.demand_mshr_miss_latency::total 21832221513 # number of demand (read+write) MSHR miss cycles 1244system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15740000 # number of overall MSHR miss cycles 1245system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 875500 # number of overall MSHR miss cycles 1246system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1975642505 # number of overall MSHR miss cycles 1247system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508 # number of overall MSHR miss cycles 1248system.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles 1249system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles 1250system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles |
| 1269system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2627781000 # number of WriteReq MSHR uncacheable cycles 1270system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2627781000 # number of WriteReq MSHR uncacheable cycles 1271system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93576407000 # number of overall MSHR uncacheable cycles 1272system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93576407000 # number of overall MSHR uncacheable cycles | 1251system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles 1252system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles |
| 1273system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1274system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1275system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses 1276system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses 1277system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses 1278system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses 1279system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses 1280system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses --- 28 unchanged lines hidden (view full) --- 1309system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency 1310system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency 1311system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency 1312system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency 1313system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency 1314system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency 1315system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency 1316system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency | 1253system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1254system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1255system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses 1256system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses 1257system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses 1258system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses 1259system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses 1260system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses --- 28 unchanged lines hidden (view full) --- 1289system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency 1290system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency 1291system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency 1292system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency 1293system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency 1294system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency 1295system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency 1296system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency |
| 1317system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188047.874624 # average WriteReq mshr uncacheable latency 1318system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188047.874624 # average WriteReq mshr uncacheable latency 1319system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159292.547451 # average overall mshr uncacheable latency 1320system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159292.547451 # average overall mshr uncacheable latency 1321system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1297system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency 1298system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency |
| 1322system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter. 1323system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1324system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1325system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. 1326system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1327system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1328system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution 1329system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution --- 156 unchanged lines hidden (view full) --- 1486system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1487system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1488system.iocache.tags.tag_accesses 428643 # Number of tag accesses 1489system.iocache.tags.data_accesses 428643 # Number of data accesses 1490system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses 1491system.iocache.ReadReq_misses::total 907 # number of ReadReq misses 1492system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1493system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses | 1299system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter. 1300system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1301system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1302system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. 1303system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1304system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1305system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution 1306system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution --- 156 unchanged lines hidden (view full) --- 1463system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1464system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1465system.iocache.tags.tag_accesses 428643 # Number of tag accesses 1466system.iocache.tags.data_accesses 428643 # Number of data accesses 1467system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses 1468system.iocache.ReadReq_misses::total 907 # number of ReadReq misses 1469system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1470system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses |
| 1494system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses 1495system.iocache.demand_misses::total 907 # number of demand (read+write) misses 1496system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses 1497system.iocache.overall_misses::total 907 # number of overall misses | 1471system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses 1472system.iocache.demand_misses::total 47627 # number of demand (read+write) misses 1473system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses 1474system.iocache.overall_misses::total 47627 # number of overall misses |
| 1498system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles 1499system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles 1500system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles 1501system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles | 1475system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles 1476system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles 1477system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles 1478system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles |
| 1502system.iocache.demand_miss_latency::pc.south_bridge.ide 150838200 # number of demand (read+write) miss cycles 1503system.iocache.demand_miss_latency::total 150838200 # number of demand (read+write) miss cycles 1504system.iocache.overall_miss_latency::pc.south_bridge.ide 150838200 # number of overall miss cycles 1505system.iocache.overall_miss_latency::total 150838200 # number of overall miss cycles | 1479system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles 1480system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles 1481system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles 1482system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles |
| 1506system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) 1507system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) 1508system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1509system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) | 1483system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) 1484system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) 1485system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1486system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) |
| 1510system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses 1511system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses 1512system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses 1513system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses | 1487system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses 1488system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses 1489system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses 1490system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses |
| 1514system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1515system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1516system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1517system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1518system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1519system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1520system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1521system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1522system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency 1523system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency 1524system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency 1525system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency | 1491system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1492system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1493system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1494system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1495system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1496system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1497system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1498system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1499system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency 1500system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency 1501system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency 1502system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency |
| 1526system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency 1527system.iocache.demand_avg_miss_latency::total 166304.520397 # average overall miss latency 1528system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency 1529system.iocache.overall_avg_miss_latency::total 166304.520397 # average overall miss latency | 1503system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency 1504system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency 1505system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency 1506system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency |
| 1530system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked 1531system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1532system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked 1533system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1534system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked 1535system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1507system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked 1508system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1509system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked 1510system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1511system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked 1512system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1536system.iocache.fast_writes 0 # number of fast writes performed 1537system.iocache.cache_copies 0 # number of cache copies performed | |
| 1538system.iocache.writebacks::writebacks 46667 # number of writebacks 1539system.iocache.writebacks::total 46667 # number of writebacks 1540system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses 1541system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses 1542system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1543system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses | 1513system.iocache.writebacks::writebacks 46667 # number of writebacks 1514system.iocache.writebacks::total 46667 # number of writebacks 1515system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses 1516system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses 1517system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1518system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses |
| 1544system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses 1545system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses 1546system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses 1547system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses | 1519system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses 1520system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses 1521system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses 1522system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses |
| 1548system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles 1549system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles 1550system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles 1551system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles | 1523system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles 1524system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles 1525system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles 1526system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles |
| 1552system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of demand (read+write) MSHR miss cycles 1553system.iocache.demand_mshr_miss_latency::total 105488200 # number of demand (read+write) MSHR miss cycles 1554system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of overall MSHR miss cycles 1555system.iocache.overall_mshr_miss_latency::total 105488200 # number of overall MSHR miss cycles | 1527system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles 1528system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles 1529system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles 1530system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles |
| 1556system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1557system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1558system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1559system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1560system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1561system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1562system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1563system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1564system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency 1565system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency 1566system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency 1567system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency | 1531system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1532system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1533system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1534system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1535system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1536system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1537system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1538system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1539system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency 1540system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency 1541system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency 1542system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency |
| 1568system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency 1569system.iocache.demand_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency 1570system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency 1571system.iocache.overall_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency 1572system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1543system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency 1544system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency 1545system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency 1546system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency |
| 1573system.membus.trans_dist::ReadReq 573476 # Transaction distribution 1574system.membus.trans_dist::ReadResp 628544 # Transaction distribution 1575system.membus.trans_dist::WriteReq 13974 # Transaction distribution 1576system.membus.trans_dist::WriteResp 13974 # Transaction distribution 1577system.membus.trans_dist::WritebackDirty 145215 # Transaction distribution 1578system.membus.trans_dist::CleanEvict 10528 # Transaction distribution 1579system.membus.trans_dist::UpgradeReq 2175 # Transaction distribution 1580system.membus.trans_dist::UpgradeResp 20 # Transaction distribution --- 70 unchanged lines hidden --- | 1547system.membus.trans_dist::ReadReq 573476 # Transaction distribution 1548system.membus.trans_dist::ReadResp 628544 # Transaction distribution 1549system.membus.trans_dist::WriteReq 13974 # Transaction distribution 1550system.membus.trans_dist::WriteResp 13974 # Transaction distribution 1551system.membus.trans_dist::WritebackDirty 145215 # Transaction distribution 1552system.membus.trans_dist::CleanEvict 10528 # Transaction distribution 1553system.membus.trans_dist::UpgradeReq 2175 # Transaction distribution 1554system.membus.trans_dist::UpgradeResp 20 # Transaction distribution --- 70 unchanged lines hidden --- |