| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.126140 # Number of seconds simulated 4sim_ticks 5126139641000 # Number of ticks simulated 5final_tick 5126139641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.144266 # Number of seconds simulated 4sim_ticks 5144265998000 # Number of ticks simulated 5final_tick 5144265998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 128755 # Simulator instruction rate (inst/s) 8host_op_rate 254500 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1618610313 # Simulator tick rate (ticks/s) 10host_mem_usage 809248 # Number of bytes of host memory used 11host_seconds 3167.00 # Real time elapsed on the host 12sim_insts 407767906 # Number of instructions simulated 13sim_ops 806002026 # Number of ops (including micro ops) simulated | 7host_inst_rate 171354 # Simulator instruction rate (inst/s) 8host_op_rate 338701 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2161855241 # Simulator tick rate (ticks/s) 10host_mem_usage 817304 # Number of bytes of host memory used 11host_seconds 2379.56 # Real time elapsed on the host 12sim_insts 407746267 # Number of instructions simulated 13sim_ops 805959101 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1038720 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10766272 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1040896 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10728128 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 11837632 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1038720 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1038720 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9565696 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9565696 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 16230 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 168223 # Number of read requests responded to by this memory | 21system.physmem.bytes_read::total 11801664 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1040896 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1040896 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9535488 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9535488 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 16264 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 167627 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::total 184963 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 149464 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 149464 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 202632 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 2100269 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2309268 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 202632 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 202632 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1866062 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1866062 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1866062 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 202632 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 2100269 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4175331 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 184963 # Number of read requests accepted 52system.physmem.writeReqs 149464 # Number of write requests accepted 53system.physmem.readBursts 184963 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 149464 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 11826048 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue 57system.physmem.bytesWritten 9564672 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 11837632 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 9565696 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue | 31system.physmem.num_reads::total 184401 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 148992 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 148992 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 202341 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 2085454 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2294140 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 202341 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 202341 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1853615 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1853615 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1853615 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 202341 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 2085454 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4147754 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 184401 # Number of read requests accepted 52system.physmem.writeReqs 148992 # Number of write requests accepted 53system.physmem.readBursts 184401 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 148992 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 11790400 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 11264 # Total number of bytes read from write queue 57system.physmem.bytesWritten 9534208 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 11801664 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 9535488 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue |
| 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 62system.physmem.neitherReadNorWriteReqs 48781 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 12059 # Per bank write bursts 64system.physmem.perBankRdBursts::1 11374 # Per bank write bursts 65system.physmem.perBankRdBursts::2 11651 # Per bank write bursts 66system.physmem.perBankRdBursts::3 11200 # Per bank write bursts 67system.physmem.perBankRdBursts::4 11713 # Per bank write bursts 68system.physmem.perBankRdBursts::5 11071 # Per bank write bursts 69system.physmem.perBankRdBursts::6 11625 # Per bank write bursts 70system.physmem.perBankRdBursts::7 11816 # Per bank write bursts 71system.physmem.perBankRdBursts::8 11540 # Per bank write bursts 72system.physmem.perBankRdBursts::9 11598 # Per bank write bursts 73system.physmem.perBankRdBursts::10 11427 # Per bank write bursts 74system.physmem.perBankRdBursts::11 11449 # Per bank write bursts 75system.physmem.perBankRdBursts::12 11382 # Per bank write bursts 76system.physmem.perBankRdBursts::13 12463 # Per bank write bursts 77system.physmem.perBankRdBursts::14 11321 # Per bank write bursts 78system.physmem.perBankRdBursts::15 11093 # Per bank write bursts 79system.physmem.perBankWrBursts::0 10213 # Per bank write bursts 80system.physmem.perBankWrBursts::1 9339 # Per bank write bursts 81system.physmem.perBankWrBursts::2 9470 # Per bank write bursts 82system.physmem.perBankWrBursts::3 9072 # Per bank write bursts 83system.physmem.perBankWrBursts::4 9457 # Per bank write bursts 84system.physmem.perBankWrBursts::5 9178 # Per bank write bursts 85system.physmem.perBankWrBursts::6 9173 # Per bank write bursts 86system.physmem.perBankWrBursts::7 8997 # Per bank write bursts 87system.physmem.perBankWrBursts::8 8928 # Per bank write bursts 88system.physmem.perBankWrBursts::9 9204 # Per bank write bursts 89system.physmem.perBankWrBursts::10 9473 # Per bank write bursts 90system.physmem.perBankWrBursts::11 8827 # Per bank write bursts 91system.physmem.perBankWrBursts::12 9527 # Per bank write bursts 92system.physmem.perBankWrBursts::13 9857 # Per bank write bursts 93system.physmem.perBankWrBursts::14 9294 # Per bank write bursts 94system.physmem.perBankWrBursts::15 9439 # Per bank write bursts | 62system.physmem.neitherReadNorWriteReqs 48430 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 11512 # Per bank write bursts 64system.physmem.perBankRdBursts::1 10865 # Per bank write bursts 65system.physmem.perBankRdBursts::2 12624 # Per bank write bursts 66system.physmem.perBankRdBursts::3 11646 # Per bank write bursts 67system.physmem.perBankRdBursts::4 11360 # Per bank write bursts 68system.physmem.perBankRdBursts::5 11063 # Per bank write bursts 69system.physmem.perBankRdBursts::6 11424 # Per bank write bursts 70system.physmem.perBankRdBursts::7 11380 # Per bank write bursts 71system.physmem.perBankRdBursts::8 11354 # Per bank write bursts 72system.physmem.perBankRdBursts::9 10854 # Per bank write bursts 73system.physmem.perBankRdBursts::10 10623 # Per bank write bursts 74system.physmem.perBankRdBursts::11 11335 # Per bank write bursts 75system.physmem.perBankRdBursts::12 12163 # Per bank write bursts 76system.physmem.perBankRdBursts::13 12460 # Per bank write bursts 77system.physmem.perBankRdBursts::14 11874 # Per bank write bursts 78system.physmem.perBankRdBursts::15 11688 # Per bank write bursts 79system.physmem.perBankWrBursts::0 9762 # Per bank write bursts 80system.physmem.perBankWrBursts::1 9087 # Per bank write bursts 81system.physmem.perBankWrBursts::2 9770 # Per bank write bursts 82system.physmem.perBankWrBursts::3 9357 # Per bank write bursts 83system.physmem.perBankWrBursts::4 9485 # Per bank write bursts 84system.physmem.perBankWrBursts::5 8994 # Per bank write bursts 85system.physmem.perBankWrBursts::6 9154 # Per bank write bursts 86system.physmem.perBankWrBursts::7 8718 # Per bank write bursts 87system.physmem.perBankWrBursts::8 8812 # Per bank write bursts 88system.physmem.perBankWrBursts::9 9056 # Per bank write bursts 89system.physmem.perBankWrBursts::10 8954 # Per bank write bursts 90system.physmem.perBankWrBursts::11 9300 # Per bank write bursts 91system.physmem.perBankWrBursts::12 9801 # Per bank write bursts 92system.physmem.perBankWrBursts::13 9709 # Per bank write bursts 93system.physmem.perBankWrBursts::14 9528 # Per bank write bursts 94system.physmem.perBankWrBursts::15 9485 # Per bank write bursts |
| 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 96system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 97system.physmem.totGap 5126139591500 # Total gap between requests | 96system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 97system.physmem.totGap 5144265948500 # Total gap between requests |
| 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) | 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 104system.physmem.readPktSize::6 184963 # Read request sizes (log2) | 104system.physmem.readPktSize::6 184401 # Read request sizes (log2) |
| 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) | 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 111system.physmem.writePktSize::6 149464 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 170238 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 11784 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 1972 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 468 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 29 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 32 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see | 111system.physmem.writePktSize::6 148992 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 169976 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 11589 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 1867 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 53 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see |
| 123system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see --- 20 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 123system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see --- 20 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::15 2243 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 2963 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 7948 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 7845 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 7778 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 7827 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 7815 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 9638 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 9886 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 11733 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 10348 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 9934 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 8512 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 8974 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 9035 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 7803 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 7671 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 7588 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 270 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 273 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 163 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 173 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 135 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 109 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 46 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 71880 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 297.588425 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 176.048684 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 320.988013 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 27629 38.44% 38.44% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 17400 24.21% 62.64% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 7428 10.33% 72.98% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 4118 5.73% 78.71% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2845 3.96% 82.67% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1999 2.78% 85.45% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1307 1.82% 87.26% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1141 1.59% 88.85% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 8013 11.15% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 71880 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 7347 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 25.150402 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 560.379075 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 7346 99.99% 99.99% # Reads before turning the bus around for writes | 159system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 2888 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 7428 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 7347 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 8228 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 8294 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 9520 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 8743 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 9904 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 10060 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 10062 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 11631 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 9054 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 8427 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 8727 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 7953 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 7460 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 167 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 152 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 120 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 100 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 170 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 45 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 73109 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 291.681517 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 174.230147 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 313.360710 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 28156 38.51% 38.51% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 17755 24.29% 62.80% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 7676 10.50% 73.30% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 4351 5.95% 79.25% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2926 4.00% 83.25% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 2405 3.29% 86.54% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1356 1.85% 88.40% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1112 1.52% 89.92% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 7372 10.08% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 73109 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 7269 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 25.343238 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 563.383377 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 7268 99.99% 99.99% # Reads before turning the bus around for writes |
| 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes | 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 227system.physmem.rdPerTurnAround::total 7347 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 7347 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 20.341364 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 18.592949 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 13.054942 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 6299 85.74% 85.74% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 77 1.05% 86.78% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 192 2.61% 89.40% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 82 1.12% 90.51% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 130 1.77% 92.28% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 203 2.76% 95.05% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 23 0.31% 95.36% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 7 0.10% 95.45% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 7 0.10% 95.55% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 8 0.11% 95.66% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 4 0.05% 95.71% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 6 0.08% 95.79% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 243 3.31% 99.10% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 7 0.10% 99.20% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 9 0.12% 99.32% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 11 0.15% 99.47% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 1 0.01% 99.48% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 1 0.01% 99.50% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::100-103 7 0.10% 99.62% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::128-131 16 0.22% 99.88% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 7347 # Writes before turning the bus around for reads 264system.physmem.totQLat 1972823732 # Total ticks spent queuing 265system.physmem.totMemAccLat 5437486232 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 923910000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 10676.49 # Average queueing delay per DRAM burst | 227system.physmem.rdPerTurnAround::total 7269 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 7269 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 20.494153 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 18.676401 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 12.977803 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 6209 85.42% 85.42% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 177 2.43% 87.85% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 31 0.43% 88.28% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 190 2.61% 90.89% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 15 0.21% 91.10% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 151 2.08% 93.18% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 110 1.51% 94.69% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 9 0.12% 94.81% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 21 0.29% 95.10% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 27 0.37% 95.47% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 5 0.07% 95.54% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 5 0.07% 95.61% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 236 3.25% 98.86% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 8 0.11% 98.97% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 6 0.08% 99.05% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 36 0.50% 99.55% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 3 0.04% 99.59% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::100-103 5 0.07% 99.68% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::104-107 1 0.01% 99.70% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::124-127 2 0.03% 99.72% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::128-131 15 0.21% 99.93% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::total 7269 # Writes before turning the bus around for reads 259system.physmem.totQLat 2113024695 # Total ticks spent queuing 260system.physmem.totMemAccLat 5567243445 # Total ticks spent from burst creation until serviced by the DRAM 261system.physmem.totBusLat 921125000 # Total ticks spent in databus transfers 262system.physmem.avgQLat 11469.80 # Average queueing delay per DRAM burst |
| 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 263system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 269system.physmem.avgMemAccLat 29426.49 # Average memory access latency per DRAM burst 270system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s | 264system.physmem.avgMemAccLat 30219.80 # Average memory access latency per DRAM burst 265system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s 266system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s 267system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s 268system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s |
| 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 275system.physmem.busUtil 0.03 # Data bus utilization in percentage 276system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes | 269system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 270system.physmem.busUtil 0.03 # Data bus utilization in percentage 271system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 272system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes |
| 278system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing 279system.physmem.avgWrQLen 22.70 # Average write queue length when enqueuing 280system.physmem.readRowHits 152120 # Number of row buffer hits during reads 281system.physmem.writeRowHits 110229 # Number of row buffer hits during writes 282system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads 283system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes 284system.physmem.avgGap 15328127.19 # Average gap between requests 285system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined 286system.physmem_0.actEnergy 270149040 # Energy for activate commands per rank (pJ) 287system.physmem_0.preEnergy 147402750 # Energy for precharge commands per rank (pJ) 288system.physmem_0.readEnergy 721570200 # Energy for read commands per rank (pJ) 289system.physmem_0.writeEnergy 485345520 # Energy for write commands per rank (pJ) 290system.physmem_0.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) 291system.physmem_0.actBackEnergy 129415070025 # Energy for active background per rank (pJ) 292system.physmem_0.preBackEnergy 2962157471250 # Energy for precharge background per rank (pJ) 293system.physmem_0.totalEnergy 3428011044705 # Total energy per rank (pJ) 294system.physmem_0.averagePower 668.732438 # Core power per rank (mW) 295system.physmem_0.memoryStateTime::IDLE 4927750166228 # Time in different power states 296system.physmem_0.memoryStateTime::REF 171172820000 # Time in different power states | 273system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 274system.physmem.avgWrQLen 23.39 # Average write queue length when enqueuing 275system.physmem.readRowHits 150283 # Number of row buffer hits during reads 276system.physmem.writeRowHits 109804 # Number of row buffer hits during writes 277system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads 278system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes 279system.physmem.avgGap 15430035.87 # Average gap between requests 280system.physmem.pageHitRate 78.05 # Row buffer hit rate, read and write combined 281system.physmem_0.actEnergy 271774440 # Energy for activate commands per rank (pJ) 282system.physmem_0.preEnergy 148289625 # Energy for precharge commands per rank (pJ) 283system.physmem_0.readEnergy 716609400 # Energy for read commands per rank (pJ) 284system.physmem_0.writeEnergy 481638960 # Energy for write commands per rank (pJ) 285system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) 286system.physmem_0.actBackEnergy 133079069070 # Energy for active background per rank (pJ) 287system.physmem_0.preBackEnergy 2969819271000 # Energy for precharge background per rank (pJ) 288system.physmem_0.totalEnergy 3440514616095 # Total energy per rank (pJ) 289system.physmem_0.averagePower 668.806670 # Core power per rank (mW) 290system.physmem_0.memoryStateTime::IDLE 4940481054222 # Time in different power states 291system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states |
| 297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 292system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 298system.physmem_0.memoryStateTime::ACT 27209465022 # Time in different power states | 293system.physmem_0.memoryStateTime::ACT 32006683778 # Time in different power states |
| 299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 294system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 300system.physmem_1.actEnergy 273263760 # Energy for activate commands per rank (pJ) 301system.physmem_1.preEnergy 149102250 # Energy for precharge commands per rank (pJ) 302system.physmem_1.readEnergy 719721600 # Energy for read commands per rank (pJ) 303system.physmem_1.writeEnergy 483077520 # Energy for write commands per rank (pJ) 304system.physmem_1.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) 305system.physmem_1.actBackEnergy 129328302060 # Energy for active background per rank (pJ) 306system.physmem_1.preBackEnergy 2962233583500 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 3428001086610 # Total energy per rank (pJ) 308system.physmem_1.averagePower 668.730496 # Core power per rank (mW) 309system.physmem_1.memoryStateTime::IDLE 4927884080230 # Time in different power states 310system.physmem_1.memoryStateTime::REF 171172820000 # Time in different power states | 295system.physmem_1.actEnergy 280929600 # Energy for activate commands per rank (pJ) 296system.physmem_1.preEnergy 153285000 # Energy for precharge commands per rank (pJ) 297system.physmem_1.readEnergy 720337800 # Energy for read commands per rank (pJ) 298system.physmem_1.writeEnergy 483699600 # Energy for write commands per rank (pJ) 299system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) 300system.physmem_1.actBackEnergy 133106515425 # Energy for active background per rank (pJ) 301system.physmem_1.preBackEnergy 2969795195250 # Energy for precharge background per rank (pJ) 302system.physmem_1.totalEnergy 3440537926275 # Total energy per rank (pJ) 303system.physmem_1.averagePower 668.811201 # Core power per rank (mW) 304system.physmem_1.memoryStateTime::IDLE 4940433568236 # Time in different power states 305system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states |
| 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 306system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 312system.physmem_1.memoryStateTime::ACT 27082630770 # Time in different power states | 307system.physmem_1.memoryStateTime::ACT 32047173014 # Time in different power states |
| 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 308system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 314system.cpu.branchPred.lookups 86515320 # Number of BP lookups 315system.cpu.branchPred.condPredicted 86515320 # Number of conditional branches predicted 316system.cpu.branchPred.condIncorrect 846562 # Number of conditional branches incorrect 317system.cpu.branchPred.BTBLookups 79887008 # Number of BTB lookups 318system.cpu.branchPred.BTBHits 77941063 # Number of BTB hits | 309system.cpu.branchPred.lookups 86512376 # Number of BP lookups 310system.cpu.branchPred.condPredicted 86512376 # Number of conditional branches predicted 311system.cpu.branchPred.condIncorrect 844809 # Number of conditional branches incorrect 312system.cpu.branchPred.BTBLookups 79880541 # Number of BTB lookups 313system.cpu.branchPred.BTBHits 77944216 # Number of BTB hits |
| 319system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 314system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 320system.cpu.branchPred.BTBHitPct 97.564128 # BTB Hit Percentage 321system.cpu.branchPred.usedRAS 1538368 # Number of times the RAS was used to get a target. 322system.cpu.branchPred.RASInCorrect 179519 # Number of incorrect RAS predictions. | 315system.cpu.branchPred.BTBHitPct 97.575974 # BTB Hit Percentage 316system.cpu.branchPred.usedRAS 1537356 # Number of times the RAS was used to get a target. 317system.cpu.branchPred.RASInCorrect 178131 # Number of incorrect RAS predictions. |
| 323system.cpu_clk_domain.clock 500 # Clock period in ticks 324system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 318system.cpu_clk_domain.clock 500 # Clock period in ticks 319system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 325system.cpu.numCycles 448780162 # number of cpu cycles simulated | 320system.cpu.numCycles 465431904 # number of cpu cycles simulated |
| 326system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 327system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 321system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 322system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 328system.cpu.fetch.icacheStallCycles 27109366 # Number of cycles fetch is stalled on an Icache miss 329system.cpu.fetch.Insts 427484272 # Number of instructions fetch has processed 330system.cpu.fetch.Branches 86515320 # Number of branches that fetch encountered 331system.cpu.fetch.predictedBranches 79479431 # Number of branches that fetch has predicted taken 332system.cpu.fetch.Cycles 417767954 # Number of cycles fetch has run and was not squashing or blocked 333system.cpu.fetch.SquashCycles 1778202 # Number of cycles fetch has spent squashing 334system.cpu.fetch.TlbCycles 144572 # Number of cycles fetch has spent waiting for tlb 335system.cpu.fetch.MiscStallCycles 59542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 336system.cpu.fetch.PendingTrapStallCycles 198505 # Number of stall cycles due to pending traps 337system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions 338system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR 339system.cpu.fetch.CacheLines 8932158 # Number of cache lines fetched 340system.cpu.fetch.IcacheSquashes 424030 # Number of outstanding Icache misses that were squashed 341system.cpu.fetch.ItlbSquashes 4890 # Number of outstanding ITLB misses that were squashed 342system.cpu.fetch.rateDist::samples 446169387 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::mean 1.890848 # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::stdev 3.050446 # Number of instructions fetched each cycle (Total) | 323system.cpu.fetch.icacheStallCycles 27316222 # Number of cycles fetch is stalled on an Icache miss 324system.cpu.fetch.Insts 427457339 # Number of instructions fetch has processed 325system.cpu.fetch.Branches 86512376 # Number of branches that fetch encountered 326system.cpu.fetch.predictedBranches 79481572 # Number of branches that fetch has predicted taken 327system.cpu.fetch.Cycles 433294653 # Number of cycles fetch has run and was not squashing or blocked 328system.cpu.fetch.SquashCycles 1774328 # Number of cycles fetch has spent squashing 329system.cpu.fetch.TlbCycles 174290 # Number of cycles fetch has spent waiting for tlb 330system.cpu.fetch.MiscStallCycles 61780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 331system.cpu.fetch.PendingTrapStallCycles 197089 # Number of stall cycles due to pending traps 332system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions 333system.cpu.fetch.IcacheWaitRetryStallCycles 797 # Number of stall cycles due to full MSHR 334system.cpu.fetch.CacheLines 8939505 # Number of cache lines fetched 335system.cpu.fetch.IcacheSquashes 424296 # Number of outstanding Icache misses that were squashed 336system.cpu.fetch.ItlbSquashes 5201 # Number of outstanding ITLB misses that were squashed 337system.cpu.fetch.rateDist::samples 461932056 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::mean 1.826209 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::stdev 3.017418 # Number of instructions fetched each cycle (Total) |
| 345system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 340system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 346system.cpu.fetch.rateDist::0 281281763 63.04% 63.04% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::1 2130107 0.48% 63.52% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::2 72126905 16.17% 79.69% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::3 1545484 0.35% 80.03% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::4 2095217 0.47% 80.50% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::5 2290541 0.51% 81.02% # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::6 1479828 0.33% 81.35% # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::7 1850907 0.41% 81.76% # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::8 81368635 18.24% 100.00% # Number of instructions fetched each cycle (Total) | 341system.cpu.fetch.rateDist::0 297044979 64.30% 64.30% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::1 2134462 0.46% 64.77% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::2 72126640 15.61% 80.38% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::3 1546779 0.33% 80.72% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::4 2100235 0.45% 81.17% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::5 2289900 0.50% 81.67% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::6 1474676 0.32% 81.99% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::7 1857009 0.40% 82.39% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::8 81357376 17.61% 100.00% # Number of instructions fetched each cycle (Total) |
| 355system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 350system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 358system.cpu.fetch.rateDist::total 446169387 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.branchRate 0.192779 # Number of branch fetches per cycle 360system.cpu.fetch.rate 0.952547 # Number of inst fetches per cycle 361system.cpu.decode.IdleCycles 23013230 # Number of cycles decode is idle 362system.cpu.decode.BlockedCycles 265986736 # Number of cycles decode is blocked 363system.cpu.decode.RunCycles 147854773 # Number of cycles decode is running 364system.cpu.decode.UnblockCycles 8425547 # Number of cycles decode is unblocking 365system.cpu.decode.SquashCycles 889101 # Number of cycles decode is squashing 366system.cpu.decode.DecodedInsts 835878661 # Number of instructions handled by decode 367system.cpu.rename.SquashCycles 889101 # Number of cycles rename is squashing 368system.cpu.rename.IdleCycles 26336765 # Number of cycles rename is idle 369system.cpu.rename.BlockCycles 222825660 # Number of cycles rename is blocking 370system.cpu.rename.serializeStallCycles 12982234 # count of cycles rename stalled for serializing inst 371system.cpu.rename.RunCycles 152266315 # Number of cycles rename is running 372system.cpu.rename.UnblockCycles 30869312 # Number of cycles rename is unblocking 373system.cpu.rename.RenamedInsts 832551989 # Number of instructions processed by rename 374system.cpu.rename.ROBFullEvents 449261 # Number of times rename has blocked due to ROB full 375system.cpu.rename.IQFullEvents 12787861 # Number of times rename has blocked due to IQ full 376system.cpu.rename.LQFullEvents 146326 # Number of times rename has blocked due to LQ full 377system.cpu.rename.SQFullEvents 14734321 # Number of times rename has blocked due to SQ full 378system.cpu.rename.RenamedOperands 994655089 # Number of destination operands rename has renamed 379system.cpu.rename.RenameLookups 1807638707 # Number of register rename lookups that rename has made 380system.cpu.rename.int_rename_lookups 1111268111 # Number of integer rename lookups 381system.cpu.rename.fp_rename_lookups 319 # Number of floating rename lookups 382system.cpu.rename.CommittedMaps 963888503 # Number of HB maps that are committed 383system.cpu.rename.UndoneMaps 30766581 # Number of HB maps that are undone due to squashing 384system.cpu.rename.serializingInsts 460676 # count of serializing insts renamed 385system.cpu.rename.tempSerializingInsts 463553 # count of temporary serializing insts renamed 386system.cpu.rename.skidInsts 43190500 # count of insts added to the skid buffer 387system.cpu.memDep0.insertedLoads 17070475 # Number of loads inserted to the mem dependence unit. 388system.cpu.memDep0.insertedStores 10019861 # Number of stores inserted to the mem dependence unit. 389system.cpu.memDep0.conflictingLoads 1311535 # Number of conflicting loads. 390system.cpu.memDep0.conflictingStores 1113253 # Number of conflicting stores. 391system.cpu.iq.iqInstsAdded 827301854 # Number of instructions added to the IQ (excludes non-spec) 392system.cpu.iq.iqNonSpecInstsAdded 1181846 # Number of non-speculative instructions added to the IQ 393system.cpu.iq.iqInstsIssued 822527972 # Number of instructions issued 394system.cpu.iq.iqSquashedInstsIssued 224018 # Number of squashed instructions issued 395system.cpu.iq.iqSquashedInstsExamined 22481665 # Number of squashed instructions iterated over during squash; mainly for profiling 396system.cpu.iq.iqSquashedOperandsExamined 33938360 # Number of squashed operands that are examined and possibly removed from graph 397system.cpu.iq.iqSquashedNonSpecRemoved 142118 # Number of squashed non-spec instructions that were removed 398system.cpu.iq.issued_per_cycle::samples 446169387 # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::mean 1.843533 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::stdev 2.419200 # Number of insts issued each cycle | 353system.cpu.fetch.rateDist::total 461932056 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.branchRate 0.185875 # Number of branch fetches per cycle 355system.cpu.fetch.rate 0.918410 # Number of inst fetches per cycle 356system.cpu.decode.IdleCycles 23107773 # Number of cycles decode is idle 357system.cpu.decode.BlockedCycles 281695317 # Number of cycles decode is blocked 358system.cpu.decode.RunCycles 147794197 # Number of cycles decode is running 359system.cpu.decode.UnblockCycles 8447605 # Number of cycles decode is unblocking 360system.cpu.decode.SquashCycles 887164 # Number of cycles decode is squashing 361system.cpu.decode.DecodedInsts 835787144 # Number of instructions handled by decode 362system.cpu.rename.SquashCycles 887164 # Number of cycles rename is squashing 363system.cpu.rename.IdleCycles 26441875 # Number of cycles rename is idle 364system.cpu.rename.BlockCycles 229504552 # Number of cycles rename is blocking 365system.cpu.rename.serializeStallCycles 14337084 # count of cycles rename stalled for serializing inst 366system.cpu.rename.RunCycles 152214834 # Number of cycles rename is running 367system.cpu.rename.UnblockCycles 38546547 # Number of cycles rename is unblocking 368system.cpu.rename.RenamedInsts 832466923 # Number of instructions processed by rename 369system.cpu.rename.ROBFullEvents 458085 # Number of times rename has blocked due to ROB full 370system.cpu.rename.IQFullEvents 12798467 # Number of times rename has blocked due to IQ full 371system.cpu.rename.LQFullEvents 221946 # Number of times rename has blocked due to LQ full 372system.cpu.rename.SQFullEvents 22321415 # Number of times rename has blocked due to SQ full 373system.cpu.rename.RenamedOperands 994552862 # Number of destination operands rename has renamed 374system.cpu.rename.RenameLookups 1807469855 # Number of register rename lookups that rename has made 375system.cpu.rename.int_rename_lookups 1111168371 # Number of integer rename lookups 376system.cpu.rename.fp_rename_lookups 379 # Number of floating rename lookups 377system.cpu.rename.CommittedMaps 963838514 # Number of HB maps that are committed 378system.cpu.rename.UndoneMaps 30714343 # Number of HB maps that are undone due to squashing 379system.cpu.rename.serializingInsts 460142 # count of serializing insts renamed 380system.cpu.rename.tempSerializingInsts 463176 # count of temporary serializing insts renamed 381system.cpu.rename.skidInsts 43334873 # count of insts added to the skid buffer 382system.cpu.memDep0.insertedLoads 17067493 # Number of loads inserted to the mem dependence unit. 383system.cpu.memDep0.insertedStores 10022220 # Number of stores inserted to the mem dependence unit. 384system.cpu.memDep0.conflictingLoads 1319734 # Number of conflicting loads. 385system.cpu.memDep0.conflictingStores 1116337 # Number of conflicting stores. 386system.cpu.iq.iqInstsAdded 827242342 # Number of instructions added to the IQ (excludes non-spec) 387system.cpu.iq.iqNonSpecInstsAdded 1181786 # Number of non-speculative instructions added to the IQ 388system.cpu.iq.iqInstsIssued 822485271 # Number of instructions issued 389system.cpu.iq.iqSquashedInstsIssued 216558 # Number of squashed instructions issued 390system.cpu.iq.iqSquashedInstsExamined 22465018 # Number of squashed instructions iterated over during squash; mainly for profiling 391system.cpu.iq.iqSquashedOperandsExamined 33877646 # Number of squashed operands that are examined and possibly removed from graph 392system.cpu.iq.iqSquashedNonSpecRemoved 141871 # Number of squashed non-spec instructions that were removed 393system.cpu.iq.issued_per_cycle::samples 461932056 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::mean 1.780533 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::stdev 2.400914 # Number of insts issued each cycle |
| 401system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 396system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 402system.cpu.iq.issued_per_cycle::0 262457891 58.82% 58.82% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::1 13818111 3.10% 61.92% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::2 9771246 2.19% 64.11% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::3 7528828 1.69% 65.80% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::4 73243364 16.42% 82.22% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::5 4832116 1.08% 83.30% # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::6 72756563 16.31% 99.61% # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::7 1182673 0.27% 99.87% # Number of insts issued each cycle 410system.cpu.iq.issued_per_cycle::8 578595 0.13% 100.00% # Number of insts issued each cycle | 397system.cpu.iq.issued_per_cycle::0 278202681 60.23% 60.23% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::1 13844974 3.00% 63.22% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::2 9781174 2.12% 65.34% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::3 7532969 1.63% 66.97% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::4 73227075 15.85% 82.82% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::5 4827596 1.05% 83.87% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::6 72754467 15.75% 99.62% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::7 1183000 0.26% 99.87% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::8 578120 0.13% 100.00% # Number of insts issued each cycle |
| 411system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 412system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 413system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 406system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 414system.cpu.iq.issued_per_cycle::total 446169387 # Number of insts issued each cycle | 409system.cpu.iq.issued_per_cycle::total 461932056 # Number of insts issued each cycle |
| 415system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 410system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 416system.cpu.iq.fu_full::IntAlu 2475977 76.35% 76.35% # attempts to use FU when none available 417system.cpu.iq.fu_full::IntMult 0 0.00% 76.35% # attempts to use FU when none available 418system.cpu.iq.fu_full::IntDiv 0 0.00% 76.35% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.35% # attempts to use FU when none available 420system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.35% # attempts to use FU when none available 421system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.35% # attempts to use FU when none available 422system.cpu.iq.fu_full::FloatMult 0 0.00% 76.35% # attempts to use FU when none available 423system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.35% # attempts to use FU when none available 424system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.35% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.35% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.35% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.35% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.35% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.35% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.35% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdMult 0 0.00% 76.35% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.35% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdShift 0 0.00% 76.35% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.35% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.35% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.35% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.35% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.35% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.35% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.35% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.35% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.35% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.35% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.35% # attempts to use FU when none available 445system.cpu.iq.fu_full::MemRead 605774 18.68% 95.03% # attempts to use FU when none available 446system.cpu.iq.fu_full::MemWrite 161247 4.97% 100.00% # attempts to use FU when none available | 411system.cpu.iq.fu_full::IntAlu 2482095 76.42% 76.42% # attempts to use FU when none available 412system.cpu.iq.fu_full::IntMult 0 0.00% 76.42% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntDiv 0 0.00% 76.42% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.42% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.42% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.42% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatMult 0 0.00% 76.42% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.42% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.42% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.42% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.42% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.42% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.42% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.42% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.42% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMult 0 0.00% 76.42% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.42% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdShift 0 0.00% 76.42% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.42% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.42% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.42% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.42% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.42% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.42% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.42% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.42% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.42% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.42% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.42% # attempts to use FU when none available 440system.cpu.iq.fu_full::MemRead 605940 18.66% 95.07% # attempts to use FU when none available 441system.cpu.iq.fu_full::MemWrite 160087 4.93% 100.00% # attempts to use FU when none available |
| 447system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 448system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 449system.cpu.iq.FU_type_0::No_OpClass 283294 0.03% 0.03% # Type of FU issued 450system.cpu.iq.FU_type_0::IntAlu 794512938 96.59% 96.63% # Type of FU issued 451system.cpu.iq.FU_type_0::IntMult 150315 0.02% 96.65% # Type of FU issued 452system.cpu.iq.FU_type_0::IntDiv 126079 0.02% 96.66% # Type of FU issued | 444system.cpu.iq.FU_type_0::No_OpClass 284904 0.03% 0.03% # Type of FU issued 445system.cpu.iq.FU_type_0::IntAlu 794458238 96.59% 96.63% # Type of FU issued 446system.cpu.iq.FU_type_0::IntMult 149904 0.02% 96.65% # Type of FU issued 447system.cpu.iq.FU_type_0::IntDiv 126188 0.02% 96.66% # Type of FU issued |
| 453system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued | 448system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued |
| 455system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.66% # Type of FU issued | 450system.cpu.iq.FU_type_0::FloatCvt 113 0.00% 96.66% # Type of FU issued |
| 456system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued 457system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued 458system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 471system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued | 451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 466system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued |
| 479system.cpu.iq.FU_type_0::MemRead 18183253 2.21% 98.87% # Type of FU issued 480system.cpu.iq.FU_type_0::MemWrite 9272009 1.13% 100.00% # Type of FU issued | 474system.cpu.iq.FU_type_0::MemRead 18188915 2.21% 98.87% # Type of FU issued 475system.cpu.iq.FU_type_0::MemWrite 9277009 1.13% 100.00% # Type of FU issued |
| 481system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 482system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 483system.cpu.iq.FU_type_0::total 822527972 # Type of FU issued 484system.cpu.iq.rate 1.832808 # Inst issue rate 485system.cpu.iq.fu_busy_cnt 3242998 # FU busy when requested 486system.cpu.iq.fu_busy_rate 0.003943 # FU busy rate (busy events/executed inst) 487system.cpu.iq.int_inst_queue_reads 2094691886 # Number of integer instruction queue reads 488system.cpu.iq.int_inst_queue_writes 850977244 # Number of integer instruction queue writes 489system.cpu.iq.int_inst_queue_wakeup_accesses 818130626 # Number of integer instruction queue wakeup accesses 490system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads 491system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes 492system.cpu.iq.fp_inst_queue_wakeup_accesses 165 # Number of floating instruction queue wakeup accesses 493system.cpu.iq.int_alu_accesses 825487451 # Number of integer alu accesses 494system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses 495system.cpu.iew.lsq.thread0.forwLoads 1857982 # Number of loads that had data forwarded from stores | 478system.cpu.iq.FU_type_0::total 822485271 # Type of FU issued 479system.cpu.iq.rate 1.767144 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 3248122 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.003949 # FU busy rate (busy events/executed inst) 482system.cpu.iq.int_inst_queue_reads 2110366769 # Number of integer instruction queue reads 483system.cpu.iq.int_inst_queue_writes 850901074 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 818087590 # Number of integer instruction queue wakeup accesses 485system.cpu.iq.fp_inst_queue_reads 508 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 586 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 178 # Number of floating instruction queue wakeup accesses 488system.cpu.iq.int_alu_accesses 825448239 # Number of integer alu accesses 489system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 1862376 # Number of loads that had data forwarded from stores |
| 496system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 491system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 497system.cpu.iew.lsq.thread0.squashedLoads 3083761 # Number of loads squashed 498system.cpu.iew.lsq.thread0.ignoredResponses 14419 # Number of memory responses ignored because the instruction is squashed 499system.cpu.iew.lsq.thread0.memOrderViolation 13953 # Number of memory ordering violations 500system.cpu.iew.lsq.thread0.squashedStores 1600409 # Number of stores squashed | 492system.cpu.iew.lsq.thread0.squashedLoads 3081864 # Number of loads squashed 493system.cpu.iew.lsq.thread0.ignoredResponses 14686 # Number of memory responses ignored because the instruction is squashed 494system.cpu.iew.lsq.thread0.memOrderViolation 14021 # Number of memory ordering violations 495system.cpu.iew.lsq.thread0.squashedStores 1600056 # Number of stores squashed |
| 501system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 502system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 496system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 497system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 503system.cpu.iew.lsq.thread0.rescheduledLoads 2207227 # Number of loads that were rescheduled 504system.cpu.iew.lsq.thread0.cacheBlocked 67958 # Number of times an access to memory failed due to the cache being blocked | 498system.cpu.iew.lsq.thread0.rescheduledLoads 2207186 # Number of loads that were rescheduled 499system.cpu.iew.lsq.thread0.cacheBlocked 68323 # Number of times an access to memory failed due to the cache being blocked |
| 505system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 500system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 506system.cpu.iew.iewSquashCycles 889101 # Number of cycles IEW is squashing 507system.cpu.iew.iewBlockCycles 204671978 # Number of cycles IEW is blocking 508system.cpu.iew.iewUnblockCycles 10002497 # Number of cycles IEW is unblocking 509system.cpu.iew.iewDispatchedInsts 828483700 # Number of instructions dispatched to IQ 510system.cpu.iew.iewDispSquashedInsts 158761 # Number of squashed instructions skipped by dispatch 511system.cpu.iew.iewDispLoadInsts 17070475 # Number of dispatched load instructions 512system.cpu.iew.iewDispStoreInsts 10019861 # Number of dispatched store instructions 513system.cpu.iew.iewDispNonSpecInsts 692471 # Number of dispatched non-speculative instructions 514system.cpu.iew.iewIQFullEvents 393140 # Number of times the IQ has become full, causing a stall 515system.cpu.iew.iewLSQFullEvents 8758574 # Number of times the LSQ has become full, causing a stall 516system.cpu.iew.memOrderViolationEvents 13953 # Number of memory order violations 517system.cpu.iew.predictedTakenIncorrect 479614 # Number of branches that were predicted taken incorrectly 518system.cpu.iew.predictedNotTakenIncorrect 507057 # Number of branches that were predicted not taken incorrectly 519system.cpu.iew.branchMispredicts 986671 # Number of branch mispredicts detected at execute 520system.cpu.iew.iewExecutedInsts 821011839 # Number of executed instructions 521system.cpu.iew.iewExecLoadInsts 17813350 # Number of load instructions executed 522system.cpu.iew.iewExecSquashedInsts 1389357 # Number of squashed instructions skipped in execute | 501system.cpu.iew.iewSquashCycles 887164 # Number of cycles IEW is squashing 502system.cpu.iew.iewBlockCycles 205274699 # Number of cycles IEW is blocking 503system.cpu.iew.iewUnblockCycles 15795611 # Number of cycles IEW is unblocking 504system.cpu.iew.iewDispatchedInsts 828424128 # Number of instructions dispatched to IQ 505system.cpu.iew.iewDispSquashedInsts 165882 # Number of squashed instructions skipped by dispatch 506system.cpu.iew.iewDispLoadInsts 17067493 # Number of dispatched load instructions 507system.cpu.iew.iewDispStoreInsts 10022220 # Number of dispatched store instructions 508system.cpu.iew.iewDispNonSpecInsts 692366 # Number of dispatched non-speculative instructions 509system.cpu.iew.iewIQFullEvents 393655 # Number of times the IQ has become full, causing a stall 510system.cpu.iew.iewLSQFullEvents 14549719 # Number of times the LSQ has become full, causing a stall 511system.cpu.iew.memOrderViolationEvents 14021 # Number of memory order violations 512system.cpu.iew.predictedTakenIncorrect 476392 # Number of branches that were predicted taken incorrectly 513system.cpu.iew.predictedNotTakenIncorrect 506422 # Number of branches that were predicted not taken incorrectly 514system.cpu.iew.branchMispredicts 982814 # Number of branch mispredicts detected at execute 515system.cpu.iew.iewExecutedInsts 820971747 # Number of executed instructions 516system.cpu.iew.iewExecLoadInsts 17818623 # Number of load instructions executed 517system.cpu.iew.iewExecSquashedInsts 1389098 # Number of squashed instructions skipped in execute |
| 523system.cpu.iew.exec_swp 0 # number of swp insts executed 524system.cpu.iew.exec_nop 0 # number of nop insts executed | 518system.cpu.iew.exec_swp 0 # number of swp insts executed 519system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 525system.cpu.iew.exec_refs 26873346 # number of memory reference insts executed 526system.cpu.iew.exec_branches 83150160 # Number of branches executed 527system.cpu.iew.exec_stores 9059996 # Number of stores executed 528system.cpu.iew.exec_rate 1.829430 # Inst execution rate 529system.cpu.iew.wb_sent 820539763 # cumulative count of insts sent to commit 530system.cpu.iew.wb_count 818130791 # cumulative count of insts written-back 531system.cpu.iew.wb_producers 639922411 # num instructions producing a value 532system.cpu.iew.wb_consumers 1048802840 # num instructions consuming a value | 520system.cpu.iew.exec_refs 26886211 # number of memory reference insts executed 521system.cpu.iew.exec_branches 83147027 # Number of branches executed 522system.cpu.iew.exec_stores 9067588 # Number of stores executed 523system.cpu.iew.exec_rate 1.763892 # Inst execution rate 524system.cpu.iew.wb_sent 820497311 # cumulative count of insts sent to commit 525system.cpu.iew.wb_count 818087768 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 639862073 # num instructions producing a value 527system.cpu.iew.wb_consumers 1048693225 # num instructions consuming a value |
| 533system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 528system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 534system.cpu.iew.wb_rate 1.823010 # insts written-back per cycle 535system.cpu.iew.wb_fanout 0.610146 # average fanout of values written-back | 529system.cpu.iew.wb_rate 1.757696 # insts written-back per cycle 530system.cpu.iew.wb_fanout 0.610152 # average fanout of values written-back |
| 536system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 531system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 537system.cpu.commit.commitSquashedInsts 22357422 # The number of squashed insts skipped by commit 538system.cpu.commit.commitNonSpecStalls 1039727 # The number of times commit has been forced to stall to communicate backwards 539system.cpu.commit.branchMispredicts 857347 # The number of times a branch was mispredicted 540system.cpu.commit.committed_per_cycle::samples 442798070 # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::mean 1.820247 # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::stdev 2.674846 # Number of insts commited each cycle | 532system.cpu.commit.commitSquashedInsts 22343285 # The number of squashed insts skipped by commit 533system.cpu.commit.commitNonSpecStalls 1039914 # The number of times commit has been forced to stall to communicate backwards 534system.cpu.commit.branchMispredicts 855258 # The number of times a branch was mispredicted 535system.cpu.commit.committed_per_cycle::samples 458562995 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::mean 1.757576 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::stdev 2.649246 # Number of insts commited each cycle |
| 543system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 538system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 544system.cpu.commit.committed_per_cycle::0 272013186 61.43% 61.43% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::1 11121974 2.51% 63.94% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::2 3639430 0.82% 64.76% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::3 74586618 16.84% 81.61% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::4 2447768 0.55% 82.16% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::5 1626880 0.37% 82.53% # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::6 1002961 0.23% 82.76% # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::7 70975924 16.03% 98.78% # Number of insts commited each cycle 552system.cpu.commit.committed_per_cycle::8 5383329 1.22% 100.00% # Number of insts commited each cycle | 539system.cpu.commit.committed_per_cycle::0 287777749 62.76% 62.76% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::1 11132608 2.43% 65.18% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::2 3641047 0.79% 65.98% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::3 74579710 16.26% 82.24% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::4 2448796 0.53% 82.78% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::5 1627078 0.35% 83.13% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::6 1001834 0.22% 83.35% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::7 70969693 15.48% 98.83% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::8 5384480 1.17% 100.00% # Number of insts commited each cycle |
| 553system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 554system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 555system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 548system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 556system.cpu.commit.committed_per_cycle::total 442798070 # Number of insts commited each cycle 557system.cpu.commit.committedInsts 407767906 # Number of instructions committed 558system.cpu.commit.committedOps 806002026 # Number of ops (including micro ops) committed | 551system.cpu.commit.committed_per_cycle::total 458562995 # Number of insts commited each cycle 552system.cpu.commit.committedInsts 407746267 # Number of instructions committed 553system.cpu.commit.committedOps 805959101 # Number of ops (including micro ops) committed |
| 559system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 554system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 560system.cpu.commit.refs 22406164 # Number of memory references committed 561system.cpu.commit.loads 13986712 # Number of loads committed 562system.cpu.commit.membars 468149 # Number of memory barriers committed 563system.cpu.commit.branches 82157432 # Number of branches committed | 555system.cpu.commit.refs 22407791 # Number of memory references committed 556system.cpu.commit.loads 13985627 # Number of loads committed 557system.cpu.commit.membars 468163 # Number of memory barriers committed 558system.cpu.commit.branches 82155343 # Number of branches committed |
| 564system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. | 559system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. |
| 565system.cpu.commit.int_insts 734850257 # Number of committed integer instructions. 566system.cpu.commit.function_calls 1155439 # Number of function calls committed. 567system.cpu.commit.op_class_0::No_OpClass 171613 0.02% 0.02% # Class of committed instruction 568system.cpu.commit.op_class_0::IntAlu 783160302 97.17% 97.19% # Class of committed instruction 569system.cpu.commit.op_class_0::IntMult 144896 0.02% 97.21% # Class of committed instruction 570system.cpu.commit.op_class_0::IntDiv 121618 0.02% 97.22% # Class of committed instruction | 560system.cpu.commit.int_insts 734813827 # Number of committed integer instructions. 561system.cpu.commit.function_calls 1155420 # Number of function calls committed. 562system.cpu.commit.op_class_0::No_OpClass 171757 0.02% 0.02% # Class of committed instruction 563system.cpu.commit.op_class_0::IntAlu 783115943 97.17% 97.19% # Class of committed instruction 564system.cpu.commit.op_class_0::IntMult 144574 0.02% 97.20% # Class of committed instruction 565system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction |
| 571system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 572system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 573system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction 574system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 575system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 576system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 577system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 578system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction --- 10 unchanged lines hidden (view full) --- 589system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 590system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 591system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 592system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 593system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 594system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 595system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 596system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction | 566system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 567system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 568system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction 569system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 570system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 571system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction --- 10 unchanged lines hidden (view full) --- 584system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 585system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 586system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 587system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 588system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 589system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 590system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 591system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction |
| 597system.cpu.commit.op_class_0::MemRead 13984129 1.73% 98.96% # Class of committed instruction 598system.cpu.commit.op_class_0::MemWrite 8419452 1.04% 100.00% # Class of committed instruction | 592system.cpu.commit.op_class_0::MemRead 13983042 1.73% 98.96% # Class of committed instruction 593system.cpu.commit.op_class_0::MemWrite 8422164 1.04% 100.00% # Class of committed instruction |
| 599system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 600system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 594system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 595system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 601system.cpu.commit.op_class_0::total 806002026 # Class of committed instruction 602system.cpu.commit.bw_lim_events 5383329 # number cycles where commit BW limit reached 603system.cpu.rob.rob_reads 1265696040 # The number of ROB reads 604system.cpu.rob.rob_writes 1660107630 # The number of ROB writes 605system.cpu.timesIdled 283975 # Number of times that the entire CPU went into an idle state and unscheduled itself 606system.cpu.idleCycles 2610775 # Total number of cycles that the CPU has spent unscheduled due to idling 607system.cpu.quiesceCycles 9803496536 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 608system.cpu.committedInsts 407767906 # Number of Instructions Simulated 609system.cpu.committedOps 806002026 # Number of Ops (including micro ops) Simulated 610system.cpu.cpi 1.100577 # CPI: Cycles Per Instruction 611system.cpu.cpi_total 1.100577 # CPI: Total CPI of All Threads 612system.cpu.ipc 0.908614 # IPC: Instructions Per Cycle 613system.cpu.ipc_total 0.908614 # IPC: Total IPC of All Threads 614system.cpu.int_regfile_reads 1090426394 # number of integer regfile reads 615system.cpu.int_regfile_writes 654841654 # number of integer regfile writes 616system.cpu.fp_regfile_reads 165 # number of floating regfile reads 617system.cpu.cc_regfile_reads 415713185 # number of cc regfile reads 618system.cpu.cc_regfile_writes 321659378 # number of cc regfile writes 619system.cpu.misc_regfile_reads 264880270 # number of misc regfile reads 620system.cpu.misc_regfile_writes 399890 # number of misc regfile writes 621system.cpu.dcache.tags.replacements 1655948 # number of replacements 622system.cpu.dcache.tags.tagsinuse 511.995019 # Cycle average of tags in use 623system.cpu.dcache.tags.total_refs 18959511 # Total number of references to valid blocks. 624system.cpu.dcache.tags.sampled_refs 1656460 # Sample count of references to valid blocks. 625system.cpu.dcache.tags.avg_refs 11.445801 # Average number of references to valid blocks. 626system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit. 627system.cpu.dcache.tags.occ_blocks::cpu.data 511.995019 # Average occupied blocks per requestor 628system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 629system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy | 596system.cpu.commit.op_class_0::total 805959101 # Class of committed instruction 597system.cpu.commit.bw_lim_events 5384480 # number cycles where commit BW limit reached 598system.cpu.rob.rob_reads 1281402583 # The number of ROB reads 599system.cpu.rob.rob_writes 1659991505 # The number of ROB writes 600system.cpu.timesIdled 284256 # Number of times that the entire CPU went into an idle state and unscheduled itself 601system.cpu.idleCycles 3499848 # Total number of cycles that the CPU has spent unscheduled due to idling 602system.cpu.quiesceCycles 9823097505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 603system.cpu.committedInsts 407746267 # Number of Instructions Simulated 604system.cpu.committedOps 805959101 # Number of Ops (including micro ops) Simulated 605system.cpu.cpi 1.141474 # CPI: Cycles Per Instruction 606system.cpu.cpi_total 1.141474 # CPI: Total CPI of All Threads 607system.cpu.ipc 0.876060 # IPC: Instructions Per Cycle 608system.cpu.ipc_total 0.876060 # IPC: Total IPC of All Threads 609system.cpu.int_regfile_reads 1090398458 # number of integer regfile reads 610system.cpu.int_regfile_writes 654801015 # number of integer regfile writes 611system.cpu.fp_regfile_reads 178 # number of floating regfile reads 612system.cpu.cc_regfile_reads 415698435 # number of cc regfile reads 613system.cpu.cc_regfile_writes 321644299 # number of cc regfile writes 614system.cpu.misc_regfile_reads 264872577 # number of misc regfile reads 615system.cpu.misc_regfile_writes 400155 # number of misc regfile writes 616system.cpu.dcache.tags.replacements 1656886 # number of replacements 617system.cpu.dcache.tags.tagsinuse 511.993571 # Cycle average of tags in use 618system.cpu.dcache.tags.total_refs 18963252 # Total number of references to valid blocks. 619system.cpu.dcache.tags.sampled_refs 1657398 # Sample count of references to valid blocks. 620system.cpu.dcache.tags.avg_refs 11.441580 # Average number of references to valid blocks. 621system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. 622system.cpu.dcache.tags.occ_blocks::cpu.data 511.993571 # Average occupied blocks per requestor 623system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy 624system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy |
| 630system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 625system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 631system.cpu.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id 632system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id 633system.cpu.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id | 626system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id 627system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id |
| 634system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 629system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 635system.cpu.dcache.tags.tag_accesses 87653092 # Number of tag accesses 636system.cpu.dcache.tags.data_accesses 87653092 # Number of data accesses 637system.cpu.dcache.ReadReq_hits::cpu.data 10818266 # number of ReadReq hits 638system.cpu.dcache.ReadReq_hits::total 10818266 # number of ReadReq hits 639system.cpu.dcache.WriteReq_hits::cpu.data 8075018 # number of WriteReq hits 640system.cpu.dcache.WriteReq_hits::total 8075018 # number of WriteReq hits 641system.cpu.dcache.SoftPFReq_hits::cpu.data 63136 # number of SoftPFReq hits 642system.cpu.dcache.SoftPFReq_hits::total 63136 # number of SoftPFReq hits 643system.cpu.dcache.demand_hits::cpu.data 18893284 # number of demand (read+write) hits 644system.cpu.dcache.demand_hits::total 18893284 # number of demand (read+write) hits 645system.cpu.dcache.overall_hits::cpu.data 18956420 # number of overall hits 646system.cpu.dcache.overall_hits::total 18956420 # number of overall hits 647system.cpu.dcache.ReadReq_misses::cpu.data 1801440 # number of ReadReq misses 648system.cpu.dcache.ReadReq_misses::total 1801440 # number of ReadReq misses 649system.cpu.dcache.WriteReq_misses::cpu.data 334795 # number of WriteReq misses 650system.cpu.dcache.WriteReq_misses::total 334795 # number of WriteReq misses 651system.cpu.dcache.SoftPFReq_misses::cpu.data 406500 # number of SoftPFReq misses 652system.cpu.dcache.SoftPFReq_misses::total 406500 # number of SoftPFReq misses 653system.cpu.dcache.demand_misses::cpu.data 2136235 # number of demand (read+write) misses 654system.cpu.dcache.demand_misses::total 2136235 # number of demand (read+write) misses 655system.cpu.dcache.overall_misses::cpu.data 2542735 # number of overall misses 656system.cpu.dcache.overall_misses::total 2542735 # number of overall misses 657system.cpu.dcache.ReadReq_miss_latency::cpu.data 26875877500 # number of ReadReq miss cycles 658system.cpu.dcache.ReadReq_miss_latency::total 26875877500 # number of ReadReq miss cycles 659system.cpu.dcache.WriteReq_miss_latency::cpu.data 13801276738 # number of WriteReq miss cycles 660system.cpu.dcache.WriteReq_miss_latency::total 13801276738 # number of WriteReq miss cycles 661system.cpu.dcache.demand_miss_latency::cpu.data 40677154238 # number of demand (read+write) miss cycles 662system.cpu.dcache.demand_miss_latency::total 40677154238 # number of demand (read+write) miss cycles 663system.cpu.dcache.overall_miss_latency::cpu.data 40677154238 # number of overall miss cycles 664system.cpu.dcache.overall_miss_latency::total 40677154238 # number of overall miss cycles 665system.cpu.dcache.ReadReq_accesses::cpu.data 12619706 # number of ReadReq accesses(hits+misses) 666system.cpu.dcache.ReadReq_accesses::total 12619706 # number of ReadReq accesses(hits+misses) 667system.cpu.dcache.WriteReq_accesses::cpu.data 8409813 # number of WriteReq accesses(hits+misses) 668system.cpu.dcache.WriteReq_accesses::total 8409813 # number of WriteReq accesses(hits+misses) 669system.cpu.dcache.SoftPFReq_accesses::cpu.data 469636 # number of SoftPFReq accesses(hits+misses) 670system.cpu.dcache.SoftPFReq_accesses::total 469636 # number of SoftPFReq accesses(hits+misses) 671system.cpu.dcache.demand_accesses::cpu.data 21029519 # number of demand (read+write) accesses 672system.cpu.dcache.demand_accesses::total 21029519 # number of demand (read+write) accesses 673system.cpu.dcache.overall_accesses::cpu.data 21499155 # number of overall (read+write) accesses 674system.cpu.dcache.overall_accesses::total 21499155 # number of overall (read+write) accesses 675system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142748 # miss rate for ReadReq accesses 676system.cpu.dcache.ReadReq_miss_rate::total 0.142748 # miss rate for ReadReq accesses 677system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039810 # miss rate for WriteReq accesses 678system.cpu.dcache.WriteReq_miss_rate::total 0.039810 # miss rate for WriteReq accesses 679system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865564 # miss rate for SoftPFReq accesses 680system.cpu.dcache.SoftPFReq_miss_rate::total 0.865564 # miss rate for SoftPFReq accesses 681system.cpu.dcache.demand_miss_rate::cpu.data 0.101583 # miss rate for demand accesses 682system.cpu.dcache.demand_miss_rate::total 0.101583 # miss rate for demand accesses 683system.cpu.dcache.overall_miss_rate::cpu.data 0.118271 # miss rate for overall accesses 684system.cpu.dcache.overall_miss_rate::total 0.118271 # miss rate for overall accesses 685system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14919.107769 # average ReadReq miss latency 686system.cpu.dcache.ReadReq_avg_miss_latency::total 14919.107769 # average ReadReq miss latency 687system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.067065 # average WriteReq miss latency 688system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.067065 # average WriteReq miss latency 689system.cpu.dcache.demand_avg_miss_latency::cpu.data 19041.516611 # average overall miss latency 690system.cpu.dcache.demand_avg_miss_latency::total 19041.516611 # average overall miss latency 691system.cpu.dcache.overall_avg_miss_latency::cpu.data 15997.402104 # average overall miss latency 692system.cpu.dcache.overall_avg_miss_latency::total 15997.402104 # average overall miss latency 693system.cpu.dcache.blocked_cycles::no_mshrs 467524 # number of cycles access was blocked 694system.cpu.dcache.blocked_cycles::no_targets 95 # number of cycles access was blocked 695system.cpu.dcache.blocked::no_mshrs 52009 # number of cycles access was blocked 696system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 697system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.989290 # average number of cycles each access was blocked 698system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked | 630system.cpu.dcache.tags.tag_accesses 87668549 # Number of tag accesses 631system.cpu.dcache.tags.data_accesses 87668549 # Number of data accesses 632system.cpu.dcache.ReadReq_hits::cpu.data 10819943 # number of ReadReq hits 633system.cpu.dcache.ReadReq_hits::total 10819943 # number of ReadReq hits 634system.cpu.dcache.WriteReq_hits::cpu.data 8077328 # number of WriteReq hits 635system.cpu.dcache.WriteReq_hits::total 8077328 # number of WriteReq hits 636system.cpu.dcache.SoftPFReq_hits::cpu.data 63083 # number of SoftPFReq hits 637system.cpu.dcache.SoftPFReq_hits::total 63083 # number of SoftPFReq hits 638system.cpu.dcache.demand_hits::cpu.data 18897271 # number of demand (read+write) hits 639system.cpu.dcache.demand_hits::total 18897271 # number of demand (read+write) hits 640system.cpu.dcache.overall_hits::cpu.data 18960354 # number of overall hits 641system.cpu.dcache.overall_hits::total 18960354 # number of overall hits 642system.cpu.dcache.ReadReq_misses::cpu.data 1800618 # number of ReadReq misses 643system.cpu.dcache.ReadReq_misses::total 1800618 # number of ReadReq misses 644system.cpu.dcache.WriteReq_misses::cpu.data 335187 # number of WriteReq misses 645system.cpu.dcache.WriteReq_misses::total 335187 # number of WriteReq misses 646system.cpu.dcache.SoftPFReq_misses::cpu.data 406619 # number of SoftPFReq misses 647system.cpu.dcache.SoftPFReq_misses::total 406619 # number of SoftPFReq misses 648system.cpu.dcache.demand_misses::cpu.data 2135805 # number of demand (read+write) misses 649system.cpu.dcache.demand_misses::total 2135805 # number of demand (read+write) misses 650system.cpu.dcache.overall_misses::cpu.data 2542424 # number of overall misses 651system.cpu.dcache.overall_misses::total 2542424 # number of overall misses 652system.cpu.dcache.ReadReq_miss_latency::cpu.data 29915350500 # number of ReadReq miss cycles 653system.cpu.dcache.ReadReq_miss_latency::total 29915350500 # number of ReadReq miss cycles 654system.cpu.dcache.WriteReq_miss_latency::cpu.data 21131383234 # number of WriteReq miss cycles 655system.cpu.dcache.WriteReq_miss_latency::total 21131383234 # number of WriteReq miss cycles 656system.cpu.dcache.demand_miss_latency::cpu.data 51046733734 # number of demand (read+write) miss cycles 657system.cpu.dcache.demand_miss_latency::total 51046733734 # number of demand (read+write) miss cycles 658system.cpu.dcache.overall_miss_latency::cpu.data 51046733734 # number of overall miss cycles 659system.cpu.dcache.overall_miss_latency::total 51046733734 # number of overall miss cycles 660system.cpu.dcache.ReadReq_accesses::cpu.data 12620561 # number of ReadReq accesses(hits+misses) 661system.cpu.dcache.ReadReq_accesses::total 12620561 # number of ReadReq accesses(hits+misses) 662system.cpu.dcache.WriteReq_accesses::cpu.data 8412515 # number of WriteReq accesses(hits+misses) 663system.cpu.dcache.WriteReq_accesses::total 8412515 # number of WriteReq accesses(hits+misses) 664system.cpu.dcache.SoftPFReq_accesses::cpu.data 469702 # number of SoftPFReq accesses(hits+misses) 665system.cpu.dcache.SoftPFReq_accesses::total 469702 # number of SoftPFReq accesses(hits+misses) 666system.cpu.dcache.demand_accesses::cpu.data 21033076 # number of demand (read+write) accesses 667system.cpu.dcache.demand_accesses::total 21033076 # number of demand (read+write) accesses 668system.cpu.dcache.overall_accesses::cpu.data 21502778 # number of overall (read+write) accesses 669system.cpu.dcache.overall_accesses::total 21502778 # number of overall (read+write) accesses 670system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142673 # miss rate for ReadReq accesses 671system.cpu.dcache.ReadReq_miss_rate::total 0.142673 # miss rate for ReadReq accesses 672system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039844 # miss rate for WriteReq accesses 673system.cpu.dcache.WriteReq_miss_rate::total 0.039844 # miss rate for WriteReq accesses 674system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865696 # miss rate for SoftPFReq accesses 675system.cpu.dcache.SoftPFReq_miss_rate::total 0.865696 # miss rate for SoftPFReq accesses 676system.cpu.dcache.demand_miss_rate::cpu.data 0.101545 # miss rate for demand accesses 677system.cpu.dcache.demand_miss_rate::total 0.101545 # miss rate for demand accesses 678system.cpu.dcache.overall_miss_rate::cpu.data 0.118237 # miss rate for overall accesses 679system.cpu.dcache.overall_miss_rate::total 0.118237 # miss rate for overall accesses 680system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16613.935049 # average ReadReq miss latency 681system.cpu.dcache.ReadReq_avg_miss_latency::total 16613.935049 # average ReadReq miss latency 682system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63043.564440 # average WriteReq miss latency 683system.cpu.dcache.WriteReq_avg_miss_latency::total 63043.564440 # average WriteReq miss latency 684system.cpu.dcache.demand_avg_miss_latency::cpu.data 23900.465508 # average overall miss latency 685system.cpu.dcache.demand_avg_miss_latency::total 23900.465508 # average overall miss latency 686system.cpu.dcache.overall_avg_miss_latency::cpu.data 20077.978234 # average overall miss latency 687system.cpu.dcache.overall_avg_miss_latency::total 20077.978234 # average overall miss latency 688system.cpu.dcache.blocked_cycles::no_mshrs 549742 # number of cycles access was blocked 689system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 690system.cpu.dcache.blocked::no_mshrs 52309 # number of cycles access was blocked 691system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 692system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.509511 # average number of cycles each access was blocked 693system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 699system.cpu.dcache.fast_writes 0 # number of fast writes performed 700system.cpu.dcache.cache_copies 0 # number of cache copies performed | 694system.cpu.dcache.fast_writes 0 # number of fast writes performed 695system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 701system.cpu.dcache.writebacks::writebacks 1557810 # number of writebacks 702system.cpu.dcache.writebacks::total 1557810 # number of writebacks 703system.cpu.dcache.ReadReq_mshr_hits::cpu.data 835579 # number of ReadReq MSHR hits 704system.cpu.dcache.ReadReq_mshr_hits::total 835579 # number of ReadReq MSHR hits 705system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44644 # number of WriteReq MSHR hits 706system.cpu.dcache.WriteReq_mshr_hits::total 44644 # number of WriteReq MSHR hits 707system.cpu.dcache.demand_mshr_hits::cpu.data 880223 # number of demand (read+write) MSHR hits 708system.cpu.dcache.demand_mshr_hits::total 880223 # number of demand (read+write) MSHR hits 709system.cpu.dcache.overall_mshr_hits::cpu.data 880223 # number of overall MSHR hits 710system.cpu.dcache.overall_mshr_hits::total 880223 # number of overall MSHR hits 711system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965861 # number of ReadReq MSHR misses 712system.cpu.dcache.ReadReq_mshr_misses::total 965861 # number of ReadReq MSHR misses 713system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290151 # number of WriteReq MSHR misses 714system.cpu.dcache.WriteReq_mshr_misses::total 290151 # number of WriteReq MSHR misses 715system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403017 # number of SoftPFReq MSHR misses 716system.cpu.dcache.SoftPFReq_mshr_misses::total 403017 # number of SoftPFReq MSHR misses 717system.cpu.dcache.demand_mshr_misses::cpu.data 1256012 # number of demand (read+write) MSHR misses 718system.cpu.dcache.demand_mshr_misses::total 1256012 # number of demand (read+write) MSHR misses 719system.cpu.dcache.overall_mshr_misses::cpu.data 1659029 # number of overall MSHR misses 720system.cpu.dcache.overall_mshr_misses::total 1659029 # number of overall MSHR misses 721system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable 722system.cpu.dcache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable 723system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13873 # number of WriteReq MSHR uncacheable 724system.cpu.dcache.WriteReq_mshr_uncacheable::total 13873 # number of WriteReq MSHR uncacheable 725system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616769 # number of overall MSHR uncacheable misses 726system.cpu.dcache.overall_mshr_uncacheable_misses::total 616769 # number of overall MSHR uncacheable misses 727system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13275179500 # number of ReadReq MSHR miss cycles 728system.cpu.dcache.ReadReq_mshr_miss_latency::total 13275179500 # number of ReadReq MSHR miss cycles 729system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12396951239 # number of WriteReq MSHR miss cycles 730system.cpu.dcache.WriteReq_mshr_miss_latency::total 12396951239 # number of WriteReq MSHR miss cycles 731system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6045548500 # number of SoftPFReq MSHR miss cycles 732system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6045548500 # number of SoftPFReq MSHR miss cycles 733system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25672130739 # number of demand (read+write) MSHR miss cycles 734system.cpu.dcache.demand_mshr_miss_latency::total 25672130739 # number of demand (read+write) MSHR miss cycles 735system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31717679239 # number of overall MSHR miss cycles 736system.cpu.dcache.overall_mshr_miss_latency::total 31717679239 # number of overall MSHR miss cycles 737system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793653500 # number of ReadReq MSHR uncacheable cycles 738system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793653500 # number of ReadReq MSHR uncacheable cycles 739system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2614977500 # number of WriteReq MSHR uncacheable cycles 740system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2614977500 # number of WriteReq MSHR uncacheable cycles 741system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100408631000 # number of overall MSHR uncacheable cycles 742system.cpu.dcache.overall_mshr_uncacheable_latency::total 100408631000 # number of overall MSHR uncacheable cycles 743system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076536 # mshr miss rate for ReadReq accesses 744system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076536 # mshr miss rate for ReadReq accesses 745system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034501 # mshr miss rate for WriteReq accesses 746system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034501 # mshr miss rate for WriteReq accesses 747system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858148 # mshr miss rate for SoftPFReq accesses 748system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858148 # mshr miss rate for SoftPFReq accesses 749system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059726 # mshr miss rate for demand accesses 750system.cpu.dcache.demand_mshr_miss_rate::total 0.059726 # mshr miss rate for demand accesses 751system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077167 # mshr miss rate for overall accesses 752system.cpu.dcache.overall_mshr_miss_rate::total 0.077167 # mshr miss rate for overall accesses 753system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.399556 # average ReadReq mshr miss latency 754system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.399556 # average ReadReq mshr miss latency 755system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42725.860807 # average WriteReq mshr miss latency 756system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42725.860807 # average WriteReq mshr miss latency 757system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15000.728257 # average SoftPFReq mshr miss latency 758system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15000.728257 # average SoftPFReq mshr miss latency 759system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20439.399257 # average overall mshr miss latency 760system.cpu.dcache.demand_avg_mshr_miss_latency::total 20439.399257 # average overall mshr miss latency 761system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19118.218692 # average overall mshr miss latency 762system.cpu.dcache.overall_avg_mshr_miss_latency::total 19118.218692 # average overall mshr miss latency 763system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.505766 # average ReadReq mshr uncacheable latency 764system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.505766 # average ReadReq mshr uncacheable latency 765system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188494.017156 # average WriteReq mshr uncacheable latency 766system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188494.017156 # average WriteReq mshr uncacheable latency 767system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.791394 # average overall mshr uncacheable latency 768system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.791394 # average overall mshr uncacheable latency | 696system.cpu.dcache.writebacks::writebacks 1559463 # number of writebacks 697system.cpu.dcache.writebacks::total 1559463 # number of writebacks 698system.cpu.dcache.ReadReq_mshr_hits::cpu.data 834370 # number of ReadReq MSHR hits 699system.cpu.dcache.ReadReq_mshr_hits::total 834370 # number of ReadReq MSHR hits 700system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44863 # number of WriteReq MSHR hits 701system.cpu.dcache.WriteReq_mshr_hits::total 44863 # number of WriteReq MSHR hits 702system.cpu.dcache.demand_mshr_hits::cpu.data 879233 # number of demand (read+write) MSHR hits 703system.cpu.dcache.demand_mshr_hits::total 879233 # number of demand (read+write) MSHR hits 704system.cpu.dcache.overall_mshr_hits::cpu.data 879233 # number of overall MSHR hits 705system.cpu.dcache.overall_mshr_hits::total 879233 # number of overall MSHR hits 706system.cpu.dcache.ReadReq_mshr_misses::cpu.data 966248 # number of ReadReq MSHR misses 707system.cpu.dcache.ReadReq_mshr_misses::total 966248 # number of ReadReq MSHR misses 708system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290324 # number of WriteReq MSHR misses 709system.cpu.dcache.WriteReq_mshr_misses::total 290324 # number of WriteReq MSHR misses 710system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403128 # number of SoftPFReq MSHR misses 711system.cpu.dcache.SoftPFReq_mshr_misses::total 403128 # number of SoftPFReq MSHR misses 712system.cpu.dcache.demand_mshr_misses::cpu.data 1256572 # number of demand (read+write) MSHR misses 713system.cpu.dcache.demand_mshr_misses::total 1256572 # number of demand (read+write) MSHR misses 714system.cpu.dcache.overall_mshr_misses::cpu.data 1659700 # number of overall MSHR misses 715system.cpu.dcache.overall_mshr_misses::total 1659700 # number of overall MSHR misses 716system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602897 # number of ReadReq MSHR uncacheable 717system.cpu.dcache.ReadReq_mshr_uncacheable::total 602897 # number of ReadReq MSHR uncacheable 718system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13882 # number of WriteReq MSHR uncacheable 719system.cpu.dcache.WriteReq_mshr_uncacheable::total 13882 # number of WriteReq MSHR uncacheable 720system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616779 # number of overall MSHR uncacheable misses 721system.cpu.dcache.overall_mshr_uncacheable_misses::total 616779 # number of overall MSHR uncacheable misses 722system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14275238000 # number of ReadReq MSHR miss cycles 723system.cpu.dcache.ReadReq_mshr_miss_latency::total 14275238000 # number of ReadReq MSHR miss cycles 724system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19179377736 # number of WriteReq MSHR miss cycles 725system.cpu.dcache.WriteReq_mshr_miss_latency::total 19179377736 # number of WriteReq MSHR miss cycles 726system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6821935500 # number of SoftPFReq MSHR miss cycles 727system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6821935500 # number of SoftPFReq MSHR miss cycles 728system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33454615736 # number of demand (read+write) MSHR miss cycles 729system.cpu.dcache.demand_mshr_miss_latency::total 33454615736 # number of demand (read+write) MSHR miss cycles 730system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40276551236 # number of overall MSHR miss cycles 731system.cpu.dcache.overall_mshr_miss_latency::total 40276551236 # number of overall MSHR miss cycles 732system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793888500 # number of ReadReq MSHR uncacheable cycles 733system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793888500 # number of ReadReq MSHR uncacheable cycles 734system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2616393000 # number of WriteReq MSHR uncacheable cycles 735system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2616393000 # number of WriteReq MSHR uncacheable cycles 736system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100410281500 # number of overall MSHR uncacheable cycles 737system.cpu.dcache.overall_mshr_uncacheable_latency::total 100410281500 # number of overall MSHR uncacheable cycles 738system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076561 # mshr miss rate for ReadReq accesses 739system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076561 # mshr miss rate for ReadReq accesses 740system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034511 # mshr miss rate for WriteReq accesses 741system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034511 # mshr miss rate for WriteReq accesses 742system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858263 # mshr miss rate for SoftPFReq accesses 743system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858263 # mshr miss rate for SoftPFReq accesses 744system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059743 # mshr miss rate for demand accesses 745system.cpu.dcache.demand_mshr_miss_rate::total 0.059743 # mshr miss rate for demand accesses 746system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077185 # mshr miss rate for overall accesses 747system.cpu.dcache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses 748system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14773.886207 # average ReadReq mshr miss latency 749system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14773.886207 # average ReadReq mshr miss latency 750system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66061.978121 # average WriteReq mshr miss latency 751system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66061.978121 # average WriteReq mshr miss latency 752system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16922.504763 # average SoftPFReq mshr miss latency 753system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16922.504763 # average SoftPFReq mshr miss latency 754system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26623.715741 # average overall mshr miss latency 755system.cpu.dcache.demand_avg_mshr_miss_latency::total 26623.715741 # average overall mshr miss latency 756system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24267.368341 # average overall mshr miss latency 757system.cpu.dcache.overall_avg_mshr_miss_latency::total 24267.368341 # average overall mshr miss latency 758system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.626505 # average ReadReq mshr uncacheable latency 759system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.626505 # average ReadReq mshr uncacheable latency 760system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188473.778994 # average WriteReq mshr uncacheable latency 761system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188473.778994 # average WriteReq mshr uncacheable latency 762system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.827909 # average overall mshr uncacheable latency 763system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909 # average overall mshr uncacheable latency |
| 769system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 764system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 770system.cpu.dtb_walker_cache.tags.replacements 71018 # number of replacements 771system.cpu.dtb_walker_cache.tags.tagsinuse 15.855051 # Cycle average of tags in use 772system.cpu.dtb_walker_cache.tags.total_refs 110090 # Total number of references to valid blocks. 773system.cpu.dtb_walker_cache.tags.sampled_refs 71033 # Sample count of references to valid blocks. 774system.cpu.dtb_walker_cache.tags.avg_refs 1.549843 # Average number of references to valid blocks. 775system.cpu.dtb_walker_cache.tags.warmup_cycle 197734009500 # Cycle when the warmup percentage was hit. 776system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.855051 # Average occupied blocks per requestor 777system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.990941 # Average percentage of cache occupancy 778system.cpu.dtb_walker_cache.tags.occ_percent::total 0.990941 # Average percentage of cache occupancy | 765system.cpu.dtb_walker_cache.tags.replacements 86946 # number of replacements 766system.cpu.dtb_walker_cache.tags.tagsinuse 15.839570 # Cycle average of tags in use 767system.cpu.dtb_walker_cache.tags.total_refs 92503 # Total number of references to valid blocks. 768system.cpu.dtb_walker_cache.tags.sampled_refs 86961 # Sample count of references to valid blocks. 769system.cpu.dtb_walker_cache.tags.avg_refs 1.063730 # Average number of references to valid blocks. 770system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500 # Cycle when the warmup percentage was hit. 771system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.839570 # Average occupied blocks per requestor 772system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.989973 # Average percentage of cache occupancy 773system.cpu.dtb_walker_cache.tags.occ_percent::total 0.989973 # Average percentage of cache occupancy |
| 779system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id | 774system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id |
| 780system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 781system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 782system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id | 775system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 776system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id |
| 783system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id | 777system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id |
| 784system.cpu.dtb_walker_cache.tags.tag_accesses 436469 # Number of tag accesses 785system.cpu.dtb_walker_cache.tags.data_accesses 436469 # Number of data accesses 786system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110104 # number of ReadReq hits 787system.cpu.dtb_walker_cache.ReadReq_hits::total 110104 # number of ReadReq hits 788system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110104 # number of demand (read+write) hits 789system.cpu.dtb_walker_cache.demand_hits::total 110104 # number of demand (read+write) hits 790system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110104 # number of overall hits 791system.cpu.dtb_walker_cache.overall_hits::total 110104 # number of overall hits 792system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 72087 # number of ReadReq misses 793system.cpu.dtb_walker_cache.ReadReq_misses::total 72087 # number of ReadReq misses 794system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 72087 # number of demand (read+write) misses 795system.cpu.dtb_walker_cache.demand_misses::total 72087 # number of demand (read+write) misses 796system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 72087 # number of overall misses 797system.cpu.dtb_walker_cache.overall_misses::total 72087 # number of overall misses 798system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 888705500 # number of ReadReq miss cycles 799system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 888705500 # number of ReadReq miss cycles 800system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 888705500 # number of demand (read+write) miss cycles 801system.cpu.dtb_walker_cache.demand_miss_latency::total 888705500 # number of demand (read+write) miss cycles 802system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 888705500 # number of overall miss cycles 803system.cpu.dtb_walker_cache.overall_miss_latency::total 888705500 # number of overall miss cycles 804system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182191 # number of ReadReq accesses(hits+misses) 805system.cpu.dtb_walker_cache.ReadReq_accesses::total 182191 # number of ReadReq accesses(hits+misses) 806system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182191 # number of demand (read+write) accesses 807system.cpu.dtb_walker_cache.demand_accesses::total 182191 # number of demand (read+write) accesses 808system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182191 # number of overall (read+write) accesses 809system.cpu.dtb_walker_cache.overall_accesses::total 182191 # number of overall (read+write) accesses 810system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395667 # miss rate for ReadReq accesses 811system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395667 # miss rate for ReadReq accesses 812system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395667 # miss rate for demand accesses 813system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395667 # miss rate for demand accesses 814system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395667 # miss rate for overall accesses 815system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395667 # miss rate for overall accesses 816system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12328.235327 # average ReadReq miss latency 817system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12328.235327 # average ReadReq miss latency 818system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency 819system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12328.235327 # average overall miss latency 820system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency 821system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12328.235327 # average overall miss latency | 778system.cpu.dtb_walker_cache.tags.tag_accesses 449092 # Number of tag accesses 779system.cpu.dtb_walker_cache.tags.data_accesses 449092 # Number of data accesses 780system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92507 # number of ReadReq hits 781system.cpu.dtb_walker_cache.ReadReq_hits::total 92507 # number of ReadReq hits 782system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92507 # number of demand (read+write) hits 783system.cpu.dtb_walker_cache.demand_hits::total 92507 # number of demand (read+write) hits 784system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92507 # number of overall hits 785system.cpu.dtb_walker_cache.overall_hits::total 92507 # number of overall hits 786system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 88026 # number of ReadReq misses 787system.cpu.dtb_walker_cache.ReadReq_misses::total 88026 # number of ReadReq misses 788system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 88026 # number of demand (read+write) misses 789system.cpu.dtb_walker_cache.demand_misses::total 88026 # number of demand (read+write) misses 790system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 88026 # number of overall misses 791system.cpu.dtb_walker_cache.overall_misses::total 88026 # number of overall misses 792system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1095128000 # number of ReadReq miss cycles 793system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1095128000 # number of ReadReq miss cycles 794system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1095128000 # number of demand (read+write) miss cycles 795system.cpu.dtb_walker_cache.demand_miss_latency::total 1095128000 # number of demand (read+write) miss cycles 796system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1095128000 # number of overall miss cycles 797system.cpu.dtb_walker_cache.overall_miss_latency::total 1095128000 # number of overall miss cycles 798system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180533 # number of ReadReq accesses(hits+misses) 799system.cpu.dtb_walker_cache.ReadReq_accesses::total 180533 # number of ReadReq accesses(hits+misses) 800system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180533 # number of demand (read+write) accesses 801system.cpu.dtb_walker_cache.demand_accesses::total 180533 # number of demand (read+write) accesses 802system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180533 # number of overall (read+write) accesses 803system.cpu.dtb_walker_cache.overall_accesses::total 180533 # number of overall (read+write) accesses 804system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.487590 # miss rate for ReadReq accesses 805system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.487590 # miss rate for ReadReq accesses 806system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.487590 # miss rate for demand accesses 807system.cpu.dtb_walker_cache.demand_miss_rate::total 0.487590 # miss rate for demand accesses 808system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.487590 # miss rate for overall accesses 809system.cpu.dtb_walker_cache.overall_miss_rate::total 0.487590 # miss rate for overall accesses 810system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625 # average ReadReq miss latency 811system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625 # average ReadReq miss latency 812system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency 813system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625 # average overall miss latency 814system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency 815system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625 # average overall miss latency |
| 822system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 823system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 824system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 825system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 826system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 827system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 828system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 829system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 816system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 817system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 818system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 819system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 820system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 821system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 822system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 823system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 830system.cpu.dtb_walker_cache.writebacks::writebacks 17880 # number of writebacks 831system.cpu.dtb_walker_cache.writebacks::total 17880 # number of writebacks 832system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 72087 # number of ReadReq MSHR misses 833system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 72087 # number of ReadReq MSHR misses 834system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 72087 # number of demand (read+write) MSHR misses 835system.cpu.dtb_walker_cache.demand_mshr_misses::total 72087 # number of demand (read+write) MSHR misses 836system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 72087 # number of overall MSHR misses 837system.cpu.dtb_walker_cache.overall_mshr_misses::total 72087 # number of overall MSHR misses 838system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 816618500 # number of ReadReq MSHR miss cycles 839system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 816618500 # number of ReadReq MSHR miss cycles 840system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 816618500 # number of demand (read+write) MSHR miss cycles 841system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 816618500 # number of demand (read+write) MSHR miss cycles 842system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 816618500 # number of overall MSHR miss cycles 843system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 816618500 # number of overall MSHR miss cycles 844system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for ReadReq accesses 845system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395667 # mshr miss rate for ReadReq accesses 846system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for demand accesses 847system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395667 # mshr miss rate for demand accesses 848system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for overall accesses 849system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395667 # mshr miss rate for overall accesses 850system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average ReadReq mshr miss latency 851system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11328.235327 # average ReadReq mshr miss latency 852system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency 853system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency 854system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency 855system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency | 824system.cpu.dtb_walker_cache.writebacks::writebacks 22750 # number of writebacks 825system.cpu.dtb_walker_cache.writebacks::total 22750 # number of writebacks 826system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 88026 # number of ReadReq MSHR misses 827system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 88026 # number of ReadReq MSHR misses 828system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 88026 # number of demand (read+write) MSHR misses 829system.cpu.dtb_walker_cache.demand_mshr_misses::total 88026 # number of demand (read+write) MSHR misses 830system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 88026 # number of overall MSHR misses 831system.cpu.dtb_walker_cache.overall_mshr_misses::total 88026 # number of overall MSHR misses 832system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of ReadReq MSHR miss cycles 833system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1007102000 # number of ReadReq MSHR miss cycles 834system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of demand (read+write) MSHR miss cycles 835system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1007102000 # number of demand (read+write) MSHR miss cycles 836system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of overall MSHR miss cycles 837system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1007102000 # number of overall MSHR miss cycles 838system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for ReadReq accesses 839system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.487590 # mshr miss rate for ReadReq accesses 840system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for demand accesses 841system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.487590 # mshr miss rate for demand accesses 842system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for overall accesses 843system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.487590 # mshr miss rate for overall accesses 844system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average ReadReq mshr miss latency 845system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625 # average ReadReq mshr miss latency 846system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency 847system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency 848system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency 849system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency |
| 856system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 850system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 857system.cpu.icache.tags.replacements 972475 # number of replacements 858system.cpu.icache.tags.tagsinuse 509.589862 # Cycle average of tags in use 859system.cpu.icache.tags.total_refs 7892622 # Total number of references to valid blocks. 860system.cpu.icache.tags.sampled_refs 972987 # Sample count of references to valid blocks. 861system.cpu.icache.tags.avg_refs 8.111745 # Average number of references to valid blocks. 862system.cpu.icache.tags.warmup_cycle 147937650500 # Cycle when the warmup percentage was hit. 863system.cpu.icache.tags.occ_blocks::cpu.inst 509.589862 # Average occupied blocks per requestor 864system.cpu.icache.tags.occ_percent::cpu.inst 0.995293 # Average percentage of cache occupancy 865system.cpu.icache.tags.occ_percent::total 0.995293 # Average percentage of cache occupancy | 851system.cpu.icache.tags.replacements 979952 # number of replacements 852system.cpu.icache.tags.tagsinuse 509.399185 # Cycle average of tags in use 853system.cpu.icache.tags.total_refs 7892668 # Total number of references to valid blocks. 854system.cpu.icache.tags.sampled_refs 980464 # Sample count of references to valid blocks. 855system.cpu.icache.tags.avg_refs 8.049931 # Average number of references to valid blocks. 856system.cpu.icache.tags.warmup_cycle 150322947500 # Cycle when the warmup percentage was hit. 857system.cpu.icache.tags.occ_blocks::cpu.inst 509.399185 # Average occupied blocks per requestor 858system.cpu.icache.tags.occ_percent::cpu.inst 0.994920 # Average percentage of cache occupancy 859system.cpu.icache.tags.occ_percent::total 0.994920 # Average percentage of cache occupancy |
| 866system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 860system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 867system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id | 861system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id |
| 868system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id | 862system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id |
| 869system.cpu.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id | 863system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id |
| 870system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 864system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 871system.cpu.icache.tags.tag_accesses 9905522 # Number of tag accesses 872system.cpu.icache.tags.data_accesses 9905522 # Number of data accesses 873system.cpu.icache.ReadReq_hits::cpu.inst 7892622 # number of ReadReq hits 874system.cpu.icache.ReadReq_hits::total 7892622 # number of ReadReq hits 875system.cpu.icache.demand_hits::cpu.inst 7892622 # number of demand (read+write) hits 876system.cpu.icache.demand_hits::total 7892622 # number of demand (read+write) hits 877system.cpu.icache.overall_hits::cpu.inst 7892622 # number of overall hits 878system.cpu.icache.overall_hits::total 7892622 # number of overall hits 879system.cpu.icache.ReadReq_misses::cpu.inst 1039533 # number of ReadReq misses 880system.cpu.icache.ReadReq_misses::total 1039533 # number of ReadReq misses 881system.cpu.icache.demand_misses::cpu.inst 1039533 # number of demand (read+write) misses 882system.cpu.icache.demand_misses::total 1039533 # number of demand (read+write) misses 883system.cpu.icache.overall_misses::cpu.inst 1039533 # number of overall misses 884system.cpu.icache.overall_misses::total 1039533 # number of overall misses 885system.cpu.icache.ReadReq_miss_latency::cpu.inst 14506630997 # number of ReadReq miss cycles 886system.cpu.icache.ReadReq_miss_latency::total 14506630997 # number of ReadReq miss cycles 887system.cpu.icache.demand_miss_latency::cpu.inst 14506630997 # number of demand (read+write) miss cycles 888system.cpu.icache.demand_miss_latency::total 14506630997 # number of demand (read+write) miss cycles 889system.cpu.icache.overall_miss_latency::cpu.inst 14506630997 # number of overall miss cycles 890system.cpu.icache.overall_miss_latency::total 14506630997 # number of overall miss cycles 891system.cpu.icache.ReadReq_accesses::cpu.inst 8932155 # number of ReadReq accesses(hits+misses) 892system.cpu.icache.ReadReq_accesses::total 8932155 # number of ReadReq accesses(hits+misses) 893system.cpu.icache.demand_accesses::cpu.inst 8932155 # number of demand (read+write) accesses 894system.cpu.icache.demand_accesses::total 8932155 # number of demand (read+write) accesses 895system.cpu.icache.overall_accesses::cpu.inst 8932155 # number of overall (read+write) accesses 896system.cpu.icache.overall_accesses::total 8932155 # number of overall (read+write) accesses 897system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116381 # miss rate for ReadReq accesses 898system.cpu.icache.ReadReq_miss_rate::total 0.116381 # miss rate for ReadReq accesses 899system.cpu.icache.demand_miss_rate::cpu.inst 0.116381 # miss rate for demand accesses 900system.cpu.icache.demand_miss_rate::total 0.116381 # miss rate for demand accesses 901system.cpu.icache.overall_miss_rate::cpu.inst 0.116381 # miss rate for overall accesses 902system.cpu.icache.overall_miss_rate::total 0.116381 # miss rate for overall accesses 903system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13954.949960 # average ReadReq miss latency 904system.cpu.icache.ReadReq_avg_miss_latency::total 13954.949960 # average ReadReq miss latency 905system.cpu.icache.demand_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency 906system.cpu.icache.demand_avg_miss_latency::total 13954.949960 # average overall miss latency 907system.cpu.icache.overall_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency 908system.cpu.icache.overall_avg_miss_latency::total 13954.949960 # average overall miss latency 909system.cpu.icache.blocked_cycles::no_mshrs 6454 # number of cycles access was blocked 910system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked 911system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked 912system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 913system.cpu.icache.avg_blocked_cycles::no_mshrs 20.554140 # average number of cycles each access was blocked 914system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked | 865system.cpu.icache.tags.tag_accesses 9920034 # Number of tag accesses 866system.cpu.icache.tags.data_accesses 9920034 # Number of data accesses 867system.cpu.icache.ReadReq_hits::cpu.inst 7892668 # number of ReadReq hits 868system.cpu.icache.ReadReq_hits::total 7892668 # number of ReadReq hits 869system.cpu.icache.demand_hits::cpu.inst 7892668 # number of demand (read+write) hits 870system.cpu.icache.demand_hits::total 7892668 # number of demand (read+write) hits 871system.cpu.icache.overall_hits::cpu.inst 7892668 # number of overall hits 872system.cpu.icache.overall_hits::total 7892668 # number of overall hits 873system.cpu.icache.ReadReq_misses::cpu.inst 1046827 # number of ReadReq misses 874system.cpu.icache.ReadReq_misses::total 1046827 # number of ReadReq misses 875system.cpu.icache.demand_misses::cpu.inst 1046827 # number of demand (read+write) misses 876system.cpu.icache.demand_misses::total 1046827 # number of demand (read+write) misses 877system.cpu.icache.overall_misses::cpu.inst 1046827 # number of overall misses 878system.cpu.icache.overall_misses::total 1046827 # number of overall misses 879system.cpu.icache.ReadReq_miss_latency::cpu.inst 15679887484 # number of ReadReq miss cycles 880system.cpu.icache.ReadReq_miss_latency::total 15679887484 # number of ReadReq miss cycles 881system.cpu.icache.demand_miss_latency::cpu.inst 15679887484 # number of demand (read+write) miss cycles 882system.cpu.icache.demand_miss_latency::total 15679887484 # number of demand (read+write) miss cycles 883system.cpu.icache.overall_miss_latency::cpu.inst 15679887484 # number of overall miss cycles 884system.cpu.icache.overall_miss_latency::total 15679887484 # number of overall miss cycles 885system.cpu.icache.ReadReq_accesses::cpu.inst 8939495 # number of ReadReq accesses(hits+misses) 886system.cpu.icache.ReadReq_accesses::total 8939495 # number of ReadReq accesses(hits+misses) 887system.cpu.icache.demand_accesses::cpu.inst 8939495 # number of demand (read+write) accesses 888system.cpu.icache.demand_accesses::total 8939495 # number of demand (read+write) accesses 889system.cpu.icache.overall_accesses::cpu.inst 8939495 # number of overall (read+write) accesses 890system.cpu.icache.overall_accesses::total 8939495 # number of overall (read+write) accesses 891system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117101 # miss rate for ReadReq accesses 892system.cpu.icache.ReadReq_miss_rate::total 0.117101 # miss rate for ReadReq accesses 893system.cpu.icache.demand_miss_rate::cpu.inst 0.117101 # miss rate for demand accesses 894system.cpu.icache.demand_miss_rate::total 0.117101 # miss rate for demand accesses 895system.cpu.icache.overall_miss_rate::cpu.inst 0.117101 # miss rate for overall accesses 896system.cpu.icache.overall_miss_rate::total 0.117101 # miss rate for overall accesses 897system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.489745 # average ReadReq miss latency 898system.cpu.icache.ReadReq_avg_miss_latency::total 14978.489745 # average ReadReq miss latency 899system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency 900system.cpu.icache.demand_avg_miss_latency::total 14978.489745 # average overall miss latency 901system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency 902system.cpu.icache.overall_avg_miss_latency::total 14978.489745 # average overall miss latency 903system.cpu.icache.blocked_cycles::no_mshrs 13392 # number of cycles access was blocked 904system.cpu.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked 905system.cpu.icache.blocked::no_mshrs 457 # number of cycles access was blocked 906system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 907system.cpu.icache.avg_blocked_cycles::no_mshrs 29.304158 # average number of cycles each access was blocked 908system.cpu.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked |
| 915system.cpu.icache.fast_writes 0 # number of fast writes performed 916system.cpu.icache.cache_copies 0 # number of cache copies performed | 909system.cpu.icache.fast_writes 0 # number of fast writes performed 910system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 917system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66166 # number of ReadReq MSHR hits 918system.cpu.icache.ReadReq_mshr_hits::total 66166 # number of ReadReq MSHR hits 919system.cpu.icache.demand_mshr_hits::cpu.inst 66166 # number of demand (read+write) MSHR hits 920system.cpu.icache.demand_mshr_hits::total 66166 # number of demand (read+write) MSHR hits 921system.cpu.icache.overall_mshr_hits::cpu.inst 66166 # number of overall MSHR hits 922system.cpu.icache.overall_mshr_hits::total 66166 # number of overall MSHR hits 923system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973367 # number of ReadReq MSHR misses 924system.cpu.icache.ReadReq_mshr_misses::total 973367 # number of ReadReq MSHR misses 925system.cpu.icache.demand_mshr_misses::cpu.inst 973367 # number of demand (read+write) MSHR misses 926system.cpu.icache.demand_mshr_misses::total 973367 # number of demand (read+write) MSHR misses 927system.cpu.icache.overall_mshr_misses::cpu.inst 973367 # number of overall MSHR misses 928system.cpu.icache.overall_mshr_misses::total 973367 # number of overall MSHR misses 929system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12880264497 # number of ReadReq MSHR miss cycles 930system.cpu.icache.ReadReq_mshr_miss_latency::total 12880264497 # number of ReadReq MSHR miss cycles 931system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12880264497 # number of demand (read+write) MSHR miss cycles 932system.cpu.icache.demand_mshr_miss_latency::total 12880264497 # number of demand (read+write) MSHR miss cycles 933system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12880264497 # number of overall MSHR miss cycles 934system.cpu.icache.overall_mshr_miss_latency::total 12880264497 # number of overall MSHR miss cycles 935system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for ReadReq accesses 936system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108973 # mshr miss rate for ReadReq accesses 937system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for demand accesses 938system.cpu.icache.demand_mshr_miss_rate::total 0.108973 # mshr miss rate for demand accesses 939system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for overall accesses 940system.cpu.icache.overall_mshr_miss_rate::total 0.108973 # mshr miss rate for overall accesses 941system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13232.690750 # average ReadReq mshr miss latency 942system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13232.690750 # average ReadReq mshr miss latency 943system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency 944system.cpu.icache.demand_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency 945system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency 946system.cpu.icache.overall_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency | 911system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66288 # number of ReadReq MSHR hits 912system.cpu.icache.ReadReq_mshr_hits::total 66288 # number of ReadReq MSHR hits 913system.cpu.icache.demand_mshr_hits::cpu.inst 66288 # number of demand (read+write) MSHR hits 914system.cpu.icache.demand_mshr_hits::total 66288 # number of demand (read+write) MSHR hits 915system.cpu.icache.overall_mshr_hits::cpu.inst 66288 # number of overall MSHR hits 916system.cpu.icache.overall_mshr_hits::total 66288 # number of overall MSHR hits 917system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980539 # number of ReadReq MSHR misses 918system.cpu.icache.ReadReq_mshr_misses::total 980539 # number of ReadReq MSHR misses 919system.cpu.icache.demand_mshr_misses::cpu.inst 980539 # number of demand (read+write) MSHR misses 920system.cpu.icache.demand_mshr_misses::total 980539 # number of demand (read+write) MSHR misses 921system.cpu.icache.overall_mshr_misses::cpu.inst 980539 # number of overall MSHR misses 922system.cpu.icache.overall_mshr_misses::total 980539 # number of overall MSHR misses 923system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13806283989 # number of ReadReq MSHR miss cycles 924system.cpu.icache.ReadReq_mshr_miss_latency::total 13806283989 # number of ReadReq MSHR miss cycles 925system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13806283989 # number of demand (read+write) MSHR miss cycles 926system.cpu.icache.demand_mshr_miss_latency::total 13806283989 # number of demand (read+write) MSHR miss cycles 927system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13806283989 # number of overall MSHR miss cycles 928system.cpu.icache.overall_mshr_miss_latency::total 13806283989 # number of overall MSHR miss cycles 929system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for ReadReq accesses 930system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109686 # mshr miss rate for ReadReq accesses 931system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for demand accesses 932system.cpu.icache.demand_mshr_miss_rate::total 0.109686 # mshr miss rate for demand accesses 933system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for overall accesses 934system.cpu.icache.overall_mshr_miss_rate::total 0.109686 # mshr miss rate for overall accesses 935system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14080.300721 # average ReadReq mshr miss latency 936system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14080.300721 # average ReadReq mshr miss latency 937system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency 938system.cpu.icache.demand_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency 939system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency 940system.cpu.icache.overall_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency |
| 947system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 941system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 948system.cpu.itb_walker_cache.tags.replacements 13962 # number of replacements 949system.cpu.itb_walker_cache.tags.tagsinuse 6.017494 # Cycle average of tags in use 950system.cpu.itb_walker_cache.tags.total_refs 24005 # Total number of references to valid blocks. 951system.cpu.itb_walker_cache.tags.sampled_refs 13975 # Sample count of references to valid blocks. 952system.cpu.itb_walker_cache.tags.avg_refs 1.717710 # Average number of references to valid blocks. 953system.cpu.itb_walker_cache.tags.warmup_cycle 5100174829000 # Cycle when the warmup percentage was hit. 954system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017494 # Average occupied blocks per requestor 955system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376093 # Average percentage of cache occupancy 956system.cpu.itb_walker_cache.tags.occ_percent::total 0.376093 # Average percentage of cache occupancy 957system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 958system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 959system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 960system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 961system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 962system.cpu.itb_walker_cache.tags.tag_accesses 92555 # Number of tag accesses 963system.cpu.itb_walker_cache.tags.data_accesses 92555 # Number of data accesses 964system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24014 # number of ReadReq hits 965system.cpu.itb_walker_cache.ReadReq_hits::total 24014 # number of ReadReq hits | 942system.cpu.itb_walker_cache.tags.replacements 19284 # number of replacements 943system.cpu.itb_walker_cache.tags.tagsinuse 6.025119 # Cycle average of tags in use 944system.cpu.itb_walker_cache.tags.total_refs 17613 # Total number of references to valid blocks. 945system.cpu.itb_walker_cache.tags.sampled_refs 19298 # Sample count of references to valid blocks. 946system.cpu.itb_walker_cache.tags.avg_refs 0.912685 # Average number of references to valid blocks. 947system.cpu.itb_walker_cache.tags.warmup_cycle 5119738953000 # Cycle when the warmup percentage was hit. 948system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.025119 # Average occupied blocks per requestor 949system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376570 # Average percentage of cache occupancy 950system.cpu.itb_walker_cache.tags.occ_percent::total 0.376570 # Average percentage of cache occupancy 951system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 952system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 953system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 954system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 955system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 956system.cpu.itb_walker_cache.tags.tag_accesses 95741 # Number of tag accesses 957system.cpu.itb_walker_cache.tags.data_accesses 95741 # Number of data accesses 958system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 17618 # number of ReadReq hits 959system.cpu.itb_walker_cache.ReadReq_hits::total 17618 # number of ReadReq hits |
| 966system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 967system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 960system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 961system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 968system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24016 # number of demand (read+write) hits 969system.cpu.itb_walker_cache.demand_hits::total 24016 # number of demand (read+write) hits 970system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24016 # number of overall hits 971system.cpu.itb_walker_cache.overall_hits::total 24016 # number of overall hits 972system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14841 # number of ReadReq misses 973system.cpu.itb_walker_cache.ReadReq_misses::total 14841 # number of ReadReq misses 974system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14841 # number of demand (read+write) misses 975system.cpu.itb_walker_cache.demand_misses::total 14841 # number of demand (read+write) misses 976system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14841 # number of overall misses 977system.cpu.itb_walker_cache.overall_misses::total 14841 # number of overall misses 978system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 170100000 # number of ReadReq miss cycles 979system.cpu.itb_walker_cache.ReadReq_miss_latency::total 170100000 # number of ReadReq miss cycles 980system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 170100000 # number of demand (read+write) miss cycles 981system.cpu.itb_walker_cache.demand_miss_latency::total 170100000 # number of demand (read+write) miss cycles 982system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 170100000 # number of overall miss cycles 983system.cpu.itb_walker_cache.overall_miss_latency::total 170100000 # number of overall miss cycles 984system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38855 # number of ReadReq accesses(hits+misses) 985system.cpu.itb_walker_cache.ReadReq_accesses::total 38855 # number of ReadReq accesses(hits+misses) | 962system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 17620 # number of demand (read+write) hits 963system.cpu.itb_walker_cache.demand_hits::total 17620 # number of demand (read+write) hits 964system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 17620 # number of overall hits 965system.cpu.itb_walker_cache.overall_hits::total 17620 # number of overall hits 966system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 20167 # number of ReadReq misses 967system.cpu.itb_walker_cache.ReadReq_misses::total 20167 # number of ReadReq misses 968system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 20167 # number of demand (read+write) misses 969system.cpu.itb_walker_cache.demand_misses::total 20167 # number of demand (read+write) misses 970system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 20167 # number of overall misses 971system.cpu.itb_walker_cache.overall_misses::total 20167 # number of overall misses 972system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 233184000 # number of ReadReq miss cycles 973system.cpu.itb_walker_cache.ReadReq_miss_latency::total 233184000 # number of ReadReq miss cycles 974system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 233184000 # number of demand (read+write) miss cycles 975system.cpu.itb_walker_cache.demand_miss_latency::total 233184000 # number of demand (read+write) miss cycles 976system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 233184000 # number of overall miss cycles 977system.cpu.itb_walker_cache.overall_miss_latency::total 233184000 # number of overall miss cycles 978system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37785 # number of ReadReq accesses(hits+misses) 979system.cpu.itb_walker_cache.ReadReq_accesses::total 37785 # number of ReadReq accesses(hits+misses) |
| 986system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 987system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 980system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 981system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 988system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38857 # number of demand (read+write) accesses 989system.cpu.itb_walker_cache.demand_accesses::total 38857 # number of demand (read+write) accesses 990system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38857 # number of overall (read+write) accesses 991system.cpu.itb_walker_cache.overall_accesses::total 38857 # number of overall (read+write) accesses 992system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381959 # miss rate for ReadReq accesses 993system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381959 # miss rate for ReadReq accesses 994system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381939 # miss rate for demand accesses 995system.cpu.itb_walker_cache.demand_miss_rate::total 0.381939 # miss rate for demand accesses 996system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381939 # miss rate for overall accesses 997system.cpu.itb_walker_cache.overall_miss_rate::total 0.381939 # miss rate for overall accesses 998system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11461.491813 # average ReadReq miss latency 999system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11461.491813 # average ReadReq miss latency 1000system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency 1001system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11461.491813 # average overall miss latency 1002system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency 1003system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11461.491813 # average overall miss latency | 982system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37787 # number of demand (read+write) accesses 983system.cpu.itb_walker_cache.demand_accesses::total 37787 # number of demand (read+write) accesses 984system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37787 # number of overall (read+write) accesses 985system.cpu.itb_walker_cache.overall_accesses::total 37787 # number of overall (read+write) accesses 986system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.533730 # miss rate for ReadReq accesses 987system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.533730 # miss rate for ReadReq accesses 988system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.533702 # miss rate for demand accesses 989system.cpu.itb_walker_cache.demand_miss_rate::total 0.533702 # miss rate for demand accesses 990system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.533702 # miss rate for overall accesses 991system.cpu.itb_walker_cache.overall_miss_rate::total 0.533702 # miss rate for overall accesses 992system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11562.651857 # average ReadReq miss latency 993system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11562.651857 # average ReadReq miss latency 994system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency 995system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11562.651857 # average overall miss latency 996system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency 997system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11562.651857 # average overall miss latency |
| 1004system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1005system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1006system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1007system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1008system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1009system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1010system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1011system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 998system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 999system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1000system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1001system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1002system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1003system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1004system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1005system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1012system.cpu.itb_walker_cache.writebacks::writebacks 2319 # number of writebacks 1013system.cpu.itb_walker_cache.writebacks::total 2319 # number of writebacks 1014system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14841 # number of ReadReq MSHR misses 1015system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14841 # number of ReadReq MSHR misses 1016system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14841 # number of demand (read+write) MSHR misses 1017system.cpu.itb_walker_cache.demand_mshr_misses::total 14841 # number of demand (read+write) MSHR misses 1018system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14841 # number of overall MSHR misses 1019system.cpu.itb_walker_cache.overall_mshr_misses::total 14841 # number of overall MSHR misses 1020system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155259000 # number of ReadReq MSHR miss cycles 1021system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155259000 # number of ReadReq MSHR miss cycles 1022system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155259000 # number of demand (read+write) MSHR miss cycles 1023system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155259000 # number of demand (read+write) MSHR miss cycles 1024system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155259000 # number of overall MSHR miss cycles 1025system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155259000 # number of overall MSHR miss cycles 1026system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381959 # mshr miss rate for ReadReq accesses 1027system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381959 # mshr miss rate for ReadReq accesses 1028system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for demand accesses 1029system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381939 # mshr miss rate for demand accesses 1030system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for overall accesses 1031system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381939 # mshr miss rate for overall accesses 1032system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average ReadReq mshr miss latency 1033system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10461.491813 # average ReadReq mshr miss latency 1034system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency 1035system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency 1036system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency 1037system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency | 1006system.cpu.itb_walker_cache.writebacks::writebacks 3197 # number of writebacks 1007system.cpu.itb_walker_cache.writebacks::total 3197 # number of writebacks 1008system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 20167 # number of ReadReq MSHR misses 1009system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 20167 # number of ReadReq MSHR misses 1010system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 20167 # number of demand (read+write) MSHR misses 1011system.cpu.itb_walker_cache.demand_mshr_misses::total 20167 # number of demand (read+write) MSHR misses 1012system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 20167 # number of overall MSHR misses 1013system.cpu.itb_walker_cache.overall_mshr_misses::total 20167 # number of overall MSHR misses 1014system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 213017000 # number of ReadReq MSHR miss cycles 1015system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 213017000 # number of ReadReq MSHR miss cycles 1016system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 213017000 # number of demand (read+write) MSHR miss cycles 1017system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 213017000 # number of demand (read+write) MSHR miss cycles 1018system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 213017000 # number of overall MSHR miss cycles 1019system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 213017000 # number of overall MSHR miss cycles 1020system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.533730 # mshr miss rate for ReadReq accesses 1021system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.533730 # mshr miss rate for ReadReq accesses 1022system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for demand accesses 1023system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.533702 # mshr miss rate for demand accesses 1024system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for overall accesses 1025system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.533702 # mshr miss rate for overall accesses 1026system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average ReadReq mshr miss latency 1027system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.651857 # average ReadReq mshr miss latency 1028system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency 1029system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency 1030system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency 1031system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency |
| 1038system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1032system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1039system.cpu.l2cache.tags.replacements 112328 # number of replacements 1040system.cpu.l2cache.tags.tagsinuse 64826.279220 # Cycle average of tags in use 1041system.cpu.l2cache.tags.total_refs 4884469 # Total number of references to valid blocks. 1042system.cpu.l2cache.tags.sampled_refs 176125 # Sample count of references to valid blocks. 1043system.cpu.l2cache.tags.avg_refs 27.732968 # Average number of references to valid blocks. | 1033system.cpu.l2cache.tags.replacements 111670 # number of replacements 1034system.cpu.l2cache.tags.tagsinuse 64798.131266 # Cycle average of tags in use 1035system.cpu.l2cache.tags.total_refs 4919632 # Total number of references to valid blocks. 1036system.cpu.l2cache.tags.sampled_refs 175949 # Sample count of references to valid blocks. 1037system.cpu.l2cache.tags.avg_refs 27.960557 # Average number of references to valid blocks. |
| 1044system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1038system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1045system.cpu.l2cache.tags.occ_blocks::writebacks 50541.510277 # Average occupied blocks per requestor 1046system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.632944 # Average occupied blocks per requestor 1047system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140332 # Average occupied blocks per requestor 1048system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.306836 # Average occupied blocks per requestor 1049system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.688831 # Average occupied blocks per requestor 1050system.cpu.l2cache.tags.occ_percent::writebacks 0.771202 # Average percentage of cache occupancy 1051system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000208 # Average percentage of cache occupancy | 1039system.cpu.l2cache.tags.occ_blocks::writebacks 50517.509380 # Average occupied blocks per requestor 1040system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.940071 # Average occupied blocks per requestor 1041system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139536 # Average occupied blocks per requestor 1042system.cpu.l2cache.tags.occ_blocks::cpu.inst 3193.810391 # Average occupied blocks per requestor 1043system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.731889 # Average occupied blocks per requestor 1044system.cpu.l2cache.tags.occ_percent::writebacks 0.770836 # Average percentage of cache occupancy 1045system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000167 # Average percentage of cache occupancy |
| 1052system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 1046system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 1053system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047383 # Average percentage of cache occupancy 1054system.cpu.l2cache.tags.occ_percent::cpu.data 0.170375 # Average percentage of cache occupancy 1055system.cpu.l2cache.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy 1056system.cpu.l2cache.tags.occ_task_id_blocks::1024 63797 # Occupied blocks per task id 1057system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 1058system.cpu.l2cache.tags.age_task_id_blocks_1024::1 708 # Occupied blocks per task id 1059system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3407 # Occupied blocks per task id 1060system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5556 # Occupied blocks per task id 1061system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54082 # Occupied blocks per task id 1062system.cpu.l2cache.tags.occ_task_id_percent::1024 0.973465 # Percentage of cache occupancy per task id 1063system.cpu.l2cache.tags.tag_accesses 43431157 # Number of tag accesses 1064system.cpu.l2cache.tags.data_accesses 43431157 # Number of data accesses 1065system.cpu.l2cache.Writeback_hits::writebacks 1578009 # number of Writeback hits 1066system.cpu.l2cache.Writeback_hits::total 1578009 # number of Writeback hits 1067system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits 1068system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits 1069system.cpu.l2cache.ReadExReq_hits::cpu.data 154224 # number of ReadExReq hits 1070system.cpu.l2cache.ReadExReq_hits::total 154224 # number of ReadExReq hits 1071system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 956701 # number of ReadCleanReq hits 1072system.cpu.l2cache.ReadCleanReq_hits::total 956701 # number of ReadCleanReq hits 1073system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 65553 # number of ReadSharedReq hits 1074system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12091 # number of ReadSharedReq hits 1075system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332425 # number of ReadSharedReq hits 1076system.cpu.l2cache.ReadSharedReq_hits::total 1410069 # number of ReadSharedReq hits 1077system.cpu.l2cache.demand_hits::cpu.dtb.walker 65553 # number of demand (read+write) hits 1078system.cpu.l2cache.demand_hits::cpu.itb.walker 12091 # number of demand (read+write) hits 1079system.cpu.l2cache.demand_hits::cpu.inst 956701 # number of demand (read+write) hits 1080system.cpu.l2cache.demand_hits::cpu.data 1486649 # number of demand (read+write) hits 1081system.cpu.l2cache.demand_hits::total 2520994 # number of demand (read+write) hits 1082system.cpu.l2cache.overall_hits::cpu.dtb.walker 65553 # number of overall hits 1083system.cpu.l2cache.overall_hits::cpu.itb.walker 12091 # number of overall hits 1084system.cpu.l2cache.overall_hits::cpu.inst 956701 # number of overall hits 1085system.cpu.l2cache.overall_hits::cpu.data 1486649 # number of overall hits 1086system.cpu.l2cache.overall_hits::total 2520994 # number of overall hits 1087system.cpu.l2cache.UpgradeReq_misses::cpu.data 1786 # number of UpgradeReq misses 1088system.cpu.l2cache.UpgradeReq_misses::total 1786 # number of UpgradeReq misses 1089system.cpu.l2cache.ReadExReq_misses::cpu.data 133488 # number of ReadExReq misses 1090system.cpu.l2cache.ReadExReq_misses::total 133488 # number of ReadExReq misses 1091system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16231 # number of ReadCleanReq misses 1092system.cpu.l2cache.ReadCleanReq_misses::total 16231 # number of ReadCleanReq misses 1093system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 61 # number of ReadSharedReq misses 1094system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 6 # number of ReadSharedReq misses 1095system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35709 # number of ReadSharedReq misses 1096system.cpu.l2cache.ReadSharedReq_misses::total 35776 # number of ReadSharedReq misses 1097system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses 1098system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 1099system.cpu.l2cache.demand_misses::cpu.inst 16231 # number of demand (read+write) misses 1100system.cpu.l2cache.demand_misses::cpu.data 169197 # number of demand (read+write) misses 1101system.cpu.l2cache.demand_misses::total 185495 # number of demand (read+write) misses 1102system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses 1103system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 1104system.cpu.l2cache.overall_misses::cpu.inst 16231 # number of overall misses 1105system.cpu.l2cache.overall_misses::cpu.data 169197 # number of overall misses 1106system.cpu.l2cache.overall_misses::total 185495 # number of overall misses 1107system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23220500 # number of UpgradeReq miss cycles 1108system.cpu.l2cache.UpgradeReq_miss_latency::total 23220500 # number of UpgradeReq miss cycles 1109system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10274230500 # number of ReadExReq miss cycles 1110system.cpu.l2cache.ReadExReq_miss_latency::total 10274230500 # number of ReadExReq miss cycles 1111system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1348223000 # number of ReadCleanReq miss cycles 1112system.cpu.l2cache.ReadCleanReq_miss_latency::total 1348223000 # number of ReadCleanReq miss cycles 1113system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 5829000 # number of ReadSharedReq miss cycles 1114system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 513000 # number of ReadSharedReq miss cycles 1115system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3059963500 # number of ReadSharedReq miss cycles 1116system.cpu.l2cache.ReadSharedReq_miss_latency::total 3066305500 # number of ReadSharedReq miss cycles 1117system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5829000 # number of demand (read+write) miss cycles 1118system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 513000 # number of demand (read+write) miss cycles 1119system.cpu.l2cache.demand_miss_latency::cpu.inst 1348223000 # number of demand (read+write) miss cycles 1120system.cpu.l2cache.demand_miss_latency::cpu.data 13334194000 # number of demand (read+write) miss cycles 1121system.cpu.l2cache.demand_miss_latency::total 14688759000 # number of demand (read+write) miss cycles 1122system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5829000 # number of overall miss cycles 1123system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 513000 # number of overall miss cycles 1124system.cpu.l2cache.overall_miss_latency::cpu.inst 1348223000 # number of overall miss cycles 1125system.cpu.l2cache.overall_miss_latency::cpu.data 13334194000 # number of overall miss cycles 1126system.cpu.l2cache.overall_miss_latency::total 14688759000 # number of overall miss cycles 1127system.cpu.l2cache.Writeback_accesses::writebacks 1578009 # number of Writeback accesses(hits+misses) 1128system.cpu.l2cache.Writeback_accesses::total 1578009 # number of Writeback accesses(hits+misses) 1129system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2107 # number of UpgradeReq accesses(hits+misses) 1130system.cpu.l2cache.UpgradeReq_accesses::total 2107 # number of UpgradeReq accesses(hits+misses) 1131system.cpu.l2cache.ReadExReq_accesses::cpu.data 287712 # number of ReadExReq accesses(hits+misses) 1132system.cpu.l2cache.ReadExReq_accesses::total 287712 # number of ReadExReq accesses(hits+misses) 1133system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 972932 # number of ReadCleanReq accesses(hits+misses) 1134system.cpu.l2cache.ReadCleanReq_accesses::total 972932 # number of ReadCleanReq accesses(hits+misses) 1135system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 65614 # number of ReadSharedReq accesses(hits+misses) 1136system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12097 # number of ReadSharedReq accesses(hits+misses) 1137system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368134 # number of ReadSharedReq accesses(hits+misses) 1138system.cpu.l2cache.ReadSharedReq_accesses::total 1445845 # number of ReadSharedReq accesses(hits+misses) 1139system.cpu.l2cache.demand_accesses::cpu.dtb.walker 65614 # number of demand (read+write) accesses 1140system.cpu.l2cache.demand_accesses::cpu.itb.walker 12097 # number of demand (read+write) accesses 1141system.cpu.l2cache.demand_accesses::cpu.inst 972932 # number of demand (read+write) accesses 1142system.cpu.l2cache.demand_accesses::cpu.data 1655846 # number of demand (read+write) accesses 1143system.cpu.l2cache.demand_accesses::total 2706489 # number of demand (read+write) accesses 1144system.cpu.l2cache.overall_accesses::cpu.dtb.walker 65614 # number of overall (read+write) accesses 1145system.cpu.l2cache.overall_accesses::cpu.itb.walker 12097 # number of overall (read+write) accesses 1146system.cpu.l2cache.overall_accesses::cpu.inst 972932 # number of overall (read+write) accesses 1147system.cpu.l2cache.overall_accesses::cpu.data 1655846 # number of overall (read+write) accesses 1148system.cpu.l2cache.overall_accesses::total 2706489 # number of overall (read+write) accesses 1149system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.847651 # miss rate for UpgradeReq accesses 1150system.cpu.l2cache.UpgradeReq_miss_rate::total 0.847651 # miss rate for UpgradeReq accesses 1151system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463964 # miss rate for ReadExReq accesses 1152system.cpu.l2cache.ReadExReq_miss_rate::total 0.463964 # miss rate for ReadExReq accesses 1153system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016683 # miss rate for ReadCleanReq accesses 1154system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016683 # miss rate for ReadCleanReq accesses 1155system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000930 # miss rate for ReadSharedReq accesses 1156system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000496 # miss rate for ReadSharedReq accesses 1157system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026101 # miss rate for ReadSharedReq accesses 1158system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024744 # miss rate for ReadSharedReq accesses 1159system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000930 # miss rate for demand accesses 1160system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000496 # miss rate for demand accesses 1161system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016683 # miss rate for demand accesses 1162system.cpu.l2cache.demand_miss_rate::cpu.data 0.102182 # miss rate for demand accesses 1163system.cpu.l2cache.demand_miss_rate::total 0.068537 # miss rate for demand accesses 1164system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000930 # miss rate for overall accesses 1165system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000496 # miss rate for overall accesses 1166system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016683 # miss rate for overall accesses 1167system.cpu.l2cache.overall_miss_rate::cpu.data 0.102182 # miss rate for overall accesses 1168system.cpu.l2cache.overall_miss_rate::total 0.068537 # miss rate for overall accesses 1169system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13001.399776 # average UpgradeReq miss latency 1170system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13001.399776 # average UpgradeReq miss latency 1171system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76967.446512 # average ReadExReq miss latency 1172system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76967.446512 # average ReadExReq miss latency 1173system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83064.691023 # average ReadCleanReq miss latency 1174system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83064.691023 # average ReadCleanReq miss latency 1175system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 95557.377049 # average ReadSharedReq miss latency 1176system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 85500 # average ReadSharedReq miss latency 1177system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85691.660366 # average ReadSharedReq miss latency 1178system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85708.449799 # average ReadSharedReq miss latency 1179system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 95557.377049 # average overall miss latency 1180system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 85500 # average overall miss latency 1181system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83064.691023 # average overall miss latency 1182system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78808.690461 # average overall miss latency 1183system.cpu.l2cache.demand_avg_miss_latency::total 79186.819052 # average overall miss latency 1184system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 95557.377049 # average overall miss latency 1185system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 85500 # average overall miss latency 1186system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83064.691023 # average overall miss latency 1187system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78808.690461 # average overall miss latency 1188system.cpu.l2cache.overall_avg_miss_latency::total 79186.819052 # average overall miss latency | 1047system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048734 # Average percentage of cache occupancy 1048system.cpu.l2cache.tags.occ_percent::cpu.data 0.169002 # Average percentage of cache occupancy 1049system.cpu.l2cache.tags.occ_percent::total 0.988741 # Average percentage of cache occupancy 1050system.cpu.l2cache.tags.occ_task_id_blocks::1024 64279 # Occupied blocks per task id 1051system.cpu.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 1052system.cpu.l2cache.tags.age_task_id_blocks_1024::1 676 # Occupied blocks per task id 1053system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3413 # Occupied blocks per task id 1054system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5955 # Occupied blocks per task id 1055system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54192 # Occupied blocks per task id 1056system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980820 # Percentage of cache occupancy per task id 1057system.cpu.l2cache.tags.tag_accesses 43682151 # Number of tag accesses 1058system.cpu.l2cache.tags.data_accesses 43682151 # Number of data accesses 1059system.cpu.l2cache.Writeback_hits::writebacks 1585410 # number of Writeback hits 1060system.cpu.l2cache.Writeback_hits::total 1585410 # number of Writeback hits 1061system.cpu.l2cache.UpgradeReq_hits::cpu.data 346 # number of UpgradeReq hits 1062system.cpu.l2cache.UpgradeReq_hits::total 346 # number of UpgradeReq hits 1063system.cpu.l2cache.ReadExReq_hits::cpu.data 155314 # number of ReadExReq hits 1064system.cpu.l2cache.ReadExReq_hits::total 155314 # number of ReadExReq hits 1065system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 964131 # number of ReadCleanReq hits 1066system.cpu.l2cache.ReadCleanReq_hits::total 964131 # number of ReadCleanReq hits 1067system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 75809 # number of ReadSharedReq hits 1068system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 15497 # number of ReadSharedReq hits 1069system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332951 # number of ReadSharedReq hits 1070system.cpu.l2cache.ReadSharedReq_hits::total 1424257 # number of ReadSharedReq hits 1071system.cpu.l2cache.demand_hits::cpu.dtb.walker 75809 # number of demand (read+write) hits 1072system.cpu.l2cache.demand_hits::cpu.itb.walker 15497 # number of demand (read+write) hits 1073system.cpu.l2cache.demand_hits::cpu.inst 964131 # number of demand (read+write) hits 1074system.cpu.l2cache.demand_hits::cpu.data 1488265 # number of demand (read+write) hits 1075system.cpu.l2cache.demand_hits::total 2543702 # number of demand (read+write) hits 1076system.cpu.l2cache.overall_hits::cpu.dtb.walker 75809 # number of overall hits 1077system.cpu.l2cache.overall_hits::cpu.itb.walker 15497 # number of overall hits 1078system.cpu.l2cache.overall_hits::cpu.inst 964131 # number of overall hits 1079system.cpu.l2cache.overall_hits::cpu.data 1488265 # number of overall hits 1080system.cpu.l2cache.overall_hits::total 2543702 # number of overall hits 1081system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses 1082system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses 1083system.cpu.l2cache.ReadExReq_misses::cpu.data 132872 # number of ReadExReq misses 1084system.cpu.l2cache.ReadExReq_misses::total 132872 # number of ReadExReq misses 1085system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16267 # number of ReadCleanReq misses 1086system.cpu.l2cache.ReadCleanReq_misses::total 16267 # number of ReadCleanReq misses 1087system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 62 # number of ReadSharedReq misses 1088system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses 1089system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35699 # number of ReadSharedReq misses 1090system.cpu.l2cache.ReadSharedReq_misses::total 35766 # number of ReadSharedReq misses 1091system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses 1092system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 1093system.cpu.l2cache.demand_misses::cpu.inst 16267 # number of demand (read+write) misses 1094system.cpu.l2cache.demand_misses::cpu.data 168571 # number of demand (read+write) misses 1095system.cpu.l2cache.demand_misses::total 184905 # number of demand (read+write) misses 1096system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses 1097system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 1098system.cpu.l2cache.overall_misses::cpu.inst 16267 # number of overall misses 1099system.cpu.l2cache.overall_misses::cpu.data 168571 # number of overall misses 1100system.cpu.l2cache.overall_misses::total 184905 # number of overall misses 1101system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 58198000 # number of UpgradeReq miss cycles 1102system.cpu.l2cache.UpgradeReq_miss_latency::total 58198000 # number of UpgradeReq miss cycles 1103system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16980826000 # number of ReadExReq miss cycles 1104system.cpu.l2cache.ReadExReq_miss_latency::total 16980826000 # number of ReadExReq miss cycles 1105system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2184446000 # number of ReadCleanReq miss cycles 1106system.cpu.l2cache.ReadCleanReq_miss_latency::total 2184446000 # number of ReadCleanReq miss cycles 1107system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 9139000 # number of ReadSharedReq miss cycles 1108system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 679500 # number of ReadSharedReq miss cycles 1109system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4828291000 # number of ReadSharedReq miss cycles 1110system.cpu.l2cache.ReadSharedReq_miss_latency::total 4838109500 # number of ReadSharedReq miss cycles 1111system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9139000 # number of demand (read+write) miss cycles 1112system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 679500 # number of demand (read+write) miss cycles 1113system.cpu.l2cache.demand_miss_latency::cpu.inst 2184446000 # number of demand (read+write) miss cycles 1114system.cpu.l2cache.demand_miss_latency::cpu.data 21809117000 # number of demand (read+write) miss cycles 1115system.cpu.l2cache.demand_miss_latency::total 24003381500 # number of demand (read+write) miss cycles 1116system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9139000 # number of overall miss cycles 1117system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 679500 # number of overall miss cycles 1118system.cpu.l2cache.overall_miss_latency::cpu.inst 2184446000 # number of overall miss cycles 1119system.cpu.l2cache.overall_miss_latency::cpu.data 21809117000 # number of overall miss cycles 1120system.cpu.l2cache.overall_miss_latency::total 24003381500 # number of overall miss cycles 1121system.cpu.l2cache.Writeback_accesses::writebacks 1585410 # number of Writeback accesses(hits+misses) 1122system.cpu.l2cache.Writeback_accesses::total 1585410 # number of Writeback accesses(hits+misses) 1123system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1808 # number of UpgradeReq accesses(hits+misses) 1124system.cpu.l2cache.UpgradeReq_accesses::total 1808 # number of UpgradeReq accesses(hits+misses) 1125system.cpu.l2cache.ReadExReq_accesses::cpu.data 288186 # number of ReadExReq accesses(hits+misses) 1126system.cpu.l2cache.ReadExReq_accesses::total 288186 # number of ReadExReq accesses(hits+misses) 1127system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 980398 # number of ReadCleanReq accesses(hits+misses) 1128system.cpu.l2cache.ReadCleanReq_accesses::total 980398 # number of ReadCleanReq accesses(hits+misses) 1129system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 75871 # number of ReadSharedReq accesses(hits+misses) 1130system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 15502 # number of ReadSharedReq accesses(hits+misses) 1131system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368650 # number of ReadSharedReq accesses(hits+misses) 1132system.cpu.l2cache.ReadSharedReq_accesses::total 1460023 # number of ReadSharedReq accesses(hits+misses) 1133system.cpu.l2cache.demand_accesses::cpu.dtb.walker 75871 # number of demand (read+write) accesses 1134system.cpu.l2cache.demand_accesses::cpu.itb.walker 15502 # number of demand (read+write) accesses 1135system.cpu.l2cache.demand_accesses::cpu.inst 980398 # number of demand (read+write) accesses 1136system.cpu.l2cache.demand_accesses::cpu.data 1656836 # number of demand (read+write) accesses 1137system.cpu.l2cache.demand_accesses::total 2728607 # number of demand (read+write) accesses 1138system.cpu.l2cache.overall_accesses::cpu.dtb.walker 75871 # number of overall (read+write) accesses 1139system.cpu.l2cache.overall_accesses::cpu.itb.walker 15502 # number of overall (read+write) accesses 1140system.cpu.l2cache.overall_accesses::cpu.inst 980398 # number of overall (read+write) accesses 1141system.cpu.l2cache.overall_accesses::cpu.data 1656836 # number of overall (read+write) accesses 1142system.cpu.l2cache.overall_accesses::total 2728607 # number of overall (read+write) accesses 1143system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808628 # miss rate for UpgradeReq accesses 1144system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808628 # miss rate for UpgradeReq accesses 1145system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461063 # miss rate for ReadExReq accesses 1146system.cpu.l2cache.ReadExReq_miss_rate::total 0.461063 # miss rate for ReadExReq accesses 1147system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016592 # miss rate for ReadCleanReq accesses 1148system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016592 # miss rate for ReadCleanReq accesses 1149system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000817 # miss rate for ReadSharedReq accesses 1150system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000323 # miss rate for ReadSharedReq accesses 1151system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026083 # miss rate for ReadSharedReq accesses 1152system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024497 # miss rate for ReadSharedReq accesses 1153system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000817 # miss rate for demand accesses 1154system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000323 # miss rate for demand accesses 1155system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016592 # miss rate for demand accesses 1156system.cpu.l2cache.demand_miss_rate::cpu.data 0.101743 # miss rate for demand accesses 1157system.cpu.l2cache.demand_miss_rate::total 0.067765 # miss rate for demand accesses 1158system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000817 # miss rate for overall accesses 1159system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000323 # miss rate for overall accesses 1160system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016592 # miss rate for overall accesses 1161system.cpu.l2cache.overall_miss_rate::cpu.data 0.101743 # miss rate for overall accesses 1162system.cpu.l2cache.overall_miss_rate::total 0.067765 # miss rate for overall accesses 1163system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39807.113543 # average UpgradeReq miss latency 1164system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39807.113543 # average UpgradeReq miss latency 1165system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127798.377386 # average ReadExReq miss latency 1166system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127798.377386 # average ReadExReq miss latency 1167system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134286.961333 # average ReadCleanReq miss latency 1168system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134286.961333 # average ReadCleanReq miss latency 1169system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 147403.225806 # average ReadSharedReq miss latency 1170system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135900 # average ReadSharedReq miss latency 1171system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135250.035015 # average ReadSharedReq miss latency 1172system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135271.193312 # average ReadSharedReq miss latency 1173system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 147403.225806 # average overall miss latency 1174system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135900 # average overall miss latency 1175system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134286.961333 # average overall miss latency 1176system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129376.446720 # average overall miss latency 1177system.cpu.l2cache.demand_avg_miss_latency::total 129814.669695 # average overall miss latency 1178system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 147403.225806 # average overall miss latency 1179system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135900 # average overall miss latency 1180system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134286.961333 # average overall miss latency 1181system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129376.446720 # average overall miss latency 1182system.cpu.l2cache.overall_avg_miss_latency::total 129814.669695 # average overall miss latency |
| 1189system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1190system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1191system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1192system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1193system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1194system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1195system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1196system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1183system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1190system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1197system.cpu.l2cache.writebacks::writebacks 102797 # number of writebacks 1198system.cpu.l2cache.writebacks::total 102797 # number of writebacks 1199system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1200system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1201system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 3 # number of ReadSharedReq MSHR hits 1202system.cpu.l2cache.ReadSharedReq_mshr_hits::total 3 # number of ReadSharedReq MSHR hits 1203system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1204system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits 1205system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 1206system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1207system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits 1208system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits 1209system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 107 # number of CleanEvict MSHR misses 1210system.cpu.l2cache.CleanEvict_mshr_misses::total 107 # number of CleanEvict MSHR misses 1211system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1786 # number of UpgradeReq MSHR misses 1212system.cpu.l2cache.UpgradeReq_mshr_misses::total 1786 # number of UpgradeReq MSHR misses 1213system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133488 # number of ReadExReq MSHR misses 1214system.cpu.l2cache.ReadExReq_mshr_misses::total 133488 # number of ReadExReq MSHR misses 1215system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16230 # number of ReadCleanReq MSHR misses 1216system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16230 # number of ReadCleanReq MSHR misses 1217system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 61 # number of ReadSharedReq MSHR misses 1218system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 6 # number of ReadSharedReq MSHR misses 1219system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35706 # number of ReadSharedReq MSHR misses 1220system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35773 # number of ReadSharedReq MSHR misses 1221system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses 1222system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1223system.cpu.l2cache.demand_mshr_misses::cpu.inst 16230 # number of demand (read+write) MSHR misses 1224system.cpu.l2cache.demand_mshr_misses::cpu.data 169194 # number of demand (read+write) MSHR misses 1225system.cpu.l2cache.demand_mshr_misses::total 185491 # number of demand (read+write) MSHR misses 1226system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses 1227system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1228system.cpu.l2cache.overall_mshr_misses::cpu.inst 16230 # number of overall MSHR misses 1229system.cpu.l2cache.overall_mshr_misses::cpu.data 169194 # number of overall MSHR misses 1230system.cpu.l2cache.overall_mshr_misses::total 185491 # number of overall MSHR misses 1231system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable 1232system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable 1233system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13873 # number of WriteReq MSHR uncacheable 1234system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13873 # number of WriteReq MSHR uncacheable 1235system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616769 # number of overall MSHR uncacheable misses 1236system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616769 # number of overall MSHR uncacheable misses 1237system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37836000 # number of UpgradeReq MSHR miss cycles 1238system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37836000 # number of UpgradeReq MSHR miss cycles 1239system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8939350500 # number of ReadExReq MSHR miss cycles 1240system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8939350500 # number of ReadExReq MSHR miss cycles 1241system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1185827000 # number of ReadCleanReq MSHR miss cycles 1242system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1185827000 # number of ReadCleanReq MSHR miss cycles 1243system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 5219000 # number of ReadSharedReq MSHR miss cycles 1244system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 453000 # number of ReadSharedReq MSHR miss cycles 1245system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2703742500 # number of ReadSharedReq MSHR miss cycles 1246system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2709414500 # number of ReadSharedReq MSHR miss cycles 1247system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5219000 # number of demand (read+write) MSHR miss cycles 1248system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 453000 # number of demand (read+write) MSHR miss cycles 1249system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1185827000 # number of demand (read+write) MSHR miss cycles 1250system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11643093000 # number of demand (read+write) MSHR miss cycles 1251system.cpu.l2cache.demand_mshr_miss_latency::total 12834592000 # number of demand (read+write) MSHR miss cycles 1252system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5219000 # number of overall MSHR miss cycles 1253system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 453000 # number of overall MSHR miss cycles 1254system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1185827000 # number of overall MSHR miss cycles 1255system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11643093000 # number of overall MSHR miss cycles 1256system.cpu.l2cache.overall_mshr_miss_latency::total 12834592000 # number of overall MSHR miss cycles 1257system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257448500 # number of ReadReq MSHR uncacheable cycles 1258system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257448500 # number of ReadReq MSHR uncacheable cycles 1259system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2455427500 # number of WriteReq MSHR uncacheable cycles 1260system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2455427500 # number of WriteReq MSHR uncacheable cycles 1261system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92712876000 # number of overall MSHR uncacheable cycles 1262system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92712876000 # number of overall MSHR uncacheable cycles | 1191system.cpu.l2cache.writebacks::writebacks 102325 # number of writebacks 1192system.cpu.l2cache.writebacks::total 102325 # number of writebacks 1193system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1194system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1195system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 2 # number of ReadSharedReq MSHR hits 1196system.cpu.l2cache.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits 1197system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1198system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits 1199system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 1200system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1201system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits 1202system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 1203system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses 1204system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses 1205system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses 1206system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses 1207system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132872 # number of ReadExReq MSHR misses 1208system.cpu.l2cache.ReadExReq_mshr_misses::total 132872 # number of ReadExReq MSHR misses 1209system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16264 # number of ReadCleanReq MSHR misses 1210system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16264 # number of ReadCleanReq MSHR misses 1211system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 62 # number of ReadSharedReq MSHR misses 1212system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses 1213system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35697 # number of ReadSharedReq MSHR misses 1214system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35764 # number of ReadSharedReq MSHR misses 1215system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses 1216system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 1217system.cpu.l2cache.demand_mshr_misses::cpu.inst 16264 # number of demand (read+write) MSHR misses 1218system.cpu.l2cache.demand_mshr_misses::cpu.data 168569 # number of demand (read+write) MSHR misses 1219system.cpu.l2cache.demand_mshr_misses::total 184900 # number of demand (read+write) MSHR misses 1220system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses 1221system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 1222system.cpu.l2cache.overall_mshr_misses::cpu.inst 16264 # number of overall MSHR misses 1223system.cpu.l2cache.overall_mshr_misses::cpu.data 168569 # number of overall MSHR misses 1224system.cpu.l2cache.overall_mshr_misses::total 184900 # number of overall MSHR misses 1225system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602897 # number of ReadReq MSHR uncacheable 1226system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602897 # number of ReadReq MSHR uncacheable 1227system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13882 # number of WriteReq MSHR uncacheable 1228system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13882 # number of WriteReq MSHR uncacheable 1229system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616779 # number of overall MSHR uncacheable misses 1230system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616779 # number of overall MSHR uncacheable misses 1231system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 104470500 # number of UpgradeReq MSHR miss cycles 1232system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 104470500 # number of UpgradeReq MSHR miss cycles 1233system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15652106000 # number of ReadExReq MSHR miss cycles 1234system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15652106000 # number of ReadExReq MSHR miss cycles 1235system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2021465000 # number of ReadCleanReq MSHR miss cycles 1236system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2021465000 # number of ReadCleanReq MSHR miss cycles 1237system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8519000 # number of ReadSharedReq MSHR miss cycles 1238system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 629500 # number of ReadSharedReq MSHR miss cycles 1239system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4471847000 # number of ReadSharedReq MSHR miss cycles 1240system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4480995500 # number of ReadSharedReq MSHR miss cycles 1241system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8519000 # number of demand (read+write) MSHR miss cycles 1242system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 629500 # number of demand (read+write) MSHR miss cycles 1243system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2021465000 # number of demand (read+write) MSHR miss cycles 1244system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20123953000 # number of demand (read+write) MSHR miss cycles 1245system.cpu.l2cache.demand_mshr_miss_latency::total 22154566500 # number of demand (read+write) MSHR miss cycles 1246system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8519000 # number of overall MSHR miss cycles 1247system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 629500 # number of overall MSHR miss cycles 1248system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2021465000 # number of overall MSHR miss cycles 1249system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20123953000 # number of overall MSHR miss cycles 1250system.cpu.l2cache.overall_mshr_miss_latency::total 22154566500 # number of overall MSHR miss cycles 1251system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257667000 # number of ReadReq MSHR uncacheable cycles 1252system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257667000 # number of ReadReq MSHR uncacheable cycles 1253system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2456737500 # number of WriteReq MSHR uncacheable cycles 1254system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2456737500 # number of WriteReq MSHR uncacheable cycles 1255system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92714404500 # number of overall MSHR uncacheable cycles 1256system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92714404500 # number of overall MSHR uncacheable cycles |
| 1263system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1264system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 1257system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1258system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 1265system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.847651 # mshr miss rate for UpgradeReq accesses 1266system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.847651 # mshr miss rate for UpgradeReq accesses 1267system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463964 # mshr miss rate for ReadExReq accesses 1268system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463964 # mshr miss rate for ReadExReq accesses 1269system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for ReadCleanReq accesses 1270system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadCleanReq accesses 1271system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for ReadSharedReq accesses 1272system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadSharedReq accesses 1273system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026098 # mshr miss rate for ReadSharedReq accesses 1274system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024742 # mshr miss rate for ReadSharedReq accesses 1275system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for demand accesses 1276system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses 1277system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for demand accesses 1278system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for demand accesses 1279system.cpu.l2cache.demand_mshr_miss_rate::total 0.068536 # mshr miss rate for demand accesses 1280system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for overall accesses 1281system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses 1282system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for overall accesses 1283system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for overall accesses 1284system.cpu.l2cache.overall_mshr_miss_rate::total 0.068536 # mshr miss rate for overall accesses 1285system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21184.770437 # average UpgradeReq mshr miss latency 1286system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21184.770437 # average UpgradeReq mshr miss latency 1287system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66967.446512 # average ReadExReq mshr miss latency 1288system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66967.446512 # average ReadExReq mshr miss latency 1289system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73063.894023 # average ReadCleanReq mshr miss latency 1290system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73063.894023 # average ReadCleanReq mshr miss latency 1291system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average ReadSharedReq mshr miss latency 1292system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75500 # average ReadSharedReq mshr miss latency 1293system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75722.357587 # average ReadSharedReq mshr miss latency 1294system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75739.090935 # average ReadSharedReq mshr miss latency 1295system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average overall mshr miss latency 1296system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75500 # average overall mshr miss latency 1297system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency 1298system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency 1299system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency 1300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average overall mshr miss latency 1301system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75500 # average overall mshr miss latency 1302system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency 1303system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency 1304system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency 1305system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.497472 # average ReadReq mshr uncacheable latency 1306system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.497472 # average ReadReq mshr uncacheable latency 1307system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176993.260290 # average WriteReq mshr uncacheable latency 1308system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176993.260290 # average WriteReq mshr uncacheable latency 1309system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.259287 # average overall mshr uncacheable latency 1310system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.259287 # average overall mshr uncacheable latency | 1259system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808628 # mshr miss rate for UpgradeReq accesses 1260system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808628 # mshr miss rate for UpgradeReq accesses 1261system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461063 # mshr miss rate for ReadExReq accesses 1262system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461063 # mshr miss rate for ReadExReq accesses 1263system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for ReadCleanReq accesses 1264system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016589 # mshr miss rate for ReadCleanReq accesses 1265system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for ReadSharedReq accesses 1266system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for ReadSharedReq accesses 1267system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses 1268system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024496 # mshr miss rate for ReadSharedReq accesses 1269system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for demand accesses 1270system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for demand accesses 1271system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for demand accesses 1272system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for demand accesses 1273system.cpu.l2cache.demand_mshr_miss_rate::total 0.067764 # mshr miss rate for demand accesses 1274system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for overall accesses 1275system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for overall accesses 1276system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for overall accesses 1277system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for overall accesses 1278system.cpu.l2cache.overall_mshr_miss_rate::total 0.067764 # mshr miss rate for overall accesses 1279system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342 # average UpgradeReq mshr miss latency 1280system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342 # average UpgradeReq mshr miss latency 1281system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386 # average ReadExReq mshr miss latency 1282system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386 # average ReadExReq mshr miss latency 1283system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879 # average ReadCleanReq mshr miss latency 1284system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879 # average ReadCleanReq mshr miss latency 1285system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average ReadSharedReq mshr miss latency 1286system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125900 # average ReadSharedReq mshr miss latency 1287system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816 # average ReadSharedReq mshr miss latency 1288system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496 # average ReadSharedReq mshr miss latency 1289system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency 1290system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency 1291system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency 1292system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency 1293system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency 1294system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency 1295system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency 1296system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency 1297system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency 1298system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency 1299system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577 # average ReadReq mshr uncacheable latency 1300system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577 # average ReadReq mshr uncacheable latency 1301system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548 # average WriteReq mshr uncacheable latency 1302system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548 # average WriteReq mshr uncacheable latency 1303system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302 # average overall mshr uncacheable latency 1304system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302 # average overall mshr uncacheable latency |
| 1311system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1305system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1312system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution 1313system.cpu.toL2Bus.trans_dist::ReadResp 3032324 # Transaction distribution 1314system.cpu.toL2Bus.trans_dist::WriteReq 13873 # Transaction distribution 1315system.cpu.toL2Bus.trans_dist::WriteResp 13873 # Transaction distribution 1316system.cpu.toL2Bus.trans_dist::Writeback 1727482 # Transaction distribution 1317system.cpu.toL2Bus.trans_dist::CleanEvict 1093519 # Transaction distribution 1318system.cpu.toL2Bus.trans_dist::UpgradeReq 2562 # Transaction distribution 1319system.cpu.toL2Bus.trans_dist::UpgradeResp 2562 # Transaction distribution 1320system.cpu.toL2Bus.trans_dist::ReadExReq 287721 # Transaction distribution 1321system.cpu.toL2Bus.trans_dist::ReadExResp 287721 # Transaction distribution 1322system.cpu.toL2Bus.trans_dist::ReadCleanReq 973367 # Transaction distribution 1323system.cpu.toL2Bus.trans_dist::ReadSharedReq 1456602 # Transaction distribution 1324system.cpu.toL2Bus.trans_dist::MessageReq 1641 # Transaction distribution | 1306system.cpu.toL2Bus.snoop_filter.tot_requests 5491514 # Total number of requests made to the snoop filter. 1307system.cpu.toL2Bus.snoop_filter.hit_single_requests 2726446 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1308system.cpu.toL2Bus.snoop_filter.hit_multi_requests 94920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1309system.cpu.toL2Bus.snoop_filter.tot_snoops 1211 # Total number of snoops made to the snoop filter. 1310system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1211 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1311system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1312system.cpu.toL2Bus.trans_dist::ReadReq 602897 # Transaction distribution 1313system.cpu.toL2Bus.trans_dist::ReadResp 3061240 # Transaction distribution 1314system.cpu.toL2Bus.trans_dist::WriteReq 13882 # Transaction distribution 1315system.cpu.toL2Bus.trans_dist::WriteResp 13882 # Transaction distribution 1316system.cpu.toL2Bus.trans_dist::Writeback 1734407 # Transaction distribution 1317system.cpu.toL2Bus.trans_dist::CleanEvict 1095490 # Transaction distribution 1318system.cpu.toL2Bus.trans_dist::UpgradeReq 2269 # Transaction distribution 1319system.cpu.toL2Bus.trans_dist::UpgradeResp 2269 # Transaction distribution 1320system.cpu.toL2Bus.trans_dist::ReadExReq 288196 # Transaction distribution 1321system.cpu.toL2Bus.trans_dist::ReadExResp 288196 # Transaction distribution 1322system.cpu.toL2Bus.trans_dist::ReadCleanReq 980539 # Transaction distribution 1323system.cpu.toL2Bus.trans_dist::ReadSharedReq 1478351 # Transaction distribution 1324system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution |
| 1325system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution 1326system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution | 1325system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution 1326system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution |
| 1327system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917513 # Packet count per connected master and slave (bytes) 1328system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6205490 # Packet count per connected master and slave (bytes) 1329system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31703 # Packet count per connected master and slave (bytes) 1330system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168231 # Packet count per connected master and slave (bytes) 1331system.cpu.toL2Bus.pkt_count::total 9322937 # Packet count per connected master and slave (bytes) 1332system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62267648 # Cumulative packet size per connected master and slave (bytes) 1333system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207474745 # Cumulative packet size per connected master and slave (bytes) 1334system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 922624 # Cumulative packet size per connected master and slave (bytes) 1335system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5343616 # Cumulative packet size per connected master and slave (bytes) 1336system.cpu.toL2Bus.pkt_size::total 276008633 # Cumulative packet size per connected master and slave (bytes) 1337system.cpu.toL2Bus.snoops 220316 # Total snoops (count) 1338system.cpu.toL2Bus.snoop_fanout::samples 6258702 # Request fanout histogram 1339system.cpu.toL2Bus.snoop_fanout::mean 3.033424 # Request fanout histogram 1340system.cpu.toL2Bus.snoop_fanout::stdev 0.179742 # Request fanout histogram | 1327system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2939753 # Packet count per connected master and slave (bytes) 1328system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6208049 # Packet count per connected master and slave (bytes) 1329system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 41124 # Packet count per connected master and slave (bytes) 1330system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 194511 # Packet count per connected master and slave (bytes) 1331system.cpu.toL2Bus.pkt_count::total 9383437 # Packet count per connected master and slave (bytes) 1332system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745472 # Cumulative packet size per connected master and slave (bytes) 1333system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207643157 # Cumulative packet size per connected master and slave (bytes) 1334system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1196736 # Cumulative packet size per connected master and slave (bytes) 1335system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 6311744 # Cumulative packet size per connected master and slave (bytes) 1336system.cpu.toL2Bus.pkt_size::total 277897109 # Cumulative packet size per connected master and slave (bytes) 1337system.cpu.toL2Bus.snoops 226924 # Total snoops (count) 1338system.cpu.toL2Bus.snoop_fanout::samples 6316816 # Request fanout histogram 1339system.cpu.toL2Bus.snoop_fanout::mean 0.030269 # Request fanout histogram 1340system.cpu.toL2Bus.snoop_fanout::stdev 0.203509 # Request fanout histogram |
| 1341system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1341system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1342system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1343system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1344system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1345system.cpu.toL2Bus.snoop_fanout::3 6049509 96.66% 96.66% # Request fanout histogram 1346system.cpu.toL2Bus.snoop_fanout::4 209193 3.34% 100.00% # Request fanout histogram | 1342system.cpu.toL2Bus.snoop_fanout::0 6163711 97.58% 97.58% # Request fanout histogram 1343system.cpu.toL2Bus.snoop_fanout::1 115005 1.82% 99.40% # Request fanout histogram 1344system.cpu.toL2Bus.snoop_fanout::2 38100 0.60% 100.00% # Request fanout histogram 1345system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram 1346system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 1347system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1347system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1348system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1349system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1350system.cpu.toL2Bus.snoop_fanout::total 6258702 # Request fanout histogram 1351system.cpu.toL2Bus.reqLayer0.occupancy 4609709481 # Layer occupancy (ticks) | 1348system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1349system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1350system.cpu.toL2Bus.snoop_fanout::total 6316816 # Request fanout histogram 1351system.cpu.toL2Bus.reqLayer0.occupancy 4646513967 # Layer occupancy (ticks) |
| 1352system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1352system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1353system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) | 1353system.cpu.toL2Bus.snoopLayer0.occupancy 659789 # Layer occupancy (ticks) |
| 1354system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1354system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1355system.cpu.toL2Bus.respLayer0.occupancy 1461362367 # Layer occupancy (ticks) | 1355system.cpu.toL2Bus.respLayer0.occupancy 1472350908 # Layer occupancy (ticks) |
| 1356system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1356system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1357system.cpu.toL2Bus.respLayer1.occupancy 3096027096 # Layer occupancy (ticks) | 1357system.cpu.toL2Bus.respLayer1.occupancy 3097364534 # Layer occupancy (ticks) |
| 1358system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1358system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1359system.cpu.toL2Bus.respLayer2.occupancy 22269484 # Layer occupancy (ticks) | 1359system.cpu.toL2Bus.respLayer2.occupancy 30265969 # Layer occupancy (ticks) |
| 1360system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1360system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1361system.cpu.toL2Bus.respLayer3.occupancy 108175907 # Layer occupancy (ticks) | 1361system.cpu.toL2Bus.respLayer3.occupancy 132091893 # Layer occupancy (ticks) |
| 1362system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1362system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1363system.iobus.trans_dist::ReadReq 222102 # Transaction distribution 1364system.iobus.trans_dist::ReadResp 222102 # Transaction distribution 1365system.iobus.trans_dist::WriteReq 57708 # Transaction distribution 1366system.iobus.trans_dist::WriteResp 57708 # Transaction distribution 1367system.iobus.trans_dist::MessageReq 1641 # Transaction distribution 1368system.iobus.trans_dist::MessageResp 1641 # Transaction distribution | 1363system.iobus.trans_dist::ReadReq 222097 # Transaction distribution 1364system.iobus.trans_dist::ReadResp 222097 # Transaction distribution 1365system.iobus.trans_dist::WriteReq 57711 # Transaction distribution 1366system.iobus.trans_dist::WriteResp 57711 # Transaction distribution 1367system.iobus.trans_dist::MessageReq 1645 # Transaction distribution 1368system.iobus.trans_dist::MessageResp 1645 # Transaction distribution |
| 1369system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1370system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1371system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) 1372system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1373system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) | 1369system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1370system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1371system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) 1372system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1373system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) |
| 1374system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) | 1374system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) |
| 1375system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1376system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1377system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes) 1378system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1379system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1380system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1381system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1382system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1383system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1384system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1385system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1386system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) | 1375system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1376system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1377system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes) 1378system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1379system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1380system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1381system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1382system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1383system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1384system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1385system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1386system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) |
| 1387system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes) 1388system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes) 1389system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes) 1390system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes) 1391system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes) 1392system.iobus.pkt_count::total 562902 # Packet count per connected master and slave (bytes) | 1387system.iobus.pkt_count_system.bridge.master::total 464358 # Packet count per connected master and slave (bytes) 1388system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) 1389system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) 1390system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) 1391system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) 1392system.iobus.pkt_count::total 562906 # Packet count per connected master and slave (bytes) |
| 1393system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1394system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1395system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) 1396system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1397system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) | 1393system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1394system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1395system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) 1396system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1397system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) |
| 1398system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) | 1398system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) |
| 1399system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1400system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1401system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes) 1402system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1403system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1404system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1405system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1406system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1407system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1408system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1409system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1410system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) | 1399system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1400system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1401system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes) 1402system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1403system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1404system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1405system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1406system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1407system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1408system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1409system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1410system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) |
| 1411system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes) 1412system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes) 1413system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes) 1414system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes) 1415system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes) 1416system.iobus.pkt_size::total 3272880 # Cumulative packet size per connected master and slave (bytes) 1417system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks) | 1411system.iobus.pkt_size_system.bridge.master::total 238456 # Cumulative packet size per connected master and slave (bytes) 1412system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) 1413system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) 1414system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) 1415system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) 1416system.iobus.pkt_size::total 3272852 # Cumulative packet size per connected master and slave (bytes) 1417system.iobus.reqLayer0.occupancy 3921096 # Layer occupancy (ticks) |
| 1418system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1419system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1420system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1421system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1422system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1423system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) 1424system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1425system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1426system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1427system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1428system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1418system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1419system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1420system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1421system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1422system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1423system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) 1424system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1425system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1426system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1427system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1428system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1429system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) | 1429system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) |
| 1430system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1431system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1432system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1433system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1434system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1435system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks) 1436system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1437system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) --- 7 unchanged lines hidden (view full) --- 1445system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1446system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1447system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1448system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1449system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1450system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1451system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1452system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 1430system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1431system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1432system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1433system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1434system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1435system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks) 1436system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1437system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) --- 7 unchanged lines hidden (view full) --- 1445system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1446system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1447system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1448system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1449system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1450system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1451system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1452system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 1453system.iobus.reqLayer19.occupancy 242679087 # Layer occupancy (ticks) | 1453system.iobus.reqLayer19.occupancy 241306768 # Layer occupancy (ticks) |
| 1454system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1455system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1456system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) | 1454system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1455system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1456system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) |
| 1457system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks) | 1457system.iobus.respLayer0.occupancy 453367000 # Layer occupancy (ticks) |
| 1458system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1458system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1459system.iobus.respLayer1.occupancy 50182000 # Layer occupancy (ticks) | 1459system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks) |
| 1460system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1460system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1461system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks) | 1461system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) |
| 1462system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) | 1462system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1463system.iocache.tags.replacements 47580 # number of replacements 1464system.iocache.tags.tagsinuse 0.091366 # Cycle average of tags in use | 1463system.iocache.tags.replacements 47574 # number of replacements 1464system.iocache.tags.tagsinuse 0.116041 # Cycle average of tags in use |
| 1465system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1465system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1466system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks. | 1466system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. |
| 1467system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1467system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1468system.iocache.tags.warmup_cycle 4993241946000 # Cycle when the warmup percentage was hit. 1469system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091366 # Average occupied blocks per requestor 1470system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005710 # Average percentage of cache occupancy 1471system.iocache.tags.occ_percent::total 0.005710 # Average percentage of cache occupancy | 1468system.iocache.tags.warmup_cycle 4999338704000 # Cycle when the warmup percentage was hit. 1469system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116041 # Average occupied blocks per requestor 1470system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007253 # Average percentage of cache occupancy 1471system.iocache.tags.occ_percent::total 0.007253 # Average percentage of cache occupancy |
| 1472system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1473system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1474system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1472system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1473system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1474system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1475system.iocache.tags.tag_accesses 428715 # Number of tag accesses 1476system.iocache.tags.data_accesses 428715 # Number of data accesses 1477system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses 1478system.iocache.ReadReq_misses::total 915 # number of ReadReq misses | 1475system.iocache.tags.tag_accesses 428661 # Number of tag accesses 1476system.iocache.tags.data_accesses 428661 # Number of data accesses 1477system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses 1478system.iocache.ReadReq_misses::total 909 # number of ReadReq misses |
| 1479system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1480system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses | 1479system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1480system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses |
| 1481system.iocache.demand_misses::pc.south_bridge.ide 915 # number of demand (read+write) misses 1482system.iocache.demand_misses::total 915 # number of demand (read+write) misses 1483system.iocache.overall_misses::pc.south_bridge.ide 915 # number of overall misses 1484system.iocache.overall_misses::total 915 # number of overall misses 1485system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143595677 # number of ReadReq miss cycles 1486system.iocache.ReadReq_miss_latency::total 143595677 # number of ReadReq miss cycles 1487system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513463410 # number of WriteLineReq miss cycles 1488system.iocache.WriteLineReq_miss_latency::total 5513463410 # number of WriteLineReq miss cycles 1489system.iocache.demand_miss_latency::pc.south_bridge.ide 143595677 # number of demand (read+write) miss cycles 1490system.iocache.demand_miss_latency::total 143595677 # number of demand (read+write) miss cycles 1491system.iocache.overall_miss_latency::pc.south_bridge.ide 143595677 # number of overall miss cycles 1492system.iocache.overall_miss_latency::total 143595677 # number of overall miss cycles 1493system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) 1494system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) | 1481system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses 1482system.iocache.demand_misses::total 909 # number of demand (read+write) misses 1483system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses 1484system.iocache.overall_misses::total 909 # number of overall misses 1485system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144457672 # number of ReadReq miss cycles 1486system.iocache.ReadReq_miss_latency::total 144457672 # number of ReadReq miss cycles 1487system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6056832096 # number of WriteLineReq miss cycles 1488system.iocache.WriteLineReq_miss_latency::total 6056832096 # number of WriteLineReq miss cycles 1489system.iocache.demand_miss_latency::pc.south_bridge.ide 144457672 # number of demand (read+write) miss cycles 1490system.iocache.demand_miss_latency::total 144457672 # number of demand (read+write) miss cycles 1491system.iocache.overall_miss_latency::pc.south_bridge.ide 144457672 # number of overall miss cycles 1492system.iocache.overall_miss_latency::total 144457672 # number of overall miss cycles 1493system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) 1494system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) |
| 1495system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1496system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) | 1495system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1496system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) |
| 1497system.iocache.demand_accesses::pc.south_bridge.ide 915 # number of demand (read+write) accesses 1498system.iocache.demand_accesses::total 915 # number of demand (read+write) accesses 1499system.iocache.overall_accesses::pc.south_bridge.ide 915 # number of overall (read+write) accesses 1500system.iocache.overall_accesses::total 915 # number of overall (read+write) accesses | 1497system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses 1498system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses 1499system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses 1500system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses |
| 1501system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1502system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1503system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1504system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1505system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1506system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1507system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1508system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1501system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1502system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1503system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1504system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1505system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1506system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1507system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1508system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1509system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average ReadReq miss latency 1510system.iocache.ReadReq_avg_miss_latency::total 156935.166120 # average ReadReq miss latency 1511system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.775043 # average WriteLineReq miss latency 1512system.iocache.WriteLineReq_avg_miss_latency::total 118010.775043 # average WriteLineReq miss latency 1513system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency 1514system.iocache.demand_avg_miss_latency::total 156935.166120 # average overall miss latency 1515system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency 1516system.iocache.overall_avg_miss_latency::total 156935.166120 # average overall miss latency 1517system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked | 1509system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average ReadReq miss latency 1510system.iocache.ReadReq_avg_miss_latency::total 158919.331133 # average ReadReq miss latency 1511system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945 # average WriteLineReq miss latency 1512system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945 # average WriteLineReq miss latency 1513system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency 1514system.iocache.demand_avg_miss_latency::total 158919.331133 # average overall miss latency 1515system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency 1516system.iocache.overall_avg_miss_latency::total 158919.331133 # average overall miss latency 1517system.iocache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked |
| 1518system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1518system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1519system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked | 1519system.iocache.blocked::no_mshrs 52 # number of cycles access was blocked |
| 1520system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1520system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1521system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked | 1521system.iocache.avg_blocked_cycles::no_mshrs 11.615385 # average number of cycles each access was blocked |
| 1522system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1523system.iocache.fast_writes 0 # number of fast writes performed 1524system.iocache.cache_copies 0 # number of cache copies performed 1525system.iocache.writebacks::writebacks 46667 # number of writebacks 1526system.iocache.writebacks::total 46667 # number of writebacks | 1522system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1523system.iocache.fast_writes 0 # number of fast writes performed 1524system.iocache.cache_copies 0 # number of cache copies performed 1525system.iocache.writebacks::writebacks 46667 # number of writebacks 1526system.iocache.writebacks::total 46667 # number of writebacks |
| 1527system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses 1528system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses | 1527system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses 1528system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses |
| 1529system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1530system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses | 1529system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1530system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses |
| 1531system.iocache.demand_mshr_misses::pc.south_bridge.ide 915 # number of demand (read+write) MSHR misses 1532system.iocache.demand_mshr_misses::total 915 # number of demand (read+write) MSHR misses 1533system.iocache.overall_mshr_misses::pc.south_bridge.ide 915 # number of overall MSHR misses 1534system.iocache.overall_mshr_misses::total 915 # number of overall MSHR misses 1535system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of ReadReq MSHR miss cycles 1536system.iocache.ReadReq_mshr_miss_latency::total 97845677 # number of ReadReq MSHR miss cycles 1537system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177463410 # number of WriteLineReq MSHR miss cycles 1538system.iocache.WriteLineReq_mshr_miss_latency::total 3177463410 # number of WriteLineReq MSHR miss cycles 1539system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of demand (read+write) MSHR miss cycles 1540system.iocache.demand_mshr_miss_latency::total 97845677 # number of demand (read+write) MSHR miss cycles 1541system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of overall MSHR miss cycles 1542system.iocache.overall_mshr_miss_latency::total 97845677 # number of overall MSHR miss cycles | 1531system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses 1532system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses 1533system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses 1534system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses 1535system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of ReadReq MSHR miss cycles 1536system.iocache.ReadReq_mshr_miss_latency::total 99007672 # number of ReadReq MSHR miss cycles 1537system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3720832096 # number of WriteLineReq MSHR miss cycles 1538system.iocache.WriteLineReq_mshr_miss_latency::total 3720832096 # number of WriteLineReq MSHR miss cycles 1539system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of demand (read+write) MSHR miss cycles 1540system.iocache.demand_mshr_miss_latency::total 99007672 # number of demand (read+write) MSHR miss cycles 1541system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of overall MSHR miss cycles 1542system.iocache.overall_mshr_miss_latency::total 99007672 # number of overall MSHR miss cycles |
| 1543system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1544system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1545system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1546system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1547system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1548system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1549system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1550system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1543system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1544system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1545system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1546system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1547system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1548system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1549system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1550system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1551system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average ReadReq mshr miss latency 1552system.iocache.ReadReq_avg_mshr_miss_latency::total 106935.166120 # average ReadReq mshr miss latency 1553system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.775043 # average WriteLineReq mshr miss latency 1554system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.775043 # average WriteLineReq mshr miss latency 1555system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency 1556system.iocache.demand_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency 1557system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency 1558system.iocache.overall_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency | 1551system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average ReadReq mshr miss latency 1552system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133 # average ReadReq mshr miss latency 1553system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945 # average WriteLineReq mshr miss latency 1554system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945 # average WriteLineReq mshr miss latency 1555system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency 1556system.iocache.demand_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency 1557system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency 1558system.iocache.overall_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency |
| 1559system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1559system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1560system.membus.trans_dist::ReadReq 602896 # Transaction distribution 1561system.membus.trans_dist::ReadResp 655806 # Transaction distribution 1562system.membus.trans_dist::WriteReq 13873 # Transaction distribution 1563system.membus.trans_dist::WriteResp 13873 # Transaction distribution 1564system.membus.trans_dist::Writeback 149464 # Transaction distribution 1565system.membus.trans_dist::CleanEvict 9883 # Transaction distribution 1566system.membus.trans_dist::UpgradeReq 2535 # Transaction distribution 1567system.membus.trans_dist::UpgradeResp 2080 # Transaction distribution 1568system.membus.trans_dist::ReadExReq 133195 # Transaction distribution 1569system.membus.trans_dist::ReadExResp 133194 # Transaction distribution 1570system.membus.trans_dist::ReadSharedReq 52918 # Transaction distribution 1571system.membus.trans_dist::MessageReq 1641 # Transaction distribution 1572system.membus.trans_dist::MessageResp 1641 # Transaction distribution | 1560system.membus.trans_dist::ReadReq 602897 # Transaction distribution 1561system.membus.trans_dist::ReadResp 655826 # Transaction distribution 1562system.membus.trans_dist::WriteReq 13882 # Transaction distribution 1563system.membus.trans_dist::WriteResp 13882 # Transaction distribution 1564system.membus.trans_dist::Writeback 148992 # Transaction distribution 1565system.membus.trans_dist::CleanEvict 9700 # Transaction distribution 1566system.membus.trans_dist::UpgradeReq 2190 # Transaction distribution 1567system.membus.trans_dist::UpgradeResp 1729 # Transaction distribution 1568system.membus.trans_dist::ReadExReq 132608 # Transaction distribution 1569system.membus.trans_dist::ReadExResp 132605 # Transaction distribution 1570system.membus.trans_dist::ReadSharedReq 52937 # Transaction distribution 1571system.membus.trans_dist::MessageReq 1645 # Transaction distribution 1572system.membus.trans_dist::MessageResp 1645 # Transaction distribution |
| 1573system.membus.trans_dist::BadAddressError 8 # Transaction distribution 1574system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 1575system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution | 1573system.membus.trans_dist::BadAddressError 8 # Transaction distribution 1574system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 1575system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution |
| 1576system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes) 1577system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes) 1578system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes) 1579system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769188 # Packet count per connected master and slave (bytes) 1580system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 486631 # Packet count per connected master and slave (bytes) | 1576system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) 1577system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) 1578system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464358 # Packet count per connected master and slave (bytes) 1579system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769200 # Packet count per connected master and slave (bytes) 1580system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484156 # Packet count per connected master and slave (bytes) |
| 1581system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) | 1581system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) |
| 1582system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720185 # Packet count per connected master and slave (bytes) 1583system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141820 # Packet count per connected master and slave (bytes) 1584system.membus.pkt_count_system.iocache.mem_side::total 141820 # Packet count per connected master and slave (bytes) 1585system.membus.pkt_count::total 1865287 # Packet count per connected master and slave (bytes) 1586system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes) 1587system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes) 1588system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes) 1589system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538373 # Cumulative packet size per connected master and slave (bytes) 1590system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18388288 # Cumulative packet size per connected master and slave (bytes) 1591system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20165113 # Cumulative packet size per connected master and slave (bytes) | 1582system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1717730 # Packet count per connected master and slave (bytes) 1583system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141814 # Packet count per connected master and slave (bytes) 1584system.membus.pkt_count_system.iocache.mem_side::total 141814 # Packet count per connected master and slave (bytes) 1585system.membus.pkt_count::total 1862834 # Packet count per connected master and slave (bytes) 1586system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) 1587system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) 1588system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238456 # Cumulative packet size per connected master and slave (bytes) 1589system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538397 # Cumulative packet size per connected master and slave (bytes) 1590system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322112 # Cumulative packet size per connected master and slave (bytes) 1591system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20098965 # Cumulative packet size per connected master and slave (bytes) |
| 1592system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) 1593system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) | 1592system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) 1593system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) |
| 1594system.membus.pkt_size::total 23186717 # Cumulative packet size per connected master and slave (bytes) | 1594system.membus.pkt_size::total 23120585 # Cumulative packet size per connected master and slave (bytes) |
| 1595system.membus.snoops 1616 # Total snoops (count) | 1595system.membus.snoops 1616 # Total snoops (count) |
| 1596system.membus.snoop_fanout::samples 1013692 # Request fanout histogram 1597system.membus.snoop_fanout::mean 1.001619 # Request fanout histogram 1598system.membus.snoop_fanout::stdev 0.040202 # Request fanout histogram | 1596system.membus.snoop_fanout::samples 1012128 # Request fanout histogram 1597system.membus.snoop_fanout::mean 1.001625 # Request fanout histogram 1598system.membus.snoop_fanout::stdev 0.040282 # Request fanout histogram |
| 1599system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1600system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1599system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1600system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1601system.membus.snoop_fanout::1 1012051 99.84% 99.84% # Request fanout histogram 1602system.membus.snoop_fanout::2 1641 0.16% 100.00% # Request fanout histogram | 1601system.membus.snoop_fanout::1 1010483 99.84% 99.84% # Request fanout histogram 1602system.membus.snoop_fanout::2 1645 0.16% 100.00% # Request fanout histogram |
| 1603system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1604system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1605system.membus.snoop_fanout::max_value 2 # Request fanout histogram | 1603system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1604system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1605system.membus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1606system.membus.snoop_fanout::total 1013692 # Request fanout histogram 1607system.membus.reqLayer0.occupancy 354973500 # Layer occupancy (ticks) | 1606system.membus.snoop_fanout::total 1012128 # Request fanout histogram 1607system.membus.reqLayer0.occupancy 355014500 # Layer occupancy (ticks) |
| 1608system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1608system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1609system.membus.reqLayer1.occupancy 388325000 # Layer occupancy (ticks) | 1609system.membus.reqLayer1.occupancy 388301500 # Layer occupancy (ticks) |
| 1610system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1610system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1611system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks) | 1611system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) |
| 1612system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1612system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1613system.membus.reqLayer3.occupancy 1016908044 # Layer occupancy (ticks) | 1613system.membus.reqLayer3.occupancy 1012808227 # Layer occupancy (ticks) |
| 1614system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1614system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 1615system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) | 1615system.membus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) |
| 1616system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 1616system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 1617system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks) | 1617system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) |
| 1618system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 1618system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1619system.membus.respLayer2.occupancy 2204699193 # Layer occupancy (ticks) | 1619system.membus.respLayer2.occupancy 2201176288 # Layer occupancy (ticks) |
| 1620system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1620system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1621system.membus.respLayer4.occupancy 86072153 # Layer occupancy (ticks) | 1621system.membus.respLayer4.occupancy 86060868 # Layer occupancy (ticks) |
| 1622system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1623system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1624system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1625system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). 1626system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1627system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1628system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1629system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1630system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1631system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1632system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1633system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1634system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1635system.cpu.kern.inst.arm 0 # number of arm instructions executed 1636system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1637 1638---------- End Simulation Statistics ---------- | 1622system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1623system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1624system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1625system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). 1626system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1627system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1628system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1629system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1630system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1631system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1632system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1633system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1634system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1635system.cpu.kern.inst.arm 0 # number of arm instructions executed 1636system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1637 1638---------- End Simulation Statistics ---------- |