| stats.txt (10811:e6b20e6b5cf9) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.122213 # Number of seconds simulated 4sim_ticks 5122212682000 # Number of ticks simulated 5final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.122213 # Number of seconds simulated 4sim_ticks 5122212682000 # Number of ticks simulated 5final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 132606 # Simulator instruction rate (inst/s) 8host_op_rate 262116 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1665061517 # Simulator tick rate (ticks/s) 10host_mem_usage 804736 # Number of bytes of host memory used 11host_seconds 3076.29 # Real time elapsed on the host | 7host_inst_rate 178126 # Simulator instruction rate (inst/s) 8host_op_rate 352092 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2236626113 # Simulator tick rate (ticks/s) 10host_mem_usage 810964 # Number of bytes of host memory used 11host_seconds 2290.15 # Real time elapsed on the host |
| 12sim_insts 407934867 # Number of instructions simulated 13sim_ops 806343968 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10801152 # Number of bytes read from this memory --- 692 unchanged lines hidden (view full) --- 712system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290839 # number of WriteReq MSHR misses 713system.cpu.dcache.WriteReq_mshr_misses::total 290839 # number of WriteReq MSHR misses 714system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402958 # number of SoftPFReq MSHR misses 715system.cpu.dcache.SoftPFReq_mshr_misses::total 402958 # number of SoftPFReq MSHR misses 716system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 # number of demand (read+write) MSHR misses 717system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses 718system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses 719system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses | 12sim_insts 407934867 # Number of instructions simulated 13sim_ops 806343968 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10801152 # Number of bytes read from this memory --- 692 unchanged lines hidden (view full) --- 712system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290839 # number of WriteReq MSHR misses 713system.cpu.dcache.WriteReq_mshr_misses::total 290839 # number of WriteReq MSHR misses 714system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402958 # number of SoftPFReq MSHR misses 715system.cpu.dcache.SoftPFReq_mshr_misses::total 402958 # number of SoftPFReq MSHR misses 716system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 # number of demand (read+write) MSHR misses 717system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses 718system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses 719system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses |
| 720system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable 721system.cpu.dcache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable 722system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable 723system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable 724system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses 725system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses |
|
| 720system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles 721system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles 722system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles 723system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles 724system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles 725system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles 726system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles 727system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles --- 20 unchanged lines hidden (view full) --- 748system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency 749system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency 750system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency 751system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency 752system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency 753system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency 754system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency 755system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency | 726system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles 727system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles 728system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles 729system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles 730system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles 731system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles 732system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles 733system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles --- 20 unchanged lines hidden (view full) --- 754system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency 755system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency 756system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency 757system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency 758system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency 759system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency 760system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency 761system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency |
| 756system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 757system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 758system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 759system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 760system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 761system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 762system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604 # average ReadReq mshr uncacheable latency 763system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency 764system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483 # average WriteReq mshr uncacheable latency 765system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency 766system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590 # average overall mshr uncacheable latency 767system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency |
| 762system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 763system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements 764system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use 765system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks. 766system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks. 767system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks. 768system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit. 769system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor --- 436 unchanged lines hidden (view full) --- 1206system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses 1207system.cpu.l2cache.demand_mshr_misses::cpu.data 169729 # number of demand (read+write) MSHR misses 1208system.cpu.l2cache.demand_mshr_misses::total 186163 # number of demand (read+write) MSHR misses 1209system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses 1210system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1211system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses 1212system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses 1213system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses | 768system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 769system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements 770system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use 771system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks. 772system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks. 773system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks. 774system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit. 775system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor --- 436 unchanged lines hidden (view full) --- 1212system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses 1213system.cpu.l2cache.demand_mshr_misses::cpu.data 169729 # number of demand (read+write) MSHR misses 1214system.cpu.l2cache.demand_mshr_misses::total 186163 # number of demand (read+write) MSHR misses 1215system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses 1216system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1217system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses 1218system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses 1219system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses |
| 1220system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable 1221system.cpu.l2cache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable 1222system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable 1223system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable 1224system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses 1225system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses |
|
| 1214system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles 1215system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles 1216system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles 1217system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2626180250 # number of ReadReq MSHR miss cycles 1218system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3793540968 # number of ReadReq MSHR miss cycles 1219system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles 1220system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles 1221system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8698623734 # number of ReadExReq MSHR miss cycles --- 47 unchanged lines hidden (view full) --- 1269system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency 1270system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency 1271system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency 1272system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency 1273system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency 1274system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency 1275system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency 1276system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency | 1226system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles 1227system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles 1228system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles 1229system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2626180250 # number of ReadReq MSHR miss cycles 1230system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3793540968 # number of ReadReq MSHR miss cycles 1231system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles 1232system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles 1233system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8698623734 # number of ReadExReq MSHR miss cycles --- 47 unchanged lines hidden (view full) --- 1281system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency 1282system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency 1283system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency 1284system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency 1285system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency 1286system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency 1287system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency 1288system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency |
| 1277system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1278system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1279system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1280system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1281system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1282system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1289system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686 # average ReadReq mshr uncacheable latency 1290system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency 1291system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873 # average WriteReq mshr uncacheable latency 1292system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency 1293system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233 # average overall mshr uncacheable latency 1294system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency |
| 1283system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1284system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution 1285system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution 1286system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution 1287system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution 1288system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution 1289system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution 1290system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution 1291system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution 1292system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution 1293system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution | 1295system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1296system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution 1297system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution 1298system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution 1299system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution 1300system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution 1301system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution 1302system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution 1303system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution 1304system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution 1305system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution |
| 1306system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution |
|
| 1294system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution 1295system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes) 1296system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes) 1297system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes) 1298system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes) 1299system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes) 1300system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes) 1301system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes) 1302system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes) 1303system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes) 1304system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes) | 1307system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution 1308system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes) 1309system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes) 1310system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes) 1311system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes) 1312system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes) 1313system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes) 1314system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes) 1315system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes) 1316system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes) 1317system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes) |
| 1305system.cpu.toL2Bus.snoops 61672 # Total snoops (count) 1306system.cpu.toL2Bus.snoop_fanout::samples 4387054 # Request fanout histogram 1307system.cpu.toL2Bus.snoop_fanout::mean 3.010870 # Request fanout histogram 1308system.cpu.toL2Bus.snoop_fanout::stdev 0.103692 # Request fanout histogram | 1318system.cpu.toL2Bus.snoops 63315 # Total snoops (count) 1319system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram 1320system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram 1321system.cpu.toL2Bus.snoop_fanout::stdev 0.098766 # Request fanout histogram |
| 1309system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1310system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1311system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1312system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1322system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1323system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1324system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1325system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1313system.cpu.toL2Bus.snoop_fanout::3 4339366 98.91% 98.91% # Request fanout histogram 1314system.cpu.toL2Bus.snoop_fanout::4 47688 1.09% 100.00% # Request fanout histogram | 1326system.cpu.toL2Bus.snoop_fanout::3 4957986 99.01% 99.01% # Request fanout histogram 1327system.cpu.toL2Bus.snoop_fanout::4 49331 0.99% 100.00% # Request fanout histogram |
| 1315system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1316system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1317system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1328system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1329system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1330system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1318system.cpu.toL2Bus.snoop_fanout::total 4387054 # Request fanout histogram | 1331system.cpu.toL2Bus.snoop_fanout::total 5007317 # Request fanout histogram |
| 1319system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks) 1320system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1321system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks) 1322system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1323system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks) 1324system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1325system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks) 1326system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) --- 228 unchanged lines hidden (view full) --- 1555system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes) 1556system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes) 1557system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes) 1558system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes) 1559system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1560system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) 1561system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes) 1562system.membus.snoops 1635 # Total snoops (count) | 1332system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks) 1333system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1334system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks) 1335system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1336system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks) 1337system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1338system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks) 1339system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) --- 228 unchanged lines hidden (view full) --- 1568system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes) 1569system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes) 1570system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes) 1571system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes) 1572system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1573system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) 1574system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes) 1575system.membus.snoops 1635 # Total snoops (count) |
| 1563system.membus.snoop_fanout::samples 385314 # Request fanout histogram 1564system.membus.snoop_fanout::mean 1 # Request fanout histogram 1565system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1576system.membus.snoop_fanout::samples 1005577 # Request fanout histogram 1577system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram 1578system.membus.snoop_fanout::stdev 0.040388 # Request fanout histogram |
| 1566system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1567system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1579system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1580system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1568system.membus.snoop_fanout::1 385314 100.00% 100.00% # Request fanout histogram 1569system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram | 1581system.membus.snoop_fanout::1 1003934 99.84% 99.84% # Request fanout histogram 1582system.membus.snoop_fanout::2 1643 0.16% 100.00% # Request fanout histogram |
| 1570system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1571system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1583system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1584system.membus.snoop_fanout::min_value 1 # Request fanout histogram |
| 1572system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1573system.membus.snoop_fanout::total 385314 # Request fanout histogram | 1585system.membus.snoop_fanout::max_value 2 # Request fanout histogram 1586system.membus.snoop_fanout::total 1005577 # Request fanout histogram |
| 1574system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks) 1575system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1576system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks) 1577system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1578system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) 1579system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1580system.membus.reqLayer3.occupancy 1203162900 # Layer occupancy (ticks) 1581system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 24 unchanged lines hidden --- | 1587system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks) 1588system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1589system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks) 1590system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1591system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) 1592system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1593system.membus.reqLayer3.occupancy 1203162900 # Layer occupancy (ticks) 1594system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 24 unchanged lines hidden --- |