stats.txt (10726:8a20e2a1562d) stats.txt (10736:4433fb00fa7d)
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2---------- Begin Simulation Statistics ----------
3sim_seconds 5.154240 # Number of seconds simulated
4sim_ticks 5154239928000 # Number of ticks simulated
5final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 177928 # Simulator instruction rate (inst/s)
8host_op_rate 351699 # Simulator op (including micro ops) rate (op/s)

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592system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
593system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
594system.cpu.commit.op_class_0::MemRead 13990083 1.73% 98.96% # Class of committed instruction
595system.cpu.commit.op_class_0::MemWrite 8425634 1.04% 100.00% # Class of committed instruction
596system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
597system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
598system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction
599system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached
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2---------- Begin Simulation Statistics ----------
3sim_seconds 5.154240 # Number of seconds simulated
4sim_ticks 5154239928000 # Number of ticks simulated
5final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 177928 # Simulator instruction rate (inst/s)
8host_op_rate 351699 # Simulator op (including micro ops) rate (op/s)

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592system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
593system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
594system.cpu.commit.op_class_0::MemRead 13990083 1.73% 98.96% # Class of committed instruction
595system.cpu.commit.op_class_0::MemWrite 8425634 1.04% 100.00% # Class of committed instruction
596system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
597system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
598system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction
599system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached
600system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
601system.cpu.rob.rob_reads 1270729806 # The number of ROB reads
602system.cpu.rob.rob_writes 1664729387 # The number of ROB writes
603system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself
604system.cpu.idleCycles 2671825 # Total number of cycles that the CPU has spent unscheduled due to idling
605system.cpu.quiesceCycles 9856461520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
606system.cpu.committedInsts 407959851 # Number of Instructions Simulated
607system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated
608system.cpu.cpi 1.107991 # CPI: Cycles Per Instruction

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600system.cpu.rob.rob_reads 1270729806 # The number of ROB reads
601system.cpu.rob.rob_writes 1664729387 # The number of ROB writes
602system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself
603system.cpu.idleCycles 2671825 # Total number of cycles that the CPU has spent unscheduled due to idling
604system.cpu.quiesceCycles 9856461520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
605system.cpu.committedInsts 407959851 # Number of Instructions Simulated
606system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated
607system.cpu.cpi 1.107991 # CPI: Cycles Per Instruction

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