| stats.txt (10636:9ac724889705) | stats.txt (10639:469cf1ea40f5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.129943 # Number of seconds simulated 4sim_ticks 5129943020500 # Number of ticks simulated 5final_tick 5129943020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.125946 # Number of seconds simulated 4sim_ticks 5125946039500 # Number of ticks simulated 5final_tick 5125946039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 121408 # Simulator instruction rate (inst/s) 8host_op_rate 239988 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1526556123 # Simulator tick rate (ticks/s) 10host_mem_usage 798272 # Number of bytes of host memory used 11host_seconds 3360.47 # Real time elapsed on the host 12sim_insts 407987808 # Number of instructions simulated 13sim_ops 806471132 # Number of ops (including micro ops) simulated | 7host_inst_rate 214937 # Simulator instruction rate (inst/s) 8host_op_rate 424847 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2699457200 # Simulator tick rate (ticks/s) 10host_mem_usage 751580 # Number of bytes of host memory used 11host_seconds 1898.88 # Real time elapsed on the host 12sim_insts 408140259 # Number of instructions simulated 13sim_ops 806733017 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.inst 1049088 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10796544 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.inst 1045568 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10796928 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 11878656 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1049088 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1049088 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9594624 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 11875520 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1045568 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1045568 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9590656 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9590656 # Number of bytes written to this memory |
| 26system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.inst 16392 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 168696 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.inst 16337 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 168702 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::total 185604 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 149916 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 848 # Total read bandwidth from this memory (bytes/s) | 31system.physmem.num_reads::total 185555 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 149854 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 149854 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 849 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::cpu.inst 204503 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 2104613 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2315553 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 204503 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 204503 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1870318 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1870318 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1870318 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 848 # Total bandwidth to/from this memory (bytes/s) | 36system.physmem.bw_read::cpu.inst 203976 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 2106329 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2316747 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 203976 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 203976 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1871002 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1871002 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1871002 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 849 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) | 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::cpu.inst 204503 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 2104613 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4185871 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 185604 # Number of read requests accepted 52system.physmem.writeReqs 196636 # Number of write requests accepted 53system.physmem.readBursts 185604 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 196636 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 11865664 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 12992 # Total number of bytes read from write queue 57system.physmem.bytesWritten 12442240 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 11878656 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 12584704 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 203 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 2199 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1712 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 11483 # Per bank write bursts 64system.physmem.perBankRdBursts::1 10958 # Per bank write bursts 65system.physmem.perBankRdBursts::2 11903 # Per bank write bursts 66system.physmem.perBankRdBursts::3 11497 # Per bank write bursts 67system.physmem.perBankRdBursts::4 11986 # Per bank write bursts 68system.physmem.perBankRdBursts::5 11369 # Per bank write bursts 69system.physmem.perBankRdBursts::6 11563 # Per bank write bursts 70system.physmem.perBankRdBursts::7 11462 # Per bank write bursts 71system.physmem.perBankRdBursts::8 11178 # Per bank write bursts 72system.physmem.perBankRdBursts::9 11812 # Per bank write bursts 73system.physmem.perBankRdBursts::10 11732 # Per bank write bursts 74system.physmem.perBankRdBursts::11 11823 # Per bank write bursts 75system.physmem.perBankRdBursts::12 11783 # Per bank write bursts 76system.physmem.perBankRdBursts::13 12309 # Per bank write bursts 77system.physmem.perBankRdBursts::14 11732 # Per bank write bursts 78system.physmem.perBankRdBursts::15 10811 # Per bank write bursts 79system.physmem.perBankWrBursts::0 14023 # Per bank write bursts 80system.physmem.perBankWrBursts::1 13077 # Per bank write bursts 81system.physmem.perBankWrBursts::2 12485 # Per bank write bursts 82system.physmem.perBankWrBursts::3 11134 # Per bank write bursts 83system.physmem.perBankWrBursts::4 11942 # Per bank write bursts 84system.physmem.perBankWrBursts::5 11710 # Per bank write bursts 85system.physmem.perBankWrBursts::6 11692 # Per bank write bursts 86system.physmem.perBankWrBursts::7 11673 # Per bank write bursts 87system.physmem.perBankWrBursts::8 11519 # Per bank write bursts 88system.physmem.perBankWrBursts::9 11764 # Per bank write bursts 89system.physmem.perBankWrBursts::10 12914 # Per bank write bursts 90system.physmem.perBankWrBursts::11 11938 # Per bank write bursts 91system.physmem.perBankWrBursts::12 12257 # Per bank write bursts 92system.physmem.perBankWrBursts::13 11913 # Per bank write bursts 93system.physmem.perBankWrBursts::14 12398 # Per bank write bursts 94system.physmem.perBankWrBursts::15 11971 # Per bank write bursts | 47system.physmem.bw_total::cpu.inst 203976 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 2106329 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4187749 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 185555 # Number of read requests accepted 52system.physmem.writeReqs 196574 # Number of write requests accepted 53system.physmem.readBursts 185555 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 196574 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 11866560 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue 57system.physmem.bytesWritten 12447744 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 11875520 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 12580736 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 2049 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1754 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 11700 # Per bank write bursts 64system.physmem.perBankRdBursts::1 10942 # Per bank write bursts 65system.physmem.perBankRdBursts::2 11772 # Per bank write bursts 66system.physmem.perBankRdBursts::3 11534 # Per bank write bursts 67system.physmem.perBankRdBursts::4 11556 # Per bank write bursts 68system.physmem.perBankRdBursts::5 11202 # Per bank write bursts 69system.physmem.perBankRdBursts::6 11589 # Per bank write bursts 70system.physmem.perBankRdBursts::7 11470 # Per bank write bursts 71system.physmem.perBankRdBursts::8 10957 # Per bank write bursts 72system.physmem.perBankRdBursts::9 11574 # Per bank write bursts 73system.physmem.perBankRdBursts::10 11037 # Per bank write bursts 74system.physmem.perBankRdBursts::11 11773 # Per bank write bursts 75system.physmem.perBankRdBursts::12 12032 # Per bank write bursts 76system.physmem.perBankRdBursts::13 13037 # Per bank write bursts 77system.physmem.perBankRdBursts::14 11759 # Per bank write bursts 78system.physmem.perBankRdBursts::15 11481 # Per bank write bursts 79system.physmem.perBankWrBursts::0 13445 # Per bank write bursts 80system.physmem.perBankWrBursts::1 12349 # Per bank write bursts 81system.physmem.perBankWrBursts::2 11384 # Per bank write bursts 82system.physmem.perBankWrBursts::3 11463 # Per bank write bursts 83system.physmem.perBankWrBursts::4 12267 # Per bank write bursts 84system.physmem.perBankWrBursts::5 12371 # Per bank write bursts 85system.physmem.perBankWrBursts::6 11486 # Per bank write bursts 86system.physmem.perBankWrBursts::7 11359 # Per bank write bursts 87system.physmem.perBankWrBursts::8 11596 # Per bank write bursts 88system.physmem.perBankWrBursts::9 12338 # Per bank write bursts 89system.physmem.perBankWrBursts::10 11770 # Per bank write bursts 90system.physmem.perBankWrBursts::11 12080 # Per bank write bursts 91system.physmem.perBankWrBursts::12 12282 # Per bank write bursts 92system.physmem.perBankWrBursts::13 12669 # Per bank write bursts 93system.physmem.perBankWrBursts::14 12453 # Per bank write bursts 94system.physmem.perBankWrBursts::15 13184 # Per bank write bursts |
| 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 97system.physmem.totGap 5129942968500 # Total gap between requests | 97system.physmem.totGap 5125945988000 # Total gap between requests |
| 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) | 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 104system.physmem.readPktSize::6 185604 # Read request sizes (log2) | 104system.physmem.readPktSize::6 185555 # Read request sizes (log2) |
| 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) | 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 111system.physmem.writePktSize::6 196636 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 170730 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 11911 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 2018 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 400 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see | 111system.physmem.writePktSize::6 196574 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 170769 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 11917 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 2025 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 375 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see |
| 120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see | 120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see |
| 122system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 28 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 28 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see | 122system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see |
| 127system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 127system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::15 2574 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 4997 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 9722 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 11014 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 11539 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 12555 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 13007 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 14095 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 13776 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 14313 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 13208 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 12728 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 11239 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 10589 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 8962 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 8627 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 8507 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 8355 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 501 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 411 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 382 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 322 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 228 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 235 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 122 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 75289 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 322.860444 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 187.432072 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 341.383638 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 27971 37.15% 37.15% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 17364 23.06% 60.21% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 7569 10.05% 70.27% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 4193 5.57% 75.84% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 3123 4.15% 79.99% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1949 2.59% 82.57% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1359 1.81% 84.38% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1178 1.56% 85.94% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 10583 14.06% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 75289 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 7789 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 23.801643 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 545.365861 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 7788 99.99% 99.99% # Reads before turning the bus around for writes | 159system.physmem.wrQLenPdf::15 2509 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 4824 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 9547 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 10935 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 11433 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 12449 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 12895 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 13963 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 13629 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 14296 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 13176 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 12672 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 11348 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 10803 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 9189 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 8820 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 8678 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 8475 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 592 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 508 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 443 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 373 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 235 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 213 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 194 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 156 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 147 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 75192 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 323.362060 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 187.476414 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 341.898646 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 27996 37.23% 37.23% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 17297 23.00% 60.24% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 7451 9.91% 70.15% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 4205 5.59% 75.74% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 3004 4.00% 79.73% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 2064 2.74% 82.48% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1408 1.87% 84.35% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1199 1.59% 85.95% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 10568 14.05% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 75192 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 7811 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 23.734349 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 544.550807 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 7810 99.99% 99.99% # Reads before turning the bus around for writes |
| 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes | 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 227system.physmem.rdPerTurnAround::total 7789 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 7789 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 24.959558 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 20.372117 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 24.594707 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 6350 81.53% 81.53% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 59 0.76% 82.28% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 17 0.22% 82.50% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 286 3.67% 86.17% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 164 2.11% 88.28% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 59 0.76% 89.04% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 41 0.53% 89.56% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 34 0.44% 90.00% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 175 2.25% 92.25% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 16 0.21% 92.45% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 16 0.21% 92.66% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 13 0.17% 92.82% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 28 0.36% 93.18% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 16 0.21% 93.39% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 10 0.13% 93.52% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 42 0.54% 94.06% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 108 1.39% 95.44% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 9 0.12% 95.56% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-91 9 0.12% 95.67% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::92-95 24 0.31% 95.98% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 141 1.81% 97.79% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 3 0.04% 97.83% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 13 0.17% 98.00% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 4 0.05% 98.05% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 34 0.44% 98.49% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 3 0.04% 98.52% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 10 0.13% 98.65% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.01% 98.66% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 14 0.18% 98.84% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 5 0.06% 98.91% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.01% 98.92% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 5 0.06% 98.99% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 13 0.17% 99.15% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::148-151 10 0.13% 99.28% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::152-155 3 0.04% 99.32% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 6 0.08% 99.40% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 11 0.14% 99.54% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::164-167 3 0.04% 99.58% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::172-175 3 0.04% 99.64% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::176-179 5 0.06% 99.70% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::180-183 1 0.01% 99.72% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::184-187 3 0.04% 99.76% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::188-191 1 0.01% 99.77% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::196-199 2 0.03% 99.79% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::200-203 6 0.08% 99.87% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::204-207 3 0.04% 99.91% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::220-223 1 0.01% 99.95% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::224-227 1 0.01% 99.96% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::total 7789 # Writes before turning the bus around for reads 287system.physmem.totQLat 1998636250 # Total ticks spent queuing 288system.physmem.totMemAccLat 5474905000 # Total ticks spent from burst creation until serviced by the DRAM 289system.physmem.totBusLat 927005000 # Total ticks spent in databus transfers 290system.physmem.avgQLat 10780.07 # Average queueing delay per DRAM burst | 227system.physmem.rdPerTurnAround::total 7811 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 7811 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 24.900269 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 20.294695 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 24.961495 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 6395 81.87% 81.87% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 66 0.84% 82.72% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 12 0.15% 82.87% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 258 3.30% 86.17% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 186 2.38% 88.55% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 50 0.64% 89.19% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 38 0.49% 89.68% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 45 0.58% 90.26% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 169 2.16% 92.42% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 11 0.14% 92.56% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 12 0.15% 92.72% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 16 0.20% 92.92% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 26 0.33% 93.25% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 16 0.20% 93.46% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 15 0.19% 93.65% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 41 0.52% 94.17% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 93 1.19% 95.37% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 13 0.17% 95.53% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-91 9 0.12% 95.65% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::92-95 19 0.24% 95.89% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 147 1.88% 97.77% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 3 0.04% 97.81% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 13 0.17% 97.98% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 4 0.05% 98.03% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 20 0.26% 98.28% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 9 0.12% 98.40% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 5 0.06% 98.46% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 3 0.04% 98.50% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 27 0.35% 98.85% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 13 0.17% 99.01% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 2 0.03% 99.04% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 4 0.05% 99.09% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 11 0.14% 99.23% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::148-151 10 0.13% 99.36% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::152-155 4 0.05% 99.41% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 2 0.03% 99.44% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 5 0.06% 99.50% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::164-167 3 0.04% 99.54% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::168-171 3 0.04% 99.58% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::172-175 2 0.03% 99.60% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::176-179 7 0.09% 99.69% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::180-183 1 0.01% 99.71% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::184-187 1 0.01% 99.72% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::188-191 2 0.03% 99.74% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::208-211 1 0.01% 99.76% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::212-215 1 0.01% 99.77% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::216-219 1 0.01% 99.78% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::220-223 7 0.09% 99.87% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::224-227 3 0.04% 99.91% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::228-231 2 0.03% 99.94% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::248-251 4 0.05% 99.99% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::total 7811 # Writes before turning the bus around for reads 285system.physmem.totQLat 1990259250 # Total ticks spent queuing 286system.physmem.totMemAccLat 5466790500 # Total ticks spent from burst creation until serviced by the DRAM 287system.physmem.totBusLat 927075000 # Total ticks spent in databus transfers 288system.physmem.avgQLat 10734.08 # Average queueing delay per DRAM burst |
| 291system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 289system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 292system.physmem.avgMemAccLat 29530.07 # Average memory access latency per DRAM burst | 290system.physmem.avgMemAccLat 29484.08 # Average memory access latency per DRAM burst |
| 293system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s 294system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s 295system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s 296system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s 297system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 298system.physmem.busUtil 0.04 # Data bus utilization in percentage 299system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 300system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 301system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing | 291system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s 292system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s 293system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s 294system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s 295system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 296system.physmem.busUtil 0.04 # Data bus utilization in percentage 297system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 298system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 299system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing |
| 302system.physmem.avgWrQLen 25.71 # Average write queue length when enqueuing 303system.physmem.readRowHits 152292 # Number of row buffer hits during reads 304system.physmem.writeRowHits 152229 # Number of row buffer hits during writes 305system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads 306system.physmem.writeRowHitRate 78.29 # Row buffer hit rate for writes 307system.physmem.avgGap 13420738.20 # Average gap between requests 308system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined 309system.physmem_0.actEnergy 279697320 # Energy for activate commands per rank (pJ) 310system.physmem_0.preEnergy 152612625 # Energy for precharge commands per rank (pJ) 311system.physmem_0.readEnergy 719316000 # Energy for read commands per rank (pJ) 312system.physmem_0.writeEnergy 633329280 # Energy for write commands per rank (pJ) 313system.physmem_0.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ) 314system.physmem_0.actBackEnergy 129572750835 # Energy for active background per rank (pJ) 315system.physmem_0.preBackEnergy 2964303640500 # Energy for precharge background per rank (pJ) 316system.physmem_0.totalEnergy 3430724068320 # Total energy per rank (pJ) 317system.physmem_0.averagePower 668.764961 # Core power per rank (mW) 318system.physmem_0.memoryStateTime::IDLE 4931314948000 # Time in different power states 319system.physmem_0.memoryStateTime::REF 171299960000 # Time in different power states | 300system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing 301system.physmem.readRowHits 152358 # Number of row buffer hits during reads 302system.physmem.writeRowHits 152360 # Number of row buffer hits during writes 303system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads 304system.physmem.writeRowHitRate 78.32 # Row buffer hit rate for writes 305system.physmem.avgGap 13414176.86 # Average gap between requests 306system.physmem.pageHitRate 80.20 # Row buffer hit rate, read and write combined 307system.physmem_0.actEnergy 277686360 # Energy for activate commands per rank (pJ) 308system.physmem_0.preEnergy 151515375 # Energy for precharge commands per rank (pJ) 309system.physmem_0.readEnergy 715759200 # Energy for read commands per rank (pJ) 310system.physmem_0.writeEnergy 622883520 # Energy for write commands per rank (pJ) 311system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) 312system.physmem_0.actBackEnergy 129454885665 # Energy for active background per rank (pJ) 313system.physmem_0.preBackEnergy 2962010423250 # Energy for precharge background per rank (pJ) 314system.physmem_0.totalEnergy 3428034983850 # Total energy per rank (pJ) 315system.physmem_0.averagePower 668.761488 # Core power per rank (mW) 316system.physmem_0.memoryStateTime::IDLE 4927497903250 # Time in different power states 317system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states |
| 320system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 318system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 321system.physmem_0.memoryStateTime::ACT 27328009000 # Time in different power states | 319system.physmem_0.memoryStateTime::ACT 27281453250 # Time in different power states |
| 322system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 320system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 323system.physmem_1.actEnergy 289487520 # Energy for activate commands per rank (pJ) 324system.physmem_1.preEnergy 157954500 # Energy for precharge commands per rank (pJ) 325system.physmem_1.readEnergy 726804000 # Energy for read commands per rank (pJ) 326system.physmem_1.writeEnergy 626447520 # Energy for write commands per rank (pJ) 327system.physmem_1.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ) 328system.physmem_1.actBackEnergy 129789266760 # Energy for active background per rank (pJ) 329system.physmem_1.preBackEnergy 2964113714250 # Energy for precharge background per rank (pJ) 330system.physmem_1.totalEnergy 3430766396310 # Total energy per rank (pJ) 331system.physmem_1.averagePower 668.773213 # Core power per rank (mW) 332system.physmem_1.memoryStateTime::IDLE 4930997374750 # Time in different power states 333system.physmem_1.memoryStateTime::REF 171299960000 # Time in different power states | 321system.physmem_1.actEnergy 290765160 # Energy for activate commands per rank (pJ) 322system.physmem_1.preEnergy 158651625 # Energy for precharge commands per rank (pJ) 323system.physmem_1.readEnergy 730470000 # Energy for read commands per rank (pJ) 324system.physmem_1.writeEnergy 637450560 # Energy for write commands per rank (pJ) 325system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) 326system.physmem_1.actBackEnergy 129625961760 # Energy for active background per rank (pJ) 327system.physmem_1.preBackEnergy 2961860356500 # Energy for precharge background per rank (pJ) 328system.physmem_1.totalEnergy 3428105486085 # Total energy per rank (pJ) 329system.physmem_1.averagePower 668.775242 # Core power per rank (mW) 330system.physmem_1.memoryStateTime::IDLE 4927247811250 # Time in different power states 331system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states |
| 334system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 332system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 335system.physmem_1.memoryStateTime::ACT 27642592750 # Time in different power states | 333system.physmem_1.memoryStateTime::ACT 27531190000 # Time in different power states |
| 336system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 334system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 337system.cpu.branchPred.lookups 86966196 # Number of BP lookups 338system.cpu.branchPred.condPredicted 86966196 # Number of conditional branches predicted 339system.cpu.branchPred.condIncorrect 908530 # Number of conditional branches incorrect 340system.cpu.branchPred.BTBLookups 80060297 # Number of BTB lookups 341system.cpu.branchPred.BTBHits 78222813 # Number of BTB hits | 335system.cpu.branchPred.lookups 87010872 # Number of BP lookups 336system.cpu.branchPred.condPredicted 87010872 # Number of conditional branches predicted 337system.cpu.branchPred.condIncorrect 908907 # Number of conditional branches incorrect 338system.cpu.branchPred.BTBLookups 80241948 # Number of BTB lookups 339system.cpu.branchPred.BTBHits 78260393 # Number of BTB hits |
| 342system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 340system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 343system.cpu.branchPred.BTBHitPct 97.704875 # BTB Hit Percentage 344system.cpu.branchPred.usedRAS 1554803 # Number of times the RAS was used to get a target. 345system.cpu.branchPred.RASInCorrect 179885 # Number of incorrect RAS predictions. | 341system.cpu.branchPred.BTBHitPct 97.530525 # BTB Hit Percentage 342system.cpu.branchPred.usedRAS 1567280 # Number of times the RAS was used to get a target. 343system.cpu.branchPred.RASInCorrect 181222 # Number of incorrect RAS predictions. |
| 346system.cpu_clk_domain.clock 500 # Clock period in ticks 347system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 344system.cpu_clk_domain.clock 500 # Clock period in ticks 345system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 348system.cpu.numCycles 449725865 # number of cpu cycles simulated | 346system.cpu.numCycles 449757362 # number of cpu cycles simulated |
| 349system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 350system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 347system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 348system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 351system.cpu.fetch.icacheStallCycles 27729826 # Number of cycles fetch is stalled on an Icache miss 352system.cpu.fetch.Insts 429316628 # Number of instructions fetch has processed 353system.cpu.fetch.Branches 86966196 # Number of branches that fetch encountered 354system.cpu.fetch.predictedBranches 79777616 # Number of branches that fetch has predicted taken 355system.cpu.fetch.Cycles 417943861 # Number of cycles fetch has run and was not squashing or blocked 356system.cpu.fetch.SquashCycles 1905694 # Number of cycles fetch has spent squashing 357system.cpu.fetch.TlbCycles 153883 # Number of cycles fetch has spent waiting for tlb 358system.cpu.fetch.MiscStallCycles 50061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 359system.cpu.fetch.PendingTrapStallCycles 216755 # Number of stall cycles due to pending traps 360system.cpu.fetch.PendingQuiesceStallCycles 126625 # Number of stall cycles due to pending quiesce instructions 361system.cpu.fetch.IcacheWaitRetryStallCycles 694 # Number of stall cycles due to full MSHR 362system.cpu.fetch.CacheLines 9209956 # Number of cache lines fetched 363system.cpu.fetch.IcacheSquashes 450181 # Number of outstanding Icache misses that were squashed 364system.cpu.fetch.ItlbSquashes 5437 # Number of outstanding ITLB misses that were squashed 365system.cpu.fetch.rateDist::samples 447174552 # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::mean 1.894587 # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::stdev 3.051890 # Number of instructions fetched each cycle (Total) | 349system.cpu.fetch.icacheStallCycles 27680627 # Number of cycles fetch is stalled on an Icache miss 350system.cpu.fetch.Insts 429642410 # Number of instructions fetch has processed 351system.cpu.fetch.Branches 87010872 # Number of branches that fetch encountered 352system.cpu.fetch.predictedBranches 79827673 # Number of branches that fetch has predicted taken 353system.cpu.fetch.Cycles 418150440 # Number of cycles fetch has run and was not squashing or blocked 354system.cpu.fetch.SquashCycles 1906654 # Number of cycles fetch has spent squashing 355system.cpu.fetch.TlbCycles 150208 # Number of cycles fetch has spent waiting for tlb 356system.cpu.fetch.MiscStallCycles 58666 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 357system.cpu.fetch.PendingTrapStallCycles 213443 # Number of stall cycles due to pending traps 358system.cpu.fetch.PendingQuiesceStallCycles 140 # Number of stall cycles due to pending quiesce instructions 359system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR 360system.cpu.fetch.CacheLines 9233721 # Number of cache lines fetched 361system.cpu.fetch.IcacheSquashes 451702 # Number of outstanding Icache misses that were squashed 362system.cpu.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed 363system.cpu.fetch.rateDist::samples 447207287 # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::mean 1.895606 # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::stdev 3.052695 # Number of instructions fetched each cycle (Total) |
| 368system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 366system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 369system.cpu.fetch.rateDist::0 281545500 62.96% 62.96% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::1 2299594 0.51% 63.48% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::2 72183543 16.14% 79.62% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::3 1609599 0.36% 79.98% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::4 2153830 0.48% 80.46% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::5 2329535 0.52% 80.98% # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::6 1534724 0.34% 81.32% # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::7 1901427 0.43% 81.75% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::8 81616800 18.25% 100.00% # Number of instructions fetched each cycle (Total) | 367system.cpu.fetch.rateDist::0 281559277 62.96% 62.96% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::1 2214583 0.50% 63.45% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::2 72218429 16.15% 79.60% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::3 1625336 0.36% 79.97% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::4 2151026 0.48% 80.45% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::5 2311115 0.52% 80.96% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::6 1533968 0.34% 81.31% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::7 1910699 0.43% 81.73% # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::8 81682854 18.27% 100.00% # Number of instructions fetched each cycle (Total) |
| 378system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 376system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 381system.cpu.fetch.rateDist::total 447174552 # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.branchRate 0.193376 # Number of branch fetches per cycle 383system.cpu.fetch.rate 0.954618 # Number of inst fetches per cycle 384system.cpu.decode.IdleCycles 23090202 # Number of cycles decode is idle 385system.cpu.decode.BlockedCycles 264882686 # Number of cycles decode is blocked 386system.cpu.decode.RunCycles 150813511 # Number of cycles decode is running 387system.cpu.decode.UnblockCycles 7435306 # Number of cycles decode is unblocking 388system.cpu.decode.SquashCycles 952847 # Number of cycles decode is squashing 389system.cpu.decode.DecodedInsts 838903899 # Number of instructions handled by decode 390system.cpu.rename.SquashCycles 952847 # Number of cycles rename is squashing 391system.cpu.rename.IdleCycles 25942831 # Number of cycles rename is idle 392system.cpu.rename.BlockCycles 223326641 # Number of cycles rename is blocking 393system.cpu.rename.serializeStallCycles 13232428 # count of cycles rename stalled for serializing inst 394system.cpu.rename.RunCycles 154708804 # Number of cycles rename is running 395system.cpu.rename.UnblockCycles 29011001 # Number of cycles rename is unblocking 396system.cpu.rename.RenamedInsts 835406292 # Number of instructions processed by rename 397system.cpu.rename.ROBFullEvents 477425 # Number of times rename has blocked due to ROB full 398system.cpu.rename.IQFullEvents 12418228 # Number of times rename has blocked due to IQ full 399system.cpu.rename.LQFullEvents 176585 # Number of times rename has blocked due to LQ full 400system.cpu.rename.SQFullEvents 13740194 # Number of times rename has blocked due to SQ full 401system.cpu.rename.RenamedOperands 997876395 # Number of destination operands rename has renamed 402system.cpu.rename.RenameLookups 1814508658 # Number of register rename lookups that rename has made 403system.cpu.rename.int_rename_lookups 1115444420 # Number of integer rename lookups 404system.cpu.rename.fp_rename_lookups 102 # Number of floating rename lookups 405system.cpu.rename.CommittedMaps 964480017 # Number of HB maps that are committed 406system.cpu.rename.UndoneMaps 33396376 # Number of HB maps that are undone due to squashing 407system.cpu.rename.serializingInsts 469202 # count of serializing insts renamed 408system.cpu.rename.tempSerializingInsts 473127 # count of temporary serializing insts renamed 409system.cpu.rename.skidInsts 39031385 # count of insts added to the skid buffer 410system.cpu.memDep0.insertedLoads 17359783 # Number of loads inserted to the mem dependence unit. 411system.cpu.memDep0.insertedStores 10198929 # Number of stores inserted to the mem dependence unit. 412system.cpu.memDep0.conflictingLoads 1317086 # Number of conflicting loads. 413system.cpu.memDep0.conflictingStores 1098616 # Number of conflicting stores. 414system.cpu.iq.iqInstsAdded 829832373 # Number of instructions added to the IQ (excludes non-spec) 415system.cpu.iq.iqNonSpecInstsAdded 1210818 # Number of non-speculative instructions added to the IQ 416system.cpu.iq.iqInstsIssued 824505871 # Number of instructions issued 417system.cpu.iq.iqSquashedInstsIssued 240863 # Number of squashed instructions issued 418system.cpu.iq.iqSquashedInstsExamined 23642425 # Number of squashed instructions iterated over during squash; mainly for profiling 419system.cpu.iq.iqSquashedOperandsExamined 36460999 # Number of squashed operands that are examined and possibly removed from graph 420system.cpu.iq.iqSquashedNonSpecRemoved 154878 # Number of squashed non-spec instructions that were removed 421system.cpu.iq.issued_per_cycle::samples 447174552 # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::mean 1.843812 # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::stdev 2.418056 # Number of insts issued each cycle | 379system.cpu.fetch.rateDist::total 447207287 # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.branchRate 0.193462 # Number of branch fetches per cycle 381system.cpu.fetch.rate 0.955276 # Number of inst fetches per cycle 382system.cpu.decode.IdleCycles 23009193 # Number of cycles decode is idle 383system.cpu.decode.BlockedCycles 264931793 # Number of cycles decode is blocked 384system.cpu.decode.RunCycles 150859313 # Number of cycles decode is running 385system.cpu.decode.UnblockCycles 7453661 # Number of cycles decode is unblocking 386system.cpu.decode.SquashCycles 953327 # Number of cycles decode is squashing 387system.cpu.decode.DecodedInsts 839350026 # Number of instructions handled by decode 388system.cpu.rename.SquashCycles 953327 # Number of cycles rename is squashing 389system.cpu.rename.IdleCycles 25875798 # Number of cycles rename is idle 390system.cpu.rename.BlockCycles 223334745 # Number of cycles rename is blocking 391system.cpu.rename.serializeStallCycles 13198087 # count of cycles rename stalled for serializing inst 392system.cpu.rename.RunCycles 154759437 # Number of cycles rename is running 393system.cpu.rename.UnblockCycles 29085893 # Number of cycles rename is unblocking 394system.cpu.rename.RenamedInsts 835811014 # Number of instructions processed by rename 395system.cpu.rename.ROBFullEvents 482001 # Number of times rename has blocked due to ROB full 396system.cpu.rename.IQFullEvents 12419616 # Number of times rename has blocked due to IQ full 397system.cpu.rename.LQFullEvents 206377 # Number of times rename has blocked due to LQ full 398system.cpu.rename.SQFullEvents 13783403 # Number of times rename has blocked due to SQ full 399system.cpu.rename.RenamedOperands 998347758 # Number of destination operands rename has renamed 400system.cpu.rename.RenameLookups 1815644422 # Number of register rename lookups that rename has made 401system.cpu.rename.int_rename_lookups 1116079946 # Number of integer rename lookups 402system.cpu.rename.fp_rename_lookups 122 # Number of floating rename lookups 403system.cpu.rename.CommittedMaps 964783456 # Number of HB maps that are committed 404system.cpu.rename.UndoneMaps 33564300 # Number of HB maps that are undone due to squashing 405system.cpu.rename.serializingInsts 467714 # count of serializing insts renamed 406system.cpu.rename.tempSerializingInsts 471747 # count of temporary serializing insts renamed 407system.cpu.rename.skidInsts 39093495 # count of insts added to the skid buffer 408system.cpu.memDep0.insertedLoads 17396694 # Number of loads inserted to the mem dependence unit. 409system.cpu.memDep0.insertedStores 10208602 # Number of stores inserted to the mem dependence unit. 410system.cpu.memDep0.conflictingLoads 1304613 # Number of conflicting loads. 411system.cpu.memDep0.conflictingStores 1095322 # Number of conflicting stores. 412system.cpu.iq.iqInstsAdded 830247357 # Number of instructions added to the IQ (excludes non-spec) 413system.cpu.iq.iqNonSpecInstsAdded 1203823 # Number of non-speculative instructions added to the IQ 414system.cpu.iq.iqInstsIssued 824890478 # Number of instructions issued 415system.cpu.iq.iqSquashedInstsIssued 241321 # Number of squashed instructions issued 416system.cpu.iq.iqSquashedInstsExamined 23772173 # Number of squashed instructions iterated over during squash; mainly for profiling 417system.cpu.iq.iqSquashedOperandsExamined 36627244 # Number of squashed operands that are examined and possibly removed from graph 418system.cpu.iq.iqSquashedNonSpecRemoved 152885 # Number of squashed non-spec instructions that were removed 419system.cpu.iq.issued_per_cycle::samples 447207287 # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::mean 1.844537 # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::stdev 2.418419 # Number of insts issued each cycle |
| 424system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 422system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 425system.cpu.iq.issued_per_cycle::0 262851560 58.78% 58.78% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::1 13883927 3.10% 61.89% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::2 10098896 2.26% 64.14% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::3 6926055 1.55% 65.69% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::4 74362880 16.63% 82.32% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::5 4459374 1.00% 83.32% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::6 72818710 16.28% 99.60% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::7 1199863 0.27% 99.87% # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::8 573287 0.13% 100.00% # Number of insts issued each cycle | 423system.cpu.iq.issued_per_cycle::0 262823455 58.77% 58.77% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::1 13859186 3.10% 61.87% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::2 10127573 2.26% 64.13% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::3 6921797 1.55% 65.68% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::4 74369123 16.63% 82.31% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::5 4467728 1.00% 83.31% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::6 72848553 16.29% 99.60% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::7 1214671 0.27% 99.87% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::8 575201 0.13% 100.00% # Number of insts issued each cycle |
| 434system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 432system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 437system.cpu.iq.issued_per_cycle::total 447174552 # Number of insts issued each cycle | 435system.cpu.iq.issued_per_cycle::total 447207287 # Number of insts issued each cycle |
| 438system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 436system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 439system.cpu.iq.fu_full::IntAlu 1983031 71.93% 71.93% # attempts to use FU when none available 440system.cpu.iq.fu_full::IntMult 252 0.01% 71.94% # attempts to use FU when none available 441system.cpu.iq.fu_full::IntDiv 1287 0.05% 71.99% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.99% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.99% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.99% # attempts to use FU when none available 445system.cpu.iq.fu_full::FloatMult 0 0.00% 71.99% # attempts to use FU when none available 446system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.99% # attempts to use FU when none available 447system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.99% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.99% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.99% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.99% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.99% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.99% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.99% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdMult 0 0.00% 71.99% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.99% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdShift 0 0.00% 71.99% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.99% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.99% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.99% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.99% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.99% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.99% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.99% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.99% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.99% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.99% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.99% # attempts to use FU when none available 468system.cpu.iq.fu_full::MemRead 612199 22.21% 94.19% # attempts to use FU when none available 469system.cpu.iq.fu_full::MemWrite 160068 5.81% 100.00% # attempts to use FU when none available | 437system.cpu.iq.fu_full::IntAlu 2002012 72.04% 72.04% # attempts to use FU when none available 438system.cpu.iq.fu_full::IntMult 252 0.01% 72.05% # attempts to use FU when none available 439system.cpu.iq.fu_full::IntDiv 1516 0.05% 72.10% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.10% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.10% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.10% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatMult 0 0.00% 72.10% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.10% # attempts to use FU when none available 445system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.10% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.10% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.10% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.10% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.10% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.10% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.10% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdMult 0 0.00% 72.10% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.10% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdShift 0 0.00% 72.10% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.10% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.10% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.10% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.10% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.10% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.10% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.10% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.10% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.10% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.10% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.10% # attempts to use FU when none available 466system.cpu.iq.fu_full::MemRead 615311 22.14% 94.24% # attempts to use FU when none available 467system.cpu.iq.fu_full::MemWrite 160020 5.76% 100.00% # attempts to use FU when none available |
| 470system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 471system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 468system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 469system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 472system.cpu.iq.FU_type_0::No_OpClass 294191 0.04% 0.04% # Type of FU issued 473system.cpu.iq.FU_type_0::IntAlu 796088573 96.55% 96.59% # Type of FU issued 474system.cpu.iq.FU_type_0::IntMult 150664 0.02% 96.61% # Type of FU issued 475system.cpu.iq.FU_type_0::IntDiv 125614 0.02% 96.62% # Type of FU issued | 470system.cpu.iq.FU_type_0::No_OpClass 292641 0.04% 0.04% # Type of FU issued 471system.cpu.iq.FU_type_0::IntAlu 796440241 96.55% 96.59% # Type of FU issued 472system.cpu.iq.FU_type_0::IntMult 150873 0.02% 96.60% # Type of FU issued 473system.cpu.iq.FU_type_0::IntDiv 125700 0.02% 96.62% # Type of FU issued |
| 476system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued 480system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued 481system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 494system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued | 474system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 492system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued |
| 502system.cpu.iq.FU_type_0::MemRead 18441786 2.24% 98.86% # Type of FU issued 503system.cpu.iq.FU_type_0::MemWrite 9405043 1.14% 100.00% # Type of FU issued | 500system.cpu.iq.FU_type_0::MemRead 18469737 2.24% 98.86% # Type of FU issued 501system.cpu.iq.FU_type_0::MemWrite 9411286 1.14% 100.00% # Type of FU issued |
| 504system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 505system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 502system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 503system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 506system.cpu.iq.FU_type_0::total 824505871 # Type of FU issued 507system.cpu.iq.rate 1.833352 # Inst issue rate 508system.cpu.iq.fu_busy_cnt 2756837 # FU busy when requested 509system.cpu.iq.fu_busy_rate 0.003344 # FU busy rate (busy events/executed inst) 510system.cpu.iq.int_inst_queue_reads 2099183812 # Number of integer instruction queue reads 511system.cpu.iq.int_inst_queue_writes 854698119 # Number of integer instruction queue writes 512system.cpu.iq.int_inst_queue_wakeup_accesses 819923286 # Number of integer instruction queue wakeup accesses 513system.cpu.iq.fp_inst_queue_reads 181 # Number of floating instruction queue reads 514system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes 515system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses 516system.cpu.iq.int_alu_accesses 826968435 # Number of integer alu accesses 517system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses 518system.cpu.iew.lsq.thread0.forwLoads 1878873 # Number of loads that had data forwarded from stores | 504system.cpu.iq.FU_type_0::total 824890478 # Type of FU issued 505system.cpu.iq.rate 1.834079 # Inst issue rate 506system.cpu.iq.fu_busy_cnt 2779111 # FU busy when requested 507system.cpu.iq.fu_busy_rate 0.003369 # FU busy rate (busy events/executed inst) 508system.cpu.iq.int_inst_queue_reads 2100008470 # Number of integer instruction queue reads 509system.cpu.iq.int_inst_queue_writes 855235960 # Number of integer instruction queue writes 510system.cpu.iq.int_inst_queue_wakeup_accesses 820301631 # Number of integer instruction queue wakeup accesses 511system.cpu.iq.fp_inst_queue_reads 204 # Number of floating instruction queue reads 512system.cpu.iq.fp_inst_queue_writes 226 # Number of floating instruction queue writes 513system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses 514system.cpu.iq.int_alu_accesses 827376851 # Number of integer alu accesses 515system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses 516system.cpu.iew.lsq.thread0.forwLoads 1872015 # Number of loads that had data forwarded from stores |
| 519system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 517system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 520system.cpu.iew.lsq.thread0.squashedLoads 3357342 # Number of loads squashed 521system.cpu.iew.lsq.thread0.ignoredResponses 15595 # Number of memory responses ignored because the instruction is squashed 522system.cpu.iew.lsq.thread0.memOrderViolation 14483 # Number of memory ordering violations 523system.cpu.iew.lsq.thread0.squashedStores 1769318 # Number of stores squashed | 518system.cpu.iew.lsq.thread0.squashedLoads 3394675 # Number of loads squashed 519system.cpu.iew.lsq.thread0.ignoredResponses 15480 # Number of memory responses ignored because the instruction is squashed 520system.cpu.iew.lsq.thread0.memOrderViolation 14595 # Number of memory ordering violations 521system.cpu.iew.lsq.thread0.squashedStores 1778587 # Number of stores squashed |
| 524system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 525system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 522system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 523system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 526system.cpu.iew.lsq.thread0.rescheduledLoads 2224742 # Number of loads that were rescheduled 527system.cpu.iew.lsq.thread0.cacheBlocked 72242 # Number of times an access to memory failed due to the cache being blocked | 524system.cpu.iew.lsq.thread0.rescheduledLoads 2224947 # Number of loads that were rescheduled 525system.cpu.iew.lsq.thread0.cacheBlocked 72059 # Number of times an access to memory failed due to the cache being blocked |
| 528system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 526system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 529system.cpu.iew.iewSquashCycles 952847 # Number of cycles IEW is squashing 530system.cpu.iew.iewBlockCycles 205624678 # Number of cycles IEW is blocking 531system.cpu.iew.iewUnblockCycles 9408932 # Number of cycles IEW is unblocking 532system.cpu.iew.iewDispatchedInsts 831043191 # Number of instructions dispatched to IQ 533system.cpu.iew.iewDispSquashedInsts 186605 # Number of squashed instructions skipped by dispatch 534system.cpu.iew.iewDispLoadInsts 17359783 # Number of dispatched load instructions 535system.cpu.iew.iewDispStoreInsts 10198929 # Number of dispatched store instructions 536system.cpu.iew.iewDispNonSpecInsts 713805 # Number of dispatched non-speculative instructions 537system.cpu.iew.iewIQFullEvents 415277 # Number of times the IQ has become full, causing a stall 538system.cpu.iew.iewLSQFullEvents 8093737 # Number of times the LSQ has become full, causing a stall 539system.cpu.iew.memOrderViolationEvents 14483 # Number of memory order violations 540system.cpu.iew.predictedTakenIncorrect 519848 # Number of branches that were predicted taken incorrectly 541system.cpu.iew.predictedNotTakenIncorrect 541033 # Number of branches that were predicted not taken incorrectly 542system.cpu.iew.branchMispredicts 1060881 # Number of branch mispredicts detected at execute 543system.cpu.iew.iewExecutedInsts 822872781 # Number of executed instructions 544system.cpu.iew.iewExecLoadInsts 18039155 # Number of load instructions executed 545system.cpu.iew.iewExecSquashedInsts 1498773 # Number of squashed instructions skipped in execute | 527system.cpu.iew.iewSquashCycles 953327 # Number of cycles IEW is squashing 528system.cpu.iew.iewBlockCycles 205633916 # Number of cycles IEW is blocking 529system.cpu.iew.iewUnblockCycles 9395655 # Number of cycles IEW is unblocking 530system.cpu.iew.iewDispatchedInsts 831451180 # Number of instructions dispatched to IQ 531system.cpu.iew.iewDispSquashedInsts 157138 # Number of squashed instructions skipped by dispatch 532system.cpu.iew.iewDispLoadInsts 17396694 # Number of dispatched load instructions 533system.cpu.iew.iewDispStoreInsts 10208602 # Number of dispatched store instructions 534system.cpu.iew.iewDispNonSpecInsts 706837 # Number of dispatched non-speculative instructions 535system.cpu.iew.iewIQFullEvents 415978 # Number of times the IQ has become full, causing a stall 536system.cpu.iew.iewLSQFullEvents 8079838 # Number of times the LSQ has become full, causing a stall 537system.cpu.iew.memOrderViolationEvents 14595 # Number of memory order violations 538system.cpu.iew.predictedTakenIncorrect 523025 # Number of branches that were predicted taken incorrectly 539system.cpu.iew.predictedNotTakenIncorrect 540470 # Number of branches that were predicted not taken incorrectly 540system.cpu.iew.branchMispredicts 1063495 # Number of branch mispredicts detected at execute 541system.cpu.iew.iewExecutedInsts 823253062 # Number of executed instructions 542system.cpu.iew.iewExecLoadInsts 18064803 # Number of load instructions executed 543system.cpu.iew.iewExecSquashedInsts 1501922 # Number of squashed instructions skipped in execute |
| 546system.cpu.iew.exec_swp 0 # number of swp insts executed 547system.cpu.iew.exec_nop 0 # number of nop insts executed | 544system.cpu.iew.exec_swp 0 # number of swp insts executed 545system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 548system.cpu.iew.exec_refs 27216659 # number of memory reference insts executed 549system.cpu.iew.exec_branches 83327917 # Number of branches executed 550system.cpu.iew.exec_stores 9177504 # Number of stores executed 551system.cpu.iew.exec_rate 1.829721 # Inst execution rate 552system.cpu.iew.wb_sent 822362005 # cumulative count of insts sent to commit 553system.cpu.iew.wb_count 819923336 # cumulative count of insts written-back 554system.cpu.iew.wb_producers 641186937 # num instructions producing a value 555system.cpu.iew.wb_consumers 1050770759 # num instructions consuming a value | 546system.cpu.iew.exec_refs 27249763 # number of memory reference insts executed 547system.cpu.iew.exec_branches 83367725 # Number of branches executed 548system.cpu.iew.exec_stores 9184960 # Number of stores executed 549system.cpu.iew.exec_rate 1.830438 # Inst execution rate 550system.cpu.iew.wb_sent 822742058 # cumulative count of insts sent to commit 551system.cpu.iew.wb_count 820301688 # cumulative count of insts written-back 552system.cpu.iew.wb_producers 641478984 # num instructions producing a value 553system.cpu.iew.wb_consumers 1051241156 # num instructions consuming a value |
| 556system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 554system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 557system.cpu.iew.wb_rate 1.823163 # insts written-back per cycle 558system.cpu.iew.wb_fanout 0.610206 # average fanout of values written-back | 555system.cpu.iew.wb_rate 1.823876 # insts written-back per cycle 556system.cpu.iew.wb_fanout 0.610211 # average fanout of values written-back |
| 559system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 557system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 560system.cpu.commit.commitSquashedInsts 24478012 # The number of squashed insts skipped by commit 561system.cpu.commit.commitNonSpecStalls 1055940 # The number of times commit has been forced to stall to communicate backwards 562system.cpu.commit.branchMispredicts 920864 # The number of times a branch was mispredicted 563system.cpu.commit.committed_per_cycle::samples 443494014 # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::mean 1.818449 # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::stdev 2.675035 # Number of insts commited each cycle | 558system.cpu.commit.commitSquashedInsts 24588739 # The number of squashed insts skipped by commit 559system.cpu.commit.commitNonSpecStalls 1050938 # The number of times commit has been forced to stall to communicate backwards 560system.cpu.commit.branchMispredicts 921334 # The number of times a branch was mispredicted 561system.cpu.commit.committed_per_cycle::samples 443513076 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::mean 1.818961 # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::stdev 2.675251 # Number of insts commited each cycle |
| 566system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 564system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 567system.cpu.commit.committed_per_cycle::0 272650089 61.48% 61.48% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::1 11209358 2.53% 64.01% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::2 3583153 0.81% 64.81% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::3 74560256 16.81% 81.63% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::4 2436163 0.55% 82.17% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::5 1608243 0.36% 82.54% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::6 951229 0.21% 82.75% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::7 71042725 16.02% 98.77% # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::8 5452798 1.23% 100.00% # Number of insts commited each cycle | 565system.cpu.commit.committed_per_cycle::0 272623912 61.47% 61.47% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::1 11196719 2.52% 63.99% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::2 3582296 0.81% 64.80% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::3 74597527 16.82% 81.62% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::4 2432522 0.55% 82.17% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::5 1609310 0.36% 82.53% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::6 947533 0.21% 82.75% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::7 71068767 16.02% 98.77% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::8 5454490 1.23% 100.00% # Number of insts commited each cycle |
| 576system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 574system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 579system.cpu.commit.committed_per_cycle::total 443494014 # Number of insts commited each cycle 580system.cpu.commit.committedInsts 407987808 # Number of instructions committed 581system.cpu.commit.committedOps 806471132 # Number of ops (including micro ops) committed | 577system.cpu.commit.committed_per_cycle::total 443513076 # Number of insts commited each cycle 578system.cpu.commit.committedInsts 408140259 # Number of instructions committed 579system.cpu.commit.committedOps 806733017 # Number of ops (including micro ops) committed |
| 582system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 580system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 583system.cpu.commit.refs 22432051 # Number of memory references committed 584system.cpu.commit.loads 14002440 # Number of loads committed 585system.cpu.commit.membars 475347 # Number of memory barriers committed 586system.cpu.commit.branches 82201961 # Number of branches committed | 581system.cpu.commit.refs 22432033 # Number of memory references committed 582system.cpu.commit.loads 14002018 # Number of loads committed 583system.cpu.commit.membars 475437 # Number of memory barriers committed 584system.cpu.commit.branches 82233213 # Number of branches committed |
| 587system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 585system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 588system.cpu.commit.int_insts 735281139 # Number of committed integer instructions. 589system.cpu.commit.function_calls 1155976 # Number of function calls committed. 590system.cpu.commit.op_class_0::No_OpClass 174273 0.02% 0.02% # Class of committed instruction 591system.cpu.commit.op_class_0::IntAlu 783598184 97.16% 97.19% # Class of committed instruction 592system.cpu.commit.op_class_0::IntMult 145019 0.02% 97.20% # Class of committed instruction 593system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction | 586system.cpu.commit.int_insts 735520454 # Number of committed integer instructions. 587system.cpu.commit.function_calls 1156067 # Number of function calls committed. 588system.cpu.commit.op_class_0::No_OpClass 171671 0.02% 0.02% # Class of committed instruction 589system.cpu.commit.op_class_0::IntAlu 783865362 97.17% 97.19% # Class of committed instruction 590system.cpu.commit.op_class_0::IntMult 145082 0.02% 97.20% # Class of committed instruction 591system.cpu.commit.op_class_0::IntDiv 121451 0.02% 97.22% # Class of committed instruction |
| 594system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 596system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction 597system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 598system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 599system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction --- 10 unchanged lines hidden (view full) --- 612system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 617system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction | 592system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 593system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 596system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 597system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 598system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 599system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction --- 10 unchanged lines hidden (view full) --- 610system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 617system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction |
| 620system.cpu.commit.op_class_0::MemRead 14002440 1.74% 98.95% # Class of committed instruction 621system.cpu.commit.op_class_0::MemWrite 8429611 1.05% 100.00% # Class of committed instruction | 618system.cpu.commit.op_class_0::MemRead 13999436 1.74% 98.96% # Class of committed instruction 619system.cpu.commit.op_class_0::MemWrite 8430015 1.04% 100.00% # Class of committed instruction |
| 622system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 623system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 620system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 621system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 624system.cpu.commit.op_class_0::total 806471132 # Class of committed instruction 625system.cpu.commit.bw_lim_events 5452798 # number cycles where commit BW limit reached | 622system.cpu.commit.op_class_0::total 806733017 # Class of committed instruction 623system.cpu.commit.bw_lim_events 5454490 # number cycles where commit BW limit reached |
| 626system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 624system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 627system.cpu.rob.rob_reads 1268912158 # The number of ROB reads 628system.cpu.rob.rob_writes 1665595320 # The number of ROB writes 629system.cpu.timesIdled 297665 # Number of times that the entire CPU went into an idle state and unscheduled itself 630system.cpu.idleCycles 2551313 # Total number of cycles that the CPU has spent unscheduled due to idling 631system.cpu.quiesceCycles 9810160420 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 632system.cpu.committedInsts 407987808 # Number of Instructions Simulated 633system.cpu.committedOps 806471132 # Number of Ops (including micro ops) Simulated 634system.cpu.cpi 1.102302 # CPI: Cycles Per Instruction 635system.cpu.cpi_total 1.102302 # CPI: Total CPI of All Threads 636system.cpu.ipc 0.907192 # IPC: Instructions Per Cycle 637system.cpu.ipc_total 0.907192 # IPC: Total IPC of All Threads 638system.cpu.int_regfile_reads 1092777925 # number of integer regfile reads 639system.cpu.int_regfile_writes 656276714 # number of integer regfile writes 640system.cpu.fp_regfile_reads 50 # number of floating regfile reads 641system.cpu.cc_regfile_reads 416321461 # number of cc regfile reads 642system.cpu.cc_regfile_writes 322134346 # number of cc regfile writes 643system.cpu.misc_regfile_reads 265712042 # number of misc regfile reads 644system.cpu.misc_regfile_writes 402822 # number of misc regfile writes 645system.cpu.dcache.tags.replacements 1660901 # number of replacements 646system.cpu.dcache.tags.tagsinuse 511.996168 # Cycle average of tags in use 647system.cpu.dcache.tags.total_refs 19148306 # Total number of references to valid blocks. 648system.cpu.dcache.tags.sampled_refs 1661413 # Sample count of references to valid blocks. 649system.cpu.dcache.tags.avg_refs 11.525314 # Average number of references to valid blocks. | 625system.cpu.rob.rob_reads 1269302111 # The number of ROB reads 626system.cpu.rob.rob_writes 1666357608 # The number of ROB writes 627system.cpu.timesIdled 293383 # Number of times that the entire CPU went into an idle state and unscheduled itself 628system.cpu.idleCycles 2550075 # Total number of cycles that the CPU has spent unscheduled due to idling 629system.cpu.quiesceCycles 9802132382 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 630system.cpu.committedInsts 408140259 # Number of Instructions Simulated 631system.cpu.committedOps 806733017 # Number of Ops (including micro ops) Simulated 632system.cpu.cpi 1.101968 # CPI: Cycles Per Instruction 633system.cpu.cpi_total 1.101968 # CPI: Total CPI of All Threads 634system.cpu.ipc 0.907468 # IPC: Instructions Per Cycle 635system.cpu.ipc_total 0.907468 # IPC: Total IPC of All Threads 636system.cpu.int_regfile_reads 1093345902 # number of integer regfile reads 637system.cpu.int_regfile_writes 656583711 # number of integer regfile writes 638system.cpu.fp_regfile_reads 57 # number of floating regfile reads 639system.cpu.cc_regfile_reads 416569502 # number of cc regfile reads 640system.cpu.cc_regfile_writes 322266839 # number of cc regfile writes 641system.cpu.misc_regfile_reads 265844677 # number of misc regfile reads 642system.cpu.misc_regfile_writes 400270 # number of misc regfile writes 643system.cpu.dcache.tags.replacements 1661069 # number of replacements 644system.cpu.dcache.tags.tagsinuse 511.997995 # Cycle average of tags in use 645system.cpu.dcache.tags.total_refs 19180634 # Total number of references to valid blocks. 646system.cpu.dcache.tags.sampled_refs 1661581 # Sample count of references to valid blocks. 647system.cpu.dcache.tags.avg_refs 11.543605 # Average number of references to valid blocks. |
| 650system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. | 648system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. |
| 651system.cpu.dcache.tags.occ_blocks::cpu.data 511.996168 # Average occupied blocks per requestor 652system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy 653system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy | 649system.cpu.dcache.tags.occ_blocks::cpu.data 511.997995 # Average occupied blocks per requestor 650system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 651system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy |
| 654system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 652system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 655system.cpu.dcache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id 656system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id 657system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id | 653system.cpu.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id 654system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id 655system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id |
| 658system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 656system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 659system.cpu.dcache.tags.tag_accesses 88407170 # Number of tag accesses 660system.cpu.dcache.tags.data_accesses 88407170 # Number of data accesses 661system.cpu.dcache.ReadReq_hits::cpu.data 10993462 # number of ReadReq hits 662system.cpu.dcache.ReadReq_hits::total 10993462 # number of ReadReq hits 663system.cpu.dcache.WriteReq_hits::cpu.data 8086554 # number of WriteReq hits 664system.cpu.dcache.WriteReq_hits::total 8086554 # number of WriteReq hits 665system.cpu.dcache.SoftPFReq_hits::cpu.data 65615 # number of SoftPFReq hits 666system.cpu.dcache.SoftPFReq_hits::total 65615 # number of SoftPFReq hits 667system.cpu.dcache.demand_hits::cpu.data 19080016 # number of demand (read+write) hits 668system.cpu.dcache.demand_hits::total 19080016 # number of demand (read+write) hits 669system.cpu.dcache.overall_hits::cpu.data 19145631 # number of overall hits 670system.cpu.dcache.overall_hits::total 19145631 # number of overall hits 671system.cpu.dcache.ReadReq_misses::cpu.data 1801010 # number of ReadReq misses 672system.cpu.dcache.ReadReq_misses::total 1801010 # number of ReadReq misses 673system.cpu.dcache.WriteReq_misses::cpu.data 333393 # number of WriteReq misses 674system.cpu.dcache.WriteReq_misses::total 333393 # number of WriteReq misses 675system.cpu.dcache.SoftPFReq_misses::cpu.data 406403 # number of SoftPFReq misses 676system.cpu.dcache.SoftPFReq_misses::total 406403 # number of SoftPFReq misses 677system.cpu.dcache.demand_misses::cpu.data 2134403 # number of demand (read+write) misses 678system.cpu.dcache.demand_misses::total 2134403 # number of demand (read+write) misses 679system.cpu.dcache.overall_misses::cpu.data 2540806 # number of overall misses 680system.cpu.dcache.overall_misses::total 2540806 # number of overall misses 681system.cpu.dcache.ReadReq_miss_latency::cpu.data 26556774697 # number of ReadReq miss cycles 682system.cpu.dcache.ReadReq_miss_latency::total 26556774697 # number of ReadReq miss cycles 683system.cpu.dcache.WriteReq_miss_latency::cpu.data 12861853063 # number of WriteReq miss cycles 684system.cpu.dcache.WriteReq_miss_latency::total 12861853063 # number of WriteReq miss cycles 685system.cpu.dcache.demand_miss_latency::cpu.data 39418627760 # number of demand (read+write) miss cycles 686system.cpu.dcache.demand_miss_latency::total 39418627760 # number of demand (read+write) miss cycles 687system.cpu.dcache.overall_miss_latency::cpu.data 39418627760 # number of overall miss cycles 688system.cpu.dcache.overall_miss_latency::total 39418627760 # number of overall miss cycles 689system.cpu.dcache.ReadReq_accesses::cpu.data 12794472 # number of ReadReq accesses(hits+misses) 690system.cpu.dcache.ReadReq_accesses::total 12794472 # number of ReadReq accesses(hits+misses) 691system.cpu.dcache.WriteReq_accesses::cpu.data 8419947 # number of WriteReq accesses(hits+misses) 692system.cpu.dcache.WriteReq_accesses::total 8419947 # number of WriteReq accesses(hits+misses) 693system.cpu.dcache.SoftPFReq_accesses::cpu.data 472018 # number of SoftPFReq accesses(hits+misses) 694system.cpu.dcache.SoftPFReq_accesses::total 472018 # number of SoftPFReq accesses(hits+misses) 695system.cpu.dcache.demand_accesses::cpu.data 21214419 # number of demand (read+write) accesses 696system.cpu.dcache.demand_accesses::total 21214419 # number of demand (read+write) accesses 697system.cpu.dcache.overall_accesses::cpu.data 21686437 # number of overall (read+write) accesses 698system.cpu.dcache.overall_accesses::total 21686437 # number of overall (read+write) accesses 699system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140765 # miss rate for ReadReq accesses 700system.cpu.dcache.ReadReq_miss_rate::total 0.140765 # miss rate for ReadReq accesses 701system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039596 # miss rate for WriteReq accesses 702system.cpu.dcache.WriteReq_miss_rate::total 0.039596 # miss rate for WriteReq accesses 703system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.860990 # miss rate for SoftPFReq accesses 704system.cpu.dcache.SoftPFReq_miss_rate::total 0.860990 # miss rate for SoftPFReq accesses 705system.cpu.dcache.demand_miss_rate::cpu.data 0.100611 # miss rate for demand accesses 706system.cpu.dcache.demand_miss_rate::total 0.100611 # miss rate for demand accesses 707system.cpu.dcache.overall_miss_rate::cpu.data 0.117161 # miss rate for overall accesses 708system.cpu.dcache.overall_miss_rate::total 0.117161 # miss rate for overall accesses 709system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.489862 # average ReadReq miss latency 710system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.489862 # average ReadReq miss latency 711system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38578.653610 # average WriteReq miss latency 712system.cpu.dcache.WriteReq_avg_miss_latency::total 38578.653610 # average WriteReq miss latency 713system.cpu.dcache.demand_avg_miss_latency::cpu.data 18468.221681 # average overall miss latency 714system.cpu.dcache.demand_avg_miss_latency::total 18468.221681 # average overall miss latency 715system.cpu.dcache.overall_avg_miss_latency::cpu.data 15514.221771 # average overall miss latency 716system.cpu.dcache.overall_avg_miss_latency::total 15514.221771 # average overall miss latency 717system.cpu.dcache.blocked_cycles::no_mshrs 376585 # number of cycles access was blocked | 657system.cpu.dcache.tags.tag_accesses 88533012 # Number of tag accesses 658system.cpu.dcache.tags.data_accesses 88533012 # Number of data accesses 659system.cpu.dcache.ReadReq_hits::cpu.data 11025921 # number of ReadReq hits 660system.cpu.dcache.ReadReq_hits::total 11025921 # number of ReadReq hits 661system.cpu.dcache.WriteReq_hits::cpu.data 8086239 # number of WriteReq hits 662system.cpu.dcache.WriteReq_hits::total 8086239 # number of WriteReq hits 663system.cpu.dcache.SoftPFReq_hits::cpu.data 65769 # number of SoftPFReq hits 664system.cpu.dcache.SoftPFReq_hits::total 65769 # number of SoftPFReq hits 665system.cpu.dcache.demand_hits::cpu.data 19112160 # number of demand (read+write) hits 666system.cpu.dcache.demand_hits::total 19112160 # number of demand (read+write) hits 667system.cpu.dcache.overall_hits::cpu.data 19177929 # number of overall hits 668system.cpu.dcache.overall_hits::total 19177929 # number of overall hits 669system.cpu.dcache.ReadReq_misses::cpu.data 1799370 # number of ReadReq misses 670system.cpu.dcache.ReadReq_misses::total 1799370 # number of ReadReq misses 671system.cpu.dcache.WriteReq_misses::cpu.data 334097 # number of WriteReq misses 672system.cpu.dcache.WriteReq_misses::total 334097 # number of WriteReq misses 673system.cpu.dcache.SoftPFReq_misses::cpu.data 406460 # number of SoftPFReq misses 674system.cpu.dcache.SoftPFReq_misses::total 406460 # number of SoftPFReq misses 675system.cpu.dcache.demand_misses::cpu.data 2133467 # number of demand (read+write) misses 676system.cpu.dcache.demand_misses::total 2133467 # number of demand (read+write) misses 677system.cpu.dcache.overall_misses::cpu.data 2539927 # number of overall misses 678system.cpu.dcache.overall_misses::total 2539927 # number of overall misses 679system.cpu.dcache.ReadReq_miss_latency::cpu.data 26521555176 # number of ReadReq miss cycles 680system.cpu.dcache.ReadReq_miss_latency::total 26521555176 # number of ReadReq miss cycles 681system.cpu.dcache.WriteReq_miss_latency::cpu.data 12869537398 # number of WriteReq miss cycles 682system.cpu.dcache.WriteReq_miss_latency::total 12869537398 # number of WriteReq miss cycles 683system.cpu.dcache.demand_miss_latency::cpu.data 39391092574 # number of demand (read+write) miss cycles 684system.cpu.dcache.demand_miss_latency::total 39391092574 # number of demand (read+write) miss cycles 685system.cpu.dcache.overall_miss_latency::cpu.data 39391092574 # number of overall miss cycles 686system.cpu.dcache.overall_miss_latency::total 39391092574 # number of overall miss cycles 687system.cpu.dcache.ReadReq_accesses::cpu.data 12825291 # number of ReadReq accesses(hits+misses) 688system.cpu.dcache.ReadReq_accesses::total 12825291 # number of ReadReq accesses(hits+misses) 689system.cpu.dcache.WriteReq_accesses::cpu.data 8420336 # number of WriteReq accesses(hits+misses) 690system.cpu.dcache.WriteReq_accesses::total 8420336 # number of WriteReq accesses(hits+misses) 691system.cpu.dcache.SoftPFReq_accesses::cpu.data 472229 # number of SoftPFReq accesses(hits+misses) 692system.cpu.dcache.SoftPFReq_accesses::total 472229 # number of SoftPFReq accesses(hits+misses) 693system.cpu.dcache.demand_accesses::cpu.data 21245627 # number of demand (read+write) accesses 694system.cpu.dcache.demand_accesses::total 21245627 # number of demand (read+write) accesses 695system.cpu.dcache.overall_accesses::cpu.data 21717856 # number of overall (read+write) accesses 696system.cpu.dcache.overall_accesses::total 21717856 # number of overall (read+write) accesses 697system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140299 # miss rate for ReadReq accesses 698system.cpu.dcache.ReadReq_miss_rate::total 0.140299 # miss rate for ReadReq accesses 699system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039677 # miss rate for WriteReq accesses 700system.cpu.dcache.WriteReq_miss_rate::total 0.039677 # miss rate for WriteReq accesses 701system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.860726 # miss rate for SoftPFReq accesses 702system.cpu.dcache.SoftPFReq_miss_rate::total 0.860726 # miss rate for SoftPFReq accesses 703system.cpu.dcache.demand_miss_rate::cpu.data 0.100419 # miss rate for demand accesses 704system.cpu.dcache.demand_miss_rate::total 0.100419 # miss rate for demand accesses 705system.cpu.dcache.overall_miss_rate::cpu.data 0.116951 # miss rate for overall accesses 706system.cpu.dcache.overall_miss_rate::total 0.116951 # miss rate for overall accesses 707system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14739.356095 # average ReadReq miss latency 708system.cpu.dcache.ReadReq_avg_miss_latency::total 14739.356095 # average ReadReq miss latency 709system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38520.362045 # average WriteReq miss latency 710system.cpu.dcache.WriteReq_avg_miss_latency::total 38520.362045 # average WriteReq miss latency 711system.cpu.dcache.demand_avg_miss_latency::cpu.data 18463.417796 # average overall miss latency 712system.cpu.dcache.demand_avg_miss_latency::total 18463.417796 # average overall miss latency 713system.cpu.dcache.overall_avg_miss_latency::cpu.data 15508.749887 # average overall miss latency 714system.cpu.dcache.overall_avg_miss_latency::total 15508.749887 # average overall miss latency 715system.cpu.dcache.blocked_cycles::no_mshrs 376355 # number of cycles access was blocked |
| 718system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 716system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 719system.cpu.dcache.blocked::no_mshrs 40128 # number of cycles access was blocked | 717system.cpu.dcache.blocked::no_mshrs 40236 # number of cycles access was blocked |
| 720system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 718system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 721system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.384594 # average number of cycles each access was blocked | 719system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353688 # average number of cycles each access was blocked |
| 722system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.dcache.fast_writes 0 # number of fast writes performed 724system.cpu.dcache.cache_copies 0 # number of cache copies performed | 720system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 721system.cpu.dcache.fast_writes 0 # number of fast writes performed 722system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 725system.cpu.dcache.writebacks::writebacks 1561149 # number of writebacks 726system.cpu.dcache.writebacks::total 1561149 # number of writebacks 727system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829563 # number of ReadReq MSHR hits 728system.cpu.dcache.ReadReq_mshr_hits::total 829563 # number of ReadReq MSHR hits 729system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44151 # number of WriteReq MSHR hits 730system.cpu.dcache.WriteReq_mshr_hits::total 44151 # number of WriteReq MSHR hits 731system.cpu.dcache.demand_mshr_hits::cpu.data 873714 # number of demand (read+write) MSHR hits 732system.cpu.dcache.demand_mshr_hits::total 873714 # number of demand (read+write) MSHR hits 733system.cpu.dcache.overall_mshr_hits::cpu.data 873714 # number of overall MSHR hits 734system.cpu.dcache.overall_mshr_hits::total 873714 # number of overall MSHR hits 735system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971447 # number of ReadReq MSHR misses 736system.cpu.dcache.ReadReq_mshr_misses::total 971447 # number of ReadReq MSHR misses 737system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289242 # number of WriteReq MSHR misses 738system.cpu.dcache.WriteReq_mshr_misses::total 289242 # number of WriteReq MSHR misses 739system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402941 # number of SoftPFReq MSHR misses 740system.cpu.dcache.SoftPFReq_mshr_misses::total 402941 # number of SoftPFReq MSHR misses 741system.cpu.dcache.demand_mshr_misses::cpu.data 1260689 # number of demand (read+write) MSHR misses 742system.cpu.dcache.demand_mshr_misses::total 1260689 # number of demand (read+write) MSHR misses 743system.cpu.dcache.overall_mshr_misses::cpu.data 1663630 # number of overall MSHR misses 744system.cpu.dcache.overall_mshr_misses::total 1663630 # number of overall MSHR misses 745system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12263679766 # number of ReadReq MSHR miss cycles 746system.cpu.dcache.ReadReq_mshr_miss_latency::total 12263679766 # number of ReadReq MSHR miss cycles 747system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11196249664 # number of WriteReq MSHR miss cycles 748system.cpu.dcache.WriteReq_mshr_miss_latency::total 11196249664 # number of WriteReq MSHR miss cycles 749system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5590634504 # number of SoftPFReq MSHR miss cycles 750system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5590634504 # number of SoftPFReq MSHR miss cycles 751system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459929430 # number of demand (read+write) MSHR miss cycles 752system.cpu.dcache.demand_mshr_miss_latency::total 23459929430 # number of demand (read+write) MSHR miss cycles 753system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050563934 # number of overall MSHR miss cycles 754system.cpu.dcache.overall_mshr_miss_latency::total 29050563934 # number of overall MSHR miss cycles 755system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390328000 # number of ReadReq MSHR uncacheable cycles 756system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390328000 # number of ReadReq MSHR uncacheable cycles 757system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564382000 # number of WriteReq MSHR uncacheable cycles 758system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564382000 # number of WriteReq MSHR uncacheable cycles 759system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954710000 # number of overall MSHR uncacheable cycles 760system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954710000 # number of overall MSHR uncacheable cycles 761system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075927 # mshr miss rate for ReadReq accesses 762system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075927 # mshr miss rate for ReadReq accesses 763system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034352 # mshr miss rate for WriteReq accesses 764system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034352 # mshr miss rate for WriteReq accesses 765system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853656 # mshr miss rate for SoftPFReq accesses 766system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853656 # mshr miss rate for SoftPFReq accesses 767system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059426 # mshr miss rate for demand accesses 768system.cpu.dcache.demand_mshr_miss_rate::total 0.059426 # mshr miss rate for demand accesses 769system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076713 # mshr miss rate for overall accesses 770system.cpu.dcache.overall_mshr_miss_rate::total 0.076713 # mshr miss rate for overall accesses 771system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12624.136742 # average ReadReq mshr miss latency 772system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12624.136742 # average ReadReq mshr miss latency 773system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38708.934608 # average WriteReq mshr miss latency 774system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38708.934608 # average WriteReq mshr miss latency 775system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13874.573459 # average SoftPFReq mshr miss latency 776system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13874.573459 # average SoftPFReq mshr miss latency 777system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18608.815838 # average overall mshr miss latency 778system.cpu.dcache.demand_avg_mshr_miss_latency::total 18608.815838 # average overall mshr miss latency 779system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17462.154406 # average overall mshr miss latency 780system.cpu.dcache.overall_avg_mshr_miss_latency::total 17462.154406 # average overall mshr miss latency | 723system.cpu.dcache.writebacks::writebacks 1562436 # number of writebacks 724system.cpu.dcache.writebacks::total 1562436 # number of writebacks 725system.cpu.dcache.ReadReq_mshr_hits::cpu.data 828680 # number of ReadReq MSHR hits 726system.cpu.dcache.ReadReq_mshr_hits::total 828680 # number of ReadReq MSHR hits 727system.cpu.dcache.WriteReq_mshr_hits::cpu.data 43973 # number of WriteReq MSHR hits 728system.cpu.dcache.WriteReq_mshr_hits::total 43973 # number of WriteReq MSHR hits 729system.cpu.dcache.demand_mshr_hits::cpu.data 872653 # number of demand (read+write) MSHR hits 730system.cpu.dcache.demand_mshr_hits::total 872653 # number of demand (read+write) MSHR hits 731system.cpu.dcache.overall_mshr_hits::cpu.data 872653 # number of overall MSHR hits 732system.cpu.dcache.overall_mshr_hits::total 872653 # number of overall MSHR hits 733system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970690 # number of ReadReq MSHR misses 734system.cpu.dcache.ReadReq_mshr_misses::total 970690 # number of ReadReq MSHR misses 735system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290124 # number of WriteReq MSHR misses 736system.cpu.dcache.WriteReq_mshr_misses::total 290124 # number of WriteReq MSHR misses 737system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403005 # number of SoftPFReq MSHR misses 738system.cpu.dcache.SoftPFReq_mshr_misses::total 403005 # number of SoftPFReq MSHR misses 739system.cpu.dcache.demand_mshr_misses::cpu.data 1260814 # number of demand (read+write) MSHR misses 740system.cpu.dcache.demand_mshr_misses::total 1260814 # number of demand (read+write) MSHR misses 741system.cpu.dcache.overall_mshr_misses::cpu.data 1663819 # number of overall MSHR misses 742system.cpu.dcache.overall_mshr_misses::total 1663819 # number of overall MSHR misses 743system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12262338773 # number of ReadReq MSHR miss cycles 744system.cpu.dcache.ReadReq_mshr_miss_latency::total 12262338773 # number of ReadReq MSHR miss cycles 745system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11212126848 # number of WriteReq MSHR miss cycles 746system.cpu.dcache.WriteReq_mshr_miss_latency::total 11212126848 # number of WriteReq MSHR miss cycles 747system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584774002 # number of SoftPFReq MSHR miss cycles 748system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584774002 # number of SoftPFReq MSHR miss cycles 749system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23474465621 # number of demand (read+write) MSHR miss cycles 750system.cpu.dcache.demand_mshr_miss_latency::total 23474465621 # number of demand (read+write) MSHR miss cycles 751system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29059239623 # number of overall MSHR miss cycles 752system.cpu.dcache.overall_mshr_miss_latency::total 29059239623 # number of overall MSHR miss cycles 753system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97396245500 # number of ReadReq MSHR uncacheable cycles 754system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97396245500 # number of ReadReq MSHR uncacheable cycles 755system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2569003000 # number of WriteReq MSHR uncacheable cycles 756system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2569003000 # number of WriteReq MSHR uncacheable cycles 757system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99965248500 # number of overall MSHR uncacheable cycles 758system.cpu.dcache.overall_mshr_uncacheable_latency::total 99965248500 # number of overall MSHR uncacheable cycles 759system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075686 # mshr miss rate for ReadReq accesses 760system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075686 # mshr miss rate for ReadReq accesses 761system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034455 # mshr miss rate for WriteReq accesses 762system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034455 # mshr miss rate for WriteReq accesses 763system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853410 # mshr miss rate for SoftPFReq accesses 764system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853410 # mshr miss rate for SoftPFReq accesses 765system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059345 # mshr miss rate for demand accesses 766system.cpu.dcache.demand_mshr_miss_rate::total 0.059345 # mshr miss rate for demand accesses 767system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076611 # mshr miss rate for overall accesses 768system.cpu.dcache.overall_mshr_miss_rate::total 0.076611 # mshr miss rate for overall accesses 769system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12632.600287 # average ReadReq mshr miss latency 770system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12632.600287 # average ReadReq mshr miss latency 771system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38645.981884 # average WriteReq mshr miss latency 772system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38645.981884 # average WriteReq mshr miss latency 773system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13857.828072 # average SoftPFReq mshr miss latency 774system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13857.828072 # average SoftPFReq mshr miss latency 775system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18618.500128 # average overall mshr miss latency 776system.cpu.dcache.demand_avg_mshr_miss_latency::total 18618.500128 # average overall mshr miss latency 777system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17465.385131 # average overall mshr miss latency 778system.cpu.dcache.overall_avg_mshr_miss_latency::total 17465.385131 # average overall mshr miss latency |
| 781system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 782system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 783system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 784system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 785system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 786system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 787system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 779system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 780system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 781system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 782system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 783system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 784system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 785system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 788system.cpu.dtb_walker_cache.tags.replacements 74149 # number of replacements 789system.cpu.dtb_walker_cache.tags.tagsinuse 15.785870 # Cycle average of tags in use 790system.cpu.dtb_walker_cache.tags.total_refs 117599 # Total number of references to valid blocks. 791system.cpu.dtb_walker_cache.tags.sampled_refs 74165 # Sample count of references to valid blocks. 792system.cpu.dtb_walker_cache.tags.avg_refs 1.585640 # Average number of references to valid blocks. 793system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000 # Cycle when the warmup percentage was hit. 794system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785870 # Average occupied blocks per requestor 795system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986617 # Average percentage of cache occupancy 796system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986617 # Average percentage of cache occupancy 797system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id | 786system.cpu.dtb_walker_cache.tags.replacements 76914 # number of replacements 787system.cpu.dtb_walker_cache.tags.tagsinuse 15.799700 # Cycle average of tags in use 788system.cpu.dtb_walker_cache.tags.total_refs 113377 # Total number of references to valid blocks. 789system.cpu.dtb_walker_cache.tags.sampled_refs 76929 # Sample count of references to valid blocks. 790system.cpu.dtb_walker_cache.tags.avg_refs 1.473788 # Average number of references to valid blocks. 791system.cpu.dtb_walker_cache.tags.warmup_cycle 194539504500 # Cycle when the warmup percentage was hit. 792system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.799700 # Average occupied blocks per requestor 793system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.987481 # Average percentage of cache occupancy 794system.cpu.dtb_walker_cache.tags.occ_percent::total 0.987481 # Average percentage of cache occupancy 795system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id |
| 798system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id | 796system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id |
| 799system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id | 797system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id |
| 800system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id | 798system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id |
| 801system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 802system.cpu.dtb_walker_cache.tags.tag_accesses 460921 # Number of tag accesses 803system.cpu.dtb_walker_cache.tags.data_accesses 460921 # Number of data accesses 804system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117599 # number of ReadReq hits 805system.cpu.dtb_walker_cache.ReadReq_hits::total 117599 # number of ReadReq hits 806system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117599 # number of demand (read+write) hits 807system.cpu.dtb_walker_cache.demand_hits::total 117599 # number of demand (read+write) hits 808system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117599 # number of overall hits 809system.cpu.dtb_walker_cache.overall_hits::total 117599 # number of overall hits 810system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75241 # number of ReadReq misses 811system.cpu.dtb_walker_cache.ReadReq_misses::total 75241 # number of ReadReq misses 812system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75241 # number of demand (read+write) misses 813system.cpu.dtb_walker_cache.demand_misses::total 75241 # number of demand (read+write) misses 814system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75241 # number of overall misses 815system.cpu.dtb_walker_cache.overall_misses::total 75241 # number of overall misses 816system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935995702 # number of ReadReq miss cycles 817system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935995702 # number of ReadReq miss cycles 818system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935995702 # number of demand (read+write) miss cycles 819system.cpu.dtb_walker_cache.demand_miss_latency::total 935995702 # number of demand (read+write) miss cycles 820system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935995702 # number of overall miss cycles 821system.cpu.dtb_walker_cache.overall_miss_latency::total 935995702 # number of overall miss cycles 822system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192840 # number of ReadReq accesses(hits+misses) 823system.cpu.dtb_walker_cache.ReadReq_accesses::total 192840 # number of ReadReq accesses(hits+misses) 824system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192840 # number of demand (read+write) accesses 825system.cpu.dtb_walker_cache.demand_accesses::total 192840 # number of demand (read+write) accesses 826system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192840 # number of overall (read+write) accesses 827system.cpu.dtb_walker_cache.overall_accesses::total 192840 # number of overall (read+write) accesses 828system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.390173 # miss rate for ReadReq accesses 829system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.390173 # miss rate for ReadReq accesses 830system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.390173 # miss rate for demand accesses 831system.cpu.dtb_walker_cache.demand_miss_rate::total 0.390173 # miss rate for demand accesses 832system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.390173 # miss rate for overall accesses 833system.cpu.dtb_walker_cache.overall_miss_rate::total 0.390173 # miss rate for overall accesses 834system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12439.968927 # average ReadReq miss latency 835system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12439.968927 # average ReadReq miss latency 836system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency 837system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12439.968927 # average overall miss latency 838system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency 839system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12439.968927 # average overall miss latency | 799system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 800system.cpu.dtb_walker_cache.tags.tag_accesses 460761 # Number of tag accesses 801system.cpu.dtb_walker_cache.tags.data_accesses 460761 # Number of data accesses 802system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113400 # number of ReadReq hits 803system.cpu.dtb_walker_cache.ReadReq_hits::total 113400 # number of ReadReq hits 804system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113400 # number of demand (read+write) hits 805system.cpu.dtb_walker_cache.demand_hits::total 113400 # number of demand (read+write) hits 806system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113400 # number of overall hits 807system.cpu.dtb_walker_cache.overall_hits::total 113400 # number of overall hits 808system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77987 # number of ReadReq misses 809system.cpu.dtb_walker_cache.ReadReq_misses::total 77987 # number of ReadReq misses 810system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77987 # number of demand (read+write) misses 811system.cpu.dtb_walker_cache.demand_misses::total 77987 # number of demand (read+write) misses 812system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77987 # number of overall misses 813system.cpu.dtb_walker_cache.overall_misses::total 77987 # number of overall misses 814system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 949066206 # number of ReadReq miss cycles 815system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 949066206 # number of ReadReq miss cycles 816system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 949066206 # number of demand (read+write) miss cycles 817system.cpu.dtb_walker_cache.demand_miss_latency::total 949066206 # number of demand (read+write) miss cycles 818system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 949066206 # number of overall miss cycles 819system.cpu.dtb_walker_cache.overall_miss_latency::total 949066206 # number of overall miss cycles 820system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191387 # number of ReadReq accesses(hits+misses) 821system.cpu.dtb_walker_cache.ReadReq_accesses::total 191387 # number of ReadReq accesses(hits+misses) 822system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191387 # number of demand (read+write) accesses 823system.cpu.dtb_walker_cache.demand_accesses::total 191387 # number of demand (read+write) accesses 824system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191387 # number of overall (read+write) accesses 825system.cpu.dtb_walker_cache.overall_accesses::total 191387 # number of overall (read+write) accesses 826system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407483 # miss rate for ReadReq accesses 827system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407483 # miss rate for ReadReq accesses 828system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407483 # miss rate for demand accesses 829system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407483 # miss rate for demand accesses 830system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407483 # miss rate for overall accesses 831system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407483 # miss rate for overall accesses 832system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12169.543719 # average ReadReq miss latency 833system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12169.543719 # average ReadReq miss latency 834system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency 835system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12169.543719 # average overall miss latency 836system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency 837system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12169.543719 # average overall miss latency |
| 840system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 841system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 842system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 843system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 844system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 845system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 846system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 847system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 838system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 839system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 840system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 841system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 842system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 843system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 844system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 845system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 848system.cpu.dtb_walker_cache.writebacks::writebacks 14429 # number of writebacks 849system.cpu.dtb_walker_cache.writebacks::total 14429 # number of writebacks 850system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75241 # number of ReadReq MSHR misses 851system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75241 # number of ReadReq MSHR misses 852system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75241 # number of demand (read+write) MSHR misses 853system.cpu.dtb_walker_cache.demand_mshr_misses::total 75241 # number of demand (read+write) MSHR misses 854system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75241 # number of overall MSHR misses 855system.cpu.dtb_walker_cache.overall_mshr_misses::total 75241 # number of overall MSHR misses 856system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 785378468 # number of ReadReq MSHR miss cycles 857system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 785378468 # number of ReadReq MSHR miss cycles 858system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 785378468 # number of demand (read+write) MSHR miss cycles 859system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 785378468 # number of demand (read+write) MSHR miss cycles 860system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 785378468 # number of overall MSHR miss cycles 861system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 785378468 # number of overall MSHR miss cycles 862system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for ReadReq accesses 863system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.390173 # mshr miss rate for ReadReq accesses 864system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for demand accesses 865system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.390173 # mshr miss rate for demand accesses 866system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for overall accesses 867system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.390173 # mshr miss rate for overall accesses 868system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average ReadReq mshr miss latency 869system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10438.171582 # average ReadReq mshr miss latency 870system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency 871system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency 872system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency 873system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency | 846system.cpu.dtb_walker_cache.writebacks::writebacks 21202 # number of writebacks 847system.cpu.dtb_walker_cache.writebacks::total 21202 # number of writebacks 848system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77987 # number of ReadReq MSHR misses 849system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77987 # number of ReadReq MSHR misses 850system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77987 # number of demand (read+write) MSHR misses 851system.cpu.dtb_walker_cache.demand_mshr_misses::total 77987 # number of demand (read+write) MSHR misses 852system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77987 # number of overall MSHR misses 853system.cpu.dtb_walker_cache.overall_mshr_misses::total 77987 # number of overall MSHR misses 854system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 792970936 # number of ReadReq MSHR miss cycles 855system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 792970936 # number of ReadReq MSHR miss cycles 856system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 792970936 # number of demand (read+write) MSHR miss cycles 857system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 792970936 # number of demand (read+write) MSHR miss cycles 858system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 792970936 # number of overall MSHR miss cycles 859system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 792970936 # number of overall MSHR miss cycles 860system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for ReadReq accesses 861system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407483 # mshr miss rate for ReadReq accesses 862system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for demand accesses 863system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407483 # mshr miss rate for demand accesses 864system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for overall accesses 865system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407483 # mshr miss rate for overall accesses 866system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average ReadReq mshr miss latency 867system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10167.988716 # average ReadReq mshr miss latency 868system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency 869system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency 870system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency 871system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency |
| 874system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 872system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 875system.cpu.icache.tags.replacements 1000738 # number of replacements 876system.cpu.icache.tags.tagsinuse 509.865289 # Cycle average of tags in use 877system.cpu.icache.tags.total_refs 8144093 # Total number of references to valid blocks. 878system.cpu.icache.tags.sampled_refs 1001250 # Sample count of references to valid blocks. 879system.cpu.icache.tags.avg_refs 8.133926 # Average number of references to valid blocks. 880system.cpu.icache.tags.warmup_cycle 147645528250 # Cycle when the warmup percentage was hit. 881system.cpu.icache.tags.occ_blocks::cpu.inst 509.865289 # Average occupied blocks per requestor 882system.cpu.icache.tags.occ_percent::cpu.inst 0.995831 # Average percentage of cache occupancy 883system.cpu.icache.tags.occ_percent::total 0.995831 # Average percentage of cache occupancy | 873system.cpu.icache.tags.replacements 998047 # number of replacements 874system.cpu.icache.tags.tagsinuse 509.614894 # Cycle average of tags in use 875system.cpu.icache.tags.total_refs 8172291 # Total number of references to valid blocks. 876system.cpu.icache.tags.sampled_refs 998559 # Sample count of references to valid blocks. 877system.cpu.icache.tags.avg_refs 8.184084 # Average number of references to valid blocks. 878system.cpu.icache.tags.warmup_cycle 147683889250 # Cycle when the warmup percentage was hit. 879system.cpu.icache.tags.occ_blocks::cpu.inst 509.614894 # Average occupied blocks per requestor 880system.cpu.icache.tags.occ_percent::cpu.inst 0.995342 # Average percentage of cache occupancy 881system.cpu.icache.tags.occ_percent::total 0.995342 # Average percentage of cache occupancy |
| 884system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 882system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 885system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 886system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id | 883system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 884system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id |
| 887system.cpu.icache.tags.age_task_id_blocks_1024::2 178 # Occupied blocks per task id 888system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 885system.cpu.icache.tags.age_task_id_blocks_1024::2 178 # Occupied blocks per task id 886system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 889system.cpu.icache.tags.tag_accesses 10211253 # Number of tag accesses 890system.cpu.icache.tags.data_accesses 10211253 # Number of data accesses 891system.cpu.icache.ReadReq_hits::cpu.inst 8144093 # number of ReadReq hits 892system.cpu.icache.ReadReq_hits::total 8144093 # number of ReadReq hits 893system.cpu.icache.demand_hits::cpu.inst 8144093 # number of demand (read+write) hits 894system.cpu.icache.demand_hits::total 8144093 # number of demand (read+write) hits 895system.cpu.icache.overall_hits::cpu.inst 8144093 # number of overall hits 896system.cpu.icache.overall_hits::total 8144093 # number of overall hits 897system.cpu.icache.ReadReq_misses::cpu.inst 1065861 # number of ReadReq misses 898system.cpu.icache.ReadReq_misses::total 1065861 # number of ReadReq misses 899system.cpu.icache.demand_misses::cpu.inst 1065861 # number of demand (read+write) misses 900system.cpu.icache.demand_misses::total 1065861 # number of demand (read+write) misses 901system.cpu.icache.overall_misses::cpu.inst 1065861 # number of overall misses 902system.cpu.icache.overall_misses::total 1065861 # number of overall misses 903system.cpu.icache.ReadReq_miss_latency::cpu.inst 14781190073 # number of ReadReq miss cycles 904system.cpu.icache.ReadReq_miss_latency::total 14781190073 # number of ReadReq miss cycles 905system.cpu.icache.demand_miss_latency::cpu.inst 14781190073 # number of demand (read+write) miss cycles 906system.cpu.icache.demand_miss_latency::total 14781190073 # number of demand (read+write) miss cycles 907system.cpu.icache.overall_miss_latency::cpu.inst 14781190073 # number of overall miss cycles 908system.cpu.icache.overall_miss_latency::total 14781190073 # number of overall miss cycles 909system.cpu.icache.ReadReq_accesses::cpu.inst 9209954 # number of ReadReq accesses(hits+misses) 910system.cpu.icache.ReadReq_accesses::total 9209954 # number of ReadReq accesses(hits+misses) 911system.cpu.icache.demand_accesses::cpu.inst 9209954 # number of demand (read+write) accesses 912system.cpu.icache.demand_accesses::total 9209954 # number of demand (read+write) accesses 913system.cpu.icache.overall_accesses::cpu.inst 9209954 # number of overall (read+write) accesses 914system.cpu.icache.overall_accesses::total 9209954 # number of overall (read+write) accesses 915system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115729 # miss rate for ReadReq accesses 916system.cpu.icache.ReadReq_miss_rate::total 0.115729 # miss rate for ReadReq accesses 917system.cpu.icache.demand_miss_rate::cpu.inst 0.115729 # miss rate for demand accesses 918system.cpu.icache.demand_miss_rate::total 0.115729 # miss rate for demand accesses 919system.cpu.icache.overall_miss_rate::cpu.inst 0.115729 # miss rate for overall accesses 920system.cpu.icache.overall_miss_rate::total 0.115729 # miss rate for overall accesses 921system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13867.840247 # average ReadReq miss latency 922system.cpu.icache.ReadReq_avg_miss_latency::total 13867.840247 # average ReadReq miss latency 923system.cpu.icache.demand_avg_miss_latency::cpu.inst 13867.840247 # average overall miss latency 924system.cpu.icache.demand_avg_miss_latency::total 13867.840247 # average overall miss latency 925system.cpu.icache.overall_avg_miss_latency::cpu.inst 13867.840247 # average overall miss latency 926system.cpu.icache.overall_avg_miss_latency::total 13867.840247 # average overall miss latency 927system.cpu.icache.blocked_cycles::no_mshrs 8856 # number of cycles access was blocked | 887system.cpu.icache.tags.tag_accesses 10232340 # Number of tag accesses 888system.cpu.icache.tags.data_accesses 10232340 # Number of data accesses 889system.cpu.icache.ReadReq_hits::cpu.inst 8172291 # number of ReadReq hits 890system.cpu.icache.ReadReq_hits::total 8172291 # number of ReadReq hits 891system.cpu.icache.demand_hits::cpu.inst 8172291 # number of demand (read+write) hits 892system.cpu.icache.demand_hits::total 8172291 # number of demand (read+write) hits 893system.cpu.icache.overall_hits::cpu.inst 8172291 # number of overall hits 894system.cpu.icache.overall_hits::total 8172291 # number of overall hits 895system.cpu.icache.ReadReq_misses::cpu.inst 1061429 # number of ReadReq misses 896system.cpu.icache.ReadReq_misses::total 1061429 # number of ReadReq misses 897system.cpu.icache.demand_misses::cpu.inst 1061429 # number of demand (read+write) misses 898system.cpu.icache.demand_misses::total 1061429 # number of demand (read+write) misses 899system.cpu.icache.overall_misses::cpu.inst 1061429 # number of overall misses 900system.cpu.icache.overall_misses::total 1061429 # number of overall misses 901system.cpu.icache.ReadReq_miss_latency::cpu.inst 14726887378 # number of ReadReq miss cycles 902system.cpu.icache.ReadReq_miss_latency::total 14726887378 # number of ReadReq miss cycles 903system.cpu.icache.demand_miss_latency::cpu.inst 14726887378 # number of demand (read+write) miss cycles 904system.cpu.icache.demand_miss_latency::total 14726887378 # number of demand (read+write) miss cycles 905system.cpu.icache.overall_miss_latency::cpu.inst 14726887378 # number of overall miss cycles 906system.cpu.icache.overall_miss_latency::total 14726887378 # number of overall miss cycles 907system.cpu.icache.ReadReq_accesses::cpu.inst 9233720 # number of ReadReq accesses(hits+misses) 908system.cpu.icache.ReadReq_accesses::total 9233720 # number of ReadReq accesses(hits+misses) 909system.cpu.icache.demand_accesses::cpu.inst 9233720 # number of demand (read+write) accesses 910system.cpu.icache.demand_accesses::total 9233720 # number of demand (read+write) accesses 911system.cpu.icache.overall_accesses::cpu.inst 9233720 # number of overall (read+write) accesses 912system.cpu.icache.overall_accesses::total 9233720 # number of overall (read+write) accesses 913system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.114951 # miss rate for ReadReq accesses 914system.cpu.icache.ReadReq_miss_rate::total 0.114951 # miss rate for ReadReq accesses 915system.cpu.icache.demand_miss_rate::cpu.inst 0.114951 # miss rate for demand accesses 916system.cpu.icache.demand_miss_rate::total 0.114951 # miss rate for demand accesses 917system.cpu.icache.overall_miss_rate::cpu.inst 0.114951 # miss rate for overall accesses 918system.cpu.icache.overall_miss_rate::total 0.114951 # miss rate for overall accesses 919system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13874.585467 # average ReadReq miss latency 920system.cpu.icache.ReadReq_avg_miss_latency::total 13874.585467 # average ReadReq miss latency 921system.cpu.icache.demand_avg_miss_latency::cpu.inst 13874.585467 # average overall miss latency 922system.cpu.icache.demand_avg_miss_latency::total 13874.585467 # average overall miss latency 923system.cpu.icache.overall_avg_miss_latency::cpu.inst 13874.585467 # average overall miss latency 924system.cpu.icache.overall_avg_miss_latency::total 13874.585467 # average overall miss latency 925system.cpu.icache.blocked_cycles::no_mshrs 7528 # number of cycles access was blocked |
| 928system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 926system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 929system.cpu.icache.blocked::no_mshrs 270 # number of cycles access was blocked | 927system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked |
| 930system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 928system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 931system.cpu.icache.avg_blocked_cycles::no_mshrs 32.800000 # average number of cycles each access was blocked | 929system.cpu.icache.avg_blocked_cycles::no_mshrs 23.974522 # average number of cycles each access was blocked |
| 932system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 933system.cpu.icache.fast_writes 0 # number of fast writes performed 934system.cpu.icache.cache_copies 0 # number of cache copies performed | 930system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 931system.cpu.icache.fast_writes 0 # number of fast writes performed 932system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 935system.cpu.icache.ReadReq_mshr_hits::cpu.inst 64562 # number of ReadReq MSHR hits 936system.cpu.icache.ReadReq_mshr_hits::total 64562 # number of ReadReq MSHR hits 937system.cpu.icache.demand_mshr_hits::cpu.inst 64562 # number of demand (read+write) MSHR hits 938system.cpu.icache.demand_mshr_hits::total 64562 # number of demand (read+write) MSHR hits 939system.cpu.icache.overall_mshr_hits::cpu.inst 64562 # number of overall MSHR hits 940system.cpu.icache.overall_mshr_hits::total 64562 # number of overall MSHR hits 941system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001299 # number of ReadReq MSHR misses 942system.cpu.icache.ReadReq_mshr_misses::total 1001299 # number of ReadReq MSHR misses 943system.cpu.icache.demand_mshr_misses::cpu.inst 1001299 # number of demand (read+write) MSHR misses 944system.cpu.icache.demand_mshr_misses::total 1001299 # number of demand (read+write) MSHR misses 945system.cpu.icache.overall_mshr_misses::cpu.inst 1001299 # number of overall MSHR misses 946system.cpu.icache.overall_mshr_misses::total 1001299 # number of overall MSHR misses 947system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12129331538 # number of ReadReq MSHR miss cycles 948system.cpu.icache.ReadReq_mshr_miss_latency::total 12129331538 # number of ReadReq MSHR miss cycles 949system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12129331538 # number of demand (read+write) MSHR miss cycles 950system.cpu.icache.demand_mshr_miss_latency::total 12129331538 # number of demand (read+write) MSHR miss cycles 951system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12129331538 # number of overall MSHR miss cycles 952system.cpu.icache.overall_mshr_miss_latency::total 12129331538 # number of overall MSHR miss cycles 953system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for ReadReq accesses 954system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108719 # mshr miss rate for ReadReq accesses 955system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for demand accesses 956system.cpu.icache.demand_mshr_miss_rate::total 0.108719 # mshr miss rate for demand accesses 957system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for overall accesses 958system.cpu.icache.overall_mshr_miss_rate::total 0.108719 # mshr miss rate for overall accesses 959system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.595977 # average ReadReq mshr miss latency 960system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.595977 # average ReadReq mshr miss latency 961system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency 962system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency 963system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency 964system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency | 933system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62809 # number of ReadReq MSHR hits 934system.cpu.icache.ReadReq_mshr_hits::total 62809 # number of ReadReq MSHR hits 935system.cpu.icache.demand_mshr_hits::cpu.inst 62809 # number of demand (read+write) MSHR hits 936system.cpu.icache.demand_mshr_hits::total 62809 # number of demand (read+write) MSHR hits 937system.cpu.icache.overall_mshr_hits::cpu.inst 62809 # number of overall MSHR hits 938system.cpu.icache.overall_mshr_hits::total 62809 # number of overall MSHR hits 939system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998620 # number of ReadReq MSHR misses 940system.cpu.icache.ReadReq_mshr_misses::total 998620 # number of ReadReq MSHR misses 941system.cpu.icache.demand_mshr_misses::cpu.inst 998620 # number of demand (read+write) MSHR misses 942system.cpu.icache.demand_mshr_misses::total 998620 # number of demand (read+write) MSHR misses 943system.cpu.icache.overall_mshr_misses::cpu.inst 998620 # number of overall MSHR misses 944system.cpu.icache.overall_mshr_misses::total 998620 # number of overall MSHR misses 945system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12093795712 # number of ReadReq MSHR miss cycles 946system.cpu.icache.ReadReq_mshr_miss_latency::total 12093795712 # number of ReadReq MSHR miss cycles 947system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12093795712 # number of demand (read+write) MSHR miss cycles 948system.cpu.icache.demand_mshr_miss_latency::total 12093795712 # number of demand (read+write) MSHR miss cycles 949system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12093795712 # number of overall MSHR miss cycles 950system.cpu.icache.overall_mshr_miss_latency::total 12093795712 # number of overall MSHR miss cycles 951system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for ReadReq accesses 952system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108149 # mshr miss rate for ReadReq accesses 953system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for demand accesses 954system.cpu.icache.demand_mshr_miss_rate::total 0.108149 # mshr miss rate for demand accesses 955system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for overall accesses 956system.cpu.icache.overall_mshr_miss_rate::total 0.108149 # mshr miss rate for overall accesses 957system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.508213 # average ReadReq mshr miss latency 958system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.508213 # average ReadReq mshr miss latency 959system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.508213 # average overall mshr miss latency 960system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.508213 # average overall mshr miss latency 961system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.508213 # average overall mshr miss latency 962system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.508213 # average overall mshr miss latency |
| 965system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 963system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 966system.cpu.itb_walker_cache.tags.replacements 16111 # number of replacements 967system.cpu.itb_walker_cache.tags.tagsinuse 6.022557 # Cycle average of tags in use 968system.cpu.itb_walker_cache.tags.total_refs 25852 # Total number of references to valid blocks. 969system.cpu.itb_walker_cache.tags.sampled_refs 16125 # Sample count of references to valid blocks. 970system.cpu.itb_walker_cache.tags.avg_refs 1.603225 # Average number of references to valid blocks. 971system.cpu.itb_walker_cache.tags.warmup_cycle 5103942671000 # Cycle when the warmup percentage was hit. 972system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.022557 # Average occupied blocks per requestor 973system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376410 # Average percentage of cache occupancy 974system.cpu.itb_walker_cache.tags.occ_percent::total 0.376410 # Average percentage of cache occupancy | 964system.cpu.itb_walker_cache.tags.replacements 15839 # number of replacements 965system.cpu.itb_walker_cache.tags.tagsinuse 6.015286 # Cycle average of tags in use 966system.cpu.itb_walker_cache.tags.total_refs 25359 # Total number of references to valid blocks. 967system.cpu.itb_walker_cache.tags.sampled_refs 15853 # Sample count of references to valid blocks. 968system.cpu.itb_walker_cache.tags.avg_refs 1.599634 # Average number of references to valid blocks. 969system.cpu.itb_walker_cache.tags.warmup_cycle 5101686667000 # Cycle when the warmup percentage was hit. 970system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.015286 # Average occupied blocks per requestor 971system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375955 # Average percentage of cache occupancy 972system.cpu.itb_walker_cache.tags.occ_percent::total 0.375955 # Average percentage of cache occupancy |
| 975system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id | 973system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id |
| 976system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 977system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id | 974system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 975system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id |
| 978system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 979system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id | 976system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 977system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id |
| 980system.cpu.itb_walker_cache.tags.tag_accesses 102724 # Number of tag accesses 981system.cpu.itb_walker_cache.tags.data_accesses 102724 # Number of data accesses 982system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25863 # number of ReadReq hits 983system.cpu.itb_walker_cache.ReadReq_hits::total 25863 # number of ReadReq hits | 978system.cpu.itb_walker_cache.tags.tag_accesses 101130 # Number of tag accesses 979system.cpu.itb_walker_cache.tags.data_accesses 101130 # Number of data accesses 980system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25498 # number of ReadReq hits 981system.cpu.itb_walker_cache.ReadReq_hits::total 25498 # number of ReadReq hits |
| 984system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 985system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 982system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 983system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 986system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25865 # number of demand (read+write) hits 987system.cpu.itb_walker_cache.demand_hits::total 25865 # number of demand (read+write) hits 988system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25865 # number of overall hits 989system.cpu.itb_walker_cache.overall_hits::total 25865 # number of overall hits 990system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16998 # number of ReadReq misses 991system.cpu.itb_walker_cache.ReadReq_misses::total 16998 # number of ReadReq misses 992system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16998 # number of demand (read+write) misses 993system.cpu.itb_walker_cache.demand_misses::total 16998 # number of demand (read+write) misses 994system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16998 # number of overall misses 995system.cpu.itb_walker_cache.overall_misses::total 16998 # number of overall misses 996system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 202038998 # number of ReadReq miss cycles 997system.cpu.itb_walker_cache.ReadReq_miss_latency::total 202038998 # number of ReadReq miss cycles 998system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 202038998 # number of demand (read+write) miss cycles 999system.cpu.itb_walker_cache.demand_miss_latency::total 202038998 # number of demand (read+write) miss cycles 1000system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 202038998 # number of overall miss cycles 1001system.cpu.itb_walker_cache.overall_miss_latency::total 202038998 # number of overall miss cycles 1002system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42861 # number of ReadReq accesses(hits+misses) 1003system.cpu.itb_walker_cache.ReadReq_accesses::total 42861 # number of ReadReq accesses(hits+misses) | 984system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25500 # number of demand (read+write) hits 985system.cpu.itb_walker_cache.demand_hits::total 25500 # number of demand (read+write) hits 986system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25500 # number of overall hits 987system.cpu.itb_walker_cache.overall_hits::total 25500 # number of overall hits 988system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16710 # number of ReadReq misses 989system.cpu.itb_walker_cache.ReadReq_misses::total 16710 # number of ReadReq misses 990system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16710 # number of demand (read+write) misses 991system.cpu.itb_walker_cache.demand_misses::total 16710 # number of demand (read+write) misses 992system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16710 # number of overall misses 993system.cpu.itb_walker_cache.overall_misses::total 16710 # number of overall misses 994system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 189443244 # number of ReadReq miss cycles 995system.cpu.itb_walker_cache.ReadReq_miss_latency::total 189443244 # number of ReadReq miss cycles 996system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 189443244 # number of demand (read+write) miss cycles 997system.cpu.itb_walker_cache.demand_miss_latency::total 189443244 # number of demand (read+write) miss cycles 998system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 189443244 # number of overall miss cycles 999system.cpu.itb_walker_cache.overall_miss_latency::total 189443244 # number of overall miss cycles 1000system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42208 # number of ReadReq accesses(hits+misses) 1001system.cpu.itb_walker_cache.ReadReq_accesses::total 42208 # number of ReadReq accesses(hits+misses) |
| 1004system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1005system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 1002system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1003system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 1006system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42863 # number of demand (read+write) accesses 1007system.cpu.itb_walker_cache.demand_accesses::total 42863 # number of demand (read+write) accesses 1008system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42863 # number of overall (read+write) accesses 1009system.cpu.itb_walker_cache.overall_accesses::total 42863 # number of overall (read+write) accesses 1010system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.396584 # miss rate for ReadReq accesses 1011system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.396584 # miss rate for ReadReq accesses 1012system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.396566 # miss rate for demand accesses 1013system.cpu.itb_walker_cache.demand_miss_rate::total 0.396566 # miss rate for demand accesses 1014system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.396566 # miss rate for overall accesses 1015system.cpu.itb_walker_cache.overall_miss_rate::total 0.396566 # miss rate for overall accesses 1016system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11886.045299 # average ReadReq miss latency 1017system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11886.045299 # average ReadReq miss latency 1018system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11886.045299 # average overall miss latency 1019system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11886.045299 # average overall miss latency 1020system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11886.045299 # average overall miss latency 1021system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11886.045299 # average overall miss latency | 1004system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42210 # number of demand (read+write) accesses 1005system.cpu.itb_walker_cache.demand_accesses::total 42210 # number of demand (read+write) accesses 1006system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42210 # number of overall (read+write) accesses 1007system.cpu.itb_walker_cache.overall_accesses::total 42210 # number of overall (read+write) accesses 1008system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.395897 # miss rate for ReadReq accesses 1009system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.395897 # miss rate for ReadReq accesses 1010system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.395878 # miss rate for demand accesses 1011system.cpu.itb_walker_cache.demand_miss_rate::total 0.395878 # miss rate for demand accesses 1012system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.395878 # miss rate for overall accesses 1013system.cpu.itb_walker_cache.overall_miss_rate::total 0.395878 # miss rate for overall accesses 1014system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11337.118133 # average ReadReq miss latency 1015system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11337.118133 # average ReadReq miss latency 1016system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11337.118133 # average overall miss latency 1017system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11337.118133 # average overall miss latency 1018system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11337.118133 # average overall miss latency 1019system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11337.118133 # average overall miss latency |
| 1022system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1023system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1024system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1025system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1026system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1027system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1028system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1029system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 1020system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1021system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1022system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1023system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1024system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1025system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1026system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1027system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1030system.cpu.itb_walker_cache.writebacks::writebacks 2256 # number of writebacks 1031system.cpu.itb_walker_cache.writebacks::total 2256 # number of writebacks 1032system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16998 # number of ReadReq MSHR misses 1033system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16998 # number of ReadReq MSHR misses 1034system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16998 # number of demand (read+write) MSHR misses 1035system.cpu.itb_walker_cache.demand_mshr_misses::total 16998 # number of demand (read+write) MSHR misses 1036system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16998 # number of overall MSHR misses 1037system.cpu.itb_walker_cache.overall_mshr_misses::total 16998 # number of overall MSHR misses 1038system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 168025032 # number of ReadReq MSHR miss cycles 1039system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 168025032 # number of ReadReq MSHR miss cycles 1040system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 168025032 # number of demand (read+write) MSHR miss cycles 1041system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 168025032 # number of demand (read+write) MSHR miss cycles 1042system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 168025032 # number of overall MSHR miss cycles 1043system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 168025032 # number of overall MSHR miss cycles 1044system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.396584 # mshr miss rate for ReadReq accesses 1045system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.396584 # mshr miss rate for ReadReq accesses 1046system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for demand accesses 1047system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.396566 # mshr miss rate for demand accesses 1048system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for overall accesses 1049system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.396566 # mshr miss rate for overall accesses 1050system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average ReadReq mshr miss latency 1051system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9884.988352 # average ReadReq mshr miss latency 1052system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency 1053system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency 1054system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency 1055system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency | 1028system.cpu.itb_walker_cache.writebacks::writebacks 3245 # number of writebacks 1029system.cpu.itb_walker_cache.writebacks::total 3245 # number of writebacks 1030system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16710 # number of ReadReq MSHR misses 1031system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16710 # number of ReadReq MSHR misses 1032system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16710 # number of demand (read+write) MSHR misses 1033system.cpu.itb_walker_cache.demand_mshr_misses::total 16710 # number of demand (read+write) MSHR misses 1034system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16710 # number of overall MSHR misses 1035system.cpu.itb_walker_cache.overall_mshr_misses::total 16710 # number of overall MSHR misses 1036system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 156005776 # number of ReadReq MSHR miss cycles 1037system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 156005776 # number of ReadReq MSHR miss cycles 1038system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 156005776 # number of demand (read+write) MSHR miss cycles 1039system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 156005776 # number of demand (read+write) MSHR miss cycles 1040system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 156005776 # number of overall MSHR miss cycles 1041system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 156005776 # number of overall MSHR miss cycles 1042system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.395897 # mshr miss rate for ReadReq accesses 1043system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.395897 # mshr miss rate for ReadReq accesses 1044system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.395878 # mshr miss rate for demand accesses 1045system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.395878 # mshr miss rate for demand accesses 1046system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.395878 # mshr miss rate for overall accesses 1047system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.395878 # mshr miss rate for overall accesses 1048system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average ReadReq mshr miss latency 1049system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9336.072771 # average ReadReq mshr miss latency 1050system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average overall mshr miss latency 1051system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9336.072771 # average overall mshr miss latency 1052system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average overall mshr miss latency 1053system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9336.072771 # average overall mshr miss latency |
| 1056system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1054system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1057system.cpu.l2cache.tags.replacements 112974 # number of replacements 1058system.cpu.l2cache.tags.tagsinuse 64818.744711 # Cycle average of tags in use 1059system.cpu.l2cache.tags.total_refs 3837920 # Total number of references to valid blocks. 1060system.cpu.l2cache.tags.sampled_refs 177018 # Sample count of references to valid blocks. 1061system.cpu.l2cache.tags.avg_refs 21.680959 # Average number of references to valid blocks. | 1055system.cpu.l2cache.tags.replacements 112952 # number of replacements 1056system.cpu.l2cache.tags.tagsinuse 64819.666116 # Cycle average of tags in use 1057system.cpu.l2cache.tags.total_refs 3838789 # Total number of references to valid blocks. 1058system.cpu.l2cache.tags.sampled_refs 176912 # Sample count of references to valid blocks. 1059system.cpu.l2cache.tags.avg_refs 21.698862 # Average number of references to valid blocks. |
| 1062system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1060system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1063system.cpu.l2cache.tags.occ_blocks::writebacks 50388.015751 # Average occupied blocks per requestor 1064system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.441797 # Average occupied blocks per requestor 1065system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125760 # Average occupied blocks per requestor 1066system.cpu.l2cache.tags.occ_blocks::cpu.inst 3267.225445 # Average occupied blocks per requestor 1067system.cpu.l2cache.tags.occ_blocks::cpu.data 11145.935958 # Average occupied blocks per requestor 1068system.cpu.l2cache.tags.occ_percent::writebacks 0.768860 # Average percentage of cache occupancy 1069system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy | 1061system.cpu.l2cache.tags.occ_blocks::writebacks 50506.549042 # Average occupied blocks per requestor 1062system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 19.197840 # Average occupied blocks per requestor 1063system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135379 # Average occupied blocks per requestor 1064system.cpu.l2cache.tags.occ_blocks::cpu.inst 3269.774951 # Average occupied blocks per requestor 1065system.cpu.l2cache.tags.occ_blocks::cpu.data 11024.008903 # Average occupied blocks per requestor 1066system.cpu.l2cache.tags.occ_percent::writebacks 0.770669 # Average percentage of cache occupancy 1067system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000293 # Average percentage of cache occupancy |
| 1070system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 1068system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 1071system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049854 # Average percentage of cache occupancy 1072system.cpu.l2cache.tags.occ_percent::cpu.data 0.170073 # Average percentage of cache occupancy 1073system.cpu.l2cache.tags.occ_percent::total 0.989056 # Average percentage of cache occupancy 1074system.cpu.l2cache.tags.occ_task_id_blocks::1024 64044 # Occupied blocks per task id 1075system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1076system.cpu.l2cache.tags.age_task_id_blocks_1024::1 598 # Occupied blocks per task id 1077system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3343 # Occupied blocks per task id 1078system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7275 # Occupied blocks per task id 1079system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52773 # Occupied blocks per task id 1080system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977234 # Percentage of cache occupancy per task id 1081system.cpu.l2cache.tags.tag_accesses 35081259 # Number of tag accesses 1082system.cpu.l2cache.tags.data_accesses 35081259 # Number of data accesses 1083system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69593 # number of ReadReq hits 1084system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 14758 # number of ReadReq hits 1085system.cpu.l2cache.ReadReq_hits::cpu.inst 984803 # number of ReadReq hits 1086system.cpu.l2cache.ReadReq_hits::cpu.data 1337710 # number of ReadReq hits 1087system.cpu.l2cache.ReadReq_hits::total 2406864 # number of ReadReq hits 1088system.cpu.l2cache.Writeback_hits::writebacks 1577834 # number of Writeback hits 1089system.cpu.l2cache.Writeback_hits::total 1577834 # number of Writeback hits 1090system.cpu.l2cache.UpgradeReq_hits::cpu.data 300 # number of UpgradeReq hits 1091system.cpu.l2cache.UpgradeReq_hits::total 300 # number of UpgradeReq hits 1092system.cpu.l2cache.ReadExReq_hits::cpu.data 153385 # number of ReadExReq hits 1093system.cpu.l2cache.ReadExReq_hits::total 153385 # number of ReadExReq hits 1094system.cpu.l2cache.demand_hits::cpu.dtb.walker 69593 # number of demand (read+write) hits 1095system.cpu.l2cache.demand_hits::cpu.itb.walker 14758 # number of demand (read+write) hits 1096system.cpu.l2cache.demand_hits::cpu.inst 984803 # number of demand (read+write) hits 1097system.cpu.l2cache.demand_hits::cpu.data 1491095 # number of demand (read+write) hits 1098system.cpu.l2cache.demand_hits::total 2560249 # number of demand (read+write) hits 1099system.cpu.l2cache.overall_hits::cpu.dtb.walker 69593 # number of overall hits 1100system.cpu.l2cache.overall_hits::cpu.itb.walker 14758 # number of overall hits 1101system.cpu.l2cache.overall_hits::cpu.inst 984803 # number of overall hits 1102system.cpu.l2cache.overall_hits::cpu.data 1491095 # number of overall hits 1103system.cpu.l2cache.overall_hits::total 2560249 # number of overall hits | 1069system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049893 # Average percentage of cache occupancy 1070system.cpu.l2cache.tags.occ_percent::cpu.data 0.168213 # Average percentage of cache occupancy 1071system.cpu.l2cache.tags.occ_percent::total 0.989070 # Average percentage of cache occupancy 1072system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id 1073system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 1074system.cpu.l2cache.tags.age_task_id_blocks_1024::1 594 # Occupied blocks per task id 1075system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id 1076system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5550 # Occupied blocks per task id 1077system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54407 # Occupied blocks per task id 1078system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id 1079system.cpu.l2cache.tags.tag_accesses 35127054 # Number of tag accesses 1080system.cpu.l2cache.tags.data_accesses 35127054 # Number of data accesses 1081system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69856 # number of ReadReq hits 1082system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13439 # number of ReadReq hits 1083system.cpu.l2cache.ReadReq_hits::cpu.inst 982174 # number of ReadReq hits 1084system.cpu.l2cache.ReadReq_hits::cpu.data 1337175 # number of ReadReq hits 1085system.cpu.l2cache.ReadReq_hits::total 2402644 # number of ReadReq hits 1086system.cpu.l2cache.Writeback_hits::writebacks 1586883 # number of Writeback hits 1087system.cpu.l2cache.Writeback_hits::total 1586883 # number of Writeback hits 1088system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits 1089system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits 1090system.cpu.l2cache.ReadExReq_hits::cpu.data 154161 # number of ReadExReq hits 1091system.cpu.l2cache.ReadExReq_hits::total 154161 # number of ReadExReq hits 1092system.cpu.l2cache.demand_hits::cpu.dtb.walker 69856 # number of demand (read+write) hits 1093system.cpu.l2cache.demand_hits::cpu.itb.walker 13439 # number of demand (read+write) hits 1094system.cpu.l2cache.demand_hits::cpu.inst 982174 # number of demand (read+write) hits 1095system.cpu.l2cache.demand_hits::cpu.data 1491336 # number of demand (read+write) hits 1096system.cpu.l2cache.demand_hits::total 2556805 # number of demand (read+write) hits 1097system.cpu.l2cache.overall_hits::cpu.dtb.walker 69856 # number of overall hits 1098system.cpu.l2cache.overall_hits::cpu.itb.walker 13439 # number of overall hits 1099system.cpu.l2cache.overall_hits::cpu.inst 982174 # number of overall hits 1100system.cpu.l2cache.overall_hits::cpu.data 1491336 # number of overall hits 1101system.cpu.l2cache.overall_hits::total 2556805 # number of overall hits |
| 1104system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 68 # number of ReadReq misses 1105system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 1102system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 68 # number of ReadReq misses 1103system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 1106system.cpu.l2cache.ReadReq_misses::cpu.inst 16393 # number of ReadReq misses 1107system.cpu.l2cache.ReadReq_misses::cpu.data 35895 # number of ReadReq misses 1108system.cpu.l2cache.ReadReq_misses::total 52361 # number of ReadReq misses 1109system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses 1110system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses 1111system.cpu.l2cache.ReadExReq_misses::cpu.data 133756 # number of ReadExReq misses 1112system.cpu.l2cache.ReadExReq_misses::total 133756 # number of ReadExReq misses | 1104system.cpu.l2cache.ReadReq_misses::cpu.inst 16339 # number of ReadReq misses 1105system.cpu.l2cache.ReadReq_misses::cpu.data 35825 # number of ReadReq misses 1106system.cpu.l2cache.ReadReq_misses::total 52237 # number of ReadReq misses 1107system.cpu.l2cache.UpgradeReq_misses::cpu.data 1483 # number of UpgradeReq misses 1108system.cpu.l2cache.UpgradeReq_misses::total 1483 # number of UpgradeReq misses 1109system.cpu.l2cache.ReadExReq_misses::cpu.data 133848 # number of ReadExReq misses 1110system.cpu.l2cache.ReadExReq_misses::total 133848 # number of ReadExReq misses |
| 1113system.cpu.l2cache.demand_misses::cpu.dtb.walker 68 # number of demand (read+write) misses 1114system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 1111system.cpu.l2cache.demand_misses::cpu.dtb.walker 68 # number of demand (read+write) misses 1112system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 1115system.cpu.l2cache.demand_misses::cpu.inst 16393 # number of demand (read+write) misses 1116system.cpu.l2cache.demand_misses::cpu.data 169651 # number of demand (read+write) misses 1117system.cpu.l2cache.demand_misses::total 186117 # number of demand (read+write) misses | 1113system.cpu.l2cache.demand_misses::cpu.inst 16339 # number of demand (read+write) misses 1114system.cpu.l2cache.demand_misses::cpu.data 169673 # number of demand (read+write) misses 1115system.cpu.l2cache.demand_misses::total 186085 # number of demand (read+write) misses |
| 1118system.cpu.l2cache.overall_misses::cpu.dtb.walker 68 # number of overall misses 1119system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 1116system.cpu.l2cache.overall_misses::cpu.dtb.walker 68 # number of overall misses 1117system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 1120system.cpu.l2cache.overall_misses::cpu.inst 16393 # number of overall misses 1121system.cpu.l2cache.overall_misses::cpu.data 169651 # number of overall misses 1122system.cpu.l2cache.overall_misses::total 186117 # number of overall misses 1123system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6414250 # number of ReadReq miss cycles 1124system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 407500 # number of ReadReq miss cycles 1125system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1255247500 # number of ReadReq miss cycles 1126system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2834689998 # number of ReadReq miss cycles 1127system.cpu.l2cache.ReadReq_miss_latency::total 4096759248 # number of ReadReq miss cycles 1128system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17266314 # number of UpgradeReq miss cycles 1129system.cpu.l2cache.UpgradeReq_miss_latency::total 17266314 # number of UpgradeReq miss cycles 1130system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9330791213 # number of ReadExReq miss cycles 1131system.cpu.l2cache.ReadExReq_miss_latency::total 9330791213 # number of ReadExReq miss cycles 1132system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6414250 # number of demand (read+write) miss cycles 1133system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 407500 # number of demand (read+write) miss cycles 1134system.cpu.l2cache.demand_miss_latency::cpu.inst 1255247500 # number of demand (read+write) miss cycles 1135system.cpu.l2cache.demand_miss_latency::cpu.data 12165481211 # number of demand (read+write) miss cycles 1136system.cpu.l2cache.demand_miss_latency::total 13427550461 # number of demand (read+write) miss cycles 1137system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6414250 # number of overall miss cycles 1138system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 407500 # number of overall miss cycles 1139system.cpu.l2cache.overall_miss_latency::cpu.inst 1255247500 # number of overall miss cycles 1140system.cpu.l2cache.overall_miss_latency::cpu.data 12165481211 # number of overall miss cycles 1141system.cpu.l2cache.overall_miss_latency::total 13427550461 # number of overall miss cycles 1142system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69661 # number of ReadReq accesses(hits+misses) 1143system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 14763 # number of ReadReq accesses(hits+misses) 1144system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001196 # number of ReadReq accesses(hits+misses) 1145system.cpu.l2cache.ReadReq_accesses::cpu.data 1373605 # number of ReadReq accesses(hits+misses) 1146system.cpu.l2cache.ReadReq_accesses::total 2459225 # number of ReadReq accesses(hits+misses) 1147system.cpu.l2cache.Writeback_accesses::writebacks 1577834 # number of Writeback accesses(hits+misses) 1148system.cpu.l2cache.Writeback_accesses::total 1577834 # number of Writeback accesses(hits+misses) 1149system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1744 # number of UpgradeReq accesses(hits+misses) 1150system.cpu.l2cache.UpgradeReq_accesses::total 1744 # number of UpgradeReq accesses(hits+misses) 1151system.cpu.l2cache.ReadExReq_accesses::cpu.data 287141 # number of ReadExReq accesses(hits+misses) 1152system.cpu.l2cache.ReadExReq_accesses::total 287141 # number of ReadExReq accesses(hits+misses) 1153system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69661 # number of demand (read+write) accesses 1154system.cpu.l2cache.demand_accesses::cpu.itb.walker 14763 # number of demand (read+write) accesses 1155system.cpu.l2cache.demand_accesses::cpu.inst 1001196 # number of demand (read+write) accesses 1156system.cpu.l2cache.demand_accesses::cpu.data 1660746 # number of demand (read+write) accesses 1157system.cpu.l2cache.demand_accesses::total 2746366 # number of demand (read+write) accesses 1158system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69661 # number of overall (read+write) accesses 1159system.cpu.l2cache.overall_accesses::cpu.itb.walker 14763 # number of overall (read+write) accesses 1160system.cpu.l2cache.overall_accesses::cpu.inst 1001196 # number of overall (read+write) accesses 1161system.cpu.l2cache.overall_accesses::cpu.data 1660746 # number of overall (read+write) accesses 1162system.cpu.l2cache.overall_accesses::total 2746366 # number of overall (read+write) accesses 1163system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000976 # miss rate for ReadReq accesses 1164system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000339 # miss rate for ReadReq accesses 1165system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016373 # miss rate for ReadReq accesses 1166system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026132 # miss rate for ReadReq accesses 1167system.cpu.l2cache.ReadReq_miss_rate::total 0.021292 # miss rate for ReadReq accesses 1168system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.827982 # miss rate for UpgradeReq accesses 1169system.cpu.l2cache.UpgradeReq_miss_rate::total 0.827982 # miss rate for UpgradeReq accesses 1170system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.465820 # miss rate for ReadExReq accesses 1171system.cpu.l2cache.ReadExReq_miss_rate::total 0.465820 # miss rate for ReadExReq accesses 1172system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000976 # miss rate for demand accesses 1173system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000339 # miss rate for demand accesses 1174system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016373 # miss rate for demand accesses 1175system.cpu.l2cache.demand_miss_rate::cpu.data 0.102153 # miss rate for demand accesses 1176system.cpu.l2cache.demand_miss_rate::total 0.067768 # miss rate for demand accesses 1177system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000976 # miss rate for overall accesses 1178system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000339 # miss rate for overall accesses 1179system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016373 # miss rate for overall accesses 1180system.cpu.l2cache.overall_miss_rate::cpu.data 0.102153 # miss rate for overall accesses 1181system.cpu.l2cache.overall_miss_rate::total 0.067768 # miss rate for overall accesses 1182system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 94327.205882 # average ReadReq miss latency 1183system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81500 # average ReadReq miss latency 1184system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76572.164948 # average ReadReq miss latency 1185system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78971.723025 # average ReadReq miss latency 1186system.cpu.l2cache.ReadReq_avg_miss_latency::total 78240.660950 # average ReadReq miss latency 1187system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11957.281163 # average UpgradeReq miss latency 1188system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11957.281163 # average UpgradeReq miss latency 1189system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69759.795546 # average ReadExReq miss latency 1190system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69759.795546 # average ReadExReq miss latency 1191system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 94327.205882 # average overall miss latency 1192system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81500 # average overall miss latency 1193system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76572.164948 # average overall miss latency 1194system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71708.868271 # average overall miss latency 1195system.cpu.l2cache.demand_avg_miss_latency::total 72145.749507 # average overall miss latency 1196system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 94327.205882 # average overall miss latency 1197system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81500 # average overall miss latency 1198system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76572.164948 # average overall miss latency 1199system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71708.868271 # average overall miss latency 1200system.cpu.l2cache.overall_avg_miss_latency::total 72145.749507 # average overall miss latency | 1118system.cpu.l2cache.overall_misses::cpu.inst 16339 # number of overall misses 1119system.cpu.l2cache.overall_misses::cpu.data 169673 # number of overall misses 1120system.cpu.l2cache.overall_misses::total 186085 # number of overall misses 1121system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6082250 # number of ReadReq miss cycles 1122system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 393250 # number of ReadReq miss cycles 1123system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1247981750 # number of ReadReq miss cycles 1124system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2833529749 # number of ReadReq miss cycles 1125system.cpu.l2cache.ReadReq_miss_latency::total 4087986999 # number of ReadReq miss cycles 1126system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17399310 # number of UpgradeReq miss cycles 1127system.cpu.l2cache.UpgradeReq_miss_latency::total 17399310 # number of UpgradeReq miss cycles 1128system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9336961710 # number of ReadExReq miss cycles 1129system.cpu.l2cache.ReadExReq_miss_latency::total 9336961710 # number of ReadExReq miss cycles 1130system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6082250 # number of demand (read+write) miss cycles 1131system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 393250 # number of demand (read+write) miss cycles 1132system.cpu.l2cache.demand_miss_latency::cpu.inst 1247981750 # number of demand (read+write) miss cycles 1133system.cpu.l2cache.demand_miss_latency::cpu.data 12170491459 # number of demand (read+write) miss cycles 1134system.cpu.l2cache.demand_miss_latency::total 13424948709 # number of demand (read+write) miss cycles 1135system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6082250 # number of overall miss cycles 1136system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 393250 # number of overall miss cycles 1137system.cpu.l2cache.overall_miss_latency::cpu.inst 1247981750 # number of overall miss cycles 1138system.cpu.l2cache.overall_miss_latency::cpu.data 12170491459 # number of overall miss cycles 1139system.cpu.l2cache.overall_miss_latency::total 13424948709 # number of overall miss cycles 1140system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69924 # number of ReadReq accesses(hits+misses) 1141system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13444 # number of ReadReq accesses(hits+misses) 1142system.cpu.l2cache.ReadReq_accesses::cpu.inst 998513 # number of ReadReq accesses(hits+misses) 1143system.cpu.l2cache.ReadReq_accesses::cpu.data 1373000 # number of ReadReq accesses(hits+misses) 1144system.cpu.l2cache.ReadReq_accesses::total 2454881 # number of ReadReq accesses(hits+misses) 1145system.cpu.l2cache.Writeback_accesses::writebacks 1586883 # number of Writeback accesses(hits+misses) 1146system.cpu.l2cache.Writeback_accesses::total 1586883 # number of Writeback accesses(hits+misses) 1147system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1792 # number of UpgradeReq accesses(hits+misses) 1148system.cpu.l2cache.UpgradeReq_accesses::total 1792 # number of UpgradeReq accesses(hits+misses) 1149system.cpu.l2cache.ReadExReq_accesses::cpu.data 288009 # number of ReadExReq accesses(hits+misses) 1150system.cpu.l2cache.ReadExReq_accesses::total 288009 # number of ReadExReq accesses(hits+misses) 1151system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69924 # number of demand (read+write) accesses 1152system.cpu.l2cache.demand_accesses::cpu.itb.walker 13444 # number of demand (read+write) accesses 1153system.cpu.l2cache.demand_accesses::cpu.inst 998513 # number of demand (read+write) accesses 1154system.cpu.l2cache.demand_accesses::cpu.data 1661009 # number of demand (read+write) accesses 1155system.cpu.l2cache.demand_accesses::total 2742890 # number of demand (read+write) accesses 1156system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69924 # number of overall (read+write) accesses 1157system.cpu.l2cache.overall_accesses::cpu.itb.walker 13444 # number of overall (read+write) accesses 1158system.cpu.l2cache.overall_accesses::cpu.inst 998513 # number of overall (read+write) accesses 1159system.cpu.l2cache.overall_accesses::cpu.data 1661009 # number of overall (read+write) accesses 1160system.cpu.l2cache.overall_accesses::total 2742890 # number of overall (read+write) accesses 1161system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000972 # miss rate for ReadReq accesses 1162system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000372 # miss rate for ReadReq accesses 1163system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016363 # miss rate for ReadReq accesses 1164system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026092 # miss rate for ReadReq accesses 1165system.cpu.l2cache.ReadReq_miss_rate::total 0.021279 # miss rate for ReadReq accesses 1166system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.827567 # miss rate for UpgradeReq accesses 1167system.cpu.l2cache.UpgradeReq_miss_rate::total 0.827567 # miss rate for UpgradeReq accesses 1168system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464735 # miss rate for ReadExReq accesses 1169system.cpu.l2cache.ReadExReq_miss_rate::total 0.464735 # miss rate for ReadExReq accesses 1170system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000972 # miss rate for demand accesses 1171system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000372 # miss rate for demand accesses 1172system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016363 # miss rate for demand accesses 1173system.cpu.l2cache.demand_miss_rate::cpu.data 0.102151 # miss rate for demand accesses 1174system.cpu.l2cache.demand_miss_rate::total 0.067843 # miss rate for demand accesses 1175system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000972 # miss rate for overall accesses 1176system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000372 # miss rate for overall accesses 1177system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016363 # miss rate for overall accesses 1178system.cpu.l2cache.overall_miss_rate::cpu.data 0.102151 # miss rate for overall accesses 1179system.cpu.l2cache.overall_miss_rate::total 0.067843 # miss rate for overall accesses 1180system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89444.852941 # average ReadReq miss latency 1181system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78650 # average ReadReq miss latency 1182system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76380.546545 # average ReadReq miss latency 1183system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79093.642680 # average ReadReq miss latency 1184system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.456630 # average ReadReq miss latency 1185system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11732.508429 # average UpgradeReq miss latency 1186system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11732.508429 # average UpgradeReq miss latency 1187system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69757.947149 # average ReadExReq miss latency 1188system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69757.947149 # average ReadExReq miss latency 1189system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89444.852941 # average overall miss latency 1190system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78650 # average overall miss latency 1191system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76380.546545 # average overall miss latency 1192system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71729.099262 # average overall miss latency 1193system.cpu.l2cache.demand_avg_miss_latency::total 72144.174485 # average overall miss latency 1194system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89444.852941 # average overall miss latency 1195system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78650 # average overall miss latency 1196system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76380.546545 # average overall miss latency 1197system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71729.099262 # average overall miss latency 1198system.cpu.l2cache.overall_avg_miss_latency::total 72144.174485 # average overall miss latency |
| 1201system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1202system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1203system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1204system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1205system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1206system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1207system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1208system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1199system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1200system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1201system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1202system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1203system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1204system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1205system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1206system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1209system.cpu.l2cache.writebacks::writebacks 103249 # number of writebacks 1210system.cpu.l2cache.writebacks::total 103249 # number of writebacks 1211system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1212system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits 1213system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1214system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1215system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits 1216system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 1217system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1218system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits 1219system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits | 1207system.cpu.l2cache.writebacks::writebacks 103187 # number of writebacks 1208system.cpu.l2cache.writebacks::total 103187 # number of writebacks 1209system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1210system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits 1211system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 1212system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1213system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits 1214system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 1215system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1216system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits 1217system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits |
| 1220system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 68 # number of ReadReq MSHR misses 1221system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses | 1218system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 68 # number of ReadReq MSHR misses 1219system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses |
| 1222system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16392 # number of ReadReq MSHR misses 1223system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35893 # number of ReadReq MSHR misses 1224system.cpu.l2cache.ReadReq_mshr_misses::total 52358 # number of ReadReq MSHR misses 1225system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses 1226system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses 1227system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133756 # number of ReadExReq MSHR misses 1228system.cpu.l2cache.ReadExReq_mshr_misses::total 133756 # number of ReadExReq MSHR misses | 1220system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16337 # number of ReadReq MSHR misses 1221system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35822 # number of ReadReq MSHR misses 1222system.cpu.l2cache.ReadReq_mshr_misses::total 52232 # number of ReadReq MSHR misses 1223system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1483 # number of UpgradeReq MSHR misses 1224system.cpu.l2cache.UpgradeReq_mshr_misses::total 1483 # number of UpgradeReq MSHR misses 1225system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133848 # number of ReadExReq MSHR misses 1226system.cpu.l2cache.ReadExReq_mshr_misses::total 133848 # number of ReadExReq MSHR misses |
| 1229system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 68 # number of demand (read+write) MSHR misses 1230system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses | 1227system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 68 # number of demand (read+write) MSHR misses 1228system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses |
| 1231system.cpu.l2cache.demand_mshr_misses::cpu.inst 16392 # number of demand (read+write) MSHR misses 1232system.cpu.l2cache.demand_mshr_misses::cpu.data 169649 # number of demand (read+write) MSHR misses 1233system.cpu.l2cache.demand_mshr_misses::total 186114 # number of demand (read+write) MSHR misses | 1229system.cpu.l2cache.demand_mshr_misses::cpu.inst 16337 # number of demand (read+write) MSHR misses 1230system.cpu.l2cache.demand_mshr_misses::cpu.data 169670 # number of demand (read+write) MSHR misses 1231system.cpu.l2cache.demand_mshr_misses::total 186080 # number of demand (read+write) MSHR misses |
| 1234system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 68 # number of overall MSHR misses 1235system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses | 1232system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 68 # number of overall MSHR misses 1233system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses |
| 1236system.cpu.l2cache.overall_mshr_misses::cpu.inst 16392 # number of overall MSHR misses 1237system.cpu.l2cache.overall_mshr_misses::cpu.data 169649 # number of overall MSHR misses 1238system.cpu.l2cache.overall_mshr_misses::total 186114 # number of overall MSHR misses 1239system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5576250 # number of ReadReq MSHR miss cycles 1240system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 344500 # number of ReadReq MSHR miss cycles 1241system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049607750 # number of ReadReq MSHR miss cycles 1242system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2389031498 # number of ReadReq MSHR miss cycles 1243system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3444559998 # number of ReadReq MSHR miss cycles 1244system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15363423 # number of UpgradeReq MSHR miss cycles 1245system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15363423 # number of UpgradeReq MSHR miss cycles 1246system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7651301287 # number of ReadExReq MSHR miss cycles 1247system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7651301287 # number of ReadExReq MSHR miss cycles 1248system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5576250 # number of demand (read+write) MSHR miss cycles 1249system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 344500 # number of demand (read+write) MSHR miss cycles 1250system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049607750 # number of demand (read+write) MSHR miss cycles 1251system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10040332785 # number of demand (read+write) MSHR miss cycles 1252system.cpu.l2cache.demand_mshr_miss_latency::total 11095861285 # number of demand (read+write) MSHR miss cycles 1253system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5576250 # number of overall MSHR miss cycles 1254system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 344500 # number of overall MSHR miss cycles 1255system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049607750 # number of overall MSHR miss cycles 1256system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10040332785 # number of overall MSHR miss cycles 1257system.cpu.l2cache.overall_mshr_miss_latency::total 11095861285 # number of overall MSHR miss cycles 1258system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275596500 # number of ReadReq MSHR uncacheable cycles 1259system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275596500 # number of ReadReq MSHR uncacheable cycles 1260system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397352000 # number of WriteReq MSHR uncacheable cycles 1261system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397352000 # number of WriteReq MSHR uncacheable cycles 1262system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672948500 # number of overall MSHR uncacheable cycles 1263system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672948500 # number of overall MSHR uncacheable cycles 1264system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for ReadReq accesses 1265system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for ReadReq accesses 1266system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for ReadReq accesses 1267system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026131 # mshr miss rate for ReadReq accesses 1268system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021290 # mshr miss rate for ReadReq accesses 1269system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827982 # mshr miss rate for UpgradeReq accesses 1270system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827982 # mshr miss rate for UpgradeReq accesses 1271system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465820 # mshr miss rate for ReadExReq accesses 1272system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465820 # mshr miss rate for ReadExReq accesses 1273system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for demand accesses 1274system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for demand accesses 1275system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for demand accesses 1276system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for demand accesses 1277system.cpu.l2cache.demand_mshr_miss_rate::total 0.067767 # mshr miss rate for demand accesses 1278system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for overall accesses 1279system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for overall accesses 1280system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for overall accesses 1281system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for overall accesses 1282system.cpu.l2cache.overall_mshr_miss_rate::total 0.067767 # mshr miss rate for overall accesses 1283system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average ReadReq mshr miss latency 1284system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68900 # average ReadReq mshr miss latency 1285system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64031.707540 # average ReadReq mshr miss latency 1286system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66559.816622 # average ReadReq mshr miss latency 1287system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65788.609152 # average ReadReq mshr miss latency 1288system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10639.489612 # average UpgradeReq mshr miss latency 1289system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10639.489612 # average UpgradeReq mshr miss latency 1290system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57203.424796 # average ReadExReq mshr miss latency 1291system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57203.424796 # average ReadExReq mshr miss latency 1292system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency 1293system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency 1294system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency 1295system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency 1296system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency 1297system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency 1298system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency 1299system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency 1300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency 1301system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency | 1234system.cpu.l2cache.overall_mshr_misses::cpu.inst 16337 # number of overall MSHR misses 1235system.cpu.l2cache.overall_mshr_misses::cpu.data 169670 # number of overall MSHR misses 1236system.cpu.l2cache.overall_mshr_misses::total 186080 # number of overall MSHR misses 1237system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5240250 # number of ReadReq MSHR miss cycles 1238system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 330750 # number of ReadReq MSHR miss cycles 1239system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1042946750 # number of ReadReq MSHR miss cycles 1240system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2388969999 # number of ReadReq MSHR miss cycles 1241system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3437487749 # number of ReadReq MSHR miss cycles 1242system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15771463 # number of UpgradeReq MSHR miss cycles 1243system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15771463 # number of UpgradeReq MSHR miss cycles 1244system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7656264290 # number of ReadExReq MSHR miss cycles 1245system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7656264290 # number of ReadExReq MSHR miss cycles 1246system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5240250 # number of demand (read+write) MSHR miss cycles 1247system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 330750 # number of demand (read+write) MSHR miss cycles 1248system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1042946750 # number of demand (read+write) MSHR miss cycles 1249system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10045234289 # number of demand (read+write) MSHR miss cycles 1250system.cpu.l2cache.demand_mshr_miss_latency::total 11093752039 # number of demand (read+write) MSHR miss cycles 1251system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5240250 # number of overall MSHR miss cycles 1252system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 330750 # number of overall MSHR miss cycles 1253system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1042946750 # number of overall MSHR miss cycles 1254system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10045234289 # number of overall MSHR miss cycles 1255system.cpu.l2cache.overall_mshr_miss_latency::total 11093752039 # number of overall MSHR miss cycles 1256system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89281194000 # number of ReadReq MSHR uncacheable cycles 1257system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89281194000 # number of ReadReq MSHR uncacheable cycles 1258system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401486500 # number of WriteReq MSHR uncacheable cycles 1259system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401486500 # number of WriteReq MSHR uncacheable cycles 1260system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91682680500 # number of overall MSHR uncacheable cycles 1261system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91682680500 # number of overall MSHR uncacheable cycles 1262system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for ReadReq accesses 1263system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for ReadReq accesses 1264system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for ReadReq accesses 1265system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026090 # mshr miss rate for ReadReq accesses 1266system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021277 # mshr miss rate for ReadReq accesses 1267system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827567 # mshr miss rate for UpgradeReq accesses 1268system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827567 # mshr miss rate for UpgradeReq accesses 1269system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464735 # mshr miss rate for ReadExReq accesses 1270system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464735 # mshr miss rate for ReadExReq accesses 1271system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for demand accesses 1272system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for demand accesses 1273system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for demand accesses 1274system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102149 # mshr miss rate for demand accesses 1275system.cpu.l2cache.demand_mshr_miss_rate::total 0.067841 # mshr miss rate for demand accesses 1276system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for overall accesses 1277system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for overall accesses 1278system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for overall accesses 1279system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102149 # mshr miss rate for overall accesses 1280system.cpu.l2cache.overall_mshr_miss_rate::total 0.067841 # mshr miss rate for overall accesses 1281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average ReadReq mshr miss latency 1282system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66150 # average ReadReq mshr miss latency 1283system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63839.551325 # average ReadReq mshr miss latency 1284system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66690.022863 # average ReadReq mshr miss latency 1285system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65811.911261 # average ReadReq mshr miss latency 1286system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10634.836817 # average UpgradeReq mshr miss latency 1287system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10634.836817 # average UpgradeReq mshr miss latency 1288system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57201.185599 # average ReadExReq mshr miss latency 1289system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57201.185599 # average ReadExReq mshr miss latency 1290system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average overall mshr miss latency 1291system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66150 # average overall mshr miss latency 1292system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63839.551325 # average overall mshr miss latency 1293system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59204.539925 # average overall mshr miss latency 1294system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.185936 # average overall mshr miss latency 1295system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average overall mshr miss latency 1296system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66150 # average overall mshr miss latency 1297system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63839.551325 # average overall mshr miss latency 1298system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59204.539925 # average overall mshr miss latency 1299system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.185936 # average overall mshr miss latency |
| 1302system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1303system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1304system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1305system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1306system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1307system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1308system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1300system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1301system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1302system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1303system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1304system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1305system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1306system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1309system.cpu.toL2Bus.trans_dist::ReadReq 3078150 # Transaction distribution 1310system.cpu.toL2Bus.trans_dist::ReadResp 3077612 # Transaction distribution 1311system.cpu.toL2Bus.trans_dist::WriteReq 13891 # Transaction distribution 1312system.cpu.toL2Bus.trans_dist::WriteResp 13891 # Transaction distribution 1313system.cpu.toL2Bus.trans_dist::Writeback 1577834 # Transaction distribution | 1307system.cpu.toL2Bus.trans_dist::ReadReq 3077249 # Transaction distribution 1308system.cpu.toL2Bus.trans_dist::ReadResp 3076704 # Transaction distribution 1309system.cpu.toL2Bus.trans_dist::WriteReq 13905 # Transaction distribution 1310system.cpu.toL2Bus.trans_dist::WriteResp 13905 # Transaction distribution 1311system.cpu.toL2Bus.trans_dist::Writeback 1586883 # Transaction distribution |
| 1314system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution | 1312system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution |
| 1315system.cpu.toL2Bus.trans_dist::UpgradeReq 2215 # Transaction distribution 1316system.cpu.toL2Bus.trans_dist::UpgradeResp 2215 # Transaction distribution 1317system.cpu.toL2Bus.trans_dist::ReadExReq 287149 # Transaction distribution 1318system.cpu.toL2Bus.trans_dist::ReadExResp 287149 # Transaction distribution 1319system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution 1320system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002495 # Packet count per connected master and slave (bytes) 1321system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6134281 # Packet count per connected master and slave (bytes) 1322system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34017 # Packet count per connected master and slave (bytes) 1323system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159331 # Packet count per connected master and slave (bytes) 1324system.cpu.toL2Bus.pkt_count::total 8330124 # Packet count per connected master and slave (bytes) 1325system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64076544 # Cumulative packet size per connected master and slave (bytes) 1326system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208017731 # Cumulative packet size per connected master and slave (bytes) 1327system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1089216 # Cumulative packet size per connected master and slave (bytes) 1328system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5381760 # Cumulative packet size per connected master and slave (bytes) 1329system.cpu.toL2Bus.pkt_size::total 278565251 # Cumulative packet size per connected master and slave (bytes) 1330system.cpu.toL2Bus.snoops 57093 # Total snoops (count) 1331system.cpu.toL2Bus.snoop_fanout::samples 4382652 # Request fanout histogram 1332system.cpu.toL2Bus.snoop_fanout::mean 3.010869 # Request fanout histogram 1333system.cpu.toL2Bus.snoop_fanout::stdev 0.103688 # Request fanout histogram | 1313system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution 1314system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution 1315system.cpu.toL2Bus.trans_dist::ReadExReq 288016 # Transaction distribution 1316system.cpu.toL2Bus.trans_dist::ReadExResp 288016 # Transaction distribution 1317system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution 1318system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1997133 # Packet count per connected master and slave (bytes) 1319system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6136134 # Packet count per connected master and slave (bytes) 1320system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 33399 # Packet count per connected master and slave (bytes) 1321system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 169113 # Packet count per connected master and slave (bytes) 1322system.cpu.toL2Bus.pkt_count::total 8335779 # Packet count per connected master and slave (bytes) 1323system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63904832 # Cumulative packet size per connected master and slave (bytes) 1324system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208116125 # Cumulative packet size per connected master and slave (bytes) 1325system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1068096 # Cumulative packet size per connected master and slave (bytes) 1326system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5832064 # Cumulative packet size per connected master and slave (bytes) 1327system.cpu.toL2Bus.pkt_size::total 278921117 # Cumulative packet size per connected master and slave (bytes) 1328system.cpu.toL2Bus.snoops 60473 # Total snoops (count) 1329system.cpu.toL2Bus.snoop_fanout::samples 4391663 # Request fanout histogram 1330system.cpu.toL2Bus.snoop_fanout::mean 3.010846 # Request fanout histogram 1331system.cpu.toL2Bus.snoop_fanout::stdev 0.103577 # Request fanout histogram |
| 1334system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1335system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1336system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1337system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1332system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1333system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1334system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1335system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1338system.cpu.toL2Bus.snoop_fanout::3 4335015 98.91% 98.91% # Request fanout histogram 1339system.cpu.toL2Bus.snoop_fanout::4 47637 1.09% 100.00% # Request fanout histogram | 1336system.cpu.toL2Bus.snoop_fanout::3 4344032 98.92% 98.92% # Request fanout histogram 1337system.cpu.toL2Bus.snoop_fanout::4 47631 1.08% 100.00% # Request fanout histogram |
| 1340system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1341system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1342system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1338system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1339system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1340system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1343system.cpu.toL2Bus.snoop_fanout::total 4382652 # Request fanout histogram 1344system.cpu.toL2Bus.reqLayer0.occupancy 4064000382 # Layer occupancy (ticks) | 1341system.cpu.toL2Bus.snoop_fanout::total 4391663 # Request fanout histogram 1342system.cpu.toL2Bus.reqLayer0.occupancy 4077594873 # Layer occupancy (ticks) |
| 1345system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1343system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1346system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks) | 1344system.cpu.toL2Bus.snoopLayer0.occupancy 562500 # Layer occupancy (ticks) |
| 1347system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1345system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1348system.cpu.toL2Bus.respLayer0.occupancy 1506120456 # Layer occupancy (ticks) | 1346system.cpu.toL2Bus.respLayer0.occupancy 1502063776 # Layer occupancy (ticks) |
| 1349system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1347system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1350system.cpu.toL2Bus.respLayer1.occupancy 3144694054 # Layer occupancy (ticks) | 1348system.cpu.toL2Bus.respLayer1.occupancy 3145123125 # Layer occupancy (ticks) |
| 1351system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1349system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1352system.cpu.toL2Bus.respLayer2.occupancy 25505983 # Layer occupancy (ticks) | 1350system.cpu.toL2Bus.respLayer2.occupancy 25073734 # Layer occupancy (ticks) |
| 1353system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1351system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1354system.cpu.toL2Bus.respLayer3.occupancy 112929117 # Layer occupancy (ticks) | 1352system.cpu.toL2Bus.respLayer3.occupancy 117041135 # Layer occupancy (ticks) |
| 1355system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1353system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1356system.iobus.trans_dist::ReadReq 225688 # Transaction distribution 1357system.iobus.trans_dist::ReadResp 225688 # Transaction distribution 1358system.iobus.trans_dist::WriteReq 57721 # Transaction distribution 1359system.iobus.trans_dist::WriteResp 11001 # Transaction distribution | 1354system.iobus.trans_dist::ReadReq 225706 # Transaction distribution 1355system.iobus.trans_dist::ReadResp 225706 # Transaction distribution 1356system.iobus.trans_dist::WriteReq 57738 # Transaction distribution 1357system.iobus.trans_dist::WriteResp 11018 # Transaction distribution |
| 1360system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 1358system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1361system.iobus.trans_dist::MessageReq 1644 # Transaction distribution 1362system.iobus.trans_dist::MessageResp 1644 # Transaction distribution | 1359system.iobus.trans_dist::MessageReq 1643 # Transaction distribution 1360system.iobus.trans_dist::MessageResp 1643 # Transaction distribution |
| 1363system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1364system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) | 1361system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1362system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) |
| 1365system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) | 1363system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) |
| 1366system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1367system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1368system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 1369system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1370system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1371system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 1372system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1373system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1374system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) | 1364system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1365system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1366system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 1367system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1368system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1369system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 1370system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1371system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1372system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) |
| 1375system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) | 1373system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) |
| 1376system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1377system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1378system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1379system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1380system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) | 1374system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1375system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1376system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1377system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1378system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) |
| 1381system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) 1382system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95274 # Packet count per connected master and slave (bytes) 1383system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95274 # Packet count per connected master and slave (bytes) 1384system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) 1385system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) 1386system.iobus.pkt_count::total 570106 # Packet count per connected master and slave (bytes) | 1379system.iobus.pkt_count_system.bridge.master::total 471626 # Packet count per connected master and slave (bytes) 1380system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) 1381system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) 1382system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) 1383system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) 1384system.iobus.pkt_count::total 570174 # Packet count per connected master and slave (bytes) |
| 1387system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1388system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) | 1385system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1386system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) |
| 1389system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) | 1387system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) |
| 1390system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1391system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1392system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 1393system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1394system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1395system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 1396system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1397system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1398system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) | 1388system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1389system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1390system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 1391system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1392system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1393system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 1394system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1395system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1396system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) |
| 1399system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) | 1397system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) |
| 1400system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1401system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1402system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1403system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1404system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) | 1398system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1399system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1400system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1401system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1402system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) |
| 1405system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) 1406system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027880 # Cumulative packet size per connected master and slave (bytes) 1407system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027880 # Cumulative packet size per connected master and slave (bytes) 1408system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) 1409system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) 1410system.iobus.pkt_size::total 3276514 # Cumulative packet size per connected master and slave (bytes) 1411system.iobus.reqLayer0.occupancy 3918684 # Layer occupancy (ticks) | 1403system.iobus.pkt_size_system.bridge.master::total 242096 # Cumulative packet size per connected master and slave (bytes) 1404system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) 1405system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) 1406system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) 1407system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) 1408system.iobus.pkt_size::total 3276500 # Cumulative packet size per connected master and slave (bytes) 1409system.iobus.reqLayer0.occupancy 3915656 # Layer occupancy (ticks) |
| 1412system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1413system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1414system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1415system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1416system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1410system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1411system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1412system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1413system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1414system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1417system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) | 1415system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) |
| 1418system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1419system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1420system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1421system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1422system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1423system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 1424system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1425system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1426system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1427system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1428system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1429system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 1430system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1431system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1432system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1433system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1434system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1435system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1436system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) | 1416system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1417system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1418system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1419system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1420system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1421system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 1422system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1423system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1424system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1425system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1426system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1427system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 1428system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1429system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1430system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1431system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1432system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1433system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1434system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
| 1437system.iobus.reqLayer14.occupancy 20719000 # Layer occupancy (ticks) | 1435system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) |
| 1438system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1439system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1440system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1441system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1442system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1443system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1444system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1445system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1446system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 1436system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1437system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1438system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1439system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1440system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1441system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1442system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1443system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1444system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 1447system.iobus.reqLayer19.occupancy 448342458 # Layer occupancy (ticks) | 1445system.iobus.reqLayer19.occupancy 448351206 # Layer occupancy (ticks) |
| 1448system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1449system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1450system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) | 1446system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1447system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1448system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) |
| 1451system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) | 1449system.iobus.respLayer0.occupancy 460608000 # Layer occupancy (ticks) |
| 1452system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1450system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1453system.iobus.respLayer1.occupancy 52374503 # Layer occupancy (ticks) | 1451system.iobus.respLayer1.occupancy 52362260 # Layer occupancy (ticks) |
| 1454system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1452system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1455system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) | 1453system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) |
| 1456system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) | 1454system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1457system.iocache.tags.replacements 47582 # number of replacements 1458system.iocache.tags.tagsinuse 0.103930 # Cycle average of tags in use | 1455system.iocache.tags.replacements 47576 # number of replacements 1456system.iocache.tags.tagsinuse 0.091535 # Cycle average of tags in use |
| 1459system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1457system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1460system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks. | 1458system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. |
| 1461system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1459system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1462system.iocache.tags.warmup_cycle 4992992710000 # Cycle when the warmup percentage was hit. 1463system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103930 # Average occupied blocks per requestor 1464system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy 1465system.iocache.tags.occ_percent::total 0.006496 # Average percentage of cache occupancy | 1460system.iocache.tags.warmup_cycle 4992994629000 # Cycle when the warmup percentage was hit. 1461system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091535 # Average occupied blocks per requestor 1462system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005721 # Average percentage of cache occupancy 1463system.iocache.tags.occ_percent::total 0.005721 # Average percentage of cache occupancy |
| 1466system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1467system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1468system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1464system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1465system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1466system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1469system.iocache.tags.tag_accesses 428733 # Number of tag accesses 1470system.iocache.tags.data_accesses 428733 # Number of data accesses 1471system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses 1472system.iocache.ReadReq_misses::total 917 # number of ReadReq misses | 1467system.iocache.tags.tag_accesses 428679 # Number of tag accesses 1468system.iocache.tags.data_accesses 428679 # Number of data accesses 1469system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 1470system.iocache.ReadReq_misses::total 911 # number of ReadReq misses |
| 1473system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1474system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses | 1471system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1472system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses |
| 1475system.iocache.demand_misses::pc.south_bridge.ide 917 # number of demand (read+write) misses 1476system.iocache.demand_misses::total 917 # number of demand (read+write) misses 1477system.iocache.overall_misses::pc.south_bridge.ide 917 # number of overall misses 1478system.iocache.overall_misses::total 917 # number of overall misses 1479system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152376946 # number of ReadReq miss cycles 1480system.iocache.ReadReq_miss_latency::total 152376946 # number of ReadReq miss cycles 1481system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12347668009 # number of WriteInvalidateReq miss cycles 1482system.iocache.WriteInvalidateReq_miss_latency::total 12347668009 # number of WriteInvalidateReq miss cycles 1483system.iocache.demand_miss_latency::pc.south_bridge.ide 152376946 # number of demand (read+write) miss cycles 1484system.iocache.demand_miss_latency::total 152376946 # number of demand (read+write) miss cycles 1485system.iocache.overall_miss_latency::pc.south_bridge.ide 152376946 # number of overall miss cycles 1486system.iocache.overall_miss_latency::total 152376946 # number of overall miss cycles 1487system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses) 1488system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses) | 1473system.iocache.demand_misses::pc.south_bridge.ide 911 # number of demand (read+write) misses 1474system.iocache.demand_misses::total 911 # number of demand (read+write) misses 1475system.iocache.overall_misses::pc.south_bridge.ide 911 # number of overall misses 1476system.iocache.overall_misses::total 911 # number of overall misses 1477system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147981947 # number of ReadReq miss cycles 1478system.iocache.ReadReq_miss_latency::total 147981947 # number of ReadReq miss cycles 1479system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12360245999 # number of WriteInvalidateReq miss cycles 1480system.iocache.WriteInvalidateReq_miss_latency::total 12360245999 # number of WriteInvalidateReq miss cycles 1481system.iocache.demand_miss_latency::pc.south_bridge.ide 147981947 # number of demand (read+write) miss cycles 1482system.iocache.demand_miss_latency::total 147981947 # number of demand (read+write) miss cycles 1483system.iocache.overall_miss_latency::pc.south_bridge.ide 147981947 # number of overall miss cycles 1484system.iocache.overall_miss_latency::total 147981947 # number of overall miss cycles 1485system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 1486system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) |
| 1489system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1490system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) | 1487system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1488system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) |
| 1491system.iocache.demand_accesses::pc.south_bridge.ide 917 # number of demand (read+write) accesses 1492system.iocache.demand_accesses::total 917 # number of demand (read+write) accesses 1493system.iocache.overall_accesses::pc.south_bridge.ide 917 # number of overall (read+write) accesses 1494system.iocache.overall_accesses::total 917 # number of overall (read+write) accesses | 1489system.iocache.demand_accesses::pc.south_bridge.ide 911 # number of demand (read+write) accesses 1490system.iocache.demand_accesses::total 911 # number of demand (read+write) accesses 1491system.iocache.overall_accesses::pc.south_bridge.ide 911 # number of overall (read+write) accesses 1492system.iocache.overall_accesses::total 911 # number of overall (read+write) accesses |
| 1495system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1496system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1497system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1498system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1499system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1500system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1501system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1502system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1493system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1494system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1495system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1496system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1497system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1498system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1499system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1500system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1503system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average ReadReq miss latency 1504system.iocache.ReadReq_avg_miss_latency::total 166168.970556 # average ReadReq miss latency 1505system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264290.839234 # average WriteInvalidateReq miss latency 1506system.iocache.WriteInvalidateReq_avg_miss_latency::total 264290.839234 # average WriteInvalidateReq miss latency 1507system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency 1508system.iocache.demand_avg_miss_latency::total 166168.970556 # average overall miss latency 1509system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency 1510system.iocache.overall_avg_miss_latency::total 166168.970556 # average overall miss latency 1511system.iocache.blocked_cycles::no_mshrs 70541 # number of cycles access was blocked | 1501system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average ReadReq miss latency 1502system.iocache.ReadReq_avg_miss_latency::total 162439.019759 # average ReadReq miss latency 1503system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264560.059910 # average WriteInvalidateReq miss latency 1504system.iocache.WriteInvalidateReq_avg_miss_latency::total 264560.059910 # average WriteInvalidateReq miss latency 1505system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency 1506system.iocache.demand_avg_miss_latency::total 162439.019759 # average overall miss latency 1507system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency 1508system.iocache.overall_avg_miss_latency::total 162439.019759 # average overall miss latency 1509system.iocache.blocked_cycles::no_mshrs 70832 # number of cycles access was blocked |
| 1512system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1510system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1513system.iocache.blocked::no_mshrs 9150 # number of cycles access was blocked | 1511system.iocache.blocked::no_mshrs 9173 # number of cycles access was blocked |
| 1514system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1512system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1515system.iocache.avg_blocked_cycles::no_mshrs 7.709399 # average number of cycles each access was blocked | 1513system.iocache.avg_blocked_cycles::no_mshrs 7.721792 # average number of cycles each access was blocked |
| 1516system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1517system.iocache.fast_writes 0 # number of fast writes performed 1518system.iocache.cache_copies 0 # number of cache copies performed 1519system.iocache.writebacks::writebacks 46667 # number of writebacks 1520system.iocache.writebacks::total 46667 # number of writebacks | 1514system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1515system.iocache.fast_writes 0 # number of fast writes performed 1516system.iocache.cache_copies 0 # number of cache copies performed 1517system.iocache.writebacks::writebacks 46667 # number of writebacks 1518system.iocache.writebacks::total 46667 # number of writebacks |
| 1521system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses 1522system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses | 1519system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 1520system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses |
| 1523system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1524system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses | 1521system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1522system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses |
| 1525system.iocache.demand_mshr_misses::pc.south_bridge.ide 917 # number of demand (read+write) MSHR misses 1526system.iocache.demand_mshr_misses::total 917 # number of demand (read+write) MSHR misses 1527system.iocache.overall_mshr_misses::pc.south_bridge.ide 917 # number of overall MSHR misses 1528system.iocache.overall_mshr_misses::total 917 # number of overall MSHR misses 1529system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of ReadReq MSHR miss cycles 1530system.iocache.ReadReq_mshr_miss_latency::total 104665946 # number of ReadReq MSHR miss cycles 1531system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918222015 # number of WriteInvalidateReq MSHR miss cycles 1532system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918222015 # number of WriteInvalidateReq MSHR miss cycles 1533system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of demand (read+write) MSHR miss cycles 1534system.iocache.demand_mshr_miss_latency::total 104665946 # number of demand (read+write) MSHR miss cycles 1535system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of overall MSHR miss cycles 1536system.iocache.overall_mshr_miss_latency::total 104665946 # number of overall MSHR miss cycles | 1523system.iocache.demand_mshr_misses::pc.south_bridge.ide 911 # number of demand (read+write) MSHR misses 1524system.iocache.demand_mshr_misses::total 911 # number of demand (read+write) MSHR misses 1525system.iocache.overall_mshr_misses::pc.south_bridge.ide 911 # number of overall MSHR misses 1526system.iocache.overall_mshr_misses::total 911 # number of overall MSHR misses 1527system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of ReadReq MSHR miss cycles 1528system.iocache.ReadReq_mshr_miss_latency::total 100584447 # number of ReadReq MSHR miss cycles 1529system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9930786019 # number of WriteInvalidateReq MSHR miss cycles 1530system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9930786019 # number of WriteInvalidateReq MSHR miss cycles 1531system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of demand (read+write) MSHR miss cycles 1532system.iocache.demand_mshr_miss_latency::total 100584447 # number of demand (read+write) MSHR miss cycles 1533system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of overall MSHR miss cycles 1534system.iocache.overall_mshr_miss_latency::total 100584447 # number of overall MSHR miss cycles |
| 1537system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1538system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1539system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1540system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1541system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1542system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1543system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1544system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1535system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1536system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1537system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1538system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1539system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1540system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1541system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1542system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1545system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average ReadReq mshr miss latency 1546system.iocache.ReadReq_avg_mshr_miss_latency::total 114139.526718 # average ReadReq mshr miss latency 1547system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212290.710938 # average WriteInvalidateReq mshr miss latency 1548system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212290.710938 # average WriteInvalidateReq mshr miss latency 1549system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency 1550system.iocache.demand_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency 1551system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency 1552system.iocache.overall_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency | 1543system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average ReadReq mshr miss latency 1544system.iocache.ReadReq_avg_mshr_miss_latency::total 110411.028540 # average ReadReq mshr miss latency 1545system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212559.632256 # average WriteInvalidateReq mshr miss latency 1546system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212559.632256 # average WriteInvalidateReq mshr miss latency 1547system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency 1548system.iocache.demand_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency 1549system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency 1550system.iocache.overall_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency |
| 1553system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1551system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1554system.membus.trans_dist::ReadReq 662691 # Transaction distribution 1555system.membus.trans_dist::ReadResp 662685 # Transaction distribution 1556system.membus.trans_dist::WriteReq 13891 # Transaction distribution 1557system.membus.trans_dist::WriteResp 13891 # Transaction distribution 1558system.membus.trans_dist::Writeback 149916 # Transaction distribution | 1552system.membus.trans_dist::ReadReq 662583 # Transaction distribution 1553system.membus.trans_dist::ReadResp 662574 # Transaction distribution 1554system.membus.trans_dist::WriteReq 13905 # Transaction distribution 1555system.membus.trans_dist::WriteResp 13905 # Transaction distribution 1556system.membus.trans_dist::Writeback 149854 # Transaction distribution |
| 1559system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1560system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 1557system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1558system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1561system.membus.trans_dist::UpgradeReq 2202 # Transaction distribution 1562system.membus.trans_dist::UpgradeResp 1731 # Transaction distribution 1563system.membus.trans_dist::ReadExReq 133471 # Transaction distribution 1564system.membus.trans_dist::ReadExResp 133469 # Transaction distribution 1565system.membus.trans_dist::MessageReq 1644 # Transaction distribution 1566system.membus.trans_dist::MessageResp 1644 # Transaction distribution 1567system.membus.trans_dist::BadAddressError 6 # Transaction distribution 1568system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) 1569system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) 1570system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) 1571system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) 1572system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478147 # Packet count per connected master and slave (bytes) 1573system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) 1574system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724773 # Packet count per connected master and slave (bytes) 1575system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes) 1576system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes) 1577system.membus.pkt_count::total 1869528 # Packet count per connected master and slave (bytes) 1578system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) 1579system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) 1580system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) 1581system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) 1582system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18458240 # Cumulative packet size per connected master and slave (bytes) 1583system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20250435 # Cumulative packet size per connected master and slave (bytes) | 1559system.membus.trans_dist::UpgradeReq 2216 # Transaction distribution 1560system.membus.trans_dist::UpgradeResp 1773 # Transaction distribution 1561system.membus.trans_dist::ReadExReq 133558 # Transaction distribution 1562system.membus.trans_dist::ReadExResp 133558 # Transaction distribution 1563system.membus.trans_dist::MessageReq 1643 # Transaction distribution 1564system.membus.trans_dist::MessageResp 1643 # Transaction distribution 1565system.membus.trans_dist::BadAddressError 9 # Transaction distribution 1566system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) 1567system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) 1568system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471626 # Packet count per connected master and slave (bytes) 1569system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) 1570system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478050 # Packet count per connected master and slave (bytes) 1571system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes) 1572system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724758 # Packet count per connected master and slave (bytes) 1573system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141461 # Packet count per connected master and slave (bytes) 1574system.membus.pkt_count_system.iocache.mem_side::total 141461 # Packet count per connected master and slave (bytes) 1575system.membus.pkt_count::total 1869505 # Packet count per connected master and slave (bytes) 1576system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) 1577system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) 1578system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242096 # Cumulative packet size per connected master and slave (bytes) 1579system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) 1580system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18451136 # Cumulative packet size per connected master and slave (bytes) 1581system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20243357 # Cumulative packet size per connected master and slave (bytes) |
| 1584system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1585system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) | 1582system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1583system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) |
| 1586system.membus.pkt_size::total 26262131 # Cumulative packet size per connected master and slave (bytes) 1587system.membus.snoops 1626 # Total snoops (count) 1588system.membus.snoop_fanout::samples 385584 # Request fanout histogram | 1584system.membus.pkt_size::total 26255049 # Cumulative packet size per connected master and slave (bytes) 1585system.membus.snoops 1599 # Total snoops (count) 1586system.membus.snoop_fanout::samples 385491 # Request fanout histogram |
| 1589system.membus.snoop_fanout::mean 1 # Request fanout histogram 1590system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1591system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1592system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1587system.membus.snoop_fanout::mean 1 # Request fanout histogram 1588system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1589system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1590system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1593system.membus.snoop_fanout::1 385584 100.00% 100.00% # Request fanout histogram | 1591system.membus.snoop_fanout::1 385491 100.00% 100.00% # Request fanout histogram |
| 1594system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1595system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1596system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1597system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1592system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1593system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1594system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1595system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1598system.membus.snoop_fanout::total 385584 # Request fanout histogram 1599system.membus.reqLayer0.occupancy 251730500 # Layer occupancy (ticks) | 1596system.membus.snoop_fanout::total 385491 # Request fanout histogram 1597system.membus.reqLayer0.occupancy 251614500 # Layer occupancy (ticks) |
| 1600system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1598system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1601system.membus.reqLayer1.occupancy 583066500 # Layer occupancy (ticks) | 1599system.membus.reqLayer1.occupancy 583372000 # Layer occupancy (ticks) |
| 1602system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1600system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1603system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) | 1601system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) |
| 1604system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1602system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1605system.membus.reqLayer3.occupancy 1995956000 # Layer occupancy (ticks) | 1603system.membus.reqLayer3.occupancy 1995485500 # Layer occupancy (ticks) |
| 1606system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1604system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 1607system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) | 1605system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) |
| 1608system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 1606system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 1609system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) | 1607system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) |
| 1610system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 1608system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1611system.membus.respLayer2.occupancy 3161502789 # Layer occupancy (ticks) | 1609system.membus.respLayer2.occupancy 3161579497 # Layer occupancy (ticks) |
| 1612system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 1610system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 1613system.membus.respLayer4.occupancy 54989497 # Layer occupancy (ticks) | 1611system.membus.respLayer4.occupancy 54941740 # Layer occupancy (ticks) |
| 1614system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1615system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1616system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1617system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 1618system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1619system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1620system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1621system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1622system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1623system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1624system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1625system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1626system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1627system.cpu.kern.inst.arm 0 # number of arm instructions executed 1628system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1629 1630---------- End Simulation Statistics ---------- | 1612system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1613system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1614system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1615system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 1616system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1617system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1618system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1619system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1620system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1621system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1622system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1623system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1624system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1625system.cpu.kern.inst.arm 0 # number of arm instructions executed 1626system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1627 1628---------- End Simulation Statistics ---------- |