| stats.txt (10530:533ec854b2f1) | stats.txt (10535:4ccec5baf82c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.125902 # Number of seconds simulated 4sim_ticks 5125902116500 # Number of ticks simulated 5final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.125902 # Number of seconds simulated 4sim_ticks 5125902116500 # Number of ticks simulated 5final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 134346 # Simulator instruction rate (inst/s) 8host_op_rate 265563 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1687822207 # Simulator tick rate (ticks/s) 10host_mem_usage 793660 # Number of bytes of host memory used 11host_seconds 3036.99 # Real time elapsed on the host | 7host_inst_rate 182847 # Simulator instruction rate (inst/s) 8host_op_rate 361437 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2297162464 # Simulator tick rate (ticks/s) 10host_mem_usage 805240 # Number of bytes of host memory used 11host_seconds 2231.41 # Real time elapsed on the host |
| 12sim_insts 408006726 # Number of instructions simulated 13sim_ops 806511598 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 408006726 # Number of instructions simulated 13sim_ops 806511598 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | |
| 17system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
|
| 21system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory |
| 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | |
| 28system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory | 27system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
|
| 32system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory | 32system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory |
| 36system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) | |
| 37system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) |
|
| 41system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s) | 41system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s) | |
| 49system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s) | 48system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s) |
| 52system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s) |
|
| 53system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 185800 # Number of read requests accepted 55system.physmem.writeReqs 149916 # Number of write requests accepted 56system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM --- 241 unchanged lines hidden (view full) --- 302system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ) 303system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ) 304system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ) 305system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ) 306system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ) 307system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ) 308system.physmem.averagePower::0 668.726542 # Core power per rank (mW) 309system.physmem.averagePower::1 668.742609 # Core power per rank (mW) | 53system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 185800 # Number of read requests accepted 55system.physmem.writeReqs 149916 # Number of write requests accepted 56system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM --- 241 unchanged lines hidden (view full) --- 302system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ) 303system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ) 304system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ) 305system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ) 306system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ) 307system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ) 308system.physmem.averagePower::0 668.726542 # Core power per rank (mW) 309system.physmem.averagePower::1 668.742609 # Core power per rank (mW) |
| 310system.membus.trans_dist::ReadReq 662592 # Transaction distribution 311system.membus.trans_dist::ReadResp 662582 # Transaction distribution 312system.membus.trans_dist::WriteReq 13889 # Transaction distribution 313system.membus.trans_dist::WriteResp 13889 # Transaction distribution 314system.membus.trans_dist::Writeback 103196 # Transaction distribution 315system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 316system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 317system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution 318system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution 319system.membus.trans_dist::ReadExReq 133104 # Transaction distribution 320system.membus.trans_dist::ReadExResp 133101 # Transaction distribution 321system.membus.trans_dist::MessageReq 1644 # Transaction distribution 322system.membus.trans_dist::MessageResp 1644 # Transaction distribution 323system.membus.trans_dist::BadAddressError 10 # Transaction distribution 324system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) 325system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes) 334system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) 335system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) 336system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) 337system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) 338system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes) 339system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes) 340system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 341system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 342system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes) 343system.membus.snoops 949 # Total snoops (count) 344system.membus.snoop_fanout::samples 338415 # Request fanout histogram 345system.membus.snoop_fanout::mean 1 # Request fanout histogram 346system.membus.snoop_fanout::stdev 0 # Request fanout histogram 347system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 348system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 349system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram 350system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 351system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 352system.membus.snoop_fanout::min_value 1 # Request fanout histogram 353system.membus.snoop_fanout::max_value 1 # Request fanout histogram 354system.membus.snoop_fanout::total 338415 # Request fanout histogram 355system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks) 356system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 357system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks) 358system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 359system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) 360system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 361system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks) 362system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 363system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) 364system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 365system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) 366system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 367system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks) 368system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 369system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks) 370system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 371system.iocache.tags.replacements 47575 # number of replacements 372system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use 373system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 374system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. 375system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 376system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit. 377system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor 378system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy 379system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy 380system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 381system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 382system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 383system.iocache.tags.tag_accesses 428670 # Number of tag accesses 384system.iocache.tags.data_accesses 428670 # Number of data accesses 385system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 386system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits 387system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses 388system.iocache.ReadReq_misses::total 910 # number of ReadReq misses 389system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses 390system.iocache.demand_misses::total 910 # number of demand (read+write) misses 391system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses 392system.iocache.overall_misses::total 910 # number of overall misses 393system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles 394system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles 395system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles 396system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles 397system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles 398system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles 399system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) 400system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) 401system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 402system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 403system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses 404system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses 405system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses 406system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses 407system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 408system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 409system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 410system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 411system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 412system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 413system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency 414system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency 415system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency 416system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency 417system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency 418system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency 419system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 420system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 422system.iocache.blocked::no_targets 0 # number of cycles access was blocked 423system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 424system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.iocache.fast_writes 46720 # number of fast writes performed 426system.iocache.cache_copies 0 # number of cache copies performed 427system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses 428system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses 429system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses 430system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses 431system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses 432system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses 433system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles 434system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles 435system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles 436system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles 437system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles 438system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles 439system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles 440system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles 441system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 442system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 443system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 444system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 445system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 446system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 447system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency 448system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency 449system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 450system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 451system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 452system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 453system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 454system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 455system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 457system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 458system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 459system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 460system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 461system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 462system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 463system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 464system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 465system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 466system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 467system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 468system.iobus.trans_dist::ReadReq 225681 # Transaction distribution 469system.iobus.trans_dist::ReadResp 225681 # Transaction distribution 470system.iobus.trans_dist::WriteReq 57721 # Transaction distribution 471system.iobus.trans_dist::WriteResp 57721 # Transaction distribution 472system.iobus.trans_dist::MessageReq 1644 # Transaction distribution 473system.iobus.trans_dist::MessageResp 1644 # Transaction distribution 474system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 475system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 477system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 479system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 485system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 486system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) 487system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 488system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 489system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 490system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 491system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 492system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) 493system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) 494system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) 495system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) 496system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) 497system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes) 498system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 504system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 505system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 506system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 507system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 508system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 509system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 510system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) 511system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 512system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 513system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 514system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 515system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 516system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) 517system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) 518system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) 519system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) 520system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) 521system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes) 522system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) 523system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 524system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 525system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 526system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 527system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 528system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) 529system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 530system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 531system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 532system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 533system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 534system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 535system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 536system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 537system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 538system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 539system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 540system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 541system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 542system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 543system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 544system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 545system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 546system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 547system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 548system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) 549system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 550system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 551system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 552system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 553system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 554system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 555system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 556system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 557system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 558system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks) 559system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 560system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 561system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 562system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) 563system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 564system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks) 565system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 566system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) 567system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 568system.cpu_clk_domain.clock 500 # Clock period in ticks | |
| 569system.cpu.branchPred.lookups 86911006 # Number of BP lookups 570system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted 571system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect 572system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups 573system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits 574system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 575system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage 576system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target. 577system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions. | 310system.cpu.branchPred.lookups 86911006 # Number of BP lookups 311system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted 312system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect 313system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups 314system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits 315system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 316system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage 317system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target. 318system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions. |
| 319system.cpu_clk_domain.clock 500 # Clock period in ticks |
|
| 578system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 579system.cpu.numCycles 449563158 # number of cpu cycles simulated 580system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 581system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 582system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss 583system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed 584system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered 585system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken --- 178 unchanged lines hidden (view full) --- 764system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch 765system.cpu.iew.iewDispLoadInsts 17327064 # Number of dispatched load instructions 766system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions 767system.cpu.iew.iewDispNonSpecInsts 714327 # Number of dispatched non-speculative instructions 768system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall 769system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall 770system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations 771system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly | 320system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 321system.cpu.numCycles 449563158 # number of cpu cycles simulated 322system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 323system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 324system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss 325system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed 326system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered 327system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken --- 178 unchanged lines hidden (view full) --- 506system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch 507system.cpu.iew.iewDispLoadInsts 17327064 # Number of dispatched load instructions 508system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions 509system.cpu.iew.iewDispNonSpecInsts 714327 # Number of dispatched non-speculative instructions 510system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall 511system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall 512system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations 513system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly |
| 772system.cpu.iew.predictedNotTakenIncorrect 536897 # Number of branches that were predicted not taken incorrectly 773system.cpu.iew.branchMispredicts 1052437 # Number of branch mispredicts detected at execute | 514system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly 515system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute |
| 774system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions 775system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed 776system.cpu.iew.iewExecSquashedInsts 1477348 # Number of squashed instructions skipped in execute 777system.cpu.iew.exec_swp 0 # number of swp insts executed 778system.cpu.iew.exec_nop 0 # number of nop insts executed 779system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed 780system.cpu.iew.exec_branches 83308581 # Number of branches executed 781system.cpu.iew.exec_stores 9169768 # Number of stores executed --- 86 unchanged lines hidden (view full) --- 868system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads 869system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads 870system.cpu.int_regfile_writes 656162059 # number of integer regfile writes 871system.cpu.fp_regfile_reads 61 # number of floating regfile reads 872system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads 873system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes 874system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads 875system.cpu.misc_regfile_writes 402647 # number of misc regfile writes | 516system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions 517system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed 518system.cpu.iew.iewExecSquashedInsts 1477348 # Number of squashed instructions skipped in execute 519system.cpu.iew.exec_swp 0 # number of swp insts executed 520system.cpu.iew.exec_nop 0 # number of nop insts executed 521system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed 522system.cpu.iew.exec_branches 83308581 # Number of branches executed 523system.cpu.iew.exec_stores 9169768 # Number of stores executed --- 86 unchanged lines hidden (view full) --- 610system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads 611system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads 612system.cpu.int_regfile_writes 656162059 # number of integer regfile writes 613system.cpu.fp_regfile_reads 61 # number of floating regfile reads 614system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads 615system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes 616system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads 617system.cpu.misc_regfile_writes 402647 # number of misc regfile writes |
| 876system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution 877system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution 879system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution 881system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution 883system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution 884system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution 885system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution 887system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes) 888system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes) 889system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes) 890system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes) 891system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes) 892system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes) 893system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes) 894system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes) 895system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes) 896system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes) 897system.cpu.toL2Bus.snoops 58568 # Total snoops (count) 898system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram 899system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram 900system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram 901system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 902system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 903system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram 911system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks) 912system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 913system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) 914system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 915system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks) 916system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 917system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks) 918system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 919system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks) 920system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 618system.cpu.dcache.tags.replacements 1657683 # number of replacements 619system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use 620system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks. 621system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks. 622system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks. 623system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. 624system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor 625system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy 626system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy 627system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 629system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 630system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 631system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 632system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses 633system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses 634system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits 635system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits 636system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits 637system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits 638system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits 639system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits 640system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits 641system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits 642system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits 643system.cpu.dcache.overall_hits::total 19128334 # number of overall hits 644system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses 645system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses 646system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses 647system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses 648system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses 649system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses 650system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses 651system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses 652system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses 653system.cpu.dcache.overall_misses::total 2535648 # number of overall misses 654system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles 655system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles 656system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles 657system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles 658system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles 659system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles 660system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles 661system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles 662system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses) 663system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses) 664system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses) 665system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses) 666system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses) 667system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses) 668system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses 669system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses 670system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses 671system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses 672system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses 674system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses 676system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses 677system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses 678system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses 679system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses 680system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses 681system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency 683system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency 684system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency 685system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency 686system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency 687system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency 688system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency 689system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency 690system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked 691system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 692system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked 693system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 694system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked 695system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 696system.cpu.dcache.fast_writes 0 # number of fast writes performed 697system.cpu.dcache.cache_copies 0 # number of cache copies performed 698system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks 699system.cpu.dcache.writebacks::total 1559289 # number of writebacks 700system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits 701system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits 702system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits 703system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits 704system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits 705system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits 706system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits 707system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits 708system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses 709system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses 710system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses 711system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses 712system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses 713system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses 714system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses 715system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses 716system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses 717system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses 718system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles 719system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles 720system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles 721system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles 722system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles 723system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles 724system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles 725system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles 726system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles 727system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles 728system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles 729system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles 730system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles 731system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles 732system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles 733system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles 734system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses 735system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses 736system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses 737system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses 738system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses 739system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses 740system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses 741system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses 742system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses 743system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency 745system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency 747system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency 748system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency 749system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency 750system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency 751system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency 752system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency 753system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency 754system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 755system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 756system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 757system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 758system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 759system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 760system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 761system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements 762system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use 763system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks. 764system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks. 765system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks. 766system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit. 767system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor 768system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy 769system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy 770system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 771system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 772system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 773system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 774system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 775system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses 776system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses 777system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits 778system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits 779system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits 780system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits 781system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits 782system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits 783system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses 784system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses 785system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses 786system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses 787system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses 788system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses 789system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles 790system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles 791system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles 792system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles 793system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles 794system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles 795system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses) 796system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses) 797system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses 798system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses 799system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses 800system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses 801system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses 802system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses 804system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses 805system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses 806system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses 807system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency 808system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency 809system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency 810system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency 811system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency 812system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency 813system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 820system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 821system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks 822system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks 823system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses 824system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses 825system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses 826system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses 827system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses 828system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses 829system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles 830system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles 831system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles 832system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles 833system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles 834system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles 835system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses 836system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses 837system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses 838system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses 839system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses 840system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses 841system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency 842system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency 843system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency 844system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency 845system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency 846system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency 847system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 923system.cpu.icache.tags.replacements 994393 # number of replacements 924system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use 925system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks. 926system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks. 927system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks. 928system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit. 929system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor 930system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy --- 166 unchanged lines hidden (view full) --- 1097system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses 1098system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency 1099system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency 1100system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency 1101system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency 1102system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency 1103system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency 1104system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 848system.cpu.icache.tags.replacements 994393 # number of replacements 849system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use 850system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks. 851system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks. 852system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks. 853system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit. 854system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor 855system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy --- 166 unchanged lines hidden (view full) --- 1022system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses 1023system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency 1024system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency 1025system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency 1026system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency 1027system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency 1028system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency 1029system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1105system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements 1106system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use 1107system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks. 1108system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks. 1109system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks. 1110system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit. 1111system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor 1112system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy 1113system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy 1114system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 1115system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1116system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 1117system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 1118system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 1119system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses 1120system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses 1121system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits 1122system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits 1123system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits 1124system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits 1125system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits 1126system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits 1127system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses 1128system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses 1129system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses 1130system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses 1131system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses 1132system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses 1133system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles 1134system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles 1135system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles 1136system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles 1137system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles 1138system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles 1139system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses) 1140system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses) 1141system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses 1142system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses 1143system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses 1144system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses 1145system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses 1146system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses 1147system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses 1148system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses 1149system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses 1150system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses 1151system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency 1152system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency 1153system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency 1154system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency 1155system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency 1156system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency 1157system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1158system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1159system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1160system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1161system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1162system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1163system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1164system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 1165system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks 1166system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks 1167system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses 1168system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses 1169system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses 1170system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses 1171system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses 1172system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses 1173system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles 1174system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles 1175system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles 1176system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles 1177system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles 1178system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles 1179system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses 1180system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses 1181system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses 1182system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses 1183system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses 1184system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses 1185system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency 1186system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency 1187system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency 1188system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency 1189system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency 1190system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency 1191system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1192system.cpu.dcache.tags.replacements 1657683 # number of replacements 1193system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use 1194system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks. 1195system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks. 1196system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks. 1197system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. 1198system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor 1199system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy 1200system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy 1201system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1202system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 1203system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 1204system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 1205system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1206system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses 1207system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses 1208system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits 1209system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits 1210system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits 1211system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits 1212system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits 1213system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits 1214system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits 1215system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits 1216system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits 1217system.cpu.dcache.overall_hits::total 19128334 # number of overall hits 1218system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses 1219system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses 1220system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses 1221system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses 1222system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses 1223system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses 1224system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses 1225system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses 1226system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses 1227system.cpu.dcache.overall_misses::total 2535648 # number of overall misses 1228system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles 1229system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles 1230system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles 1231system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles 1232system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles 1233system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles 1234system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles 1235system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles 1236system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses) 1237system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses) 1238system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses) 1239system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses) 1240system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses) 1241system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses) 1242system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses 1243system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses 1244system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses 1245system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses 1246system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses 1247system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses 1248system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses 1249system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses 1250system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses 1251system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses 1252system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses 1253system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses 1254system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses 1255system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses 1256system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency 1257system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency 1258system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency 1259system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency 1260system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency 1261system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency 1262system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency 1263system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency 1264system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked 1265system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1266system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked 1267system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1268system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked 1269system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1270system.cpu.dcache.fast_writes 0 # number of fast writes performed 1271system.cpu.dcache.cache_copies 0 # number of cache copies performed 1272system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks 1273system.cpu.dcache.writebacks::total 1559289 # number of writebacks 1274system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits 1275system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits 1276system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits 1277system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits 1278system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits 1279system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits 1280system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits 1281system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits 1282system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses 1283system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses 1284system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses 1285system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses 1286system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses 1287system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses 1288system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses 1289system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses 1290system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses 1291system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses 1292system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles 1293system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles 1294system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles 1295system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles 1296system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles 1297system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles 1298system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles 1299system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles 1300system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles 1301system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles 1302system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles 1303system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles 1304system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles 1305system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles 1306system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles 1307system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles 1308system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses 1309system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses 1310system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses 1311system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses 1312system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses 1313system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses 1314system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses 1315system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses 1316system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses 1317system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses 1318system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency 1319system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency 1320system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency 1321system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency 1322system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency 1323system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency 1324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency 1325system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency 1326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency 1327system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency 1328system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1329system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1330system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1331system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1332system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1333system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1334system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1335system.cpu.l2cache.tags.replacements 113085 # number of replacements 1336system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use 1337system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks. 1338system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks. 1339system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks. 1340system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1341system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor 1342system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor --- 236 unchanged lines hidden (view full) --- 1579system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency 1580system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1581system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1582system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1583system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1584system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1585system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1586system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1030system.cpu.l2cache.tags.replacements 113085 # number of replacements 1031system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use 1032system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks. 1033system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks. 1034system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks. 1035system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1036system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor 1037system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor --- 236 unchanged lines hidden (view full) --- 1274system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency 1275system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1276system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1277system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1278system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1279system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1280system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1281system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1282system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution 1283system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution 1284system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution 1285system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution 1286system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution 1287system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution 1288system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution 1289system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution 1290system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution 1291system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution 1292system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution 1293system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes) 1294system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes) 1295system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes) 1296system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes) 1297system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes) 1298system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes) 1299system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes) 1300system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes) 1301system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes) 1302system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes) 1303system.cpu.toL2Bus.snoops 58568 # Total snoops (count) 1304system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram 1305system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram 1306system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram 1307system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1308system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1309system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1310system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1311system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram 1312system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram 1313system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1314system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1315system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1316system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram 1317system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks) 1318system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1319system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) 1320system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1321system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks) 1322system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1323system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks) 1324system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1325system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks) 1326system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1327system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks) 1328system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1329system.iobus.trans_dist::ReadReq 225681 # Transaction distribution 1330system.iobus.trans_dist::ReadResp 225681 # Transaction distribution 1331system.iobus.trans_dist::WriteReq 57721 # Transaction distribution 1332system.iobus.trans_dist::WriteResp 57721 # Transaction distribution 1333system.iobus.trans_dist::MessageReq 1644 # Transaction distribution 1334system.iobus.trans_dist::MessageResp 1644 # Transaction distribution 1335system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1336system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1337system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 1338system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1339system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1340system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 1341system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1342system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1343system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 1344system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1345system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 1346system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1347system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) 1348system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1349system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1350system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1351system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1352system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1353system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) 1354system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) 1355system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) 1356system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) 1357system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) 1358system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes) 1359system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1360system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1361system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 1362system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1363system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1364system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 1365system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1366system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1367system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 1368system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1369system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 1370system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1371system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) 1372system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1373system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1374system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1375system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1376system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1377system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) 1378system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) 1379system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) 1380system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) 1381system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) 1382system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes) 1383system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) 1384system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1385system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1386system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1387system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1388system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1389system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) 1390system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1391system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1392system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1393system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1394system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1395system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 1396system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1397system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1398system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1399system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1400system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1401system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 1402system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1403system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1404system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1405system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1406system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1407system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 1408system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1409system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) 1410system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1411system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 1412system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1413system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1414system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1415system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1416system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1417system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1418system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1419system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks) 1420system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1421system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 1422system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1423system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) 1424system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1425system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks) 1426system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1427system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) 1428system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1429system.iocache.tags.replacements 47575 # number of replacements 1430system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use 1431system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1432system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. 1433system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1434system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit. 1435system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor 1436system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy 1437system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy 1438system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1439system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1440system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1441system.iocache.tags.tag_accesses 428670 # Number of tag accesses 1442system.iocache.tags.data_accesses 428670 # Number of data accesses 1443system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 1444system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits 1445system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses 1446system.iocache.ReadReq_misses::total 910 # number of ReadReq misses 1447system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses 1448system.iocache.demand_misses::total 910 # number of demand (read+write) misses 1449system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses 1450system.iocache.overall_misses::total 910 # number of overall misses 1451system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles 1452system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles 1453system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles 1454system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles 1455system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles 1456system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles 1457system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) 1458system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) 1459system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1460system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 1461system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses 1462system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses 1463system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses 1464system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses 1465system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1466system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1467system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1468system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1469system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1470system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1471system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency 1472system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency 1473system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency 1474system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency 1475system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency 1476system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency 1477system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 1478system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1479system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 1480system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1481system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 1482system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1483system.iocache.fast_writes 46720 # number of fast writes performed 1484system.iocache.cache_copies 0 # number of cache copies performed 1485system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses 1486system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses 1487system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses 1488system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses 1489system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses 1490system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses 1491system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles 1492system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles 1493system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles 1494system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles 1495system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles 1496system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles 1497system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles 1498system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles 1499system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1500system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1501system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1502system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1503system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1504system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1505system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency 1506system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency 1507system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 1508system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1509system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 1510system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 1511system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 1512system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 1513system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1514system.membus.trans_dist::ReadReq 662592 # Transaction distribution 1515system.membus.trans_dist::ReadResp 662582 # Transaction distribution 1516system.membus.trans_dist::WriteReq 13889 # Transaction distribution 1517system.membus.trans_dist::WriteResp 13889 # Transaction distribution 1518system.membus.trans_dist::Writeback 103196 # Transaction distribution 1519system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1520system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 1521system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution 1522system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution 1523system.membus.trans_dist::ReadExReq 133104 # Transaction distribution 1524system.membus.trans_dist::ReadExResp 133101 # Transaction distribution 1525system.membus.trans_dist::MessageReq 1644 # Transaction distribution 1526system.membus.trans_dist::MessageResp 1644 # Transaction distribution 1527system.membus.trans_dist::BadAddressError 10 # Transaction distribution 1528system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) 1529system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) 1530system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) 1531system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) 1532system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes) 1533system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes) 1534system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes) 1535system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes) 1536system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes) 1537system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes) 1538system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) 1539system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) 1540system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) 1541system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) 1542system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes) 1543system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes) 1544system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 1545system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 1546system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes) 1547system.membus.snoops 949 # Total snoops (count) 1548system.membus.snoop_fanout::samples 338415 # Request fanout histogram 1549system.membus.snoop_fanout::mean 1 # Request fanout histogram 1550system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1551system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1552system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1553system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram 1554system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1555system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1556system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1557system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1558system.membus.snoop_fanout::total 338415 # Request fanout histogram 1559system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks) 1560system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1561system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks) 1562system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1563system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) 1564system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1565system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks) 1566system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1567system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) 1568system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 1569system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) 1570system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1571system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks) 1572system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1573system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks) 1574system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1575system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1576system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1577system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 1578system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1579system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1580system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1581system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1582system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1583system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1584system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1585system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1586system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
|
| 1587system.cpu.kern.inst.arm 0 # number of arm instructions executed 1588system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1589 1590---------- End Simulation Statistics ---------- | 1587system.cpu.kern.inst.arm 0 # number of arm instructions executed 1588system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1589 1590---------- End Simulation Statistics ---------- |