| stats.txt (10452:be23c690f8c0) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.125902 # Number of seconds simulated 4sim_ticks 5125902116500 # Number of ticks simulated 5final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.125902 # Number of seconds simulated 4sim_ticks 5125902116500 # Number of ticks simulated 5final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 254798 # Simulator instruction rate (inst/s) 8host_op_rate 503662 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3201100243 # Simulator tick rate (ticks/s) 10host_mem_usage 749084 # Number of bytes of host memory used 11host_seconds 1601.29 # Real time elapsed on the host | 7host_inst_rate 196886 # Simulator instruction rate (inst/s) 8host_op_rate 389187 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2473535129 # Simulator tick rate (ticks/s) 10host_mem_usage 743248 # Number of bytes of host memory used 11host_seconds 2072.30 # Real time elapsed on the host |
| 12sim_insts 408006726 # Number of instructions simulated 13sim_ops 806511598 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory --- 401 unchanged lines hidden (view full) --- 421system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 422system.iocache.blocked::no_targets 0 # number of cycles access was blocked 423system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 424system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.iocache.fast_writes 46720 # number of fast writes performed 426system.iocache.cache_copies 0 # number of cache copies performed 427system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses 428system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses | 12sim_insts 408006726 # Number of instructions simulated 13sim_ops 806511598 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory --- 401 unchanged lines hidden (view full) --- 421system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 422system.iocache.blocked::no_targets 0 # number of cycles access was blocked 423system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 424system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.iocache.fast_writes 46720 # number of fast writes performed 426system.iocache.cache_copies 0 # number of cache copies performed 427system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses 428system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses |
| 429system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 430system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses | |
| 431system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses 432system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses 433system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses 434system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses 435system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles 436system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles 437system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles 438system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles 439system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles 440system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles 441system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles 442system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles 443system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 444system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 429system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses 430system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses 431system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses 432system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses 433system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles 434system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles 435system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles 436system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles 437system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles 438system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles 439system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles 440system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles 441system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 442system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 445system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 446system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses | |
| 447system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 448system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 449system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 450system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 451system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency 452system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency | 443system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 444system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 445system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 446system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 447system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency 448system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency |
| 453system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60928.460338 # average WriteInvalidateReq mshr miss latency 454system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60928.460338 # average WriteInvalidateReq mshr miss latency | 449system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 450system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 455system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 456system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 457system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 458system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 459system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 460system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 461system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 462system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). --- 1132 unchanged lines hidden --- | 451system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 452system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 453system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 454system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 455system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 457system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 458system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). --- 1132 unchanged lines hidden --- |