| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.129874 # Number of seconds simulated 4sim_ticks 5129873616500 # Number of ticks simulated 5final_tick 5129873616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.129877 # Number of seconds simulated 4sim_ticks 5129876981500 # Number of ticks simulated 5final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 122712 # Simulator instruction rate (inst/s) 8host_op_rate 242564 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1543734215 # Simulator tick rate (ticks/s) 10host_mem_usage 750608 # Number of bytes of host memory used 11host_seconds 3323.03 # Real time elapsed on the host 12sim_insts 407773893 # Number of instructions simulated 13sim_ops 806048632 # Number of ops (including micro ops) simulated | 7host_inst_rate 179907 # Simulator instruction rate (inst/s) 8host_op_rate 355619 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2263051238 # Simulator tick rate (ticks/s) 10host_mem_usage 804092 # Number of bytes of host memory used 11host_seconds 2266.80 # Real time elapsed on the host 12sim_insts 407812863 # Number of instructions simulated 13sim_ops 806114915 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1049344 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10817792 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11900032 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1049344 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1049344 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6600896 # Number of bytes written to this memory | 17system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1048192 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10832768 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11913792 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1048192 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1048192 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6597248 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory | 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 9590976 # Number of bytes written to this memory | 26system.physmem.bytes_written::total 9587328 # Number of bytes written to this memory |
| 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 16396 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 169028 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 185938 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 103139 # Number of write requests responded to by this memory | 28system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 16378 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 169262 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 186153 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 103082 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory | 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 149859 # Number of write requests responded to by this memory | 35system.physmem.num_writes::total 149802 # Number of write requests responded to by this memory |
| 36system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.dtb.walker 823 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 204556 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 2108783 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2319751 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 204556 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 204556 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1286756 # Write bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu.dtb.walker 798 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 204331 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 2111701 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2322432 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 204331 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 204331 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1286044 # Write bandwidth from this memory (bytes/s) |
| 45system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s) | 45system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_write::total 1869632 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1286756 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 588403 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 823 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 204556 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 2108783 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4189384 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 185938 # Number of read requests accepted 55system.physmem.writeReqs 149859 # Number of write requests accepted 56system.physmem.readBursts 185938 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 149859 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11881152 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9589248 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 11900032 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 9590976 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue | 46system.physmem.bw_write::total 1868920 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1286044 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 588402 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 798 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 204331 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 2111701 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4191352 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 186153 # Number of read requests accepted 55system.physmem.writeReqs 149802 # Number of write requests accepted 56system.physmem.readBursts 186153 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 149802 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11895360 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 18432 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9586112 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 11913792 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 9587328 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue |
| 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 65system.physmem.neitherReadNorWriteReqs 1710 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11383 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10659 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11850 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11657 # Per bank write bursts 70system.physmem.perBankRdBursts::4 11883 # Per bank write bursts 71system.physmem.perBankRdBursts::5 11508 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11028 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11462 # Per bank write bursts 74system.physmem.perBankRdBursts::8 11217 # Per bank write bursts 75system.physmem.perBankRdBursts::9 11477 # Per bank write bursts 76system.physmem.perBankRdBursts::10 11649 # Per bank write bursts 77system.physmem.perBankRdBursts::11 12129 # Per bank write bursts 78system.physmem.perBankRdBursts::12 11737 # Per bank write bursts 79system.physmem.perBankRdBursts::13 12518 # Per bank write bursts 80system.physmem.perBankRdBursts::14 12268 # Per bank write bursts 81system.physmem.perBankRdBursts::15 11218 # Per bank write bursts 82system.physmem.perBankWrBursts::0 10090 # Per bank write bursts 83system.physmem.perBankWrBursts::1 9375 # Per bank write bursts 84system.physmem.perBankWrBursts::2 9103 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8918 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9314 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9243 # Per bank write bursts 88system.physmem.perBankWrBursts::6 8603 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8925 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9240 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9268 # Per bank write bursts 92system.physmem.perBankWrBursts::10 9747 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9397 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9475 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9702 # Per bank write bursts 96system.physmem.perBankWrBursts::14 10013 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9419 # Per bank write bursts | 65system.physmem.neitherReadNorWriteReqs 1739 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11465 # Per bank write bursts 67system.physmem.perBankRdBursts::1 11004 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11873 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11540 # Per bank write bursts 70system.physmem.perBankRdBursts::4 11961 # Per bank write bursts 71system.physmem.perBankRdBursts::5 11322 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11640 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11420 # Per bank write bursts 74system.physmem.perBankRdBursts::8 11351 # Per bank write bursts 75system.physmem.perBankRdBursts::9 11861 # Per bank write bursts 76system.physmem.perBankRdBursts::10 11826 # Per bank write bursts 77system.physmem.perBankRdBursts::11 12031 # Per bank write bursts 78system.physmem.perBankRdBursts::12 11538 # Per bank write bursts 79system.physmem.perBankRdBursts::13 12375 # Per bank write bursts 80system.physmem.perBankRdBursts::14 11569 # Per bank write bursts 81system.physmem.perBankRdBursts::15 11089 # Per bank write bursts 82system.physmem.perBankWrBursts::0 10234 # Per bank write bursts 83system.physmem.perBankWrBursts::1 9627 # Per bank write bursts 84system.physmem.perBankWrBursts::2 9640 # Per bank write bursts 85system.physmem.perBankWrBursts::3 9149 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9237 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9047 # Per bank write bursts 88system.physmem.perBankWrBursts::6 8744 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8727 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9070 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9221 # Per bank write bursts 92system.physmem.perBankWrBursts::10 9815 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9405 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9499 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9604 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9640 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9124 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 4 # Number of times write queue was full causing retry 100system.physmem.totGap 5129873502000 # Total gap between requests | 99system.physmem.numWrRetry 2 # Number of times write queue was full causing retry 100system.physmem.totGap 5129876930000 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 185938 # Read request sizes (log2) | 107system.physmem.readPktSize::6 186153 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 149859 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 170868 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 11901 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2132 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 408 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 52 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 149802 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 171145 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 11892 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2095 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 399 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see |
| 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see | 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see |
| 126system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see | 126system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see |
| 128system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see --- 18 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 128system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see --- 18 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2274 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3008 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7218 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 7696 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 7847 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 8666 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 8996 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 9690 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 10286 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11378 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10590 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9936 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 9091 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 8900 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7829 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7668 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7590 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 251 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 193 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 186 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 160 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 14 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 71875 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 298.717718 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 177.081512 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 320.465816 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 27438 38.17% 38.17% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 17395 24.20% 62.38% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 7359 10.24% 72.61% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 4225 5.88% 78.49% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2947 4.10% 82.59% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 2054 2.86% 85.45% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1404 1.95% 87.40% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1166 1.62% 89.03% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7887 10.97% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 71875 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 7354 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 25.241501 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 560.072825 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 7353 99.99% 99.99% # Reads before turning the bus around for writes | 162system.physmem.wrQLenPdf::15 2222 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2928 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7174 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 7679 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 7821 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 8641 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 8986 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 9732 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 10392 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11488 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10681 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9974 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 9218 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 9052 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7930 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7716 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7761 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7619 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 106 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 102 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 101 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 129 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 110 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 72700 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 295.480165 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 175.038242 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 318.841917 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 28215 38.81% 38.81% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 17447 24.00% 62.81% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 7490 10.30% 73.11% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 4112 5.66% 78.77% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 3047 4.19% 82.96% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 2009 2.76% 85.72% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1387 1.91% 87.63% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1145 1.57% 89.20% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7848 10.80% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 72700 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 7372 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 25.211883 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 559.387781 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 7371 99.99% 99.99% # Reads before turning the bus around for writes |
| 229system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes | 229system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::total 7354 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 7354 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.374218 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.656947 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.477131 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 6319 85.93% 85.93% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 51 0.69% 86.62% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 33 0.45% 87.07% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 263 3.58% 90.64% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 273 3.71% 94.36% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 24 0.33% 94.68% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 24 0.33% 95.01% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 15 0.20% 95.21% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 39 0.53% 95.74% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 6 0.08% 95.83% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 3 0.04% 95.87% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 1 0.01% 95.88% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 229 3.11% 98.99% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 5 0.07% 99.06% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 3 0.04% 99.10% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 2 0.03% 99.13% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 25 0.34% 99.47% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 13 0.18% 99.65% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::112-115 5 0.07% 99.78% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::124-127 2 0.03% 99.82% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::128-131 10 0.14% 99.96% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 7354 # Writes before turning the bus around for reads 262system.physmem.totQLat 1988147750 # Total ticks spent queuing 263system.physmem.totMemAccLat 5468954000 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 928215000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 10709.52 # Average queueing delay per DRAM burst | 230system.physmem.rdPerTurnAround::total 7372 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 7372 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.317824 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.630780 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.249046 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 6322 85.76% 85.76% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 58 0.79% 86.54% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 24 0.33% 86.87% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 276 3.74% 90.61% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 291 3.95% 94.56% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 18 0.24% 94.80% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 12 0.16% 94.97% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 14 0.19% 95.16% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 37 0.50% 95.66% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 4 0.05% 95.71% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 3 0.04% 95.75% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 3 0.04% 95.79% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 249 3.38% 99.17% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 3 0.04% 99.21% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 4 0.05% 99.27% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 4 0.05% 99.32% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 19 0.26% 99.58% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::96-99 7 0.09% 99.69% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::108-111 2 0.03% 99.74% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::112-115 6 0.08% 99.82% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::116-119 1 0.01% 99.84% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.01% 99.85% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 7 0.09% 99.95% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 7372 # Writes before turning the bus around for reads 265system.physmem.totQLat 2030519500 # Total ticks spent queuing 266system.physmem.totMemAccLat 5515488250 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 929325000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 10924.70 # Average queueing delay per DRAM burst |
| 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 267system.physmem.avgMemAccLat 29459.52 # Average memory access latency per DRAM burst | 270system.physmem.avgMemAccLat 29674.70 # Average memory access latency per DRAM burst |
| 268system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.03 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes | 271system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.03 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes |
| 276system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing 277system.physmem.avgWrQLen 22.59 # Average write queue length when enqueuing 278system.physmem.readRowHits 152685 # Number of row buffer hits during reads 279system.physmem.writeRowHits 110914 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes 282system.physmem.avgGap 15276710.34 # Average gap between requests 283system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined 284system.physmem.memoryStateTime::IDLE 4923726743250 # Time in different power states | 279system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 25.68 # Average write queue length when enqueuing 281system.physmem.readRowHits 152396 # Number of row buffer hits during reads 282system.physmem.writeRowHits 110551 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 73.80 # Row buffer hit rate for writes 285system.physmem.avgGap 15269535.89 # Average gap between requests 286system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 4923406969000 # Time in different power states |
| 285system.physmem.memoryStateTime::REF 171297620000 # Time in different power states 286system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 288system.physmem.memoryStateTime::REF 171297620000 # Time in different power states 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 287system.physmem.memoryStateTime::ACT 34849149750 # Time in different power states | 290system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states |
| 288system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 289system.membus.throughput 4545861 # Throughput (bytes/s) 290system.membus.trans_dist::ReadReq 662568 # Transaction distribution 291system.membus.trans_dist::ReadResp 662557 # Transaction distribution | 292system.membus.trans_dist::ReadReq 662528 # Transaction distribution 293system.membus.trans_dist::ReadResp 662520 # Transaction distribution |
| 292system.membus.trans_dist::WriteReq 13776 # Transaction distribution 293system.membus.trans_dist::WriteResp 13776 # Transaction distribution | 294system.membus.trans_dist::WriteReq 13776 # Transaction distribution 295system.membus.trans_dist::WriteResp 13776 # Transaction distribution |
| 294system.membus.trans_dist::Writeback 103139 # Transaction distribution | 296system.membus.trans_dist::Writeback 103082 # Transaction distribution |
| 295system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 296system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 297system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 298system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 297system.membus.trans_dist::UpgradeReq 2217 # Transaction distribution 298system.membus.trans_dist::UpgradeResp 1710 # Transaction distribution 299system.membus.trans_dist::ReadExReq 133156 # Transaction distribution 300system.membus.trans_dist::ReadExResp 133153 # Transaction distribution 301system.membus.trans_dist::MessageReq 1644 # Transaction distribution 302system.membus.trans_dist::MessageResp 1644 # Transaction distribution 303system.membus.trans_dist::BadAddressError 11 # Transaction distribution 304system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) | 299system.membus.trans_dist::UpgradeReq 2203 # Transaction distribution 300system.membus.trans_dist::UpgradeResp 1739 # Transaction distribution 301system.membus.trans_dist::ReadExReq 133413 # Transaction distribution 302system.membus.trans_dist::ReadExResp 133410 # Transaction distribution 303system.membus.trans_dist::MessageReq 1645 # Transaction distribution 304system.membus.trans_dist::MessageResp 1645 # Transaction distribution 305system.membus.trans_dist::BadAddressError 8 # Transaction distribution 306system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) |
| 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) | 308system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) |
| 308system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478059 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 22 # Packet count per connected master and slave (bytes) 310system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724235 # Packet count per connected master and slave (bytes) 311system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94797 # Packet count per connected master and slave (bytes) 312system.membus.pkt_count_system.iocache.mem_side::total 94797 # Packet count per connected master and slave (bytes) 313system.membus.pkt_count::total 1822320 # Packet count per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) 316system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) 317system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) 318system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18472576 # Cumulative packet size per connected master and slave (bytes) 319system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20264541 # Cumulative packet size per connected master and slave (bytes) 320system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size::total 23289549 # Cumulative packet size per connected master and slave (bytes) 323system.membus.data_through_bus 23289549 # Total data (bytes) 324system.membus.snoop_data_through_bus 30144 # Total snoop data (bytes) 325system.membus.reqLayer0.occupancy 251288000 # Layer occupancy (ticks) | 310system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478447 # Packet count per connected master and slave (bytes) 311system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) 312system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724617 # Packet count per connected master and slave (bytes) 313system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94802 # Packet count per connected master and slave (bytes) 314system.membus.pkt_count_system.iocache.mem_side::total 94802 # Packet count per connected master and slave (bytes) 315system.membus.pkt_count::total 1822709 # Packet count per connected master and slave (bytes) 316system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) 317system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) 318system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) 319system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) 320system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18482688 # Cumulative packet size per connected master and slave (bytes) 321system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20274653 # Cumulative packet size per connected master and slave (bytes) 322system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 323system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 324system.membus.pkt_size::total 23299665 # Cumulative packet size per connected master and slave (bytes) 325system.membus.snoops 943 # Total snoops (count) 326system.membus.snoop_fanout::samples 338647 # Request fanout histogram 327system.membus.snoop_fanout::mean 1 # Request fanout histogram 328system.membus.snoop_fanout::stdev 0 # Request fanout histogram 329system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 330system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 331system.membus.snoop_fanout::1 338647 100.00% 100.00% # Request fanout histogram 332system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 333system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 334system.membus.snoop_fanout::min_value 1 # Request fanout histogram 335system.membus.snoop_fanout::max_value 1 # Request fanout histogram 336system.membus.snoop_fanout::total 338647 # Request fanout histogram 337system.membus.reqLayer0.occupancy 251233500 # Layer occupancy (ticks) |
| 326system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 338system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 327system.membus.reqLayer1.occupancy 583699000 # Layer occupancy (ticks) | 339system.membus.reqLayer1.occupancy 583254000 # Layer occupancy (ticks) |
| 328system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 340system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 329system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) | 341system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) |
| 330system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 342system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 331system.membus.reqLayer3.occupancy 1574361000 # Layer occupancy (ticks) | 343system.membus.reqLayer3.occupancy 1574333248 # Layer occupancy (ticks) |
| 332system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 344system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 333system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) | 345system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) |
| 334system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 346system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 335system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) | 347system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) |
| 336system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 348system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 337system.membus.respLayer2.occupancy 3158618040 # Layer occupancy (ticks) | 349system.membus.respLayer2.occupancy 3160566012 # Layer occupancy (ticks) |
| 338system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 350system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 339system.membus.respLayer4.occupancy 54966743 # Layer occupancy (ticks) | 351system.membus.respLayer4.occupancy 55015741 # Layer occupancy (ticks) |
| 340system.membus.respLayer4.utilization 0.0 # Layer utilization (%) | 352system.membus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 341system.iocache.tags.replacements 47579 # number of replacements 342system.iocache.tags.tagsinuse 0.103859 # Cycle average of tags in use | 353system.iocache.tags.replacements 47584 # number of replacements 354system.iocache.tags.tagsinuse 0.103867 # Cycle average of tags in use |
| 343system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 355system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 344system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. | 356system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. |
| 345system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 357system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 346system.iocache.tags.warmup_cycle 4992945696000 # Cycle when the warmup percentage was hit. 347system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103859 # Average occupied blocks per requestor 348system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006491 # Average percentage of cache occupancy 349system.iocache.tags.occ_percent::total 0.006491 # Average percentage of cache occupancy | 358system.iocache.tags.warmup_cycle 4992945897000 # Cycle when the warmup percentage was hit. 359system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103867 # Average occupied blocks per requestor 360system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006492 # Average percentage of cache occupancy 361system.iocache.tags.occ_percent::total 0.006492 # Average percentage of cache occupancy |
| 350system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 351system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 352system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 362system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 363system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 364system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 353system.iocache.tags.tag_accesses 428706 # Number of tag accesses 354system.iocache.tags.data_accesses 428706 # Number of data accesses | 365system.iocache.tags.tag_accesses 428751 # Number of tag accesses 366system.iocache.tags.data_accesses 428751 # Number of data accesses |
| 355system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 356system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits | 367system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 368system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits |
| 357system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses 358system.iocache.ReadReq_misses::total 914 # number of ReadReq misses 359system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses 360system.iocache.demand_misses::total 914 # number of demand (read+write) misses 361system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses 362system.iocache.overall_misses::total 914 # number of overall misses 363system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152667446 # number of ReadReq miss cycles 364system.iocache.ReadReq_miss_latency::total 152667446 # number of ReadReq miss cycles 365system.iocache.demand_miss_latency::pc.south_bridge.ide 152667446 # number of demand (read+write) miss cycles 366system.iocache.demand_miss_latency::total 152667446 # number of demand (read+write) miss cycles 367system.iocache.overall_miss_latency::pc.south_bridge.ide 152667446 # number of overall miss cycles 368system.iocache.overall_miss_latency::total 152667446 # number of overall miss cycles 369system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) 370system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) | 369system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses 370system.iocache.ReadReq_misses::total 919 # number of ReadReq misses 371system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses 372system.iocache.demand_misses::total 919 # number of demand (read+write) misses 373system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses 374system.iocache.overall_misses::total 919 # number of overall misses 375system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 156299196 # number of ReadReq miss cycles 376system.iocache.ReadReq_miss_latency::total 156299196 # number of ReadReq miss cycles 377system.iocache.demand_miss_latency::pc.south_bridge.ide 156299196 # number of demand (read+write) miss cycles 378system.iocache.demand_miss_latency::total 156299196 # number of demand (read+write) miss cycles 379system.iocache.overall_miss_latency::pc.south_bridge.ide 156299196 # number of overall miss cycles 380system.iocache.overall_miss_latency::total 156299196 # number of overall miss cycles 381system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) 382system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) |
| 371system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 372system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) | 383system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 384system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) |
| 373system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses 374system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses 375system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses 376system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses | 385system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses 386system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses 387system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses 388system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses |
| 377system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 378system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 379system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 380system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 381system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 382system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 389system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 390system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 391system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 392system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 393system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 394system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 383system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average ReadReq miss latency 384system.iocache.ReadReq_avg_miss_latency::total 167032.216630 # average ReadReq miss latency 385system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency 386system.iocache.demand_avg_miss_latency::total 167032.216630 # average overall miss latency 387system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency 388system.iocache.overall_avg_miss_latency::total 167032.216630 # average overall miss latency | 395system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average ReadReq miss latency 396system.iocache.ReadReq_avg_miss_latency::total 170075.294886 # average ReadReq miss latency 397system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency 398system.iocache.demand_avg_miss_latency::total 170075.294886 # average overall miss latency 399system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency 400system.iocache.overall_avg_miss_latency::total 170075.294886 # average overall miss latency |
| 389system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 390system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 392system.iocache.blocked::no_targets 0 # number of cycles access was blocked 393system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 394system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.iocache.fast_writes 46720 # number of fast writes performed 396system.iocache.cache_copies 0 # number of cache copies performed | 401system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 402system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 404system.iocache.blocked::no_targets 0 # number of cycles access was blocked 405system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 406system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 407system.iocache.fast_writes 46720 # number of fast writes performed 408system.iocache.cache_copies 0 # number of cache copies performed |
| 397system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses 398system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses | 409system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses 410system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses |
| 399system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 400system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses | 411system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 412system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses |
| 401system.iocache.demand_mshr_misses::pc.south_bridge.ide 914 # number of demand (read+write) MSHR misses 402system.iocache.demand_mshr_misses::total 914 # number of demand (read+write) MSHR misses 403system.iocache.overall_mshr_misses::pc.south_bridge.ide 914 # number of overall MSHR misses 404system.iocache.overall_mshr_misses::total 914 # number of overall MSHR misses 405system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of ReadReq MSHR miss cycles 406system.iocache.ReadReq_mshr_miss_latency::total 105114946 # number of ReadReq MSHR miss cycles 407system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2850047667 # number of WriteInvalidateReq MSHR miss cycles 408system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2850047667 # number of WriteInvalidateReq MSHR miss cycles 409system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of demand (read+write) MSHR miss cycles 410system.iocache.demand_mshr_miss_latency::total 105114946 # number of demand (read+write) MSHR miss cycles 411system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of overall MSHR miss cycles 412system.iocache.overall_mshr_miss_latency::total 105114946 # number of overall MSHR miss cycles | 413system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses 414system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses 415system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses 416system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses 417system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of ReadReq MSHR miss cycles 418system.iocache.ReadReq_mshr_miss_latency::total 108481196 # number of ReadReq MSHR miss cycles 419system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2843906419 # number of WriteInvalidateReq MSHR miss cycles 420system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2843906419 # number of WriteInvalidateReq MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of demand (read+write) MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::total 108481196 # number of demand (read+write) MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of overall MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::total 108481196 # number of overall MSHR miss cycles |
| 413system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 414system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 415system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 416system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 417system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 418system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 419system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 420system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 425system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 427system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 428system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 429system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 421system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average ReadReq mshr miss latency 422system.iocache.ReadReq_avg_mshr_miss_latency::total 115005.411379 # average ReadReq mshr miss latency 423system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61002.732598 # average WriteInvalidateReq mshr miss latency 424system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61002.732598 # average WriteInvalidateReq mshr miss latency 425system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency 426system.iocache.demand_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency 427system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency 428system.iocache.overall_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency | 433system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707 # average ReadReq mshr miss latency 435system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653 # average WriteInvalidateReq mshr miss latency 436system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653 # average WriteInvalidateReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency |
| 429system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 430system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 431system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 432system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 433system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 434system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 435system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 436system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 437system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 438system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 439system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 440system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 441system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 444system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 445system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 446system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 447system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 448system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 453system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 442system.iobus.throughput 638663 # Throughput (bytes/s) 443system.iobus.trans_dist::ReadReq 225570 # Transaction distribution 444system.iobus.trans_dist::ReadResp 225570 # Transaction distribution | 454system.iobus.trans_dist::ReadReq 225575 # Transaction distribution 455system.iobus.trans_dist::ReadResp 225575 # Transaction distribution |
| 445system.iobus.trans_dist::WriteReq 57606 # Transaction distribution 446system.iobus.trans_dist::WriteResp 57606 # Transaction distribution | 456system.iobus.trans_dist::WriteReq 57606 # Transaction distribution 457system.iobus.trans_dist::WriteResp 57606 # Transaction distribution |
| 447system.iobus.trans_dist::MessageReq 1644 # Transaction distribution 448system.iobus.trans_dist::MessageResp 1644 # Transaction distribution | 458system.iobus.trans_dist::MessageReq 1645 # Transaction distribution 459system.iobus.trans_dist::MessageResp 1645 # Transaction distribution |
| 449system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 450system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 451system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 452system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 453system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 454system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 455system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 456system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 457system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 458system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 459system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 460system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 461system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 462system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 463system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 464system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 465system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 466system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 467system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) | 460system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 461system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 462system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 463system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 464system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 465system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 466system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 467system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 468system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 469system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 470system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 471system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 472system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 473system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 474system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 475system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 477system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) |
| 468system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes) 469system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes) 470system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) 471system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) 472system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes) 473system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 474system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 475system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 476system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 477system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 478system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 479system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 480system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 481system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 482system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 483system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 484system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 485system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 486system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 487system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 488system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 489system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 490system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 491system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) 492system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes) 493system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes) 494system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) 495system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) 496system.iobus.tot_pkt_size::total 3276260 # Cumulative packet size per connected master and slave (bytes) 497system.iobus.data_through_bus 3276260 # Total data (bytes) 498system.iobus.reqLayer0.occupancy 3918185 # Layer occupancy (ticks) | 479system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count::total 569652 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 485system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 486system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 487system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 488system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 489system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 490system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 491system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 492system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 493system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 494system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 495system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 496system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 497system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 498system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) 504system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) 505system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) 506system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) 507system.iobus.pkt_size::total 3276304 # Cumulative packet size per connected master and slave (bytes) 508system.iobus.reqLayer0.occupancy 3920684 # Layer occupancy (ticks) |
| 499system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 500system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 501system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 502system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 503system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 504system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) 505system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 506system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) --- 19 unchanged lines hidden (view full) --- 526system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 527system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 528system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 529system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 530system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 531system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 532system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 533system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 509system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 510system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 511system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 512system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 513system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 514system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) 515system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 516system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) --- 19 unchanged lines hidden (view full) --- 536system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 537system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 538system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 539system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 540system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 541system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 542system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 543system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 534system.iobus.reqLayer18.occupancy 422017356 # Layer occupancy (ticks) | 544system.iobus.reqLayer18.occupancy 422027356 # Layer occupancy (ticks) |
| 535system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 536system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 537system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 538system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) 539system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 545system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 546system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 547system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 548system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) 549system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 540system.iobus.respLayer1.occupancy 52370257 # Layer occupancy (ticks) | 550system.iobus.respLayer1.occupancy 52381259 # Layer occupancy (ticks) |
| 541system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 551system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 542system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) | 552system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) |
| 543system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 544system.cpu_clk_domain.clock 500 # Clock period in ticks | 553system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 554system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 545system.cpu.branchPred.lookups 86877356 # Number of BP lookups 546system.cpu.branchPred.condPredicted 86877356 # Number of conditional branches predicted 547system.cpu.branchPred.condIncorrect 902542 # Number of conditional branches incorrect 548system.cpu.branchPred.BTBLookups 80133511 # Number of BTB lookups 549system.cpu.branchPred.BTBHits 78163225 # Number of BTB hits | 555system.cpu.branchPred.lookups 86898883 # Number of BP lookups 556system.cpu.branchPred.condPredicted 86898883 # Number of conditional branches predicted 557system.cpu.branchPred.condIncorrect 901790 # Number of conditional branches incorrect 558system.cpu.branchPred.BTBLookups 80120336 # Number of BTB lookups 559system.cpu.branchPred.BTBHits 78166165 # Number of BTB hits |
| 550system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 560system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 551system.cpu.branchPred.BTBHitPct 97.541246 # BTB Hit Percentage 552system.cpu.branchPred.usedRAS 1555611 # Number of times the RAS was used to get a target. 553system.cpu.branchPred.RASInCorrect 178528 # Number of incorrect RAS predictions. | 561system.cpu.branchPred.BTBHitPct 97.560955 # BTB Hit Percentage 562system.cpu.branchPred.usedRAS 1553548 # Number of times the RAS was used to get a target. 563system.cpu.branchPred.RASInCorrect 177807 # Number of incorrect RAS predictions. |
| 554system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 564system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 555system.cpu.numCycles 449309558 # number of cpu cycles simulated | 565system.cpu.numCycles 449490093 # number of cpu cycles simulated |
| 556system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 557system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 566system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 567system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 558system.cpu.fetch.icacheStallCycles 27651859 # Number of cycles fetch is stalled on an Icache miss 559system.cpu.fetch.Insts 428959611 # Number of instructions fetch has processed 560system.cpu.fetch.Branches 86877356 # Number of branches that fetch encountered 561system.cpu.fetch.predictedBranches 79718836 # Number of branches that fetch has predicted taken 562system.cpu.fetch.Cycles 417653044 # Number of cycles fetch has run and was not squashing or blocked 563system.cpu.fetch.SquashCycles 1892712 # Number of cycles fetch has spent squashing 564system.cpu.fetch.TlbCycles 141479 # Number of cycles fetch has spent waiting for tlb 565system.cpu.fetch.MiscStallCycles 49827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 566system.cpu.fetch.PendingTrapStallCycles 205407 # Number of stall cycles due to pending traps 567system.cpu.fetch.PendingQuiesceStallCycles 127451 # Number of stall cycles due to pending quiesce instructions 568system.cpu.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR 569system.cpu.fetch.CacheLines 9182196 # Number of cache lines fetched 570system.cpu.fetch.IcacheSquashes 444767 # Number of outstanding Icache misses that were squashed 571system.cpu.fetch.ItlbSquashes 5009 # Number of outstanding ITLB misses that were squashed 572system.cpu.fetch.rateDist::samples 446775840 # Number of instructions fetched each cycle (Total) 573system.cpu.fetch.rateDist::mean 1.894723 # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::stdev 3.051895 # Number of instructions fetched each cycle (Total) | 568system.cpu.fetch.icacheStallCycles 27736713 # Number of cycles fetch is stalled on an Icache miss 569system.cpu.fetch.Insts 428990683 # Number of instructions fetch has processed 570system.cpu.fetch.Branches 86898883 # Number of branches that fetch encountered 571system.cpu.fetch.predictedBranches 79719713 # Number of branches that fetch has predicted taken 572system.cpu.fetch.Cycles 417726391 # Number of cycles fetch has run and was not squashing or blocked 573system.cpu.fetch.SquashCycles 1890728 # Number of cycles fetch has spent squashing 574system.cpu.fetch.TlbCycles 147536 # Number of cycles fetch has spent waiting for tlb 575system.cpu.fetch.MiscStallCycles 50079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 576system.cpu.fetch.PendingTrapStallCycles 202600 # Number of stall cycles due to pending traps 577system.cpu.fetch.PendingQuiesceStallCycles 127031 # Number of stall cycles due to pending quiesce instructions 578system.cpu.fetch.IcacheWaitRetryStallCycles 405 # Number of stall cycles due to full MSHR 579system.cpu.fetch.CacheLines 9184683 # Number of cache lines fetched 580system.cpu.fetch.IcacheSquashes 447260 # Number of outstanding Icache misses that were squashed 581system.cpu.fetch.ItlbSquashes 5357 # Number of outstanding ITLB misses that were squashed 582system.cpu.fetch.rateDist::samples 446936119 # Number of instructions fetched each cycle (Total) 583system.cpu.fetch.rateDist::mean 1.894164 # Number of instructions fetched each cycle (Total) 584system.cpu.fetch.rateDist::stdev 3.051823 # Number of instructions fetched each cycle (Total) |
| 575system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 585system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 576system.cpu.fetch.rateDist::0 281257253 62.95% 62.95% # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::1 2318085 0.52% 63.47% # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::2 72134929 16.15% 79.62% # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.rateDist::3 1613434 0.36% 79.98% # Number of instructions fetched each cycle (Total) 580system.cpu.fetch.rateDist::4 2149929 0.48% 80.46% # Number of instructions fetched each cycle (Total) 581system.cpu.fetch.rateDist::5 2328393 0.52% 80.98% # Number of instructions fetched each cycle (Total) 582system.cpu.fetch.rateDist::6 1530698 0.34% 81.32% # Number of instructions fetched each cycle (Total) 583system.cpu.fetch.rateDist::7 1882713 0.42% 81.74% # Number of instructions fetched each cycle (Total) 584system.cpu.fetch.rateDist::8 81560406 18.26% 100.00% # Number of instructions fetched each cycle (Total) | 586system.cpu.fetch.rateDist::0 281459283 62.98% 62.98% # Number of instructions fetched each cycle (Total) 587system.cpu.fetch.rateDist::1 2262059 0.51% 63.48% # Number of instructions fetched each cycle (Total) 588system.cpu.fetch.rateDist::2 72137620 16.14% 79.62% # Number of instructions fetched each cycle (Total) 589system.cpu.fetch.rateDist::3 1613997 0.36% 79.98% # Number of instructions fetched each cycle (Total) 590system.cpu.fetch.rateDist::4 2155091 0.48% 80.47% # Number of instructions fetched each cycle (Total) 591system.cpu.fetch.rateDist::5 2322801 0.52% 80.98% # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.rateDist::6 1535694 0.34% 81.33% # Number of instructions fetched each cycle (Total) 593system.cpu.fetch.rateDist::7 1854025 0.41% 81.74% # Number of instructions fetched each cycle (Total) 594system.cpu.fetch.rateDist::8 81595549 18.26% 100.00% # Number of instructions fetched each cycle (Total) |
| 585system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 586system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 587system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 595system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 588system.cpu.fetch.rateDist::total 446775840 # Number of instructions fetched each cycle (Total) 589system.cpu.fetch.branchRate 0.193357 # Number of branch fetches per cycle 590system.cpu.fetch.rate 0.954708 # Number of inst fetches per cycle 591system.cpu.decode.IdleCycles 23023114 # Number of cycles decode is idle 592system.cpu.decode.BlockedCycles 264661195 # Number of cycles decode is blocked 593system.cpu.decode.RunCycles 150717323 # Number of cycles decode is running 594system.cpu.decode.UnblockCycles 7427852 # Number of cycles decode is unblocking 595system.cpu.decode.SquashCycles 946356 # Number of cycles decode is squashing 596system.cpu.decode.DecodedInsts 838299668 # Number of instructions handled by decode 597system.cpu.rename.SquashCycles 946356 # Number of cycles rename is squashing 598system.cpu.rename.IdleCycles 25879231 # Number of cycles rename is idle 599system.cpu.rename.BlockCycles 223164657 # Number of cycles rename is blocking 600system.cpu.rename.serializeStallCycles 13208529 # count of cycles rename stalled for serializing inst 601system.cpu.rename.RunCycles 154609969 # Number of cycles rename is running 602system.cpu.rename.UnblockCycles 28967098 # Number of cycles rename is unblocking 603system.cpu.rename.RenamedInsts 834812666 # Number of instructions processed by rename 604system.cpu.rename.ROBFullEvents 479412 # Number of times rename has blocked due to ROB full 605system.cpu.rename.IQFullEvents 12346095 # Number of times rename has blocked due to IQ full 606system.cpu.rename.LQFullEvents 191662 # Number of times rename has blocked due to LQ full 607system.cpu.rename.SQFullEvents 13684658 # Number of times rename has blocked due to SQ full 608system.cpu.rename.RenamedOperands 997151203 # Number of destination operands rename has renamed 609system.cpu.rename.RenameLookups 1813191058 # Number of register rename lookups that rename has made 610system.cpu.rename.int_rename_lookups 1114665342 # Number of integer rename lookups 611system.cpu.rename.fp_rename_lookups 185 # Number of floating rename lookups 612system.cpu.rename.CommittedMaps 963963482 # Number of HB maps that are committed 613system.cpu.rename.UndoneMaps 33187719 # Number of HB maps that are undone due to squashing 614system.cpu.rename.serializingInsts 468373 # count of serializing insts renamed 615system.cpu.rename.tempSerializingInsts 472487 # count of temporary serializing insts renamed 616system.cpu.rename.skidInsts 39006494 # count of insts added to the skid buffer 617system.cpu.memDep0.insertedLoads 17336272 # Number of loads inserted to the mem dependence unit. 618system.cpu.memDep0.insertedStores 10188880 # Number of stores inserted to the mem dependence unit. 619system.cpu.memDep0.conflictingLoads 1345741 # Number of conflicting loads. 620system.cpu.memDep0.conflictingStores 1123547 # Number of conflicting stores. 621system.cpu.iq.iqInstsAdded 829275749 # Number of instructions added to the IQ (excludes non-spec) 622system.cpu.iq.iqNonSpecInstsAdded 1209290 # Number of non-speculative instructions added to the IQ 623system.cpu.iq.iqInstsIssued 824021244 # Number of instructions issued 624system.cpu.iq.iqSquashedInstsIssued 242579 # Number of squashed instructions issued 625system.cpu.iq.iqSquashedInstsExamined 23492118 # Number of squashed instructions iterated over during squash; mainly for profiling 626system.cpu.iq.iqSquashedOperandsExamined 36175819 # Number of squashed operands that are examined and possibly removed from graph 627system.cpu.iq.iqSquashedNonSpecRemoved 154222 # Number of squashed non-spec instructions that were removed 628system.cpu.iq.issued_per_cycle::samples 446775840 # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::mean 1.844373 # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::stdev 2.418251 # Number of insts issued each cycle | 598system.cpu.fetch.rateDist::total 446936119 # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.branchRate 0.193328 # Number of branch fetches per cycle 600system.cpu.fetch.rate 0.954394 # Number of inst fetches per cycle 601system.cpu.decode.IdleCycles 23065529 # Number of cycles decode is idle 602system.cpu.decode.BlockedCycles 264763767 # Number of cycles decode is blocked 603system.cpu.decode.RunCycles 150736142 # Number of cycles decode is running 604system.cpu.decode.UnblockCycles 7425317 # Number of cycles decode is unblocking 605system.cpu.decode.SquashCycles 945364 # Number of cycles decode is squashing 606system.cpu.decode.DecodedInsts 838360092 # Number of instructions handled by decode 607system.cpu.rename.SquashCycles 945364 # Number of cycles rename is squashing 608system.cpu.rename.IdleCycles 25914691 # Number of cycles rename is idle 609system.cpu.rename.BlockCycles 223241691 # Number of cycles rename is blocking 610system.cpu.rename.serializeStallCycles 13213057 # count of cycles rename stalled for serializing inst 611system.cpu.rename.RunCycles 154633432 # Number of cycles rename is running 612system.cpu.rename.UnblockCycles 28987884 # Number of cycles rename is unblocking 613system.cpu.rename.RenamedInsts 834905613 # Number of instructions processed by rename 614system.cpu.rename.ROBFullEvents 478581 # Number of times rename has blocked due to ROB full 615system.cpu.rename.IQFullEvents 12335118 # Number of times rename has blocked due to IQ full 616system.cpu.rename.LQFullEvents 182483 # Number of times rename has blocked due to LQ full 617system.cpu.rename.SQFullEvents 13727584 # Number of times rename has blocked due to SQ full 618system.cpu.rename.RenamedOperands 997265714 # Number of destination operands rename has renamed 619system.cpu.rename.RenameLookups 1813395255 # Number of register rename lookups that rename has made 620system.cpu.rename.int_rename_lookups 1114768158 # Number of integer rename lookups 621system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups 622system.cpu.rename.CommittedMaps 964051126 # Number of HB maps that are committed 623system.cpu.rename.UndoneMaps 33214586 # Number of HB maps that are undone due to squashing 624system.cpu.rename.serializingInsts 466449 # count of serializing insts renamed 625system.cpu.rename.tempSerializingInsts 470370 # count of temporary serializing insts renamed 626system.cpu.rename.skidInsts 38986770 # count of insts added to the skid buffer 627system.cpu.memDep0.insertedLoads 17343174 # Number of loads inserted to the mem dependence unit. 628system.cpu.memDep0.insertedStores 10196687 # Number of stores inserted to the mem dependence unit. 629system.cpu.memDep0.conflictingLoads 1348761 # Number of conflicting loads. 630system.cpu.memDep0.conflictingStores 1124760 # Number of conflicting stores. 631system.cpu.iq.iqInstsAdded 829365293 # Number of instructions added to the IQ (excludes non-spec) 632system.cpu.iq.iqNonSpecInstsAdded 1208199 # Number of non-speculative instructions added to the IQ 633system.cpu.iq.iqInstsIssued 824078412 # Number of instructions issued 634system.cpu.iq.iqSquashedInstsIssued 244412 # Number of squashed instructions issued 635system.cpu.iq.iqSquashedInstsExamined 23515910 # Number of squashed instructions iterated over during squash; mainly for profiling 636system.cpu.iq.iqSquashedOperandsExamined 36291432 # Number of squashed operands that are examined and possibly removed from graph 637system.cpu.iq.iqSquashedNonSpecRemoved 152927 # Number of squashed non-spec instructions that were removed 638system.cpu.iq.issued_per_cycle::samples 446936119 # Number of insts issued each cycle 639system.cpu.iq.issued_per_cycle::mean 1.843839 # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::stdev 2.418170 # Number of insts issued each cycle |
| 631system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 641system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 632system.cpu.iq.issued_per_cycle::0 262561849 58.77% 58.77% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::1 13882888 3.11% 61.88% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::2 10086827 2.26% 64.13% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::3 6921999 1.55% 65.68% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::4 74315249 16.63% 82.32% # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::5 4452451 1.00% 83.31% # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::6 72780033 16.29% 99.60% # Number of insts issued each cycle 639system.cpu.iq.issued_per_cycle::7 1201096 0.27% 99.87% # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::8 573448 0.13% 100.00% # Number of insts issued each cycle | 642system.cpu.iq.issued_per_cycle::0 262716607 58.78% 58.78% # Number of insts issued each cycle 643system.cpu.iq.issued_per_cycle::1 13881580 3.11% 61.89% # Number of insts issued each cycle 644system.cpu.iq.issued_per_cycle::2 10086185 2.26% 64.14% # Number of insts issued each cycle 645system.cpu.iq.issued_per_cycle::3 6914821 1.55% 65.69% # Number of insts issued each cycle 646system.cpu.iq.issued_per_cycle::4 74322504 16.63% 82.32% # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::5 4455510 1.00% 83.32% # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::6 72776226 16.28% 99.60% # Number of insts issued each cycle 649system.cpu.iq.issued_per_cycle::7 1206411 0.27% 99.87% # Number of insts issued each cycle 650system.cpu.iq.issued_per_cycle::8 576275 0.13% 100.00% # Number of insts issued each cycle |
| 641system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 642system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 643system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 651system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 652system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 653system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 644system.cpu.iq.issued_per_cycle::total 446775840 # Number of insts issued each cycle | 654system.cpu.iq.issued_per_cycle::total 446936119 # Number of insts issued each cycle |
| 645system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 655system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 646system.cpu.iq.fu_full::IntAlu 1974933 71.79% 71.79% # attempts to use FU when none available 647system.cpu.iq.fu_full::IntMult 151 0.01% 71.79% # attempts to use FU when none available 648system.cpu.iq.fu_full::IntDiv 606 0.02% 71.81% # attempts to use FU when none available 649system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.81% # attempts to use FU when none available 650system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.81% # attempts to use FU when none available 651system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.81% # attempts to use FU when none available 652system.cpu.iq.fu_full::FloatMult 0 0.00% 71.81% # attempts to use FU when none available 653system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.81% # attempts to use FU when none available 654system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.81% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.81% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.81% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.81% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.81% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.81% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.81% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdMult 0 0.00% 71.81% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.81% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdShift 0 0.00% 71.81% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.81% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.81% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.81% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.81% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.81% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.81% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.81% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.81% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.81% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.81% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.81% # attempts to use FU when none available 675system.cpu.iq.fu_full::MemRead 614459 22.33% 94.15% # attempts to use FU when none available 676system.cpu.iq.fu_full::MemWrite 161026 5.85% 100.00% # attempts to use FU when none available | 656system.cpu.iq.fu_full::IntAlu 1975200 71.80% 71.80% # attempts to use FU when none available 657system.cpu.iq.fu_full::IntMult 252 0.01% 71.81% # attempts to use FU when none available 658system.cpu.iq.fu_full::IntDiv 1109 0.04% 71.85% # attempts to use FU when none available 659system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available 660system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available 661system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available 662system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available 663system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available 664system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available 685system.cpu.iq.fu_full::MemRead 614218 22.33% 94.18% # attempts to use FU when none available 686system.cpu.iq.fu_full::MemWrite 160061 5.82% 100.00% # attempts to use FU when none available |
| 677system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 678system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 687system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 688system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 679system.cpu.iq.FU_type_0::No_OpClass 292875 0.04% 0.04% # Type of FU issued 680system.cpu.iq.FU_type_0::IntAlu 795624977 96.55% 96.59% # Type of FU issued 681system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.61% # Type of FU issued 682system.cpu.iq.FU_type_0::IntDiv 125321 0.02% 96.62% # Type of FU issued | 689system.cpu.iq.FU_type_0::No_OpClass 293084 0.04% 0.04% # Type of FU issued 690system.cpu.iq.FU_type_0::IntAlu 795671914 96.55% 96.59% # Type of FU issued 691system.cpu.iq.FU_type_0::IntMult 150614 0.02% 96.61% # Type of FU issued 692system.cpu.iq.FU_type_0::IntDiv 125303 0.02% 96.62% # Type of FU issued |
| 683system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued 684system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued 685system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued 686system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued 687system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued 688system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued 689system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued 690system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 701system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued 702system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued 704system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued 705system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued 706system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued | 693system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued 694system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued 695system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued 696system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued 697system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued 698system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 711system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued 715system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued 716system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued 717system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued 718system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued |
| 709system.cpu.iq.FU_type_0::MemRead 18429310 2.24% 98.86% # Type of FU issued 710system.cpu.iq.FU_type_0::MemWrite 9398312 1.14% 100.00% # Type of FU issued | 719system.cpu.iq.FU_type_0::MemRead 18435146 2.24% 98.86% # Type of FU issued 720system.cpu.iq.FU_type_0::MemWrite 9402351 1.14% 100.00% # Type of FU issued |
| 711system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 712system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 721system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 722system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 713system.cpu.iq.FU_type_0::total 824021244 # Type of FU issued 714system.cpu.iq.rate 1.833972 # Inst issue rate 715system.cpu.iq.fu_busy_cnt 2751175 # FU busy when requested 716system.cpu.iq.fu_busy_rate 0.003339 # FU busy rate (busy events/executed inst) 717system.cpu.iq.int_inst_queue_reads 2097811864 # Number of integer instruction queue reads 718system.cpu.iq.int_inst_queue_writes 853989635 # Number of integer instruction queue writes 719system.cpu.iq.int_inst_queue_wakeup_accesses 819447653 # Number of integer instruction queue wakeup accesses 720system.cpu.iq.fp_inst_queue_reads 217 # Number of floating instruction queue reads 721system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes 722system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses 723system.cpu.iq.int_alu_accesses 826479445 # Number of integer alu accesses 724system.cpu.iq.fp_alu_accesses 99 # Number of floating point alu accesses 725system.cpu.iew.lsq.thread0.forwLoads 1882501 # Number of loads that had data forwarded from stores | 723system.cpu.iq.FU_type_0::total 824078412 # Type of FU issued 724system.cpu.iq.rate 1.833363 # Inst issue rate 725system.cpu.iq.fu_busy_cnt 2750840 # FU busy when requested 726system.cpu.iq.fu_busy_rate 0.003338 # FU busy rate (busy events/executed inst) 727system.cpu.iq.int_inst_queue_reads 2098087999 # Number of integer instruction queue reads 728system.cpu.iq.int_inst_queue_writes 854102050 # Number of integer instruction queue writes 729system.cpu.iq.int_inst_queue_wakeup_accesses 819507550 # Number of integer instruction queue wakeup accesses 730system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads 731system.cpu.iq.fp_inst_queue_writes 194 # Number of floating instruction queue writes 732system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses 733system.cpu.iq.int_alu_accesses 826536078 # Number of integer alu accesses 734system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses 735system.cpu.iew.lsq.thread0.forwLoads 1879985 # Number of loads that had data forwarded from stores |
| 726system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 736system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 727system.cpu.iew.lsq.thread0.squashedLoads 3343168 # Number of loads squashed 728system.cpu.iew.lsq.thread0.ignoredResponses 14800 # Number of memory responses ignored because the instruction is squashed 729system.cpu.iew.lsq.thread0.memOrderViolation 14469 # Number of memory ordering violations 730system.cpu.iew.lsq.thread0.squashedStores 1764190 # Number of stores squashed | 737system.cpu.iew.lsq.thread0.squashedLoads 3343174 # Number of loads squashed 738system.cpu.iew.lsq.thread0.ignoredResponses 14903 # Number of memory responses ignored because the instruction is squashed 739system.cpu.iew.lsq.thread0.memOrderViolation 14336 # Number of memory ordering violations 740system.cpu.iew.lsq.thread0.squashedStores 1767440 # Number of stores squashed |
| 731system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 732system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 741system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 742system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 733system.cpu.iew.lsq.thread0.rescheduledLoads 2224524 # Number of loads that were rescheduled 734system.cpu.iew.lsq.thread0.cacheBlocked 72794 # Number of times an access to memory failed due to the cache being blocked | 743system.cpu.iew.lsq.thread0.rescheduledLoads 2224972 # Number of loads that were rescheduled 744system.cpu.iew.lsq.thread0.cacheBlocked 73807 # Number of times an access to memory failed due to the cache being blocked |
| 735system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 745system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 736system.cpu.iew.iewSquashCycles 946356 # Number of cycles IEW is squashing 737system.cpu.iew.iewBlockCycles 205489198 # Number of cycles IEW is blocking 738system.cpu.iew.iewUnblockCycles 9385897 # Number of cycles IEW is unblocking 739system.cpu.iew.iewDispatchedInsts 830485039 # Number of instructions dispatched to IQ 740system.cpu.iew.iewDispSquashedInsts 188872 # Number of squashed instructions skipped by dispatch 741system.cpu.iew.iewDispLoadInsts 17336272 # Number of dispatched load instructions 742system.cpu.iew.iewDispStoreInsts 10188880 # Number of dispatched store instructions 743system.cpu.iew.iewDispNonSpecInsts 713065 # Number of dispatched non-speculative instructions 744system.cpu.iew.iewIQFullEvents 415930 # Number of times the IQ has become full, causing a stall 745system.cpu.iew.iewLSQFullEvents 8070911 # Number of times the LSQ has become full, causing a stall 746system.cpu.iew.memOrderViolationEvents 14469 # Number of memory order violations 747system.cpu.iew.predictedTakenIncorrect 518528 # Number of branches that were predicted taken incorrectly 748system.cpu.iew.predictedNotTakenIncorrect 536731 # Number of branches that were predicted not taken incorrectly 749system.cpu.iew.branchMispredicts 1055259 # Number of branch mispredicts detected at execute 750system.cpu.iew.iewExecutedInsts 822394413 # Number of executed instructions 751system.cpu.iew.iewExecLoadInsts 18030482 # Number of load instructions executed 752system.cpu.iew.iewExecSquashedInsts 1492613 # Number of squashed instructions skipped in execute | 746system.cpu.iew.iewSquashCycles 945364 # Number of cycles IEW is squashing 747system.cpu.iew.iewBlockCycles 205481336 # Number of cycles IEW is blocking 748system.cpu.iew.iewUnblockCycles 9444308 # Number of cycles IEW is unblocking 749system.cpu.iew.iewDispatchedInsts 830573492 # Number of instructions dispatched to IQ 750system.cpu.iew.iewDispSquashedInsts 185181 # Number of squashed instructions skipped by dispatch 751system.cpu.iew.iewDispLoadInsts 17343194 # Number of dispatched load instructions 752system.cpu.iew.iewDispStoreInsts 10196687 # Number of dispatched store instructions 753system.cpu.iew.iewDispNonSpecInsts 711600 # Number of dispatched non-speculative instructions 754system.cpu.iew.iewIQFullEvents 416792 # Number of times the IQ has become full, causing a stall 755system.cpu.iew.iewLSQFullEvents 8129202 # Number of times the LSQ has become full, causing a stall 756system.cpu.iew.memOrderViolationEvents 14336 # Number of memory order violations 757system.cpu.iew.predictedTakenIncorrect 515306 # Number of branches that were predicted taken incorrectly 758system.cpu.iew.predictedNotTakenIncorrect 539272 # Number of branches that were predicted not taken incorrectly 759system.cpu.iew.branchMispredicts 1054578 # Number of branch mispredicts detected at execute 760system.cpu.iew.iewExecutedInsts 822459197 # Number of executed instructions 761system.cpu.iew.iewExecLoadInsts 18034619 # Number of load instructions executed 762system.cpu.iew.iewExecSquashedInsts 1483642 # Number of squashed instructions skipped in execute |
| 753system.cpu.iew.exec_swp 0 # number of swp insts executed 754system.cpu.iew.exec_nop 0 # number of nop insts executed | 763system.cpu.iew.exec_swp 0 # number of swp insts executed 764system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 755system.cpu.iew.exec_refs 27200783 # number of memory reference insts executed 756system.cpu.iew.exec_branches 83281301 # Number of branches executed 757system.cpu.iew.exec_stores 9170301 # Number of stores executed 758system.cpu.iew.exec_rate 1.830351 # Inst execution rate 759system.cpu.iew.wb_sent 821885746 # cumulative count of insts sent to commit 760system.cpu.iew.wb_count 819447713 # cumulative count of insts written-back 761system.cpu.iew.wb_producers 640810294 # num instructions producing a value 762system.cpu.iew.wb_consumers 1050192124 # num instructions consuming a value | 765system.cpu.iew.exec_refs 27209233 # number of memory reference insts executed 766system.cpu.iew.exec_branches 83289157 # Number of branches executed 767system.cpu.iew.exec_stores 9174614 # Number of stores executed 768system.cpu.iew.exec_rate 1.829760 # Inst execution rate 769system.cpu.iew.wb_sent 821946704 # cumulative count of insts sent to commit 770system.cpu.iew.wb_count 819507606 # cumulative count of insts written-back 771system.cpu.iew.wb_producers 640910074 # num instructions producing a value 772system.cpu.iew.wb_consumers 1050315789 # num instructions consuming a value |
| 763system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 773system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 764system.cpu.iew.wb_rate 1.823793 # insts written-back per cycle 765system.cpu.iew.wb_fanout 0.610184 # average fanout of values written-back | 774system.cpu.iew.wb_rate 1.823194 # insts written-back per cycle 775system.cpu.iew.wb_fanout 0.610207 # average fanout of values written-back |
| 766system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 776system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 767system.cpu.commit.commitSquashedInsts 24342460 # The number of squashed insts skipped by commit 768system.cpu.commit.commitNonSpecStalls 1055068 # The number of times commit has been forced to stall to communicate backwards 769system.cpu.commit.branchMispredicts 914367 # The number of times a branch was mispredicted 770system.cpu.commit.committed_per_cycle::samples 443118746 # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::mean 1.819035 # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::stdev 2.675250 # Number of insts commited each cycle | 777system.cpu.commit.commitSquashedInsts 24363502 # The number of squashed insts skipped by commit 778system.cpu.commit.commitNonSpecStalls 1055272 # The number of times commit has been forced to stall to communicate backwards 779system.cpu.commit.branchMispredicts 913280 # The number of times a branch was mispredicted 780system.cpu.commit.committed_per_cycle::samples 443273616 # Number of insts commited each cycle 781system.cpu.commit.committed_per_cycle::mean 1.818549 # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::stdev 2.675153 # Number of insts commited each cycle |
| 773system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 783system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 774system.cpu.commit.committed_per_cycle::0 272366005 61.47% 61.47% # Number of insts commited each cycle 775system.cpu.commit.committed_per_cycle::1 11194221 2.53% 63.99% # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::2 3590232 0.81% 64.80% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::3 74521712 16.82% 81.62% # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::4 2434404 0.55% 82.17% # Number of insts commited each cycle 779system.cpu.commit.committed_per_cycle::5 1603700 0.36% 82.53% # Number of insts commited each cycle 780system.cpu.commit.committed_per_cycle::6 952599 0.21% 82.75% # Number of insts commited each cycle 781system.cpu.commit.committed_per_cycle::7 71009883 16.03% 98.77% # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::8 5445990 1.23% 100.00% # Number of insts commited each cycle | 784system.cpu.commit.committed_per_cycle::0 272516770 61.48% 61.48% # Number of insts commited each cycle 785system.cpu.commit.committed_per_cycle::1 11195258 2.53% 64.00% # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::2 3583043 0.81% 64.81% # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::3 74523250 16.81% 81.62% # Number of insts commited each cycle 788system.cpu.commit.committed_per_cycle::4 2432181 0.55% 82.17% # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::5 1605992 0.36% 82.54% # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::6 951269 0.21% 82.75% # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::7 71009301 16.02% 98.77% # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::8 5456552 1.23% 100.00% # Number of insts commited each cycle |
| 783system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 784system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 785system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 793system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 786system.cpu.commit.committed_per_cycle::total 443118746 # Number of insts commited each cycle 787system.cpu.commit.committedInsts 407773893 # Number of instructions committed 788system.cpu.commit.committedOps 806048632 # Number of ops (including micro ops) committed | 796system.cpu.commit.committed_per_cycle::total 443273616 # Number of insts commited each cycle 797system.cpu.commit.committedInsts 407812863 # Number of instructions committed 798system.cpu.commit.committedOps 806114915 # Number of ops (including micro ops) committed |
| 789system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 799system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 790system.cpu.commit.refs 22417793 # Number of memory references committed 791system.cpu.commit.loads 13993103 # Number of loads committed 792system.cpu.commit.membars 474875 # Number of memory barriers committed 793system.cpu.commit.branches 82158924 # Number of branches committed | 800system.cpu.commit.refs 22429266 # Number of memory references committed 801system.cpu.commit.loads 14000019 # Number of loads committed 802system.cpu.commit.membars 474889 # Number of memory barriers committed 803system.cpu.commit.branches 82168190 # Number of branches committed |
| 794system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 804system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 795system.cpu.commit.int_insts 734892496 # Number of committed integer instructions. 796system.cpu.commit.function_calls 1155452 # Number of function calls committed. 797system.cpu.commit.op_class_0::No_OpClass 174150 0.02% 0.02% # Class of committed instruction 798system.cpu.commit.op_class_0::IntAlu 783190673 97.16% 97.19% # Class of committed instruction 799system.cpu.commit.op_class_0::IntMult 144749 0.02% 97.20% # Class of committed instruction 800system.cpu.commit.op_class_0::IntDiv 121267 0.02% 97.22% # Class of committed instruction | 805system.cpu.commit.int_insts 734958550 # Number of committed integer instructions. 806system.cpu.commit.function_calls 1155635 # Number of function calls committed. 807system.cpu.commit.op_class_0::No_OpClass 174258 0.02% 0.02% # Class of committed instruction 808system.cpu.commit.op_class_0::IntAlu 783245185 97.16% 97.18% # Class of committed instruction 809system.cpu.commit.op_class_0::IntMult 144842 0.02% 97.20% # Class of committed instruction 810system.cpu.commit.op_class_0::IntDiv 121364 0.02% 97.22% # Class of committed instruction |
| 801system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 802system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 803system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction 804system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 805system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 806system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 807system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 808system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction --- 10 unchanged lines hidden (view full) --- 819system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 820system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 821system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 822system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 824system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 825system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction | 811system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 812system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 813system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction 814system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 815system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 816system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 817system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 818system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction --- 10 unchanged lines hidden (view full) --- 829system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 830system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 832system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 833system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 834system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction |
| 827system.cpu.commit.op_class_0::MemRead 13993103 1.74% 98.95% # Class of committed instruction 828system.cpu.commit.op_class_0::MemWrite 8424690 1.05% 100.00% # Class of committed instruction | 837system.cpu.commit.op_class_0::MemRead 14000019 1.74% 98.95% # Class of committed instruction 838system.cpu.commit.op_class_0::MemWrite 8429247 1.05% 100.00% # Class of committed instruction |
| 829system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 830system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 839system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 840system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 831system.cpu.commit.op_class_0::total 806048632 # Class of committed instruction 832system.cpu.commit.bw_lim_events 5445990 # number cycles where commit BW limit reached | 841system.cpu.commit.op_class_0::total 806114915 # Class of committed instruction 842system.cpu.commit.bw_lim_events 5456552 # number cycles where commit BW limit reached |
| 833system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 843system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 834system.cpu.rob.rob_reads 1267985613 # The number of ROB reads 835system.cpu.rob.rob_writes 1664458820 # The number of ROB writes 836system.cpu.timesIdled 297027 # Number of times that the entire CPU went into an idle state and unscheduled itself 837system.cpu.idleCycles 2533718 # Total number of cycles that the CPU has spent unscheduled due to idling 838system.cpu.quiesceCycles 9810435335 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 839system.cpu.committedInsts 407773893 # Number of Instructions Simulated 840system.cpu.committedOps 806048632 # Number of Ops (including micro ops) Simulated 841system.cpu.cpi 1.101860 # CPI: Cycles Per Instruction 842system.cpu.cpi_total 1.101860 # CPI: Total CPI of All Threads 843system.cpu.ipc 0.907557 # IPC: Instructions Per Cycle 844system.cpu.ipc_total 0.907557 # IPC: Total IPC of All Threads 845system.cpu.int_regfile_reads 1092201088 # number of integer regfile reads 846system.cpu.int_regfile_writes 655889202 # number of integer regfile writes 847system.cpu.fp_regfile_reads 60 # number of floating regfile reads 848system.cpu.cc_regfile_reads 416095530 # number of cc regfile reads 849system.cpu.cc_regfile_writes 321948927 # number of cc regfile writes 850system.cpu.misc_regfile_reads 265553416 # number of misc regfile reads 851system.cpu.misc_regfile_writes 402606 # number of misc regfile writes 852system.cpu.toL2Bus.throughput 55008962 # Throughput (bytes/s) 853system.cpu.toL2Bus.trans_dist::ReadReq 3071462 # Transaction distribution 854system.cpu.toL2Bus.trans_dist::ReadResp 3070914 # Transaction distribution | 844system.cpu.rob.rob_reads 1268217156 # The number of ROB reads 845system.cpu.rob.rob_writes 1664635865 # The number of ROB writes 846system.cpu.timesIdled 297982 # Number of times that the entire CPU went into an idle state and unscheduled itself 847system.cpu.idleCycles 2553974 # Total number of cycles that the CPU has spent unscheduled due to idling 848system.cpu.quiesceCycles 9810264132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 849system.cpu.committedInsts 407812863 # Number of Instructions Simulated 850system.cpu.committedOps 806114915 # Number of Ops (including micro ops) Simulated 851system.cpu.cpi 1.102197 # CPI: Cycles Per Instruction 852system.cpu.cpi_total 1.102197 # CPI: Total CPI of All Threads 853system.cpu.ipc 0.907279 # IPC: Instructions Per Cycle 854system.cpu.ipc_total 0.907279 # IPC: Total IPC of All Threads 855system.cpu.int_regfile_reads 1092267062 # number of integer regfile reads 856system.cpu.int_regfile_writes 655932610 # number of integer regfile writes 857system.cpu.fp_regfile_reads 56 # number of floating regfile reads 858system.cpu.cc_regfile_reads 416128291 # number of cc regfile reads 859system.cpu.cc_regfile_writes 321990784 # number of cc regfile writes 860system.cpu.misc_regfile_reads 265578345 # number of misc regfile reads 861system.cpu.misc_regfile_writes 402863 # number of misc regfile writes 862system.cpu.toL2Bus.trans_dist::ReadReq 3083726 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::ReadResp 3083187 # Transaction distribution |
| 855system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution 856system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution | 864system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution |
| 857system.cpu.toL2Bus.trans_dist::Writeback 1585837 # Transaction distribution 858system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution 859system.cpu.toL2Bus.trans_dist::UpgradeReq 2242 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::UpgradeResp 2242 # Transaction distribution 861system.cpu.toL2Bus.trans_dist::ReadExReq 287030 # Transaction distribution 862system.cpu.toL2Bus.trans_dist::ReadExResp 287030 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::BadAddressError 11 # Transaction distribution 864system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1996026 # Packet count per connected master and slave (bytes) 865system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130754 # Packet count per connected master and slave (bytes) 866system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30653 # Packet count per connected master and slave (bytes) 867system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 164256 # Packet count per connected master and slave (bytes) 868system.cpu.toL2Bus.pkt_count::total 8321689 # Packet count per connected master and slave (bytes) 869system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63869504 # Cumulative packet size per connected master and slave (bytes) 870system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207903453 # Cumulative packet size per connected master and slave (bytes) 871system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 978368 # Cumulative packet size per connected master and slave (bytes) 872system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5729920 # Cumulative packet size per connected master and slave (bytes) 873system.cpu.toL2Bus.tot_pkt_size::total 278481245 # Cumulative packet size per connected master and slave (bytes) 874system.cpu.toL2Bus.data_through_bus 278457117 # Total data (bytes) 875system.cpu.toL2Bus.snoop_data_through_bus 3731904 # Total snoop data (bytes) 876system.cpu.toL2Bus.reqLayer0.occupancy 4072507880 # Layer occupancy (ticks) | 866system.cpu.toL2Bus.trans_dist::Writeback 1587489 # Transaction distribution 867system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46722 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::UpgradeReq 2231 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::UpgradeResp 2231 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::ReadExReq 287826 # Transaction distribution 871system.cpu.toL2Bus.trans_dist::ReadExResp 287826 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution 873system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2007150 # Packet count per connected master and slave (bytes) 874system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6137120 # Packet count per connected master and slave (bytes) 875system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34489 # Packet count per connected master and slave (bytes) 876system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168921 # Packet count per connected master and slave (bytes) 877system.cpu.toL2Bus.pkt_count::total 8347680 # Packet count per connected master and slave (bytes) 878system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64225408 # Cumulative packet size per connected master and slave (bytes) 879system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208172445 # Cumulative packet size per connected master and slave (bytes) 880system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1082112 # Cumulative packet size per connected master and slave (bytes) 881system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5828032 # Cumulative packet size per connected master and slave (bytes) 882system.cpu.toL2Bus.pkt_size::total 279307997 # Cumulative packet size per connected master and slave (bytes) 883system.cpu.toL2Bus.snoops 61506 # Total snoops (count) 884system.cpu.toL2Bus.snoop_fanout::samples 4398693 # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::mean 3.010831 # Request fanout histogram 886system.cpu.toL2Bus.snoop_fanout::stdev 0.103506 # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 889system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 890system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::3 4351052 98.92% 98.92% # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::4 47641 1.08% 100.00% # Request fanout histogram 893system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 894system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 895system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 896system.cpu.toL2Bus.snoop_fanout::total 4398693 # Request fanout histogram 897system.cpu.toL2Bus.reqLayer0.occupancy 4081523356 # Layer occupancy (ticks) |
| 877system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 898system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 878system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) | 899system.cpu.toL2Bus.snoopLayer0.occupancy 582000 # Layer occupancy (ticks) |
| 879system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 900system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 880system.cpu.toL2Bus.respLayer0.occupancy 1501244795 # Layer occupancy (ticks) | 901system.cpu.toL2Bus.respLayer0.occupancy 1509600495 # Layer occupancy (ticks) |
| 881system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 902system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 882system.cpu.toL2Bus.respLayer1.occupancy 3142652109 # Layer occupancy (ticks) | 903system.cpu.toL2Bus.respLayer1.occupancy 3145861612 # Layer occupancy (ticks) |
| 883system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 904system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 884system.cpu.toL2Bus.respLayer2.occupancy 23061226 # Layer occupancy (ticks) | 905system.cpu.toL2Bus.respLayer2.occupancy 26384476 # Layer occupancy (ticks) |
| 885system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 906system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 886system.cpu.toL2Bus.respLayer3.occupancy 112150627 # Layer occupancy (ticks) | 907system.cpu.toL2Bus.respLayer3.occupancy 116845140 # Layer occupancy (ticks) |
| 887system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 908system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 888system.cpu.icache.tags.replacements 997506 # number of replacements 889system.cpu.icache.tags.tagsinuse 509.982226 # Cycle average of tags in use 890system.cpu.icache.tags.total_refs 8120756 # Total number of references to valid blocks. 891system.cpu.icache.tags.sampled_refs 998018 # Sample count of references to valid blocks. 892system.cpu.icache.tags.avg_refs 8.136883 # Average number of references to valid blocks. 893system.cpu.icache.tags.warmup_cycle 147598371250 # Cycle when the warmup percentage was hit. 894system.cpu.icache.tags.occ_blocks::cpu.inst 509.982226 # Average occupied blocks per requestor 895system.cpu.icache.tags.occ_percent::cpu.inst 0.996059 # Average percentage of cache occupancy 896system.cpu.icache.tags.occ_percent::total 0.996059 # Average percentage of cache occupancy | 909system.cpu.icache.tags.replacements 1003070 # number of replacements 910system.cpu.icache.tags.tagsinuse 510.154171 # Cycle average of tags in use 911system.cpu.icache.tags.total_refs 8117984 # Total number of references to valid blocks. 912system.cpu.icache.tags.sampled_refs 1003582 # Sample count of references to valid blocks. 913system.cpu.icache.tags.avg_refs 8.089009 # Average number of references to valid blocks. 914system.cpu.icache.tags.warmup_cycle 147599073250 # Cycle when the warmup percentage was hit. 915system.cpu.icache.tags.occ_blocks::cpu.inst 510.154171 # Average occupied blocks per requestor 916system.cpu.icache.tags.occ_percent::cpu.inst 0.996395 # Average percentage of cache occupancy 917system.cpu.icache.tags.occ_percent::total 0.996395 # Average percentage of cache occupancy |
| 897system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 918system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 898system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 899system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 900system.cpu.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id | 919system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 920system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id 921system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id |
| 901system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 922system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 902system.cpu.icache.tags.tag_accesses 10180257 # Number of tag accesses 903system.cpu.icache.tags.data_accesses 10180257 # Number of data accesses 904system.cpu.icache.ReadReq_hits::cpu.inst 8120756 # number of ReadReq hits 905system.cpu.icache.ReadReq_hits::total 8120756 # number of ReadReq hits 906system.cpu.icache.demand_hits::cpu.inst 8120756 # number of demand (read+write) hits 907system.cpu.icache.demand_hits::total 8120756 # number of demand (read+write) hits 908system.cpu.icache.overall_hits::cpu.inst 8120756 # number of overall hits 909system.cpu.icache.overall_hits::total 8120756 # number of overall hits 910system.cpu.icache.ReadReq_misses::cpu.inst 1061436 # number of ReadReq misses 911system.cpu.icache.ReadReq_misses::total 1061436 # number of ReadReq misses 912system.cpu.icache.demand_misses::cpu.inst 1061436 # number of demand (read+write) misses 913system.cpu.icache.demand_misses::total 1061436 # number of demand (read+write) misses 914system.cpu.icache.overall_misses::cpu.inst 1061436 # number of overall misses 915system.cpu.icache.overall_misses::total 1061436 # number of overall misses 916system.cpu.icache.ReadReq_miss_latency::cpu.inst 14736249127 # number of ReadReq miss cycles 917system.cpu.icache.ReadReq_miss_latency::total 14736249127 # number of ReadReq miss cycles 918system.cpu.icache.demand_miss_latency::cpu.inst 14736249127 # number of demand (read+write) miss cycles 919system.cpu.icache.demand_miss_latency::total 14736249127 # number of demand (read+write) miss cycles 920system.cpu.icache.overall_miss_latency::cpu.inst 14736249127 # number of overall miss cycles 921system.cpu.icache.overall_miss_latency::total 14736249127 # number of overall miss cycles 922system.cpu.icache.ReadReq_accesses::cpu.inst 9182192 # number of ReadReq accesses(hits+misses) 923system.cpu.icache.ReadReq_accesses::total 9182192 # number of ReadReq accesses(hits+misses) 924system.cpu.icache.demand_accesses::cpu.inst 9182192 # number of demand (read+write) accesses 925system.cpu.icache.demand_accesses::total 9182192 # number of demand (read+write) accesses 926system.cpu.icache.overall_accesses::cpu.inst 9182192 # number of overall (read+write) accesses 927system.cpu.icache.overall_accesses::total 9182192 # number of overall (read+write) accesses 928system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115597 # miss rate for ReadReq accesses 929system.cpu.icache.ReadReq_miss_rate::total 0.115597 # miss rate for ReadReq accesses 930system.cpu.icache.demand_miss_rate::cpu.inst 0.115597 # miss rate for demand accesses 931system.cpu.icache.demand_miss_rate::total 0.115597 # miss rate for demand accesses 932system.cpu.icache.overall_miss_rate::cpu.inst 0.115597 # miss rate for overall accesses 933system.cpu.icache.overall_miss_rate::total 0.115597 # miss rate for overall accesses 934system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13883.313857 # average ReadReq miss latency 935system.cpu.icache.ReadReq_avg_miss_latency::total 13883.313857 # average ReadReq miss latency 936system.cpu.icache.demand_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency 937system.cpu.icache.demand_avg_miss_latency::total 13883.313857 # average overall miss latency 938system.cpu.icache.overall_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency 939system.cpu.icache.overall_avg_miss_latency::total 13883.313857 # average overall miss latency 940system.cpu.icache.blocked_cycles::no_mshrs 6673 # number of cycles access was blocked | 923system.cpu.icache.tags.tag_accesses 10188308 # Number of tag accesses 924system.cpu.icache.tags.data_accesses 10188308 # Number of data accesses 925system.cpu.icache.ReadReq_hits::cpu.inst 8117984 # number of ReadReq hits 926system.cpu.icache.ReadReq_hits::total 8117984 # number of ReadReq hits 927system.cpu.icache.demand_hits::cpu.inst 8117984 # number of demand (read+write) hits 928system.cpu.icache.demand_hits::total 8117984 # number of demand (read+write) hits 929system.cpu.icache.overall_hits::cpu.inst 8117984 # number of overall hits 930system.cpu.icache.overall_hits::total 8117984 # number of overall hits 931system.cpu.icache.ReadReq_misses::cpu.inst 1066696 # number of ReadReq misses 932system.cpu.icache.ReadReq_misses::total 1066696 # number of ReadReq misses 933system.cpu.icache.demand_misses::cpu.inst 1066696 # number of demand (read+write) misses 934system.cpu.icache.demand_misses::total 1066696 # number of demand (read+write) misses 935system.cpu.icache.overall_misses::cpu.inst 1066696 # number of overall misses 936system.cpu.icache.overall_misses::total 1066696 # number of overall misses 937system.cpu.icache.ReadReq_miss_latency::cpu.inst 14789893561 # number of ReadReq miss cycles 938system.cpu.icache.ReadReq_miss_latency::total 14789893561 # number of ReadReq miss cycles 939system.cpu.icache.demand_miss_latency::cpu.inst 14789893561 # number of demand (read+write) miss cycles 940system.cpu.icache.demand_miss_latency::total 14789893561 # number of demand (read+write) miss cycles 941system.cpu.icache.overall_miss_latency::cpu.inst 14789893561 # number of overall miss cycles 942system.cpu.icache.overall_miss_latency::total 14789893561 # number of overall miss cycles 943system.cpu.icache.ReadReq_accesses::cpu.inst 9184680 # number of ReadReq accesses(hits+misses) 944system.cpu.icache.ReadReq_accesses::total 9184680 # number of ReadReq accesses(hits+misses) 945system.cpu.icache.demand_accesses::cpu.inst 9184680 # number of demand (read+write) accesses 946system.cpu.icache.demand_accesses::total 9184680 # number of demand (read+write) accesses 947system.cpu.icache.overall_accesses::cpu.inst 9184680 # number of overall (read+write) accesses 948system.cpu.icache.overall_accesses::total 9184680 # number of overall (read+write) accesses 949system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116139 # miss rate for ReadReq accesses 950system.cpu.icache.ReadReq_miss_rate::total 0.116139 # miss rate for ReadReq accesses 951system.cpu.icache.demand_miss_rate::cpu.inst 0.116139 # miss rate for demand accesses 952system.cpu.icache.demand_miss_rate::total 0.116139 # miss rate for demand accesses 953system.cpu.icache.overall_miss_rate::cpu.inst 0.116139 # miss rate for overall accesses 954system.cpu.icache.overall_miss_rate::total 0.116139 # miss rate for overall accesses 955system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.143922 # average ReadReq miss latency 956system.cpu.icache.ReadReq_avg_miss_latency::total 13865.143922 # average ReadReq miss latency 957system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency 958system.cpu.icache.demand_avg_miss_latency::total 13865.143922 # average overall miss latency 959system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency 960system.cpu.icache.overall_avg_miss_latency::total 13865.143922 # average overall miss latency 961system.cpu.icache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked |
| 941system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 962system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 942system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked | 963system.cpu.icache.blocked::no_mshrs 266 # number of cycles access was blocked |
| 943system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 964system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 944system.cpu.icache.avg_blocked_cycles::no_mshrs 22.852740 # average number of cycles each access was blocked | 965system.cpu.icache.avg_blocked_cycles::no_mshrs 22.943609 # average number of cycles each access was blocked |
| 945system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 946system.cpu.icache.fast_writes 0 # number of fast writes performed 947system.cpu.icache.cache_copies 0 # number of cache copies performed | 966system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 967system.cpu.icache.fast_writes 0 # number of fast writes performed 968system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 948system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63371 # number of ReadReq MSHR hits 949system.cpu.icache.ReadReq_mshr_hits::total 63371 # number of ReadReq MSHR hits 950system.cpu.icache.demand_mshr_hits::cpu.inst 63371 # number of demand (read+write) MSHR hits 951system.cpu.icache.demand_mshr_hits::total 63371 # number of demand (read+write) MSHR hits 952system.cpu.icache.overall_mshr_hits::cpu.inst 63371 # number of overall MSHR hits 953system.cpu.icache.overall_mshr_hits::total 63371 # number of overall MSHR hits 954system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998065 # number of ReadReq MSHR misses 955system.cpu.icache.ReadReq_mshr_misses::total 998065 # number of ReadReq MSHR misses 956system.cpu.icache.demand_mshr_misses::cpu.inst 998065 # number of demand (read+write) MSHR misses 957system.cpu.icache.demand_mshr_misses::total 998065 # number of demand (read+write) MSHR misses 958system.cpu.icache.overall_mshr_misses::cpu.inst 998065 # number of overall MSHR misses 959system.cpu.icache.overall_mshr_misses::total 998065 # number of overall MSHR misses 960system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095503951 # number of ReadReq MSHR miss cycles 961system.cpu.icache.ReadReq_mshr_miss_latency::total 12095503951 # number of ReadReq MSHR miss cycles 962system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095503951 # number of demand (read+write) MSHR miss cycles 963system.cpu.icache.demand_mshr_miss_latency::total 12095503951 # number of demand (read+write) MSHR miss cycles 964system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095503951 # number of overall MSHR miss cycles 965system.cpu.icache.overall_mshr_miss_latency::total 12095503951 # number of overall MSHR miss cycles 966system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for ReadReq accesses 967system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108696 # mshr miss rate for ReadReq accesses 968system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for demand accesses 969system.cpu.icache.demand_mshr_miss_rate::total 0.108696 # mshr miss rate for demand accesses 970system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for overall accesses 971system.cpu.icache.overall_mshr_miss_rate::total 0.108696 # mshr miss rate for overall accesses 972system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12118.954127 # average ReadReq mshr miss latency 973system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12118.954127 # average ReadReq mshr miss latency 974system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency 975system.cpu.icache.demand_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency 976system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency 977system.cpu.icache.overall_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency | 969system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63068 # number of ReadReq MSHR hits 970system.cpu.icache.ReadReq_mshr_hits::total 63068 # number of ReadReq MSHR hits 971system.cpu.icache.demand_mshr_hits::cpu.inst 63068 # number of demand (read+write) MSHR hits 972system.cpu.icache.demand_mshr_hits::total 63068 # number of demand (read+write) MSHR hits 973system.cpu.icache.overall_mshr_hits::cpu.inst 63068 # number of overall MSHR hits 974system.cpu.icache.overall_mshr_hits::total 63068 # number of overall MSHR hits 975system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1003628 # number of ReadReq MSHR misses 976system.cpu.icache.ReadReq_mshr_misses::total 1003628 # number of ReadReq MSHR misses 977system.cpu.icache.demand_mshr_misses::cpu.inst 1003628 # number of demand (read+write) MSHR misses 978system.cpu.icache.demand_mshr_misses::total 1003628 # number of demand (read+write) MSHR misses 979system.cpu.icache.overall_mshr_misses::cpu.inst 1003628 # number of overall MSHR misses 980system.cpu.icache.overall_mshr_misses::total 1003628 # number of overall MSHR misses 981system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143729999 # number of ReadReq MSHR miss cycles 982system.cpu.icache.ReadReq_mshr_miss_latency::total 12143729999 # number of ReadReq MSHR miss cycles 983system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143729999 # number of demand (read+write) MSHR miss cycles 984system.cpu.icache.demand_mshr_miss_latency::total 12143729999 # number of demand (read+write) MSHR miss cycles 985system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143729999 # number of overall MSHR miss cycles 986system.cpu.icache.overall_mshr_miss_latency::total 12143729999 # number of overall MSHR miss cycles 987system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for ReadReq accesses 988system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109272 # mshr miss rate for ReadReq accesses 989system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for demand accesses 990system.cpu.icache.demand_mshr_miss_rate::total 0.109272 # mshr miss rate for demand accesses 991system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for overall accesses 992system.cpu.icache.overall_mshr_miss_rate::total 0.109272 # mshr miss rate for overall accesses 993system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12099.831809 # average ReadReq mshr miss latency 994system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12099.831809 # average ReadReq mshr miss latency 995system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency 996system.cpu.icache.demand_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency 997system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency 998system.cpu.icache.overall_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency |
| 978system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 999system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 979system.cpu.itb_walker_cache.tags.replacements 14491 # number of replacements 980system.cpu.itb_walker_cache.tags.tagsinuse 6.005977 # Cycle average of tags in use 981system.cpu.itb_walker_cache.tags.total_refs 26506 # Total number of references to valid blocks. 982system.cpu.itb_walker_cache.tags.sampled_refs 14506 # Sample count of references to valid blocks. 983system.cpu.itb_walker_cache.tags.avg_refs 1.827244 # Average number of references to valid blocks. 984system.cpu.itb_walker_cache.tags.warmup_cycle 5104029760000 # Cycle when the warmup percentage was hit. 985system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.005977 # Average occupied blocks per requestor 986system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375374 # Average percentage of cache occupancy 987system.cpu.itb_walker_cache.tags.occ_percent::total 0.375374 # Average percentage of cache occupancy 988system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 989system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 990system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 991system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 992system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 993system.cpu.itb_walker_cache.tags.tag_accesses 99110 # Number of tag accesses 994system.cpu.itb_walker_cache.tags.data_accesses 99110 # Number of data accesses 995system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26504 # number of ReadReq hits 996system.cpu.itb_walker_cache.ReadReq_hits::total 26504 # number of ReadReq hits | 1000system.cpu.itb_walker_cache.tags.replacements 16690 # number of replacements 1001system.cpu.itb_walker_cache.tags.tagsinuse 6.006176 # Cycle average of tags in use 1002system.cpu.itb_walker_cache.tags.total_refs 23588 # Total number of references to valid blocks. 1003system.cpu.itb_walker_cache.tags.sampled_refs 16704 # Sample count of references to valid blocks. 1004system.cpu.itb_walker_cache.tags.avg_refs 1.412117 # Average number of references to valid blocks. 1005system.cpu.itb_walker_cache.tags.warmup_cycle 5099387464000 # Cycle when the warmup percentage was hit. 1006system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006176 # Average occupied blocks per requestor 1007system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375386 # Average percentage of cache occupancy 1008system.cpu.itb_walker_cache.tags.occ_percent::total 0.375386 # Average percentage of cache occupancy 1009system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 1010system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 1011system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 1012system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 1013system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 1014system.cpu.itb_walker_cache.tags.tag_accesses 99931 # Number of tag accesses 1015system.cpu.itb_walker_cache.tags.data_accesses 99931 # Number of data accesses 1016system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 23592 # number of ReadReq hits 1017system.cpu.itb_walker_cache.ReadReq_hits::total 23592 # number of ReadReq hits |
| 997system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 998system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 1018system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1019system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 999system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26506 # number of demand (read+write) hits 1000system.cpu.itb_walker_cache.demand_hits::total 26506 # number of demand (read+write) hits 1001system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26506 # number of overall hits 1002system.cpu.itb_walker_cache.overall_hits::total 26506 # number of overall hits 1003system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15366 # number of ReadReq misses 1004system.cpu.itb_walker_cache.ReadReq_misses::total 15366 # number of ReadReq misses 1005system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15366 # number of demand (read+write) misses 1006system.cpu.itb_walker_cache.demand_misses::total 15366 # number of demand (read+write) misses 1007system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15366 # number of overall misses 1008system.cpu.itb_walker_cache.overall_misses::total 15366 # number of overall misses 1009system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 173869741 # number of ReadReq miss cycles 1010system.cpu.itb_walker_cache.ReadReq_miss_latency::total 173869741 # number of ReadReq miss cycles 1011system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 173869741 # number of demand (read+write) miss cycles 1012system.cpu.itb_walker_cache.demand_miss_latency::total 173869741 # number of demand (read+write) miss cycles 1013system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 173869741 # number of overall miss cycles 1014system.cpu.itb_walker_cache.overall_miss_latency::total 173869741 # number of overall miss cycles 1015system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41870 # number of ReadReq accesses(hits+misses) 1016system.cpu.itb_walker_cache.ReadReq_accesses::total 41870 # number of ReadReq accesses(hits+misses) | 1020system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 23594 # number of demand (read+write) hits 1021system.cpu.itb_walker_cache.demand_hits::total 23594 # number of demand (read+write) hits 1022system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 23594 # number of overall hits 1023system.cpu.itb_walker_cache.overall_hits::total 23594 # number of overall hits 1024system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 17581 # number of ReadReq misses 1025system.cpu.itb_walker_cache.ReadReq_misses::total 17581 # number of ReadReq misses 1026system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 17581 # number of demand (read+write) misses 1027system.cpu.itb_walker_cache.demand_misses::total 17581 # number of demand (read+write) misses 1028system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 17581 # number of overall misses 1029system.cpu.itb_walker_cache.overall_misses::total 17581 # number of overall misses 1030system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 194939990 # number of ReadReq miss cycles 1031system.cpu.itb_walker_cache.ReadReq_miss_latency::total 194939990 # number of ReadReq miss cycles 1032system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 194939990 # number of demand (read+write) miss cycles 1033system.cpu.itb_walker_cache.demand_miss_latency::total 194939990 # number of demand (read+write) miss cycles 1034system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 194939990 # number of overall miss cycles 1035system.cpu.itb_walker_cache.overall_miss_latency::total 194939990 # number of overall miss cycles 1036system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41173 # number of ReadReq accesses(hits+misses) 1037system.cpu.itb_walker_cache.ReadReq_accesses::total 41173 # number of ReadReq accesses(hits+misses) |
| 1017system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1018system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 1038system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1039system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 1019system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41872 # number of demand (read+write) accesses 1020system.cpu.itb_walker_cache.demand_accesses::total 41872 # number of demand (read+write) accesses 1021system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41872 # number of overall (read+write) accesses 1022system.cpu.itb_walker_cache.overall_accesses::total 41872 # number of overall (read+write) accesses 1023system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.366993 # miss rate for ReadReq accesses 1024system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.366993 # miss rate for ReadReq accesses 1025system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.366976 # miss rate for demand accesses 1026system.cpu.itb_walker_cache.demand_miss_rate::total 0.366976 # miss rate for demand accesses 1027system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.366976 # miss rate for overall accesses 1028system.cpu.itb_walker_cache.overall_miss_rate::total 0.366976 # miss rate for overall accesses 1029system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11315.224587 # average ReadReq miss latency 1030system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11315.224587 # average ReadReq miss latency 1031system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency 1032system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11315.224587 # average overall miss latency 1033system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency 1034system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11315.224587 # average overall miss latency | 1040system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41175 # number of demand (read+write) accesses 1041system.cpu.itb_walker_cache.demand_accesses::total 41175 # number of demand (read+write) accesses 1042system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41175 # number of overall (read+write) accesses 1043system.cpu.itb_walker_cache.overall_accesses::total 41175 # number of overall (read+write) accesses 1044system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.427003 # miss rate for ReadReq accesses 1045system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.427003 # miss rate for ReadReq accesses 1046system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.426982 # miss rate for demand accesses 1047system.cpu.itb_walker_cache.demand_miss_rate::total 0.426982 # miss rate for demand accesses 1048system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.426982 # miss rate for overall accesses 1049system.cpu.itb_walker_cache.overall_miss_rate::total 0.426982 # miss rate for overall accesses 1050system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11088.105910 # average ReadReq miss latency 1051system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11088.105910 # average ReadReq miss latency 1052system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency 1053system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11088.105910 # average overall miss latency 1054system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency 1055system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11088.105910 # average overall miss latency |
| 1035system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1036system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1037system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1039system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1040system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1041system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1042system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 1056system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1058system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1059system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1060system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1061system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1062system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1063system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1043system.cpu.itb_walker_cache.writebacks::writebacks 2963 # number of writebacks 1044system.cpu.itb_walker_cache.writebacks::total 2963 # number of writebacks 1045system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15366 # number of ReadReq MSHR misses 1046system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15366 # number of ReadReq MSHR misses 1047system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15366 # number of demand (read+write) MSHR misses 1048system.cpu.itb_walker_cache.demand_mshr_misses::total 15366 # number of demand (read+write) MSHR misses 1049system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15366 # number of overall MSHR misses 1050system.cpu.itb_walker_cache.overall_mshr_misses::total 15366 # number of overall MSHR misses 1051system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143113289 # number of ReadReq MSHR miss cycles 1052system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143113289 # number of ReadReq MSHR miss cycles 1053system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143113289 # number of demand (read+write) MSHR miss cycles 1054system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143113289 # number of demand (read+write) MSHR miss cycles 1055system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143113289 # number of overall MSHR miss cycles 1056system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143113289 # number of overall MSHR miss cycles 1057system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.366993 # mshr miss rate for ReadReq accesses 1058system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.366993 # mshr miss rate for ReadReq accesses 1059system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for demand accesses 1060system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.366976 # mshr miss rate for demand accesses 1061system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for overall accesses 1062system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.366976 # mshr miss rate for overall accesses 1063system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average ReadReq mshr miss latency 1064system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9313.633281 # average ReadReq mshr miss latency 1065system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency 1066system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency 1067system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency 1068system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency | 1064system.cpu.itb_walker_cache.writebacks::writebacks 3261 # number of writebacks 1065system.cpu.itb_walker_cache.writebacks::total 3261 # number of writebacks 1066system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 17581 # number of ReadReq MSHR misses 1067system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 17581 # number of ReadReq MSHR misses 1068system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 17581 # number of demand (read+write) MSHR misses 1069system.cpu.itb_walker_cache.demand_mshr_misses::total 17581 # number of demand (read+write) MSHR misses 1070system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 17581 # number of overall MSHR misses 1071system.cpu.itb_walker_cache.overall_mshr_misses::total 17581 # number of overall MSHR misses 1072system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159752038 # number of ReadReq MSHR miss cycles 1073system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159752038 # number of ReadReq MSHR miss cycles 1074system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159752038 # number of demand (read+write) MSHR miss cycles 1075system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159752038 # number of demand (read+write) MSHR miss cycles 1076system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159752038 # number of overall MSHR miss cycles 1077system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159752038 # number of overall MSHR miss cycles 1078system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.427003 # mshr miss rate for ReadReq accesses 1079system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.427003 # mshr miss rate for ReadReq accesses 1080system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for demand accesses 1081system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.426982 # mshr miss rate for demand accesses 1082system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for overall accesses 1083system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.426982 # mshr miss rate for overall accesses 1084system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average ReadReq mshr miss latency 1085system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9086.629771 # average ReadReq mshr miss latency 1086system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency 1087system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency 1088system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency 1089system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency |
| 1069system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1090system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1070system.cpu.dtb_walker_cache.tags.replacements 73624 # number of replacements 1071system.cpu.dtb_walker_cache.tags.tagsinuse 15.198399 # Cycle average of tags in use 1072system.cpu.dtb_walker_cache.tags.total_refs 115934 # Total number of references to valid blocks. 1073system.cpu.dtb_walker_cache.tags.sampled_refs 73640 # Sample count of references to valid blocks. 1074system.cpu.dtb_walker_cache.tags.avg_refs 1.574335 # Average number of references to valid blocks. 1075system.cpu.dtb_walker_cache.tags.warmup_cycle 3233327929250 # Cycle when the warmup percentage was hit. 1076system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.198399 # Average occupied blocks per requestor 1077system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.949900 # Average percentage of cache occupancy 1078system.cpu.dtb_walker_cache.tags.occ_percent::total 0.949900 # Average percentage of cache occupancy | 1091system.cpu.dtb_walker_cache.tags.replacements 76771 # number of replacements 1092system.cpu.dtb_walker_cache.tags.tagsinuse 15.789364 # Cycle average of tags in use 1093system.cpu.dtb_walker_cache.tags.total_refs 114792 # Total number of references to valid blocks. 1094system.cpu.dtb_walker_cache.tags.sampled_refs 76787 # Sample count of references to valid blocks. 1095system.cpu.dtb_walker_cache.tags.avg_refs 1.494941 # Average number of references to valid blocks. 1096system.cpu.dtb_walker_cache.tags.warmup_cycle 197445175000 # Cycle when the warmup percentage was hit. 1097system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.789364 # Average occupied blocks per requestor 1098system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986835 # Average percentage of cache occupancy 1099system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986835 # Average percentage of cache occupancy |
| 1079system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id | 1100system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id |
| 1080system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 1081system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 1082system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id | 1101system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1102system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 1103system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id |
| 1083system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1104system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1084system.cpu.dtb_walker_cache.tags.tag_accesses 456046 # Number of tag accesses 1085system.cpu.dtb_walker_cache.tags.data_accesses 456046 # Number of data accesses 1086system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 115934 # number of ReadReq hits 1087system.cpu.dtb_walker_cache.ReadReq_hits::total 115934 # number of ReadReq hits 1088system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 115934 # number of demand (read+write) hits 1089system.cpu.dtb_walker_cache.demand_hits::total 115934 # number of demand (read+write) hits 1090system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 115934 # number of overall hits 1091system.cpu.dtb_walker_cache.overall_hits::total 115934 # number of overall hits 1092system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74726 # number of ReadReq misses 1093system.cpu.dtb_walker_cache.ReadReq_misses::total 74726 # number of ReadReq misses 1094system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74726 # number of demand (read+write) misses 1095system.cpu.dtb_walker_cache.demand_misses::total 74726 # number of demand (read+write) misses 1096system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74726 # number of overall misses 1097system.cpu.dtb_walker_cache.overall_misses::total 74726 # number of overall misses 1098system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 911611211 # number of ReadReq miss cycles 1099system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 911611211 # number of ReadReq miss cycles 1100system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 911611211 # number of demand (read+write) miss cycles 1101system.cpu.dtb_walker_cache.demand_miss_latency::total 911611211 # number of demand (read+write) miss cycles 1102system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 911611211 # number of overall miss cycles 1103system.cpu.dtb_walker_cache.overall_miss_latency::total 911611211 # number of overall miss cycles 1104system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190660 # number of ReadReq accesses(hits+misses) 1105system.cpu.dtb_walker_cache.ReadReq_accesses::total 190660 # number of ReadReq accesses(hits+misses) 1106system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190660 # number of demand (read+write) accesses 1107system.cpu.dtb_walker_cache.demand_accesses::total 190660 # number of demand (read+write) accesses 1108system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190660 # number of overall (read+write) accesses 1109system.cpu.dtb_walker_cache.overall_accesses::total 190660 # number of overall (read+write) accesses 1110system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391933 # miss rate for ReadReq accesses 1111system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391933 # miss rate for ReadReq accesses 1112system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391933 # miss rate for demand accesses 1113system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391933 # miss rate for demand accesses 1114system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391933 # miss rate for overall accesses 1115system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391933 # miss rate for overall accesses 1116system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12199.384565 # average ReadReq miss latency 1117system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12199.384565 # average ReadReq miss latency 1118system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency 1119system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12199.384565 # average overall miss latency 1120system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency 1121system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12199.384565 # average overall miss latency | 1105system.cpu.dtb_walker_cache.tags.tag_accesses 463158 # Number of tag accesses 1106system.cpu.dtb_walker_cache.tags.data_accesses 463158 # Number of data accesses 1107system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114792 # number of ReadReq hits 1108system.cpu.dtb_walker_cache.ReadReq_hits::total 114792 # number of ReadReq hits 1109system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114792 # number of demand (read+write) hits 1110system.cpu.dtb_walker_cache.demand_hits::total 114792 # number of demand (read+write) hits 1111system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114792 # number of overall hits 1112system.cpu.dtb_walker_cache.overall_hits::total 114792 # number of overall hits 1113system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77858 # number of ReadReq misses 1114system.cpu.dtb_walker_cache.ReadReq_misses::total 77858 # number of ReadReq misses 1115system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77858 # number of demand (read+write) misses 1116system.cpu.dtb_walker_cache.demand_misses::total 77858 # number of demand (read+write) misses 1117system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77858 # number of overall misses 1118system.cpu.dtb_walker_cache.overall_misses::total 77858 # number of overall misses 1119system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 943768714 # number of ReadReq miss cycles 1120system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 943768714 # number of ReadReq miss cycles 1121system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 943768714 # number of demand (read+write) miss cycles 1122system.cpu.dtb_walker_cache.demand_miss_latency::total 943768714 # number of demand (read+write) miss cycles 1123system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 943768714 # number of overall miss cycles 1124system.cpu.dtb_walker_cache.overall_miss_latency::total 943768714 # number of overall miss cycles 1125system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192650 # number of ReadReq accesses(hits+misses) 1126system.cpu.dtb_walker_cache.ReadReq_accesses::total 192650 # number of ReadReq accesses(hits+misses) 1127system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192650 # number of demand (read+write) accesses 1128system.cpu.dtb_walker_cache.demand_accesses::total 192650 # number of demand (read+write) accesses 1129system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192650 # number of overall (read+write) accesses 1130system.cpu.dtb_walker_cache.overall_accesses::total 192650 # number of overall (read+write) accesses 1131system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404142 # miss rate for ReadReq accesses 1132system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404142 # miss rate for ReadReq accesses 1133system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404142 # miss rate for demand accesses 1134system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404142 # miss rate for demand accesses 1135system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404142 # miss rate for overall accesses 1136system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404142 # miss rate for overall accesses 1137system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12121.666547 # average ReadReq miss latency 1138system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12121.666547 # average ReadReq miss latency 1139system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency 1140system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12121.666547 # average overall miss latency 1141system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency 1142system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12121.666547 # average overall miss latency |
| 1122system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1123system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1124system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1125system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1126system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1127system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1128system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1129system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 1143system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1144system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1145system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1146system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1147system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1148system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1149system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1150system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1130system.cpu.dtb_walker_cache.writebacks::writebacks 22207 # number of writebacks 1131system.cpu.dtb_walker_cache.writebacks::total 22207 # number of writebacks 1132system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74726 # number of ReadReq MSHR misses 1133system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74726 # number of ReadReq MSHR misses 1134system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74726 # number of demand (read+write) MSHR misses 1135system.cpu.dtb_walker_cache.demand_mshr_misses::total 74726 # number of demand (read+write) MSHR misses 1136system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74726 # number of overall MSHR misses 1137system.cpu.dtb_walker_cache.overall_mshr_misses::total 74726 # number of overall MSHR misses 1138system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 762035957 # number of ReadReq MSHR miss cycles 1139system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 762035957 # number of ReadReq MSHR miss cycles 1140system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 762035957 # number of demand (read+write) MSHR miss cycles 1141system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 762035957 # number of demand (read+write) MSHR miss cycles 1142system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 762035957 # number of overall MSHR miss cycles 1143system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 762035957 # number of overall MSHR miss cycles 1144system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for ReadReq accesses 1145system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391933 # mshr miss rate for ReadReq accesses 1146system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for demand accesses 1147system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391933 # mshr miss rate for demand accesses 1148system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for overall accesses 1149system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391933 # mshr miss rate for overall accesses 1150system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average ReadReq mshr miss latency 1151system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10197.735152 # average ReadReq mshr miss latency 1152system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency 1153system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency 1154system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency 1155system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency | 1151system.cpu.dtb_walker_cache.writebacks::writebacks 21599 # number of writebacks 1152system.cpu.dtb_walker_cache.writebacks::total 21599 # number of writebacks 1153system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77858 # number of ReadReq MSHR misses 1154system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77858 # number of ReadReq MSHR misses 1155system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77858 # number of demand (read+write) MSHR misses 1156system.cpu.dtb_walker_cache.demand_mshr_misses::total 77858 # number of demand (read+write) MSHR misses 1157system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77858 # number of overall MSHR misses 1158system.cpu.dtb_walker_cache.overall_mshr_misses::total 77858 # number of overall MSHR misses 1159system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 787936434 # number of ReadReq MSHR miss cycles 1160system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 787936434 # number of ReadReq MSHR miss cycles 1161system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 787936434 # number of demand (read+write) MSHR miss cycles 1162system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 787936434 # number of demand (read+write) MSHR miss cycles 1163system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 787936434 # number of overall MSHR miss cycles 1164system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 787936434 # number of overall MSHR miss cycles 1165system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for ReadReq accesses 1166system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404142 # mshr miss rate for ReadReq accesses 1167system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for demand accesses 1168system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404142 # mshr miss rate for demand accesses 1169system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for overall accesses 1170system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404142 # mshr miss rate for overall accesses 1171system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average ReadReq mshr miss latency 1172system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10120.173059 # average ReadReq mshr miss latency 1173system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency 1174system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency 1175system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency 1176system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency |
| 1156system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1177system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1157system.cpu.dcache.tags.replacements 1659582 # number of replacements 1158system.cpu.dcache.tags.tagsinuse 511.996805 # Cycle average of tags in use 1159system.cpu.dcache.tags.total_refs 19130892 # Total number of references to valid blocks. 1160system.cpu.dcache.tags.sampled_refs 1660094 # Sample count of references to valid blocks. 1161system.cpu.dcache.tags.avg_refs 11.523981 # Average number of references to valid blocks. | 1178system.cpu.dcache.tags.replacements 1661725 # number of replacements 1179system.cpu.dcache.tags.tagsinuse 511.996415 # Cycle average of tags in use 1180system.cpu.dcache.tags.total_refs 19139703 # Total number of references to valid blocks. 1181system.cpu.dcache.tags.sampled_refs 1662237 # Sample count of references to valid blocks. 1182system.cpu.dcache.tags.avg_refs 11.514425 # Average number of references to valid blocks. |
| 1162system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. | 1183system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. |
| 1163system.cpu.dcache.tags.occ_blocks::cpu.data 511.996805 # Average occupied blocks per requestor 1164system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 1165system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy | 1184system.cpu.dcache.tags.occ_blocks::cpu.data 511.996415 # Average occupied blocks per requestor 1185system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy 1186system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy |
| 1166system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1187system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1167system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id 1168system.cpu.dcache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id 1169system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id | 1188system.cpu.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 1189system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 1190system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id |
| 1170system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1191system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1171system.cpu.dcache.tags.tag_accesses 88336593 # Number of tag accesses 1172system.cpu.dcache.tags.data_accesses 88336593 # Number of data accesses 1173system.cpu.dcache.ReadReq_hits::cpu.data 10981431 # number of ReadReq hits 1174system.cpu.dcache.ReadReq_hits::total 10981431 # number of ReadReq hits 1175system.cpu.dcache.WriteReq_hits::cpu.data 8081664 # number of WriteReq hits 1176system.cpu.dcache.WriteReq_hits::total 8081664 # number of WriteReq hits 1177system.cpu.dcache.SoftPFReq_hits::cpu.data 65027 # number of SoftPFReq hits 1178system.cpu.dcache.SoftPFReq_hits::total 65027 # number of SoftPFReq hits 1179system.cpu.dcache.demand_hits::cpu.data 19063095 # number of demand (read+write) hits 1180system.cpu.dcache.demand_hits::total 19063095 # number of demand (read+write) hits 1181system.cpu.dcache.overall_hits::cpu.data 19128122 # number of overall hits 1182system.cpu.dcache.overall_hits::total 19128122 # number of overall hits 1183system.cpu.dcache.ReadReq_misses::cpu.data 1801191 # number of ReadReq misses 1184system.cpu.dcache.ReadReq_misses::total 1801191 # number of ReadReq misses 1185system.cpu.dcache.WriteReq_misses::cpu.data 333463 # number of WriteReq misses 1186system.cpu.dcache.WriteReq_misses::total 333463 # number of WriteReq misses 1187system.cpu.dcache.SoftPFReq_misses::cpu.data 406345 # number of SoftPFReq misses 1188system.cpu.dcache.SoftPFReq_misses::total 406345 # number of SoftPFReq misses 1189system.cpu.dcache.demand_misses::cpu.data 2134654 # number of demand (read+write) misses 1190system.cpu.dcache.demand_misses::total 2134654 # number of demand (read+write) misses 1191system.cpu.dcache.overall_misses::cpu.data 2540999 # number of overall misses 1192system.cpu.dcache.overall_misses::total 2540999 # number of overall misses 1193system.cpu.dcache.ReadReq_miss_latency::cpu.data 26558757753 # number of ReadReq miss cycles 1194system.cpu.dcache.ReadReq_miss_latency::total 26558757753 # number of ReadReq miss cycles 1195system.cpu.dcache.WriteReq_miss_latency::cpu.data 12819840878 # number of WriteReq miss cycles 1196system.cpu.dcache.WriteReq_miss_latency::total 12819840878 # number of WriteReq miss cycles 1197system.cpu.dcache.demand_miss_latency::cpu.data 39378598631 # number of demand (read+write) miss cycles 1198system.cpu.dcache.demand_miss_latency::total 39378598631 # number of demand (read+write) miss cycles 1199system.cpu.dcache.overall_miss_latency::cpu.data 39378598631 # number of overall miss cycles 1200system.cpu.dcache.overall_miss_latency::total 39378598631 # number of overall miss cycles 1201system.cpu.dcache.ReadReq_accesses::cpu.data 12782622 # number of ReadReq accesses(hits+misses) 1202system.cpu.dcache.ReadReq_accesses::total 12782622 # number of ReadReq accesses(hits+misses) 1203system.cpu.dcache.WriteReq_accesses::cpu.data 8415127 # number of WriteReq accesses(hits+misses) 1204system.cpu.dcache.WriteReq_accesses::total 8415127 # number of WriteReq accesses(hits+misses) 1205system.cpu.dcache.SoftPFReq_accesses::cpu.data 471372 # number of SoftPFReq accesses(hits+misses) 1206system.cpu.dcache.SoftPFReq_accesses::total 471372 # number of SoftPFReq accesses(hits+misses) 1207system.cpu.dcache.demand_accesses::cpu.data 21197749 # number of demand (read+write) accesses 1208system.cpu.dcache.demand_accesses::total 21197749 # number of demand (read+write) accesses 1209system.cpu.dcache.overall_accesses::cpu.data 21669121 # number of overall (read+write) accesses 1210system.cpu.dcache.overall_accesses::total 21669121 # number of overall (read+write) accesses 1211system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140909 # miss rate for ReadReq accesses 1212system.cpu.dcache.ReadReq_miss_rate::total 0.140909 # miss rate for ReadReq accesses 1213system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039627 # miss rate for WriteReq accesses 1214system.cpu.dcache.WriteReq_miss_rate::total 0.039627 # miss rate for WriteReq accesses 1215system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862047 # miss rate for SoftPFReq accesses 1216system.cpu.dcache.SoftPFReq_miss_rate::total 0.862047 # miss rate for SoftPFReq accesses 1217system.cpu.dcache.demand_miss_rate::cpu.data 0.100702 # miss rate for demand accesses 1218system.cpu.dcache.demand_miss_rate::total 0.100702 # miss rate for demand accesses 1219system.cpu.dcache.overall_miss_rate::cpu.data 0.117264 # miss rate for overall accesses 1220system.cpu.dcache.overall_miss_rate::total 0.117264 # miss rate for overall accesses 1221system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.109071 # average ReadReq miss latency 1222system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.109071 # average ReadReq miss latency 1223system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38444.567697 # average WriteReq miss latency 1224system.cpu.dcache.WriteReq_avg_miss_latency::total 38444.567697 # average WriteReq miss latency 1225system.cpu.dcache.demand_avg_miss_latency::cpu.data 18447.298078 # average overall miss latency 1226system.cpu.dcache.demand_avg_miss_latency::total 18447.298078 # average overall miss latency 1227system.cpu.dcache.overall_avg_miss_latency::cpu.data 15497.290094 # average overall miss latency 1228system.cpu.dcache.overall_avg_miss_latency::total 15497.290094 # average overall miss latency 1229system.cpu.dcache.blocked_cycles::no_mshrs 378253 # number of cycles access was blocked | 1192system.cpu.dcache.tags.tag_accesses 88377305 # Number of tag accesses 1193system.cpu.dcache.tags.data_accesses 88377305 # Number of data accesses 1194system.cpu.dcache.ReadReq_hits::cpu.data 10986051 # number of ReadReq hits 1195system.cpu.dcache.ReadReq_hits::total 10986051 # number of ReadReq hits 1196system.cpu.dcache.WriteReq_hits::cpu.data 8085611 # number of WriteReq hits 1197system.cpu.dcache.WriteReq_hits::total 8085611 # number of WriteReq hits 1198system.cpu.dcache.SoftPFReq_hits::cpu.data 65242 # number of SoftPFReq hits 1199system.cpu.dcache.SoftPFReq_hits::total 65242 # number of SoftPFReq hits 1200system.cpu.dcache.demand_hits::cpu.data 19071662 # number of demand (read+write) hits 1201system.cpu.dcache.demand_hits::total 19071662 # number of demand (read+write) hits 1202system.cpu.dcache.overall_hits::cpu.data 19136904 # number of overall hits 1203system.cpu.dcache.overall_hits::total 19136904 # number of overall hits 1204system.cpu.dcache.ReadReq_misses::cpu.data 1801162 # number of ReadReq misses 1205system.cpu.dcache.ReadReq_misses::total 1801162 # number of ReadReq misses 1206system.cpu.dcache.WriteReq_misses::cpu.data 334073 # number of WriteReq misses 1207system.cpu.dcache.WriteReq_misses::total 334073 # number of WriteReq misses 1208system.cpu.dcache.SoftPFReq_misses::cpu.data 406623 # number of SoftPFReq misses 1209system.cpu.dcache.SoftPFReq_misses::total 406623 # number of SoftPFReq misses 1210system.cpu.dcache.demand_misses::cpu.data 2135235 # number of demand (read+write) misses 1211system.cpu.dcache.demand_misses::total 2135235 # number of demand (read+write) misses 1212system.cpu.dcache.overall_misses::cpu.data 2541858 # number of overall misses 1213system.cpu.dcache.overall_misses::total 2541858 # number of overall misses 1214system.cpu.dcache.ReadReq_miss_latency::cpu.data 26563616547 # number of ReadReq miss cycles 1215system.cpu.dcache.ReadReq_miss_latency::total 26563616547 # number of ReadReq miss cycles 1216system.cpu.dcache.WriteReq_miss_latency::cpu.data 12873735113 # number of WriteReq miss cycles 1217system.cpu.dcache.WriteReq_miss_latency::total 12873735113 # number of WriteReq miss cycles 1218system.cpu.dcache.demand_miss_latency::cpu.data 39437351660 # number of demand (read+write) miss cycles 1219system.cpu.dcache.demand_miss_latency::total 39437351660 # number of demand (read+write) miss cycles 1220system.cpu.dcache.overall_miss_latency::cpu.data 39437351660 # number of overall miss cycles 1221system.cpu.dcache.overall_miss_latency::total 39437351660 # number of overall miss cycles 1222system.cpu.dcache.ReadReq_accesses::cpu.data 12787213 # number of ReadReq accesses(hits+misses) 1223system.cpu.dcache.ReadReq_accesses::total 12787213 # number of ReadReq accesses(hits+misses) 1224system.cpu.dcache.WriteReq_accesses::cpu.data 8419684 # number of WriteReq accesses(hits+misses) 1225system.cpu.dcache.WriteReq_accesses::total 8419684 # number of WriteReq accesses(hits+misses) 1226system.cpu.dcache.SoftPFReq_accesses::cpu.data 471865 # number of SoftPFReq accesses(hits+misses) 1227system.cpu.dcache.SoftPFReq_accesses::total 471865 # number of SoftPFReq accesses(hits+misses) 1228system.cpu.dcache.demand_accesses::cpu.data 21206897 # number of demand (read+write) accesses 1229system.cpu.dcache.demand_accesses::total 21206897 # number of demand (read+write) accesses 1230system.cpu.dcache.overall_accesses::cpu.data 21678762 # number of overall (read+write) accesses 1231system.cpu.dcache.overall_accesses::total 21678762 # number of overall (read+write) accesses 1232system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140856 # miss rate for ReadReq accesses 1233system.cpu.dcache.ReadReq_miss_rate::total 0.140856 # miss rate for ReadReq accesses 1234system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039678 # miss rate for WriteReq accesses 1235system.cpu.dcache.WriteReq_miss_rate::total 0.039678 # miss rate for WriteReq accesses 1236system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.861736 # miss rate for SoftPFReq accesses 1237system.cpu.dcache.SoftPFReq_miss_rate::total 0.861736 # miss rate for SoftPFReq accesses 1238system.cpu.dcache.demand_miss_rate::cpu.data 0.100686 # miss rate for demand accesses 1239system.cpu.dcache.demand_miss_rate::total 0.100686 # miss rate for demand accesses 1240system.cpu.dcache.overall_miss_rate::cpu.data 0.117251 # miss rate for overall accesses 1241system.cpu.dcache.overall_miss_rate::total 0.117251 # miss rate for overall accesses 1242system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14748.044067 # average ReadReq miss latency 1243system.cpu.dcache.ReadReq_avg_miss_latency::total 14748.044067 # average ReadReq miss latency 1244system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38535.694633 # average WriteReq miss latency 1245system.cpu.dcache.WriteReq_avg_miss_latency::total 38535.694633 # average WriteReq miss latency 1246system.cpu.dcache.demand_avg_miss_latency::cpu.data 18469.794500 # average overall miss latency 1247system.cpu.dcache.demand_avg_miss_latency::total 18469.794500 # average overall miss latency 1248system.cpu.dcache.overall_avg_miss_latency::cpu.data 15515.167118 # average overall miss latency 1249system.cpu.dcache.overall_avg_miss_latency::total 15515.167118 # average overall miss latency 1250system.cpu.dcache.blocked_cycles::no_mshrs 377678 # number of cycles access was blocked |
| 1230system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1251system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1231system.cpu.dcache.blocked::no_mshrs 40145 # number of cycles access was blocked | 1252system.cpu.dcache.blocked::no_mshrs 40377 # number of cycles access was blocked |
| 1232system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1253system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1233system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.422170 # average number of cycles each access was blocked | 1254system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353791 # average number of cycles each access was blocked |
| 1234system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1235system.cpu.dcache.fast_writes 0 # number of fast writes performed 1236system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1255system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1256system.cpu.dcache.fast_writes 0 # number of fast writes performed 1257system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1237system.cpu.dcache.writebacks::writebacks 1560667 # number of writebacks 1238system.cpu.dcache.writebacks::total 1560667 # number of writebacks 1239system.cpu.dcache.ReadReq_mshr_hits::cpu.data 830878 # number of ReadReq MSHR hits 1240system.cpu.dcache.ReadReq_mshr_hits::total 830878 # number of ReadReq MSHR hits 1241system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44317 # number of WriteReq MSHR hits 1242system.cpu.dcache.WriteReq_mshr_hits::total 44317 # number of WriteReq MSHR hits 1243system.cpu.dcache.demand_mshr_hits::cpu.data 875195 # number of demand (read+write) MSHR hits 1244system.cpu.dcache.demand_mshr_hits::total 875195 # number of demand (read+write) MSHR hits 1245system.cpu.dcache.overall_mshr_hits::cpu.data 875195 # number of overall MSHR hits 1246system.cpu.dcache.overall_mshr_hits::total 875195 # number of overall MSHR hits 1247system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970313 # number of ReadReq MSHR misses 1248system.cpu.dcache.ReadReq_mshr_misses::total 970313 # number of ReadReq MSHR misses 1249system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289146 # number of WriteReq MSHR misses 1250system.cpu.dcache.WriteReq_mshr_misses::total 289146 # number of WriteReq MSHR misses 1251system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402890 # number of SoftPFReq MSHR misses 1252system.cpu.dcache.SoftPFReq_mshr_misses::total 402890 # number of SoftPFReq MSHR misses 1253system.cpu.dcache.demand_mshr_misses::cpu.data 1259459 # number of demand (read+write) MSHR misses 1254system.cpu.dcache.demand_mshr_misses::total 1259459 # number of demand (read+write) MSHR misses 1255system.cpu.dcache.overall_mshr_misses::cpu.data 1662349 # number of overall MSHR misses 1256system.cpu.dcache.overall_mshr_misses::total 1662349 # number of overall MSHR misses 1257system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12260897766 # number of ReadReq MSHR miss cycles 1258system.cpu.dcache.ReadReq_mshr_miss_latency::total 12260897766 # number of ReadReq MSHR miss cycles 1259system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11156657127 # number of WriteReq MSHR miss cycles 1260system.cpu.dcache.WriteReq_mshr_miss_latency::total 11156657127 # number of WriteReq MSHR miss cycles 1261system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584385500 # number of SoftPFReq MSHR miss cycles 1262system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584385500 # number of SoftPFReq MSHR miss cycles 1263system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23417554893 # number of demand (read+write) MSHR miss cycles 1264system.cpu.dcache.demand_mshr_miss_latency::total 23417554893 # number of demand (read+write) MSHR miss cycles 1265system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29001940393 # number of overall MSHR miss cycles 1266system.cpu.dcache.overall_mshr_miss_latency::total 29001940393 # number of overall MSHR miss cycles 1267system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364665000 # number of ReadReq MSHR uncacheable cycles 1268system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364665000 # number of ReadReq MSHR uncacheable cycles 1269system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539423000 # number of WriteReq MSHR uncacheable cycles 1270system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539423000 # number of WriteReq MSHR uncacheable cycles 1271system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99904088000 # number of overall MSHR uncacheable cycles 1272system.cpu.dcache.overall_mshr_uncacheable_latency::total 99904088000 # number of overall MSHR uncacheable cycles 1273system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075909 # mshr miss rate for ReadReq accesses 1274system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075909 # mshr miss rate for ReadReq accesses 1275system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034360 # mshr miss rate for WriteReq accesses 1276system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034360 # mshr miss rate for WriteReq accesses 1277system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854718 # mshr miss rate for SoftPFReq accesses 1278system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854718 # mshr miss rate for SoftPFReq accesses 1279system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059415 # mshr miss rate for demand accesses 1280system.cpu.dcache.demand_mshr_miss_rate::total 0.059415 # mshr miss rate for demand accesses 1281system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076715 # mshr miss rate for overall accesses 1282system.cpu.dcache.overall_mshr_miss_rate::total 0.076715 # mshr miss rate for overall accesses 1283system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.023392 # average ReadReq mshr miss latency 1284system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.023392 # average ReadReq mshr miss latency 1285system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38584.857224 # average WriteReq mshr miss latency 1286system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38584.857224 # average WriteReq mshr miss latency 1287system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13860.819330 # average SoftPFReq mshr miss latency 1288system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13860.819330 # average SoftPFReq mshr miss latency 1289system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18593.344359 # average overall mshr miss latency 1290system.cpu.dcache.demand_avg_mshr_miss_latency::total 18593.344359 # average overall mshr miss latency 1291system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17446.360778 # average overall mshr miss latency 1292system.cpu.dcache.overall_avg_mshr_miss_latency::total 17446.360778 # average overall mshr miss latency | 1258system.cpu.dcache.writebacks::writebacks 1562629 # number of writebacks 1259system.cpu.dcache.writebacks::total 1562629 # number of writebacks 1260system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829779 # number of ReadReq MSHR hits 1261system.cpu.dcache.ReadReq_mshr_hits::total 829779 # number of ReadReq MSHR hits 1262system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44137 # number of WriteReq MSHR hits 1263system.cpu.dcache.WriteReq_mshr_hits::total 44137 # number of WriteReq MSHR hits 1264system.cpu.dcache.demand_mshr_hits::cpu.data 873916 # number of demand (read+write) MSHR hits 1265system.cpu.dcache.demand_mshr_hits::total 873916 # number of demand (read+write) MSHR hits 1266system.cpu.dcache.overall_mshr_hits::cpu.data 873916 # number of overall MSHR hits 1267system.cpu.dcache.overall_mshr_hits::total 873916 # number of overall MSHR hits 1268system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971383 # number of ReadReq MSHR misses 1269system.cpu.dcache.ReadReq_mshr_misses::total 971383 # number of ReadReq MSHR misses 1270system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289936 # number of WriteReq MSHR misses 1271system.cpu.dcache.WriteReq_mshr_misses::total 289936 # number of WriteReq MSHR misses 1272system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403164 # number of SoftPFReq MSHR misses 1273system.cpu.dcache.SoftPFReq_mshr_misses::total 403164 # number of SoftPFReq MSHR misses 1274system.cpu.dcache.demand_mshr_misses::cpu.data 1261319 # number of demand (read+write) MSHR misses 1275system.cpu.dcache.demand_mshr_misses::total 1261319 # number of demand (read+write) MSHR misses 1276system.cpu.dcache.overall_mshr_misses::cpu.data 1664483 # number of overall MSHR misses 1277system.cpu.dcache.overall_mshr_misses::total 1664483 # number of overall MSHR misses 1278system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264764518 # number of ReadReq MSHR miss cycles 1279system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264764518 # number of ReadReq MSHR miss cycles 1280system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11214941849 # number of WriteReq MSHR miss cycles 1281system.cpu.dcache.WriteReq_mshr_miss_latency::total 11214941849 # number of WriteReq MSHR miss cycles 1282system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5603688502 # number of SoftPFReq MSHR miss cycles 1283system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5603688502 # number of SoftPFReq MSHR miss cycles 1284system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23479706367 # number of demand (read+write) MSHR miss cycles 1285system.cpu.dcache.demand_mshr_miss_latency::total 23479706367 # number of demand (read+write) MSHR miss cycles 1286system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29083394869 # number of overall MSHR miss cycles 1287system.cpu.dcache.overall_mshr_miss_latency::total 29083394869 # number of overall MSHR miss cycles 1288system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364659500 # number of ReadReq MSHR uncacheable cycles 1289system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364659500 # number of ReadReq MSHR uncacheable cycles 1290system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538935000 # number of WriteReq MSHR uncacheable cycles 1291system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538935000 # number of WriteReq MSHR uncacheable cycles 1292system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903594500 # number of overall MSHR uncacheable cycles 1293system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903594500 # number of overall MSHR uncacheable cycles 1294system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075965 # mshr miss rate for ReadReq accesses 1295system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075965 # mshr miss rate for ReadReq accesses 1296system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034435 # mshr miss rate for WriteReq accesses 1297system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034435 # mshr miss rate for WriteReq accesses 1298system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854405 # mshr miss rate for SoftPFReq accesses 1299system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854405 # mshr miss rate for SoftPFReq accesses 1300system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059477 # mshr miss rate for demand accesses 1301system.cpu.dcache.demand_mshr_miss_rate::total 0.059477 # mshr miss rate for demand accesses 1302system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076779 # mshr miss rate for overall accesses 1303system.cpu.dcache.overall_mshr_miss_rate::total 0.076779 # mshr miss rate for overall accesses 1304system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12626.085198 # average ReadReq mshr miss latency 1305system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12626.085198 # average ReadReq mshr miss latency 1306system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38680.749714 # average WriteReq mshr miss latency 1307system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38680.749714 # average WriteReq mshr miss latency 1308system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13899.277966 # average SoftPFReq mshr miss latency 1309system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13899.277966 # average SoftPFReq mshr miss latency 1310system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18615.200728 # average overall mshr miss latency 1311system.cpu.dcache.demand_avg_mshr_miss_latency::total 18615.200728 # average overall mshr miss latency 1312system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.929954 # average overall mshr miss latency 1313system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.929954 # average overall mshr miss latency |
| 1293system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1294system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1295system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1296system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1297system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1298system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1299system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1314system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1315system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1316system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1317system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1318system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1319system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1320system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1300system.cpu.l2cache.tags.replacements 112856 # number of replacements 1301system.cpu.l2cache.tags.tagsinuse 64816.166677 # Cycle average of tags in use 1302system.cpu.l2cache.tags.total_refs 3836348 # Total number of references to valid blocks. 1303system.cpu.l2cache.tags.sampled_refs 176998 # Sample count of references to valid blocks. 1304system.cpu.l2cache.tags.avg_refs 21.674527 # Average number of references to valid blocks. | 1321system.cpu.l2cache.tags.replacements 112646 # number of replacements 1322system.cpu.l2cache.tags.tagsinuse 64814.554294 # Cycle average of tags in use 1323system.cpu.l2cache.tags.total_refs 3852282 # Total number of references to valid blocks. 1324system.cpu.l2cache.tags.sampled_refs 176740 # Sample count of references to valid blocks. 1325system.cpu.l2cache.tags.avg_refs 21.796322 # Average number of references to valid blocks. |
| 1305system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1326system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1306system.cpu.l2cache.tags.occ_blocks::writebacks 50391.724726 # Average occupied blocks per requestor 1307system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.855148 # Average occupied blocks per requestor 1308system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135532 # Average occupied blocks per requestor 1309system.cpu.l2cache.tags.occ_blocks::cpu.inst 3265.471036 # Average occupied blocks per requestor 1310system.cpu.l2cache.tags.occ_blocks::cpu.data 11143.980235 # Average occupied blocks per requestor 1311system.cpu.l2cache.tags.occ_percent::writebacks 0.768917 # Average percentage of cache occupancy 1312system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000227 # Average percentage of cache occupancy | 1327system.cpu.l2cache.tags.occ_blocks::writebacks 50353.205869 # Average occupied blocks per requestor 1328system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.791697 # Average occupied blocks per requestor 1329system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140401 # Average occupied blocks per requestor 1330system.cpu.l2cache.tags.occ_blocks::cpu.inst 3275.059967 # Average occupied blocks per requestor 1331system.cpu.l2cache.tags.occ_blocks::cpu.data 11170.356359 # Average occupied blocks per requestor 1332system.cpu.l2cache.tags.occ_percent::writebacks 0.768329 # Average percentage of cache occupancy 1333system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000241 # Average percentage of cache occupancy |
| 1313system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 1334system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 1314system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049827 # Average percentage of cache occupancy 1315system.cpu.l2cache.tags.occ_percent::cpu.data 0.170044 # Average percentage of cache occupancy 1316system.cpu.l2cache.tags.occ_percent::total 0.989016 # Average percentage of cache occupancy 1317system.cpu.l2cache.tags.occ_task_id_blocks::1024 64142 # Occupied blocks per task id 1318system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1319system.cpu.l2cache.tags.age_task_id_blocks_1024::1 609 # Occupied blocks per task id 1320system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3329 # Occupied blocks per task id 1321system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5865 # Occupied blocks per task id 1322system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54284 # Occupied blocks per task id 1323system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978729 # Percentage of cache occupancy per task id 1324system.cpu.l2cache.tags.tag_accesses 35070365 # Number of tag accesses 1325system.cpu.l2cache.tags.data_accesses 35070365 # Number of data accesses 1326system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67257 # number of ReadReq hits 1327system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12319 # number of ReadReq hits 1328system.cpu.l2cache.ReadReq_hits::cpu.inst 981564 # number of ReadReq hits 1329system.cpu.l2cache.ReadReq_hits::cpu.data 1336552 # number of ReadReq hits 1330system.cpu.l2cache.ReadReq_hits::total 2397692 # number of ReadReq hits 1331system.cpu.l2cache.Writeback_hits::writebacks 1585837 # number of Writeback hits 1332system.cpu.l2cache.Writeback_hits::total 1585837 # number of Writeback hits 1333system.cpu.l2cache.UpgradeReq_hits::cpu.data 306 # number of UpgradeReq hits 1334system.cpu.l2cache.UpgradeReq_hits::total 306 # number of UpgradeReq hits 1335system.cpu.l2cache.ReadExReq_hits::cpu.data 153585 # number of ReadExReq hits 1336system.cpu.l2cache.ReadExReq_hits::total 153585 # number of ReadExReq hits 1337system.cpu.l2cache.demand_hits::cpu.dtb.walker 67257 # number of demand (read+write) hits 1338system.cpu.l2cache.demand_hits::cpu.itb.walker 12319 # number of demand (read+write) hits 1339system.cpu.l2cache.demand_hits::cpu.inst 981564 # number of demand (read+write) hits 1340system.cpu.l2cache.demand_hits::cpu.data 1490137 # number of demand (read+write) hits 1341system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits 1342system.cpu.l2cache.overall_hits::cpu.dtb.walker 67257 # number of overall hits 1343system.cpu.l2cache.overall_hits::cpu.itb.walker 12319 # number of overall hits 1344system.cpu.l2cache.overall_hits::cpu.inst 981564 # number of overall hits 1345system.cpu.l2cache.overall_hits::cpu.data 1490137 # number of overall hits 1346system.cpu.l2cache.overall_hits::total 2551277 # number of overall hits 1347system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses 1348system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 1349system.cpu.l2cache.ReadReq_misses::cpu.inst 16397 # number of ReadReq misses 1350system.cpu.l2cache.ReadReq_misses::cpu.data 35888 # number of ReadReq misses 1351system.cpu.l2cache.ReadReq_misses::total 52356 # number of ReadReq misses 1352system.cpu.l2cache.UpgradeReq_misses::cpu.data 1429 # number of UpgradeReq misses 1353system.cpu.l2cache.UpgradeReq_misses::total 1429 # number of UpgradeReq misses 1354system.cpu.l2cache.ReadExReq_misses::cpu.data 133434 # number of ReadExReq misses 1355system.cpu.l2cache.ReadExReq_misses::total 133434 # number of ReadExReq misses 1356system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses 1357system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 1358system.cpu.l2cache.demand_misses::cpu.inst 16397 # number of demand (read+write) misses 1359system.cpu.l2cache.demand_misses::cpu.data 169322 # number of demand (read+write) misses 1360system.cpu.l2cache.demand_misses::total 185790 # number of demand (read+write) misses 1361system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses 1362system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 1363system.cpu.l2cache.overall_misses::cpu.inst 16397 # number of overall misses 1364system.cpu.l2cache.overall_misses::cpu.data 169322 # number of overall misses 1365system.cpu.l2cache.overall_misses::total 185790 # number of overall misses 1366system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5156250 # number of ReadReq miss cycles 1367system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 377750 # number of ReadReq miss cycles 1368system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1256760500 # number of ReadReq miss cycles 1369system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2837055499 # number of ReadReq miss cycles 1370system.cpu.l2cache.ReadReq_miss_latency::total 4099349999 # number of ReadReq miss cycles 1371system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16426795 # number of UpgradeReq miss cycles 1372system.cpu.l2cache.UpgradeReq_miss_latency::total 16426795 # number of UpgradeReq miss cycles 1373system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9290345968 # number of ReadExReq miss cycles 1374system.cpu.l2cache.ReadExReq_miss_latency::total 9290345968 # number of ReadExReq miss cycles 1375system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5156250 # number of demand (read+write) miss cycles 1376system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 377750 # number of demand (read+write) miss cycles 1377system.cpu.l2cache.demand_miss_latency::cpu.inst 1256760500 # number of demand (read+write) miss cycles 1378system.cpu.l2cache.demand_miss_latency::cpu.data 12127401467 # number of demand (read+write) miss cycles 1379system.cpu.l2cache.demand_miss_latency::total 13389695967 # number of demand (read+write) miss cycles 1380system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5156250 # number of overall miss cycles 1381system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 377750 # number of overall miss cycles 1382system.cpu.l2cache.overall_miss_latency::cpu.inst 1256760500 # number of overall miss cycles 1383system.cpu.l2cache.overall_miss_latency::cpu.data 12127401467 # number of overall miss cycles 1384system.cpu.l2cache.overall_miss_latency::total 13389695967 # number of overall miss cycles 1385system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67323 # number of ReadReq accesses(hits+misses) 1386system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses) 1387system.cpu.l2cache.ReadReq_accesses::cpu.inst 997961 # number of ReadReq accesses(hits+misses) 1388system.cpu.l2cache.ReadReq_accesses::cpu.data 1372440 # number of ReadReq accesses(hits+misses) 1389system.cpu.l2cache.ReadReq_accesses::total 2450048 # number of ReadReq accesses(hits+misses) 1390system.cpu.l2cache.Writeback_accesses::writebacks 1585837 # number of Writeback accesses(hits+misses) 1391system.cpu.l2cache.Writeback_accesses::total 1585837 # number of Writeback accesses(hits+misses) 1392system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1735 # number of UpgradeReq accesses(hits+misses) 1393system.cpu.l2cache.UpgradeReq_accesses::total 1735 # number of UpgradeReq accesses(hits+misses) 1394system.cpu.l2cache.ReadExReq_accesses::cpu.data 287019 # number of ReadExReq accesses(hits+misses) 1395system.cpu.l2cache.ReadExReq_accesses::total 287019 # number of ReadExReq accesses(hits+misses) 1396system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67323 # number of demand (read+write) accesses 1397system.cpu.l2cache.demand_accesses::cpu.itb.walker 12324 # number of demand (read+write) accesses 1398system.cpu.l2cache.demand_accesses::cpu.inst 997961 # number of demand (read+write) accesses 1399system.cpu.l2cache.demand_accesses::cpu.data 1659459 # number of demand (read+write) accesses 1400system.cpu.l2cache.demand_accesses::total 2737067 # number of demand (read+write) accesses 1401system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67323 # number of overall (read+write) accesses 1402system.cpu.l2cache.overall_accesses::cpu.itb.walker 12324 # number of overall (read+write) accesses 1403system.cpu.l2cache.overall_accesses::cpu.inst 997961 # number of overall (read+write) accesses 1404system.cpu.l2cache.overall_accesses::cpu.data 1659459 # number of overall (read+write) accesses 1405system.cpu.l2cache.overall_accesses::total 2737067 # number of overall (read+write) accesses 1406system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000980 # miss rate for ReadReq accesses 1407system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000406 # miss rate for ReadReq accesses 1408system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016431 # miss rate for ReadReq accesses 1409system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026149 # miss rate for ReadReq accesses 1410system.cpu.l2cache.ReadReq_miss_rate::total 0.021369 # miss rate for ReadReq accesses 1411system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823631 # miss rate for UpgradeReq accesses 1412system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823631 # miss rate for UpgradeReq accesses 1413system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464896 # miss rate for ReadExReq accesses 1414system.cpu.l2cache.ReadExReq_miss_rate::total 0.464896 # miss rate for ReadExReq accesses 1415system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000980 # miss rate for demand accesses 1416system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000406 # miss rate for demand accesses 1417system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016431 # miss rate for demand accesses 1418system.cpu.l2cache.demand_miss_rate::cpu.data 0.102034 # miss rate for demand accesses 1419system.cpu.l2cache.demand_miss_rate::total 0.067879 # miss rate for demand accesses 1420system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000980 # miss rate for overall accesses 1421system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000406 # miss rate for overall accesses 1422system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016431 # miss rate for overall accesses 1423system.cpu.l2cache.overall_miss_rate::cpu.data 0.102034 # miss rate for overall accesses 1424system.cpu.l2cache.overall_miss_rate::total 0.067879 # miss rate for overall accesses 1425system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78125 # average ReadReq miss latency 1426system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75550 # average ReadReq miss latency 1427system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76645.758370 # average ReadReq miss latency 1428system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79053.039986 # average ReadReq miss latency 1429system.cpu.l2cache.ReadReq_avg_miss_latency::total 78297.616300 # average ReadReq miss latency 1430system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11495.307908 # average UpgradeReq miss latency 1431system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11495.307908 # average UpgradeReq miss latency 1432system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69625.027864 # average ReadExReq miss latency 1433system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69625.027864 # average ReadExReq miss latency 1434system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78125 # average overall miss latency 1435system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75550 # average overall miss latency 1436system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76645.758370 # average overall miss latency 1437system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71623.306286 # average overall miss latency 1438system.cpu.l2cache.demand_avg_miss_latency::total 72068.980930 # average overall miss latency 1439system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78125 # average overall miss latency 1440system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75550 # average overall miss latency 1441system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76645.758370 # average overall miss latency 1442system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71623.306286 # average overall miss latency 1443system.cpu.l2cache.overall_avg_miss_latency::total 72068.980930 # average overall miss latency | 1335system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049973 # Average percentage of cache occupancy 1336system.cpu.l2cache.tags.occ_percent::cpu.data 0.170446 # Average percentage of cache occupancy 1337system.cpu.l2cache.tags.occ_percent::total 0.988992 # Average percentage of cache occupancy 1338system.cpu.l2cache.tags.occ_task_id_blocks::1024 64094 # Occupied blocks per task id 1339system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 1340system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id 1341system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3429 # Occupied blocks per task id 1342system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5695 # Occupied blocks per task id 1343system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54337 # Occupied blocks per task id 1344system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977997 # Percentage of cache occupancy per task id 1345system.cpu.l2cache.tags.tag_accesses 35174951 # Number of tag accesses 1346system.cpu.l2cache.tags.data_accesses 35174951 # Number of data accesses 1347system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69400 # number of ReadReq hits 1348system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13641 # number of ReadReq hits 1349system.cpu.l2cache.ReadReq_hits::cpu.inst 987138 # number of ReadReq hits 1350system.cpu.l2cache.ReadReq_hits::cpu.data 1338009 # number of ReadReq hits 1351system.cpu.l2cache.ReadReq_hits::total 2408188 # number of ReadReq hits 1352system.cpu.l2cache.Writeback_hits::writebacks 1587489 # number of Writeback hits 1353system.cpu.l2cache.Writeback_hits::total 1587489 # number of Writeback hits 1354system.cpu.l2cache.UpgradeReq_hits::cpu.data 311 # number of UpgradeReq hits 1355system.cpu.l2cache.UpgradeReq_hits::total 311 # number of UpgradeReq hits 1356system.cpu.l2cache.ReadExReq_hits::cpu.data 154123 # number of ReadExReq hits 1357system.cpu.l2cache.ReadExReq_hits::total 154123 # number of ReadExReq hits 1358system.cpu.l2cache.demand_hits::cpu.dtb.walker 69400 # number of demand (read+write) hits 1359system.cpu.l2cache.demand_hits::cpu.itb.walker 13641 # number of demand (read+write) hits 1360system.cpu.l2cache.demand_hits::cpu.inst 987138 # number of demand (read+write) hits 1361system.cpu.l2cache.demand_hits::cpu.data 1492132 # number of demand (read+write) hits 1362system.cpu.l2cache.demand_hits::total 2562311 # number of demand (read+write) hits 1363system.cpu.l2cache.overall_hits::cpu.dtb.walker 69400 # number of overall hits 1364system.cpu.l2cache.overall_hits::cpu.itb.walker 13641 # number of overall hits 1365system.cpu.l2cache.overall_hits::cpu.inst 987138 # number of overall hits 1366system.cpu.l2cache.overall_hits::cpu.data 1492132 # number of overall hits 1367system.cpu.l2cache.overall_hits::total 2562311 # number of overall hits 1368system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 64 # number of ReadReq misses 1369system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 1370system.cpu.l2cache.ReadReq_misses::cpu.inst 16384 # number of ReadReq misses 1371system.cpu.l2cache.ReadReq_misses::cpu.data 35861 # number of ReadReq misses 1372system.cpu.l2cache.ReadReq_misses::total 52315 # number of ReadReq misses 1373system.cpu.l2cache.UpgradeReq_misses::cpu.data 1456 # number of UpgradeReq misses 1374system.cpu.l2cache.UpgradeReq_misses::total 1456 # number of UpgradeReq misses 1375system.cpu.l2cache.ReadExReq_misses::cpu.data 133693 # number of ReadExReq misses 1376system.cpu.l2cache.ReadExReq_misses::total 133693 # number of ReadExReq misses 1377system.cpu.l2cache.demand_misses::cpu.dtb.walker 64 # number of demand (read+write) misses 1378system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 1379system.cpu.l2cache.demand_misses::cpu.inst 16384 # number of demand (read+write) misses 1380system.cpu.l2cache.demand_misses::cpu.data 169554 # number of demand (read+write) misses 1381system.cpu.l2cache.demand_misses::total 186008 # number of demand (read+write) misses 1382system.cpu.l2cache.overall_misses::cpu.dtb.walker 64 # number of overall misses 1383system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 1384system.cpu.l2cache.overall_misses::cpu.inst 16384 # number of overall misses 1385system.cpu.l2cache.overall_misses::cpu.data 169554 # number of overall misses 1386system.cpu.l2cache.overall_misses::total 186008 # number of overall misses 1387system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5398250 # number of ReadReq miss cycles 1388system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467000 # number of ReadReq miss cycles 1389system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1244423000 # number of ReadReq miss cycles 1390system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2844994996 # number of ReadReq miss cycles 1391system.cpu.l2cache.ReadReq_miss_latency::total 4095283246 # number of ReadReq miss cycles 1392system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17419754 # number of UpgradeReq miss cycles 1393system.cpu.l2cache.UpgradeReq_miss_latency::total 17419754 # number of UpgradeReq miss cycles 1394system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9341540216 # number of ReadExReq miss cycles 1395system.cpu.l2cache.ReadExReq_miss_latency::total 9341540216 # number of ReadExReq miss cycles 1396system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5398250 # number of demand (read+write) miss cycles 1397system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467000 # number of demand (read+write) miss cycles 1398system.cpu.l2cache.demand_miss_latency::cpu.inst 1244423000 # number of demand (read+write) miss cycles 1399system.cpu.l2cache.demand_miss_latency::cpu.data 12186535212 # number of demand (read+write) miss cycles 1400system.cpu.l2cache.demand_miss_latency::total 13436823462 # number of demand (read+write) miss cycles 1401system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5398250 # number of overall miss cycles 1402system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467000 # number of overall miss cycles 1403system.cpu.l2cache.overall_miss_latency::cpu.inst 1244423000 # number of overall miss cycles 1404system.cpu.l2cache.overall_miss_latency::cpu.data 12186535212 # number of overall miss cycles 1405system.cpu.l2cache.overall_miss_latency::total 13436823462 # number of overall miss cycles 1406system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69464 # number of ReadReq accesses(hits+misses) 1407system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13647 # number of ReadReq accesses(hits+misses) 1408system.cpu.l2cache.ReadReq_accesses::cpu.inst 1003522 # number of ReadReq accesses(hits+misses) 1409system.cpu.l2cache.ReadReq_accesses::cpu.data 1373870 # number of ReadReq accesses(hits+misses) 1410system.cpu.l2cache.ReadReq_accesses::total 2460503 # number of ReadReq accesses(hits+misses) 1411system.cpu.l2cache.Writeback_accesses::writebacks 1587489 # number of Writeback accesses(hits+misses) 1412system.cpu.l2cache.Writeback_accesses::total 1587489 # number of Writeback accesses(hits+misses) 1413system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1767 # number of UpgradeReq accesses(hits+misses) 1414system.cpu.l2cache.UpgradeReq_accesses::total 1767 # number of UpgradeReq accesses(hits+misses) 1415system.cpu.l2cache.ReadExReq_accesses::cpu.data 287816 # number of ReadExReq accesses(hits+misses) 1416system.cpu.l2cache.ReadExReq_accesses::total 287816 # number of ReadExReq accesses(hits+misses) 1417system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69464 # number of demand (read+write) accesses 1418system.cpu.l2cache.demand_accesses::cpu.itb.walker 13647 # number of demand (read+write) accesses 1419system.cpu.l2cache.demand_accesses::cpu.inst 1003522 # number of demand (read+write) accesses 1420system.cpu.l2cache.demand_accesses::cpu.data 1661686 # number of demand (read+write) accesses 1421system.cpu.l2cache.demand_accesses::total 2748319 # number of demand (read+write) accesses 1422system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69464 # number of overall (read+write) accesses 1423system.cpu.l2cache.overall_accesses::cpu.itb.walker 13647 # number of overall (read+write) accesses 1424system.cpu.l2cache.overall_accesses::cpu.inst 1003522 # number of overall (read+write) accesses 1425system.cpu.l2cache.overall_accesses::cpu.data 1661686 # number of overall (read+write) accesses 1426system.cpu.l2cache.overall_accesses::total 2748319 # number of overall (read+write) accesses 1427system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses 1428system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000440 # miss rate for ReadReq accesses 1429system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016326 # miss rate for ReadReq accesses 1430system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026102 # miss rate for ReadReq accesses 1431system.cpu.l2cache.ReadReq_miss_rate::total 0.021262 # miss rate for ReadReq accesses 1432system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823995 # miss rate for UpgradeReq accesses 1433system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823995 # miss rate for UpgradeReq accesses 1434system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464509 # miss rate for ReadExReq accesses 1435system.cpu.l2cache.ReadExReq_miss_rate::total 0.464509 # miss rate for ReadExReq accesses 1436system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses 1437system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000440 # miss rate for demand accesses 1438system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016326 # miss rate for demand accesses 1439system.cpu.l2cache.demand_miss_rate::cpu.data 0.102037 # miss rate for demand accesses 1440system.cpu.l2cache.demand_miss_rate::total 0.067681 # miss rate for demand accesses 1441system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses 1442system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000440 # miss rate for overall accesses 1443system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016326 # miss rate for overall accesses 1444system.cpu.l2cache.overall_miss_rate::cpu.data 0.102037 # miss rate for overall accesses 1445system.cpu.l2cache.overall_miss_rate::total 0.067681 # miss rate for overall accesses 1446system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84347.656250 # average ReadReq miss latency 1447system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77833.333333 # average ReadReq miss latency 1448system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75953.552246 # average ReadReq miss latency 1449system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79333.955997 # average ReadReq miss latency 1450system.cpu.l2cache.ReadReq_avg_miss_latency::total 78281.243353 # average ReadReq miss latency 1451system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11964.116758 # average UpgradeReq miss latency 1452system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11964.116758 # average UpgradeReq miss latency 1453system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69873.069016 # average ReadExReq miss latency 1454system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69873.069016 # average ReadExReq miss latency 1455system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84347.656250 # average overall miss latency 1456system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77833.333333 # average overall miss latency 1457system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75953.552246 # average overall miss latency 1458system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71874.064970 # average overall miss latency 1459system.cpu.l2cache.demand_avg_miss_latency::total 72237.879349 # average overall miss latency 1460system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84347.656250 # average overall miss latency 1461system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77833.333333 # average overall miss latency 1462system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75953.552246 # average overall miss latency 1463system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71874.064970 # average overall miss latency 1464system.cpu.l2cache.overall_avg_miss_latency::total 72237.879349 # average overall miss latency |
| 1444system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1445system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1446system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1447system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1448system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1449system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1450system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1451system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1465system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1466system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1467system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1468system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1469system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1470system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1471system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1472system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1452system.cpu.l2cache.writebacks::writebacks 103139 # number of writebacks 1453system.cpu.l2cache.writebacks::total 103139 # number of writebacks 1454system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1455system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits 1456system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1457system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1458system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits 1459system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 1460system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1461system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits 1462system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits 1463system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses 1464system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 1465system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16396 # number of ReadReq MSHR misses 1466system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35886 # number of ReadReq MSHR misses 1467system.cpu.l2cache.ReadReq_mshr_misses::total 52353 # number of ReadReq MSHR misses 1468system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1429 # number of UpgradeReq MSHR misses 1469system.cpu.l2cache.UpgradeReq_mshr_misses::total 1429 # number of UpgradeReq MSHR misses 1470system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133434 # number of ReadExReq MSHR misses 1471system.cpu.l2cache.ReadExReq_mshr_misses::total 133434 # number of ReadExReq MSHR misses 1472system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses 1473system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 1474system.cpu.l2cache.demand_mshr_misses::cpu.inst 16396 # number of demand (read+write) MSHR misses 1475system.cpu.l2cache.demand_mshr_misses::cpu.data 169320 # number of demand (read+write) MSHR misses 1476system.cpu.l2cache.demand_mshr_misses::total 185787 # number of demand (read+write) MSHR misses 1477system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses 1478system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 1479system.cpu.l2cache.overall_mshr_misses::cpu.inst 16396 # number of overall MSHR misses 1480system.cpu.l2cache.overall_mshr_misses::cpu.data 169320 # number of overall MSHR misses 1481system.cpu.l2cache.overall_mshr_misses::total 185787 # number of overall MSHR misses 1482system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4346250 # number of ReadReq MSHR miss cycles 1483system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 315250 # number of ReadReq MSHR miss cycles 1484system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1051024500 # number of ReadReq MSHR miss cycles 1485system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2391844499 # number of ReadReq MSHR miss cycles 1486system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3447530499 # number of ReadReq MSHR miss cycles 1487system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14329428 # number of UpgradeReq MSHR miss cycles 1488system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14329428 # number of UpgradeReq MSHR miss cycles 1489system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7615118032 # number of ReadExReq MSHR miss cycles 1490system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7615118032 # number of ReadExReq MSHR miss cycles 1491system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4346250 # number of demand (read+write) MSHR miss cycles 1492system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 315250 # number of demand (read+write) MSHR miss cycles 1493system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1051024500 # number of demand (read+write) MSHR miss cycles 1494system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006962531 # number of demand (read+write) MSHR miss cycles 1495system.cpu.l2cache.demand_mshr_miss_latency::total 11062648531 # number of demand (read+write) MSHR miss cycles 1496system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4346250 # number of overall MSHR miss cycles 1497system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles 1498system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1051024500 # number of overall MSHR miss cycles 1499system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006962531 # number of overall MSHR miss cycles 1500system.cpu.l2cache.overall_mshr_miss_latency::total 11062648531 # number of overall MSHR miss cycles 1501system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251423000 # number of ReadReq MSHR uncacheable cycles 1502system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251423000 # number of ReadReq MSHR uncacheable cycles 1503system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373128500 # number of WriteReq MSHR uncacheable cycles 1504system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373128500 # 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mshr miss rate for overall accesses 1525system.cpu.l2cache.overall_mshr_miss_rate::total 0.067878 # mshr miss rate for overall accesses 1526system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average ReadReq mshr miss latency 1527system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency 1528system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64102.494511 # average ReadReq mshr miss latency 1529system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66651.187065 # average ReadReq mshr miss latency 1530system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65851.632170 # average ReadReq mshr miss latency 1531system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.591323 # average UpgradeReq mshr miss latency 1532system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.591323 # average UpgradeReq mshr miss latency 1533system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57070.297166 # average ReadExReq mshr miss latency 1534system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57070.297166 # average ReadExReq mshr miss latency 1535system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average overall mshr miss latency 1536system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency 1537system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64102.494511 # average overall mshr miss latency 1538system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.889033 # average overall mshr miss latency 1539system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59544.793398 # average overall mshr miss latency 1540system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average overall mshr miss latency 1541system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency 1542system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64102.494511 # average overall mshr miss latency 1543system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.889033 # average overall mshr miss latency 1544system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59544.793398 # average overall mshr miss latency | 1473system.cpu.l2cache.writebacks::writebacks 103082 # number of writebacks 1474system.cpu.l2cache.writebacks::total 103082 # number of writebacks 1475system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 1476system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1477system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits 1478system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits 1479system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1480system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 1481system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits 1482system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1483system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits 1484system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 64 # number of ReadReq MSHR misses 1485system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1486system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16378 # number of ReadReq MSHR misses 1487system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35860 # number of ReadReq MSHR misses 1488system.cpu.l2cache.ReadReq_mshr_misses::total 52308 # number of ReadReq MSHR misses 1489system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1456 # number of UpgradeReq MSHR misses 1490system.cpu.l2cache.UpgradeReq_mshr_misses::total 1456 # number of UpgradeReq MSHR misses 1491system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133693 # number of ReadExReq MSHR misses 1492system.cpu.l2cache.ReadExReq_mshr_misses::total 133693 # number of ReadExReq MSHR misses 1493system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 64 # number of demand (read+write) MSHR misses 1494system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1495system.cpu.l2cache.demand_mshr_misses::cpu.inst 16378 # number of demand (read+write) MSHR misses 1496system.cpu.l2cache.demand_mshr_misses::cpu.data 169553 # number of demand (read+write) MSHR misses 1497system.cpu.l2cache.demand_mshr_misses::total 186001 # number of demand (read+write) MSHR misses 1498system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 64 # number of overall MSHR misses 1499system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1500system.cpu.l2cache.overall_mshr_misses::cpu.inst 16378 # number of overall MSHR misses 1501system.cpu.l2cache.overall_mshr_misses::cpu.data 169553 # number of overall MSHR misses 1502system.cpu.l2cache.overall_mshr_misses::total 186001 # number of overall MSHR misses 1503system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4610750 # number of ReadReq MSHR miss cycles 1504system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 391500 # 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number of demand (read+write) MSHR miss cycles 1515system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10062465280 # number of demand (read+write) MSHR miss cycles 1516system.cpu.l2cache.demand_mshr_miss_latency::total 11106232530 # number of demand (read+write) MSHR miss cycles 1517system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4610750 # number of overall MSHR miss cycles 1518system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles 1519system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1038765000 # number of overall MSHR miss cycles 1520system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10062465280 # number of overall MSHR miss cycles 1521system.cpu.l2cache.overall_mshr_miss_latency::total 11106232530 # number of overall MSHR miss cycles 1522system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251418000 # number of ReadReq MSHR uncacheable cycles 1523system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251418000 # number of ReadReq MSHR uncacheable cycles 1524system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373087500 # number of WriteReq MSHR uncacheable cycles 1525system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373087500 # number of WriteReq MSHR uncacheable cycles 1526system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624505500 # number of overall MSHR uncacheable cycles 1527system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624505500 # number of overall MSHR uncacheable cycles 1528system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for ReadReq accesses 1529system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for ReadReq accesses 1530system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for ReadReq accesses 1531system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026101 # mshr miss rate for ReadReq accesses 1532system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021259 # mshr miss rate for ReadReq accesses 1533system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823995 # mshr miss rate for UpgradeReq accesses 1534system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823995 # mshr miss rate for UpgradeReq accesses 1535system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464509 # mshr miss rate for ReadExReq accesses 1536system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464509 # mshr miss rate for ReadExReq accesses 1537system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for demand accesses 1538system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for demand accesses 1539system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for demand accesses 1540system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for demand accesses 1541system.cpu.l2cache.demand_mshr_miss_rate::total 0.067678 # mshr miss rate for demand accesses 1542system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for overall accesses 1543system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for overall accesses 1544system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for overall accesses 1545system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for overall accesses 1546system.cpu.l2cache.overall_mshr_miss_rate::total 0.067678 # mshr miss rate for overall accesses 1547system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average ReadReq mshr miss latency 1548system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency 1549system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795 # average ReadReq mshr miss latency 1550system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156 # average ReadReq mshr miss latency 1551system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285 # average ReadReq mshr miss latency 1552system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495 # average UpgradeReq mshr miss latency 1553system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.380495 # average UpgradeReq mshr miss latency 1554system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57315.934896 # average ReadExReq mshr miss latency 1555system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57315.934896 # average ReadExReq mshr miss latency 1556system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency 1557system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1558system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency 1559system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency 1560system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency 1561system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency 1562system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1563system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency 1564system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency 1565system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency |
| 1545system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1546system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1547system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1548system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1549system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1550system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1551system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1552system.cpu.kern.inst.arm 0 # number of arm instructions executed 1553system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1554 1555---------- End Simulation Statistics ---------- | 1566system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1567system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1568system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1569system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1570system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1571system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1572system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1573system.cpu.kern.inst.arm 0 # number of arm instructions executed 1574system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1575 1576---------- End Simulation Statistics ---------- |