| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.137972 # Number of seconds simulated 4sim_ticks 5137971999000 # Number of ticks simulated 5final_tick 5137971999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.141960 # Number of seconds simulated 4sim_ticks 5141959613000 # Number of ticks simulated 5final_tick 5141959613000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 151274 # Simulator instruction rate (inst/s) 8host_op_rate 299020 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1905679647 # Simulator tick rate (ticks/s) 10host_mem_usage 770140 # Number of bytes of host memory used 11host_seconds 2696.14 # Real time elapsed on the host 12sim_insts 407854776 # Number of instructions simulated 13sim_ops 806198141 # Number of ops (including micro ops) simulated | 7host_inst_rate 152486 # Simulator instruction rate (inst/s) 8host_op_rate 301416 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1922658876 # Simulator tick rate (ticks/s) 10host_mem_usage 770128 # Number of bytes of host memory used 11host_seconds 2674.40 # Real time elapsed on the host 12sim_insts 407807707 # Number of instructions simulated 13sim_ops 806107146 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::pc.south_bridge.ide 2477120 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 256 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1034624 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10750336 # Number of bytes read from this memory 21system.physmem.bytes_read::total 14265472 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1034624 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1034624 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9529024 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9529024 # Number of bytes written to this memory 26system.physmem.num_reads::pc.south_bridge.ide 38705 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 4 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 16166 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 167974 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 222898 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 148891 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 148891 # Number of write requests responded to by this memory 34system.physmem.bw_read::pc.south_bridge.ide 482120 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 201368 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 2092331 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2776479 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 201368 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 201368 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1854627 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1854627 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1854627 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::pc.south_bridge.ide 482120 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.inst 201368 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.data 2092331 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4631107 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 222898 # Number of read requests accepted 52system.physmem.writeReqs 148891 # Number of write requests accepted 53system.physmem.readBursts 222898 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 148891 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 14252672 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 12800 # Total number of bytes read from write queue 57system.physmem.bytesWritten 9527360 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 14265472 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 9529024 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 200 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::pc.south_bridge.ide 2476992 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1035072 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10749056 # Number of bytes read from this memory 21system.physmem.bytes_read::total 14265280 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1035072 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1035072 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9521344 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9521344 # Number of bytes written to this memory 26system.physmem.num_reads::pc.south_bridge.ide 38703 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 16173 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 167954 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 222895 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 148771 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 148771 # Number of write requests responded to by this memory 34system.physmem.bw_read::pc.south_bridge.ide 481721 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 747 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 201299 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 2090459 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2774289 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 201299 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 201299 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1851696 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1851696 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1851696 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::pc.south_bridge.ide 481721 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.dtb.walker 747 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.inst 201299 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.data 2090459 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4625984 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 222895 # Number of read requests accepted 52system.physmem.writeReqs 148771 # Number of write requests accepted 53system.physmem.readBursts 222895 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 148771 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 14256576 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue 57system.physmem.bytesWritten 9520064 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 14265280 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 9521344 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue |
| 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 62system.physmem.neitherReadNorWriteReqs 1701 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 14548 # Per bank write bursts 64system.physmem.perBankRdBursts::1 13887 # Per bank write bursts 65system.physmem.perBankRdBursts::2 14162 # Per bank write bursts 66system.physmem.perBankRdBursts::3 13520 # Per bank write bursts 67system.physmem.perBankRdBursts::4 14300 # Per bank write bursts 68system.physmem.perBankRdBursts::5 13581 # Per bank write bursts 69system.physmem.perBankRdBursts::6 13426 # Per bank write bursts 70system.physmem.perBankRdBursts::7 13413 # Per bank write bursts 71system.physmem.perBankRdBursts::8 13607 # Per bank write bursts 72system.physmem.perBankRdBursts::9 13662 # Per bank write bursts 73system.physmem.perBankRdBursts::10 13602 # Per bank write bursts 74system.physmem.perBankRdBursts::11 13631 # Per bank write bursts 75system.physmem.perBankRdBursts::12 14336 # Per bank write bursts 76system.physmem.perBankRdBursts::13 14588 # Per bank write bursts 77system.physmem.perBankRdBursts::14 14340 # Per bank write bursts 78system.physmem.perBankRdBursts::15 14095 # Per bank write bursts 79system.physmem.perBankWrBursts::0 9881 # Per bank write bursts 80system.physmem.perBankWrBursts::1 9301 # Per bank write bursts 81system.physmem.perBankWrBursts::2 9417 # Per bank write bursts 82system.physmem.perBankWrBursts::3 9104 # Per bank write bursts 83system.physmem.perBankWrBursts::4 9702 # Per bank write bursts 84system.physmem.perBankWrBursts::5 8858 # Per bank write bursts 85system.physmem.perBankWrBursts::6 8862 # Per bank write bursts 86system.physmem.perBankWrBursts::7 8906 # Per bank write bursts 87system.physmem.perBankWrBursts::8 8978 # Per bank write bursts 88system.physmem.perBankWrBursts::9 9056 # Per bank write bursts 89system.physmem.perBankWrBursts::10 9081 # Per bank write bursts 90system.physmem.perBankWrBursts::11 9102 # Per bank write bursts 91system.physmem.perBankWrBursts::12 9605 # Per bank write bursts 92system.physmem.perBankWrBursts::13 9854 # Per bank write bursts 93system.physmem.perBankWrBursts::14 9646 # Per bank write bursts 94system.physmem.perBankWrBursts::15 9512 # Per bank write bursts | 62system.physmem.neitherReadNorWriteReqs 1680 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 14406 # Per bank write bursts 64system.physmem.perBankRdBursts::1 13692 # Per bank write bursts 65system.physmem.perBankRdBursts::2 14137 # Per bank write bursts 66system.physmem.perBankRdBursts::3 13444 # Per bank write bursts 67system.physmem.perBankRdBursts::4 14027 # Per bank write bursts 68system.physmem.perBankRdBursts::5 13372 # Per bank write bursts 69system.physmem.perBankRdBursts::6 13359 # Per bank write bursts 70system.physmem.perBankRdBursts::7 13805 # Per bank write bursts 71system.physmem.perBankRdBursts::8 13762 # Per bank write bursts 72system.physmem.perBankRdBursts::9 13592 # Per bank write bursts 73system.physmem.perBankRdBursts::10 13956 # Per bank write bursts 74system.physmem.perBankRdBursts::11 13564 # Per bank write bursts 75system.physmem.perBankRdBursts::12 14528 # Per bank write bursts 76system.physmem.perBankRdBursts::13 14698 # Per bank write bursts 77system.physmem.perBankRdBursts::14 14291 # Per bank write bursts 78system.physmem.perBankRdBursts::15 14126 # Per bank write bursts 79system.physmem.perBankWrBursts::0 9807 # Per bank write bursts 80system.physmem.perBankWrBursts::1 9166 # Per bank write bursts 81system.physmem.perBankWrBursts::2 9421 # Per bank write bursts 82system.physmem.perBankWrBursts::3 8835 # Per bank write bursts 83system.physmem.perBankWrBursts::4 9422 # Per bank write bursts 84system.physmem.perBankWrBursts::5 8917 # Per bank write bursts 85system.physmem.perBankWrBursts::6 8763 # Per bank write bursts 86system.physmem.perBankWrBursts::7 9221 # Per bank write bursts 87system.physmem.perBankWrBursts::8 9116 # Per bank write bursts 88system.physmem.perBankWrBursts::9 9134 # Per bank write bursts 89system.physmem.perBankWrBursts::10 9470 # Per bank write bursts 90system.physmem.perBankWrBursts::11 8904 # Per bank write bursts 91system.physmem.perBankWrBursts::12 9718 # Per bank write bursts 92system.physmem.perBankWrBursts::13 9806 # Per bank write bursts 93system.physmem.perBankWrBursts::14 9580 # Per bank write bursts 94system.physmem.perBankWrBursts::15 9471 # Per bank write bursts |
| 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 96system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 97system.physmem.totGap 5137971883500 # Total gap between requests | 96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 97system.physmem.totGap 5141959559500 # Total gap between requests |
| 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) | 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 104system.physmem.readPktSize::6 222898 # Read request sizes (log2) | 104system.physmem.readPktSize::6 222895 # Read request sizes (log2) |
| 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) | 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 111system.physmem.writePktSize::6 148891 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 173419 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 13832 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 4649 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 2839 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 2570 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 4077 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 3447 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 3320 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 2968 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 1633 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 1479 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 1288 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 1096 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 836 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 757 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 696 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 691 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 416 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see | 111system.physmem.writePktSize::6 148771 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 173187 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 13769 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 5947 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 3181 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 3035 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 3711 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 3299 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 3149 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 2487 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 1694 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 1507 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 1005 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 833 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 764 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 718 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 557 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 456 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 376 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see |
| 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::15 1621 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 1713 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 2212 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 6088 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 6446 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 6593 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 6786 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 6786 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 6856 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 8981 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 7771 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 7845 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 9165 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 8452 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 8559 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 8587 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 8595 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 2877 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 2483 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 2347 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 2192 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 2164 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 2092 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 1899 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 1791 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 1654 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 1568 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 1402 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 1217 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 1040 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 892 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 750 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 634 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 513 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 450 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 352 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 284 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 49 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 49868 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 381.994064 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 221.175651 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 374.202346 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 15813 31.71% 31.71% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 11064 22.19% 53.90% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 5080 10.19% 64.08% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 2824 5.66% 69.75% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 1980 3.97% 73.72% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1284 2.57% 76.29% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 922 1.85% 78.14% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 716 1.44% 79.58% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 10185 20.42% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 49868 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 8142 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 27.350037 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 531.765782 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 8141 99.99% 99.99% # Reads before turning the bus around for writes | 159system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 1818 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 6295 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 6657 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 6807 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 6895 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 7018 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 7687 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 7974 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 8492 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 8737 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 8899 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 9209 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 9147 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 9322 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 9232 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 9176 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 1873 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 1747 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 1906 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 1843 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 1738 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 1562 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 1321 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 1057 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 845 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 632 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 486 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 196 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 94 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 74587 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 318.776409 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 185.138812 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 338.199277 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 28275 37.91% 37.91% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 16828 22.56% 60.47% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 7503 10.06% 70.53% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 4244 5.69% 76.22% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 3057 4.10% 80.32% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 2068 2.77% 83.09% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1382 1.85% 84.94% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1175 1.58% 86.52% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 10055 13.48% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 74587 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 8285 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 26.884007 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 527.034010 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 8284 99.99% 99.99% # Reads before turning the bus around for writes |
| 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes | 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 227system.physmem.rdPerTurnAround::total 8142 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 8142 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 18.283591 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 17.627324 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 6.611364 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-17 6056 74.38% 74.38% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::18-19 1276 15.67% 90.05% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::20-21 101 1.24% 91.29% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::22-23 41 0.50% 91.80% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::24-25 52 0.64% 92.43% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::26-27 70 0.86% 93.29% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-29 65 0.80% 94.09% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::30-31 71 0.87% 94.96% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-33 51 0.63% 95.59% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::34-35 44 0.54% 96.13% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-37 56 0.69% 96.82% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::38-39 33 0.41% 97.22% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-41 34 0.42% 97.64% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::42-43 29 0.36% 98.00% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::44-45 35 0.43% 98.43% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::46-47 23 0.28% 98.71% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::48-49 19 0.23% 98.94% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::50-51 12 0.15% 99.09% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::52-53 12 0.15% 99.24% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::54-55 9 0.11% 99.35% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::56-57 6 0.07% 99.42% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::58-59 7 0.09% 99.51% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::60-61 2 0.02% 99.53% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::62-63 13 0.16% 99.69% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::64-65 13 0.16% 99.85% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::66-67 1 0.01% 99.86% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::70-71 1 0.01% 99.88% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::72-73 4 0.05% 99.93% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::74-75 3 0.04% 99.96% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::76-77 2 0.02% 99.99% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::80-81 1 0.01% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 8142 # Writes before turning the bus around for reads 264system.physmem.totQLat 5275412250 # Total ticks spent queuing 265system.physmem.totMemAccLat 9510468500 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 1113490000 # Total ticks spent in databus transfers 267system.physmem.totBankLat 3121566250 # Total ticks spent accessing banks 268system.physmem.avgQLat 23688.64 # Average queueing delay per DRAM burst 269system.physmem.avgBankLat 14017.04 # Average bank access latency per DRAM burst | 227system.physmem.rdPerTurnAround::total 8285 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 8285 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 17.954255 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 17.428609 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 5.676130 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-17 6158 74.33% 74.33% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::18-19 1338 16.15% 90.48% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::20-21 52 0.63% 91.10% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::22-23 77 0.93% 92.03% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::24-25 47 0.57% 92.60% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::26-27 55 0.66% 93.26% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-29 103 1.24% 94.51% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::30-31 89 1.07% 95.58% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-33 47 0.57% 96.15% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::34-35 58 0.70% 96.85% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-37 37 0.45% 97.30% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::38-39 45 0.54% 97.84% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-41 69 0.83% 98.67% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::42-43 27 0.33% 99.00% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::44-45 11 0.13% 99.13% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::46-47 16 0.19% 99.32% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::48-49 22 0.27% 99.59% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::50-51 4 0.05% 99.64% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::52-53 7 0.08% 99.72% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::54-55 3 0.04% 99.76% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::56-57 2 0.02% 99.78% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::58-59 3 0.04% 99.82% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::60-61 5 0.06% 99.88% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::62-63 4 0.05% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::64-65 3 0.04% 99.96% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::66-67 1 0.01% 99.98% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::80-81 1 0.01% 99.99% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::88-89 1 0.01% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::total 8285 # Writes before turning the bus around for reads 261system.physmem.totQLat 4923822749 # Total ticks spent queuing 262system.physmem.totMemAccLat 9100553999 # Total ticks spent from burst creation until serviced by the DRAM 263system.physmem.totBusLat 1113795000 # Total ticks spent in databus transfers 264system.physmem.avgQLat 22103.81 # Average queueing delay per DRAM burst |
| 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 265system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 271system.physmem.avgMemAccLat 42705.68 # Average memory access latency per DRAM burst | 266system.physmem.avgMemAccLat 40853.81 # Average memory access latency per DRAM burst |
| 272system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s | 267system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s 268system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s |
| 274system.physmem.avgRdBWSys 2.78 # Average system read bandwidth in MiByte/s | 269system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s |
| 275system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.04 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes | 270system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s 271system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 272system.physmem.busUtil 0.04 # Data bus utilization in percentage 273system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 274system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes |
| 280system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 281system.physmem.avgWrQLen 24.02 # Average write queue length when enqueuing 282system.physmem.readRowHits 186969 # Number of row buffer hits during reads 283system.physmem.writeRowHits 110725 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 83.96 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes 286system.physmem.avgGap 13819590.91 # Average gap between requests 287system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined 288system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state 289system.membus.throughput 5100645 # Throughput (bytes/s) 290system.membus.trans_dist::ReadReq 662331 # Transaction distribution 291system.membus.trans_dist::ReadResp 662323 # Transaction distribution 292system.membus.trans_dist::WriteReq 13764 # Transaction distribution 293system.membus.trans_dist::WriteResp 13764 # Transaction distribution 294system.membus.trans_dist::Writeback 148891 # Transaction distribution 295system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution 296system.membus.trans_dist::UpgradeResp 1718 # Transaction distribution 297system.membus.trans_dist::ReadExReq 179464 # Transaction distribution 298system.membus.trans_dist::ReadExResp 179461 # Transaction distribution 299system.membus.trans_dist::MessageReq 1643 # Transaction distribution 300system.membus.trans_dist::MessageResp 1643 # Transaction distribution 301system.membus.trans_dist::BadAddressError 8 # Transaction distribution 302system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) 303system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775076 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475146 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721276 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 133006 # Packet count per connected master and slave (bytes) 310system.membus.pkt_count_system.iocache.mem_side::total 133006 # Packet count per connected master and slave (bytes) 311system.membus.pkt_count::total 1857568 # Packet count per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550149 # Cumulative packet size per connected master and slave (bytes) 316system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18330624 # Cumulative packet size per connected master and slave (bytes) 317system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20122575 # Cumulative packet size per connected master and slave (bytes) 318system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463872 # Cumulative packet size per connected master and slave (bytes) 319system.membus.tot_pkt_size_system.iocache.mem_side::total 5463872 # Cumulative packet size per connected master and slave (bytes) 320system.membus.tot_pkt_size::total 25593019 # Cumulative packet size per connected master and slave (bytes) 321system.membus.data_through_bus 25593019 # Total data (bytes) 322system.membus.snoop_data_through_bus 613952 # Total snoop data (bytes) 323system.membus.reqLayer0.occupancy 250521000 # Layer occupancy (ticks) | 275system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing 276system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing 277system.physmem.readRowHits 186870 # Number of row buffer hits during reads 278system.physmem.writeRowHits 110052 # Number of row buffer hits during writes 279system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads 280system.physmem.writeRowHitRate 73.97 # Row buffer hit rate for writes 281system.physmem.avgGap 13834893.59 # Average gap between requests 282system.physmem.pageHitRate 79.92 # Row buffer hit rate, read and write combined 283system.physmem.memoryStateTime::IDLE 4934274417750 # Time in different power states 284system.physmem.memoryStateTime::REF 171701140000 # Time in different power states 285system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 286system.physmem.memoryStateTime::ACT 35983950250 # Time in different power states 287system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 288system.membus.throughput 5095093 # Throughput (bytes/s) 289system.membus.trans_dist::ReadReq 662466 # Transaction distribution 290system.membus.trans_dist::ReadResp 662464 # Transaction distribution 291system.membus.trans_dist::WriteReq 13782 # Transaction distribution 292system.membus.trans_dist::WriteResp 13782 # Transaction distribution 293system.membus.trans_dist::Writeback 148771 # Transaction distribution 294system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution 295system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution 296system.membus.trans_dist::ReadExReq 179320 # Transaction distribution 297system.membus.trans_dist::ReadExResp 179319 # Transaction distribution 298system.membus.trans_dist::MessageReq 1645 # Transaction distribution 299system.membus.trans_dist::MessageResp 1645 # Transaction distribution 300system.membus.trans_dist::BadAddressError 2 # Transaction distribution 301system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) 302system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) 303system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775082 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475021 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721191 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132996 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.iocache.mem_side::total 132996 # Packet count per connected master and slave (bytes) 310system.membus.pkt_count::total 1857477 # Packet count per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550161 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322944 # Cumulative packet size per connected master and slave (bytes) 316system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20114933 # Cumulative packet size per connected master and slave (bytes) 317system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463680 # Cumulative packet size per connected master and slave (bytes) 318system.membus.tot_pkt_size_system.iocache.mem_side::total 5463680 # Cumulative packet size per connected master and slave (bytes) 319system.membus.tot_pkt_size::total 25585193 # Cumulative packet size per connected master and slave (bytes) 320system.membus.data_through_bus 25585193 # Total data (bytes) 321system.membus.snoop_data_through_bus 613568 # Total snoop data (bytes) 322system.membus.reqLayer0.occupancy 250592000 # Layer occupancy (ticks) |
| 324system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 323system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 325system.membus.reqLayer1.occupancy 583253500 # Layer occupancy (ticks) | 324system.membus.reqLayer1.occupancy 583283000 # Layer occupancy (ticks) |
| 326system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 325system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 327system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) | 326system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) |
| 328system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 327system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 329system.membus.reqLayer3.occupancy 1611616249 # Layer occupancy (ticks) | 328system.membus.reqLayer3.occupancy 1610033997 # Layer occupancy (ticks) |
| 330system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 329system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 331system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) | 330system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) |
| 332system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 331system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 333system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) | 332system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) |
| 334system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 333system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 335system.membus.respLayer2.occupancy 3152435901 # Layer occupancy (ticks) | 334system.membus.respLayer2.occupancy 3152758703 # Layer occupancy (ticks) |
| 336system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 335system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 337system.membus.respLayer4.occupancy 429736248 # Layer occupancy (ticks) | 336system.membus.respLayer4.occupancy 429601748 # Layer occupancy (ticks) |
| 338system.membus.respLayer4.utilization 0.0 # Layer utilization (%) | 337system.membus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 339system.iocache.tags.replacements 47579 # number of replacements 340system.iocache.tags.tagsinuse 0.116331 # Cycle average of tags in use | 338system.iocache.tags.replacements 47571 # number of replacements 339system.iocache.tags.tagsinuse 0.128712 # Cycle average of tags in use |
| 341system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 340system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 342system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. | 341system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. |
| 343system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 342system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 344system.iocache.tags.warmup_cycle 4992993838000 # Cycle when the warmup percentage was hit. 345system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116331 # Average occupied blocks per requestor 346system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007271 # Average percentage of cache occupancy 347system.iocache.tags.occ_percent::total 0.007271 # Average percentage of cache occupancy | 343system.iocache.tags.warmup_cycle 4992977133000 # Cycle when the warmup percentage was hit. 344system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128712 # Average occupied blocks per requestor 345system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008045 # Average percentage of cache occupancy 346system.iocache.tags.occ_percent::total 0.008045 # Average percentage of cache occupancy |
| 348system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 349system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 350system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 347system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 348system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 349system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 351system.iocache.tags.tag_accesses 428697 # Number of tag accesses 352system.iocache.tags.data_accesses 428697 # Number of data accesses 353system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses 354system.iocache.ReadReq_misses::total 913 # number of ReadReq misses | 350system.iocache.tags.tag_accesses 428634 # Number of tag accesses 351system.iocache.tags.data_accesses 428634 # Number of data accesses 352system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses 353system.iocache.ReadReq_misses::total 906 # number of ReadReq misses |
| 355system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 356system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses | 354system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 355system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses |
| 357system.iocache.demand_misses::pc.south_bridge.ide 47633 # number of demand (read+write) misses 358system.iocache.demand_misses::total 47633 # number of demand (read+write) misses 359system.iocache.overall_misses::pc.south_bridge.ide 47633 # number of overall misses 360system.iocache.overall_misses::total 47633 # number of overall misses 361system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149265435 # number of ReadReq miss cycles 362system.iocache.ReadReq_miss_latency::total 149265435 # number of ReadReq miss cycles 363system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11474717915 # number of WriteReq miss cycles 364system.iocache.WriteReq_miss_latency::total 11474717915 # number of WriteReq miss cycles 365system.iocache.demand_miss_latency::pc.south_bridge.ide 11623983350 # number of demand (read+write) miss cycles 366system.iocache.demand_miss_latency::total 11623983350 # number of demand (read+write) miss cycles 367system.iocache.overall_miss_latency::pc.south_bridge.ide 11623983350 # number of overall miss cycles 368system.iocache.overall_miss_latency::total 11623983350 # number of overall miss cycles 369system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) 370system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) | 356system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses 357system.iocache.demand_misses::total 47626 # number of demand (read+write) misses 358system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses 359system.iocache.overall_misses::total 47626 # number of overall misses 360system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147491196 # number of ReadReq miss cycles 361system.iocache.ReadReq_miss_latency::total 147491196 # number of ReadReq miss cycles 362system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11109159898 # number of WriteReq miss cycles 363system.iocache.WriteReq_miss_latency::total 11109159898 # number of WriteReq miss cycles 364system.iocache.demand_miss_latency::pc.south_bridge.ide 11256651094 # number of demand (read+write) miss cycles 365system.iocache.demand_miss_latency::total 11256651094 # number of demand (read+write) miss cycles 366system.iocache.overall_miss_latency::pc.south_bridge.ide 11256651094 # number of overall miss cycles 367system.iocache.overall_miss_latency::total 11256651094 # number of overall miss cycles 368system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) 369system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) |
| 371system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 372system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) | 370system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 371system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) |
| 373system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses 374system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses 375system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses 376system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses | 372system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses 373system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses 374system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses 375system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses |
| 377system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 378system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 379system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 380system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 381system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 382system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 383system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 384system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 376system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 377system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 378system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 379system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 380system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 381system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 382system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 383system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 385system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163488.975904 # average ReadReq miss latency 386system.iocache.ReadReq_avg_miss_latency::total 163488.975904 # average ReadReq miss latency 387system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245606.119756 # average WriteReq miss latency 388system.iocache.WriteReq_avg_miss_latency::total 245606.119756 # average WriteReq miss latency 389system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244032.148930 # average overall miss latency 390system.iocache.demand_avg_miss_latency::total 244032.148930 # average overall miss latency 391system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244032.148930 # average overall miss latency 392system.iocache.overall_avg_miss_latency::total 244032.148930 # average overall miss latency 393system.iocache.blocked_cycles::no_mshrs 177888 # number of cycles access was blocked | 384system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570 # average ReadReq miss latency 385system.iocache.ReadReq_avg_miss_latency::total 162793.814570 # average ReadReq miss latency 386system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899 # average WriteReq miss latency 387system.iocache.WriteReq_avg_miss_latency::total 237781.675899 # average WriteReq miss latency 388system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency 389system.iocache.demand_avg_miss_latency::total 236355.165120 # average overall miss latency 390system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency 391system.iocache.overall_avg_miss_latency::total 236355.165120 # average overall miss latency 392system.iocache.blocked_cycles::no_mshrs 159859 # number of cycles access was blocked |
| 394system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 393system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 395system.iocache.blocked::no_mshrs 14382 # number of cycles access was blocked | 394system.iocache.blocked::no_mshrs 14672 # number of cycles access was blocked |
| 396system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 395system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 397system.iocache.avg_blocked_cycles::no_mshrs 12.368794 # average number of cycles each access was blocked | 396system.iocache.avg_blocked_cycles::no_mshrs 10.895515 # average number of cycles each access was blocked |
| 398system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 399system.iocache.fast_writes 0 # number of fast writes performed 400system.iocache.cache_copies 0 # number of cache copies performed | 397system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 398system.iocache.fast_writes 0 # number of fast writes performed 399system.iocache.cache_copies 0 # number of cache copies performed |
| 401system.iocache.writebacks::writebacks 46668 # number of writebacks 402system.iocache.writebacks::total 46668 # number of writebacks 403system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 913 # number of ReadReq MSHR misses 404system.iocache.ReadReq_mshr_misses::total 913 # number of ReadReq MSHR misses | 400system.iocache.writebacks::writebacks 46667 # number of writebacks 401system.iocache.writebacks::total 46667 # number of writebacks 402system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses 403system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses |
| 405system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 406system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses | 404system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 405system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses |
| 407system.iocache.demand_mshr_misses::pc.south_bridge.ide 47633 # number of demand (read+write) MSHR misses 408system.iocache.demand_mshr_misses::total 47633 # number of demand (read+write) MSHR misses 409system.iocache.overall_mshr_misses::pc.south_bridge.ide 47633 # number of overall MSHR misses 410system.iocache.overall_mshr_misses::total 47633 # number of overall MSHR misses 411system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101762935 # number of ReadReq MSHR miss cycles 412system.iocache.ReadReq_mshr_miss_latency::total 101762935 # number of ReadReq MSHR miss cycles 413system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9043225919 # number of WriteReq MSHR miss cycles 414system.iocache.WriteReq_mshr_miss_latency::total 9043225919 # number of WriteReq MSHR miss cycles 415system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9144988854 # number of demand (read+write) MSHR miss cycles 416system.iocache.demand_mshr_miss_latency::total 9144988854 # number of demand (read+write) MSHR miss cycles 417system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9144988854 # number of overall MSHR miss cycles 418system.iocache.overall_mshr_miss_latency::total 9144988854 # number of overall MSHR miss cycles | 406system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses 407system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses 408system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses 409system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses 410system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100353196 # number of ReadReq MSHR miss cycles 411system.iocache.ReadReq_mshr_miss_latency::total 100353196 # number of ReadReq MSHR miss cycles 412system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8677810402 # number of WriteReq MSHR miss cycles 413system.iocache.WriteReq_mshr_miss_latency::total 8677810402 # number of WriteReq MSHR miss cycles 414system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of demand (read+write) MSHR miss cycles 415system.iocache.demand_mshr_miss_latency::total 8778163598 # number of demand (read+write) MSHR miss cycles 416system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of overall MSHR miss cycles 417system.iocache.overall_mshr_miss_latency::total 8778163598 # number of overall MSHR miss cycles |
| 419system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 420system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 421system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 422system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 423system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 424system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 425system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 426system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 418system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 419system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 420system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 421system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 422system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 423system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 424system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 425system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 427system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111459.950712 # average ReadReq mshr miss latency 428system.iocache.ReadReq_avg_mshr_miss_latency::total 111459.950712 # average ReadReq mshr miss latency 429system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193562.198609 # average WriteReq mshr miss latency 430system.iocache.WriteReq_avg_mshr_miss_latency::total 193562.198609 # average WriteReq mshr miss latency 431system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300 # average overall mshr miss latency 432system.iocache.demand_avg_mshr_miss_latency::total 191988.513300 # average overall mshr miss latency 433system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300 # average overall mshr miss latency 434system.iocache.overall_avg_mshr_miss_latency::total 191988.513300 # average overall mshr miss latency | 426system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998 # average ReadReq mshr miss latency 427system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998 # average ReadReq mshr miss latency 428system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837 # average WriteReq mshr miss latency 429system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837 # average WriteReq mshr miss latency 430system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency 431system.iocache.demand_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency 432system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency 433system.iocache.overall_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency |
| 435system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 436system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 437system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). | 434system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 435system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 436system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |
| 438system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). | 437system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). |
| 439system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 440system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 441system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 442system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 444system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 445system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 446system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 447system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 438system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 439system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 440system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 441system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 442system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 443system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 444system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 445system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 446system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 448system.iobus.throughput 637649 # Throughput (bytes/s) 449system.iobus.trans_dist::ReadReq 225561 # Transaction distribution 450system.iobus.trans_dist::ReadResp 225561 # Transaction distribution 451system.iobus.trans_dist::WriteReq 57591 # Transaction distribution 452system.iobus.trans_dist::WriteResp 57591 # Transaction distribution 453system.iobus.trans_dist::MessageReq 1643 # Transaction distribution 454system.iobus.trans_dist::MessageResp 1643 # Transaction distribution | 447system.iobus.throughput 637150 # Throughput (bytes/s) 448system.iobus.trans_dist::ReadReq 225562 # Transaction distribution 449system.iobus.trans_dist::ReadResp 225562 # Transaction distribution 450system.iobus.trans_dist::WriteReq 57606 # Transaction distribution 451system.iobus.trans_dist::WriteResp 57606 # Transaction distribution 452system.iobus.trans_dist::MessageReq 1645 # Transaction distribution 453system.iobus.trans_dist::MessageResp 1645 # Transaction distribution |
| 455system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 456system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) | 454system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 455system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) |
| 457system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) | 456system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) |
| 458system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 459system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 460system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 461system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 462system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 463system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 464system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 465system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 466system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 467system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 468system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 469system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 470system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 471system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 472system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) | 457system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 458system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 459system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 460system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 461system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 462system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 463system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 464system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 465system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 466system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 467system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 468system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 469system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 470system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 471system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) |
| 473system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) 474system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95266 # Packet count per connected master and slave (bytes) 475system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95266 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) 477system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) | 472system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) 473system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) 474system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) 475system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) 477system.iobus.pkt_count::total 569626 # Packet count per connected master and slave (bytes) |
| 479system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 480system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) | 478system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 479system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) |
| 481system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) | 480system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) |
| 482system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 483system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 484system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 485system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 486system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 487system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 488system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 489system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 490system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 491system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 492system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 493system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 494system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 495system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 496system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) | 481system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 482system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 483system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 484system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 485system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 486system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 487system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 488system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 489system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 490system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 491system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 492system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 493system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 494system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 495system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) |
| 497system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) 498system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027848 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027848 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.tot_pkt_size::total 3276222 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.data_through_bus 3276222 # Total data (bytes) 504system.iobus.reqLayer0.occupancy 3918904 # Layer occupancy (ticks) | 496system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) 497system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) 498system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.tot_pkt_size::total 3276200 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.data_through_bus 3276200 # Total data (bytes) 503system.iobus.reqLayer0.occupancy 3930346 # Layer occupancy (ticks) |
| 505system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 506system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 507system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 508system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 509system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 504system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 505system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 506system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 507system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 508system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 510system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) | 509system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) |
| 511system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 512system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 513system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 514system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 515system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 516system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 517system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 518system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) --- 13 unchanged lines hidden (view full) --- 532system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 533system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 534system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 535system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 536system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 537system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 538system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 539system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 510system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 511system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 512system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 513system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 514system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 515system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 516system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 517system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) --- 13 unchanged lines hidden (view full) --- 531system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 532system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 533system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 534system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 535system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 536system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 537system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 538system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 540system.iobus.reqLayer18.occupancy 425268102 # Layer occupancy (ticks) | 539system.iobus.reqLayer18.occupancy 424685346 # Layer occupancy (ticks) |
| 541system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 542system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 543system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) | 540system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 541system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 542system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) |
| 544system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) | 543system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) |
| 545system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 544system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 546system.iobus.respLayer1.occupancy 53403752 # Layer occupancy (ticks) | 545system.iobus.respLayer1.occupancy 53671252 # Layer occupancy (ticks) |
| 547system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 546system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 548system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) | 547system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) |
| 549system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 550system.cpu_clk_domain.clock 500 # Clock period in ticks | 548system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 549system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 551system.cpu.branchPred.lookups 85606951 # Number of BP lookups 552system.cpu.branchPred.condPredicted 85606951 # Number of conditional branches predicted 553system.cpu.branchPred.condIncorrect 878900 # Number of conditional branches incorrect 554system.cpu.branchPred.BTBLookups 79252981 # Number of BTB lookups 555system.cpu.branchPred.BTBHits 77536604 # Number of BTB hits | 550system.cpu.branchPred.lookups 85633263 # Number of BP lookups 551system.cpu.branchPred.condPredicted 85633263 # Number of conditional branches predicted 552system.cpu.branchPred.condIncorrect 884686 # Number of conditional branches incorrect 553system.cpu.branchPred.BTBLookups 79267379 # Number of BTB lookups 554system.cpu.branchPred.BTBHits 77548662 # Number of BTB hits |
| 556system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 555system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 557system.cpu.branchPred.BTBHitPct 97.834306 # BTB Hit Percentage 558system.cpu.branchPred.usedRAS 1442152 # Number of times the RAS was used to get a target. 559system.cpu.branchPred.RASInCorrect 179942 # Number of incorrect RAS predictions. | 556system.cpu.branchPred.BTBHitPct 97.831747 # BTB Hit Percentage 557system.cpu.branchPred.usedRAS 1440338 # Number of times the RAS was used to get a target. 558system.cpu.branchPred.RASInCorrect 180105 # Number of incorrect RAS predictions. |
| 560system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 559system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 561system.cpu.numCycles 453123649 # number of cpu cycles simulated | 560system.cpu.numCycles 453234333 # number of cpu cycles simulated |
| 562system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 563system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 561system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 562system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 564system.cpu.fetch.icacheStallCycles 25513299 # Number of cycles fetch is stalled on an Icache miss 565system.cpu.fetch.Insts 422793316 # Number of instructions fetch has processed 566system.cpu.fetch.Branches 85606951 # Number of branches that fetch encountered 567system.cpu.fetch.predictedBranches 78978756 # Number of branches that fetch has predicted taken 568system.cpu.fetch.Cycles 162666775 # Number of cycles fetch has run and was not squashing or blocked 569system.cpu.fetch.SquashCycles 3977899 # Number of cycles fetch has spent squashing 570system.cpu.fetch.TlbCycles 109317 # Number of cycles fetch has spent waiting for tlb 571system.cpu.fetch.BlockedCycles 70887668 # Number of cycles fetch has spent blocked 572system.cpu.fetch.MiscStallCycles 43514 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 573system.cpu.fetch.PendingTrapStallCycles 89257 # Number of stall cycles due to pending traps 574system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR 575system.cpu.fetch.CacheLines 8479758 # Number of cache lines fetched 576system.cpu.fetch.IcacheSquashes 384207 # Number of outstanding Icache misses that were squashed 577system.cpu.fetch.ItlbSquashes 2414 # Number of outstanding ITLB misses that were squashed 578system.cpu.fetch.rateDist::samples 262364646 # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.rateDist::mean 3.182537 # Number of instructions fetched each cycle (Total) 580system.cpu.fetch.rateDist::stdev 3.411732 # Number of instructions fetched each cycle (Total) | 563system.cpu.fetch.icacheStallCycles 25483623 # Number of cycles fetch is stalled on an Icache miss 564system.cpu.fetch.Insts 422835891 # Number of instructions fetch has processed 565system.cpu.fetch.Branches 85633263 # Number of branches that fetch encountered 566system.cpu.fetch.predictedBranches 78989000 # Number of branches that fetch has predicted taken 567system.cpu.fetch.Cycles 162683938 # Number of cycles fetch has run and was not squashing or blocked 568system.cpu.fetch.SquashCycles 4002747 # Number of cycles fetch has spent squashing 569system.cpu.fetch.TlbCycles 108573 # Number of cycles fetch has spent waiting for tlb 570system.cpu.fetch.BlockedCycles 70983982 # Number of cycles fetch has spent blocked 571system.cpu.fetch.MiscStallCycles 43526 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 572system.cpu.fetch.PendingTrapStallCycles 92374 # Number of stall cycles due to pending traps 573system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR 574system.cpu.fetch.CacheLines 8487571 # Number of cache lines fetched 575system.cpu.fetch.IcacheSquashes 384793 # Number of outstanding Icache misses that were squashed 576system.cpu.fetch.ItlbSquashes 2466 # Number of outstanding ITLB misses that were squashed 577system.cpu.fetch.rateDist::samples 262469836 # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::mean 3.181706 # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.rateDist::stdev 3.411661 # Number of instructions fetched each cycle (Total) |
| 581system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 580system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 582system.cpu.fetch.rateDist::0 100112047 38.16% 38.16% # Number of instructions fetched each cycle (Total) 583system.cpu.fetch.rateDist::1 1537808 0.59% 38.74% # Number of instructions fetched each cycle (Total) 584system.cpu.fetch.rateDist::2 71834602 27.38% 66.12% # Number of instructions fetched each cycle (Total) 585system.cpu.fetch.rateDist::3 894624 0.34% 66.46% # Number of instructions fetched each cycle (Total) 586system.cpu.fetch.rateDist::4 1560586 0.59% 67.06% # Number of instructions fetched each cycle (Total) 587system.cpu.fetch.rateDist::5 2393199 0.91% 67.97% # Number of instructions fetched each cycle (Total) 588system.cpu.fetch.rateDist::6 1018516 0.39% 68.36% # Number of instructions fetched each cycle (Total) 589system.cpu.fetch.rateDist::7 1331320 0.51% 68.87% # Number of instructions fetched each cycle (Total) 590system.cpu.fetch.rateDist::8 81681944 31.13% 100.00% # Number of instructions fetched each cycle (Total) | 581system.cpu.fetch.rateDist::0 100201994 38.18% 38.18% # Number of instructions fetched each cycle (Total) 582system.cpu.fetch.rateDist::1 1531970 0.58% 38.76% # Number of instructions fetched each cycle (Total) 583system.cpu.fetch.rateDist::2 71824716 27.36% 66.13% # Number of instructions fetched each cycle (Total) 584system.cpu.fetch.rateDist::3 909581 0.35% 66.47% # Number of instructions fetched each cycle (Total) 585system.cpu.fetch.rateDist::4 1572022 0.60% 67.07% # Number of instructions fetched each cycle (Total) 586system.cpu.fetch.rateDist::5 2391233 0.91% 67.98% # Number of instructions fetched each cycle (Total) 587system.cpu.fetch.rateDist::6 1015593 0.39% 68.37% # Number of instructions fetched each cycle (Total) 588system.cpu.fetch.rateDist::7 1327813 0.51% 68.87% # Number of instructions fetched each cycle (Total) 589system.cpu.fetch.rateDist::8 81694914 31.13% 100.00% # Number of instructions fetched each cycle (Total) |
| 591system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 593system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 590system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 591system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 594system.cpu.fetch.rateDist::total 262364646 # Number of instructions fetched each cycle (Total) 595system.cpu.fetch.branchRate 0.188926 # Number of branch fetches per cycle 596system.cpu.fetch.rate 0.933064 # Number of inst fetches per cycle 597system.cpu.decode.IdleCycles 29407134 # Number of cycles decode is idle 598system.cpu.decode.BlockedCycles 68048451 # Number of cycles decode is blocked 599system.cpu.decode.RunCycles 158512522 # Number of cycles decode is running 600system.cpu.decode.UnblockCycles 3341909 # Number of cycles decode is unblocking 601system.cpu.decode.SquashCycles 3054630 # Number of cycles decode is squashing 602system.cpu.decode.DecodedInsts 832669874 # Number of instructions handled by decode 603system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode 604system.cpu.rename.SquashCycles 3054630 # Number of cycles rename is squashing 605system.cpu.rename.IdleCycles 32105381 # Number of cycles rename is idle 606system.cpu.rename.BlockCycles 42832622 # Number of cycles rename is blocking 607system.cpu.rename.serializeStallCycles 12466754 # count of cycles rename stalled for serializing inst 608system.cpu.rename.RunCycles 158806940 # Number of cycles rename is running 609system.cpu.rename.UnblockCycles 13098319 # Number of cycles rename is unblocking 610system.cpu.rename.RenamedInsts 829768905 # Number of instructions processed by rename 611system.cpu.rename.ROBFullEvents 20738 # Number of times rename has blocked due to ROB full 612system.cpu.rename.IQFullEvents 6073581 # Number of times rename has blocked due to IQ full 613system.cpu.rename.LSQFullEvents 5148249 # Number of times rename has blocked due to LSQ full 614system.cpu.rename.RenamedOperands 991466417 # Number of destination operands rename has renamed 615system.cpu.rename.RenameLookups 1800660067 # Number of register rename lookups that rename has made 616system.cpu.rename.int_rename_lookups 1107048961 # Number of integer rename lookups 617system.cpu.rename.fp_rename_lookups 106 # Number of floating rename lookups 618system.cpu.rename.CommittedMaps 964157062 # Number of HB maps that are committed 619system.cpu.rename.UndoneMaps 27309353 # Number of HB maps that are undone due to squashing 620system.cpu.rename.serializingInsts 454429 # count of serializing insts renamed 621system.cpu.rename.tempSerializingInsts 460129 # count of temporary serializing insts renamed 622system.cpu.rename.skidInsts 29597584 # count of insts added to the skid buffer 623system.cpu.memDep0.insertedLoads 16731616 # Number of loads inserted to the mem dependence unit. 624system.cpu.memDep0.insertedStores 9822119 # Number of stores inserted to the mem dependence unit. 625system.cpu.memDep0.conflictingLoads 1090956 # Number of conflicting loads. 626system.cpu.memDep0.conflictingStores 912656 # Number of conflicting stores. 627system.cpu.iq.iqInstsAdded 824999655 # Number of instructions added to the IQ (excludes non-spec) 628system.cpu.iq.iqNonSpecInstsAdded 1185445 # Number of non-speculative instructions added to the IQ 629system.cpu.iq.iqInstsIssued 821065367 # Number of instructions issued 630system.cpu.iq.iqSquashedInstsIssued 147374 # Number of squashed instructions issued 631system.cpu.iq.iqSquashedInstsExamined 19153823 # Number of squashed instructions iterated over during squash; mainly for profiling 632system.cpu.iq.iqSquashedOperandsExamined 29264539 # Number of squashed operands that are examined and possibly removed from graph 633system.cpu.iq.iqSquashedNonSpecRemoved 130709 # Number of squashed non-spec instructions that were removed 634system.cpu.iq.issued_per_cycle::samples 262364646 # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::mean 3.129482 # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::stdev 2.399412 # Number of insts issued each cycle | 593system.cpu.fetch.rateDist::total 262469836 # Number of instructions fetched each cycle (Total) 594system.cpu.fetch.branchRate 0.188938 # Number of branch fetches per cycle 595system.cpu.fetch.rate 0.932930 # Number of inst fetches per cycle 596system.cpu.decode.IdleCycles 29410093 # Number of cycles decode is idle 597system.cpu.decode.BlockedCycles 68121182 # Number of cycles decode is blocked 598system.cpu.decode.RunCycles 158520657 # Number of cycles decode is running 599system.cpu.decode.UnblockCycles 3344277 # Number of cycles decode is unblocking 600system.cpu.decode.SquashCycles 3073627 # Number of cycles decode is squashing 601system.cpu.decode.DecodedInsts 832752013 # Number of instructions handled by decode 602system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode 603system.cpu.rename.SquashCycles 3073627 # Number of cycles rename is squashing 604system.cpu.rename.IdleCycles 32108860 # Number of cycles rename is idle 605system.cpu.rename.BlockCycles 42947155 # Number of cycles rename is blocking 606system.cpu.rename.serializeStallCycles 12423337 # count of cycles rename stalled for serializing inst 607system.cpu.rename.RunCycles 158815296 # Number of cycles rename is running 608system.cpu.rename.UnblockCycles 13101561 # Number of cycles rename is unblocking 609system.cpu.rename.RenamedInsts 829828808 # Number of instructions processed by rename 610system.cpu.rename.ROBFullEvents 20476 # Number of times rename has blocked due to ROB full 611system.cpu.rename.IQFullEvents 6069323 # Number of times rename has blocked due to IQ full 612system.cpu.rename.LSQFullEvents 5155919 # Number of times rename has blocked due to LSQ full 613system.cpu.rename.RenamedOperands 991491995 # Number of destination operands rename has renamed 614system.cpu.rename.RenameLookups 1800757525 # Number of register rename lookups that rename has made 615system.cpu.rename.int_rename_lookups 1107104494 # Number of integer rename lookups 616system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups 617system.cpu.rename.CommittedMaps 964043985 # Number of HB maps that are committed 618system.cpu.rename.UndoneMaps 27448008 # Number of HB maps that are undone due to squashing 619system.cpu.rename.serializingInsts 454148 # count of serializing insts renamed 620system.cpu.rename.tempSerializingInsts 459927 # count of temporary serializing insts renamed 621system.cpu.rename.skidInsts 29603104 # count of insts added to the skid buffer 622system.cpu.memDep0.insertedLoads 16744391 # Number of loads inserted to the mem dependence unit. 623system.cpu.memDep0.insertedStores 9834089 # Number of stores inserted to the mem dependence unit. 624system.cpu.memDep0.conflictingLoads 1098610 # Number of conflicting loads. 625system.cpu.memDep0.conflictingStores 922271 # Number of conflicting stores. 626system.cpu.iq.iqInstsAdded 825029586 # Number of instructions added to the IQ (excludes non-spec) 627system.cpu.iq.iqNonSpecInstsAdded 1184674 # Number of non-speculative instructions added to the IQ 628system.cpu.iq.iqInstsIssued 821050392 # Number of instructions issued 629system.cpu.iq.iqSquashedInstsIssued 152353 # Number of squashed instructions issued 630system.cpu.iq.iqSquashedInstsExamined 19282759 # Number of squashed instructions iterated over during squash; mainly for profiling 631system.cpu.iq.iqSquashedOperandsExamined 29404306 # Number of squashed operands that are examined and possibly removed from graph 632system.cpu.iq.iqSquashedNonSpecRemoved 129800 # Number of squashed non-spec instructions that were removed 633system.cpu.iq.issued_per_cycle::samples 262469836 # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::mean 3.128170 # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::stdev 2.399623 # Number of insts issued each cycle |
| 637system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 636system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 638system.cpu.iq.issued_per_cycle::0 75980319 28.96% 28.96% # Number of insts issued each cycle 639system.cpu.iq.issued_per_cycle::1 15750588 6.00% 34.96% # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::2 10556494 4.02% 38.99% # Number of insts issued each cycle 641system.cpu.iq.issued_per_cycle::3 7365908 2.81% 41.79% # Number of insts issued each cycle 642system.cpu.iq.issued_per_cycle::4 75746368 28.87% 70.66% # Number of insts issued each cycle 643system.cpu.iq.issued_per_cycle::5 3736962 1.42% 72.09% # Number of insts issued each cycle 644system.cpu.iq.issued_per_cycle::6 72307682 27.56% 99.65% # Number of insts issued each cycle 645system.cpu.iq.issued_per_cycle::7 774907 0.30% 99.94% # Number of insts issued each cycle 646system.cpu.iq.issued_per_cycle::8 145418 0.06% 100.00% # Number of insts issued each cycle | 637system.cpu.iq.issued_per_cycle::0 76068971 28.98% 28.98% # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::1 15764450 6.01% 34.99% # Number of insts issued each cycle 639system.cpu.iq.issued_per_cycle::2 10561557 4.02% 39.01% # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::3 7380977 2.81% 41.82% # Number of insts issued each cycle 641system.cpu.iq.issued_per_cycle::4 75732754 28.85% 70.68% # Number of insts issued each cycle 642system.cpu.iq.issued_per_cycle::5 3744713 1.43% 72.10% # Number of insts issued each cycle 643system.cpu.iq.issued_per_cycle::6 72297753 27.55% 99.65% # Number of insts issued each cycle 644system.cpu.iq.issued_per_cycle::7 770490 0.29% 99.94% # Number of insts issued each cycle 645system.cpu.iq.issued_per_cycle::8 148171 0.06% 100.00% # Number of insts issued each cycle |
| 647system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 649system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 646system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 650system.cpu.iq.issued_per_cycle::total 262364646 # Number of insts issued each cycle | 649system.cpu.iq.issued_per_cycle::total 262469836 # Number of insts issued each cycle |
| 651system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 650system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 652system.cpu.iq.fu_full::IntAlu 352804 33.38% 33.38% # attempts to use FU when none available 653system.cpu.iq.fu_full::IntMult 241 0.02% 33.40% # attempts to use FU when none available 654system.cpu.iq.fu_full::IntDiv 895 0.08% 33.49% # attempts to use FU when none available 655system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.49% # attempts to use FU when none available 656system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.49% # attempts to use FU when none available 657system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.49% # attempts to use FU when none available 658system.cpu.iq.fu_full::FloatMult 0 0.00% 33.49% # attempts to use FU when none available 659system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.49% # attempts to use FU when none available 660system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.49% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.49% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.49% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.49% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.49% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.49% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.49% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdMult 0 0.00% 33.49% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.49% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdShift 0 0.00% 33.49% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.49% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.49% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.49% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.49% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.49% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.49% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.49% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.49% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.49% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.49% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.49% # attempts to use FU when none available 681system.cpu.iq.fu_full::MemRead 548620 51.91% 85.40% # attempts to use FU when none available 682system.cpu.iq.fu_full::MemWrite 154313 14.60% 100.00% # attempts to use FU when none available | 651system.cpu.iq.fu_full::IntAlu 351121 33.32% 33.32% # attempts to use FU when none available 652system.cpu.iq.fu_full::IntMult 242 0.02% 33.34% # attempts to use FU when none available 653system.cpu.iq.fu_full::IntDiv 235 0.02% 33.36% # attempts to use FU when none available 654system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.36% # attempts to use FU when none available 655system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.36% # attempts to use FU when none available 656system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.36% # attempts to use FU when none available 657system.cpu.iq.fu_full::FloatMult 0 0.00% 33.36% # attempts to use FU when none available 658system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.36% # attempts to use FU when none available 659system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.36% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.36% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.36% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.36% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.36% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.36% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.36% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdMult 0 0.00% 33.36% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.36% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdShift 0 0.00% 33.36% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.36% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.36% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.36% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.36% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.36% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.36% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.36% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.36% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.36% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.36% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.36% # attempts to use FU when none available 680system.cpu.iq.fu_full::MemRead 548827 52.08% 85.44% # attempts to use FU when none available 681system.cpu.iq.fu_full::MemWrite 153397 14.56% 100.00% # attempts to use FU when none available |
| 683system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 684system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 682system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 683system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 685system.cpu.iq.FU_type_0::No_OpClass 307554 0.04% 0.04% # Type of FU issued 686system.cpu.iq.FU_type_0::IntAlu 793584898 96.65% 96.69% # Type of FU issued 687system.cpu.iq.FU_type_0::IntMult 150109 0.02% 96.71% # Type of FU issued 688system.cpu.iq.FU_type_0::IntDiv 124066 0.02% 96.72% # Type of FU issued | 684system.cpu.iq.FU_type_0::No_OpClass 310274 0.04% 0.04% # Type of FU issued 685system.cpu.iq.FU_type_0::IntAlu 793553745 96.65% 96.69% # Type of FU issued 686system.cpu.iq.FU_type_0::IntMult 150127 0.02% 96.71% # Type of FU issued 687system.cpu.iq.FU_type_0::IntDiv 124319 0.02% 96.72% # Type of FU issued |
| 689system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued 690system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued 691system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued 692system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued 693system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued 694system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 707system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued | 688system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued 689system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued 690system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued 691system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued 692system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued 693system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 706system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued |
| 715system.cpu.iq.FU_type_0::MemRead 17676623 2.15% 98.88% # Type of FU issued 716system.cpu.iq.FU_type_0::MemWrite 9222117 1.12% 100.00% # Type of FU issued | 714system.cpu.iq.FU_type_0::MemRead 17682976 2.15% 98.88% # Type of FU issued 715system.cpu.iq.FU_type_0::MemWrite 9228951 1.12% 100.00% # Type of FU issued |
| 717system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 718system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 716system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 717system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 719system.cpu.iq.FU_type_0::total 821065367 # Type of FU issued 720system.cpu.iq.rate 1.812012 # Inst issue rate 721system.cpu.iq.fu_busy_cnt 1056873 # FU busy when requested 722system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) 723system.cpu.iq.int_inst_queue_reads 1905808819 # Number of integer instruction queue reads 724system.cpu.iq.int_inst_queue_writes 845349453 # Number of integer instruction queue writes 725system.cpu.iq.int_inst_queue_wakeup_accesses 817155578 # Number of integer instruction queue wakeup accesses 726system.cpu.iq.fp_inst_queue_reads 173 # Number of floating instruction queue reads 727system.cpu.iq.fp_inst_queue_writes 180 # Number of floating instruction queue writes 728system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses 729system.cpu.iq.int_alu_accesses 821814606 # Number of integer alu accesses 730system.cpu.iq.fp_alu_accesses 80 # Number of floating point alu accesses 731system.cpu.iew.lsq.thread0.forwLoads 1693534 # Number of loads that had data forwarded from stores | 718system.cpu.iq.FU_type_0::total 821050392 # Type of FU issued 719system.cpu.iq.rate 1.811536 # Inst issue rate 720system.cpu.iq.fu_busy_cnt 1053822 # FU busy when requested 721system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) 722system.cpu.iq.int_inst_queue_reads 1905885622 # Number of integer instruction queue reads 723system.cpu.iq.int_inst_queue_writes 845507474 # Number of integer instruction queue writes 724system.cpu.iq.int_inst_queue_wakeup_accesses 817131376 # Number of integer instruction queue wakeup accesses 725system.cpu.iq.fp_inst_queue_reads 174 # Number of floating instruction queue reads 726system.cpu.iq.fp_inst_queue_writes 198 # Number of floating instruction queue writes 727system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses 728system.cpu.iq.int_alu_accesses 821793858 # Number of integer alu accesses 729system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses 730system.cpu.iew.lsq.thread0.forwLoads 1694774 # Number of loads that had data forwarded from stores |
| 732system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 731system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 733system.cpu.iew.lsq.thread0.squashedLoads 2731831 # Number of loads squashed 734system.cpu.iew.lsq.thread0.ignoredResponses 17734 # Number of memory responses ignored because the instruction is squashed 735system.cpu.iew.lsq.thread0.memOrderViolation 12108 # Number of memory ordering violations 736system.cpu.iew.lsq.thread0.squashedStores 1395931 # Number of stores squashed | 732system.cpu.iew.lsq.thread0.squashedLoads 2743773 # Number of loads squashed 733system.cpu.iew.lsq.thread0.ignoredResponses 18703 # Number of memory responses ignored because the instruction is squashed 734system.cpu.iew.lsq.thread0.memOrderViolation 12097 # Number of memory ordering violations 735system.cpu.iew.lsq.thread0.squashedStores 1404751 # Number of stores squashed |
| 737system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 738system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 736system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 737system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 739system.cpu.iew.lsq.thread0.rescheduledLoads 1932011 # Number of loads that were rescheduled 740system.cpu.iew.lsq.thread0.cacheBlocked 12232 # Number of times an access to memory failed due to the cache being blocked | 738system.cpu.iew.lsq.thread0.rescheduledLoads 1931902 # Number of loads that were rescheduled 739system.cpu.iew.lsq.thread0.cacheBlocked 12205 # Number of times an access to memory failed due to the cache being blocked |
| 741system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 740system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 742system.cpu.iew.iewSquashCycles 3054630 # Number of cycles IEW is squashing 743system.cpu.iew.iewBlockCycles 30960729 # Number of cycles IEW is blocking 744system.cpu.iew.iewUnblockCycles 2157350 # Number of cycles IEW is unblocking 745system.cpu.iew.iewDispatchedInsts 826185100 # Number of instructions dispatched to IQ 746system.cpu.iew.iewDispSquashedInsts 241589 # Number of squashed instructions skipped by dispatch 747system.cpu.iew.iewDispLoadInsts 16731616 # Number of dispatched load instructions 748system.cpu.iew.iewDispStoreInsts 9822119 # Number of dispatched store instructions 749system.cpu.iew.iewDispNonSpecInsts 690497 # Number of dispatched non-speculative instructions 750system.cpu.iew.iewIQFullEvents 1620390 # Number of times the IQ has become full, causing a stall 751system.cpu.iew.iewLSQFullEvents 12858 # Number of times the LSQ has become full, causing a stall 752system.cpu.iew.memOrderViolationEvents 12108 # Number of memory order violations 753system.cpu.iew.predictedTakenIncorrect 495281 # Number of branches that were predicted taken incorrectly 754system.cpu.iew.predictedNotTakenIncorrect 506440 # Number of branches that were predicted not taken incorrectly 755system.cpu.iew.branchMispredicts 1001721 # Number of branch mispredicts detected at execute 756system.cpu.iew.iewExecutedInsts 819661058 # Number of executed instructions 757system.cpu.iew.iewExecLoadInsts 17373288 # Number of load instructions executed 758system.cpu.iew.iewExecSquashedInsts 1404308 # Number of squashed instructions skipped in execute | 741system.cpu.iew.iewSquashCycles 3073627 # Number of cycles IEW is squashing 742system.cpu.iew.iewBlockCycles 31062869 # Number of cycles IEW is blocking 743system.cpu.iew.iewUnblockCycles 2159597 # Number of cycles IEW is unblocking 744system.cpu.iew.iewDispatchedInsts 826214260 # Number of instructions dispatched to IQ 745system.cpu.iew.iewDispSquashedInsts 248339 # Number of squashed instructions skipped by dispatch 746system.cpu.iew.iewDispLoadInsts 16744391 # Number of dispatched load instructions 747system.cpu.iew.iewDispStoreInsts 9834089 # Number of dispatched store instructions 748system.cpu.iew.iewDispNonSpecInsts 689465 # Number of dispatched non-speculative instructions 749system.cpu.iew.iewIQFullEvents 1620816 # Number of times the IQ has become full, causing a stall 750system.cpu.iew.iewLSQFullEvents 13300 # Number of times the LSQ has become full, causing a stall 751system.cpu.iew.memOrderViolationEvents 12097 # Number of memory order violations 752system.cpu.iew.predictedTakenIncorrect 498594 # Number of branches that were predicted taken incorrectly 753system.cpu.iew.predictedNotTakenIncorrect 510068 # Number of branches that were predicted not taken incorrectly 754system.cpu.iew.branchMispredicts 1008662 # Number of branch mispredicts detected at execute 755system.cpu.iew.iewExecutedInsts 819639552 # Number of executed instructions 756system.cpu.iew.iewExecLoadInsts 17378500 # Number of load instructions executed 757system.cpu.iew.iewExecSquashedInsts 1410839 # Number of squashed instructions skipped in execute |
| 759system.cpu.iew.exec_swp 0 # number of swp insts executed 760system.cpu.iew.exec_nop 0 # number of nop insts executed | 758system.cpu.iew.exec_swp 0 # number of swp insts executed 759system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 761system.cpu.iew.exec_refs 26412112 # number of memory reference insts executed 762system.cpu.iew.exec_branches 83101028 # Number of branches executed 763system.cpu.iew.exec_stores 9038824 # Number of stores executed 764system.cpu.iew.exec_rate 1.808913 # Inst execution rate 765system.cpu.iew.wb_sent 819257147 # cumulative count of insts sent to commit 766system.cpu.iew.wb_count 817155626 # cumulative count of insts written-back 767system.cpu.iew.wb_producers 638657480 # num instructions producing a value 768system.cpu.iew.wb_consumers 1044041746 # num instructions consuming a value | 760system.cpu.iew.exec_refs 26423310 # number of memory reference insts executed 761system.cpu.iew.exec_branches 83104184 # Number of branches executed 762system.cpu.iew.exec_stores 9044810 # Number of stores executed 763system.cpu.iew.exec_rate 1.808423 # Inst execution rate 764system.cpu.iew.wb_sent 819235043 # cumulative count of insts sent to commit 765system.cpu.iew.wb_count 817131426 # cumulative count of insts written-back 766system.cpu.iew.wb_producers 638623234 # num instructions producing a value 767system.cpu.iew.wb_consumers 1043962608 # num instructions consuming a value |
| 769system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 768system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 770system.cpu.iew.wb_rate 1.803383 # insts written-back per cycle 771system.cpu.iew.wb_fanout 0.611716 # average fanout of values written-back | 769system.cpu.iew.wb_rate 1.802890 # insts written-back per cycle 770system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back |
| 772system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 771system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 773system.cpu.commit.commitSquashedInsts 19877862 # The number of squashed insts skipped by commit 774system.cpu.commit.commitNonSpecStalls 1054736 # The number of times commit has been forced to stall to communicate backwards 775system.cpu.commit.branchMispredicts 888910 # The number of times a branch was mispredicted 776system.cpu.commit.committed_per_cycle::samples 259310016 # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::mean 3.109013 # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::stdev 2.863250 # Number of insts commited each cycle | 772system.cpu.commit.commitSquashedInsts 19998130 # The number of squashed insts skipped by commit 773system.cpu.commit.commitNonSpecStalls 1054874 # The number of times commit has been forced to stall to communicate backwards 774system.cpu.commit.branchMispredicts 894775 # The number of times a branch was mispredicted 775system.cpu.commit.committed_per_cycle::samples 259396209 # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::mean 3.107629 # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::stdev 2.863349 # Number of insts commited each cycle |
| 779system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 778system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 780system.cpu.commit.committed_per_cycle::0 87730314 33.83% 33.83% # Number of insts commited each cycle 781system.cpu.commit.committed_per_cycle::1 11862694 4.57% 38.41% # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::2 3835821 1.48% 39.89% # Number of insts commited each cycle 783system.cpu.commit.committed_per_cycle::3 74768182 28.83% 68.72% # Number of insts commited each cycle 784system.cpu.commit.committed_per_cycle::4 2381229 0.92% 69.64% # Number of insts commited each cycle 785system.cpu.commit.committed_per_cycle::5 1479438 0.57% 70.21% # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::6 861979 0.33% 70.54% # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::7 70857593 27.33% 97.87% # Number of insts commited each cycle 788system.cpu.commit.committed_per_cycle::8 5532766 2.13% 100.00% # Number of insts commited each cycle | 779system.cpu.commit.committed_per_cycle::0 87828444 33.86% 33.86% # Number of insts commited each cycle 780system.cpu.commit.committed_per_cycle::1 11868241 4.58% 38.43% # Number of insts commited each cycle 781system.cpu.commit.committed_per_cycle::2 3842531 1.48% 39.92% # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::3 74752258 28.82% 68.73% # Number of insts commited each cycle 783system.cpu.commit.committed_per_cycle::4 2384729 0.92% 69.65% # Number of insts commited each cycle 784system.cpu.commit.committed_per_cycle::5 1479281 0.57% 70.22% # Number of insts commited each cycle 785system.cpu.commit.committed_per_cycle::6 859408 0.33% 70.55% # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::7 70845236 27.31% 97.87% # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::8 5536081 2.13% 100.00% # Number of insts commited each cycle |
| 789system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 788system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 792system.cpu.commit.committed_per_cycle::total 259310016 # Number of insts commited each cycle 793system.cpu.commit.committedInsts 407854776 # Number of instructions committed 794system.cpu.commit.committedOps 806198141 # Number of ops (including micro ops) committed | 791system.cpu.commit.committed_per_cycle::total 259396209 # Number of insts commited each cycle 792system.cpu.commit.committedInsts 407807707 # Number of instructions committed 793system.cpu.commit.committedOps 806107146 # Number of ops (including micro ops) committed |
| 795system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 794system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 796system.cpu.commit.refs 22425972 # Number of memory references committed 797system.cpu.commit.loads 13999784 # Number of loads committed 798system.cpu.commit.membars 474669 # Number of memory barriers committed 799system.cpu.commit.branches 82177261 # Number of branches committed | 795system.cpu.commit.refs 22429955 # Number of memory references committed 796system.cpu.commit.loads 14000617 # Number of loads committed 797system.cpu.commit.membars 474711 # Number of memory barriers committed 798system.cpu.commit.branches 82167469 # Number of branches committed |
| 800system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 799system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 801system.cpu.commit.int_insts 735033306 # Number of committed integer instructions. 802system.cpu.commit.function_calls 1155486 # Number of function calls committed. 803system.cpu.commit.bw_lim_events 5532766 # number cycles where commit BW limit reached | 800system.cpu.commit.int_insts 734952495 # Number of committed integer instructions. 801system.cpu.commit.function_calls 1155627 # Number of function calls committed. 802system.cpu.commit.op_class_0::No_OpClass 174437 0.02% 0.02% # Class of committed instruction 803system.cpu.commit.op_class_0::IntAlu 783236239 97.16% 97.18% # Class of committed instruction 804system.cpu.commit.op_class_0::IntMult 144862 0.02% 97.20% # Class of committed instruction 805system.cpu.commit.op_class_0::IntDiv 121653 0.02% 97.22% # Class of committed instruction 806system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 807system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 808system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction 809system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 810system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 811system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 812system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 813system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction 814system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction 815system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction 816system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction 817system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction 818system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction 819system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction 820system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction 821system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction 822system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction 824system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 825system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 828system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 829system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 830system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction 832system.cpu.commit.op_class_0::MemRead 14000617 1.74% 98.95% # Class of committed instruction 833system.cpu.commit.op_class_0::MemWrite 8429338 1.05% 100.00% # Class of committed instruction 834system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 835system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 836system.cpu.commit.op_class_0::total 806107146 # Class of committed instruction 837system.cpu.commit.bw_lim_events 5536081 # number cycles where commit BW limit reached |
| 804system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 838system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 805system.cpu.rob.rob_reads 1079774887 # The number of ROB reads 806system.cpu.rob.rob_writes 1655221365 # The number of ROB writes 807system.cpu.timesIdled 1257777 # Number of times that the entire CPU went into an idle state and unscheduled itself 808system.cpu.idleCycles 190759003 # Total number of cycles that the CPU has spent unscheduled due to idling 809system.cpu.quiesceCycles 9822826051 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 810system.cpu.committedInsts 407854776 # Number of Instructions Simulated 811system.cpu.committedOps 806198141 # Number of Ops (including micro ops) Simulated 812system.cpu.committedInsts_total 407854776 # Number of Instructions Simulated 813system.cpu.cpi 1.110993 # CPI: Cycles Per Instruction 814system.cpu.cpi_total 1.110993 # CPI: Total CPI of All Threads 815system.cpu.ipc 0.900096 # IPC: Instructions Per Cycle 816system.cpu.ipc_total 0.900096 # IPC: Total IPC of All Threads 817system.cpu.int_regfile_reads 1088904390 # number of integer regfile reads 818system.cpu.int_regfile_writes 653903158 # number of integer regfile writes 819system.cpu.fp_regfile_reads 48 # number of floating regfile reads 820system.cpu.cc_regfile_reads 415697548 # number of cc regfile reads 821system.cpu.cc_regfile_writes 321557341 # number of cc regfile writes 822system.cpu.misc_regfile_reads 264102486 # number of misc regfile reads 823system.cpu.misc_regfile_writes 402568 # number of misc regfile writes 824system.cpu.toL2Bus.throughput 53587278 # Throughput (bytes/s) 825system.cpu.toL2Bus.trans_dist::ReadReq 3014875 # Transaction distribution 826system.cpu.toL2Bus.trans_dist::ReadResp 3014340 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::WriteReq 13764 # Transaction distribution 828system.cpu.toL2Bus.trans_dist::WriteResp 13764 # Transaction distribution 829system.cpu.toL2Bus.trans_dist::Writeback 1579042 # Transaction distribution 830system.cpu.toL2Bus.trans_dist::UpgradeReq 2208 # Transaction distribution 831system.cpu.toL2Bus.trans_dist::UpgradeResp 2208 # Transaction distribution 832system.cpu.toL2Bus.trans_dist::ReadExReq 336648 # Transaction distribution 833system.cpu.toL2Bus.trans_dist::ReadExResp 289942 # Transaction distribution 834system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution 835system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1911181 # Packet count per connected master and slave (bytes) 836system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6131826 # Packet count per connected master and slave (bytes) 837system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18757 # Packet count per connected master and slave (bytes) 838system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 150026 # Packet count per connected master and slave (bytes) 839system.cpu.toL2Bus.pkt_count::total 8211790 # Packet count per connected master and slave (bytes) 840system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61153920 # Cumulative packet size per connected master and slave (bytes) 841system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207959183 # Cumulative packet size per connected master and slave (bytes) 842system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 582080 # Cumulative packet size per connected master and slave (bytes) 843system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5191488 # Cumulative packet size per connected master and slave (bytes) 844system.cpu.toL2Bus.tot_pkt_size::total 274886671 # Cumulative packet size per connected master and slave (bytes) 845system.cpu.toL2Bus.data_through_bus 274861071 # Total data (bytes) 846system.cpu.toL2Bus.snoop_data_through_bus 468864 # Total snoop data (bytes) 847system.cpu.toL2Bus.reqLayer0.occupancy 4035423910 # Layer occupancy (ticks) | 839system.cpu.rob.rob_reads 1079887016 # The number of ROB reads 840system.cpu.rob.rob_writes 1655298855 # The number of ROB writes 841system.cpu.timesIdled 1259672 # Number of times that the entire CPU went into an idle state and unscheduled itself 842system.cpu.idleCycles 190764497 # Total number of cycles that the CPU has spent unscheduled due to idling 843system.cpu.quiesceCycles 9830690598 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 844system.cpu.committedInsts 407807707 # Number of Instructions Simulated 845system.cpu.committedOps 806107146 # Number of Ops (including micro ops) Simulated 846system.cpu.committedInsts_total 407807707 # Number of Instructions Simulated 847system.cpu.cpi 1.111392 # CPI: Cycles Per Instruction 848system.cpu.cpi_total 1.111392 # CPI: Total CPI of All Threads 849system.cpu.ipc 0.899772 # IPC: Instructions Per Cycle 850system.cpu.ipc_total 0.899772 # IPC: Total IPC of All Threads 851system.cpu.int_regfile_reads 1088844162 # number of integer regfile reads 852system.cpu.int_regfile_writes 653876789 # number of integer regfile writes 853system.cpu.fp_regfile_reads 50 # number of floating regfile reads 854system.cpu.cc_regfile_reads 415644137 # number of cc regfile reads 855system.cpu.cc_regfile_writes 321521730 # number of cc regfile writes 856system.cpu.misc_regfile_reads 264115519 # number of misc regfile reads 857system.cpu.misc_regfile_writes 402672 # number of misc regfile writes 858system.cpu.toL2Bus.throughput 53624827 # Throughput (bytes/s) 859system.cpu.toL2Bus.trans_dist::ReadReq 3015737 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::ReadResp 3015197 # Transaction distribution 861system.cpu.toL2Bus.trans_dist::WriteReq 13782 # Transaction distribution 862system.cpu.toL2Bus.trans_dist::WriteResp 13782 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::Writeback 1584798 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::ReadExReq 336401 # Transaction distribution 867system.cpu.toL2Bus.trans_dist::ReadExResp 289692 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution 869system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908205 # Packet count per connected master and slave (bytes) 870system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6128379 # Packet count per connected master and slave (bytes) 871system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19318 # Packet count per connected master and slave (bytes) 872system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159676 # Packet count per connected master and slave (bytes) 873system.cpu.toL2Bus.pkt_count::total 8215578 # Packet count per connected master and slave (bytes) 874system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61059136 # Cumulative packet size per connected master and slave (bytes) 875system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207801717 # Cumulative packet size per connected master and slave (bytes) 876system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 607680 # Cumulative packet size per connected master and slave (bytes) 877system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5615104 # Cumulative packet size per connected master and slave (bytes) 878system.cpu.toL2Bus.tot_pkt_size::total 275083637 # Cumulative packet size per connected master and slave (bytes) 879system.cpu.toL2Bus.data_through_bus 275059381 # Total data (bytes) 880system.cpu.toL2Bus.snoop_data_through_bus 677312 # Total snoop data (bytes) 881system.cpu.toL2Bus.reqLayer0.occupancy 4044441846 # Layer occupancy (ticks) |
| 848system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 882system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 849system.cpu.toL2Bus.snoopLayer0.occupancy 600000 # Layer occupancy (ticks) | 883system.cpu.toL2Bus.snoopLayer0.occupancy 568500 # Layer occupancy (ticks) |
| 850system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 884system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 851system.cpu.toL2Bus.respLayer0.occupancy 1436807344 # Layer occupancy (ticks) | 885system.cpu.toL2Bus.respLayer0.occupancy 1434613560 # Layer occupancy (ticks) |
| 852system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 886system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 853system.cpu.toL2Bus.respLayer1.occupancy 3142634309 # Layer occupancy (ticks) | 887system.cpu.toL2Bus.respLayer1.occupancy 3141764506 # Layer occupancy (ticks) |
| 854system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 888system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 855system.cpu.toL2Bus.respLayer2.occupancy 14495745 # Layer occupancy (ticks) | 889system.cpu.toL2Bus.respLayer2.occupancy 14738244 # Layer occupancy (ticks) |
| 856system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 890system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 857system.cpu.toL2Bus.respLayer3.occupancy 103414152 # Layer occupancy (ticks) | 891system.cpu.toL2Bus.respLayer3.occupancy 107967138 # Layer occupancy (ticks) |
| 858system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 892system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 859system.cpu.icache.tags.replacements 955079 # number of replacements 860system.cpu.icache.tags.tagsinuse 509.954947 # Cycle average of tags in use 861system.cpu.icache.tags.total_refs 7470392 # Total number of references to valid blocks. 862system.cpu.icache.tags.sampled_refs 955591 # Sample count of references to valid blocks. 863system.cpu.icache.tags.avg_refs 7.817562 # Average number of references to valid blocks. 864system.cpu.icache.tags.warmup_cycle 147668859250 # Cycle when the warmup percentage was hit. 865system.cpu.icache.tags.occ_blocks::cpu.inst 509.954947 # Average occupied blocks per requestor 866system.cpu.icache.tags.occ_percent::cpu.inst 0.996006 # Average percentage of cache occupancy 867system.cpu.icache.tags.occ_percent::total 0.996006 # Average percentage of cache occupancy | 893system.cpu.icache.tags.replacements 953583 # number of replacements 894system.cpu.icache.tags.tagsinuse 509.342760 # Cycle average of tags in use 895system.cpu.icache.tags.total_refs 7479724 # Total number of references to valid blocks. 896system.cpu.icache.tags.sampled_refs 954095 # Sample count of references to valid blocks. 897system.cpu.icache.tags.avg_refs 7.839601 # Average number of references to valid blocks. 898system.cpu.icache.tags.warmup_cycle 147639960250 # Cycle when the warmup percentage was hit. 899system.cpu.icache.tags.occ_blocks::cpu.inst 509.342760 # Average occupied blocks per requestor 900system.cpu.icache.tags.occ_percent::cpu.inst 0.994810 # Average percentage of cache occupancy 901system.cpu.icache.tags.occ_percent::total 0.994810 # Average percentage of cache occupancy |
| 868system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 902system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 869system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 870system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 871system.cpu.icache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id | 903system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 904system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id 905system.cpu.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id |
| 872system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 906system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 873system.cpu.icache.tags.tag_accesses 9435405 # Number of tag accesses 874system.cpu.icache.tags.data_accesses 9435405 # Number of data accesses 875system.cpu.icache.ReadReq_hits::cpu.inst 7470392 # number of ReadReq hits 876system.cpu.icache.ReadReq_hits::total 7470392 # number of ReadReq hits 877system.cpu.icache.demand_hits::cpu.inst 7470392 # number of demand (read+write) hits 878system.cpu.icache.demand_hits::total 7470392 # number of demand (read+write) hits 879system.cpu.icache.overall_hits::cpu.inst 7470392 # number of overall hits 880system.cpu.icache.overall_hits::total 7470392 # number of overall hits 881system.cpu.icache.ReadReq_misses::cpu.inst 1009362 # number of ReadReq misses 882system.cpu.icache.ReadReq_misses::total 1009362 # number of ReadReq misses 883system.cpu.icache.demand_misses::cpu.inst 1009362 # number of demand (read+write) misses 884system.cpu.icache.demand_misses::total 1009362 # number of demand (read+write) misses 885system.cpu.icache.overall_misses::cpu.inst 1009362 # number of overall misses 886system.cpu.icache.overall_misses::total 1009362 # number of overall misses 887system.cpu.icache.ReadReq_miss_latency::cpu.inst 14063763284 # number of ReadReq miss cycles 888system.cpu.icache.ReadReq_miss_latency::total 14063763284 # number of ReadReq miss cycles 889system.cpu.icache.demand_miss_latency::cpu.inst 14063763284 # number of demand (read+write) miss cycles 890system.cpu.icache.demand_miss_latency::total 14063763284 # number of demand (read+write) miss cycles 891system.cpu.icache.overall_miss_latency::cpu.inst 14063763284 # number of overall miss cycles 892system.cpu.icache.overall_miss_latency::total 14063763284 # number of overall miss cycles 893system.cpu.icache.ReadReq_accesses::cpu.inst 8479754 # number of ReadReq accesses(hits+misses) 894system.cpu.icache.ReadReq_accesses::total 8479754 # number of ReadReq accesses(hits+misses) 895system.cpu.icache.demand_accesses::cpu.inst 8479754 # number of demand (read+write) accesses 896system.cpu.icache.demand_accesses::total 8479754 # number of demand (read+write) accesses 897system.cpu.icache.overall_accesses::cpu.inst 8479754 # number of overall (read+write) accesses 898system.cpu.icache.overall_accesses::total 8479754 # number of overall (read+write) accesses 899system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119032 # miss rate for ReadReq accesses 900system.cpu.icache.ReadReq_miss_rate::total 0.119032 # miss rate for ReadReq accesses 901system.cpu.icache.demand_miss_rate::cpu.inst 0.119032 # miss rate for demand accesses 902system.cpu.icache.demand_miss_rate::total 0.119032 # miss rate for demand accesses 903system.cpu.icache.overall_miss_rate::cpu.inst 0.119032 # miss rate for overall accesses 904system.cpu.icache.overall_miss_rate::total 0.119032 # miss rate for overall accesses 905system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13933.319546 # average ReadReq miss latency 906system.cpu.icache.ReadReq_avg_miss_latency::total 13933.319546 # average ReadReq miss latency 907system.cpu.icache.demand_avg_miss_latency::cpu.inst 13933.319546 # average overall miss latency 908system.cpu.icache.demand_avg_miss_latency::total 13933.319546 # average overall miss latency 909system.cpu.icache.overall_avg_miss_latency::cpu.inst 13933.319546 # average overall miss latency 910system.cpu.icache.overall_avg_miss_latency::total 13933.319546 # average overall miss latency 911system.cpu.icache.blocked_cycles::no_mshrs 4512 # number of cycles access was blocked | 907system.cpu.icache.tags.tag_accesses 9441724 # Number of tag accesses 908system.cpu.icache.tags.data_accesses 9441724 # Number of data accesses 909system.cpu.icache.ReadReq_hits::cpu.inst 7479724 # number of ReadReq hits 910system.cpu.icache.ReadReq_hits::total 7479724 # number of ReadReq hits 911system.cpu.icache.demand_hits::cpu.inst 7479724 # number of demand (read+write) hits 912system.cpu.icache.demand_hits::total 7479724 # number of demand (read+write) hits 913system.cpu.icache.overall_hits::cpu.inst 7479724 # number of overall hits 914system.cpu.icache.overall_hits::total 7479724 # number of overall hits 915system.cpu.icache.ReadReq_misses::cpu.inst 1007844 # number of ReadReq misses 916system.cpu.icache.ReadReq_misses::total 1007844 # number of ReadReq misses 917system.cpu.icache.demand_misses::cpu.inst 1007844 # number of demand (read+write) misses 918system.cpu.icache.demand_misses::total 1007844 # number of demand (read+write) misses 919system.cpu.icache.overall_misses::cpu.inst 1007844 # number of overall misses 920system.cpu.icache.overall_misses::total 1007844 # number of overall misses 921system.cpu.icache.ReadReq_miss_latency::cpu.inst 14035582232 # number of ReadReq miss cycles 922system.cpu.icache.ReadReq_miss_latency::total 14035582232 # number of ReadReq miss cycles 923system.cpu.icache.demand_miss_latency::cpu.inst 14035582232 # number of demand (read+write) miss cycles 924system.cpu.icache.demand_miss_latency::total 14035582232 # number of demand (read+write) miss cycles 925system.cpu.icache.overall_miss_latency::cpu.inst 14035582232 # number of overall miss cycles 926system.cpu.icache.overall_miss_latency::total 14035582232 # number of overall miss cycles 927system.cpu.icache.ReadReq_accesses::cpu.inst 8487568 # number of ReadReq accesses(hits+misses) 928system.cpu.icache.ReadReq_accesses::total 8487568 # number of ReadReq accesses(hits+misses) 929system.cpu.icache.demand_accesses::cpu.inst 8487568 # number of demand (read+write) accesses 930system.cpu.icache.demand_accesses::total 8487568 # number of demand (read+write) accesses 931system.cpu.icache.overall_accesses::cpu.inst 8487568 # number of overall (read+write) accesses 932system.cpu.icache.overall_accesses::total 8487568 # number of overall (read+write) accesses 933system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118744 # miss rate for ReadReq accesses 934system.cpu.icache.ReadReq_miss_rate::total 0.118744 # miss rate for ReadReq accesses 935system.cpu.icache.demand_miss_rate::cpu.inst 0.118744 # miss rate for demand accesses 936system.cpu.icache.demand_miss_rate::total 0.118744 # miss rate for demand accesses 937system.cpu.icache.overall_miss_rate::cpu.inst 0.118744 # miss rate for overall accesses 938system.cpu.icache.overall_miss_rate::total 0.118744 # miss rate for overall accesses 939system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13926.343990 # average ReadReq miss latency 940system.cpu.icache.ReadReq_avg_miss_latency::total 13926.343990 # average ReadReq miss latency 941system.cpu.icache.demand_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency 942system.cpu.icache.demand_avg_miss_latency::total 13926.343990 # average overall miss latency 943system.cpu.icache.overall_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency 944system.cpu.icache.overall_avg_miss_latency::total 13926.343990 # average overall miss latency 945system.cpu.icache.blocked_cycles::no_mshrs 4168 # number of cycles access was blocked |
| 912system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 946system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 913system.cpu.icache.blocked::no_mshrs 173 # number of cycles access was blocked | 947system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked |
| 914system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 948system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 915system.cpu.icache.avg_blocked_cycles::no_mshrs 26.080925 # average number of cycles each access was blocked | 949system.cpu.icache.avg_blocked_cycles::no_mshrs 21.936842 # average number of cycles each access was blocked |
| 916system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 917system.cpu.icache.fast_writes 0 # number of fast writes performed 918system.cpu.icache.cache_copies 0 # number of cache copies performed | 950system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 951system.cpu.icache.fast_writes 0 # number of fast writes performed 952system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 919system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53711 # number of ReadReq MSHR hits 920system.cpu.icache.ReadReq_mshr_hits::total 53711 # number of ReadReq MSHR hits 921system.cpu.icache.demand_mshr_hits::cpu.inst 53711 # number of demand (read+write) MSHR hits 922system.cpu.icache.demand_mshr_hits::total 53711 # number of demand (read+write) MSHR hits 923system.cpu.icache.overall_mshr_hits::cpu.inst 53711 # number of overall MSHR hits 924system.cpu.icache.overall_mshr_hits::total 53711 # number of overall MSHR hits 925system.cpu.icache.ReadReq_mshr_misses::cpu.inst 955651 # number of ReadReq MSHR misses 926system.cpu.icache.ReadReq_mshr_misses::total 955651 # number of ReadReq MSHR misses 927system.cpu.icache.demand_mshr_misses::cpu.inst 955651 # number of demand (read+write) MSHR misses 928system.cpu.icache.demand_mshr_misses::total 955651 # number of demand (read+write) MSHR misses 929system.cpu.icache.overall_mshr_misses::cpu.inst 955651 # number of overall MSHR misses 930system.cpu.icache.overall_mshr_misses::total 955651 # number of overall MSHR misses 931system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11613116903 # number of ReadReq MSHR miss cycles 932system.cpu.icache.ReadReq_mshr_miss_latency::total 11613116903 # number of ReadReq MSHR miss cycles 933system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11613116903 # number of demand (read+write) MSHR miss cycles 934system.cpu.icache.demand_mshr_miss_latency::total 11613116903 # number of demand (read+write) MSHR miss cycles 935system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11613116903 # number of overall MSHR miss cycles 936system.cpu.icache.overall_mshr_miss_latency::total 11613116903 # number of overall MSHR miss cycles 937system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for ReadReq accesses 938system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112698 # mshr miss rate for ReadReq accesses 939system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for demand accesses 940system.cpu.icache.demand_mshr_miss_rate::total 0.112698 # mshr miss rate for demand accesses 941system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for overall accesses 942system.cpu.icache.overall_mshr_miss_rate::total 0.112698 # mshr miss rate for overall accesses 943system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12152.048083 # average ReadReq mshr miss latency 944system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12152.048083 # average ReadReq mshr miss latency 945system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12152.048083 # average overall mshr miss latency 946system.cpu.icache.demand_avg_mshr_miss_latency::total 12152.048083 # average overall mshr miss latency 947system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12152.048083 # average overall mshr miss latency 948system.cpu.icache.overall_avg_mshr_miss_latency::total 12152.048083 # average overall mshr miss latency | 953system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53688 # number of ReadReq MSHR hits 954system.cpu.icache.ReadReq_mshr_hits::total 53688 # number of ReadReq MSHR hits 955system.cpu.icache.demand_mshr_hits::cpu.inst 53688 # number of demand (read+write) MSHR hits 956system.cpu.icache.demand_mshr_hits::total 53688 # number of demand (read+write) MSHR hits 957system.cpu.icache.overall_mshr_hits::cpu.inst 53688 # number of overall MSHR hits 958system.cpu.icache.overall_mshr_hits::total 53688 # number of overall MSHR hits 959system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954156 # number of ReadReq MSHR misses 960system.cpu.icache.ReadReq_mshr_misses::total 954156 # number of ReadReq MSHR misses 961system.cpu.icache.demand_mshr_misses::cpu.inst 954156 # number of demand (read+write) MSHR misses 962system.cpu.icache.demand_mshr_misses::total 954156 # number of demand (read+write) MSHR misses 963system.cpu.icache.overall_mshr_misses::cpu.inst 954156 # number of overall MSHR misses 964system.cpu.icache.overall_mshr_misses::total 954156 # number of overall MSHR misses 965system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587558437 # number of ReadReq MSHR miss cycles 966system.cpu.icache.ReadReq_mshr_miss_latency::total 11587558437 # number of ReadReq MSHR miss cycles 967system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587558437 # number of demand (read+write) MSHR miss cycles 968system.cpu.icache.demand_mshr_miss_latency::total 11587558437 # number of demand (read+write) MSHR miss cycles 969system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587558437 # number of overall MSHR miss cycles 970system.cpu.icache.overall_mshr_miss_latency::total 11587558437 # number of overall MSHR miss cycles 971system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for ReadReq accesses 972system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112418 # mshr miss rate for ReadReq accesses 973system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for demand accesses 974system.cpu.icache.demand_mshr_miss_rate::total 0.112418 # mshr miss rate for demand accesses 975system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for overall accesses 976system.cpu.icache.overall_mshr_miss_rate::total 0.112418 # mshr miss rate for overall accesses 977system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12144.301809 # average ReadReq mshr miss latency 978system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12144.301809 # average ReadReq mshr miss latency 979system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency 980system.cpu.icache.demand_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency 981system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency 982system.cpu.icache.overall_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency |
| 949system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 983system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 950system.cpu.itb_walker_cache.tags.replacements 8788 # number of replacements 951system.cpu.itb_walker_cache.tags.tagsinuse 5.050842 # Cycle average of tags in use 952system.cpu.itb_walker_cache.tags.total_refs 20362 # Total number of references to valid blocks. 953system.cpu.itb_walker_cache.tags.sampled_refs 8802 # Sample count of references to valid blocks. 954system.cpu.itb_walker_cache.tags.avg_refs 2.313338 # Average number of references to valid blocks. 955system.cpu.itb_walker_cache.tags.warmup_cycle 5105053160000 # Cycle when the warmup percentage was hit. 956system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 5.050842 # Average occupied blocks per requestor 957system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.315678 # Average percentage of cache occupancy 958system.cpu.itb_walker_cache.tags.occ_percent::total 0.315678 # Average percentage of cache occupancy | 984system.cpu.itb_walker_cache.tags.replacements 8939 # number of replacements 985system.cpu.itb_walker_cache.tags.tagsinuse 6.031288 # Cycle average of tags in use 986system.cpu.itb_walker_cache.tags.total_refs 21114 # Total number of references to valid blocks. 987system.cpu.itb_walker_cache.tags.sampled_refs 8953 # Sample count of references to valid blocks. 988system.cpu.itb_walker_cache.tags.avg_refs 2.358316 # Average number of references to valid blocks. 989system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000 # Cycle when the warmup percentage was hit. 990system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031288 # Average occupied blocks per requestor 991system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376956 # Average percentage of cache occupancy 992system.cpu.itb_walker_cache.tags.occ_percent::total 0.376956 # Average percentage of cache occupancy |
| 959system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id | 993system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id |
| 960system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 961system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 962system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id | 994system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 995system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 996system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id |
| 963system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id | 997system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id |
| 964system.cpu.itb_walker_cache.tags.tag_accesses 69716 # Number of tag accesses 965system.cpu.itb_walker_cache.tags.data_accesses 69716 # Number of data accesses 966system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20363 # number of ReadReq hits 967system.cpu.itb_walker_cache.ReadReq_hits::total 20363 # number of ReadReq hits | 998system.cpu.itb_walker_cache.tags.tag_accesses 71741 # Number of tag accesses 999system.cpu.itb_walker_cache.tags.data_accesses 71741 # Number of data accesses 1000system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21134 # number of ReadReq hits 1001system.cpu.itb_walker_cache.ReadReq_hits::total 21134 # number of ReadReq hits |
| 968system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 969system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 1002system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1003system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 970system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20365 # number of demand (read+write) hits 971system.cpu.itb_walker_cache.demand_hits::total 20365 # number of demand (read+write) hits 972system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20365 # number of overall hits 973system.cpu.itb_walker_cache.overall_hits::total 20365 # number of overall hits 974system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9662 # number of ReadReq misses 975system.cpu.itb_walker_cache.ReadReq_misses::total 9662 # number of ReadReq misses 976system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9662 # number of demand (read+write) misses 977system.cpu.itb_walker_cache.demand_misses::total 9662 # number of demand (read+write) misses 978system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9662 # number of overall misses 979system.cpu.itb_walker_cache.overall_misses::total 9662 # number of overall misses 980system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 109674498 # number of ReadReq miss cycles 981system.cpu.itb_walker_cache.ReadReq_miss_latency::total 109674498 # number of ReadReq miss cycles 982system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 109674498 # number of demand (read+write) miss cycles 983system.cpu.itb_walker_cache.demand_miss_latency::total 109674498 # number of demand (read+write) miss cycles 984system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 109674498 # number of overall miss cycles 985system.cpu.itb_walker_cache.overall_miss_latency::total 109674498 # number of overall miss cycles 986system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30025 # number of ReadReq accesses(hits+misses) 987system.cpu.itb_walker_cache.ReadReq_accesses::total 30025 # number of ReadReq accesses(hits+misses) | 1004system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21136 # number of demand (read+write) hits 1005system.cpu.itb_walker_cache.demand_hits::total 21136 # number of demand (read+write) hits 1006system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21136 # number of overall hits 1007system.cpu.itb_walker_cache.overall_hits::total 21136 # number of overall hits 1008system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses 1009system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses 1010system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses 1011system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses 1012system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses 1013system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses 1014system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 107949749 # number of ReadReq miss cycles 1015system.cpu.itb_walker_cache.ReadReq_miss_latency::total 107949749 # number of ReadReq miss cycles 1016system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 107949749 # number of demand (read+write) miss cycles 1017system.cpu.itb_walker_cache.demand_miss_latency::total 107949749 # number of demand (read+write) miss cycles 1018system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 107949749 # number of overall miss cycles 1019system.cpu.itb_walker_cache.overall_miss_latency::total 107949749 # number of overall miss cycles 1020system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30957 # number of ReadReq accesses(hits+misses) 1021system.cpu.itb_walker_cache.ReadReq_accesses::total 30957 # number of ReadReq accesses(hits+misses) |
| 988system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 989system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 1022system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1023system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 990system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30027 # number of demand (read+write) accesses 991system.cpu.itb_walker_cache.demand_accesses::total 30027 # number of demand (read+write) accesses 992system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30027 # number of overall (read+write) accesses 993system.cpu.itb_walker_cache.overall_accesses::total 30027 # number of overall (read+write) accesses 994system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.321799 # miss rate for ReadReq accesses 995system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.321799 # miss rate for ReadReq accesses 996system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.321777 # miss rate for demand accesses 997system.cpu.itb_walker_cache.demand_miss_rate::total 0.321777 # miss rate for demand accesses 998system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.321777 # miss rate for overall accesses 999system.cpu.itb_walker_cache.overall_miss_rate::total 0.321777 # miss rate for overall accesses 1000system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11351.117574 # average ReadReq miss latency 1001system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11351.117574 # average ReadReq miss latency 1002system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11351.117574 # average overall miss latency 1003system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11351.117574 # average overall miss latency 1004system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11351.117574 # average overall miss latency 1005system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11351.117574 # average overall miss latency | 1024system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30959 # number of demand (read+write) accesses 1025system.cpu.itb_walker_cache.demand_accesses::total 30959 # number of demand (read+write) accesses 1026system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30959 # number of overall (read+write) accesses 1027system.cpu.itb_walker_cache.overall_accesses::total 30959 # number of overall (read+write) accesses 1028system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.317311 # miss rate for ReadReq accesses 1029system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.317311 # miss rate for ReadReq accesses 1030system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.317291 # miss rate for demand accesses 1031system.cpu.itb_walker_cache.demand_miss_rate::total 0.317291 # miss rate for demand accesses 1032system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.317291 # miss rate for overall accesses 1033system.cpu.itb_walker_cache.overall_miss_rate::total 0.317291 # miss rate for overall accesses 1034system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10989.488853 # average ReadReq miss latency 1035system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10989.488853 # average ReadReq miss latency 1036system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency 1037system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10989.488853 # average overall miss latency 1038system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency 1039system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10989.488853 # average overall miss latency |
| 1006system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1007system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1008system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1009system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1010system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1011system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1012system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1013system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 1040system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1047system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1014system.cpu.itb_walker_cache.writebacks::writebacks 1311 # number of writebacks 1015system.cpu.itb_walker_cache.writebacks::total 1311 # number of writebacks 1016system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9662 # number of ReadReq MSHR misses 1017system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9662 # number of ReadReq MSHR misses 1018system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9662 # number of demand (read+write) MSHR misses 1019system.cpu.itb_walker_cache.demand_mshr_misses::total 9662 # number of demand (read+write) MSHR misses 1020system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9662 # number of overall MSHR misses 1021system.cpu.itb_walker_cache.overall_mshr_misses::total 9662 # number of overall MSHR misses 1022system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 90345008 # number of ReadReq MSHR miss cycles 1023system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 90345008 # number of ReadReq MSHR miss cycles 1024system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 90345008 # number of demand (read+write) MSHR miss cycles 1025system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 90345008 # number of demand (read+write) MSHR miss cycles 1026system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 90345008 # number of overall MSHR miss cycles 1027system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 90345008 # number of overall MSHR miss cycles 1028system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.321799 # mshr miss rate for ReadReq accesses 1029system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.321799 # mshr miss rate for ReadReq accesses 1030system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.321777 # mshr miss rate for demand accesses 1031system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.321777 # mshr miss rate for demand accesses 1032system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.321777 # mshr miss rate for overall accesses 1033system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.321777 # mshr miss rate for overall accesses 1034system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average ReadReq mshr miss latency 1035system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9350.549369 # average ReadReq mshr miss latency 1036system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average overall mshr miss latency 1037system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9350.549369 # average overall mshr miss latency 1038system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average overall mshr miss latency 1039system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9350.549369 # average overall mshr miss latency | 1048system.cpu.itb_walker_cache.writebacks::writebacks 1983 # number of writebacks 1049system.cpu.itb_walker_cache.writebacks::total 1983 # number of writebacks 1050system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses 1051system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses 1052system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses 1053system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses 1054system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses 1055system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses 1056system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88296261 # number of ReadReq MSHR miss cycles 1057system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 88296261 # number of ReadReq MSHR miss cycles 1058system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 88296261 # number of demand (read+write) MSHR miss cycles 1059system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 88296261 # number of demand (read+write) MSHR miss cycles 1060system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 88296261 # number of overall MSHR miss cycles 1061system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 88296261 # number of overall MSHR miss cycles 1062system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.317311 # mshr miss rate for ReadReq accesses 1063system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.317311 # mshr miss rate for ReadReq accesses 1064system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for demand accesses 1065system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.317291 # mshr miss rate for demand accesses 1066system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for overall accesses 1067system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.317291 # mshr miss rate for overall accesses 1068system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average ReadReq mshr miss latency 1069system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8988.726560 # average ReadReq mshr miss latency 1070system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency 1071system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency 1072system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency 1073system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency |
| 1040system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1074system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1041system.cpu.dtb_walker_cache.tags.replacements 67950 # number of replacements 1042system.cpu.dtb_walker_cache.tags.tagsinuse 13.831671 # Cycle average of tags in use 1043system.cpu.dtb_walker_cache.tags.total_refs 92323 # Total number of references to valid blocks. 1044system.cpu.dtb_walker_cache.tags.sampled_refs 67966 # Sample count of references to valid blocks. 1045system.cpu.dtb_walker_cache.tags.avg_refs 1.358370 # Average number of references to valid blocks. 1046system.cpu.dtb_walker_cache.tags.warmup_cycle 5101646178000 # Cycle when the warmup percentage was hit. 1047system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.831671 # Average occupied blocks per requestor 1048system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.864479 # Average percentage of cache occupancy 1049system.cpu.dtb_walker_cache.tags.occ_percent::total 0.864479 # Average percentage of cache occupancy | 1075system.cpu.dtb_walker_cache.tags.replacements 70861 # number of replacements 1076system.cpu.dtb_walker_cache.tags.tagsinuse 12.940736 # Cycle average of tags in use 1077system.cpu.dtb_walker_cache.tags.total_refs 90199 # Total number of references to valid blocks. 1078system.cpu.dtb_walker_cache.tags.sampled_refs 70877 # Sample count of references to valid blocks. 1079system.cpu.dtb_walker_cache.tags.avg_refs 1.272613 # Average number of references to valid blocks. 1080system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500 # Cycle when the warmup percentage was hit. 1081system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 12.940736 # Average occupied blocks per requestor 1082system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.808796 # Average percentage of cache occupancy 1083system.cpu.dtb_walker_cache.tags.occ_percent::total 0.808796 # Average percentage of cache occupancy |
| 1050system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id | 1084system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id |
| 1051system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 1052system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 1053system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id | 1085system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 1086system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 1087system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id |
| 1054system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1088system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1055system.cpu.dtb_walker_cache.tags.tag_accesses 391373 # Number of tag accesses 1056system.cpu.dtb_walker_cache.tags.data_accesses 391373 # Number of data accesses 1057system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92323 # number of ReadReq hits 1058system.cpu.dtb_walker_cache.ReadReq_hits::total 92323 # number of ReadReq hits 1059system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92323 # number of demand (read+write) hits 1060system.cpu.dtb_walker_cache.demand_hits::total 92323 # number of demand (read+write) hits 1061system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92323 # number of overall hits 1062system.cpu.dtb_walker_cache.overall_hits::total 92323 # number of overall hits 1063system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68909 # number of ReadReq misses 1064system.cpu.dtb_walker_cache.ReadReq_misses::total 68909 # number of ReadReq misses 1065system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68909 # number of demand (read+write) misses 1066system.cpu.dtb_walker_cache.demand_misses::total 68909 # number of demand (read+write) misses 1067system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68909 # number of overall misses 1068system.cpu.dtb_walker_cache.overall_misses::total 68909 # number of overall misses 1069system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 862549215 # number of ReadReq miss cycles 1070system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 862549215 # number of ReadReq miss cycles 1071system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 862549215 # number of demand (read+write) miss cycles 1072system.cpu.dtb_walker_cache.demand_miss_latency::total 862549215 # number of demand (read+write) miss cycles 1073system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 862549215 # number of overall miss cycles 1074system.cpu.dtb_walker_cache.overall_miss_latency::total 862549215 # number of overall miss cycles 1075system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161232 # number of ReadReq accesses(hits+misses) 1076system.cpu.dtb_walker_cache.ReadReq_accesses::total 161232 # number of ReadReq accesses(hits+misses) 1077system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161232 # number of demand (read+write) accesses 1078system.cpu.dtb_walker_cache.demand_accesses::total 161232 # number of demand (read+write) accesses 1079system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161232 # number of overall (read+write) accesses 1080system.cpu.dtb_walker_cache.overall_accesses::total 161232 # number of overall (read+write) accesses 1081system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.427390 # miss rate for ReadReq accesses 1082system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.427390 # miss rate for ReadReq accesses 1083system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.427390 # miss rate for demand accesses 1084system.cpu.dtb_walker_cache.demand_miss_rate::total 0.427390 # miss rate for demand accesses 1085system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.427390 # miss rate for overall accesses 1086system.cpu.dtb_walker_cache.overall_miss_rate::total 0.427390 # miss rate for overall accesses 1087system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12517.221481 # average ReadReq miss latency 1088system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12517.221481 # average ReadReq miss latency 1089system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12517.221481 # average overall miss latency 1090system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12517.221481 # average overall miss latency 1091system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12517.221481 # average overall miss latency 1092system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12517.221481 # average overall miss latency | 1089system.cpu.dtb_walker_cache.tags.tag_accesses 396218 # Number of tag accesses 1090system.cpu.dtb_walker_cache.tags.data_accesses 396218 # Number of data accesses 1091system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90199 # number of ReadReq hits 1092system.cpu.dtb_walker_cache.ReadReq_hits::total 90199 # number of ReadReq hits 1093system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90199 # number of demand (read+write) hits 1094system.cpu.dtb_walker_cache.demand_hits::total 90199 # number of demand (read+write) hits 1095system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90199 # number of overall hits 1096system.cpu.dtb_walker_cache.overall_hits::total 90199 # number of overall hits 1097system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71940 # number of ReadReq misses 1098system.cpu.dtb_walker_cache.ReadReq_misses::total 71940 # number of ReadReq misses 1099system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71940 # number of demand (read+write) misses 1100system.cpu.dtb_walker_cache.demand_misses::total 71940 # number of demand (read+write) misses 1101system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71940 # number of overall misses 1102system.cpu.dtb_walker_cache.overall_misses::total 71940 # number of overall misses 1103system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 878693205 # number of ReadReq miss cycles 1104system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 878693205 # number of ReadReq miss cycles 1105system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 878693205 # number of demand (read+write) miss cycles 1106system.cpu.dtb_walker_cache.demand_miss_latency::total 878693205 # number of demand (read+write) miss cycles 1107system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 878693205 # number of overall miss cycles 1108system.cpu.dtb_walker_cache.overall_miss_latency::total 878693205 # number of overall miss cycles 1109system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162139 # number of ReadReq accesses(hits+misses) 1110system.cpu.dtb_walker_cache.ReadReq_accesses::total 162139 # number of ReadReq accesses(hits+misses) 1111system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162139 # number of demand (read+write) accesses 1112system.cpu.dtb_walker_cache.demand_accesses::total 162139 # number of demand (read+write) accesses 1113system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162139 # number of overall (read+write) accesses 1114system.cpu.dtb_walker_cache.overall_accesses::total 162139 # number of overall (read+write) accesses 1115system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.443693 # miss rate for ReadReq accesses 1116system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.443693 # miss rate for ReadReq accesses 1117system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.443693 # miss rate for demand accesses 1118system.cpu.dtb_walker_cache.demand_miss_rate::total 0.443693 # miss rate for demand accesses 1119system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.443693 # miss rate for overall accesses 1120system.cpu.dtb_walker_cache.overall_miss_rate::total 0.443693 # miss rate for overall accesses 1121system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834 # average ReadReq miss latency 1122system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834 # average ReadReq miss latency 1123system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency 1124system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834 # average overall miss latency 1125system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency 1126system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834 # average overall miss latency |
| 1093system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1094system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1095system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1096system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1097system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1098system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1099system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1100system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 1127system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1128system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1129system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1130system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1131system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1132system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1133system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1134system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1101system.cpu.dtb_walker_cache.writebacks::writebacks 16529 # number of writebacks 1102system.cpu.dtb_walker_cache.writebacks::total 16529 # number of writebacks 1103system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68909 # number of ReadReq MSHR misses 1104system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68909 # number of ReadReq MSHR misses 1105system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68909 # number of demand (read+write) MSHR misses 1106system.cpu.dtb_walker_cache.demand_mshr_misses::total 68909 # number of demand (read+write) MSHR misses 1107system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68909 # number of overall MSHR misses 1108system.cpu.dtb_walker_cache.overall_mshr_misses::total 68909 # number of overall MSHR misses 1109system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 724629911 # number of ReadReq MSHR miss cycles 1110system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 724629911 # number of ReadReq MSHR miss cycles 1111system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 724629911 # number of demand (read+write) MSHR miss cycles 1112system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 724629911 # number of demand (read+write) MSHR miss cycles 1113system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 724629911 # number of overall MSHR miss cycles 1114system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 724629911 # number of overall MSHR miss cycles 1115system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for ReadReq accesses 1116system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.427390 # mshr miss rate for ReadReq accesses 1117system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for demand accesses 1118system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.427390 # mshr miss rate for demand accesses 1119system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for overall accesses 1120system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.427390 # mshr miss rate for overall accesses 1121system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average ReadReq mshr miss latency 1122system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.751368 # average ReadReq mshr miss latency 1123system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average overall mshr miss latency 1124system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.751368 # average overall mshr miss latency 1125system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average overall mshr miss latency 1126system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.751368 # average overall mshr miss latency | 1135system.cpu.dtb_walker_cache.writebacks::writebacks 22838 # number of writebacks 1136system.cpu.dtb_walker_cache.writebacks::total 22838 # number of writebacks 1137system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71940 # number of ReadReq MSHR misses 1138system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71940 # number of ReadReq MSHR misses 1139system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71940 # number of demand (read+write) MSHR misses 1140system.cpu.dtb_walker_cache.demand_mshr_misses::total 71940 # number of demand (read+write) MSHR misses 1141system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71940 # number of overall MSHR misses 1142system.cpu.dtb_walker_cache.overall_mshr_misses::total 71940 # number of overall MSHR misses 1143system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 734698929 # number of ReadReq MSHR miss cycles 1144system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 734698929 # number of ReadReq MSHR miss cycles 1145system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 734698929 # number of demand (read+write) MSHR miss cycles 1146system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 734698929 # number of demand (read+write) MSHR miss cycles 1147system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 734698929 # number of overall MSHR miss cycles 1148system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 734698929 # number of overall MSHR miss cycles 1149system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for ReadReq accesses 1150system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.443693 # mshr miss rate for ReadReq accesses 1151system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for demand accesses 1152system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.443693 # mshr miss rate for demand accesses 1153system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for overall accesses 1154system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.443693 # mshr miss rate for overall accesses 1155system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average ReadReq mshr miss latency 1156system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344 # average ReadReq mshr miss latency 1157system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency 1158system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency 1159system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency 1160system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency |
| 1127system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1161system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1128system.cpu.dcache.tags.replacements 1659840 # number of replacements 1129system.cpu.dcache.tags.tagsinuse 511.996448 # Cycle average of tags in use 1130system.cpu.dcache.tags.total_refs 18992605 # Total number of references to valid blocks. 1131system.cpu.dcache.tags.sampled_refs 1660352 # Sample count of references to valid blocks. 1132system.cpu.dcache.tags.avg_refs 11.438903 # Average number of references to valid blocks. 1133system.cpu.dcache.tags.warmup_cycle 40084250 # Cycle when the warmup percentage was hit. 1134system.cpu.dcache.tags.occ_blocks::cpu.data 511.996448 # Average occupied blocks per requestor 1135system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy 1136system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy | 1162system.cpu.dcache.tags.replacements 1658766 # number of replacements 1163system.cpu.dcache.tags.tagsinuse 511.994288 # Cycle average of tags in use 1164system.cpu.dcache.tags.total_refs 19002910 # Total number of references to valid blocks. 1165system.cpu.dcache.tags.sampled_refs 1659278 # Sample count of references to valid blocks. 1166system.cpu.dcache.tags.avg_refs 11.452517 # Average number of references to valid blocks. 1167system.cpu.dcache.tags.warmup_cycle 39778250 # Cycle when the warmup percentage was hit. 1168system.cpu.dcache.tags.occ_blocks::cpu.data 511.994288 # Average occupied blocks per requestor 1169system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 1170system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy |
| 1137system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1171system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1138system.cpu.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 1139system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id 1140system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id | 1172system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id 1173system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id 1174system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id |
| 1141system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1175system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1142system.cpu.dcache.tags.tag_accesses 87845319 # Number of tag accesses 1143system.cpu.dcache.tags.data_accesses 87845319 # Number of data accesses 1144system.cpu.dcache.ReadReq_hits::cpu.data 10889826 # number of ReadReq hits 1145system.cpu.dcache.ReadReq_hits::total 10889826 # number of ReadReq hits 1146system.cpu.dcache.WriteReq_hits::cpu.data 8100117 # number of WriteReq hits 1147system.cpu.dcache.WriteReq_hits::total 8100117 # number of WriteReq hits 1148system.cpu.dcache.demand_hits::cpu.data 18989943 # number of demand (read+write) hits 1149system.cpu.dcache.demand_hits::total 18989943 # number of demand (read+write) hits 1150system.cpu.dcache.overall_hits::cpu.data 18989943 # number of overall hits 1151system.cpu.dcache.overall_hits::total 18989943 # number of overall hits 1152system.cpu.dcache.ReadReq_misses::cpu.data 2239768 # number of ReadReq misses 1153system.cpu.dcache.ReadReq_misses::total 2239768 # number of ReadReq misses 1154system.cpu.dcache.WriteReq_misses::cpu.data 316527 # number of WriteReq misses 1155system.cpu.dcache.WriteReq_misses::total 316527 # number of WriteReq misses 1156system.cpu.dcache.demand_misses::cpu.data 2556295 # number of demand (read+write) misses 1157system.cpu.dcache.demand_misses::total 2556295 # number of demand (read+write) misses 1158system.cpu.dcache.overall_misses::cpu.data 2556295 # number of overall misses 1159system.cpu.dcache.overall_misses::total 2556295 # number of overall misses 1160system.cpu.dcache.ReadReq_miss_latency::cpu.data 32903838390 # number of ReadReq miss cycles 1161system.cpu.dcache.ReadReq_miss_latency::total 32903838390 # number of ReadReq miss cycles 1162system.cpu.dcache.WriteReq_miss_latency::cpu.data 11976667737 # number of WriteReq miss cycles 1163system.cpu.dcache.WriteReq_miss_latency::total 11976667737 # number of WriteReq miss cycles 1164system.cpu.dcache.demand_miss_latency::cpu.data 44880506127 # number of demand (read+write) miss cycles 1165system.cpu.dcache.demand_miss_latency::total 44880506127 # number of demand (read+write) miss cycles 1166system.cpu.dcache.overall_miss_latency::cpu.data 44880506127 # number of overall miss cycles 1167system.cpu.dcache.overall_miss_latency::total 44880506127 # number of overall miss cycles 1168system.cpu.dcache.ReadReq_accesses::cpu.data 13129594 # number of ReadReq accesses(hits+misses) 1169system.cpu.dcache.ReadReq_accesses::total 13129594 # number of ReadReq accesses(hits+misses) 1170system.cpu.dcache.WriteReq_accesses::cpu.data 8416644 # number of WriteReq accesses(hits+misses) 1171system.cpu.dcache.WriteReq_accesses::total 8416644 # number of WriteReq accesses(hits+misses) 1172system.cpu.dcache.demand_accesses::cpu.data 21546238 # number of demand (read+write) accesses 1173system.cpu.dcache.demand_accesses::total 21546238 # number of demand (read+write) accesses 1174system.cpu.dcache.overall_accesses::cpu.data 21546238 # number of overall (read+write) accesses 1175system.cpu.dcache.overall_accesses::total 21546238 # number of overall (read+write) accesses 1176system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170589 # miss rate for ReadReq accesses 1177system.cpu.dcache.ReadReq_miss_rate::total 0.170589 # miss rate for ReadReq accesses 1178system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 1179system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses 1180system.cpu.dcache.demand_miss_rate::cpu.data 0.118642 # miss rate for demand accesses 1181system.cpu.dcache.demand_miss_rate::total 0.118642 # miss rate for demand accesses 1182system.cpu.dcache.overall_miss_rate::cpu.data 0.118642 # miss rate for overall accesses 1183system.cpu.dcache.overall_miss_rate::total 0.118642 # miss rate for overall accesses 1184system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14690.735107 # average ReadReq miss latency 1185system.cpu.dcache.ReadReq_avg_miss_latency::total 14690.735107 # average ReadReq miss latency 1186system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37837.744448 # average WriteReq miss latency 1187system.cpu.dcache.WriteReq_avg_miss_latency::total 37837.744448 # average WriteReq miss latency 1188system.cpu.dcache.demand_avg_miss_latency::cpu.data 17556.857142 # average overall miss latency 1189system.cpu.dcache.demand_avg_miss_latency::total 17556.857142 # average overall miss latency 1190system.cpu.dcache.overall_avg_miss_latency::cpu.data 17556.857142 # average overall miss latency 1191system.cpu.dcache.overall_avg_miss_latency::total 17556.857142 # average overall miss latency 1192system.cpu.dcache.blocked_cycles::no_mshrs 388578 # number of cycles access was blocked | 1176system.cpu.dcache.tags.tag_accesses 87874474 # Number of tag accesses 1177system.cpu.dcache.tags.data_accesses 87874474 # Number of data accesses 1178system.cpu.dcache.ReadReq_hits::cpu.data 10896738 # number of ReadReq hits 1179system.cpu.dcache.ReadReq_hits::total 10896738 # number of ReadReq hits 1180system.cpu.dcache.WriteReq_hits::cpu.data 8103479 # number of WriteReq hits 1181system.cpu.dcache.WriteReq_hits::total 8103479 # number of WriteReq hits 1182system.cpu.dcache.demand_hits::cpu.data 19000217 # number of demand (read+write) hits 1183system.cpu.dcache.demand_hits::total 19000217 # number of demand (read+write) hits 1184system.cpu.dcache.overall_hits::cpu.data 19000217 # number of overall hits 1185system.cpu.dcache.overall_hits::total 19000217 # number of overall hits 1186system.cpu.dcache.ReadReq_misses::cpu.data 2237270 # number of ReadReq misses 1187system.cpu.dcache.ReadReq_misses::total 2237270 # number of ReadReq misses 1188system.cpu.dcache.WriteReq_misses::cpu.data 316309 # number of WriteReq misses 1189system.cpu.dcache.WriteReq_misses::total 316309 # number of WriteReq misses 1190system.cpu.dcache.demand_misses::cpu.data 2553579 # number of demand (read+write) misses 1191system.cpu.dcache.demand_misses::total 2553579 # number of demand (read+write) misses 1192system.cpu.dcache.overall_misses::cpu.data 2553579 # number of overall misses 1193system.cpu.dcache.overall_misses::total 2553579 # number of overall misses 1194system.cpu.dcache.ReadReq_miss_latency::cpu.data 32758938054 # number of ReadReq miss cycles 1195system.cpu.dcache.ReadReq_miss_latency::total 32758938054 # number of ReadReq miss cycles 1196system.cpu.dcache.WriteReq_miss_latency::cpu.data 12034849454 # number of WriteReq miss cycles 1197system.cpu.dcache.WriteReq_miss_latency::total 12034849454 # number of WriteReq miss cycles 1198system.cpu.dcache.demand_miss_latency::cpu.data 44793787508 # number of demand (read+write) miss cycles 1199system.cpu.dcache.demand_miss_latency::total 44793787508 # number of demand (read+write) miss cycles 1200system.cpu.dcache.overall_miss_latency::cpu.data 44793787508 # number of overall miss cycles 1201system.cpu.dcache.overall_miss_latency::total 44793787508 # number of overall miss cycles 1202system.cpu.dcache.ReadReq_accesses::cpu.data 13134008 # number of ReadReq accesses(hits+misses) 1203system.cpu.dcache.ReadReq_accesses::total 13134008 # number of ReadReq accesses(hits+misses) 1204system.cpu.dcache.WriteReq_accesses::cpu.data 8419788 # number of WriteReq accesses(hits+misses) 1205system.cpu.dcache.WriteReq_accesses::total 8419788 # number of WriteReq accesses(hits+misses) 1206system.cpu.dcache.demand_accesses::cpu.data 21553796 # number of demand (read+write) accesses 1207system.cpu.dcache.demand_accesses::total 21553796 # number of demand (read+write) accesses 1208system.cpu.dcache.overall_accesses::cpu.data 21553796 # number of overall (read+write) accesses 1209system.cpu.dcache.overall_accesses::total 21553796 # number of overall (read+write) accesses 1210system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170342 # miss rate for ReadReq accesses 1211system.cpu.dcache.ReadReq_miss_rate::total 0.170342 # miss rate for ReadReq accesses 1212system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037567 # miss rate for WriteReq accesses 1213system.cpu.dcache.WriteReq_miss_rate::total 0.037567 # miss rate for WriteReq accesses 1214system.cpu.dcache.demand_miss_rate::cpu.data 0.118475 # miss rate for demand accesses 1215system.cpu.dcache.demand_miss_rate::total 0.118475 # miss rate for demand accesses 1216system.cpu.dcache.overall_miss_rate::cpu.data 0.118475 # miss rate for overall accesses 1217system.cpu.dcache.overall_miss_rate::total 0.118475 # miss rate for overall accesses 1218system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307 # average ReadReq miss latency 1219system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307 # average ReadReq miss latency 1220system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695 # average WriteReq miss latency 1221system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695 # average WriteReq miss latency 1222system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency 1223system.cpu.dcache.demand_avg_miss_latency::total 17541.571069 # average overall miss latency 1224system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency 1225system.cpu.dcache.overall_avg_miss_latency::total 17541.571069 # average overall miss latency 1226system.cpu.dcache.blocked_cycles::no_mshrs 388234 # number of cycles access was blocked |
| 1193system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1227system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1194system.cpu.dcache.blocked::no_mshrs 42350 # number of cycles access was blocked | 1228system.cpu.dcache.blocked::no_mshrs 42159 # number of cycles access was blocked |
| 1195system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1229system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1196system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.175396 # average number of cycles each access was blocked | 1230system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.208805 # average number of cycles each access was blocked |
| 1197system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1198system.cpu.dcache.fast_writes 0 # number of fast writes performed 1199system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1231system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1232system.cpu.dcache.fast_writes 0 # number of fast writes performed 1233system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1200system.cpu.dcache.writebacks::writebacks 1561202 # number of writebacks 1201system.cpu.dcache.writebacks::total 1561202 # number of writebacks 1202system.cpu.dcache.ReadReq_mshr_hits::cpu.data 869210 # number of ReadReq MSHR hits 1203system.cpu.dcache.ReadReq_mshr_hits::total 869210 # number of ReadReq MSHR hits 1204system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24502 # number of WriteReq MSHR hits 1205system.cpu.dcache.WriteReq_mshr_hits::total 24502 # number of WriteReq MSHR hits 1206system.cpu.dcache.demand_mshr_hits::cpu.data 893712 # number of demand (read+write) MSHR hits 1207system.cpu.dcache.demand_mshr_hits::total 893712 # number of demand (read+write) MSHR hits 1208system.cpu.dcache.overall_mshr_hits::cpu.data 893712 # number of overall MSHR hits 1209system.cpu.dcache.overall_mshr_hits::total 893712 # number of overall MSHR hits 1210system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1370558 # number of ReadReq MSHR misses 1211system.cpu.dcache.ReadReq_mshr_misses::total 1370558 # number of ReadReq MSHR misses 1212system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292025 # number of WriteReq MSHR misses 1213system.cpu.dcache.WriteReq_mshr_misses::total 292025 # number of WriteReq MSHR misses 1214system.cpu.dcache.demand_mshr_misses::cpu.data 1662583 # number of demand (read+write) MSHR misses 1215system.cpu.dcache.demand_mshr_misses::total 1662583 # number of demand (read+write) MSHR misses 1216system.cpu.dcache.overall_mshr_misses::cpu.data 1662583 # number of overall MSHR misses 1217system.cpu.dcache.overall_mshr_misses::total 1662583 # number of overall MSHR misses 1218system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17741695710 # number of ReadReq MSHR miss cycles 1219system.cpu.dcache.ReadReq_mshr_miss_latency::total 17741695710 # number of ReadReq MSHR miss cycles 1220system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11080104948 # number of WriteReq MSHR miss cycles 1221system.cpu.dcache.WriteReq_mshr_miss_latency::total 11080104948 # number of WriteReq MSHR miss cycles 1222system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28821800658 # number of demand (read+write) MSHR miss cycles 1223system.cpu.dcache.demand_mshr_miss_latency::total 28821800658 # number of demand (read+write) MSHR miss cycles 1224system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28821800658 # number of overall MSHR miss cycles 1225system.cpu.dcache.overall_mshr_miss_latency::total 28821800658 # number of overall MSHR miss cycles 1226system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363380000 # number of ReadReq MSHR uncacheable cycles 1227system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363380000 # number of ReadReq MSHR uncacheable cycles 1228system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536381000 # number of WriteReq MSHR uncacheable cycles 1229system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536381000 # number of WriteReq MSHR uncacheable cycles 1230system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899761000 # number of overall MSHR uncacheable cycles 1231system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899761000 # number of overall MSHR uncacheable cycles 1232system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104387 # mshr miss rate for ReadReq accesses 1233system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104387 # mshr miss rate for ReadReq accesses 1234system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034696 # mshr miss rate for WriteReq accesses 1235system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034696 # mshr miss rate for WriteReq accesses 1236system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077163 # mshr miss rate for demand accesses 1237system.cpu.dcache.demand_mshr_miss_rate::total 0.077163 # mshr miss rate for demand accesses 1238system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077163 # mshr miss rate for overall accesses 1239system.cpu.dcache.overall_mshr_miss_rate::total 0.077163 # mshr miss rate for overall accesses 1240system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12944.870418 # average ReadReq mshr miss latency 1241system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12944.870418 # average ReadReq mshr miss latency 1242system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.316404 # average WriteReq mshr miss latency 1243system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.316404 # average WriteReq mshr miss latency 1244system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17335.555974 # average overall mshr miss latency 1245system.cpu.dcache.demand_avg_mshr_miss_latency::total 17335.555974 # average overall mshr miss latency 1246system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17335.555974 # average overall mshr miss latency 1247system.cpu.dcache.overall_avg_mshr_miss_latency::total 17335.555974 # average overall mshr miss latency | 1234system.cpu.dcache.writebacks::writebacks 1559977 # number of writebacks 1235system.cpu.dcache.writebacks::total 1559977 # number of writebacks 1236system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867558 # number of ReadReq MSHR hits 1237system.cpu.dcache.ReadReq_mshr_hits::total 867558 # number of ReadReq MSHR hits 1238system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24476 # number of WriteReq MSHR hits 1239system.cpu.dcache.WriteReq_mshr_hits::total 24476 # number of WriteReq MSHR hits 1240system.cpu.dcache.demand_mshr_hits::cpu.data 892034 # number of demand (read+write) MSHR hits 1241system.cpu.dcache.demand_mshr_hits::total 892034 # number of demand (read+write) MSHR hits 1242system.cpu.dcache.overall_mshr_hits::cpu.data 892034 # number of overall MSHR hits 1243system.cpu.dcache.overall_mshr_hits::total 892034 # number of overall MSHR hits 1244system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369712 # number of ReadReq MSHR misses 1245system.cpu.dcache.ReadReq_mshr_misses::total 1369712 # number of ReadReq MSHR misses 1246system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291833 # number of WriteReq MSHR misses 1247system.cpu.dcache.WriteReq_mshr_misses::total 291833 # number of WriteReq MSHR misses 1248system.cpu.dcache.demand_mshr_misses::cpu.data 1661545 # number of demand (read+write) MSHR misses 1249system.cpu.dcache.demand_mshr_misses::total 1661545 # number of demand (read+write) MSHR misses 1250system.cpu.dcache.overall_mshr_misses::cpu.data 1661545 # number of overall MSHR misses 1251system.cpu.dcache.overall_mshr_misses::total 1661545 # number of overall MSHR misses 1252system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17680675970 # number of ReadReq MSHR miss cycles 1253system.cpu.dcache.ReadReq_mshr_miss_latency::total 17680675970 # number of ReadReq MSHR miss cycles 1254system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11138475501 # number of WriteReq MSHR miss cycles 1255system.cpu.dcache.WriteReq_mshr_miss_latency::total 11138475501 # number of WriteReq MSHR miss cycles 1256system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28819151471 # number of demand (read+write) MSHR miss cycles 1257system.cpu.dcache.demand_mshr_miss_latency::total 28819151471 # number of demand (read+write) MSHR miss cycles 1258system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28819151471 # number of overall MSHR miss cycles 1259system.cpu.dcache.overall_mshr_miss_latency::total 28819151471 # number of overall MSHR miss cycles 1260system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364609500 # number of ReadReq MSHR uncacheable cycles 1261system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364609500 # number of ReadReq MSHR uncacheable cycles 1262system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539074000 # number of WriteReq MSHR uncacheable cycles 1263system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539074000 # number of WriteReq MSHR uncacheable cycles 1264system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903683500 # number of overall MSHR uncacheable cycles 1265system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903683500 # number of overall MSHR uncacheable cycles 1266system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104287 # mshr miss rate for ReadReq accesses 1267system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104287 # mshr miss rate for ReadReq accesses 1268system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034660 # mshr miss rate for WriteReq accesses 1269system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034660 # mshr miss rate for WriteReq accesses 1270system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses 1271system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses 1272system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses 1273system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses 1274system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.316471 # average ReadReq mshr miss latency 1275system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471 # average ReadReq mshr miss latency 1276system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599 # average WriteReq mshr miss latency 1277system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599 # average WriteReq mshr miss latency 1278system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency 1279system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency 1280system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency 1281system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency |
| 1248system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1249system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1250system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1251system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1252system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1253system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1254system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1282system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1283system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1284system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1285system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1286system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1287system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1288system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1255system.cpu.l2cache.tags.replacements 111989 # number of replacements 1256system.cpu.l2cache.tags.tagsinuse 64821.159717 # Cycle average of tags in use 1257system.cpu.l2cache.tags.total_refs 3780351 # Total number of references to valid blocks. 1258system.cpu.l2cache.tags.sampled_refs 176044 # Sample count of references to valid blocks. 1259system.cpu.l2cache.tags.avg_refs 21.473899 # Average number of references to valid blocks. | 1289system.cpu.l2cache.tags.replacements 111887 # number of replacements 1290system.cpu.l2cache.tags.tagsinuse 64820.177016 # Cycle average of tags in use 1291system.cpu.l2cache.tags.total_refs 3787056 # Total number of references to valid blocks. 1292system.cpu.l2cache.tags.sampled_refs 176012 # Sample count of references to valid blocks. 1293system.cpu.l2cache.tags.avg_refs 21.515897 # Average number of references to valid blocks. |
| 1260system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1294system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1261system.cpu.l2cache.tags.occ_blocks::writebacks 50592.226872 # Average occupied blocks per requestor 1262system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.121398 # Average occupied blocks per requestor 1263system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.097025 # Average occupied blocks per requestor 1264system.cpu.l2cache.tags.occ_blocks::cpu.inst 2916.382816 # Average occupied blocks per requestor 1265system.cpu.l2cache.tags.occ_blocks::cpu.data 11302.331606 # Average occupied blocks per requestor 1266system.cpu.l2cache.tags.occ_percent::writebacks 0.771976 # Average percentage of cache occupancy 1267system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000154 # Average percentage of cache occupancy 1268system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy 1269system.cpu.l2cache.tags.occ_percent::cpu.inst 0.044500 # Average percentage of cache occupancy 1270system.cpu.l2cache.tags.occ_percent::cpu.data 0.172460 # Average percentage of cache occupancy 1271system.cpu.l2cache.tags.occ_percent::total 0.989092 # Average percentage of cache occupancy 1272system.cpu.l2cache.tags.occ_task_id_blocks::1024 64055 # Occupied blocks per task id 1273system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 1274system.cpu.l2cache.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id 1275system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3496 # Occupied blocks per task id 1276system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6269 # Occupied blocks per task id 1277system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53720 # Occupied blocks per task id 1278system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977402 # Percentage of cache occupancy per task id 1279system.cpu.l2cache.tags.tag_accesses 34623360 # Number of tag accesses 1280system.cpu.l2cache.tags.data_accesses 34623360 # Number of data accesses 1281system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64539 # number of ReadReq hits 1282system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7780 # number of ReadReq hits 1283system.cpu.l2cache.ReadReq_hits::cpu.inst 939362 # number of ReadReq hits 1284system.cpu.l2cache.ReadReq_hits::cpu.data 1333943 # number of ReadReq hits 1285system.cpu.l2cache.ReadReq_hits::total 2345624 # number of ReadReq hits 1286system.cpu.l2cache.Writeback_hits::writebacks 1579042 # number of Writeback hits 1287system.cpu.l2cache.Writeback_hits::total 1579042 # number of Writeback hits 1288system.cpu.l2cache.UpgradeReq_hits::cpu.data 315 # number of UpgradeReq hits 1289system.cpu.l2cache.UpgradeReq_hits::total 315 # number of UpgradeReq hits 1290system.cpu.l2cache.ReadExReq_hits::cpu.data 156902 # number of ReadExReq hits 1291system.cpu.l2cache.ReadExReq_hits::total 156902 # number of ReadExReq hits 1292system.cpu.l2cache.demand_hits::cpu.dtb.walker 64539 # number of demand (read+write) hits 1293system.cpu.l2cache.demand_hits::cpu.itb.walker 7780 # number of demand (read+write) hits 1294system.cpu.l2cache.demand_hits::cpu.inst 939362 # number of demand (read+write) hits 1295system.cpu.l2cache.demand_hits::cpu.data 1490845 # number of demand (read+write) hits 1296system.cpu.l2cache.demand_hits::total 2502526 # number of demand (read+write) hits 1297system.cpu.l2cache.overall_hits::cpu.dtb.walker 64539 # number of overall hits 1298system.cpu.l2cache.overall_hits::cpu.itb.walker 7780 # number of overall hits 1299system.cpu.l2cache.overall_hits::cpu.inst 939362 # number of overall hits 1300system.cpu.l2cache.overall_hits::cpu.data 1490845 # number of overall hits 1301system.cpu.l2cache.overall_hits::total 2502526 # number of overall hits 1302system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses 1303system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4 # number of ReadReq misses 1304system.cpu.l2cache.ReadReq_misses::cpu.inst 16168 # number of ReadReq misses 1305system.cpu.l2cache.ReadReq_misses::cpu.data 35908 # number of ReadReq misses 1306system.cpu.l2cache.ReadReq_misses::total 52129 # number of ReadReq misses 1307system.cpu.l2cache.UpgradeReq_misses::cpu.data 1443 # number of UpgradeReq misses 1308system.cpu.l2cache.UpgradeReq_misses::total 1443 # number of UpgradeReq misses 1309system.cpu.l2cache.ReadExReq_misses::cpu.data 133016 # number of ReadExReq misses 1310system.cpu.l2cache.ReadExReq_misses::total 133016 # number of ReadExReq misses 1311system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses 1312system.cpu.l2cache.demand_misses::cpu.itb.walker 4 # number of demand (read+write) misses 1313system.cpu.l2cache.demand_misses::cpu.inst 16168 # number of demand (read+write) misses 1314system.cpu.l2cache.demand_misses::cpu.data 168924 # number of demand (read+write) misses 1315system.cpu.l2cache.demand_misses::total 185145 # number of demand (read+write) misses 1316system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses 1317system.cpu.l2cache.overall_misses::cpu.itb.walker 4 # number of overall misses 1318system.cpu.l2cache.overall_misses::cpu.inst 16168 # number of overall misses 1319system.cpu.l2cache.overall_misses::cpu.data 168924 # number of overall misses 1320system.cpu.l2cache.overall_misses::total 185145 # number of overall misses 1321system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4159750 # number of ReadReq miss cycles 1322system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 369250 # number of ReadReq miss cycles 1323system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1243133741 # number of ReadReq miss cycles 1324system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2836550442 # number of ReadReq miss cycles 1325system.cpu.l2cache.ReadReq_miss_latency::total 4084213183 # number of ReadReq miss cycles 1326system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17687795 # number of UpgradeReq miss cycles 1327system.cpu.l2cache.UpgradeReq_miss_latency::total 17687795 # number of UpgradeReq miss cycles 1328system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9175416141 # number of ReadExReq miss cycles 1329system.cpu.l2cache.ReadExReq_miss_latency::total 9175416141 # number of ReadExReq miss cycles 1330system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4159750 # number of demand (read+write) miss cycles 1331system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 369250 # number of demand (read+write) miss cycles 1332system.cpu.l2cache.demand_miss_latency::cpu.inst 1243133741 # number of demand (read+write) miss cycles 1333system.cpu.l2cache.demand_miss_latency::cpu.data 12011966583 # number of demand (read+write) miss cycles 1334system.cpu.l2cache.demand_miss_latency::total 13259629324 # number of demand (read+write) miss cycles 1335system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4159750 # number of overall miss cycles 1336system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 369250 # number of overall miss cycles 1337system.cpu.l2cache.overall_miss_latency::cpu.inst 1243133741 # number of overall miss cycles 1338system.cpu.l2cache.overall_miss_latency::cpu.data 12011966583 # number of overall miss cycles 1339system.cpu.l2cache.overall_miss_latency::total 13259629324 # number of overall miss cycles 1340system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64588 # number of ReadReq accesses(hits+misses) 1341system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7784 # number of ReadReq accesses(hits+misses) 1342system.cpu.l2cache.ReadReq_accesses::cpu.inst 955530 # number of ReadReq accesses(hits+misses) 1343system.cpu.l2cache.ReadReq_accesses::cpu.data 1369851 # number of ReadReq accesses(hits+misses) 1344system.cpu.l2cache.ReadReq_accesses::total 2397753 # number of ReadReq accesses(hits+misses) 1345system.cpu.l2cache.Writeback_accesses::writebacks 1579042 # number of Writeback accesses(hits+misses) 1346system.cpu.l2cache.Writeback_accesses::total 1579042 # number of Writeback accesses(hits+misses) 1347system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1758 # number of UpgradeReq accesses(hits+misses) 1348system.cpu.l2cache.UpgradeReq_accesses::total 1758 # number of UpgradeReq accesses(hits+misses) 1349system.cpu.l2cache.ReadExReq_accesses::cpu.data 289918 # number of ReadExReq accesses(hits+misses) 1350system.cpu.l2cache.ReadExReq_accesses::total 289918 # number of ReadExReq accesses(hits+misses) 1351system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64588 # number of demand (read+write) accesses 1352system.cpu.l2cache.demand_accesses::cpu.itb.walker 7784 # number of demand (read+write) accesses 1353system.cpu.l2cache.demand_accesses::cpu.inst 955530 # number of demand (read+write) accesses 1354system.cpu.l2cache.demand_accesses::cpu.data 1659769 # number of demand (read+write) accesses 1355system.cpu.l2cache.demand_accesses::total 2687671 # number of demand (read+write) accesses 1356system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64588 # number of overall (read+write) accesses 1357system.cpu.l2cache.overall_accesses::cpu.itb.walker 7784 # number of overall (read+write) accesses 1358system.cpu.l2cache.overall_accesses::cpu.inst 955530 # number of overall (read+write) accesses 1359system.cpu.l2cache.overall_accesses::cpu.data 1659769 # number of overall (read+write) accesses 1360system.cpu.l2cache.overall_accesses::total 2687671 # number of overall (read+write) accesses 1361system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000759 # miss rate for ReadReq accesses 1362system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000514 # miss rate for ReadReq accesses 1363system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016920 # miss rate for ReadReq accesses 1364system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026213 # miss rate for ReadReq accesses 1365system.cpu.l2cache.ReadReq_miss_rate::total 0.021741 # miss rate for ReadReq accesses 1366system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820819 # miss rate for UpgradeReq accesses 1367system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820819 # miss rate for UpgradeReq accesses 1368system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.458806 # miss rate for ReadExReq accesses 1369system.cpu.l2cache.ReadExReq_miss_rate::total 0.458806 # miss rate for ReadExReq accesses 1370system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000759 # miss rate for demand accesses 1371system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000514 # miss rate for demand accesses 1372system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016920 # miss rate for demand accesses 1373system.cpu.l2cache.demand_miss_rate::cpu.data 0.101776 # miss rate for demand accesses 1374system.cpu.l2cache.demand_miss_rate::total 0.068887 # miss rate for demand accesses 1375system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000759 # miss rate for overall accesses 1376system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000514 # miss rate for overall accesses 1377system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016920 # miss rate for overall accesses 1378system.cpu.l2cache.overall_miss_rate::cpu.data 0.101776 # miss rate for overall accesses 1379system.cpu.l2cache.overall_miss_rate::total 0.068887 # miss rate for overall accesses 1380system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84892.857143 # average ReadReq miss latency 1381system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 92312.500000 # average ReadReq miss latency 1382system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76888.529255 # average ReadReq miss latency 1383system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78994.943801 # average ReadReq miss latency 1384system.cpu.l2cache.ReadReq_avg_miss_latency::total 78348.197414 # average ReadReq miss latency 1385system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12257.654193 # average UpgradeReq miss latency 1386system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12257.654193 # average UpgradeReq miss latency 1387system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68979.792965 # average ReadExReq miss latency 1388system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68979.792965 # average ReadExReq miss latency 1389system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84892.857143 # average overall miss latency 1390system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 92312.500000 # average overall miss latency 1391system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76888.529255 # average overall miss latency 1392system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71108.703222 # average overall miss latency 1393system.cpu.l2cache.demand_avg_miss_latency::total 71617.539356 # average overall miss latency 1394system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84892.857143 # average overall miss latency 1395system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 92312.500000 # average overall miss latency 1396system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76888.529255 # average overall miss latency 1397system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71108.703222 # average overall miss latency 1398system.cpu.l2cache.overall_avg_miss_latency::total 71617.539356 # average overall miss latency | 1295system.cpu.l2cache.tags.occ_blocks::writebacks 50551.329322 # Average occupied blocks per requestor 1296system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.553377 # Average occupied blocks per requestor 1297system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.127382 # Average occupied blocks per requestor 1298system.cpu.l2cache.tags.occ_blocks::cpu.inst 2956.401453 # Average occupied blocks per requestor 1299system.cpu.l2cache.tags.occ_blocks::cpu.data 11298.765482 # Average occupied blocks per requestor 1300system.cpu.l2cache.tags.occ_percent::writebacks 0.771352 # Average percentage of cache occupancy 1301system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000207 # Average percentage of cache occupancy 1302system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1303system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045111 # Average percentage of cache occupancy 1304system.cpu.l2cache.tags.occ_percent::cpu.data 0.172405 # Average percentage of cache occupancy 1305system.cpu.l2cache.tags.occ_percent::total 0.989077 # Average percentage of cache occupancy 1306system.cpu.l2cache.tags.occ_task_id_blocks::1024 64125 # Occupied blocks per task id 1307system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 1308system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id 1309system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3391 # Occupied blocks per task id 1310system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5259 # Occupied blocks per task id 1311system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54885 # Occupied blocks per task id 1312system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978470 # Percentage of cache occupancy per task id 1313system.cpu.l2cache.tags.tag_accesses 34647865 # Number of tag accesses 1314system.cpu.l2cache.tags.data_accesses 34647865 # Number of data accesses 1315system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64838 # number of ReadReq hits 1316system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7507 # number of ReadReq hits 1317system.cpu.l2cache.ReadReq_hits::cpu.inst 937874 # number of ReadReq hits 1318system.cpu.l2cache.ReadReq_hits::cpu.data 1332851 # number of ReadReq hits 1319system.cpu.l2cache.ReadReq_hits::total 2343070 # number of ReadReq hits 1320system.cpu.l2cache.Writeback_hits::writebacks 1584798 # number of Writeback hits 1321system.cpu.l2cache.Writeback_hits::total 1584798 # number of Writeback hits 1322system.cpu.l2cache.UpgradeReq_hits::cpu.data 327 # number of UpgradeReq hits 1323system.cpu.l2cache.UpgradeReq_hits::total 327 # number of UpgradeReq hits 1324system.cpu.l2cache.ReadExReq_hits::cpu.data 156813 # number of ReadExReq hits 1325system.cpu.l2cache.ReadExReq_hits::total 156813 # number of ReadExReq hits 1326system.cpu.l2cache.demand_hits::cpu.dtb.walker 64838 # number of demand (read+write) hits 1327system.cpu.l2cache.demand_hits::cpu.itb.walker 7507 # number of demand (read+write) hits 1328system.cpu.l2cache.demand_hits::cpu.inst 937874 # number of demand (read+write) hits 1329system.cpu.l2cache.demand_hits::cpu.data 1489664 # number of demand (read+write) hits 1330system.cpu.l2cache.demand_hits::total 2499883 # number of demand (read+write) hits 1331system.cpu.l2cache.overall_hits::cpu.dtb.walker 64838 # number of overall hits 1332system.cpu.l2cache.overall_hits::cpu.itb.walker 7507 # number of overall hits 1333system.cpu.l2cache.overall_hits::cpu.inst 937874 # number of overall hits 1334system.cpu.l2cache.overall_hits::cpu.data 1489664 # number of overall hits 1335system.cpu.l2cache.overall_hits::total 2499883 # number of overall hits 1336system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 60 # number of ReadReq misses 1337system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 1338system.cpu.l2cache.ReadReq_misses::cpu.inst 16175 # number of ReadReq misses 1339system.cpu.l2cache.ReadReq_misses::cpu.data 36023 # number of ReadReq misses 1340system.cpu.l2cache.ReadReq_misses::total 52263 # number of ReadReq misses 1341system.cpu.l2cache.UpgradeReq_misses::cpu.data 1437 # number of UpgradeReq misses 1342system.cpu.l2cache.UpgradeReq_misses::total 1437 # number of UpgradeReq misses 1343system.cpu.l2cache.ReadExReq_misses::cpu.data 132861 # number of ReadExReq misses 1344system.cpu.l2cache.ReadExReq_misses::total 132861 # number of ReadExReq misses 1345system.cpu.l2cache.demand_misses::cpu.dtb.walker 60 # number of demand (read+write) misses 1346system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 1347system.cpu.l2cache.demand_misses::cpu.inst 16175 # number of demand (read+write) misses 1348system.cpu.l2cache.demand_misses::cpu.data 168884 # number of demand (read+write) misses 1349system.cpu.l2cache.demand_misses::total 185124 # number of demand (read+write) misses 1350system.cpu.l2cache.overall_misses::cpu.dtb.walker 60 # number of overall misses 1351system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 1352system.cpu.l2cache.overall_misses::cpu.inst 16175 # number of overall misses 1353system.cpu.l2cache.overall_misses::cpu.data 168884 # number of overall misses 1354system.cpu.l2cache.overall_misses::total 185124 # number of overall misses 1355system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5066750 # number of ReadReq miss cycles 1356system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 378250 # number of ReadReq miss cycles 1357system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1233234983 # number of ReadReq miss cycles 1358system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2788798959 # number of ReadReq miss cycles 1359system.cpu.l2cache.ReadReq_miss_latency::total 4027478942 # number of ReadReq miss cycles 1360system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17149821 # number of UpgradeReq miss cycles 1361system.cpu.l2cache.UpgradeReq_miss_latency::total 17149821 # number of UpgradeReq miss cycles 1362system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9234678927 # number of ReadExReq miss cycles 1363system.cpu.l2cache.ReadExReq_miss_latency::total 9234678927 # number of ReadExReq miss cycles 1364system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5066750 # number of demand (read+write) miss cycles 1365system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 378250 # number of demand (read+write) miss cycles 1366system.cpu.l2cache.demand_miss_latency::cpu.inst 1233234983 # number of demand (read+write) miss cycles 1367system.cpu.l2cache.demand_miss_latency::cpu.data 12023477886 # number of demand (read+write) miss cycles 1368system.cpu.l2cache.demand_miss_latency::total 13262157869 # number of demand (read+write) miss cycles 1369system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5066750 # number of overall miss cycles 1370system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 378250 # number of overall miss cycles 1371system.cpu.l2cache.overall_miss_latency::cpu.inst 1233234983 # number of overall miss cycles 1372system.cpu.l2cache.overall_miss_latency::cpu.data 12023477886 # number of overall miss cycles 1373system.cpu.l2cache.overall_miss_latency::total 13262157869 # number of overall miss cycles 1374system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64898 # number of ReadReq accesses(hits+misses) 1375system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7512 # number of ReadReq accesses(hits+misses) 1376system.cpu.l2cache.ReadReq_accesses::cpu.inst 954049 # number of ReadReq accesses(hits+misses) 1377system.cpu.l2cache.ReadReq_accesses::cpu.data 1368874 # number of ReadReq accesses(hits+misses) 1378system.cpu.l2cache.ReadReq_accesses::total 2395333 # number of ReadReq accesses(hits+misses) 1379system.cpu.l2cache.Writeback_accesses::writebacks 1584798 # number of Writeback accesses(hits+misses) 1380system.cpu.l2cache.Writeback_accesses::total 1584798 # number of Writeback accesses(hits+misses) 1381system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1764 # number of UpgradeReq accesses(hits+misses) 1382system.cpu.l2cache.UpgradeReq_accesses::total 1764 # number of UpgradeReq accesses(hits+misses) 1383system.cpu.l2cache.ReadExReq_accesses::cpu.data 289674 # number of ReadExReq accesses(hits+misses) 1384system.cpu.l2cache.ReadExReq_accesses::total 289674 # number of ReadExReq accesses(hits+misses) 1385system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64898 # number of demand (read+write) accesses 1386system.cpu.l2cache.demand_accesses::cpu.itb.walker 7512 # number of demand (read+write) accesses 1387system.cpu.l2cache.demand_accesses::cpu.inst 954049 # number of demand (read+write) accesses 1388system.cpu.l2cache.demand_accesses::cpu.data 1658548 # number of demand (read+write) accesses 1389system.cpu.l2cache.demand_accesses::total 2685007 # number of demand (read+write) accesses 1390system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64898 # number of overall (read+write) accesses 1391system.cpu.l2cache.overall_accesses::cpu.itb.walker 7512 # number of overall (read+write) accesses 1392system.cpu.l2cache.overall_accesses::cpu.inst 954049 # number of overall (read+write) accesses 1393system.cpu.l2cache.overall_accesses::cpu.data 1658548 # number of overall (read+write) accesses 1394system.cpu.l2cache.overall_accesses::total 2685007 # number of overall (read+write) accesses 1395system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000925 # miss rate for ReadReq accesses 1396system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000666 # miss rate for ReadReq accesses 1397system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016954 # miss rate for ReadReq accesses 1398system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026316 # miss rate for ReadReq accesses 1399system.cpu.l2cache.ReadReq_miss_rate::total 0.021819 # miss rate for ReadReq accesses 1400system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814626 # miss rate for UpgradeReq accesses 1401system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814626 # miss rate for UpgradeReq accesses 1402system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.458657 # miss rate for ReadExReq accesses 1403system.cpu.l2cache.ReadExReq_miss_rate::total 0.458657 # miss rate for ReadExReq accesses 1404system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000925 # miss rate for demand accesses 1405system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000666 # miss rate for demand accesses 1406system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016954 # miss rate for demand accesses 1407system.cpu.l2cache.demand_miss_rate::cpu.data 0.101826 # miss rate for demand accesses 1408system.cpu.l2cache.demand_miss_rate::total 0.068947 # miss rate for demand accesses 1409system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000925 # miss rate for overall accesses 1410system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000666 # miss rate for overall accesses 1411system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016954 # miss rate for overall accesses 1412system.cpu.l2cache.overall_miss_rate::cpu.data 0.101826 # miss rate for overall accesses 1413system.cpu.l2cache.overall_miss_rate::total 0.068947 # miss rate for overall accesses 1414system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84445.833333 # average ReadReq miss latency 1415system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75650 # average ReadReq miss latency 1416system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76243.275611 # average ReadReq miss latency 1417system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77417.176776 # average ReadReq miss latency 1418system.cpu.l2cache.ReadReq_avg_miss_latency::total 77061.763427 # average ReadReq miss latency 1419system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11934.461378 # average UpgradeReq miss latency 1420system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11934.461378 # average UpgradeReq miss latency 1421system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69506.318084 # average ReadExReq miss latency 1422system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69506.318084 # average ReadExReq miss latency 1423system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84445.833333 # average overall miss latency 1424system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75650 # average overall miss latency 1425system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76243.275611 # average overall miss latency 1426system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71193.706248 # average overall miss latency 1427system.cpu.l2cache.demand_avg_miss_latency::total 71639.322125 # average overall miss latency 1428system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84445.833333 # average overall miss latency 1429system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75650 # average overall miss latency 1430system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76243.275611 # average overall miss latency 1431system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71193.706248 # average overall miss latency 1432system.cpu.l2cache.overall_avg_miss_latency::total 71639.322125 # average overall miss latency |
| 1399system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1400system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1401system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1402system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1403system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1404system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1405system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1406system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1433system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1434system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1435system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1436system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1437system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1438system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1439system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1440system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1407system.cpu.l2cache.writebacks::writebacks 102223 # number of writebacks 1408system.cpu.l2cache.writebacks::total 102223 # number of writebacks | 1441system.cpu.l2cache.writebacks::writebacks 102104 # number of writebacks 1442system.cpu.l2cache.writebacks::total 102104 # number of writebacks |
| 1409system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1410system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits 1411system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 1412system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1413system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits 1414system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 1415system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1416system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits 1417system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits | 1443system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1444system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits 1445system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 1446system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1447system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits 1448system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 1449system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1450system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits 1451system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits |
| 1418system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses 1419system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4 # number of ReadReq MSHR misses 1420system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16166 # number of ReadReq MSHR misses 1421system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35906 # number of ReadReq MSHR misses 1422system.cpu.l2cache.ReadReq_mshr_misses::total 52125 # number of ReadReq MSHR misses 1423system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1443 # number of UpgradeReq MSHR misses 1424system.cpu.l2cache.UpgradeReq_mshr_misses::total 1443 # number of UpgradeReq MSHR misses 1425system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133016 # number of ReadExReq MSHR misses 1426system.cpu.l2cache.ReadExReq_mshr_misses::total 133016 # number of ReadExReq MSHR misses 1427system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses 1428system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4 # number of demand (read+write) MSHR misses 1429system.cpu.l2cache.demand_mshr_misses::cpu.inst 16166 # number of demand (read+write) MSHR misses 1430system.cpu.l2cache.demand_mshr_misses::cpu.data 168922 # number of demand (read+write) MSHR misses 1431system.cpu.l2cache.demand_mshr_misses::total 185141 # number of demand (read+write) MSHR misses 1432system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses 1433system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4 # number of overall MSHR misses 1434system.cpu.l2cache.overall_mshr_misses::cpu.inst 16166 # number of overall MSHR misses 1435system.cpu.l2cache.overall_mshr_misses::cpu.data 168922 # number of overall MSHR misses 1436system.cpu.l2cache.overall_mshr_misses::total 185141 # number of overall MSHR misses 1437system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3552250 # number of ReadReq MSHR miss cycles 1438system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 319250 # number of ReadReq MSHR miss cycles 1439system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1040184259 # number of ReadReq MSHR miss cycles 1440system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2389977554 # number of ReadReq MSHR miss cycles 1441system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3434033313 # number of ReadReq MSHR miss cycles 1442system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15330925 # number of UpgradeReq MSHR miss cycles 1443system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15330925 # number of UpgradeReq MSHR miss cycles 1444system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7506177359 # number of ReadExReq MSHR miss cycles 1445system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7506177359 # number of ReadExReq MSHR miss cycles 1446system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3552250 # number of demand (read+write) MSHR miss cycles 1447system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 319250 # number of demand (read+write) MSHR miss cycles 1448system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1040184259 # number of demand (read+write) MSHR miss cycles 1449system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9896154913 # number of demand (read+write) MSHR miss cycles 1450system.cpu.l2cache.demand_mshr_miss_latency::total 10940210672 # number of demand (read+write) MSHR miss cycles 1451system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3552250 # number of overall MSHR miss cycles 1452system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 319250 # number of overall MSHR miss cycles 1453system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1040184259 # number of overall MSHR miss cycles 1454system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9896154913 # number of overall MSHR miss cycles 1455system.cpu.l2cache.overall_mshr_miss_latency::total 10940210672 # number of overall MSHR miss cycles 1456system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250256000 # number of ReadReq MSHR uncacheable cycles 1457system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250256000 # number of ReadReq MSHR uncacheable cycles 1458system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370696500 # number of WriteReq MSHR uncacheable cycles 1459system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370696500 # number of WriteReq MSHR uncacheable cycles 1460system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620952500 # number of overall MSHR uncacheable cycles 1461system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620952500 # number of overall MSHR uncacheable cycles 1462system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000759 # mshr miss rate for ReadReq accesses 1463system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000514 # mshr miss rate for ReadReq accesses 1464system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016918 # mshr miss rate for ReadReq accesses 1465system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026212 # mshr miss rate for ReadReq accesses 1466system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021739 # mshr miss rate for ReadReq accesses 1467system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820819 # mshr miss rate for UpgradeReq accesses 1468system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820819 # mshr miss rate for UpgradeReq accesses 1469system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.458806 # mshr miss rate for ReadExReq accesses 1470system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.458806 # mshr miss rate for ReadExReq accesses 1471system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000759 # mshr miss rate for demand accesses 1472system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000514 # mshr miss rate for demand accesses 1473system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016918 # mshr miss rate for demand accesses 1474system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101774 # mshr miss rate for demand accesses 1475system.cpu.l2cache.demand_mshr_miss_rate::total 0.068885 # mshr miss rate for demand accesses 1476system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000759 # mshr miss rate for overall accesses 1477system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000514 # mshr miss rate for overall accesses 1478system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016918 # mshr miss rate for overall accesses 1479system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101774 # mshr miss rate for overall accesses 1480system.cpu.l2cache.overall_mshr_miss_rate::total 0.068885 # mshr miss rate for overall accesses 1481system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959 # average ReadReq mshr miss latency 1482system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79812.500000 # average ReadReq mshr miss latency 1483system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64343.947730 # average ReadReq mshr miss latency 1484system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66562.066340 # average ReadReq mshr miss latency 1485system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65880.735022 # average ReadReq mshr miss latency 1486system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10624.341649 # average UpgradeReq mshr miss latency 1487system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10624.341649 # average UpgradeReq mshr miss latency 1488system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56430.635104 # average ReadExReq mshr miss latency 1489system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56430.635104 # average ReadExReq mshr miss latency 1490system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959 # average overall mshr miss latency 1491system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79812.500000 # average overall mshr miss latency 1492system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64343.947730 # average overall mshr miss latency 1493system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58584.168510 # average overall mshr miss latency 1494system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59091.236798 # average overall mshr miss latency 1495system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959 # average overall mshr miss latency 1496system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79812.500000 # average overall mshr miss latency 1497system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64343.947730 # average overall mshr miss latency 1498system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58584.168510 # average overall mshr miss latency 1499system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59091.236798 # average overall mshr miss latency | 1452system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 60 # number of ReadReq MSHR misses 1453system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 1454system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16173 # number of ReadReq MSHR misses 1455system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36021 # number of ReadReq MSHR misses 1456system.cpu.l2cache.ReadReq_mshr_misses::total 52259 # number of ReadReq MSHR misses 1457system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1437 # number of UpgradeReq MSHR misses 1458system.cpu.l2cache.UpgradeReq_mshr_misses::total 1437 # number of UpgradeReq MSHR misses 1459system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132861 # number of ReadExReq MSHR misses 1460system.cpu.l2cache.ReadExReq_mshr_misses::total 132861 # number of ReadExReq MSHR misses 1461system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 60 # number of demand (read+write) MSHR misses 1462system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 1463system.cpu.l2cache.demand_mshr_misses::cpu.inst 16173 # number of demand (read+write) MSHR misses 1464system.cpu.l2cache.demand_mshr_misses::cpu.data 168882 # number of demand (read+write) MSHR misses 1465system.cpu.l2cache.demand_mshr_misses::total 185120 # number of demand (read+write) MSHR misses 1466system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 60 # number of overall MSHR misses 1467system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 1468system.cpu.l2cache.overall_mshr_misses::cpu.inst 16173 # number of overall MSHR misses 1469system.cpu.l2cache.overall_mshr_misses::cpu.data 168882 # number of overall MSHR misses 1470system.cpu.l2cache.overall_mshr_misses::total 185120 # number of overall MSHR misses 1471system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4324750 # number of ReadReq MSHR miss cycles 1472system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 315250 # number of ReadReq MSHR miss cycles 1473system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1030094767 # number of ReadReq MSHR miss cycles 1474system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2339275539 # number of ReadReq MSHR miss cycles 1475system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3374010306 # number of ReadReq MSHR miss cycles 1476system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15289917 # number of UpgradeReq MSHR miss cycles 1477system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15289917 # number of UpgradeReq MSHR miss cycles 1478system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7567196573 # number of ReadExReq MSHR miss cycles 1479system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7567196573 # number of ReadExReq MSHR miss cycles 1480system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4324750 # number of demand (read+write) MSHR miss cycles 1481system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 315250 # number of demand (read+write) MSHR miss cycles 1482system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1030094767 # number of demand (read+write) MSHR miss cycles 1483system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9906472112 # number of demand (read+write) MSHR miss cycles 1484system.cpu.l2cache.demand_mshr_miss_latency::total 10941206879 # number of demand (read+write) MSHR miss cycles 1485system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4324750 # number of overall MSHR miss cycles 1486system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles 1487system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1030094767 # number of overall MSHR miss cycles 1488system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9906472112 # number of overall MSHR miss cycles 1489system.cpu.l2cache.overall_mshr_miss_latency::total 10941206879 # number of overall MSHR miss cycles 1490system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251381500 # number of ReadReq MSHR uncacheable cycles 1491system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251381500 # number of ReadReq MSHR uncacheable cycles 1492system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373144500 # number of WriteReq MSHR uncacheable cycles 1493system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373144500 # number of WriteReq MSHR uncacheable cycles 1494system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624526000 # number of overall MSHR uncacheable cycles 1495system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624526000 # number of overall MSHR uncacheable cycles 1496system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for ReadReq accesses 1497system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for ReadReq accesses 1498system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for ReadReq accesses 1499system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026314 # mshr miss rate for ReadReq accesses 1500system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021817 # mshr miss rate for ReadReq accesses 1501system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814626 # mshr miss rate for UpgradeReq accesses 1502system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814626 # mshr miss rate for UpgradeReq accesses 1503system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.458657 # mshr miss rate for ReadExReq accesses 1504system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.458657 # mshr miss rate for ReadExReq accesses 1505system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for demand accesses 1506system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for demand accesses 1507system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for demand accesses 1508system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for demand accesses 1509system.cpu.l2cache.demand_mshr_miss_rate::total 0.068946 # mshr miss rate for demand accesses 1510system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for overall accesses 1511system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for overall accesses 1512system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for overall accesses 1513system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for overall accesses 1514system.cpu.l2cache.overall_mshr_miss_rate::total 0.068946 # mshr miss rate for overall accesses 1515system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average ReadReq mshr miss latency 1516system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency 1517system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479 # average ReadReq mshr miss latency 1518system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254 # average ReadReq mshr miss latency 1519system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983 # average ReadReq mshr miss latency 1520system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927 # average UpgradeReq mshr miss latency 1521system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927 # average UpgradeReq mshr miss latency 1522system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006 # average ReadExReq mshr miss latency 1523system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006 # average ReadExReq mshr miss latency 1524system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency 1525system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency 1526system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency 1527system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency 1528system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency 1529system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency 1530system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency 1531system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency 1532system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency 1533system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency |
| 1500system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1501system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1502system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1503system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1504system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1505system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1506system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1507system.cpu.kern.inst.arm 0 # number of arm instructions executed 1508system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1509 1510---------- End Simulation Statistics ---------- | 1534system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1535system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1536system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1537system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1538system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1539system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1540system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1541system.cpu.kern.inst.arm 0 # number of arm instructions executed 1542system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1543 1544---------- End Simulation Statistics ---------- |