3,5c3,5
< sim_seconds 5.133932 # Number of seconds simulated
< sim_ticks 5133932129000 # Number of ticks simulated
< final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.133933 # Number of seconds simulated
> sim_ticks 5133933067000 # Number of ticks simulated
> final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,14c7,14
< host_inst_rate 157497 # Simulator instruction rate (inst/s)
< host_op_rate 311329 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1982921852 # Simulator tick rate (ticks/s)
< host_mem_usage 759792 # Number of bytes of host memory used
< host_seconds 2589.07 # Real time elapsed on the host
< sim_insts 407772261 # Number of instructions simulated
< sim_ops 806052921 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory
---
> host_inst_rate 121984 # Simulator instruction rate (inst/s)
> host_op_rate 241126 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1535878817 # Simulator tick rate (ticks/s)
> host_mem_usage 781700 # Number of bytes of host memory used
> host_seconds 3342.67 # Real time elapsed on the host
> sim_insts 407751929 # Number of instructions simulated
> sim_ops 806002693 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory
17,24c17,24
< system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory
< system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory
< system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::cpu.inst 1029376 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10746496 # Number of bytes read from this memory
> system.physmem.bytes_read::total 14217280 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1029376 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1029376 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9492672 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9492672 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 38081 # Number of read requests responded to by this memory
27,32c27,32
< system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory
< system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu.inst 16084 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 167914 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 222145 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 148323 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 148323 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 474721 # Total read bandwidth from this memory (bytes/s)
35,43c35,43
< system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 200504 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2093229 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2769276 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 200504 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 200504 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1849006 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1849006 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1849006 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 474721 # Total bandwidth to/from this memory (bytes/s)
46,58c46,58
< system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 222430 # Number of read requests accepted
< system.physmem.writeReqs 148587 # Number of write requests accepted
< system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::cpu.inst 200504 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2093229 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4618282 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 222145 # Number of read requests accepted
> system.physmem.writeReqs 148323 # Number of write requests accepted
> system.physmem.readBursts 222145 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 148323 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 14211648 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9492416 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 14217280 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 9492672 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue
60,79c60,79
< system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 14853 # Per bank write bursts
< system.physmem.perBankRdBursts::1 13635 # Per bank write bursts
< system.physmem.perBankRdBursts::2 14415 # Per bank write bursts
< system.physmem.perBankRdBursts::3 13770 # Per bank write bursts
< system.physmem.perBankRdBursts::4 14136 # Per bank write bursts
< system.physmem.perBankRdBursts::5 13341 # Per bank write bursts
< system.physmem.perBankRdBursts::6 13755 # Per bank write bursts
< system.physmem.perBankRdBursts::7 13953 # Per bank write bursts
< system.physmem.perBankRdBursts::8 13590 # Per bank write bursts
< system.physmem.perBankRdBursts::9 13369 # Per bank write bursts
< system.physmem.perBankRdBursts::10 13469 # Per bank write bursts
< system.physmem.perBankRdBursts::11 13962 # Per bank write bursts
< system.physmem.perBankRdBursts::12 14252 # Per bank write bursts
< system.physmem.perBankRdBursts::13 14454 # Per bank write bursts
< system.physmem.perBankRdBursts::14 13844 # Per bank write bursts
< system.physmem.perBankRdBursts::15 13571 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10225 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9089 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9605 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 1715 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 14970 # Per bank write bursts
> system.physmem.perBankRdBursts::1 13960 # Per bank write bursts
> system.physmem.perBankRdBursts::2 14769 # Per bank write bursts
> system.physmem.perBankRdBursts::3 13764 # Per bank write bursts
> system.physmem.perBankRdBursts::4 13644 # Per bank write bursts
> system.physmem.perBankRdBursts::5 13392 # Per bank write bursts
> system.physmem.perBankRdBursts::6 13407 # Per bank write bursts
> system.physmem.perBankRdBursts::7 13589 # Per bank write bursts
> system.physmem.perBankRdBursts::8 13408 # Per bank write bursts
> system.physmem.perBankRdBursts::9 13258 # Per bank write bursts
> system.physmem.perBankRdBursts::10 13821 # Per bank write bursts
> system.physmem.perBankRdBursts::11 13878 # Per bank write bursts
> system.physmem.perBankRdBursts::12 14332 # Per bank write bursts
> system.physmem.perBankRdBursts::13 14527 # Per bank write bursts
> system.physmem.perBankRdBursts::14 13749 # Per bank write bursts
> system.physmem.perBankRdBursts::15 13589 # Per bank write bursts
> system.physmem.perBankWrBursts::0 10370 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9405 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9871 # Per bank write bursts
81,92c81,92
< system.physmem.perBankWrBursts::4 9475 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8866 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9032 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9363 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8843 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8764 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9099 # Per bank write bursts
< system.physmem.perBankWrBursts::11 9352 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9596 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9639 # Per bank write bursts
< system.physmem.perBankWrBursts::14 9447 # Per bank write bursts
< system.physmem.perBankWrBursts::15 9010 # Per bank write bursts
---
> system.physmem.perBankWrBursts::4 9017 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8953 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8740 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8992 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8721 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8568 # Per bank write bursts
> system.physmem.perBankWrBursts::10 9309 # Per bank write bursts
> system.physmem.perBankWrBursts::11 9216 # Per bank write bursts
> system.physmem.perBankWrBursts::12 9686 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9800 # Per bank write bursts
> system.physmem.perBankWrBursts::14 9415 # Per bank write bursts
> system.physmem.perBankWrBursts::15 9091 # Per bank write bursts
94,95c94,95
< system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
< system.physmem.totGap 5133932076000 # Total gap between requests
---
> system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
> system.physmem.totGap 5133933013500 # Total gap between requests
102c102
< system.physmem.readPktSize::6 222430 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 222145 # Read request sizes (log2)
109,119c109,119
< system.physmem.writePktSize::6 148587 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 148323 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 174666 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 21456 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 6950 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 2913 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2112 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2066 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1506 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1430 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1072 # What read queue length does an incoming req see
121,127c121,127
< system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::11 755 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 678 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 656 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 606 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 583 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 571 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 555 # What read queue length does an incoming req see
129,132c129,132
< system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::19 523 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
142,243c142,243
< system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation
---
> system.physmem.wrQLenPdf::0 6022 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 6256 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 6299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 6341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 6448 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 6596 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 6608 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 6666 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 6998 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 7022 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 7020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 7083 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 7644 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 7121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 7236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 7399 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 7458 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6317 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6188 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6157 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 386 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 69 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 36 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 68754 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 344.735608 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 150.882581 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 1084.800437 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-67 30893 44.93% 44.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-131 10573 15.38% 60.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-195 6859 9.98% 70.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-259 4406 6.41% 76.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-323 2663 3.87% 80.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-387 2166 3.15% 83.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-451 1652 2.40% 86.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-515 1226 1.78% 87.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-579 1018 1.48% 89.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-643 978 1.42% 90.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-707 656 0.95% 91.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-771 637 0.93% 92.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-835 446 0.65% 93.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-899 438 0.64% 93.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-963 344 0.50% 94.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1027 542 0.79% 95.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1091 252 0.37% 95.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1155 218 0.32% 95.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1219 163 0.24% 96.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1283 136 0.20% 96.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1347 158 0.23% 96.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1411 420 0.61% 97.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1475 150 0.22% 97.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1539 127 0.18% 97.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1603 107 0.16% 97.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1667 87 0.13% 97.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1795 64 0.09% 98.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1859 17 0.02% 98.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1923 43 0.06% 98.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1987 19 0.03% 98.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2051 31 0.05% 98.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2179 40 0.06% 98.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2243 10 0.01% 98.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2371 16 0.02% 98.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2435 31 0.05% 98.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2499 10 0.01% 98.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2627 13 0.02% 98.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2691 31 0.05% 98.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2883 6 0.01% 98.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2947 27 0.04% 98.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3011 9 0.01% 98.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3075 12 0.02% 98.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3203 28 0.04% 98.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3331 7 0.01% 98.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3459 25 0.04% 98.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712-3715 26 0.04% 98.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3779 10 0.01% 98.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3843 5 0.01% 98.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3907 9 0.01% 98.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4099 15 0.02% 98.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4160-4163 3 0.00% 98.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4227 27 0.04% 98.94% # Bytes accessed per row activation
245,248c245,248
< system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480-4483 23 0.03% 98.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.98% # Bytes accessed per row activation
250,252c250,252
< system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::4672-4675 5 0.01% 98.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736-4739 25 0.04% 99.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4803 4 0.01% 99.04% # Bytes accessed per row activation
254,256c254,255
< system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::4992-4995 22 0.03% 99.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056-5059 2 0.00% 99.07% # Bytes accessed per row activation
258c257
< system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::5184-5187 4 0.01% 99.08% # Bytes accessed per row activation
261c260
< system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::5440-5443 2 0.00% 99.12% # Bytes accessed per row activation
263,325c262,327
< system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::5568-5571 4 0.01% 99.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5696-5699 3 0.00% 99.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5760-5763 24 0.03% 99.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5824-5827 4 0.01% 99.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016-6019 24 0.03% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208-6211 3 0.00% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6272-6275 24 0.03% 99.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6339 3 0.00% 99.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6400-6403 4 0.01% 99.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6528-6531 23 0.03% 99.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656-6659 75 0.11% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6723 3 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6784-6787 2 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6912-6915 5 0.01% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6976-6979 3 0.00% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7040-7043 9 0.01% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7104-7107 2 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7232-7235 2 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7488-7491 2 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7552-7555 2 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7680-7683 1 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7744-7747 2 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7808-7811 3 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7936-7939 3 0.00% 99.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8064-8067 5 0.01% 99.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8128-8131 3 0.00% 99.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8195 15 0.02% 99.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8512-8515 5 0.01% 99.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8640-8643 2 0.00% 99.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9152-9155 4 0.01% 99.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9536-9539 4 0.01% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9600-9603 4 0.01% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.65% # Bytes accessed per row activation
327,338c329,338
< system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11136-11139 1 0.00% 99.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11392-11395 3 0.00% 99.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11520-11523 3 0.00% 99.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.68% # Bytes accessed per row activation
340,370c340,368
< system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::12224-12227 2 0.00% 99.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12672-12675 3 0.00% 99.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13696-13699 3 0.00% 99.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13952-13955 5 0.01% 99.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14272-14275 4 0.01% 99.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14912-14915 25 0.04% 99.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14976-14979 6 0.01% 99.80% # Bytes accessed per row activation
372,391c370,389
< system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15168-15171 3 0.00% 99.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15232-15235 8 0.01% 99.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15296-15299 3 0.00% 99.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15808-15811 4 0.01% 99.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16064-16067 3 0.00% 99.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16128-16131 4 0.01% 99.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16192-16195 2 0.00% 99.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16256-16259 10 0.01% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.94% # Bytes accessed per row activation
393,399c391,397
< system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation
< system.physmem.totQLat 5163279754 # Total ticks spent queuing
< system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks
< system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst
---
> system.physmem.bytesPerActivate::total 68754 # Bytes accessed per row activation
> system.physmem.totQLat 5103462500 # Total ticks spent queuing
> system.physmem.totMemAccLat 9310522500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1110285000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 3096775000 # Total ticks spent accessing banks
> system.physmem.avgQLat 22982.67 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 13945.86 # Average bank access latency per DRAM burst
401c399
< system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 41928.53 # Average memory access latency per DRAM burst
411,417c409,415
< system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing
< system.physmem.readRowHits 193089 # Number of row buffer hits during reads
< system.physmem.writeRowHits 108689 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes
< system.physmem.avgGap 13837457.79 # Average gap between requests
< system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined
---
> system.physmem.avgWrQLen 8.57 # Average write queue length when enqueuing
> system.physmem.readRowHits 193293 # Number of row buffer hits during reads
> system.physmem.writeRowHits 108329 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes
> system.physmem.avgGap 13857966.18 # Average gap between requests
> system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
419,453c417,451
< system.membus.throughput 5101771 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 662370 # Transaction distribution
< system.membus.trans_dist::ReadResp 662362 # Transaction distribution
< system.membus.trans_dist::WriteReq 13778 # Transaction distribution
< system.membus.trans_dist::WriteResp 13778 # Transaction distribution
< system.membus.trans_dist::Writeback 148587 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution
< system.membus.trans_dist::ReadExReq 179504 # Transaction distribution
< system.membus.trans_dist::ReadExResp 179502 # Transaction distribution
< system.membus.trans_dist::MessageReq 1643 # Transaction distribution
< system.membus.trans_dist::MessageResp 1643 # Transaction distribution
< system.membus.trans_dist::BadAddressError 8 # Transaction distribution
< system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 25543633 # Total data (bytes)
< system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks)
---
> system.membus.throughput 5095991 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 662317 # Transaction distribution
> system.membus.trans_dist::ReadResp 662311 # Transaction distribution
> system.membus.trans_dist::WriteReq 13762 # Transaction distribution
> system.membus.trans_dist::WriteResp 13762 # Transaction distribution
> system.membus.trans_dist::Writeback 148323 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 2201 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1734 # Transaction distribution
> system.membus.trans_dist::ReadExReq 179351 # Transaction distribution
> system.membus.trans_dist::ReadExResp 179346 # Transaction distribution
> system.membus.trans_dist::MessageReq 1642 # Transaction distribution
> system.membus.trans_dist::MessageResp 1642 # Transaction distribution
> system.membus.trans_dist::BadAddressError 6 # Transaction distribution
> system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 474374 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720496 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132379 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 132379 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1856159 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18286080 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20078023 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5423872 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::total 5423872 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 25508463 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 25508463 # Total data (bytes)
> system.membus.snoop_data_through_bus 654016 # Total snoop data (bytes)
> system.membus.reqLayer0.occupancy 250556000 # Layer occupancy (ticks)
455c453
< system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 583258500 # Layer occupancy (ticks)
457c455
< system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks)
459c457
< system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1605908499 # Layer occupancy (ticks)
461c459
< system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
---
> system.membus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
463c461
< system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
465c463
< system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 3150989153 # Layer occupancy (ticks)
467c465
< system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks)
---
> system.membus.respLayer4.occupancy 429464748 # Layer occupancy (ticks)
470c468
< system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.103980 # Cycle average of tags in use
474,475c472,473
< system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 4992951939000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor
486,493c484,491
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151022435 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 151022435 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11480088301 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 11480088301 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 11631110736 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 11631110736 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 11631110736 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 11631110736 # number of overall miss cycles
510,518c508,516
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165776.547750 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 165776.547750 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245721.068086 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 245721.068086 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 244192.033256 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 244192.033256 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 172788 # number of cycles access was blocked
520c518
< system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 10383 # number of cycles access was blocked
522c520
< system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 16.641433 # average number of cycles each access was blocked
536,543c534,541
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 103624935 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 103624935 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9049102305 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 9049102305 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9152727240 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9152727240 # number of overall MSHR miss cycles
552,559c550,557
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113748.556531 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 113748.556531 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193687.977419 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 193687.977419 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency
563c561
< system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
---
> system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
573,579c571,577
< system.iobus.throughput 638153 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 225567 # Transaction distribution
< system.iobus.trans_dist::ReadResp 225567 # Transaction distribution
< system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
< system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
< system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
< system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
---
> system.iobus.throughput 638147 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 225559 # Transaction distribution
> system.iobus.trans_dist::ReadResp 225559 # Transaction distribution
> system.iobus.trans_dist::WriteReq 57591 # Transaction distribution
> system.iobus.trans_dist::WriteResp 57591 # Transaction distribution
> system.iobus.trans_dist::MessageReq 1642 # Transaction distribution
> system.iobus.trans_dist::MessageResp 1642 # Transaction distribution
582c580
< system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
598c596
< system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes)
601,603c599,601
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 569584 # Packet count per connected master and slave (bytes)
606c604
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
622c620
< system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes)
625,629c623,627
< system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 3276232 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size::total 3276202 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 3276202 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 3916600 # Layer occupancy (ticks)
635c633
< system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
665c663
< system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks)
---
> system.iobus.reqLayer18.occupancy 424364988 # Layer occupancy (ticks)
669c667
< system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks)
671c669
< system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 53080252 # Layer occupancy (ticks)
673c671
< system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
---
> system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks)
675,679c673,677
< system.cpu.branchPred.lookups 85592238 # Number of BP lookups
< system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits
---
> system.cpu.branchPred.lookups 85602749 # Number of BP lookups
> system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 79146839 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 77528417 # Number of BTB hits
681,684c679,682
< system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions.
< system.cpu.numCycles 453841851 # number of cpu cycles simulated
---
> system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions.
> system.cpu.numCycles 453810576 # number of cpu cycles simulated
687,703c685,701
< system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 25587128 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 422793434 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 85602749 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 78973010 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 162653475 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 3995125 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 108453 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.BlockedCycles 71359520 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 43835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 87857 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 8489508 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 384110 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 2391 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 262908725 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 3.175877 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.411274 # Number of instructions fetched each cycle (Total)
705,713c703,711
< system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 100670178 38.29% 38.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1530444 0.58% 38.87% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 71820335 27.32% 66.19% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 896426 0.34% 66.53% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 1566584 0.60% 67.13% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 2396730 0.91% 68.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 1019321 0.39% 68.43% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1330214 0.51% 68.93% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 81678493 31.07% 100.00% # Number of instructions fetched each cycle (Total)
717,759c715,757
< system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 262908725 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.188631 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.931652 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 29469022 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 68533895 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 158500921 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 3336716 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 3068171 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 832628882 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 3068171 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 32166033 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 43333689 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 12473461 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 158788115 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 13079256 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 829706187 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 21464 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 6056720 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 5143219 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 991368832 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1800529447 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1106981108 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 114 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 963921381 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 27447449 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 454679 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 459073 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 29562257 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 16738170 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 9831898 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1099509 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 931888 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 824922108 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1185282 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 820965230 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 150616 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 19266581 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 29327510 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 130776 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 262908725 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 3.122625 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 2.401229 # Number of insts issued each cycle
761,769c759,767
< system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 76541753 29.11% 29.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 15760378 5.99% 35.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 10546081 4.01% 39.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7369618 2.80% 41.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 75729447 28.80% 70.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 3748882 1.43% 72.15% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 72293205 27.50% 99.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 772480 0.29% 99.94% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 146881 0.06% 100.00% # Number of insts issued each cycle
773c771
< system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 262908725 # Number of insts issued each cycle
775,805c773,803
< system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 349560 33.18% 33.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 241 0.02% 33.20% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 1967 0.19% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 548780 52.08% 85.47% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 153094 14.53% 100.00% # attempts to use FU when none available
808,811c806,809
< system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 307236 0.04% 0.04% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 793474466 96.65% 96.69% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 149866 0.02% 96.71% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 124488 0.02% 96.72% # Type of FU issued
838,839c836,837
< system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 17682042 2.15% 98.88% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 9227132 1.12% 100.00% # Type of FU issued
842,854c840,852
< system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued
< system.cpu.iq.rate 1.808871 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 820965230 # Type of FU issued
> system.cpu.iq.rate 1.809048 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1053642 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.001283 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 1906151693 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 845384400 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 817050943 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 198 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 821711543 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1694469 # Number of loads that had data forwarded from stores
856,859c854,857
< system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 2748093 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 19141 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 11819 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1409863 # Number of stores squashed
862,863c860,861
< system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 1931395 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 11998 # Number of times an access to memory failed due to the cache being blocked
865,881c863,879
< system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 3068171 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 31463417 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 2151711 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 826107390 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 248376 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 16738170 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 9831898 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 690155 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 1620159 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 12279 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 11819 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 498534 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 508074 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1006608 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 819554351 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 17378079 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1410878 # Number of squashed instructions skipped in execute
884,891c882,889
< system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed
< system.cpu.iew.exec_branches 83090404 # Number of branches executed
< system.cpu.iew.exec_stores 9036920 # Number of stores executed
< system.cpu.iew.exec_rate 1.805776 # Inst execution rate
< system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 638560375 # num instructions producing a value
< system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 26421028 # number of memory reference insts executed
> system.cpu.iew.exec_branches 83090233 # Number of branches executed
> system.cpu.iew.exec_stores 9042949 # Number of stores executed
> system.cpu.iew.exec_rate 1.805939 # Inst execution rate
> system.cpu.iew.wb_sent 819150966 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 817050997 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 638575855 # num instructions producing a value
> system.cpu.iew.wb_consumers 1043882621 # num instructions consuming a value
893,894c891,892
< system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.800423 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.611731 # average fanout of values written-back
896,901c894,899
< system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 19994665 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1054506 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 892807 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 259840554 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 3.101913 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.863847 # Number of insts commited each cycle
903,911c901,909
< system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 88304488 33.98% 33.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 11858711 4.56% 38.55% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3833949 1.48% 40.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 74748511 28.77% 68.79% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 2384583 0.92% 69.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1475819 0.57% 70.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 859128 0.33% 70.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 70844564 27.26% 97.87% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 5530801 2.13% 100.00% # Number of insts commited each cycle
915,917c913,915
< system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 407772261 # Number of instructions committed
< system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 259840554 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 407751929 # Number of instructions committed
> system.cpu.commit.committedOps 806002693 # Number of ops (including micro ops) committed
919,922c917,920
< system.cpu.commit.refs 22412414 # Number of memory references committed
< system.cpu.commit.loads 13990896 # Number of loads committed
< system.cpu.commit.membars 474709 # Number of memory barriers committed
< system.cpu.commit.branches 82160310 # Number of branches committed
---
> system.cpu.commit.refs 22412111 # Number of memory references committed
> system.cpu.commit.loads 13990076 # Number of loads committed
> system.cpu.commit.membars 474663 # Number of memory barriers committed
> system.cpu.commit.branches 82157264 # Number of branches committed
924,926c922,924
< system.cpu.commit.int_insts 734896243 # Number of committed integer instructions.
< system.cpu.commit.function_calls 1155289 # Number of function calls committed.
< system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached
---
> system.cpu.commit.int_insts 734852381 # Number of committed integer instructions.
> system.cpu.commit.function_calls 1155163 # Number of function calls committed.
> system.cpu.commit.bw_lim_events 5530801 # number cycles where commit BW limit reached
928,970c926,968
< system.cpu.rob.rob_reads 1080212949 # The number of ROB reads
< system.cpu.rob.rob_writes 1654925831 # The number of ROB writes
< system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 407772261 # Number of Instructions Simulated
< system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated
< system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads
< system.cpu.int_regfile_writes 653799671 # number of integer regfile writes
< system.cpu.fp_regfile_reads 52 # number of floating regfile reads
< system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads
< system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes
< system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads
< system.cpu.misc_regfile_writes 402440 # number of misc regfile writes
< system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks)
---
> system.cpu.rob.rob_reads 1080228878 # The number of ROB reads
> system.cpu.rob.rob_writes 1655077473 # The number of ROB writes
> system.cpu.timesIdled 1260592 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 190901851 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 9814061063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 407751929 # Number of Instructions Simulated
> system.cpu.committedOps 806002693 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 407751929 # Number of Instructions Simulated
> system.cpu.cpi 1.112958 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.112958 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.898507 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.898507 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1088763208 # number of integer regfile reads
> system.cpu.int_regfile_writes 653821136 # number of integer regfile writes
> system.cpu.fp_regfile_reads 54 # number of floating regfile reads
> system.cpu.cc_regfile_reads 415622850 # number of cc regfile reads
> system.cpu.cc_regfile_writes 321492626 # number of cc regfile writes
> system.cpu.misc_regfile_reads 264082516 # number of misc regfile reads
> system.cpu.misc_regfile_writes 402300 # number of misc regfile writes
> system.cpu.toL2Bus.throughput 53661983 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 3016761 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3016231 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 13762 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 13762 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1581663 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2241 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2241 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 334732 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 288041 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916491 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123200 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19443 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154439 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8213573 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61324288 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207594695 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 616960 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5463872 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 274999815 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 274973191 # Total data (bytes)
> system.cpu.toL2Bus.snoop_data_through_bus 523840 # Total snoop data (bytes)
> system.cpu.toL2Bus.reqLayer0.occupancy 4039348922 # Layer occupancy (ticks)
972c970
< system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 624000 # Layer occupancy (ticks)
974c972
< system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1440815600 # Layer occupancy (ticks)
976c974
< system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3139539816 # Layer occupancy (ticks)
978c976
< system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 14707994 # Layer occupancy (ticks)
980c978
< system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 103656142 # Layer occupancy (ticks)
982,986c980,984
< system.cpu.icache.tags.replacements 959142 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 957724 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.254964 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 7477774 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 958236 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 7.803687 # Average number of references to valid blocks.
988,1027c986,1025
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits
< system.cpu.icache.overall_hits::total 7468451 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses
< system.cpu.icache.overall_misses::total 1013022 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.994639 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 7477774 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 7477774 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 7477774 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 7477774 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 7477774 # number of overall hits
> system.cpu.icache.overall_hits::total 7477774 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1011731 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1011731 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1011731 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1011731 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1011731 # number of overall misses
> system.cpu.icache.overall_misses::total 1011731 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14180716030 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14180716030 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14180716030 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14180716030 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14180716030 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14180716030 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 8489505 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 8489505 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 8489505 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 8489505 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 8489505 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 8489505 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119174 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.119174 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.119174 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.119174 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.119174 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.119174 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.290921 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14016.290921 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14016.290921 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14016.290921 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 5333 # number of cycles access was blocked
1029c1027
< system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked
1031c1029
< system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.827027 # average number of cycles each access was blocked
1035,1064c1033,1062
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53298 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 53298 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 53298 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 53298 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 53298 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 53298 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959724 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 959724 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 959724 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 959724 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 959724 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 959724 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11694537694 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11694537694 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11694537694 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.113155 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.113155 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12185.313376 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12185.313376 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53432 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 53432 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 53432 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 53432 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 53432 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 53432 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958299 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 958299 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 958299 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 958299 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 958299 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 958299 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11693776143 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11693776143 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11693776143 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11693776143 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11693776143 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11693776143 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112880 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.112880 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.112880 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12202.638365 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12202.638365 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency
1066,1076c1064,1074
< system.cpu.itb_walker_cache.tags.replacements 8004 # number of replacements
< system.cpu.itb_walker_cache.tags.tagsinuse 6.959011 # Cycle average of tags in use
< system.cpu.itb_walker_cache.tags.total_refs 21893 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.sampled_refs 8020 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.tags.avg_refs 2.729800 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.warmup_cycle 5103903665500 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.959011 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.434938 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.434938 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21891 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 21891 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.tags.replacements 8926 # number of replacements
> system.cpu.itb_walker_cache.tags.tagsinuse 6.004704 # Cycle average of tags in use
> system.cpu.itb_walker_cache.tags.total_refs 20407 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.sampled_refs 8940 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.tags.avg_refs 2.282662 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.warmup_cycle 5105549292500 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.004704 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375294 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.375294 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20415 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 20415 # number of ReadReq hits
1079,1096c1077,1094
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21893 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 21893 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21893 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 21893 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8894 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 8894 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8894 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 8894 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8894 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 8894 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 101842497 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 101842497 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 101842497 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 101842497 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 101842497 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 101842497 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30785 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 30785 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20417 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 20417 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20417 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 20417 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9803 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 9803 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9803 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 9803 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9803 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 9803 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 109186247 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 109186247 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 109186247 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 109186247 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 109186247 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 109186247 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30218 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 30218 # number of ReadReq accesses(hits+misses)
1099,1114c1097,1112
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30787 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30220 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 30220 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30220 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 30220 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.324409 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.324409 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.324388 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.324388 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.324388 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.324388 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11138.044170 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11138.044170 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11138.044170 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11138.044170 # average overall miss latency
1123,1148c1121,1146
< system.cpu.itb_walker_cache.writebacks::writebacks 2197 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 2197 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8894 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8894 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8894 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 8894 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 84047009 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 84047009 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 84047009 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 84047009 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 84047009 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9803 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9803 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9803 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 9803 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9803 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 9803 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 89573259 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 89573259 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 89573259 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 89573259 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 89573259 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 89573259 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.324409 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.324409 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.324388 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.324388 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9137.331327 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency
1150,1194c1148,1192
< system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements
< system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency
---
> system.cpu.dtb_walker_cache.tags.replacements 68011 # number of replacements
> system.cpu.dtb_walker_cache.tags.tagsinuse 14.842846 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 91726 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.sampled_refs 68027 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.avg_refs 1.348376 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 91726 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91726 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 91726 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69066 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 69066 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69066 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 69066 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69066 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 69066 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 860977213 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 860977213 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 860977213 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 860977213 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 860977213 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 860977213 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160792 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 160792 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160792 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 160792 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160792 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 160792 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429536 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429536 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429536 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429536 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429536 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429536 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12466.006617 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12466.006617 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12466.006617 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12466.006617 # average overall miss latency
1203,1228c1201,1226
< system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 21216 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 21216 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69066 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69066 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69066 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 69066 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69066 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 69066 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 722730929 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 722730929 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 722730929 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 722730929 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 722730929 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 722730929 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429536 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429536 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429536 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10464.351910 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency
1230,1234c1228,1232
< system.cpu.dcache.tags.replacements 1657437 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 1656829 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.997280 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 18997986 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1657341 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 11.462931 # Average number of references to valid blocks.
1236,1287c1234,1285
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits
< system.cpu.dcache.overall_hits::total 18986697 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2550677 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2550677 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2550677 # number of overall misses
< system.cpu.dcache.overall_misses::total 2550677 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 33004921637 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 33004921637 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 12257889032 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 12257889032 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 45262810669 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 45262810669 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 45262810669 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 45262810669 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13125399 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13125399 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8411975 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8411975 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21537374 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21537374 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21537374 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21537374 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170241 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.170241 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 17745.410598 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 17745.410598 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 397669 # number of cycles access was blocked
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.997280 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 10898836 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 10898836 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8096443 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8096443 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 18995279 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 18995279 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 18995279 # number of overall hits
> system.cpu.dcache.overall_hits::total 18995279 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2236048 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2236048 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 316058 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 316058 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2552106 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2552106 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2552106 # number of overall misses
> system.cpu.dcache.overall_misses::total 2552106 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 33041447208 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 33041447208 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 12234670517 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 12234670517 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 45276117725 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 45276117725 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 45276117725 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 45276117725 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 13134884 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13134884 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8412501 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8412501 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21547385 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21547385 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21547385 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21547385 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170237 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.170237 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037570 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.037570 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.118442 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.118442 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.118442 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.118442 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14776.716425 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14776.716425 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38710.206725 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38710.206725 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 17740.688563 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 17740.688563 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 395761 # number of cycles access was blocked
1289c1287
< system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 42262 # number of cycles access was blocked
1291c1289
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.364465 # average number of cycles each access was blocked
1295,1342c1293,1340
< system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks
< system.cpu.dcache.writebacks::total 1558744 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 864490 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25919 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 25919 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 890409 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 890409 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 890409 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 890409 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369989 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1369989 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290279 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 290279 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1660268 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1660268 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1660268 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1660268 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17836083706 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 17836083706 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11362753211 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11362753211 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29198836917 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 29198836917 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29198836917 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034508 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034508 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13019.143735 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13019.143735 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39144.248158 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39144.248158 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 1558454 # number of writebacks
> system.cpu.dcache.writebacks::total 1558454 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866560 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 866560 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25905 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 25905 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 892465 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 892465 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 892465 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 892465 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369488 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1369488 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290153 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 290153 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1659641 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1659641 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1659641 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1659641 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17811534705 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 17811534705 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11340798474 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11340798474 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29152333179 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 29152333179 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29152333179 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 29152333179 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363398000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363398000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536146500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536146500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899544500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899544500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104263 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104263 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034491 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034491 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.077023 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.077023 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.980852 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.980852 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39085.580621 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39085.580621 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency
1350,1354c1348,1352
< system.cpu.l2cache.tags.replacements 111632 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64821.705622 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3786761 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 175570 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 21.568383 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 111322 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64824.350244 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3788284 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 175285 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 21.612140 # Average number of references to valid blocks.
1356,1362c1354,1360
< system.cpu.l2cache.tags.occ_blocks::writebacks 50709.515998 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.756367 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126012 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3028.517183 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.790063 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.773766 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000118 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50850.934653 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.783858 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126014 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3002.561725 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10960.943994 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.775924 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000149 # Average percentage of cache occupancy
1364,1387c1362,1385
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046212 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.169003 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.989101 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7222 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 943511 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1333169 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2348748 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1585586 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1585586 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 155047 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 155047 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 64846 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 7222 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 943511 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1488216 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2503795 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 64846 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 7222 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 943511 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1488216 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2503795 # number of overall hits
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045815 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.167251 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.989141 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64096 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7642 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 942107 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1332840 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2346685 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1581663 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1581663 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 155094 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 155094 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 64096 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 942107 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1487934 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2501779 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 64096 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 7642 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 942107 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1487934 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2501779 # number of overall hits
1390,1396c1388,1394
< system.cpu.l2cache.ReadReq_misses::cpu.inst 16089 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 36006 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 52161 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133062 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133062 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 16085 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 35964 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 52115 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1454 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1454 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 132906 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 132906 # number of ReadExReq misses
1399,1401c1397,1399
< system.cpu.l2cache.demand_misses::cpu.inst 16089 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 169068 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 185223 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 16085 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 168870 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 185021 # number of demand (read+write) misses
1404,1484c1402,1482
< system.cpu.l2cache.overall_misses::cpu.inst 16089 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 169068 # number of overall misses
< system.cpu.l2cache.overall_misses::total 185223 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5260500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1277797734 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940044940 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 4223492924 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17900790 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 17900790 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9477459899 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9477459899 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5260500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1277797734 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12417504839 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 13700952823 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5260500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1277797734 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12417504839 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 13700952823 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64907 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7227 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 959600 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1369175 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2400909 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1585586 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1585586 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1776 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1776 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 288109 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 288109 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64907 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 7227 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 959600 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1657284 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2689018 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64907 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 7227 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 959600 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1657284 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2689018 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000940 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000692 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016766 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026298 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823198 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823198 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461846 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.461846 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000940 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000692 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016766 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102015 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.068881 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000940 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000692 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016766 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102015 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.068881 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86237.704918 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77950 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79420.581391 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81654.305949 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 80970.321198 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12244.042408 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12244.042408 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71225.893937 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71225.893937 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73970.040562 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73970.040562 # average overall miss latency
---
> system.cpu.l2cache.overall_misses::cpu.inst 16085 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 168870 # number of overall misses
> system.cpu.l2cache.overall_misses::total 185021 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5922249 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 375500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1293203490 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2919351194 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 4218852433 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17719300 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 17719300 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9455061655 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9455061655 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5922249 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 375500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1293203490 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12374412849 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 13673914088 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5922249 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 375500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1293203490 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12374412849 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 13673914088 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64157 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7647 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 958192 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1368804 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2398800 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1581663 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1581663 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1774 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1774 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 288000 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 288000 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64157 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 7647 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 958192 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1656804 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2686800 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64157 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 7647 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 958192 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1656804 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2686800 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000951 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000654 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016787 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026274 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021725 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.819617 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.819617 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461479 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.461479 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000951 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000654 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016787 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.101925 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.068863 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000951 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000654 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016787 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.101925 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.068863 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97086.049180 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75100 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80398.103202 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81174.262985 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 80952.747443 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12186.588721 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12186.588721 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71140.969219 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71140.969219 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97086.049180 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75100 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80398.103202 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73277.745301 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73904.659947 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97086.049180 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75100 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80398.103202 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73277.745301 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73904.659947 # average overall miss latency
1493,1495c1491,1493
< system.cpu.l2cache.writebacks::writebacks 101920 # number of writebacks
< system.cpu.l2cache.writebacks::total 101920 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 101656 # number of writebacks
> system.cpu.l2cache.writebacks::total 101656 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
1497,1498c1495,1496
< system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1500,1501c1498,1499
< system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1503c1501
< system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
1506,1512c1504,1510
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16087 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36005 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 52158 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133062 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133062 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16084 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35963 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 52113 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1454 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1454 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132906 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 132906 # number of ReadExReq MSHR misses
1515,1517c1513,1515
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16087 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 169067 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 185220 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16084 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 168869 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 185019 # number of demand (read+write) MSHR misses
1520,1585c1518,1583
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16087 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 169067 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 185220 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4502000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075523016 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2491735810 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3572087076 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15586943 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15586943 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7807116101 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7807116101 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4502000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075523016 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10298851911 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 11379203177 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4502000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075523016 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10298851911 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 11379203177 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251387000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251387000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372677500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372677500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624064500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624064500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026297 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823198 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823198 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461846 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461846 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.068880 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.068880 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16084 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 168869 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 185019 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5166251 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 312500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1091253760 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2471371556 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3568104067 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15558435 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15558435 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7786682845 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7786682845 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5166251 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1091253760 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10258054401 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11354786912 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5166251 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 312500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1091253760 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10258054401 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11354786912 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250274500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250274500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370476500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370476500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620751000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620751000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026273 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021725 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.819617 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.819617 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461479 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461479 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.068862 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.068862 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67847.162397 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68719.838612 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68468.598373 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10700.436726 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10700.436726 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58587.895543 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58587.895543 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency