3,5c3,5
< sim_seconds 5.132866 # Number of seconds simulated
< sim_ticks 5132865528000 # Number of ticks simulated
< final_tick 5132865528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.132970 # Number of seconds simulated
> sim_ticks 5132969930500 # Number of ticks simulated
> final_tick 5132969930500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,15c7,15
< host_inst_rate 61482 # Simulator instruction rate (inst/s)
< host_op_rate 121532 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 773550742 # Simulator tick rate (ticks/s)
< host_mem_usage 771808 # Number of bytes of host memory used
< host_seconds 6635.46 # Real time elapsed on the host
< sim_insts 407963797 # Number of instructions simulated
< sim_ops 806422961 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::pc.south_bridge.ide 2435200 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory
---
> host_inst_rate 124251 # Simulator instruction rate (inst/s)
> host_op_rate 245606 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1563205434 # Simulator tick rate (ticks/s)
> host_mem_usage 769808 # Number of bytes of host memory used
> host_seconds 3283.62 # Real time elapsed on the host
> sim_insts 407992820 # Number of instructions simulated
> sim_ops 806477449 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::pc.south_bridge.ide 2455424 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory
17,25c17,25
< system.physmem.bytes_read::cpu.inst 1080768 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10867584 # Number of bytes read from this memory
< system.physmem.bytes_read::total 14387264 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1080768 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1080768 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9583040 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9583040 # Number of bytes written to this memory
< system.physmem.num_reads::pc.south_bridge.ide 38050 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::cpu.inst 1078336 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10828544 # Number of bytes read from this memory
> system.physmem.bytes_read::total 14365568 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1078336 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1078336 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9561728 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9561728 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 38366 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory
27,33c27,33
< system.physmem.num_reads::cpu.inst 16887 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 169806 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 224801 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 149735 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 149735 # Number of write requests responded to by this memory
< system.physmem.bw_read::pc.south_bridge.ide 474433 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu.inst 16849 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 169196 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 224462 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 149402 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 149402 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 478363 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 561 # Total read bandwidth from this memory (bytes/s)
35,44c35,44
< system.physmem.bw_read::cpu.inst 210558 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2117255 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2802969 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 210558 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 210558 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1866996 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1866996 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1866996 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 474433 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 210080 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2109606 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2798685 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 210080 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 210080 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1862806 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1862806 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1862806 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 478363 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 561 # Total bandwidth to/from this memory (bytes/s)
46,89c46,89
< system.physmem.bw_total::cpu.inst 210558 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2117255 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4669965 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 224801 # Total number of read requests seen
< system.physmem.writeReqs 149735 # Total number of write requests seen
< system.physmem.cpureqs 378687 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 14387264 # Total number of bytes read from memory
< system.physmem.bytesWritten 9583040 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 14387264 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 9583040 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 4143 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 14181 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 13154 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 13072 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 16238 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 13617 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 13098 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 13611 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 16569 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 13873 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 13226 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 13363 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 15769 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 13267 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 12663 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 13279 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 15733 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 9192 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 8646 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 8408 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 11578 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 8737 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 8467 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 8901 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 11873 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 9014 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 8670 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 8751 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 11255 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 8399 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 8107 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 8591 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 11146 # Track writes on a per bank basis
---
> system.physmem.bw_total::cpu.inst 210080 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2109606 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4661492 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 224462 # Total number of read requests seen
> system.physmem.writeReqs 149402 # Total number of write requests seen
> system.physmem.cpureqs 377855 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 14365568 # Total number of bytes read from memory
> system.physmem.bytesWritten 9561728 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 14365568 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 9561728 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 117 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 3983 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 14085 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 13102 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 13279 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 16301 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 13529 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 13167 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 13352 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 16230 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 13914 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 13149 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 13590 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 15875 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 13170 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 12525 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 13306 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 15771 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 9020 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 8543 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 8624 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 11619 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 8726 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 8620 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 8763 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 11646 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 9037 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 8560 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 8885 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 11311 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 8333 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 8041 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 8600 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 11074 # Track writes on a per bank basis
92c92
< system.physmem.totGap 5132865474500 # Total gap between requests
---
> system.physmem.totGap 5132969877000 # Total gap between requests
99c99
< system.physmem.readPktSize::6 224801 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 224462 # Categorize read packet sizes
106,128c106,128
< system.physmem.writePktSize::6 149735 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 174182 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 19233 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 7394 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 3462 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 2978 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2373 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1871 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1730 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1664 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1149 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1011 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 945 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 877 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 806 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 787 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 920 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 857 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 409 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 232 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 149402 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 173725 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 19496 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 7507 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 3528 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3016 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2369 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1847 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1787 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1703 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1643 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1099 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 996 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 911 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 849 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 783 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 765 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 852 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 836 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 389 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 218 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
139,165c139,165
< system.physmem.wrQLenPdf::0 5387 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 5729 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 6323 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 6403 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 6452 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 6475 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 6492 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 6496 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 6498 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 1124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 188 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 108 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 5343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 5697 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 6328 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 6401 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 6437 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 6470 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 6476 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 6496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 6496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 6496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 6496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 6496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 6496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 6496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 6496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 799 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 95 # What write queue length does an incoming req see
167,176c167,176
< system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
< system.physmem.totQLat 4748150250 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 9279735250 # Sum of mem lat for all requests
< system.physmem.totBusLat 1123565000 # Total cycles spent in databus access
< system.physmem.totBankLat 3408020000 # Total cycles spent in bank access
< system.physmem.avgQLat 21129.84 # Average queueing delay per request
< system.physmem.avgBankLat 15166.10 # Average bank access latency per request
---
> system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see
> system.physmem.totQLat 4645349999 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 9161289999 # Sum of mem lat for all requests
> system.physmem.totBusLat 1121725000 # Total cycles spent in databus access
> system.physmem.totBankLat 3394215000 # Total cycles spent in bank access
> system.physmem.avgQLat 20706.28 # Average queueing delay per request
> system.physmem.avgBankLat 15129.44 # Average bank access latency per request
178c178
< system.physmem.avgMemAccLat 41295.94 # Average memory access latency
---
> system.physmem.avgMemAccLat 40835.72 # Average memory access latency
180c180
< system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s
---
> system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
182c182
< system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
186,193c186,193
< system.physmem.avgWrQLen 10.74 # Average write queue length over time
< system.physmem.readRowHits 193533 # Number of row buffer hits during reads
< system.physmem.writeRowHits 105971 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 86.12 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes
< system.physmem.avgGap 13704598.42 # Average gap between requests
< system.iocache.replacements 47575 # number of replacements
< system.iocache.tagsinuse 0.104035 # Cycle average of tags in use
---
> system.physmem.avgWrQLen 14.56 # Average write queue length over time
> system.physmem.readRowHits 193479 # Number of row buffer hits during reads
> system.physmem.writeRowHits 105949 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 86.24 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 70.92 # Row buffer hit rate for writes
> system.physmem.avgGap 13729510.94 # Average gap between requests
> system.iocache.replacements 47582 # number of replacements
> system.iocache.tagsinuse 0.103934 # Cycle average of tags in use
195c195
< system.iocache.sampled_refs 47591 # Sample count of references to valid blocks.
---
> system.iocache.sampled_refs 47598 # Sample count of references to valid blocks.
197,202c197,202
< system.iocache.warmup_cycle 4991882227000 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::pc.south_bridge.ide 0.104035 # Average occupied blocks per requestor
< system.iocache.occ_percent::pc.south_bridge.ide 0.006502 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.006502 # Average percentage of cache occupancy
< system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
---
> system.iocache.warmup_cycle 4992018141000 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::pc.south_bridge.ide 0.103934 # Average occupied blocks per requestor
> system.iocache.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.006496 # Average percentage of cache occupancy
> system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 917 # number of ReadReq misses
205,218c205,218
< system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses
< system.iocache.demand_misses::total 47630 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses
< system.iocache.overall_misses::total 47630 # number of overall misses
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142432660 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 142432660 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10000305290 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10000305290 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 10142737950 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10142737950 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 10142737950 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10142737950 # number of overall miss cycles
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::pc.south_bridge.ide 47637 # number of demand (read+write) misses
> system.iocache.demand_misses::total 47637 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 47637 # number of overall misses
> system.iocache.overall_misses::total 47637 # number of overall misses
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144155397 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 144155397 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9929896111 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 9929896111 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 10074051508 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 10074051508 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 10074051508 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 10074051508 # number of overall miss cycles
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses)
221,224c221,224
< system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 47637 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 47637 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 47637 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 47637 # number of overall (read+write) accesses
233,241c233,241
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156519.406593 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 156519.406593 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214047.630351 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 214047.630351 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 212948.518791 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 212948.518791 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 212948.518791 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 212948.518791 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 135861 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157203.268266 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 157203.268266 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212540.584568 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 212540.584568 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211475.355459 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 211475.355459 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211475.355459 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 211475.355459 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 131232 # number of cycles access was blocked
243c243
< system.iocache.blocked::no_mshrs 12418 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 11911 # number of cycles access was blocked
245c245
< system.iocache.avg_blocked_cycles::no_mshrs 10.940651 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 11.017715 # average number of cycles each access was blocked
251,252c251,252
< system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses
255,266c255,266
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95090941 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 95090941 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7569522729 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 7569522729 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7664613670 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 7664613670 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7664613670 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 7664613670 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 47637 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 47637 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 47637 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 47637 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96449927 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 96449927 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7499098563 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 7499098563 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7595548490 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 7595548490 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7595548490 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 7595548490 # number of overall MSHR miss cycles
275,282c275,282
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104495.539560 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 104495.539560 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162018.894028 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 162018.894028 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105179.854962 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 105179.854962 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160511.527461 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 160511.527461 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159446.406995 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 159446.406995 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159446.406995 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 159446.406995 # average overall mshr miss latency
286c286
< system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
---
> system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
296,300c296,300
< system.cpu.branchPred.lookups 86256793 # Number of BP lookups
< system.cpu.branchPred.condPredicted 86256793 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1113068 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 81525739 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 79259204 # Number of BTB hits
---
> system.cpu.branchPred.lookups 86228247 # Number of BP lookups
> system.cpu.branchPred.condPredicted 86228247 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1109691 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 81322722 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 79235054 # Number of BTB hits
302c302
< system.cpu.branchPred.BTBHitPct 97.219853 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 97.432860 # BTB Hit Percentage
305c305
< system.cpu.numCycles 448546895 # number of cpu cycles simulated
---
> system.cpu.numCycles 448477988 # number of cpu cycles simulated
308,324c308,324
< system.cpu.fetch.icacheStallCycles 27629675 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 426131263 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 86256793 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 79259204 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 163637829 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 4743979 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 122519 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.BlockedCycles 63152705 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 36413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 51550 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 9043434 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 488848 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 3024 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 258223805 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 3.257780 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.417802 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 27463696 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 426083477 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 86228247 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 79235054 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 163617772 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 4719624 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 125826 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.BlockedCycles 63227537 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 35895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 53383 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 9034836 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 484573 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 2662 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 258095876 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 3.259036 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.417947 # Number of instructions fetched each cycle (Total)
326,334c326,334
< system.cpu.fetch.rateDist::0 95012138 36.79% 36.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1565899 0.61% 37.40% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 71926197 27.85% 65.26% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 935616 0.36% 65.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 1604506 0.62% 66.24% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 2433567 0.94% 67.18% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 1079084 0.42% 67.60% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1383528 0.54% 68.13% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 82283270 31.87% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 94906138 36.77% 36.77% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1565225 0.61% 37.38% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 71916844 27.86% 65.24% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 940016 0.36% 65.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 1600383 0.62% 66.23% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 2424857 0.94% 67.17% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 1078498 0.42% 67.58% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1383259 0.54% 68.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 82280656 31.88% 100.00% # Number of instructions fetched each cycle (Total)
338,381c338,381
< system.cpu.fetch.rateDist::total 258223805 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.192303 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.950026 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 31307096 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 60630076 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 159436775 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 3257103 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 3592755 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 838113616 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 880 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 3592755 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 34040592 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 37476959 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 11041434 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 159631550 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 12440515 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 834468110 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 19385 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 5834152 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 4771877 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 8971 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 996054249 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1811560635 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1811560099 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 964410768 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 31643474 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 457361 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 464527 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 28752334 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 17095902 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 10132687 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1166436 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 902107 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 828339786 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1247404 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 823331592 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 149918 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 22245950 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 33811662 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 194652 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 258223805 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 3.188442 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.385103 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 258095876 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.192269 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.950066 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 31171664 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 60678279 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 159406116 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 3268443 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 3571374 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 838032918 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 3571374 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 33913667 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 37519467 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 11021070 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 159605851 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 12464447 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 834371126 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 19504 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 5869459 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 4764277 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 8601 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 995955832 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1811371309 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1811370333 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 976 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 964482413 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 31473412 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 459237 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 467213 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 28827657 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 17084902 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 10144761 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1200685 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 943086 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 828239567 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1251844 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 823277169 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 150176 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 22096824 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 33604785 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 197691 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 258095876 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 3.189811 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 2.384487 # Number of insts issued each cycle
383,391c383,391
< system.cpu.iq.issued_per_cycle::0 71699549 27.77% 27.77% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 15529974 6.01% 33.78% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 10286408 3.98% 37.76% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7471868 2.89% 40.66% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 75917572 29.40% 70.06% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 3857166 1.49% 71.55% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 72524361 28.09% 99.64% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 784342 0.30% 99.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 152565 0.06% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 71559419 27.73% 27.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 15540861 6.02% 33.75% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 10303423 3.99% 37.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7474044 2.90% 40.64% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 75918752 29.41% 70.05% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 3850758 1.49% 71.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 72514611 28.10% 99.64% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 781198 0.30% 99.94% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 152810 0.06% 100.00% # Number of insts issued each cycle
395c395
< system.cpu.iq.issued_per_cycle::total 258223805 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 258095876 # Number of insts issued each cycle
397c397
< system.cpu.iq.fu_full::IntAlu 368681 34.39% 34.39% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 369026 34.39% 34.39% # attempts to use FU when none available
426,427c426,427
< system.cpu.iq.fu_full::MemRead 552933 51.58% 85.98% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 150329 14.02% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 552435 51.48% 85.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 151573 14.13% 100.00% # attempts to use FU when none available
430,431c430,431
< system.cpu.iq.FU_type_0::No_OpClass 310005 0.04% 0.04% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 795767028 96.65% 96.69% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 311214 0.04% 0.04% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 795705202 96.65% 96.69% # Type of FU issued
460,461c460,461
< system.cpu.iq.FU_type_0::MemRead 17865255 2.17% 98.86% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 9389304 1.14% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 17863780 2.17% 98.86% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 9396973 1.14% 100.00% # Type of FU issued
464,476c464,476
< system.cpu.iq.FU_type_0::total 823331592 # Type of FU issued
< system.cpu.iq.rate 1.835553 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1071943 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.001302 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 1906239242 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 851843261 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 818849223 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 824093432 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1643495 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 823277169 # Type of FU issued
> system.cpu.iq.rate 1.835714 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1073034 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.001303 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 1906003583 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 851598062 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 818801577 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 824038818 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1644527 # Number of loads that had data forwarded from stores
478,481c478,481
< system.cpu.iew.lsq.thread0.squashedLoads 3116410 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 23570 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 11612 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1711798 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 3094800 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 23435 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 11502 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1720038 # Number of stores squashed
484,485c484,485
< system.cpu.iew.lsq.thread0.rescheduledLoads 1932508 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 11844 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 1932547 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 11959 # Number of times an access to memory failed due to the cache being blocked
487,503c487,503
< system.cpu.iew.iewSquashCycles 3592755 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 26248050 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 2110636 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 829587190 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 321004 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 17095902 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 10132687 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 717072 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 1612321 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 11848 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 11612 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 657039 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 595254 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1252293 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 821445338 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 17448687 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1886253 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 3571374 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 26260647 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 2115726 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 829491411 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 321621 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 17084902 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 10144761 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 719315 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 1617594 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 12405 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 11502 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 654420 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 592576 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1246996 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 821399469 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 17452724 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1877699 # Number of squashed instructions skipped in execute
506,513c506,513
< system.cpu.iew.exec_refs 26607218 # number of memory reference insts executed
< system.cpu.iew.exec_branches 83228491 # Number of branches executed
< system.cpu.iew.exec_stores 9158531 # Number of stores executed
< system.cpu.iew.exec_rate 1.831348 # Inst execution rate
< system.cpu.iew.wb_sent 820983226 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 818849277 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 639988645 # num instructions producing a value
< system.cpu.iew.wb_consumers 1045811759 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 26617414 # number of memory reference insts executed
> system.cpu.iew.exec_branches 83217280 # Number of branches executed
> system.cpu.iew.exec_stores 9164690 # Number of stores executed
> system.cpu.iew.exec_rate 1.831527 # Inst execution rate
> system.cpu.iew.wb_sent 820937084 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 818801671 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 639944880 # num instructions producing a value
> system.cpu.iew.wb_consumers 1045797819 # num instructions consuming a value
515,516c515,516
< system.cpu.iew.wb_rate 1.825560 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.611954 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.825734 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.611920 # average fanout of values written-back
518,523c518,523
< system.cpu.commit.commitSquashedInsts 23057499 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1052750 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 1117600 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 254631050 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 3.167025 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.854459 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 22903910 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1054151 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 1114557 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 254524502 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 3.168565 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.854370 # Number of insts commited each cycle
525,533c525,533
< system.cpu.commit.committed_per_cycle::0 82837862 32.53% 32.53% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 11822724 4.64% 37.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3905327 1.53% 38.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 74951929 29.44% 68.14% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 2438342 0.96% 69.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1480698 0.58% 69.68% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 927919 0.36% 70.05% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 70920568 27.85% 97.90% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 5345681 2.10% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 82731188 32.50% 32.50% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 11811542 4.64% 37.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3909670 1.54% 38.68% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 74949600 29.45% 68.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 2435927 0.96% 69.08% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1480813 0.58% 69.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 938860 0.37% 70.04% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 70918382 27.86% 97.90% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 5348520 2.10% 100.00% # Number of insts commited each cycle
537,539c537,539
< system.cpu.commit.committed_per_cycle::total 254631050 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 407963797 # Number of instructions committed
< system.cpu.commit.committedOps 806422961 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 254524502 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 407992820 # Number of instructions committed
> system.cpu.commit.committedOps 806477449 # Number of ops (including micro ops) committed
541,544c541,544
< system.cpu.commit.refs 22400378 # Number of memory references committed
< system.cpu.commit.loads 13979489 # Number of loads committed
< system.cpu.commit.membars 473507 # Number of memory barriers committed
< system.cpu.commit.branches 82198469 # Number of branches committed
---
> system.cpu.commit.refs 22414822 # Number of memory references committed
> system.cpu.commit.loads 13990099 # Number of loads committed
> system.cpu.commit.membars 474403 # Number of memory barriers committed
> system.cpu.commit.branches 82204209 # Number of branches committed
546c546
< system.cpu.commit.int_insts 735362199 # Number of committed integer instructions.
---
> system.cpu.commit.int_insts 735419466 # Number of committed integer instructions.
548c548
< system.cpu.commit.bw_lim_events 5345681 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 5348520 # number cycles where commit BW limit reached
550,612c550,612
< system.cpu.rob.rob_reads 1078687614 # The number of ROB reads
< system.cpu.rob.rob_writes 1662572605 # The number of ROB writes
< system.cpu.timesIdled 1222238 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 190323090 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 9817181581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 407963797 # Number of Instructions Simulated
< system.cpu.committedOps 806422961 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 407963797 # Number of Instructions Simulated
< system.cpu.cpi 1.099477 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.099477 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.909523 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.909523 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1507059295 # number of integer regfile reads
< system.cpu.int_regfile_writes 977046319 # number of integer regfile writes
< system.cpu.fp_regfile_reads 54 # number of floating regfile reads
< system.cpu.misc_regfile_reads 264741173 # number of misc regfile reads
< system.cpu.misc_regfile_writes 402265 # number of misc regfile writes
< system.cpu.icache.replacements 1056074 # number of replacements
< system.cpu.icache.tagsinuse 510.395640 # Cycle average of tags in use
< system.cpu.icache.total_refs 7921465 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 1056586 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 7.497227 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 56044666000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 510.395640 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.996866 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.996866 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 7921465 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 7921465 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 7921465 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 7921465 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 7921465 # number of overall hits
< system.cpu.icache.overall_hits::total 7921465 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1121968 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1121968 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1121968 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1121968 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1121968 # number of overall misses
< system.cpu.icache.overall_misses::total 1121968 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15396039491 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15396039491 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15396039491 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15396039491 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15396039491 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15396039491 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 9043433 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 9043433 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 9043433 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 9043433 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 9043433 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 9043433 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124064 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.124064 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.124064 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.124064 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.124064 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.124064 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13722.351699 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13722.351699 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13722.351699 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13722.351699 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13722.351699 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13722.351699 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 11326 # number of cycles access was blocked
---
> system.cpu.rob.rob_reads 1078479140 # The number of ROB reads
> system.cpu.rob.rob_writes 1662352652 # The number of ROB writes
> system.cpu.timesIdled 1219186 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 190382112 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 9817459293 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 407992820 # Number of Instructions Simulated
> system.cpu.committedOps 806477449 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 407992820 # Number of Instructions Simulated
> system.cpu.cpi 1.099230 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.099230 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.909728 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.909728 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1507089895 # number of integer regfile reads
> system.cpu.int_regfile_writes 977019847 # number of integer regfile writes
> system.cpu.fp_regfile_reads 94 # number of floating regfile reads
> system.cpu.misc_regfile_reads 264717116 # number of misc regfile reads
> system.cpu.misc_regfile_writes 402314 # number of misc regfile writes
> system.cpu.icache.replacements 1047040 # number of replacements
> system.cpu.icache.tagsinuse 510.337680 # Cycle average of tags in use
> system.cpu.icache.total_refs 7922656 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 1047552 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 7.563019 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 56182186000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 510.337680 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.996753 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.996753 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 7922656 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 7922656 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 7922656 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 7922656 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 7922656 # number of overall hits
> system.cpu.icache.overall_hits::total 7922656 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1112177 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1112177 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1112177 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1112177 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1112177 # number of overall misses
> system.cpu.icache.overall_misses::total 1112177 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15267217991 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15267217991 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15267217991 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15267217991 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15267217991 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15267217991 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 9034833 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 9034833 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 9034833 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 9034833 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 9034833 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 9034833 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123099 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.123099 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.123099 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.123099 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.123099 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.123099 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.327567 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13727.327567 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.327567 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13727.327567 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.327567 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13727.327567 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 9786 # number of cycles access was blocked
614c614
< system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked
616c616
< system.cpu.icache.avg_blocked_cycles::no_mshrs 43.229008 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 33.744828 # average number of cycles each access was blocked
620,649c620,649
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62943 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 62943 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 62943 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 62943 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 62943 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 62943 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1059025 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1059025 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1059025 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1059025 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1059025 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1059025 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12680665992 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12680665992 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12680665992 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12680665992 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12680665992 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12680665992 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117104 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.117104 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.117104 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11973.906180 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11973.906180 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11973.906180 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11973.906180 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11973.906180 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11973.906180 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62286 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 62286 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 62286 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 62286 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 62286 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 62286 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1049891 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1049891 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1049891 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1049891 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1049891 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1049891 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12557489993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12557489993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12557489993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12557489993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12557489993 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12557489993 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116205 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.116205 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.116205 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11960.755919 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11960.755919 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11960.755919 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11960.755919 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11960.755919 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11960.755919 # average overall mshr miss latency
651,661c651,661
< system.cpu.itb_walker_cache.replacements 9902 # number of replacements
< system.cpu.itb_walker_cache.tagsinuse 6.007248 # Cycle average of tags in use
< system.cpu.itb_walker_cache.total_refs 25368 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.sampled_refs 9915 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.avg_refs 2.558548 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.warmup_cycle 5106962474500 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.007248 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375453 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.occ_percent::total 0.375453 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25400 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 25400 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.replacements 9201 # number of replacements
> system.cpu.itb_walker_cache.tagsinuse 6.008096 # Cycle average of tags in use
> system.cpu.itb_walker_cache.total_refs 25985 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.sampled_refs 9214 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.avg_refs 2.820165 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.warmup_cycle 5102794236000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008096 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375506 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.occ_percent::total 0.375506 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25989 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 25989 # number of ReadReq hits
664,681c664,681
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25402 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 25402 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25402 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 25402 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10789 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 10789 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10789 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 10789 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10789 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 10789 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 118480500 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 118480500 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 118480500 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 118480500 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 118480500 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 118480500 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36189 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 36189 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25991 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 25991 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25991 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 25991 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10086 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 10086 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10086 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 10086 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10086 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 10086 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117807500 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117807500 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117807500 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 117807500 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117807500 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 117807500 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36075 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 36075 # number of ReadReq accesses(hits+misses)
684,699c684,699
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36191 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 36191 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36191 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 36191 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298129 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298129 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298113 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.298113 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298113 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.298113 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10981.601631 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10981.601631 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10981.601631 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10981.601631 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10981.601631 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10981.601631 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36077 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 36077 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36077 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 36077 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.279584 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.279584 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.279569 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.279569 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.279569 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.279569 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11680.299425 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11680.299425 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11680.299425 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11680.299425 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11680.299425 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11680.299425 # average overall miss latency
708,733c708,733
< system.cpu.itb_walker_cache.writebacks::writebacks 2074 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 2074 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10789 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10789 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10789 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 10789 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10789 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 10789 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96902500 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96902500 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96902500 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96902500 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96902500 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96902500 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298129 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298129 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298113 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298113 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298113 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298113 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8981.601631 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8981.601631 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8981.601631 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 1386 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 1386 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10086 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10086 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10086 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 10086 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10086 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 10086 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97635500 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97635500 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 97635500 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 97635500 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97635500 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97635500 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.279584 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.279584 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.279569 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.279569 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.279569 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.279569 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9680.299425 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9680.299425 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9680.299425 # average overall mshr miss latency
735,779c735,779
< system.cpu.dtb_walker_cache.replacements 112679 # number of replacements
< system.cpu.dtb_walker_cache.tagsinuse 13.888368 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.total_refs 129664 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.sampled_refs 112694 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.avg_refs 1.150585 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.warmup_cycle 5099752322000 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.888368 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.868023 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.occ_percent::total 0.868023 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 129683 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 129683 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 129683 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 129683 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 129683 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 129683 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 113702 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 113702 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 113702 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 113702 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113702 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 113702 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1421375500 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1421375500 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1421375500 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 1421375500 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1421375500 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 1421375500 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243385 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 243385 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243385 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 243385 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243385 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 243385 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.467169 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.467169 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.467169 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.467169 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.467169 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.467169 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12500.883889 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12500.883889 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12500.883889 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12500.883889 # average overall miss latency
---
> system.cpu.dtb_walker_cache.replacements 108065 # number of replacements
> system.cpu.dtb_walker_cache.tagsinuse 12.354963 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.total_refs 134808 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.sampled_refs 108080 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.avg_refs 1.247298 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.warmup_cycle 5099892629000 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.354963 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.772185 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.occ_percent::total 0.772185 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134808 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 134808 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134808 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 134808 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134808 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 134808 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109105 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 109105 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109105 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 109105 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109105 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 109105 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1388403500 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1388403500 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1388403500 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 1388403500 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1388403500 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 1388403500 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243913 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 243913 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243913 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 243913 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243913 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 243913 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447311 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447311 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447311 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447311 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447311 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447311 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12725.388387 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12725.388387 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12725.388387 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12725.388387 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12725.388387 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12725.388387 # average overall miss latency
788,813c788,813
< system.cpu.dtb_walker_cache.writebacks::writebacks 35808 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 35808 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 113702 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 113702 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 113702 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 113702 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 113702 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 113702 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1193971500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1193971500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1193971500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.467169 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.467169 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.467169 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10500.883889 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10500.883889 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10500.883889 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 24362 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 24362 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109105 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109105 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109105 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 109105 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109105 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 109105 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1170193500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1170193500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1170193500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1170193500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1170193500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1170193500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447311 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447311 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447311 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447311 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447311 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447311 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10725.388387 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10725.388387 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10725.388387 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10725.388387 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10725.388387 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10725.388387 # average overall mshr miss latency
815,819c815,819
< system.cpu.dcache.replacements 1659172 # number of replacements
< system.cpu.dcache.tagsinuse 511.998283 # Cycle average of tags in use
< system.cpu.dcache.total_refs 19096669 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1659684 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 11.506208 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 1660424 # number of replacements
> system.cpu.dcache.tagsinuse 511.994188 # Cycle average of tags in use
> system.cpu.dcache.total_refs 19105277 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1660936 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 11.502717 # Average number of references to valid blocks.
821,857c821,857
< system.cpu.dcache.occ_blocks::cpu.data 511.998283 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.999997 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.999997 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 10998697 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 10998697 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8092860 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8092860 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 19091557 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 19091557 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 19091557 # number of overall hits
< system.cpu.dcache.overall_hits::total 19091557 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2244277 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2244277 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 318772 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 318772 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2563049 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2563049 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2563049 # number of overall misses
< system.cpu.dcache.overall_misses::total 2563049 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 32186629000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 32186629000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9715417494 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9715417494 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 41902046494 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 41902046494 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 41902046494 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 41902046494 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13242974 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13242974 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8411632 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8411632 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21654606 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21654606 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21654606 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21654606 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169469 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.169469 # miss rate for ReadReq accesses
---
> system.cpu.dcache.occ_blocks::cpu.data 511.994188 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 11003963 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11003963 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8096336 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8096336 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 19100299 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 19100299 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 19100299 # number of overall hits
> system.cpu.dcache.overall_hits::total 19100299 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2241441 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2241441 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 318912 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 318912 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2560353 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2560353 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2560353 # number of overall misses
> system.cpu.dcache.overall_misses::total 2560353 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 32061348000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 32061348000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9677558995 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9677558995 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 41738906995 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 41738906995 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 41738906995 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 41738906995 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 13245404 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13245404 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8415248 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8415248 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21660652 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21660652 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21660652 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21660652 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169224 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.169224 # miss rate for ReadReq accesses
860,872c860,872
< system.cpu.dcache.demand_miss_rate::cpu.data 0.118360 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.118360 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.118360 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.118360 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14341.647221 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14341.647221 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30477.637603 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 30477.637603 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 16348.515574 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 16348.515574 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 16348.515574 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 16348.515574 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 394709 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.118203 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.118203 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.118203 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.118203 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14303.900036 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14303.900036 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30345.546718 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 30345.546718 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 16302.012650 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 16302.012650 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 16302.012650 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 16302.012650 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 390714 # number of cycles access was blocked
874c874
< system.cpu.dcache.blocked::no_mshrs 43025 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 42563 # number of cycles access was blocked
876c876
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.173945 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.179663 # average number of cycles each access was blocked
880,927c880,927
< system.cpu.dcache.writebacks::writebacks 1560811 # number of writebacks
< system.cpu.dcache.writebacks::total 1560811 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 872480 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 872480 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26264 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 26264 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 898744 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 898744 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 898744 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 898744 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371797 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1371797 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292508 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 292508 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1664305 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1664305 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1664305 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1664305 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17453179000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 17453179000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8875888494 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8875888494 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26329067494 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26329067494 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26329067494 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26329067494 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97298479500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97298479500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473755000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473755000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99772234500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 99772234500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103587 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103587 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034774 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034774 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076857 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.076857 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076857 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.076857 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12722.858411 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12722.858411 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30344.088004 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30344.088004 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15819.857234 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 15819.857234 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15819.857234 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 15819.857234 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 1561895 # number of writebacks
> system.cpu.dcache.writebacks::total 1561895 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868390 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 868390 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26484 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 26484 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 894874 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 894874 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 894874 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 894874 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1373051 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1373051 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292428 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 292428 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1665479 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1665479 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1665479 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1665479 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17447685000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 17447685000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8836657995 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8836657995 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26284342995 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26284342995 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26284342995 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26284342995 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349027500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349027500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523629000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523629000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99872656500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 99872656500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103662 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103662 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034750 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034750 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076890 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.076890 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076890 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.076890 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12707.237386 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12707.237386 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30218.234899 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30218.234899 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15781.851945 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 15781.851945 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15781.851945 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 15781.851945 # average overall mshr miss latency
935,947c935,947
< system.cpu.l2cache.replacements 113709 # number of replacements
< system.cpu.l2cache.tagsinuse 64835.556178 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 3943740 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 177736 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 22.188752 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 50100.135073 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.dtb.walker 8.974222 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131215 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 3272.117566 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 11454.198102 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.764467 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000137 # Average percentage of cache occupancy
---
> system.cpu.l2cache.replacements 113316 # number of replacements
> system.cpu.l2cache.tagsinuse 64844.947508 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 3926990 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 177399 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 22.136483 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 218233367500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 50081.422465 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.dtb.walker 7.214267 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131819 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 3279.773941 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 11476.405015 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.764182 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000110 # Average percentage of cache occupancy
949,973c949,973
< system.cpu.l2cache.occ_percent::cpu.inst 0.049929 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.174777 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.989312 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 105558 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8113 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1039658 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1333728 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2487057 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1598693 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1598693 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 154593 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 154593 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 105558 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 8113 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1039658 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1488321 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2641650 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 105558 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 8113 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1039658 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1488321 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2641650 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses
---
> system.cpu.l2cache.occ_percent::cpu.inst 0.050045 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.175116 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.989455 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 104037 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8366 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1030644 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1335229 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2478276 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1587643 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1587643 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 340 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 340 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 155070 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 155070 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 104037 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 8366 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1030644 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1490299 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2633346 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 104037 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 8366 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1030644 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1490299 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2633346 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 45 # number of ReadReq misses
975,982c975,982
< system.cpu.l2cache.ReadReq_misses::cpu.inst 16888 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 36900 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 53846 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 3866 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 3866 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133854 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133854 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 16850 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 36755 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 53656 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 3711 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 3711 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133382 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133382 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 45 # number of demand (read+write) misses
984,987c984,987
< system.cpu.l2cache.demand_misses::cpu.inst 16888 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 170754 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 187700 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 16850 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 170137 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 187038 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 45 # number of overall misses
989,1035c989,1035
< system.cpu.l2cache.overall_misses::cpu.inst 16888 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 170754 # number of overall misses
< system.cpu.l2cache.overall_misses::total 187700 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4568000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1172288500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2518183499 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3695429499 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17446500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 17446500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6941993500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6941993500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4568000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1172288500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9460176999 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10637422999 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4568000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1172288500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9460176999 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10637422999 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 105610 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8119 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1056546 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1370628 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2540903 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1598693 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1598693 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4187 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 4187 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 288447 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 288447 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 105610 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 8119 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1056546 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1659075 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2829350 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 105610 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 8119 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1056546 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1659075 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2829350 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000492 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000739 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015984 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026922 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_misses::cpu.inst 16850 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 170137 # number of overall misses
> system.cpu.l2cache.overall_misses::total 187038 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4321500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 844000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1148867000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2499324500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3653357000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17608000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 17608000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6900952000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6900952000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4321500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 844000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1148867000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9400276500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 10554309000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4321500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 844000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1148867000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9400276500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 10554309000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 104082 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8372 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1047494 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1371984 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2531932 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1587643 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1587643 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4051 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 4051 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 288452 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 288452 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 104082 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 8372 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1047494 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1660436 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2820384 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 104082 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 8372 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1047494 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1660436 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2820384 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000432 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000717 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016086 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026790 # miss rate for ReadReq accesses
1037,1069c1037,1069
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.923334 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.923334 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464051 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.464051 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000492 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000739 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015984 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102921 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.066340 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000492 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000739 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015984 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102921 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.066340 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87846.153846 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69415.472525 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68243.455257 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68629.601066 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4512.803932 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4512.803932 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51862.428467 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51862.428467 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87846.153846 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69415.472525 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55402.374170 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 56672.472025 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87846.153846 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69415.472525 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55402.374170 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 56672.472025 # average overall miss latency
---
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916070 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916070 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.462406 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.462406 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000432 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000717 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016086 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102465 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.066317 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000432 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000717 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016086 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102465 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.066317 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 96033.333333 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 140666.666667 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68182.017804 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67999.578289 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68088.508275 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4744.812719 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4744.812719 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51738.255537 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51738.255537 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 96033.333333 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 140666.666667 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68182.017804 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55251.218136 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 56428.688288 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 96033.333333 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 140666.666667 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68182.017804 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55251.218136 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 56428.688288 # average overall miss latency
1078,1079c1078,1079
< system.cpu.l2cache.writebacks::writebacks 103068 # number of writebacks
< system.cpu.l2cache.writebacks::total 103068 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 102735 # number of writebacks
> system.cpu.l2cache.writebacks::total 102735 # number of writebacks
1089c1089
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 45 # number of ReadReq MSHR misses
1091,1098c1091,1098
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16887 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36899 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 53844 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3866 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 3866 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133854 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133854 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16849 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36754 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 53654 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3711 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 3711 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133382 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133382 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 45 # number of demand (read+write) MSHR misses
1100,1103c1100,1103
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16887 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 170753 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 187698 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16849 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 170136 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 187036 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 45 # number of overall MSHR misses
1105,1136c1105,1136
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16887 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 170753 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 187698 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3916050 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 962195275 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2059471232 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3025896812 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39657846 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39657846 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5291032825 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5291032825 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3916050 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 962195275 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7350504057 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 8316929637 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3916050 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 962195275 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7350504057 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 8316929637 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89189069500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89189069500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2311324000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2311324000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91500393500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91500393500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026921 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16849 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 170136 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 187036 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3761043 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 768755 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 939262274 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2042484891 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2986276963 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 38121191 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 38121191 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5255773881 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5255773881 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3761043 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 768755 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 939262274 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7298258772 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 8242050844 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3761043 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 768755 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 939262274 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7298258772 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 8242050844 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236734500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236734500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2358597000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2358597000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91595331500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91595331500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000432 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000717 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016085 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026789 # mshr miss rate for ReadReq accesses
1138,1170c1138,1170
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.923334 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.923334 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464051 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464051 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102921 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.066340 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102921 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.066340 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56978.461242 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55813.741077 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56197.474408 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10258.108122 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10258.108122 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39528.387833 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39528.387833 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56978.461242 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43047.583685 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44310.166528 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56978.461242 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43047.583685 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44310.166528 # average overall mshr miss latency
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916070 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916070 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.462406 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.462406 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000432 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000717 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016085 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102465 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.066316 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000432 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000717 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016085 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102465 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.066316 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55745.876551 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55571.771535 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55658.049036 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10272.484775 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10272.484775 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39403.921676 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39403.921676 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55745.876551 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42896.616660 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44066.654783 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55745.876551 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42896.616660 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44066.654783 # average overall mshr miss latency