3,5c3,5
< sim_seconds 5.173841 # Number of seconds simulated
< sim_ticks 5173840734500 # Number of ticks simulated
< final_tick 5173840734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.172902 # Number of seconds simulated
> sim_ticks 5172902281500 # Number of ticks simulated
> final_tick 5172902281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,53c7,53
< host_inst_rate 158571 # Simulator instruction rate (inst/s)
< host_op_rate 312487 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1923470418 # Simulator tick rate (ticks/s)
< host_mem_usage 368528 # Number of bytes of host memory used
< host_seconds 2689.85 # Real time elapsed on the host
< sim_insts 426531587 # Number of instructions simulated
< sim_ops 840543055 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::pc.south_bridge.ide 2458496 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 1064640 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10449152 # Number of bytes read from this memory
< system.physmem.bytes_read::total 13975936 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1064640 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1064640 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9180480 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9180480 # Number of bytes written to this memory
< system.physmem.num_reads::pc.south_bridge.ide 38414 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 16635 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 163268 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 218374 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 143445 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 143445 # Number of write requests responded to by this memory
< system.physmem.bw_read::pc.south_bridge.ide 475178 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.dtb.walker 618 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 205774 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2019612 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2701269 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 205774 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 205774 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1774403 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1774403 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1774403 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 475178 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 618 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 205774 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2019612 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4475672 # Total bandwidth to/from this memory (bytes/s)
< system.l2c.replacements 107079 # number of replacements
< system.l2c.tagsinuse 64844.194000 # Cycle average of tags in use
< system.l2c.total_refs 3995584 # Total number of references to valid blocks.
< system.l2c.sampled_refs 171337 # Sample count of references to valid blocks.
< system.l2c.avg_refs 23.320030 # Average number of references to valid blocks.
---
> host_inst_rate 117061 # Simulator instruction rate (inst/s)
> host_op_rate 230687 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1419746087 # Simulator tick rate (ticks/s)
> host_mem_usage 420308 # Number of bytes of host memory used
> host_seconds 3643.54 # Real time elapsed on the host
> sim_insts 426515724 # Number of instructions simulated
> sim_ops 840516219 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::pc.south_bridge.ide 2496512 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1067840 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10426304 # Number of bytes read from this memory
> system.physmem.bytes_read::total 13994560 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1067840 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1067840 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9194240 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9194240 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 39008 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 16685 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 162911 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 218665 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 143660 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 143660 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 482613 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 680 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 206430 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2015562 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2705359 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 206430 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 206430 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1777385 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1777385 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1777385 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 482613 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 206430 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2015562 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4482745 # Total bandwidth to/from this memory (bytes/s)
> system.l2c.replacements 107419 # number of replacements
> system.l2c.tagsinuse 64844.084797 # Cycle average of tags in use
> system.l2c.total_refs 3992672 # Total number of references to valid blocks.
> system.l2c.sampled_refs 171622 # Sample count of references to valid blocks.
> system.l2c.avg_refs 23.264337 # Average number of references to valid blocks.
55,60c55,60
< system.l2c.occ_blocks::writebacks 50153.806815 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.dtb.walker 12.883885 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.itb.walker 0.168545 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.inst 3383.279361 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 11294.055394 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.765286 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::writebacks 50135.967843 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.dtb.walker 12.897301 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.itb.walker 0.156788 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.inst 3372.666022 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 11322.396844 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.765014 # Average percentage of cache occupancy
62,165c62,165
< system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.inst 0.051625 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.data 0.172334 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.989444 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu.dtb.walker 110015 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.itb.walker 8879 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.inst 1055721 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.data 1346083 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 2520698 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 1613450 # number of Writeback hits
< system.l2c.Writeback_hits::total 1613450 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu.data 329 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 329 # number of UpgradeReq hits
< system.l2c.ReadExReq_hits::cpu.data 163813 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 163813 # number of ReadExReq hits
< system.l2c.demand_hits::cpu.dtb.walker 110015 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.itb.walker 8879 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.inst 1055721 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.data 1509896 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2684511 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu.dtb.walker 110015 # number of overall hits
< system.l2c.overall_hits::cpu.itb.walker 8879 # number of overall hits
< system.l2c.overall_hits::cpu.inst 1055721 # number of overall hits
< system.l2c.overall_hits::cpu.data 1509896 # number of overall hits
< system.l2c.overall_hits::total 2684511 # number of overall hits
< system.l2c.ReadReq_misses::cpu.dtb.walker 50 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.inst 16637 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.data 34998 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 51692 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu.data 1514 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 1514 # number of UpgradeReq misses
< system.l2c.ReadExReq_misses::cpu.data 129215 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 129215 # number of ReadExReq misses
< system.l2c.demand_misses::cpu.dtb.walker 50 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.inst 16637 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.data 164213 # number of demand (read+write) misses
< system.l2c.demand_misses::total 180907 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu.dtb.walker 50 # number of overall misses
< system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses
< system.l2c.overall_misses::cpu.inst 16637 # number of overall misses
< system.l2c.overall_misses::cpu.data 164213 # number of overall misses
< system.l2c.overall_misses::total 180907 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2626500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.inst 883116000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.data 1863608490 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 2749714990 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu.data 39367500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 39367500 # number of UpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu.data 6737631498 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 6737631498 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu.dtb.walker 2626500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.inst 883116000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.data 8601239988 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 9487346488 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu.dtb.walker 2626500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.inst 883116000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.data 8601239988 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 9487346488 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu.dtb.walker 110065 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.itb.walker 8886 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.inst 1072358 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.data 1381081 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2572390 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 1613450 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 1613450 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu.data 1843 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 1843 # number of UpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu.data 293028 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 293028 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu.dtb.walker 110065 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.itb.walker 8886 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.inst 1072358 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.data 1674109 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2865418 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu.dtb.walker 110065 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.itb.walker 8886 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.inst 1072358 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.data 1674109 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2865418 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000454 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000788 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.inst 0.015514 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.data 0.025341 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.020095 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu.data 0.821487 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.821487 # miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu.data 0.440965 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.440965 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu.dtb.walker 0.000454 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.itb.walker 0.000788 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.inst 0.015514 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.data 0.098090 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.063135 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu.dtb.walker 0.000454 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.itb.walker 0.000788 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.inst 0.015514 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.data 0.098090 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.063135 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52530 # average ReadReq miss latency
---
> system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu.inst 0.051463 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu.data 0.172766 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.989442 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu.dtb.walker 110667 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.itb.walker 8396 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.inst 1054432 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.data 1345104 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 2518599 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 1613189 # number of Writeback hits
> system.l2c.Writeback_hits::total 1613189 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits
> system.l2c.ReadExReq_hits::cpu.data 163997 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 163997 # number of ReadExReq hits
> system.l2c.demand_hits::cpu.dtb.walker 110667 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.itb.walker 8396 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.inst 1054432 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.data 1509101 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2682596 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu.dtb.walker 110667 # number of overall hits
> system.l2c.overall_hits::cpu.itb.walker 8396 # number of overall hits
> system.l2c.overall_hits::cpu.inst 1054432 # number of overall hits
> system.l2c.overall_hits::cpu.data 1509101 # number of overall hits
> system.l2c.overall_hits::total 2682596 # number of overall hits
> system.l2c.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.inst 16686 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.data 35012 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 51759 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu.data 1516 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 1516 # number of UpgradeReq misses
> system.l2c.ReadExReq_misses::cpu.data 128839 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 128839 # number of ReadExReq misses
> system.l2c.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.inst 16686 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.data 163851 # number of demand (read+write) misses
> system.l2c.demand_misses::total 180598 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu.dtb.walker 55 # number of overall misses
> system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses
> system.l2c.overall_misses::cpu.inst 16686 # number of overall misses
> system.l2c.overall_misses::cpu.data 163851 # number of overall misses
> system.l2c.overall_misses::total 180598 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2907000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu.itb.walker 312000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu.inst 885914499 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu.data 1865182494 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 2754315993 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu.data 39171500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 39171500 # number of UpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu.data 6715513999 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 6715513999 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu.dtb.walker 2907000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu.itb.walker 312000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu.inst 885914499 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu.data 8580696493 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 9469829992 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu.dtb.walker 2907000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu.itb.walker 312000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu.inst 885914499 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu.data 8580696493 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 9469829992 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu.dtb.walker 110722 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.itb.walker 8402 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.inst 1071118 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.data 1380116 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2570358 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 1613189 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 1613189 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu.data 1853 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 1853 # number of UpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu.data 292836 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 292836 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu.dtb.walker 110722 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.itb.walker 8402 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.inst 1071118 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.data 1672952 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2863194 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu.dtb.walker 110722 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.itb.walker 8402 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.inst 1071118 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.data 1672952 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2863194 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000497 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000714 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.inst 0.015578 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.data 0.025369 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.020137 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu.data 0.818133 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.818133 # miss rate for UpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu.data 0.439970 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.439970 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu.dtb.walker 0.000497 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.itb.walker 0.000714 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.inst 0.015578 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.data 0.097941 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.063076 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu.dtb.walker 0.000497 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.itb.walker 0.000714 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.inst 0.015578 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.data 0.097941 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.063076 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52854.545455 # average ReadReq miss latency
167,174c167,174
< system.l2c.ReadReq_avg_miss_latency::cpu.inst 53081.444972 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.data 53248.999657 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 53194.207808 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu.data 26002.311757 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 26002.311757 # average UpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu.data 52142.796873 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 52142.796873 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52530 # average overall miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu.inst 53093.281733 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu.data 53272.663487 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 53214.242798 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25838.720317 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 25838.720317 # average UpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.301167 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 52123.301167 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency
176,179c176,179
< system.l2c.demand_avg_miss_latency::cpu.inst 53081.444972 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.data 52378.557045 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 52443.224906 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52530 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 52435.962702 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency
181,183c181,183
< system.l2c.overall_avg_miss_latency::cpu.inst 53081.444972 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.data 52378.557045 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 52443.224906 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 52435.962702 # average overall miss latency
192,194c192,194
< system.l2c.writebacks::writebacks 96778 # number of writebacks
< system.l2c.writebacks::total 96778 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
---
> system.l2c.writebacks::writebacks 96993 # number of writebacks
> system.l2c.writebacks::total 96993 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
196,197c196,197
< system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
---
> system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
199,200c199,200
< system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
---
> system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
202,266c202,266
< system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 50 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.inst 16635 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.data 34997 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 51689 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu.data 1514 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 1514 # number of UpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu.data 129215 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 129215 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu.dtb.walker 50 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.inst 16635 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.data 164212 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 180904 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu.dtb.walker 50 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.inst 16635 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.data 164212 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 180904 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2020500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.inst 680227000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.data 1435916999 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 2118444499 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 60967500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 60967500 # number of UpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5181066001 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 5181066001 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2020500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.inst 680227000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.data 6616983000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 7299510500 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2020500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.inst 680227000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.data 6616983000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 7299510500 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59191869564 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 59191869564 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211082000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 1211082000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu.data 60402951564 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 60402951564 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025340 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.020094 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.821487 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.821487 # mshr miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.440965 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.440965 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.data 0.098089 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.063134 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.data 0.098089 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.063134 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average ReadReq mshr miss latency
---
> system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu.inst 16685 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu.data 35011 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 51757 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu.data 1516 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 1516 # number of UpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu.data 128839 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 128839 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu.inst 16685 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu.data 163850 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 180596 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu.inst 16685 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu.data 163850 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 180596 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2241000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu.inst 682427500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu.data 1437356500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 2122265000 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 61068000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 61068000 # number of UpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5163609501 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 5163609501 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2241000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu.inst 682427500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu.data 6600966001 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 7285874501 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2241000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu.inst 682427500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu.data 6600966001 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 7285874501 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192209064 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 59192209064 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211526000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 1211526000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu.data 60403735064 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 60403735064 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818133 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.818133 # mshr miss rate for UpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.439970 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.439970 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.063075 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.063075 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average ReadReq mshr miss latency
268,275c268,275
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40891.313496 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41029.716804 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 40984.435741 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40269.154557 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40269.154557 # average UpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40096.474875 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40096.474875 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40900.659275 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41054.425752 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 41004.405201 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40282.321900 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40282.321900 # average UpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.000458 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.000458 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency
277,280c277,280
< system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency
282,284c282,284
< system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency
292,293c292,293
< system.iocache.replacements 47568 # number of replacements
< system.iocache.tagsinuse 0.202980 # Cycle average of tags in use
---
> system.iocache.replacements 47565 # number of replacements
> system.iocache.tagsinuse 0.200108 # Cycle average of tags in use
295c295
< system.iocache.sampled_refs 47584 # Sample count of references to valid blocks.
---
> system.iocache.sampled_refs 47581 # Sample count of references to valid blocks.
297,302c297,302
< system.iocache.warmup_cycle 5000598826000 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::pc.south_bridge.ide 0.202980 # Average occupied blocks per requestor
< system.iocache.occ_percent::pc.south_bridge.ide 0.012686 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.012686 # Average percentage of cache occupancy
< system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
---
> system.iocache.warmup_cycle 5000599162000 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::pc.south_bridge.ide 0.200108 # Average occupied blocks per requestor
> system.iocache.occ_percent::pc.south_bridge.ide 0.012507 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.012507 # Average percentage of cache occupancy
> system.iocache.ReadReq_misses::pc.south_bridge.ide 900 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 900 # number of ReadReq misses
305,318c305,318
< system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
< system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
< system.iocache.overall_misses::total 47623 # number of overall misses
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135810932 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 135810932 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6905757160 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 6905757160 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 7041568092 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 7041568092 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 7041568092 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 7041568092 # number of overall miss cycles
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::pc.south_bridge.ide 47620 # number of demand (read+write) misses
> system.iocache.demand_misses::total 47620 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 47620 # number of overall misses
> system.iocache.overall_misses::total 47620 # number of overall misses
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135466932 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 135466932 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6926961160 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 6926961160 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 7062428092 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 7062428092 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 7062428092 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 7062428092 # number of overall miss cycles
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 900 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 900 # number of ReadReq accesses(hits+misses)
321,324c321,324
< system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 47620 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 47620 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 47620 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 47620 # number of overall (read+write) accesses
333,340c333,340
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150399.703212 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 150399.703212 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147811.583048 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 147811.583048 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 147860.657497 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 147860.657497 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150518.813333 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 150518.813333 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148265.435788 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 148265.435788 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 148308.023772 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 148308.023772 # average overall miss latency
351,352c351,352
< system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 903 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 903 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 900 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 900 # number of ReadReq MSHR misses
355,366c355,366
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 47623 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 47623 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 47623 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 47623 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88823000 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 88823000 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4476002926 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 4476002926 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4564825926 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 4564825926 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4564825926 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 4564825926 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 47620 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 47620 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 47620 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 47620 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88635000 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 88635000 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4497207944 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 4497207944 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 4585842944 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 4585842944 # number of overall MSHR miss cycles
375,382c375,382
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98364.341085 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 98364.341085 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95804.857149 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 95804.857149 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98483.333333 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 98483.333333 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96258.731678 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 96258.731678 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency
396c396
< system.cpu.numCycles 473010428 # number of cpu cycles simulated
---
> system.cpu.numCycles 472946175 # number of cpu cycles simulated
399,403c399,403
< system.cpu.BPredUnit.lookups 90027775 # Number of BP lookups
< system.cpu.BPredUnit.condPredicted 90027775 # Number of conditional branches predicted
< system.cpu.BPredUnit.condIncorrect 1176793 # Number of conditional branches incorrect
< system.cpu.BPredUnit.BTBLookups 84224638 # Number of BTB lookups
< system.cpu.BPredUnit.BTBHits 81706962 # Number of BTB hits
---
> system.cpu.BPredUnit.lookups 90027772 # Number of BP lookups
> system.cpu.BPredUnit.condPredicted 90027772 # Number of conditional branches predicted
> system.cpu.BPredUnit.condIncorrect 1176455 # Number of conditional branches incorrect
> system.cpu.BPredUnit.BTBLookups 84282590 # Number of BTB lookups
> system.cpu.BPredUnit.BTBHits 81704922 # Number of BTB hits
407,423c407,423
< system.cpu.fetch.icacheStallCycles 31360026 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 446936699 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 90027775 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 81706962 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 169789390 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 5321789 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 167863 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.BlockedCycles 104601282 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 37271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 44086 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 9371006 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 537925 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 5262 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 310106612 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.836098 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.376721 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 31264026 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 446943348 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 90027772 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 81704922 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 169792009 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 5327046 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 167003 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.BlockedCycles 104616235 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 37821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 45804 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 9365381 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 539972 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5058 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 310035010 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.836765 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.376817 # Number of instructions fetched each cycle (Total)
425,433c425,433
< system.cpu.fetch.rateDist::0 140752877 45.39% 45.39% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1771842 0.57% 45.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 72784841 23.47% 69.43% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 985545 0.32% 69.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 1639332 0.53% 70.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 3672529 1.18% 71.46% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 1138013 0.37% 71.83% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1446532 0.47% 72.29% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 85915101 27.71% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 140677603 45.37% 45.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1773611 0.57% 45.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 72784877 23.48% 69.42% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 988899 0.32% 69.74% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 1639325 0.53% 70.27% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 3670845 1.18% 71.45% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 1138945 0.37% 71.82% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1446155 0.47% 72.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 85914750 27.71% 100.00% # Number of instructions fetched each cycle (Total)
437,480c437,480
< system.cpu.fetch.rateDist::total 310106612 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.190329 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.944877 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 36504487 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 100689087 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 164100014 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 4706777 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 4106247 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 876222772 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 974 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 4106247 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 40918052 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 44290154 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 10988643 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 163783570 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 46019946 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 872439032 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 9880 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 35250675 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 3950071 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 31995010 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 1394183444 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2488413838 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 2488413278 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 1347594272 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 46589165 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 469708 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 477213 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 48119615 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 18916713 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 10445823 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1292985 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1005726 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 865744936 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1721292 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 864337925 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 123293 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 26001434 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 53514506 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 205573 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 310106612 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.787228 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.396179 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 310035010 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.190355 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.945019 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 36438516 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 100672732 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 164105371 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 4706760 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 4111631 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 876235114 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 4111631 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 40855551 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 44279722 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 10981847 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 163785428 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 46020831 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 872430616 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 10252 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 35253394 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 3952381 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 31994944 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 1394146617 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2488353855 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 2488353319 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 1347546781 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 46599829 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 470336 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 478135 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 48126988 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 18909339 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 10455877 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1294020 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1017517 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 865756561 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1721302 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 864328719 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 124616 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 26046990 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 53600910 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 205527 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 310035010 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.787842 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 2.396151 # Number of insts issued each cycle
482,490c482,490
< system.cpu.iq.issued_per_cycle::0 102391332 33.02% 33.02% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 23760486 7.66% 40.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 19024925 6.13% 46.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7818761 2.52% 49.34% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 80618326 26.00% 75.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 3106091 1.00% 76.34% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 72752494 23.46% 99.80% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 520993 0.17% 99.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 113204 0.04% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 102334281 33.01% 33.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 23751530 7.66% 40.67% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 19011662 6.13% 46.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7830278 2.53% 49.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 80611792 26.00% 75.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 3104970 1.00% 76.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 72755101 23.47% 99.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 522761 0.17% 99.96% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 112635 0.04% 100.00% # Number of insts issued each cycle
494c494
< system.cpu.iq.issued_per_cycle::total 310106612 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 310035010 # Number of insts issued each cycle
496,526c496,526
< system.cpu.iq.fu_full::IntAlu 162823 7.80% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 1765220 84.55% 92.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 159742 7.65% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 164564 7.88% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 1763434 84.48% 92.37% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 159280 7.63% 100.00% # attempts to use FU when none available
529,530c529,530
< system.cpu.iq.FU_type_0::No_OpClass 296671 0.03% 0.03% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 829442170 95.96% 96.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 297202 0.03% 0.03% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 829439322 95.96% 96.00% # Type of FU issued
559,560c559,560
< system.cpu.iq.FU_type_0::MemRead 25162510 2.91% 98.91% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 9436574 1.09% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 25154463 2.91% 98.91% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 9437732 1.09% 100.00% # Type of FU issued
563,565c563,565
< system.cpu.iq.FU_type_0::total 864337925 # Type of FU issued
< system.cpu.iq.rate 1.827313 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 2087785 # FU busy when requested
---
> system.cpu.iq.FU_type_0::total 864328719 # Type of FU issued
> system.cpu.iq.rate 1.827541 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 2087278 # FU busy when requested
567,575c567,575
< system.cpu.iq.int_inst_queue_reads 2041131934 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 893478671 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 853934886 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 866128931 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1577690 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.int_inst_queue_reads 2041042185 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 893535851 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 853927067 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 866118699 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 96 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1579181 # Number of loads that had data forwarded from stores
577,580c577,580
< system.cpu.iew.lsq.thread0.squashedLoads 3621025 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 20103 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 12189 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 2042088 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 3618734 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 20083 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 12084 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 2054359 # Number of stores squashed
583,584c583,584
< system.cpu.iew.lsq.thread0.rescheduledLoads 7821421 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 4286 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 7821519 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 4487 # Number of times an access to memory failed due to the cache being blocked
586,602c586,602
< system.cpu.iew.iewSquashCycles 4106247 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 27916479 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1927801 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 867466228 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 303428 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 18916713 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 10445834 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 882766 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 975199 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 12189 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 699297 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 625213 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1324510 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 862446659 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 24735217 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1891265 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 4111631 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 27910035 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1927143 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 867477863 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 297836 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 18909339 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 10455877 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 883178 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 975186 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 15536 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 12084 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 697834 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 626380 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1324214 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 862437508 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 24726867 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1891210 # Number of squashed instructions skipped in execute
605,612c605,612
< system.cpu.iew.exec_refs 33929559 # number of memory reference insts executed
< system.cpu.iew.exec_branches 86496146 # Number of branches executed
< system.cpu.iew.exec_stores 9194342 # Number of stores executed
< system.cpu.iew.exec_rate 1.823314 # Inst execution rate
< system.cpu.iew.wb_sent 861961974 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 853934949 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 669649521 # num instructions producing a value
< system.cpu.iew.wb_consumers 1918783501 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 33920253 # number of memory reference insts executed
> system.cpu.iew.exec_branches 86495383 # Number of branches executed
> system.cpu.iew.exec_stores 9193386 # Number of stores executed
> system.cpu.iew.exec_rate 1.823543 # Inst execution rate
> system.cpu.iew.wb_sent 861952908 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 853927121 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 669642895 # num instructions producing a value
> system.cpu.iew.wb_consumers 1918737755 # num instructions consuming a value
614,615c614,615
< system.cpu.iew.wb_rate 1.805319 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.348997 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.805548 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.349002 # average fanout of values written-back
617,624c617,624
< system.cpu.commit.commitCommittedInsts 426531587 # The number of committed instructions
< system.cpu.commit.commitCommittedOps 840543055 # The number of committed instructions
< system.cpu.commit.commitSquashedInsts 26818803 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1515717 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 1181719 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 306015924 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 2.746730 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.861261 # Number of insts commited each cycle
---
> system.cpu.commit.commitCommittedInsts 426515724 # The number of committed instructions
> system.cpu.commit.commitCommittedOps 840516219 # The number of committed instructions
> system.cpu.commit.commitSquashedInsts 26857823 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1515773 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 1181578 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 305938932 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 2.747333 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.861326 # Number of insts commited each cycle
626,634c626,634
< system.cpu.commit.committed_per_cycle::0 125070317 40.87% 40.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 14726015 4.81% 45.68% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4257326 1.39% 47.07% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 76646045 25.05% 72.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 3895754 1.27% 73.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1793252 0.59% 73.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1102852 0.36% 74.34% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 71997039 23.53% 97.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 6527324 2.13% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 125006118 40.86% 40.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 14720749 4.81% 45.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4254060 1.39% 47.06% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 76641454 25.05% 72.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 3896789 1.27% 73.39% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1794252 0.59% 73.97% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1101361 0.36% 74.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 71996786 23.53% 97.87% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 6527363 2.13% 100.00% # Number of insts commited each cycle
638,640c638,640
< system.cpu.commit.committed_per_cycle::total 306015924 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 426531587 # Number of instructions committed
< system.cpu.commit.committedOps 840543055 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 305938932 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 426515724 # Number of instructions committed
> system.cpu.commit.committedOps 840516219 # Number of ops (including micro ops) committed
642,645c642,645
< system.cpu.commit.refs 23699431 # Number of memory references committed
< system.cpu.commit.loads 15295685 # Number of loads committed
< system.cpu.commit.membars 781577 # Number of memory barriers committed
< system.cpu.commit.branches 85508404 # Number of branches committed
---
> system.cpu.commit.refs 23692120 # Number of memory references committed
> system.cpu.commit.loads 15290602 # Number of loads committed
> system.cpu.commit.membars 781565 # Number of memory barriers committed
> system.cpu.commit.branches 85505775 # Number of branches committed
647c647
< system.cpu.commit.int_insts 768361520 # Number of committed integer instructions.
---
> system.cpu.commit.int_insts 768334838 # Number of committed integer instructions.
649c649
< system.cpu.commit.bw_lim_events 6527324 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 6527363 # number cycles where commit BW limit reached
651,713c651,713
< system.cpu.rob.rob_reads 1166770942 # The number of ROB reads
< system.cpu.rob.rob_writes 1738844954 # The number of ROB writes
< system.cpu.timesIdled 2997386 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 162903816 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 9874668492 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 426531587 # Number of Instructions Simulated
< system.cpu.committedOps 840543055 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 426531587 # Number of Instructions Simulated
< system.cpu.cpi 1.108969 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.108969 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.901738 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.901738 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 2163215430 # number of integer regfile reads
< system.cpu.int_regfile_writes 1362691420 # number of integer regfile writes
< system.cpu.fp_regfile_reads 63 # number of floating regfile reads
< system.cpu.misc_regfile_reads 281069935 # number of misc regfile reads
< system.cpu.misc_regfile_writes 403791 # number of misc regfile writes
< system.cpu.icache.replacements 1071897 # number of replacements
< system.cpu.icache.tagsinuse 510.429584 # Cycle average of tags in use
< system.cpu.icache.total_refs 8228054 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 1072409 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 7.672496 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 56932855000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 510.429584 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.996933 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.996933 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 8228054 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 8228054 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 8228054 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 8228054 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 8228054 # number of overall hits
< system.cpu.icache.overall_hits::total 8228054 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1142948 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1142948 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1142948 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1142948 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1142948 # number of overall misses
< system.cpu.icache.overall_misses::total 1142948 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 18865193488 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 18865193488 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 18865193488 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 18865193488 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 18865193488 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 18865193488 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 9371002 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 9371002 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 9371002 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 9371002 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 9371002 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 9371002 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121966 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.121966 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.121966 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.121966 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.121966 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.121966 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16505.732096 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 16505.732096 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 16505.732096 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 16505.732096 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 3301994 # number of cycles access was blocked
---
> system.cpu.rob.rob_reads 1166706140 # The number of ROB reads
> system.cpu.rob.rob_writes 1738874776 # The number of ROB writes
> system.cpu.timesIdled 2996123 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 162911165 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 9872855838 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 426515724 # Number of Instructions Simulated
> system.cpu.committedOps 840516219 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 426515724 # Number of Instructions Simulated
> system.cpu.cpi 1.108860 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.108860 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.901827 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.901827 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 2163141042 # number of integer regfile reads
> system.cpu.int_regfile_writes 1362663536 # number of integer regfile writes
> system.cpu.fp_regfile_reads 54 # number of floating regfile reads
> system.cpu.misc_regfile_reads 281062978 # number of misc regfile reads
> system.cpu.misc_regfile_writes 403820 # number of misc regfile writes
> system.cpu.icache.replacements 1070658 # number of replacements
> system.cpu.icache.tagsinuse 510.425099 # Cycle average of tags in use
> system.cpu.icache.total_refs 8224431 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 1071170 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 7.677989 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 56932899000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 510.425099 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.996924 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.996924 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 8224431 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 8224431 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 8224431 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 8224431 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 8224431 # number of overall hits
> system.cpu.icache.overall_hits::total 8224431 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1140947 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1140947 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1140947 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1140947 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1140947 # number of overall misses
> system.cpu.icache.overall_misses::total 1140947 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 18841256486 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 18841256486 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 18841256486 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 18841256486 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 18841256486 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 18841256486 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 9365378 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 9365378 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 9365378 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 9365378 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 9365378 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 9365378 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121826 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.121826 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.121826 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.121826 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.121826 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.121826 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16513.700011 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 16513.700011 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 16513.700011 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 16513.700011 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 3271992 # number of cycles access was blocked
717c717
< system.cpu.icache.avg_blocked_cycles::no_mshrs 8275.674185 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 8200.481203 # average number of cycles each access was blocked
721,752c721,752
< system.cpu.icache.writebacks::writebacks 1600 # number of writebacks
< system.cpu.icache.writebacks::total 1600 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70415 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 70415 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 70415 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 70415 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 70415 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 70415 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072533 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1072533 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1072533 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1072533 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1072533 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1072533 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14734319994 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 14734319994 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14734319994 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 14734319994 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14734319994 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 14734319994 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114452 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.114452 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.114452 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13737.870997 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13737.870997 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency
---
> system.cpu.icache.writebacks::writebacks 1605 # number of writebacks
> system.cpu.icache.writebacks::total 1605 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69655 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 69655 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 69655 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 69655 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 69655 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 69655 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071292 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1071292 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1071292 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1071292 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1071292 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1071292 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14719464992 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14719464992 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14719464992 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14719464992 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14719464992 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14719464992 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114389 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.114389 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.114389 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13739.918708 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13739.918708 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency
754,764c754,764
< system.cpu.itb_walker_cache.replacements 11177 # number of replacements
< system.cpu.itb_walker_cache.tagsinuse 6.030365 # Cycle average of tags in use
< system.cpu.itb_walker_cache.total_refs 31227 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.sampled_refs 11191 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.avg_refs 2.790367 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.warmup_cycle 5136145388000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.030365 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376898 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.occ_percent::total 0.376898 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31228 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 31228 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.replacements 10504 # number of replacements
> system.cpu.itb_walker_cache.tagsinuse 6.031363 # Cycle average of tags in use
> system.cpu.itb_walker_cache.total_refs 31807 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.sampled_refs 10516 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.avg_refs 3.024629 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.warmup_cycle 5135227037000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.031363 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376960 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.occ_percent::total 0.376960 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31848 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 31848 # number of ReadReq hits
767,784c767,784
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31231 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 31231 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31231 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 31231 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12057 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 12057 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12057 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 12057 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12057 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 12057 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 192652500 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 192652500 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 192652500 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 192652500 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 192652500 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 192652500 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43285 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 43285 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31851 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 31851 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31851 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 31851 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11386 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 11386 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11386 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 11386 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11386 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 11386 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 182254500 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 182254500 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 182254500 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 182254500 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 182254500 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 182254500 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43234 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 43234 # number of ReadReq accesses(hits+misses)
787,802c787,802
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43288 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 43288 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43288 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 43288 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.278549 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.278549 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.278530 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.278530 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.278530 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.278530 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 15978.477233 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 15978.477233 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 15978.477233 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 15978.477233 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43237 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 43237 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43237 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 43237 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.263358 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.263358 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.263339 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.263339 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.263339 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.263339 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16006.894432 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16006.894432 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16006.894432 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16006.894432 # average overall miss latency
811,836c811,836
< system.cpu.itb_walker_cache.writebacks::writebacks 1620 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 1620 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12057 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12057 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12057 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 12057 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12057 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 12057 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155859527 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155859527 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155859527 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155859527 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155859527 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155859527 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.278549 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.278549 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.278530 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.278530 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12926.891184 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 1641 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 1641 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11386 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11386 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11386 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 11386 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11386 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 11386 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147453030 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147453030 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147453030 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147453030 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147453030 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147453030 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.263358 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.263358 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.263339 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.263339 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12950.380292 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency
838,882c838,882
< system.cpu.dtb_walker_cache.replacements 116226 # number of replacements
< system.cpu.dtb_walker_cache.tagsinuse 12.942586 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.total_refs 138119 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.sampled_refs 116242 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.avg_refs 1.188202 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.warmup_cycle 5112881220000 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942586 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808912 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.occ_percent::total 0.808912 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138119 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 138119 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138119 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 138119 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138119 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 138119 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117277 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 117277 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117277 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 117277 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117277 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 117277 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2115105000 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2115105000 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2115105000 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 2115105000 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2115105000 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 2115105000 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255396 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 255396 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255396 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 255396 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255396 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 255396 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.459197 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.459197 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.459197 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.459197 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.459197 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.459197 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18035.121976 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18035.121976 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18035.121976 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18035.121976 # average overall miss latency
---
> system.cpu.dtb_walker_cache.replacements 117278 # number of replacements
> system.cpu.dtb_walker_cache.tagsinuse 13.523999 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.total_refs 136775 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.sampled_refs 117293 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.avg_refs 1.166097 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.warmup_cycle 5112876101000 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.523999 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.845250 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.occ_percent::total 0.845250 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 136779 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 136779 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 136779 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 136779 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 136779 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 136779 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 118304 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 118304 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 118304 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 118304 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 118304 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 118304 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2123660000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2123660000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2123660000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 2123660000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2123660000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 2123660000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255083 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 255083 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255083 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 255083 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255083 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 255083 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463786 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463786 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463786 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463786 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463786 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463786 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17950.872329 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17950.872329 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17950.872329 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17950.872329 # average overall miss latency
891,916c891,916
< system.cpu.dtb_walker_cache.writebacks::writebacks 36600 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 36600 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117277 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117277 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117277 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 117277 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117277 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 117277 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1760668506 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1760668506 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1760668506 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.459197 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.459197 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.459197 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15012.905395 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 37674 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 37674 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118304 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118304 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118304 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 118304 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 118304 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 118304 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1766049009 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1766049009 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1766049009 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463786 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463786 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463786 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14928.058299 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency
918,922c918,922
< system.cpu.dcache.replacements 1674194 # number of replacements
< system.cpu.dcache.tagsinuse 511.997520 # Cycle average of tags in use
< system.cpu.dcache.total_refs 19015880 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1674706 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 11.354757 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 1673136 # number of replacements
> system.cpu.dcache.tagsinuse 511.997556 # Cycle average of tags in use
> system.cpu.dcache.total_refs 19006106 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1673648 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 11.356095 # Average number of references to valid blocks.
924c924
< system.cpu.dcache.occ_blocks::cpu.data 511.997520 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 511.997556 # Average occupied blocks per requestor
927,975c927,975
< system.cpu.dcache.ReadReq_hits::cpu.data 10936415 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 10936415 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8076863 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8076863 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 19013278 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 19013278 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 19013278 # number of overall hits
< system.cpu.dcache.overall_hits::total 19013278 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 2432524 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 2432524 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 317516 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 317516 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 2750040 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2750040 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2750040 # number of overall misses
< system.cpu.dcache.overall_misses::total 2750040 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 45245018000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 45245018000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10626959991 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10626959991 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 55871977991 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 55871977991 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 55871977991 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 55871977991 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13368939 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13368939 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8394379 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8394379 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21763318 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21763318 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21763318 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21763318 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181953 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.181953 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037825 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.037825 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.126361 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.126361 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.126361 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.126361 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18600.029434 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 18600.029434 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33469.053500 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 33469.053500 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.787389 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 20316.787389 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.787389 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 20316.787389 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 26625491 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_hits::cpu.data 10928708 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 10928708 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8074811 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8074811 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 19003519 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 19003519 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 19003519 # number of overall hits
> system.cpu.dcache.overall_hits::total 19003519 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 2430538 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 2430538 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 317333 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 317333 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 2747871 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2747871 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2747871 # number of overall misses
> system.cpu.dcache.overall_misses::total 2747871 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 45186101000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 45186101000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10603069990 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10603069990 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 55789170990 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 55789170990 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 55789170990 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 55789170990 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 13359246 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13359246 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8392144 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8392144 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21751390 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21751390 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21751390 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21751390 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181937 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.181937 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.126331 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.126331 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.126331 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.126331 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18590.987263 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 18590.987263 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33413.070781 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33413.070781 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 20302.689242 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 20302.689242 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 27875990 # number of cycles access was blocked
977c977
< system.cpu.dcache.blocked::no_mshrs 4915 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 4957 # number of cycles access was blocked
979c979
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 5417.190437 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 5623.560621 # average number of cycles each access was blocked
983,1030c983,1030
< system.cpu.dcache.writebacks::writebacks 1573630 # number of writebacks
< system.cpu.dcache.writebacks::total 1573630 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1050273 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1050273 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22706 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 22706 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1072979 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1072979 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1072979 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1072979 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1382251 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1382251 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294810 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 294810 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1677061 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1677061 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1677061 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1677061 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23310362534 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 23310362534 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9362745997 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 9362745997 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32673108531 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 32673108531 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32673108531 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 32673108531 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207340500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207340500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386118500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386118500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86593459000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 86593459000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103393 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103393 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035120 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035120 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.077059 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.077059 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16864.059085 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16864.059085 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31758.576700 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31758.576700 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 1572269 # number of writebacks
> system.cpu.dcache.writebacks::total 1572269 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049151 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1049151 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22726 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 22726 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1071877 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1071877 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1071877 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1071877 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381387 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1381387 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294607 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 294607 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1675994 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1675994 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1675994 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1675994 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23290713035 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 23290713035 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9337845997 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 9337845997 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32628559032 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 32628559032 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32628559032 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 32628559032 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207723000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207723000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386731000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386731000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594454000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594454000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103403 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103403 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035105 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035105 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.077052 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.077052 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16860.382380 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16860.382380 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31695.940684 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31695.940684 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency