7,11c7,11
< host_inst_rate 128842 # Simulator instruction rate (inst/s)
< host_op_rate 253899 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1558019011 # Simulator tick rate (ticks/s)
< host_mem_usage 389972 # Number of bytes of host memory used
< host_seconds 3310.30 # Real time elapsed on the host
---
> host_inst_rate 123762 # Simulator instruction rate (inst/s)
> host_op_rate 243888 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1496586873 # Simulator tick rate (ticks/s)
> host_mem_usage 369148 # Number of bytes of host memory used
> host_seconds 3446.18 # Real time elapsed on the host
14,23c14,48
< system.physmem.bytes_read 15959488 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 1257664 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 12050112 # Number of bytes written to this memory
< system.physmem.num_reads 249367 # Number of read requests responded to by this memory
< system.physmem.num_writes 188283 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 3094415 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 243851 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 2336419 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 5430833 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory
> system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory
> system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s)
124a150
> system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses
125a152
> system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses
126a154
> system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses
130a159
> system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses
134a164
> system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses
138a169
> system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency
139a171
> system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency
140a173
> system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency
144a178
> system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency
148a183
> system.l2c.overall_avg_miss_latency::total 52201.292100 # average overall miss latency
215a251
> system.l2c.ReadReq_mshr_miss_rate::total 0.025337 # mshr miss rate for ReadReq accesses
216a253
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.882394 # mshr miss rate for UpgradeReq accesses
217a255
> system.l2c.ReadExReq_mshr_miss_rate::total 0.481904 # mshr miss rate for ReadExReq accesses
221a260
> system.l2c.demand_mshr_miss_rate::total 0.071838 # mshr miss rate for demand accesses
225a265
> system.l2c.overall_mshr_miss_rate::total 0.071838 # mshr miss rate for overall accesses
229a270
> system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency
230a272
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency
231a274
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency
235a279
> system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency
239a284
> system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency
240a286
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
241a288
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
242a290
> system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
277a326
> system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
278a328
> system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
279a330
> system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
280a332
> system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
281a334
> system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency
282a336
> system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency
283a338
> system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency
284a340
> system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency
311a368
> system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
312a370
> system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
313a372
> system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
314a374
> system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
315a376
> system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency
316a378
> system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency
317a380
> system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency
318a382
> system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency
637a702
> system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses
638a704
> system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses
639a706
> system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses
640a708
> system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency
641a710
> system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency
642a712
> system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency
671a742
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115814 # mshr miss rate for ReadReq accesses
672a744
> system.cpu.icache.demand_mshr_miss_rate::total 0.115814 # mshr miss rate for demand accesses
673a746
> system.cpu.icache.overall_mshr_miss_rate::total 0.115814 # mshr miss rate for overall accesses
674a748
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282 # average ReadReq mshr miss latency
675a750
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency
676a752
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency
715a792
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298946 # miss rate for ReadReq accesses
716a794
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.298923 # miss rate for demand accesses
717a796
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.298923 # miss rate for overall accesses
718a798
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308 # average ReadReq miss latency
719a800
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308 # average overall miss latency
720a802
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308 # average overall miss latency
743a826
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses
744a828
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses
745a830
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses
746a832
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency
747a834
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency
748a836
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency
783a872
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses
784a874
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses
785a876
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses
786a878
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency
787a880
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency
788a882
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency
811a906
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses
812a908
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses
813a910
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses
814a912
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency
815a914
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency
816a916
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency
859a960
> system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses
860a962
> system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses
861a964
> system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses
862a966
> system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses
863a968
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency
864a970
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency
865a972
> system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency
866a974
> system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency
907a1016
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses
908a1018
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses
909a1020
> system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses
910a1022
> system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses
911a1024
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency
912a1026
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency
913a1028
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency
914a1030
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency
915a1032
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
916a1034
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
917a1036
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< host_inst_rate 128842 # Simulator instruction rate (inst/s)
< host_op_rate 253899 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1558019011 # Simulator tick rate (ticks/s)
< host_mem_usage 389972 # Number of bytes of host memory used
< host_seconds 3310.30 # Real time elapsed on the host
---
> host_inst_rate 123762 # Simulator instruction rate (inst/s)
> host_op_rate 243888 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1496586873 # Simulator tick rate (ticks/s)
> host_mem_usage 369148 # Number of bytes of host memory used
> host_seconds 3446.18 # Real time elapsed on the host
14,23c14,48
< system.physmem.bytes_read 15959488 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 1257664 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 12050112 # Number of bytes written to this memory
< system.physmem.num_reads 249367 # Number of read requests responded to by this memory
< system.physmem.num_writes 188283 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 3094415 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 243851 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 2336419 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 5430833 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory
> system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory
> system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s)
124a150
> system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses
125a152
> system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses
126a154
> system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses
130a159
> system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses
134a164
> system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses
138a169
> system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency
139a171
> system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency
140a173
> system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency
144a178
> system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency
148a183
> system.l2c.overall_avg_miss_latency::total 52201.292100 # average overall miss latency
215a251
> system.l2c.ReadReq_mshr_miss_rate::total 0.025337 # mshr miss rate for ReadReq accesses
216a253
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.882394 # mshr miss rate for UpgradeReq accesses
217a255
> system.l2c.ReadExReq_mshr_miss_rate::total 0.481904 # mshr miss rate for ReadExReq accesses
221a260
> system.l2c.demand_mshr_miss_rate::total 0.071838 # mshr miss rate for demand accesses
225a265
> system.l2c.overall_mshr_miss_rate::total 0.071838 # mshr miss rate for overall accesses
229a270
> system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency
230a272
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency
231a274
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency
235a279
> system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency
239a284
> system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency
240a286
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
241a288
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
242a290
> system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
277a326
> system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
278a328
> system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
279a330
> system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
280a332
> system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
281a334
> system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency
282a336
> system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency
283a338
> system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency
284a340
> system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency
311a368
> system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
312a370
> system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
313a372
> system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
314a374
> system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
315a376
> system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency
316a378
> system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency
317a380
> system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency
318a382
> system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency
637a702
> system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses
638a704
> system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses
639a706
> system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses
640a708
> system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency
641a710
> system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency
642a712
> system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency
671a742
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115814 # mshr miss rate for ReadReq accesses
672a744
> system.cpu.icache.demand_mshr_miss_rate::total 0.115814 # mshr miss rate for demand accesses
673a746
> system.cpu.icache.overall_mshr_miss_rate::total 0.115814 # mshr miss rate for overall accesses
674a748
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282 # average ReadReq mshr miss latency
675a750
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency
676a752
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency
715a792
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298946 # miss rate for ReadReq accesses
716a794
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.298923 # miss rate for demand accesses
717a796
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.298923 # miss rate for overall accesses
718a798
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308 # average ReadReq miss latency
719a800
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308 # average overall miss latency
720a802
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308 # average overall miss latency
743a826
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses
744a828
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses
745a830
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses
746a832
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency
747a834
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency
748a836
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency
783a872
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses
784a874
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses
785a876
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses
786a878
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency
787a880
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency
788a882
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency
811a906
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses
812a908
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses
813a910
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses
814a912
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency
815a914
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency
816a916
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency
859a960
> system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses
860a962
> system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses
861a964
> system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses
862a966
> system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses
863a968
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency
864a970
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency
865a972
> system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency
866a974
> system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency
907a1016
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses
908a1018
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses
909a1020
> system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses
910a1022
> system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses
911a1024
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency
912a1026
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency
913a1028
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency
914a1030
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency
915a1032
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
916a1034
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
917a1036
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency