7,11c7,11
< host_inst_rate 192642 # Simulator instruction rate (inst/s)
< host_op_rate 380808 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2470040631 # Simulator tick rate (ticks/s)
< host_mem_usage 757076 # Number of bytes of host memory used
< host_seconds 2117.71 # Real time elapsed on the host
---
> host_inst_rate 185450 # Simulator instruction rate (inst/s)
> host_op_rate 366593 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2377836678 # Simulator tick rate (ticks/s)
> host_mem_usage 757080 # Number of bytes of host memory used
> host_seconds 2199.83 # Real time elapsed on the host
701,702d700
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
741,744c739,740
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2788550500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2788550500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100905771500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 100905771500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 98117221000 # number of overall MSHR uncacheable cycles
767,771c763,764
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199552.776585 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199552.776585 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171769.123330 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171769.123330 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency
830,831d822
< system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
< system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
858d848
< system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
918,919d907
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
952d939
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1016,1017d1002
< system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
< system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1044d1028
< system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1205,1206d1188
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1269,1272c1251,1252
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2627781000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2627781000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93576407000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93576407000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles
1317,1321c1297,1298
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188047.874624 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188047.874624 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159292.547451 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159292.547451 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency
1494,1497c1471,1474
< system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
< system.iocache.demand_misses::total 907 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
< system.iocache.overall_misses::total 907 # number of overall misses
---
> system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
> system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
> system.iocache.overall_misses::total 47627 # number of overall misses
1502,1505c1479,1482
< system.iocache.demand_miss_latency::pc.south_bridge.ide 150838200 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 150838200 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 150838200 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 150838200 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles
1510,1513c1487,1490
< system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
1526,1529c1503,1506
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 166304.520397 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 166304.520397 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency
1536,1537d1512
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1544,1547c1519,1522
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
1552,1555c1527,1530
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 105488200 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 105488200 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles
1568,1572c1543,1546
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
< host_inst_rate 192642 # Simulator instruction rate (inst/s)
< host_op_rate 380808 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2470040631 # Simulator tick rate (ticks/s)
< host_mem_usage 757076 # Number of bytes of host memory used
< host_seconds 2117.71 # Real time elapsed on the host
---
> host_inst_rate 185450 # Simulator instruction rate (inst/s)
> host_op_rate 366593 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2377836678 # Simulator tick rate (ticks/s)
> host_mem_usage 757080 # Number of bytes of host memory used
> host_seconds 2199.83 # Real time elapsed on the host
701,702d700
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
741,744c739,740
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2788550500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2788550500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100905771500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 100905771500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 98117221000 # number of overall MSHR uncacheable cycles
767,771c763,764
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199552.776585 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199552.776585 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171769.123330 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171769.123330 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency
830,831d822
< system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
< system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
858d848
< system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
918,919d907
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
952d939
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1016,1017d1002
< system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
< system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1044d1028
< system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1205,1206d1188
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1269,1272c1251,1252
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2627781000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2627781000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93576407000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93576407000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles
1317,1321c1297,1298
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188047.874624 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188047.874624 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159292.547451 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159292.547451 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency
1494,1497c1471,1474
< system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
< system.iocache.demand_misses::total 907 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
< system.iocache.overall_misses::total 907 # number of overall misses
---
> system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
> system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
> system.iocache.overall_misses::total 47627 # number of overall misses
1502,1505c1479,1482
< system.iocache.demand_miss_latency::pc.south_bridge.ide 150838200 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 150838200 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 150838200 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 150838200 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles
1510,1513c1487,1490
< system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
1526,1529c1503,1506
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 166304.520397 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 166304.520397 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency
1536,1537d1512
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1544,1547c1519,1522
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
1552,1555c1527,1530
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 105488200 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 105488200 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles
1568,1572c1543,1546
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency