3,5c3,5
< sim_seconds 5.126140 # Number of seconds simulated
< sim_ticks 5126139641000 # Number of ticks simulated
< final_tick 5126139641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.144266 # Number of seconds simulated
> sim_ticks 5144265998000 # Number of ticks simulated
> final_tick 5144265998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 128755 # Simulator instruction rate (inst/s)
< host_op_rate 254500 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1618610313 # Simulator tick rate (ticks/s)
< host_mem_usage 809248 # Number of bytes of host memory used
< host_seconds 3167.00 # Real time elapsed on the host
< sim_insts 407767906 # Number of instructions simulated
< sim_ops 806002026 # Number of ops (including micro ops) simulated
---
> host_inst_rate 171354 # Simulator instruction rate (inst/s)
> host_op_rate 338701 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2161855241 # Simulator tick rate (ticks/s)
> host_mem_usage 817304 # Number of bytes of host memory used
> host_seconds 2379.56 # Real time elapsed on the host
> sim_insts 407746267 # Number of instructions simulated
> sim_ops 805959101 # Number of ops (including micro ops) simulated
16,19c16,19
< system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 1038720 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10766272 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1040896 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10728128 # Number of bytes read from this memory
21,29c21,29
< system.physmem.bytes_read::total 11837632 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1038720 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1038720 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9565696 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9565696 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 16230 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 168223 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 11801664 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1040896 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1040896 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9535488 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9535488 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 16264 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 167627 # Number of read requests responded to by this memory
31,60c31,60
< system.physmem.num_reads::total 184963 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 149464 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 149464 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 202632 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2100269 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2309268 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 202632 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 202632 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1866062 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1866062 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1866062 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 202632 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2100269 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4175331 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 184963 # Number of read requests accepted
< system.physmem.writeReqs 149464 # Number of write requests accepted
< system.physmem.readBursts 184963 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 149464 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 11826048 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9564672 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 11837632 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 9565696 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::total 184401 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 148992 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 148992 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 202341 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2085454 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2294140 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 202341 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 202341 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1853615 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1853615 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1853615 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 202341 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2085454 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4147754 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 184401 # Number of read requests accepted
> system.physmem.writeReqs 148992 # Number of write requests accepted
> system.physmem.readBursts 184401 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 148992 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 11790400 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 11264 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9534208 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 11801664 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 9535488 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue
62,94c62,94
< system.physmem.neitherReadNorWriteReqs 48781 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12059 # Per bank write bursts
< system.physmem.perBankRdBursts::1 11374 # Per bank write bursts
< system.physmem.perBankRdBursts::2 11651 # Per bank write bursts
< system.physmem.perBankRdBursts::3 11200 # Per bank write bursts
< system.physmem.perBankRdBursts::4 11713 # Per bank write bursts
< system.physmem.perBankRdBursts::5 11071 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11625 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11816 # Per bank write bursts
< system.physmem.perBankRdBursts::8 11540 # Per bank write bursts
< system.physmem.perBankRdBursts::9 11598 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11427 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11449 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11382 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12463 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11321 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11093 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10213 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9339 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9470 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9072 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9457 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9178 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9173 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8997 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8928 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9204 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9473 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8827 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9527 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9857 # Per bank write bursts
< system.physmem.perBankWrBursts::14 9294 # Per bank write bursts
< system.physmem.perBankWrBursts::15 9439 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 48430 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 11512 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10865 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12624 # Per bank write bursts
> system.physmem.perBankRdBursts::3 11646 # Per bank write bursts
> system.physmem.perBankRdBursts::4 11360 # Per bank write bursts
> system.physmem.perBankRdBursts::5 11063 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11424 # Per bank write bursts
> system.physmem.perBankRdBursts::7 11380 # Per bank write bursts
> system.physmem.perBankRdBursts::8 11354 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10854 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10623 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11335 # Per bank write bursts
> system.physmem.perBankRdBursts::12 12163 # Per bank write bursts
> system.physmem.perBankRdBursts::13 12460 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11874 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11688 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9762 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9087 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9770 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9357 # Per bank write bursts
> system.physmem.perBankWrBursts::4 9485 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8994 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9154 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8718 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8812 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9056 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8954 # Per bank write bursts
> system.physmem.perBankWrBursts::11 9300 # Per bank write bursts
> system.physmem.perBankWrBursts::12 9801 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9709 # Per bank write bursts
> system.physmem.perBankWrBursts::14 9528 # Per bank write bursts
> system.physmem.perBankWrBursts::15 9485 # Per bank write bursts
96,97c96,97
< system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
< system.physmem.totGap 5126139591500 # Total gap between requests
---
> system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
> system.physmem.totGap 5144265948500 # Total gap between requests
104c104
< system.physmem.readPktSize::6 184963 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 184401 # Read request sizes (log2)
111,122c111,122
< system.physmem.writePktSize::6 149464 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 170238 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 11784 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 1972 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 468 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 29 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 32 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 148992 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 169976 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 11589 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 1867 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 53 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see
159,225c159,225
< system.physmem.wrQLenPdf::15 2243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2963 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 7948 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 7845 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 7778 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7827 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7815 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 9638 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9886 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 11733 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10348 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9934 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8512 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8974 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 9035 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7803 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7671 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7588 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 270 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 273 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 163 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 71880 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 297.588425 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 176.048684 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 320.988013 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 27629 38.44% 38.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17400 24.21% 62.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 7428 10.33% 72.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4118 5.73% 78.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2845 3.96% 82.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1999 2.78% 85.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1307 1.82% 87.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1141 1.59% 88.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8013 11.15% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 71880 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 7347 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.150402 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 560.379075 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 7346 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2888 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 7428 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 7347 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 8228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 8294 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 9520 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8743 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 9904 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 10060 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 10062 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 11631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 9054 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8427 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8727 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7953 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7460 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 100 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 45 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 73109 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 291.681517 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 174.230147 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 313.360710 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 28156 38.51% 38.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17755 24.29% 62.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 7676 10.50% 73.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 4351 5.95% 79.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2926 4.00% 83.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2405 3.29% 86.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1356 1.85% 88.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1112 1.52% 89.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7372 10.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 73109 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 7269 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 25.343238 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 563.383377 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 7268 99.99% 99.99% # Reads before turning the bus around for writes
227,267c227,262
< system.physmem.rdPerTurnAround::total 7347 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 7347 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.341364 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.592949 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 13.054942 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 6299 85.74% 85.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 77 1.05% 86.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 192 2.61% 89.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 82 1.12% 90.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 130 1.77% 92.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 203 2.76% 95.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 23 0.31% 95.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 7 0.10% 95.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 7 0.10% 95.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 8 0.11% 95.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.05% 95.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 6 0.08% 95.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 243 3.31% 99.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 7 0.10% 99.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 9 0.12% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 11 0.15% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 1 0.01% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.01% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 7 0.10% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 16 0.22% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 7347 # Writes before turning the bus around for reads
< system.physmem.totQLat 1972823732 # Total ticks spent queuing
< system.physmem.totMemAccLat 5437486232 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 923910000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10676.49 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 7269 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 7269 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.494153 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.676401 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 12.977803 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 6209 85.42% 85.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 177 2.43% 87.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 31 0.43% 88.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 190 2.61% 90.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 15 0.21% 91.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 151 2.08% 93.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 110 1.51% 94.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 9 0.12% 94.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 21 0.29% 95.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 27 0.37% 95.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 5 0.07% 95.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 5 0.07% 95.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 236 3.25% 98.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 8 0.11% 98.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 6 0.08% 99.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 36 0.50% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 3 0.04% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 5 0.07% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.01% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 2 0.03% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 15 0.21% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 7269 # Writes before turning the bus around for reads
> system.physmem.totQLat 2113024695 # Total ticks spent queuing
> system.physmem.totMemAccLat 5567243445 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 921125000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11469.80 # Average queueing delay per DRAM burst
269,273c264,268
< system.physmem.avgMemAccLat 29426.49 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30219.80 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
278,296c273,291
< system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 22.70 # Average write queue length when enqueuing
< system.physmem.readRowHits 152120 # Number of row buffer hits during reads
< system.physmem.writeRowHits 110229 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes
< system.physmem.avgGap 15328127.19 # Average gap between requests
< system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 270149040 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 147402750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 721570200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 485345520 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 129415070025 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 2962157471250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 3428011044705 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.732438 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 4927750166228 # Time in different power states
< system.physmem_0.memoryStateTime::REF 171172820000 # Time in different power states
---
> system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 23.39 # Average write queue length when enqueuing
> system.physmem.readRowHits 150283 # Number of row buffer hits during reads
> system.physmem.writeRowHits 109804 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes
> system.physmem.avgGap 15430035.87 # Average gap between requests
> system.physmem.pageHitRate 78.05 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 271774440 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 148289625 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 716609400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 481638960 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 133079069070 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 2969819271000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 3440514616095 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.806670 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 4940481054222 # Time in different power states
> system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states
298c293
< system.physmem_0.memoryStateTime::ACT 27209465022 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 32006683778 # Time in different power states
300,310c295,305
< system.physmem_1.actEnergy 273263760 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 149102250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 719721600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 483077520 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 129328302060 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2962233583500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 3428001086610 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.730496 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 4927884080230 # Time in different power states
< system.physmem_1.memoryStateTime::REF 171172820000 # Time in different power states
---
> system.physmem_1.actEnergy 280929600 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 153285000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 720337800 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 483699600 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 133106515425 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 2969795195250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 3440537926275 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.811201 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 4940433568236 # Time in different power states
> system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states
312c307
< system.physmem_1.memoryStateTime::ACT 27082630770 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 32047173014 # Time in different power states
314,318c309,313
< system.cpu.branchPred.lookups 86515320 # Number of BP lookups
< system.cpu.branchPred.condPredicted 86515320 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 846562 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 79887008 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 77941063 # Number of BTB hits
---
> system.cpu.branchPred.lookups 86512376 # Number of BP lookups
> system.cpu.branchPred.condPredicted 86512376 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 844809 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 79880541 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 77944216 # Number of BTB hits
320,322c315,317
< system.cpu.branchPred.BTBHitPct 97.564128 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1538368 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 179519 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 97.575974 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1537356 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 178131 # Number of incorrect RAS predictions.
325c320
< system.cpu.numCycles 448780162 # number of cpu cycles simulated
---
> system.cpu.numCycles 465431904 # number of cpu cycles simulated
328,344c323,339
< system.cpu.fetch.icacheStallCycles 27109366 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 427484272 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 86515320 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 79479431 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 417767954 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1778202 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 144572 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 59542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 198505 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 8932158 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 424030 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 4890 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 446169387 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.890848 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.050446 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 27316222 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 427457339 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 86512376 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 79481572 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 433294653 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1774328 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 174290 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 61780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 197089 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 797 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 8939505 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 424296 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5201 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 461932056 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.826209 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.017418 # Number of instructions fetched each cycle (Total)
346,354c341,349
< system.cpu.fetch.rateDist::0 281281763 63.04% 63.04% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2130107 0.48% 63.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 72126905 16.17% 79.69% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 1545484 0.35% 80.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2095217 0.47% 80.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 2290541 0.51% 81.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 1479828 0.33% 81.35% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1850907 0.41% 81.76% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 81368635 18.24% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 297044979 64.30% 64.30% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2134462 0.46% 64.77% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 72126640 15.61% 80.38% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 1546779 0.33% 80.72% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2100235 0.45% 81.17% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 2289900 0.50% 81.67% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 1474676 0.32% 81.99% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1857009 0.40% 82.39% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 81357376 17.61% 100.00% # Number of instructions fetched each cycle (Total)
358,400c353,395
< system.cpu.fetch.rateDist::total 446169387 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.192779 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.952547 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 23013230 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 265986736 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 147854773 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 8425547 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 889101 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 835878661 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 889101 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 26336765 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 222825660 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 12982234 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 152266315 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 30869312 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 832551989 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 449261 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 12787861 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 146326 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 14734321 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 994655089 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1807638707 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1111268111 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 319 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 963888503 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 30766581 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 460676 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 463553 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 43190500 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 17070475 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 10019861 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1311535 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1113253 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 827301854 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1181846 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 822527972 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 224018 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 22481665 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 33938360 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 142118 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 446169387 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.843533 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.419200 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 461932056 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.185875 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.918410 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 23107773 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 281695317 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 147794197 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 8447605 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 887164 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 835787144 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 887164 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 26441875 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 229504552 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 14337084 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 152214834 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 38546547 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 832466923 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 458085 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 12798467 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 221946 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 22321415 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 994552862 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1807469855 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1111168371 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 379 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 963838514 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 30714343 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 460142 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 463176 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 43334873 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 17067493 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 10022220 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1319734 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1116337 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 827242342 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1181786 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 822485271 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 216558 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 22465018 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 33877646 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 141871 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 461932056 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.780533 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 2.400914 # Number of insts issued each cycle
402,410c397,405
< system.cpu.iq.issued_per_cycle::0 262457891 58.82% 58.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 13818111 3.10% 61.92% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 9771246 2.19% 64.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7528828 1.69% 65.80% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 73243364 16.42% 82.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 4832116 1.08% 83.30% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 72756563 16.31% 99.61% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 1182673 0.27% 99.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 578595 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 278202681 60.23% 60.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 13844974 3.00% 63.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 9781174 2.12% 65.34% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7532969 1.63% 66.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 73227075 15.85% 82.82% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 4827596 1.05% 83.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 72754467 15.75% 99.62% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 1183000 0.26% 99.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 578120 0.13% 100.00% # Number of insts issued each cycle
414c409
< system.cpu.iq.issued_per_cycle::total 446169387 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 461932056 # Number of insts issued each cycle
416,446c411,441
< system.cpu.iq.fu_full::IntAlu 2475977 76.35% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 605774 18.68% 95.03% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 161247 4.97% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 2482095 76.42% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.42% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 605940 18.66% 95.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 160087 4.93% 100.00% # attempts to use FU when none available
449,452c444,447
< system.cpu.iq.FU_type_0::No_OpClass 283294 0.03% 0.03% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 794512938 96.59% 96.63% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 150315 0.02% 96.65% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 126079 0.02% 96.66% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 284904 0.03% 0.03% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 794458238 96.59% 96.63% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 149904 0.02% 96.65% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 126188 0.02% 96.66% # Type of FU issued
455c450
< system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.66% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatCvt 113 0.00% 96.66% # Type of FU issued
479,480c474,475
< system.cpu.iq.FU_type_0::MemRead 18183253 2.21% 98.87% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 9272009 1.13% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 18188915 2.21% 98.87% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 9277009 1.13% 100.00% # Type of FU issued
483,495c478,490
< system.cpu.iq.FU_type_0::total 822527972 # Type of FU issued
< system.cpu.iq.rate 1.832808 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 3242998 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.003943 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 2094691886 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 850977244 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 818130626 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 165 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 825487451 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1857982 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 822485271 # Type of FU issued
> system.cpu.iq.rate 1.767144 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 3248122 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.003949 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 2110366769 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 850901074 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 818087590 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 508 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 586 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 178 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 825448239 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1862376 # Number of loads that had data forwarded from stores
497,500c492,495
< system.cpu.iew.lsq.thread0.squashedLoads 3083761 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 14419 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 13953 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1600409 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 3081864 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 14686 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 14021 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1600056 # Number of stores squashed
503,504c498,499
< system.cpu.iew.lsq.thread0.rescheduledLoads 2207227 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 67958 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 2207186 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 68323 # Number of times an access to memory failed due to the cache being blocked
506,522c501,517
< system.cpu.iew.iewSquashCycles 889101 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 204671978 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 10002497 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 828483700 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 158761 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 17070475 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 10019861 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 692471 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 393140 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 8758574 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 13953 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 479614 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 507057 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 986671 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 821011839 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 17813350 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1389357 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 887164 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 205274699 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 15795611 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 828424128 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 165882 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 17067493 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 10022220 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 692366 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 393655 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 14549719 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 14021 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 476392 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 506422 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 982814 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 820971747 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 17818623 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1389098 # Number of squashed instructions skipped in execute
525,532c520,527
< system.cpu.iew.exec_refs 26873346 # number of memory reference insts executed
< system.cpu.iew.exec_branches 83150160 # Number of branches executed
< system.cpu.iew.exec_stores 9059996 # Number of stores executed
< system.cpu.iew.exec_rate 1.829430 # Inst execution rate
< system.cpu.iew.wb_sent 820539763 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 818130791 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 639922411 # num instructions producing a value
< system.cpu.iew.wb_consumers 1048802840 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 26886211 # number of memory reference insts executed
> system.cpu.iew.exec_branches 83147027 # Number of branches executed
> system.cpu.iew.exec_stores 9067588 # Number of stores executed
> system.cpu.iew.exec_rate 1.763892 # Inst execution rate
> system.cpu.iew.wb_sent 820497311 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 818087768 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 639862073 # num instructions producing a value
> system.cpu.iew.wb_consumers 1048693225 # num instructions consuming a value
534,535c529,530
< system.cpu.iew.wb_rate 1.823010 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.610146 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.757696 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.610152 # average fanout of values written-back
537,542c532,537
< system.cpu.commit.commitSquashedInsts 22357422 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1039727 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 857347 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 442798070 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.820247 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.674846 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 22343285 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1039914 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 855258 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 458562995 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.757576 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.649246 # Number of insts commited each cycle
544,552c539,547
< system.cpu.commit.committed_per_cycle::0 272013186 61.43% 61.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 11121974 2.51% 63.94% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3639430 0.82% 64.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 74586618 16.84% 81.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 2447768 0.55% 82.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1626880 0.37% 82.53% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1002961 0.23% 82.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 70975924 16.03% 98.78% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 5383329 1.22% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 287777749 62.76% 62.76% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 11132608 2.43% 65.18% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3641047 0.79% 65.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 74579710 16.26% 82.24% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 2448796 0.53% 82.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1627078 0.35% 83.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1001834 0.22% 83.35% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 70969693 15.48% 98.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 5384480 1.17% 100.00% # Number of insts commited each cycle
556,558c551,553
< system.cpu.commit.committed_per_cycle::total 442798070 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 407767906 # Number of instructions committed
< system.cpu.commit.committedOps 806002026 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 458562995 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 407746267 # Number of instructions committed
> system.cpu.commit.committedOps 805959101 # Number of ops (including micro ops) committed
560,563c555,558
< system.cpu.commit.refs 22406164 # Number of memory references committed
< system.cpu.commit.loads 13986712 # Number of loads committed
< system.cpu.commit.membars 468149 # Number of memory barriers committed
< system.cpu.commit.branches 82157432 # Number of branches committed
---
> system.cpu.commit.refs 22407791 # Number of memory references committed
> system.cpu.commit.loads 13985627 # Number of loads committed
> system.cpu.commit.membars 468163 # Number of memory barriers committed
> system.cpu.commit.branches 82155343 # Number of branches committed
565,570c560,565
< system.cpu.commit.int_insts 734850257 # Number of committed integer instructions.
< system.cpu.commit.function_calls 1155439 # Number of function calls committed.
< system.cpu.commit.op_class_0::No_OpClass 171613 0.02% 0.02% # Class of committed instruction
< system.cpu.commit.op_class_0::IntAlu 783160302 97.17% 97.19% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 144896 0.02% 97.21% # Class of committed instruction
< system.cpu.commit.op_class_0::IntDiv 121618 0.02% 97.22% # Class of committed instruction
---
> system.cpu.commit.int_insts 734813827 # Number of committed integer instructions.
> system.cpu.commit.function_calls 1155420 # Number of function calls committed.
> system.cpu.commit.op_class_0::No_OpClass 171757 0.02% 0.02% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 783115943 97.17% 97.19% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 144574 0.02% 97.20% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction
597,598c592,593
< system.cpu.commit.op_class_0::MemRead 13984129 1.73% 98.96% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 8419452 1.04% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 13983042 1.73% 98.96% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 8422164 1.04% 100.00% # Class of committed instruction
601,629c596,624
< system.cpu.commit.op_class_0::total 806002026 # Class of committed instruction
< system.cpu.commit.bw_lim_events 5383329 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 1265696040 # The number of ROB reads
< system.cpu.rob.rob_writes 1660107630 # The number of ROB writes
< system.cpu.timesIdled 283975 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 2610775 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 9803496536 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 407767906 # Number of Instructions Simulated
< system.cpu.committedOps 806002026 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 1.100577 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.100577 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.908614 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.908614 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1090426394 # number of integer regfile reads
< system.cpu.int_regfile_writes 654841654 # number of integer regfile writes
< system.cpu.fp_regfile_reads 165 # number of floating regfile reads
< system.cpu.cc_regfile_reads 415713185 # number of cc regfile reads
< system.cpu.cc_regfile_writes 321659378 # number of cc regfile writes
< system.cpu.misc_regfile_reads 264880270 # number of misc regfile reads
< system.cpu.misc_regfile_writes 399890 # number of misc regfile writes
< system.cpu.dcache.tags.replacements 1655948 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.995019 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 18959511 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1656460 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 11.445801 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.995019 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
---
> system.cpu.commit.op_class_0::total 805959101 # Class of committed instruction
> system.cpu.commit.bw_lim_events 5384480 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 1281402583 # The number of ROB reads
> system.cpu.rob.rob_writes 1659991505 # The number of ROB writes
> system.cpu.timesIdled 284256 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 3499848 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 9823097505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 407746267 # Number of Instructions Simulated
> system.cpu.committedOps 805959101 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 1.141474 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.141474 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.876060 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.876060 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1090398458 # number of integer regfile reads
> system.cpu.int_regfile_writes 654801015 # number of integer regfile writes
> system.cpu.fp_regfile_reads 178 # number of floating regfile reads
> system.cpu.cc_regfile_reads 415698435 # number of cc regfile reads
> system.cpu.cc_regfile_writes 321644299 # number of cc regfile writes
> system.cpu.misc_regfile_reads 264872577 # number of misc regfile reads
> system.cpu.misc_regfile_writes 400155 # number of misc regfile writes
> system.cpu.dcache.tags.replacements 1656886 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.993571 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 18963252 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1657398 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 11.441580 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.993571 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
631,633c626,628
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
635,698c630,693
< system.cpu.dcache.tags.tag_accesses 87653092 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 87653092 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 10818266 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 10818266 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8075018 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8075018 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 63136 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 63136 # number of SoftPFReq hits
< system.cpu.dcache.demand_hits::cpu.data 18893284 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 18893284 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 18956420 # number of overall hits
< system.cpu.dcache.overall_hits::total 18956420 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1801440 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1801440 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 334795 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 334795 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 406500 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 406500 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 2136235 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2136235 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2542735 # number of overall misses
< system.cpu.dcache.overall_misses::total 2542735 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 26875877500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 26875877500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 13801276738 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 13801276738 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 40677154238 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 40677154238 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 40677154238 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 40677154238 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 12619706 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 12619706 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8409813 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8409813 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 469636 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 469636 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21029519 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21029519 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21499155 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21499155 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142748 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.142748 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039810 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.039810 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865564 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.865564 # miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.101583 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.101583 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.118271 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.118271 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14919.107769 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14919.107769 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.067065 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.067065 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 19041.516611 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 19041.516611 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 15997.402104 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 15997.402104 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 467524 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 95 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 52009 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.989290 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked
---
> system.cpu.dcache.tags.tag_accesses 87668549 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 87668549 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 10819943 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 10819943 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8077328 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8077328 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 63083 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 63083 # number of SoftPFReq hits
> system.cpu.dcache.demand_hits::cpu.data 18897271 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 18897271 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 18960354 # number of overall hits
> system.cpu.dcache.overall_hits::total 18960354 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1800618 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1800618 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 335187 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 335187 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 406619 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 406619 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 2135805 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2135805 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2542424 # number of overall misses
> system.cpu.dcache.overall_misses::total 2542424 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 29915350500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 29915350500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 21131383234 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 21131383234 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 51046733734 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 51046733734 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 51046733734 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 51046733734 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 12620561 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12620561 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8412515 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8412515 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 469702 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 469702 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21033076 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21033076 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21502778 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21502778 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142673 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.142673 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039844 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.039844 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865696 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.865696 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.101545 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.101545 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.118237 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.118237 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16613.935049 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16613.935049 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63043.564440 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63043.564440 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23900.465508 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23900.465508 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 20077.978234 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 20077.978234 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 549742 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 52309 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.509511 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
701,768c696,763
< system.cpu.dcache.writebacks::writebacks 1557810 # number of writebacks
< system.cpu.dcache.writebacks::total 1557810 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 835579 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 835579 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44644 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 44644 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 880223 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 880223 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 880223 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 880223 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965861 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 965861 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290151 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 290151 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403017 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 403017 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1256012 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1256012 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1659029 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1659029 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13873 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 13873 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616769 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 616769 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13275179500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 13275179500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12396951239 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12396951239 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6045548500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6045548500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25672130739 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 25672130739 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31717679239 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 31717679239 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793653500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793653500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2614977500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2614977500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100408631000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 100408631000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076536 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076536 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034501 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034501 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858148 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858148 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059726 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.059726 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077167 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.077167 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.399556 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.399556 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42725.860807 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42725.860807 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15000.728257 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15000.728257 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20439.399257 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20439.399257 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19118.218692 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 19118.218692 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.505766 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.505766 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188494.017156 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188494.017156 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.791394 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.791394 # average overall mshr uncacheable latency
---
> system.cpu.dcache.writebacks::writebacks 1559463 # number of writebacks
> system.cpu.dcache.writebacks::total 1559463 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 834370 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 834370 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44863 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 44863 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 879233 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 879233 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 879233 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 879233 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 966248 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 966248 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290324 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 290324 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403128 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 403128 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1256572 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1256572 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1659700 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1659700 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602897 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 602897 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13882 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 13882 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616779 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 616779 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14275238000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 14275238000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19179377736 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 19179377736 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6821935500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6821935500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33454615736 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 33454615736 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40276551236 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 40276551236 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793888500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793888500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2616393000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2616393000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100410281500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 100410281500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076561 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076561 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034511 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034511 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858263 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858263 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059743 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.059743 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077185 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14773.886207 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14773.886207 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66061.978121 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66061.978121 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16922.504763 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16922.504763 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26623.715741 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26623.715741 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24267.368341 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24267.368341 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.626505 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.626505 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188473.778994 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188473.778994 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.827909 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909 # average overall mshr uncacheable latency
770,778c765,773
< system.cpu.dtb_walker_cache.tags.replacements 71018 # number of replacements
< system.cpu.dtb_walker_cache.tags.tagsinuse 15.855051 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 110090 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.sampled_refs 71033 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.avg_refs 1.549843 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 197734009500 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.855051 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.990941 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_percent::total 0.990941 # Average percentage of cache occupancy
---
> system.cpu.dtb_walker_cache.tags.replacements 86946 # number of replacements
> system.cpu.dtb_walker_cache.tags.tagsinuse 15.839570 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 92503 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.sampled_refs 86961 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.avg_refs 1.063730 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.839570 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.989973 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_percent::total 0.989973 # Average percentage of cache occupancy
780,782c775,776
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
---
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
784,821c778,815
< system.cpu.dtb_walker_cache.tags.tag_accesses 436469 # Number of tag accesses
< system.cpu.dtb_walker_cache.tags.data_accesses 436469 # Number of data accesses
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110104 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 110104 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110104 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 110104 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110104 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 110104 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 72087 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 72087 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 72087 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 72087 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 72087 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 72087 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 888705500 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 888705500 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 888705500 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 888705500 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 888705500 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 888705500 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182191 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 182191 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182191 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 182191 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182191 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 182191 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395667 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395667 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395667 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395667 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395667 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395667 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12328.235327 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12328.235327 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12328.235327 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12328.235327 # average overall miss latency
---
> system.cpu.dtb_walker_cache.tags.tag_accesses 449092 # Number of tag accesses
> system.cpu.dtb_walker_cache.tags.data_accesses 449092 # Number of data accesses
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92507 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 92507 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92507 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 92507 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92507 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 92507 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 88026 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 88026 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 88026 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 88026 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 88026 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 88026 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1095128000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1095128000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1095128000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 1095128000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1095128000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 1095128000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180533 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 180533 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180533 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 180533 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180533 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 180533 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.487590 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.487590 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.487590 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.487590 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.487590 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.487590 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625 # average overall miss latency
830,855c824,849
< system.cpu.dtb_walker_cache.writebacks::writebacks 17880 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 17880 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 72087 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 72087 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 72087 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 72087 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 72087 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 72087 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 816618500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 816618500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 816618500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 816618500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 816618500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 816618500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395667 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395667 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395667 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11328.235327 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 22750 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 22750 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 88026 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 88026 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 88026 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 88026 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 88026 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 88026 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1007102000 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1007102000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1007102000 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.487590 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.487590 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.487590 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency
857,865c851,859
< system.cpu.icache.tags.replacements 972475 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.589862 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 7892622 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 972987 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 8.111745 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 147937650500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.589862 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.995293 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.995293 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 979952 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.399185 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 7892668 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 980464 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 8.049931 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 150322947500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.399185 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.994920 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.994920 # Average percentage of cache occupancy
867c861
< system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
869c863
< system.cpu.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id
871,914c865,908
< system.cpu.icache.tags.tag_accesses 9905522 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 9905522 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 7892622 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 7892622 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 7892622 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 7892622 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 7892622 # number of overall hits
< system.cpu.icache.overall_hits::total 7892622 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1039533 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1039533 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1039533 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1039533 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1039533 # number of overall misses
< system.cpu.icache.overall_misses::total 1039533 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14506630997 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14506630997 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14506630997 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14506630997 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14506630997 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14506630997 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 8932155 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 8932155 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 8932155 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 8932155 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 8932155 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 8932155 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116381 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.116381 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.116381 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.116381 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.116381 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.116381 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13954.949960 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13954.949960 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13954.949960 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13954.949960 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 6454 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 20.554140 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked
---
> system.cpu.icache.tags.tag_accesses 9920034 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 9920034 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 7892668 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 7892668 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 7892668 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 7892668 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 7892668 # number of overall hits
> system.cpu.icache.overall_hits::total 7892668 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1046827 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1046827 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1046827 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1046827 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1046827 # number of overall misses
> system.cpu.icache.overall_misses::total 1046827 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15679887484 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15679887484 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15679887484 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15679887484 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15679887484 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15679887484 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 8939495 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 8939495 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 8939495 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 8939495 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 8939495 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 8939495 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117101 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.117101 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.117101 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.117101 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.117101 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.117101 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.489745 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14978.489745 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14978.489745 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14978.489745 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 13392 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 457 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 29.304158 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked
917,946c911,940
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66166 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 66166 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 66166 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 66166 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 66166 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 66166 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973367 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 973367 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 973367 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 973367 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 973367 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 973367 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12880264497 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12880264497 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12880264497 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12880264497 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12880264497 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12880264497 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108973 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.108973 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.108973 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13232.690750 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13232.690750 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66288 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 66288 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 66288 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 66288 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 66288 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 66288 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980539 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 980539 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 980539 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 980539 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 980539 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 980539 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13806283989 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 13806283989 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13806283989 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 13806283989 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13806283989 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 13806283989 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109686 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.109686 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.109686 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14080.300721 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14080.300721 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency
948,965c942,959
< system.cpu.itb_walker_cache.tags.replacements 13962 # number of replacements
< system.cpu.itb_walker_cache.tags.tagsinuse 6.017494 # Cycle average of tags in use
< system.cpu.itb_walker_cache.tags.total_refs 24005 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.sampled_refs 13975 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.tags.avg_refs 1.717710 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.warmup_cycle 5100174829000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017494 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376093 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.376093 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
< system.cpu.itb_walker_cache.tags.tag_accesses 92555 # Number of tag accesses
< system.cpu.itb_walker_cache.tags.data_accesses 92555 # Number of data accesses
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24014 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 24014 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.tags.replacements 19284 # number of replacements
> system.cpu.itb_walker_cache.tags.tagsinuse 6.025119 # Cycle average of tags in use
> system.cpu.itb_walker_cache.tags.total_refs 17613 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.sampled_refs 19298 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.tags.avg_refs 0.912685 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.warmup_cycle 5119738953000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.025119 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376570 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.376570 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
> system.cpu.itb_walker_cache.tags.tag_accesses 95741 # Number of tag accesses
> system.cpu.itb_walker_cache.tags.data_accesses 95741 # Number of data accesses
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 17618 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 17618 # number of ReadReq hits
968,985c962,979
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24016 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 24016 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24016 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 24016 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14841 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 14841 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14841 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 14841 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14841 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 14841 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 170100000 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 170100000 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 170100000 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 170100000 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 170100000 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 170100000 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38855 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 38855 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 17620 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 17620 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 17620 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 17620 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 20167 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 20167 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 20167 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 20167 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 20167 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 20167 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 233184000 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 233184000 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 233184000 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 233184000 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 233184000 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 233184000 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37785 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 37785 # number of ReadReq accesses(hits+misses)
988,1003c982,997
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38857 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 38857 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38857 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 38857 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381959 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381959 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381939 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.381939 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381939 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.381939 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11461.491813 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11461.491813 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11461.491813 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11461.491813 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37787 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 37787 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37787 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 37787 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.533730 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.533730 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.533702 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.533702 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.533702 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.533702 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11562.651857 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11562.651857 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11562.651857 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11562.651857 # average overall miss latency
1012,1037c1006,1031
< system.cpu.itb_walker_cache.writebacks::writebacks 2319 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 2319 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14841 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14841 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14841 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 14841 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14841 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 14841 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155259000 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155259000 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155259000 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155259000 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155259000 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155259000 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381959 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381959 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381939 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381939 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10461.491813 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 3197 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 3197 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 20167 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 20167 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 20167 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 20167 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 20167 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 20167 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 213017000 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 213017000 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 213017000 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 213017000 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 213017000 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 213017000 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.533730 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.533730 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.533702 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.533702 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.651857 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency
1039,1043c1033,1037
< system.cpu.l2cache.tags.replacements 112328 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64826.279220 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4884469 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 176125 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 27.732968 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 111670 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64798.131266 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4919632 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 175949 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 27.960557 # Average number of references to valid blocks.
1045,1051c1039,1045
< system.cpu.l2cache.tags.occ_blocks::writebacks 50541.510277 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.632944 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140332 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.306836 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.688831 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.771202 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000208 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50517.509380 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.940071 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139536 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3193.810391 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.731889 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.770836 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000167 # Average percentage of cache occupancy
1053,1188c1047,1182
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047383 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.170375 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 63797 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 708 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3407 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5556 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54082 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.973465 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 43431157 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 43431157 # Number of data accesses
< system.cpu.l2cache.Writeback_hits::writebacks 1578009 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1578009 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 154224 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 154224 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 956701 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 956701 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 65553 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12091 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332425 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 1410069 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 65553 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 12091 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 956701 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1486649 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2520994 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 65553 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 12091 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 956701 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1486649 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2520994 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1786 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1786 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133488 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133488 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16231 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 16231 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 61 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 6 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35709 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 35776 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 16231 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 169197 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 185495 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 16231 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 169197 # number of overall misses
< system.cpu.l2cache.overall_misses::total 185495 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23220500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 23220500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10274230500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10274230500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1348223000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1348223000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 5829000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 513000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3059963500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3066305500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5829000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 513000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1348223000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13334194000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 14688759000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5829000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 513000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1348223000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13334194000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 14688759000 # number of overall miss cycles
< system.cpu.l2cache.Writeback_accesses::writebacks 1578009 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1578009 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2107 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2107 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 287712 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 287712 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 972932 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 972932 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 65614 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12097 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368134 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1445845 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 65614 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 12097 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 972932 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1655846 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2706489 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 65614 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 12097 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 972932 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1655846 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2706489 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.847651 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.847651 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463964 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.463964 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016683 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016683 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000930 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000496 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026101 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024744 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000930 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000496 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016683 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102182 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.068537 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000930 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000496 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016683 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102182 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.068537 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13001.399776 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13001.399776 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76967.446512 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76967.446512 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83064.691023 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83064.691023 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 95557.377049 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 85500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85691.660366 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85708.449799 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 95557.377049 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 85500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83064.691023 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78808.690461 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79186.819052 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 95557.377049 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 85500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83064.691023 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78808.690461 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79186.819052 # average overall miss latency
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048734 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.169002 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.988741 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 64279 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 676 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3413 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5955 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54192 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980820 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 43682151 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 43682151 # Number of data accesses
> system.cpu.l2cache.Writeback_hits::writebacks 1585410 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1585410 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 346 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 346 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 155314 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 155314 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 964131 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 964131 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 75809 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 15497 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332951 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 1424257 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 75809 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 15497 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 964131 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1488265 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2543702 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 75809 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 15497 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 964131 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1488265 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2543702 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 132872 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 132872 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16267 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 16267 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 62 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35699 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 35766 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 16267 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 168571 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 184905 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 16267 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 168571 # number of overall misses
> system.cpu.l2cache.overall_misses::total 184905 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 58198000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 58198000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16980826000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 16980826000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2184446000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2184446000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 9139000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 679500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4828291000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4838109500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9139000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 679500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2184446000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 21809117000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 24003381500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9139000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 679500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2184446000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 21809117000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 24003381500 # number of overall miss cycles
> system.cpu.l2cache.Writeback_accesses::writebacks 1585410 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1585410 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1808 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1808 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 288186 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 288186 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 980398 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 980398 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 75871 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 15502 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368650 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1460023 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 75871 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 15502 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 980398 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1656836 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2728607 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 75871 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 15502 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 980398 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1656836 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2728607 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808628 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808628 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461063 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.461063 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016592 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016592 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000817 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000323 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026083 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024497 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000817 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000323 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016592 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.101743 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.067765 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000817 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000323 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016592 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.101743 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.067765 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39807.113543 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39807.113543 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127798.377386 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127798.377386 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134286.961333 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134286.961333 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 147403.225806 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135900 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135250.035015 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135271.193312 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 147403.225806 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135900 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134286.961333 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129376.446720 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 129814.669695 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 147403.225806 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135900 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134286.961333 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129376.446720 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 129814.669695 # average overall miss latency
1197,1262c1191,1256
< system.cpu.l2cache.writebacks::writebacks 102797 # number of writebacks
< system.cpu.l2cache.writebacks::total 102797 # number of writebacks
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 3 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 3 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 107 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 107 # number of CleanEvict MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1786 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1786 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133488 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133488 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16230 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16230 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 61 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 6 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35706 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35773 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16230 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 169194 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 185491 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16230 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 169194 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 185491 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13873 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13873 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616769 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616769 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37836000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37836000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8939350500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8939350500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1185827000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1185827000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 5219000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 453000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2703742500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2709414500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5219000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 453000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1185827000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11643093000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 12834592000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5219000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 453000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1185827000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11643093000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 12834592000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257448500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257448500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2455427500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2455427500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92712876000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92712876000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.writebacks::writebacks 102325 # number of writebacks
> system.cpu.l2cache.writebacks::total 102325 # number of writebacks
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 2 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132872 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 132872 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16264 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16264 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 62 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35697 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35764 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16264 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 168569 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 184900 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16264 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 168569 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 184900 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602897 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602897 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13882 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13882 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616779 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616779 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 104470500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 104470500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15652106000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15652106000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2021465000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2021465000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8519000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 629500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4471847000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4480995500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8519000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 629500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2021465000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20123953000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 22154566500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8519000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 629500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2021465000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20123953000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 22154566500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257667000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257667000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2456737500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2456737500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92714404500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92714404500 # number of overall MSHR uncacheable cycles
1265,1310c1259,1304
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.847651 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.847651 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463964 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463964 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026098 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024742 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.068536 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.068536 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21184.770437 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21184.770437 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66967.446512 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66967.446512 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73063.894023 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73063.894023 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75722.357587 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75739.090935 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.497472 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.497472 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176993.260290 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176993.260290 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.259287 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.259287 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808628 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808628 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461063 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461063 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016589 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024496 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.067764 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.067764 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125900 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302 # average overall mshr uncacheable latency
1312,1324c1306,1324
< system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3032324 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 13873 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 13873 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1727482 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 1093519 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2562 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2562 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 287721 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 287721 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 973367 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1456602 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::MessageReq 1641 # Transaction distribution
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 5491514 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2726446 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 94920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1211 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1211 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.trans_dist::ReadReq 602897 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3061240 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 13882 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 13882 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1734407 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 1095490 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2269 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2269 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 288196 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 288196 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 980539 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1478351 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution
1327,1340c1327,1340
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917513 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6205490 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31703 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168231 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 9322937 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62267648 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207474745 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 922624 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5343616 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 276008633 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 220316 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 6258702 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.033424 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.179742 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2939753 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6208049 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 41124 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 194511 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 9383437 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745472 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207643157 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1196736 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 6311744 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 277897109 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 226924 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 6316816 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.030269 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.203509 # Request fanout histogram
1342,1346c1342,1346
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 6049509 96.66% 96.66% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 209193 3.34% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 6163711 97.58% 97.58% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 115005 1.82% 99.40% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 38100 0.60% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1348,1351c1348,1351
< system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 6258702 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4609709481 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 6316816 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4646513967 # Layer occupancy (ticks)
1353c1353
< system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 659789 # Layer occupancy (ticks)
1355c1355
< system.cpu.toL2Bus.respLayer0.occupancy 1461362367 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1472350908 # Layer occupancy (ticks)
1357c1357
< system.cpu.toL2Bus.respLayer1.occupancy 3096027096 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3097364534 # Layer occupancy (ticks)
1359c1359
< system.cpu.toL2Bus.respLayer2.occupancy 22269484 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 30265969 # Layer occupancy (ticks)
1361c1361
< system.cpu.toL2Bus.respLayer3.occupancy 108175907 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 132091893 # Layer occupancy (ticks)
1363,1368c1363,1368
< system.iobus.trans_dist::ReadReq 222102 # Transaction distribution
< system.iobus.trans_dist::ReadResp 222102 # Transaction distribution
< system.iobus.trans_dist::WriteReq 57708 # Transaction distribution
< system.iobus.trans_dist::WriteResp 57708 # Transaction distribution
< system.iobus.trans_dist::MessageReq 1641 # Transaction distribution
< system.iobus.trans_dist::MessageResp 1641 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 222097 # Transaction distribution
> system.iobus.trans_dist::ReadResp 222097 # Transaction distribution
> system.iobus.trans_dist::WriteReq 57711 # Transaction distribution
> system.iobus.trans_dist::WriteResp 57711 # Transaction distribution
> system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
> system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
1374c1374
< system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
1387,1392c1387,1392
< system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 562902 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 464358 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 562906 # Packet count per connected master and slave (bytes)
1398c1398
< system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
1411,1417c1411,1417
< system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 3272880 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.bridge.master::total 238456 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 3272852 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 3921096 # Layer occupancy (ticks)
1429c1429
< system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
1453c1453
< system.iobus.reqLayer19.occupancy 242679087 # Layer occupancy (ticks)
---
> system.iobus.reqLayer19.occupancy 241306768 # Layer occupancy (ticks)
1457c1457
< system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 453367000 # Layer occupancy (ticks)
1459c1459
< system.iobus.respLayer1.occupancy 50182000 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks)
1461c1461
< system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks)
---
> system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
1463,1464c1463,1464
< system.iocache.tags.replacements 47580 # number of replacements
< system.iocache.tags.tagsinuse 0.091366 # Cycle average of tags in use
---
> system.iocache.tags.replacements 47574 # number of replacements
> system.iocache.tags.tagsinuse 0.116041 # Cycle average of tags in use
1466c1466
< system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
1468,1471c1468,1471
< system.iocache.tags.warmup_cycle 4993241946000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091366 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005710 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.005710 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 4999338704000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116041 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007253 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.007253 # Average percentage of cache occupancy
1475,1478c1475,1478
< system.iocache.tags.tag_accesses 428715 # Number of tag accesses
< system.iocache.tags.data_accesses 428715 # Number of data accesses
< system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 915 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 428661 # Number of tag accesses
> system.iocache.tags.data_accesses 428661 # Number of data accesses
> system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
1481,1494c1481,1494
< system.iocache.demand_misses::pc.south_bridge.ide 915 # number of demand (read+write) misses
< system.iocache.demand_misses::total 915 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 915 # number of overall misses
< system.iocache.overall_misses::total 915 # number of overall misses
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143595677 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 143595677 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513463410 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 5513463410 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 143595677 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 143595677 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 143595677 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 143595677 # number of overall miss cycles
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses
> system.iocache.demand_misses::total 909 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses
> system.iocache.overall_misses::total 909 # number of overall misses
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144457672 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 144457672 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6056832096 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 6056832096 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 144457672 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 144457672 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 144457672 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 144457672 # number of overall miss cycles
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
1497,1500c1497,1500
< system.iocache.demand_accesses::pc.south_bridge.ide 915 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 915 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 915 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 915 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses
1509,1517c1509,1517
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 156935.166120 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.775043 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118010.775043 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 156935.166120 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 156935.166120 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 158919.331133 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 158919.331133 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 158919.331133 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked
1519c1519
< system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 52 # number of cycles access was blocked
1521c1521
< system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 11.615385 # average number of cycles each access was blocked
1527,1528c1527,1528
< system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses
1531,1542c1531,1542
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 915 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 915 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 915 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 915 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 97845677 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177463410 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 3177463410 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 97845677 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 97845677 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 99007672 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3720832096 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 3720832096 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 99007672 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 99007672 # number of overall MSHR miss cycles
1551,1558c1551,1558
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 106935.166120 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.775043 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.775043 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency
1560,1572c1560,1572
< system.membus.trans_dist::ReadReq 602896 # Transaction distribution
< system.membus.trans_dist::ReadResp 655806 # Transaction distribution
< system.membus.trans_dist::WriteReq 13873 # Transaction distribution
< system.membus.trans_dist::WriteResp 13873 # Transaction distribution
< system.membus.trans_dist::Writeback 149464 # Transaction distribution
< system.membus.trans_dist::CleanEvict 9883 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 2535 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 2080 # Transaction distribution
< system.membus.trans_dist::ReadExReq 133195 # Transaction distribution
< system.membus.trans_dist::ReadExResp 133194 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 52918 # Transaction distribution
< system.membus.trans_dist::MessageReq 1641 # Transaction distribution
< system.membus.trans_dist::MessageResp 1641 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 602897 # Transaction distribution
> system.membus.trans_dist::ReadResp 655826 # Transaction distribution
> system.membus.trans_dist::WriteReq 13882 # Transaction distribution
> system.membus.trans_dist::WriteResp 13882 # Transaction distribution
> system.membus.trans_dist::Writeback 148992 # Transaction distribution
> system.membus.trans_dist::CleanEvict 9700 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 2190 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1729 # Transaction distribution
> system.membus.trans_dist::ReadExReq 132608 # Transaction distribution
> system.membus.trans_dist::ReadExResp 132605 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 52937 # Transaction distribution
> system.membus.trans_dist::MessageReq 1645 # Transaction distribution
> system.membus.trans_dist::MessageResp 1645 # Transaction distribution
1576,1580c1576,1580
< system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769188 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 486631 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464358 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769200 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484156 # Packet count per connected master and slave (bytes)
1582,1591c1582,1591
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720185 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141820 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 141820 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1865287 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538373 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18388288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20165113 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1717730 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141814 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 141814 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1862834 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238456 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538397 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20098965 # Cumulative packet size per connected master and slave (bytes)
1594c1594
< system.membus.pkt_size::total 23186717 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 23120585 # Cumulative packet size per connected master and slave (bytes)
1596,1598c1596,1598
< system.membus.snoop_fanout::samples 1013692 # Request fanout histogram
< system.membus.snoop_fanout::mean 1.001619 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.040202 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 1012128 # Request fanout histogram
> system.membus.snoop_fanout::mean 1.001625 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.040282 # Request fanout histogram
1601,1602c1601,1602
< system.membus.snoop_fanout::1 1012051 99.84% 99.84% # Request fanout histogram
< system.membus.snoop_fanout::2 1641 0.16% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 1010483 99.84% 99.84% # Request fanout histogram
> system.membus.snoop_fanout::2 1645 0.16% 100.00% # Request fanout histogram
1606,1607c1606,1607
< system.membus.snoop_fanout::total 1013692 # Request fanout histogram
< system.membus.reqLayer0.occupancy 354973500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 1012128 # Request fanout histogram
> system.membus.reqLayer0.occupancy 355014500 # Layer occupancy (ticks)
1609c1609
< system.membus.reqLayer1.occupancy 388325000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 388301500 # Layer occupancy (ticks)
1611c1611
< system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks)
1613c1613
< system.membus.reqLayer3.occupancy 1016908044 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1012808227 # Layer occupancy (ticks)
1615c1615
< system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
---
> system.membus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
1617c1617
< system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks)
1619c1619
< system.membus.respLayer2.occupancy 2204699193 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 2201176288 # Layer occupancy (ticks)
1621c1621
< system.membus.respLayer4.occupancy 86072153 # Layer occupancy (ticks)
---
> system.membus.respLayer4.occupancy 86060868 # Layer occupancy (ticks)