3,5c3,5
< sim_seconds 5.129943 # Number of seconds simulated
< sim_ticks 5129943020500 # Number of ticks simulated
< final_tick 5129943020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.125946 # Number of seconds simulated
> sim_ticks 5125946039500 # Number of ticks simulated
> final_tick 5125946039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 121408 # Simulator instruction rate (inst/s)
< host_op_rate 239988 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1526556123 # Simulator tick rate (ticks/s)
< host_mem_usage 798272 # Number of bytes of host memory used
< host_seconds 3360.47 # Real time elapsed on the host
< sim_insts 407987808 # Number of instructions simulated
< sim_ops 806471132 # Number of ops (including micro ops) simulated
---
> host_inst_rate 214937 # Simulator instruction rate (inst/s)
> host_op_rate 424847 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2699457200 # Simulator tick rate (ticks/s)
> host_mem_usage 751580 # Number of bytes of host memory used
> host_seconds 1898.88 # Real time elapsed on the host
> sim_insts 408140259 # Number of instructions simulated
> sim_ops 806733017 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1049088 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10796544 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1045568 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10796928 # Number of bytes read from this memory
21,25c21,25
< system.physmem.bytes_read::total 11878656 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1049088 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1049088 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9594624 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11875520 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1045568 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1045568 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9590656 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9590656 # Number of bytes written to this memory
28,29c28,29
< system.physmem.num_reads::cpu.inst 16392 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 168696 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 16337 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 168702 # Number of read requests responded to by this memory
31,34c31,34
< system.physmem.num_reads::total 185604 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 149916 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 848 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::total 185555 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 149854 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 149854 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 849 # Total read bandwidth from this memory (bytes/s)
36,45c36,45
< system.physmem.bw_read::cpu.inst 204503 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2104613 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2315553 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 204503 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 204503 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1870318 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1870318 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1870318 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 848 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 203976 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2106329 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2316747 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 203976 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 203976 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1871002 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1871002 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1871002 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 849 # Total bandwidth to/from this memory (bytes/s)
47,94c47,94
< system.physmem.bw_total::cpu.inst 204503 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2104613 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4185871 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 185604 # Number of read requests accepted
< system.physmem.writeReqs 196636 # Number of write requests accepted
< system.physmem.readBursts 185604 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 196636 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 11865664 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 12992 # Total number of bytes read from write queue
< system.physmem.bytesWritten 12442240 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 11878656 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 12584704 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 203 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2199 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 1712 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 11483 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10958 # Per bank write bursts
< system.physmem.perBankRdBursts::2 11903 # Per bank write bursts
< system.physmem.perBankRdBursts::3 11497 # Per bank write bursts
< system.physmem.perBankRdBursts::4 11986 # Per bank write bursts
< system.physmem.perBankRdBursts::5 11369 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11563 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11462 # Per bank write bursts
< system.physmem.perBankRdBursts::8 11178 # Per bank write bursts
< system.physmem.perBankRdBursts::9 11812 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11732 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11823 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11783 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12309 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11732 # Per bank write bursts
< system.physmem.perBankRdBursts::15 10811 # Per bank write bursts
< system.physmem.perBankWrBursts::0 14023 # Per bank write bursts
< system.physmem.perBankWrBursts::1 13077 # Per bank write bursts
< system.physmem.perBankWrBursts::2 12485 # Per bank write bursts
< system.physmem.perBankWrBursts::3 11134 # Per bank write bursts
< system.physmem.perBankWrBursts::4 11942 # Per bank write bursts
< system.physmem.perBankWrBursts::5 11710 # Per bank write bursts
< system.physmem.perBankWrBursts::6 11692 # Per bank write bursts
< system.physmem.perBankWrBursts::7 11673 # Per bank write bursts
< system.physmem.perBankWrBursts::8 11519 # Per bank write bursts
< system.physmem.perBankWrBursts::9 11764 # Per bank write bursts
< system.physmem.perBankWrBursts::10 12914 # Per bank write bursts
< system.physmem.perBankWrBursts::11 11938 # Per bank write bursts
< system.physmem.perBankWrBursts::12 12257 # Per bank write bursts
< system.physmem.perBankWrBursts::13 11913 # Per bank write bursts
< system.physmem.perBankWrBursts::14 12398 # Per bank write bursts
< system.physmem.perBankWrBursts::15 11971 # Per bank write bursts
---
> system.physmem.bw_total::cpu.inst 203976 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2106329 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4187749 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 185555 # Number of read requests accepted
> system.physmem.writeReqs 196574 # Number of write requests accepted
> system.physmem.readBursts 185555 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 196574 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 11866560 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue
> system.physmem.bytesWritten 12447744 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 11875520 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 12580736 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2049 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 1754 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 11700 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10942 # Per bank write bursts
> system.physmem.perBankRdBursts::2 11772 # Per bank write bursts
> system.physmem.perBankRdBursts::3 11534 # Per bank write bursts
> system.physmem.perBankRdBursts::4 11556 # Per bank write bursts
> system.physmem.perBankRdBursts::5 11202 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11589 # Per bank write bursts
> system.physmem.perBankRdBursts::7 11470 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10957 # Per bank write bursts
> system.physmem.perBankRdBursts::9 11574 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11037 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11773 # Per bank write bursts
> system.physmem.perBankRdBursts::12 12032 # Per bank write bursts
> system.physmem.perBankRdBursts::13 13037 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11759 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11481 # Per bank write bursts
> system.physmem.perBankWrBursts::0 13445 # Per bank write bursts
> system.physmem.perBankWrBursts::1 12349 # Per bank write bursts
> system.physmem.perBankWrBursts::2 11384 # Per bank write bursts
> system.physmem.perBankWrBursts::3 11463 # Per bank write bursts
> system.physmem.perBankWrBursts::4 12267 # Per bank write bursts
> system.physmem.perBankWrBursts::5 12371 # Per bank write bursts
> system.physmem.perBankWrBursts::6 11486 # Per bank write bursts
> system.physmem.perBankWrBursts::7 11359 # Per bank write bursts
> system.physmem.perBankWrBursts::8 11596 # Per bank write bursts
> system.physmem.perBankWrBursts::9 12338 # Per bank write bursts
> system.physmem.perBankWrBursts::10 11770 # Per bank write bursts
> system.physmem.perBankWrBursts::11 12080 # Per bank write bursts
> system.physmem.perBankWrBursts::12 12282 # Per bank write bursts
> system.physmem.perBankWrBursts::13 12669 # Per bank write bursts
> system.physmem.perBankWrBursts::14 12453 # Per bank write bursts
> system.physmem.perBankWrBursts::15 13184 # Per bank write bursts
97c97
< system.physmem.totGap 5129942968500 # Total gap between requests
---
> system.physmem.totGap 5125945988000 # Total gap between requests
104c104
< system.physmem.readPktSize::6 185604 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 185555 # Read request sizes (log2)
111,119c111,119
< system.physmem.writePktSize::6 196636 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 170730 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 11911 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 2018 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 400 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 196574 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 170769 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 11917 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2025 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 375 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see
122,126c122,126
< system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 28 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 28 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
159,225c159,225
< system.physmem.wrQLenPdf::15 2574 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4997 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 9722 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 11014 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 11539 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 12555 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 13007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 14095 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 13776 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 14313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 13208 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 12728 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 11239 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 10589 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 8627 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8507 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 8355 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 501 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 411 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 382 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 322 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 228 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 235 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 75289 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 322.860444 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 187.432072 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 341.383638 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 27971 37.15% 37.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17364 23.06% 60.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 7569 10.05% 70.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4193 5.57% 75.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3123 4.15% 79.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1949 2.59% 82.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1359 1.81% 84.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1178 1.56% 85.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10583 14.06% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 75289 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 7789 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 23.801643 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 545.365861 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 7788 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2509 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4824 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 9547 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 10935 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 11433 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 12449 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 12895 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 13963 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 13629 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 14296 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 13176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 12672 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 11348 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 10803 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 9189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 8820 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 8678 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 8475 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 592 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 508 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 443 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 373 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 235 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 156 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 75192 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 323.362060 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 187.476414 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 341.898646 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 27996 37.23% 37.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17297 23.00% 60.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 7451 9.91% 70.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 4205 5.59% 75.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3004 4.00% 79.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2064 2.74% 82.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1408 1.87% 84.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1199 1.59% 85.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10568 14.05% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 75192 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 7811 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 23.734349 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 544.550807 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 7810 99.99% 99.99% # Reads before turning the bus around for writes
227,290c227,288
< system.physmem.rdPerTurnAround::total 7789 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 7789 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 24.959558 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 20.372117 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 24.594707 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 6350 81.53% 81.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 59 0.76% 82.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 17 0.22% 82.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 286 3.67% 86.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 164 2.11% 88.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 59 0.76% 89.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 41 0.53% 89.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 34 0.44% 90.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 175 2.25% 92.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 16 0.21% 92.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 16 0.21% 92.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 13 0.17% 92.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 28 0.36% 93.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 16 0.21% 93.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 10 0.13% 93.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 42 0.54% 94.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 108 1.39% 95.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 9 0.12% 95.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 9 0.12% 95.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 24 0.31% 95.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 141 1.81% 97.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 3 0.04% 97.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 13 0.17% 98.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 4 0.05% 98.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 34 0.44% 98.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 3 0.04% 98.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 10 0.13% 98.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.01% 98.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 14 0.18% 98.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 5 0.06% 98.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.01% 98.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 5 0.06% 98.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 13 0.17% 99.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 10 0.13% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 3 0.04% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 6 0.08% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 11 0.14% 99.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 3 0.04% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 3 0.04% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 5 0.06% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.01% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 3 0.04% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 1 0.01% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::196-199 2 0.03% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 6 0.08% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::204-207 3 0.04% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::220-223 1 0.01% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 1 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 7789 # Writes before turning the bus around for reads
< system.physmem.totQLat 1998636250 # Total ticks spent queuing
< system.physmem.totMemAccLat 5474905000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 927005000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10780.07 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 7811 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 7811 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 24.900269 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 20.294695 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 24.961495 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 6395 81.87% 81.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 66 0.84% 82.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 12 0.15% 82.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 258 3.30% 86.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 186 2.38% 88.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 50 0.64% 89.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 38 0.49% 89.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 45 0.58% 90.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 169 2.16% 92.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 11 0.14% 92.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 12 0.15% 92.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 16 0.20% 92.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 26 0.33% 93.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 16 0.20% 93.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 15 0.19% 93.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 41 0.52% 94.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 93 1.19% 95.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 13 0.17% 95.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 9 0.12% 95.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 19 0.24% 95.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 147 1.88% 97.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 3 0.04% 97.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 13 0.17% 97.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 4 0.05% 98.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 20 0.26% 98.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 9 0.12% 98.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 5 0.06% 98.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 3 0.04% 98.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 27 0.35% 98.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 13 0.17% 99.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 2 0.03% 99.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 4 0.05% 99.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 11 0.14% 99.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 10 0.13% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 4 0.05% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.03% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 5 0.06% 99.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 3 0.04% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 3 0.04% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 2 0.03% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 7 0.09% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 1 0.01% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-187 1 0.01% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 2 0.03% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-211 1 0.01% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::212-215 1 0.01% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-219 1 0.01% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::220-223 7 0.09% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-227 3 0.04% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::228-231 2 0.03% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::248-251 4 0.05% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 7811 # Writes before turning the bus around for reads
> system.physmem.totQLat 1990259250 # Total ticks spent queuing
> system.physmem.totMemAccLat 5466790500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 927075000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10734.08 # Average queueing delay per DRAM burst
292c290
< system.physmem.avgMemAccLat 29530.07 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 29484.08 # Average memory access latency per DRAM burst
302,319c300,317
< system.physmem.avgWrQLen 25.71 # Average write queue length when enqueuing
< system.physmem.readRowHits 152292 # Number of row buffer hits during reads
< system.physmem.writeRowHits 152229 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.29 # Row buffer hit rate for writes
< system.physmem.avgGap 13420738.20 # Average gap between requests
< system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 279697320 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 152612625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 719316000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 633329280 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 129572750835 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 2964303640500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 3430724068320 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.764961 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 4931314948000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 171299960000 # Time in different power states
---
> system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing
> system.physmem.readRowHits 152358 # Number of row buffer hits during reads
> system.physmem.writeRowHits 152360 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 78.32 # Row buffer hit rate for writes
> system.physmem.avgGap 13414176.86 # Average gap between requests
> system.physmem.pageHitRate 80.20 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 277686360 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 151515375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 715759200 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 622883520 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 129454885665 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 2962010423250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 3428034983850 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.761488 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 4927497903250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states
321c319
< system.physmem_0.memoryStateTime::ACT 27328009000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 27281453250 # Time in different power states
323,333c321,331
< system.physmem_1.actEnergy 289487520 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 157954500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 726804000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 626447520 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 129789266760 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2964113714250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 3430766396310 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.773213 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 4930997374750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 171299960000 # Time in different power states
---
> system.physmem_1.actEnergy 290765160 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 158651625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 730470000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 637450560 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 129625961760 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 2961860356500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 3428105486085 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.775242 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 4927247811250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states
335c333
< system.physmem_1.memoryStateTime::ACT 27642592750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 27531190000 # Time in different power states
337,341c335,339
< system.cpu.branchPred.lookups 86966196 # Number of BP lookups
< system.cpu.branchPred.condPredicted 86966196 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 908530 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 80060297 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 78222813 # Number of BTB hits
---
> system.cpu.branchPred.lookups 87010872 # Number of BP lookups
> system.cpu.branchPred.condPredicted 87010872 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 908907 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 80241948 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 78260393 # Number of BTB hits
343,345c341,343
< system.cpu.branchPred.BTBHitPct 97.704875 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1554803 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 179885 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 97.530525 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1567280 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 181222 # Number of incorrect RAS predictions.
348c346
< system.cpu.numCycles 449725865 # number of cpu cycles simulated
---
> system.cpu.numCycles 449757362 # number of cpu cycles simulated
351,367c349,365
< system.cpu.fetch.icacheStallCycles 27729826 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 429316628 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 86966196 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 79777616 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 417943861 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1905694 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 153883 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 50061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 216755 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 126625 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 694 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 9209956 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 450181 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 5437 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 447174552 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.894587 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.051890 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 27680627 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 429642410 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 87010872 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 79827673 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 418150440 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1906654 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 150208 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 58666 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 213443 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 140 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 9233721 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 451702 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 447207287 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.895606 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.052695 # Number of instructions fetched each cycle (Total)
369,377c367,375
< system.cpu.fetch.rateDist::0 281545500 62.96% 62.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2299594 0.51% 63.48% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 72183543 16.14% 79.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 1609599 0.36% 79.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2153830 0.48% 80.46% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 2329535 0.52% 80.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 1534724 0.34% 81.32% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1901427 0.43% 81.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 81616800 18.25% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 281559277 62.96% 62.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2214583 0.50% 63.45% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 72218429 16.15% 79.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 1625336 0.36% 79.97% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2151026 0.48% 80.45% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 2311115 0.52% 80.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 1533968 0.34% 81.31% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1910699 0.43% 81.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 81682854 18.27% 100.00% # Number of instructions fetched each cycle (Total)
381,423c379,421
< system.cpu.fetch.rateDist::total 447174552 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.193376 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.954618 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 23090202 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 264882686 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 150813511 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 7435306 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 952847 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 838903899 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 952847 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 25942831 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 223326641 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 13232428 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 154708804 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 29011001 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 835406292 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 477425 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 12418228 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 176585 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 13740194 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 997876395 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1814508658 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1115444420 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 102 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 964480017 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 33396376 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 469202 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 473127 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 39031385 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 17359783 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 10198929 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1317086 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1098616 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 829832373 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1210818 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 824505871 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 240863 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 23642425 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 36460999 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 154878 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 447174552 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.843812 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.418056 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 447207287 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.193462 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.955276 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 23009193 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 264931793 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 150859313 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 7453661 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 953327 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 839350026 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 953327 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 25875798 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 223334745 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 13198087 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 154759437 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 29085893 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 835811014 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 482001 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 12419616 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 206377 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 13783403 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 998347758 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1815644422 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1116079946 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 122 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 964783456 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 33564300 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 467714 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 471747 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 39093495 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 17396694 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 10208602 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1304613 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1095322 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 830247357 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1203823 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 824890478 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 241321 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 23772173 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 36627244 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 152885 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 447207287 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.844537 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 2.418419 # Number of insts issued each cycle
425,433c423,431
< system.cpu.iq.issued_per_cycle::0 262851560 58.78% 58.78% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 13883927 3.10% 61.89% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 10098896 2.26% 64.14% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 6926055 1.55% 65.69% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 74362880 16.63% 82.32% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 4459374 1.00% 83.32% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 72818710 16.28% 99.60% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 1199863 0.27% 99.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 573287 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 262823455 58.77% 58.77% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 13859186 3.10% 61.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 10127573 2.26% 64.13% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 6921797 1.55% 65.68% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 74369123 16.63% 82.31% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 4467728 1.00% 83.31% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 72848553 16.29% 99.60% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 1214671 0.27% 99.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 575201 0.13% 100.00% # Number of insts issued each cycle
437c435
< system.cpu.iq.issued_per_cycle::total 447174552 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 447207287 # Number of insts issued each cycle
439,469c437,467
< system.cpu.iq.fu_full::IntAlu 1983031 71.93% 71.93% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 252 0.01% 71.94% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 1287 0.05% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 612199 22.21% 94.19% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 160068 5.81% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 2002012 72.04% 72.04% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 252 0.01% 72.05% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 1516 0.05% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.10% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 615311 22.14% 94.24% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 160020 5.76% 100.00% # attempts to use FU when none available
472,475c470,473
< system.cpu.iq.FU_type_0::No_OpClass 294191 0.04% 0.04% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 796088573 96.55% 96.59% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 150664 0.02% 96.61% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 125614 0.02% 96.62% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 292641 0.04% 0.04% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 796440241 96.55% 96.59% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 150873 0.02% 96.60% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 125700 0.02% 96.62% # Type of FU issued
502,503c500,501
< system.cpu.iq.FU_type_0::MemRead 18441786 2.24% 98.86% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 9405043 1.14% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 18469737 2.24% 98.86% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 9411286 1.14% 100.00% # Type of FU issued
506,518c504,516
< system.cpu.iq.FU_type_0::total 824505871 # Type of FU issued
< system.cpu.iq.rate 1.833352 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 2756837 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.003344 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 2099183812 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 854698119 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 819923286 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 181 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 826968435 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1878873 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 824890478 # Type of FU issued
> system.cpu.iq.rate 1.834079 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 2779111 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.003369 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 2100008470 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 855235960 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 820301631 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 204 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 226 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 827376851 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1872015 # Number of loads that had data forwarded from stores
520,523c518,521
< system.cpu.iew.lsq.thread0.squashedLoads 3357342 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 15595 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 14483 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1769318 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 3394675 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 15480 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 14595 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1778587 # Number of stores squashed
526,527c524,525
< system.cpu.iew.lsq.thread0.rescheduledLoads 2224742 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 72242 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 2224947 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 72059 # Number of times an access to memory failed due to the cache being blocked
529,545c527,543
< system.cpu.iew.iewSquashCycles 952847 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 205624678 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 9408932 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 831043191 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 186605 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 17359783 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 10198929 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 713805 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 415277 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 8093737 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 14483 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 519848 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 541033 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1060881 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 822872781 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 18039155 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1498773 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 953327 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 205633916 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 9395655 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 831451180 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 157138 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 17396694 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 10208602 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 706837 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 415978 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 8079838 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 14595 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 523025 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 540470 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1063495 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 823253062 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 18064803 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1501922 # Number of squashed instructions skipped in execute
548,555c546,553
< system.cpu.iew.exec_refs 27216659 # number of memory reference insts executed
< system.cpu.iew.exec_branches 83327917 # Number of branches executed
< system.cpu.iew.exec_stores 9177504 # Number of stores executed
< system.cpu.iew.exec_rate 1.829721 # Inst execution rate
< system.cpu.iew.wb_sent 822362005 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 819923336 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 641186937 # num instructions producing a value
< system.cpu.iew.wb_consumers 1050770759 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 27249763 # number of memory reference insts executed
> system.cpu.iew.exec_branches 83367725 # Number of branches executed
> system.cpu.iew.exec_stores 9184960 # Number of stores executed
> system.cpu.iew.exec_rate 1.830438 # Inst execution rate
> system.cpu.iew.wb_sent 822742058 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 820301688 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 641478984 # num instructions producing a value
> system.cpu.iew.wb_consumers 1051241156 # num instructions consuming a value
557,558c555,556
< system.cpu.iew.wb_rate 1.823163 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.610206 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.823876 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.610211 # average fanout of values written-back
560,565c558,563
< system.cpu.commit.commitSquashedInsts 24478012 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1055940 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 920864 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 443494014 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.818449 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.675035 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 24588739 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1050938 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 921334 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 443513076 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.818961 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.675251 # Number of insts commited each cycle
567,575c565,573
< system.cpu.commit.committed_per_cycle::0 272650089 61.48% 61.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 11209358 2.53% 64.01% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3583153 0.81% 64.81% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 74560256 16.81% 81.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 2436163 0.55% 82.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1608243 0.36% 82.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 951229 0.21% 82.75% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 71042725 16.02% 98.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 5452798 1.23% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 272623912 61.47% 61.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 11196719 2.52% 63.99% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3582296 0.81% 64.80% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 74597527 16.82% 81.62% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 2432522 0.55% 82.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1609310 0.36% 82.53% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 947533 0.21% 82.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 71068767 16.02% 98.77% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 5454490 1.23% 100.00% # Number of insts commited each cycle
579,581c577,579
< system.cpu.commit.committed_per_cycle::total 443494014 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 407987808 # Number of instructions committed
< system.cpu.commit.committedOps 806471132 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 443513076 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 408140259 # Number of instructions committed
> system.cpu.commit.committedOps 806733017 # Number of ops (including micro ops) committed
583,586c581,584
< system.cpu.commit.refs 22432051 # Number of memory references committed
< system.cpu.commit.loads 14002440 # Number of loads committed
< system.cpu.commit.membars 475347 # Number of memory barriers committed
< system.cpu.commit.branches 82201961 # Number of branches committed
---
> system.cpu.commit.refs 22432033 # Number of memory references committed
> system.cpu.commit.loads 14002018 # Number of loads committed
> system.cpu.commit.membars 475437 # Number of memory barriers committed
> system.cpu.commit.branches 82233213 # Number of branches committed
588,593c586,591
< system.cpu.commit.int_insts 735281139 # Number of committed integer instructions.
< system.cpu.commit.function_calls 1155976 # Number of function calls committed.
< system.cpu.commit.op_class_0::No_OpClass 174273 0.02% 0.02% # Class of committed instruction
< system.cpu.commit.op_class_0::IntAlu 783598184 97.16% 97.19% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 145019 0.02% 97.20% # Class of committed instruction
< system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction
---
> system.cpu.commit.int_insts 735520454 # Number of committed integer instructions.
> system.cpu.commit.function_calls 1156067 # Number of function calls committed.
> system.cpu.commit.op_class_0::No_OpClass 171671 0.02% 0.02% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 783865362 97.17% 97.19% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 145082 0.02% 97.20% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 121451 0.02% 97.22% # Class of committed instruction
620,621c618,619
< system.cpu.commit.op_class_0::MemRead 14002440 1.74% 98.95% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 8429611 1.05% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 13999436 1.74% 98.96% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 8430015 1.04% 100.00% # Class of committed instruction
624,625c622,623
< system.cpu.commit.op_class_0::total 806471132 # Class of committed instruction
< system.cpu.commit.bw_lim_events 5452798 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 806733017 # Class of committed instruction
> system.cpu.commit.bw_lim_events 5454490 # number cycles where commit BW limit reached
627,649c625,647
< system.cpu.rob.rob_reads 1268912158 # The number of ROB reads
< system.cpu.rob.rob_writes 1665595320 # The number of ROB writes
< system.cpu.timesIdled 297665 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 2551313 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 9810160420 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 407987808 # Number of Instructions Simulated
< system.cpu.committedOps 806471132 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 1.102302 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.102302 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.907192 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.907192 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1092777925 # number of integer regfile reads
< system.cpu.int_regfile_writes 656276714 # number of integer regfile writes
< system.cpu.fp_regfile_reads 50 # number of floating regfile reads
< system.cpu.cc_regfile_reads 416321461 # number of cc regfile reads
< system.cpu.cc_regfile_writes 322134346 # number of cc regfile writes
< system.cpu.misc_regfile_reads 265712042 # number of misc regfile reads
< system.cpu.misc_regfile_writes 402822 # number of misc regfile writes
< system.cpu.dcache.tags.replacements 1660901 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.996168 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 19148306 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1661413 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 11.525314 # Average number of references to valid blocks.
---
> system.cpu.rob.rob_reads 1269302111 # The number of ROB reads
> system.cpu.rob.rob_writes 1666357608 # The number of ROB writes
> system.cpu.timesIdled 293383 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 2550075 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 9802132382 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 408140259 # Number of Instructions Simulated
> system.cpu.committedOps 806733017 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 1.101968 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.101968 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.907468 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.907468 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1093345902 # number of integer regfile reads
> system.cpu.int_regfile_writes 656583711 # number of integer regfile writes
> system.cpu.fp_regfile_reads 57 # number of floating regfile reads
> system.cpu.cc_regfile_reads 416569502 # number of cc regfile reads
> system.cpu.cc_regfile_writes 322266839 # number of cc regfile writes
> system.cpu.misc_regfile_reads 265844677 # number of misc regfile reads
> system.cpu.misc_regfile_writes 400270 # number of misc regfile writes
> system.cpu.dcache.tags.replacements 1661069 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.997995 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 19180634 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1661581 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 11.543605 # Average number of references to valid blocks.
651,653c649,651
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.996168 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.997995 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
655,657c653,655
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
659,717c657,715
< system.cpu.dcache.tags.tag_accesses 88407170 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88407170 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 10993462 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 10993462 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8086554 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8086554 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 65615 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 65615 # number of SoftPFReq hits
< system.cpu.dcache.demand_hits::cpu.data 19080016 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 19080016 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 19145631 # number of overall hits
< system.cpu.dcache.overall_hits::total 19145631 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1801010 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1801010 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 333393 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 333393 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 406403 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 406403 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 2134403 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2134403 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2540806 # number of overall misses
< system.cpu.dcache.overall_misses::total 2540806 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 26556774697 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 26556774697 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 12861853063 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 12861853063 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 39418627760 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39418627760 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39418627760 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39418627760 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 12794472 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 12794472 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8419947 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8419947 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 472018 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 472018 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21214419 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21214419 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21686437 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21686437 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140765 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.140765 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039596 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.039596 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.860990 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.860990 # miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.100611 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.100611 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.117161 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.117161 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.489862 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.489862 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38578.653610 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38578.653610 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 18468.221681 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 18468.221681 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 15514.221771 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 15514.221771 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 376585 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 88533012 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88533012 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 11025921 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11025921 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8086239 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8086239 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 65769 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 65769 # number of SoftPFReq hits
> system.cpu.dcache.demand_hits::cpu.data 19112160 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 19112160 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 19177929 # number of overall hits
> system.cpu.dcache.overall_hits::total 19177929 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1799370 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1799370 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 334097 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 334097 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 406460 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 406460 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 2133467 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2133467 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2539927 # number of overall misses
> system.cpu.dcache.overall_misses::total 2539927 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 26521555176 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 26521555176 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 12869537398 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 12869537398 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39391092574 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39391092574 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39391092574 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39391092574 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 12825291 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12825291 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8420336 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8420336 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 472229 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 472229 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21245627 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21245627 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21717856 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21717856 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140299 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.140299 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039677 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.039677 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.860726 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.860726 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.100419 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.100419 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.116951 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.116951 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14739.356095 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14739.356095 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38520.362045 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38520.362045 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 18463.417796 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 18463.417796 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 15508.749887 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 15508.749887 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 376355 # number of cycles access was blocked
719c717
< system.cpu.dcache.blocked::no_mshrs 40128 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 40236 # number of cycles access was blocked
721c719
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.384594 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353688 # average number of cycles each access was blocked
725,780c723,778
< system.cpu.dcache.writebacks::writebacks 1561149 # number of writebacks
< system.cpu.dcache.writebacks::total 1561149 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829563 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 829563 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44151 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 44151 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 873714 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 873714 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 873714 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 873714 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971447 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 971447 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289242 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 289242 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402941 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 402941 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1260689 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1260689 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1663630 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1663630 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12263679766 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 12263679766 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11196249664 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11196249664 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5590634504 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5590634504 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459929430 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23459929430 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050563934 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 29050563934 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390328000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390328000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564382000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564382000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954710000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954710000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075927 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075927 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034352 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034352 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853656 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853656 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059426 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.059426 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076713 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.076713 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12624.136742 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12624.136742 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38708.934608 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38708.934608 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13874.573459 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13874.573459 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18608.815838 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18608.815838 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17462.154406 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 17462.154406 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 1562436 # number of writebacks
> system.cpu.dcache.writebacks::total 1562436 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 828680 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 828680 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 43973 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 43973 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 872653 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 872653 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 872653 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 872653 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970690 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 970690 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290124 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 290124 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403005 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 403005 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1260814 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1260814 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1663819 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1663819 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12262338773 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 12262338773 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11212126848 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11212126848 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584774002 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584774002 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23474465621 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23474465621 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29059239623 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 29059239623 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97396245500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97396245500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2569003000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2569003000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99965248500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 99965248500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075686 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075686 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034455 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034455 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853410 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853410 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059345 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.059345 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076611 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.076611 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12632.600287 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12632.600287 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38645.981884 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38645.981884 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13857.828072 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13857.828072 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18618.500128 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18618.500128 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17465.385131 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 17465.385131 # average overall mshr miss latency
788,797c786,795
< system.cpu.dtb_walker_cache.tags.replacements 74149 # number of replacements
< system.cpu.dtb_walker_cache.tags.tagsinuse 15.785870 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 117599 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.sampled_refs 74165 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.avg_refs 1.585640 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785870 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986617 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986617 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
---
> system.cpu.dtb_walker_cache.tags.replacements 76914 # number of replacements
> system.cpu.dtb_walker_cache.tags.tagsinuse 15.799700 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 113377 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.sampled_refs 76929 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.avg_refs 1.473788 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 194539504500 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.799700 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.987481 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_percent::total 0.987481 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
799c797
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
---
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
801,839c799,837
< system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dtb_walker_cache.tags.tag_accesses 460921 # Number of tag accesses
< system.cpu.dtb_walker_cache.tags.data_accesses 460921 # Number of data accesses
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117599 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 117599 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117599 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 117599 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117599 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 117599 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75241 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 75241 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75241 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 75241 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75241 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 75241 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935995702 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935995702 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935995702 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 935995702 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935995702 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 935995702 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192840 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 192840 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192840 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 192840 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192840 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 192840 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.390173 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.390173 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.390173 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.390173 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.390173 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.390173 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12439.968927 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12439.968927 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12439.968927 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12439.968927 # average overall miss latency
---
> system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
> system.cpu.dtb_walker_cache.tags.tag_accesses 460761 # Number of tag accesses
> system.cpu.dtb_walker_cache.tags.data_accesses 460761 # Number of data accesses
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113400 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 113400 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113400 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 113400 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113400 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 113400 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77987 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 77987 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77987 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 77987 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77987 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 77987 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 949066206 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 949066206 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 949066206 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 949066206 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 949066206 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 949066206 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191387 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 191387 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191387 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 191387 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191387 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 191387 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407483 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407483 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407483 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407483 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407483 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407483 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12169.543719 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12169.543719 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12169.543719 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12169.543719 # average overall miss latency
848,873c846,871
< system.cpu.dtb_walker_cache.writebacks::writebacks 14429 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 14429 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75241 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75241 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75241 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 75241 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75241 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 75241 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 785378468 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 785378468 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 785378468 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 785378468 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 785378468 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 785378468 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.390173 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.390173 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.390173 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10438.171582 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 21202 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 21202 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77987 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77987 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77987 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 77987 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77987 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 77987 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 792970936 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 792970936 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 792970936 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 792970936 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 792970936 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 792970936 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407483 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407483 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407483 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10167.988716 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency
875,883c873,881
< system.cpu.icache.tags.replacements 1000738 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.865289 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 8144093 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1001250 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 8.133926 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 147645528250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.865289 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.995831 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.995831 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 998047 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.614894 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 8172291 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 998559 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 8.184084 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 147683889250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.614894 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.995342 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.995342 # Average percentage of cache occupancy
885,886c883,884
< system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
889,927c887,925
< system.cpu.icache.tags.tag_accesses 10211253 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 10211253 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 8144093 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 8144093 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 8144093 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 8144093 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 8144093 # number of overall hits
< system.cpu.icache.overall_hits::total 8144093 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1065861 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1065861 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1065861 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1065861 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1065861 # number of overall misses
< system.cpu.icache.overall_misses::total 1065861 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14781190073 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14781190073 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14781190073 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14781190073 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14781190073 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14781190073 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 9209954 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 9209954 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 9209954 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 9209954 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 9209954 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 9209954 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115729 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.115729 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.115729 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.115729 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.115729 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.115729 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13867.840247 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13867.840247 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13867.840247 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13867.840247 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13867.840247 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13867.840247 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 8856 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 10232340 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 10232340 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 8172291 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 8172291 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 8172291 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 8172291 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 8172291 # number of overall hits
> system.cpu.icache.overall_hits::total 8172291 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1061429 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1061429 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1061429 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1061429 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1061429 # number of overall misses
> system.cpu.icache.overall_misses::total 1061429 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14726887378 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14726887378 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14726887378 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14726887378 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14726887378 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14726887378 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 9233720 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 9233720 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 9233720 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 9233720 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 9233720 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 9233720 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.114951 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.114951 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.114951 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.114951 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.114951 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.114951 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13874.585467 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13874.585467 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13874.585467 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13874.585467 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13874.585467 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13874.585467 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 7528 # number of cycles access was blocked
929c927
< system.cpu.icache.blocked::no_mshrs 270 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked
931c929
< system.cpu.icache.avg_blocked_cycles::no_mshrs 32.800000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 23.974522 # average number of cycles each access was blocked
935,964c933,962
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 64562 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 64562 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 64562 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 64562 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 64562 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 64562 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001299 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1001299 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1001299 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1001299 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1001299 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1001299 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12129331538 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12129331538 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12129331538 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12129331538 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12129331538 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12129331538 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108719 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.108719 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.108719 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.595977 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.595977 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62809 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 62809 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 62809 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 62809 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 62809 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 62809 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998620 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 998620 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 998620 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 998620 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 998620 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 998620 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12093795712 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12093795712 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12093795712 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12093795712 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12093795712 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12093795712 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108149 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.108149 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.108149 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.508213 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.508213 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.508213 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.508213 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.508213 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.508213 # average overall mshr miss latency
966,974c964,972
< system.cpu.itb_walker_cache.tags.replacements 16111 # number of replacements
< system.cpu.itb_walker_cache.tags.tagsinuse 6.022557 # Cycle average of tags in use
< system.cpu.itb_walker_cache.tags.total_refs 25852 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.sampled_refs 16125 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.tags.avg_refs 1.603225 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.warmup_cycle 5103942671000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.022557 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376410 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.376410 # Average percentage of cache occupancy
---
> system.cpu.itb_walker_cache.tags.replacements 15839 # number of replacements
> system.cpu.itb_walker_cache.tags.tagsinuse 6.015286 # Cycle average of tags in use
> system.cpu.itb_walker_cache.tags.total_refs 25359 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.sampled_refs 15853 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.tags.avg_refs 1.599634 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.warmup_cycle 5101686667000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.015286 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375955 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.375955 # Average percentage of cache occupancy
976,977c974,975
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
---
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
980,983c978,981
< system.cpu.itb_walker_cache.tags.tag_accesses 102724 # Number of tag accesses
< system.cpu.itb_walker_cache.tags.data_accesses 102724 # Number of data accesses
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25863 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 25863 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.tags.tag_accesses 101130 # Number of tag accesses
> system.cpu.itb_walker_cache.tags.data_accesses 101130 # Number of data accesses
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25498 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 25498 # number of ReadReq hits
986,1003c984,1001
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25865 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 25865 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25865 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 25865 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16998 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 16998 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16998 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 16998 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16998 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 16998 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 202038998 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 202038998 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 202038998 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 202038998 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 202038998 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 202038998 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42861 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 42861 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25500 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 25500 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25500 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 25500 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16710 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 16710 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16710 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 16710 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16710 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 16710 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 189443244 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 189443244 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 189443244 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 189443244 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 189443244 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 189443244 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42208 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 42208 # number of ReadReq accesses(hits+misses)
1006,1021c1004,1019
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42863 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 42863 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42863 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 42863 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.396584 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.396584 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.396566 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.396566 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.396566 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.396566 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11886.045299 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11886.045299 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11886.045299 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11886.045299 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11886.045299 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11886.045299 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42210 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 42210 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42210 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 42210 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.395897 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.395897 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.395878 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.395878 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.395878 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.395878 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11337.118133 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11337.118133 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11337.118133 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11337.118133 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11337.118133 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11337.118133 # average overall miss latency
1030,1055c1028,1053
< system.cpu.itb_walker_cache.writebacks::writebacks 2256 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 2256 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16998 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16998 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16998 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 16998 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16998 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 16998 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 168025032 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 168025032 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 168025032 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 168025032 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 168025032 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 168025032 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.396584 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.396584 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.396566 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.396566 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9884.988352 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 3245 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 3245 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16710 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16710 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16710 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 16710 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16710 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 16710 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 156005776 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 156005776 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 156005776 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 156005776 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 156005776 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 156005776 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.395897 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.395897 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.395878 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.395878 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.395878 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.395878 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9336.072771 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9336.072771 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9336.072771 # average overall mshr miss latency
1057,1061c1055,1059
< system.cpu.l2cache.tags.replacements 112974 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64818.744711 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3837920 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 177018 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 21.680959 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 112952 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64819.666116 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3838789 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 176912 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 21.698862 # Average number of references to valid blocks.
1063,1069c1061,1067
< system.cpu.l2cache.tags.occ_blocks::writebacks 50388.015751 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.441797 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125760 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3267.225445 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 11145.935958 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.768860 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50506.549042 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 19.197840 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135379 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3269.774951 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 11024.008903 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.770669 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000293 # Average percentage of cache occupancy
1071,1103c1069,1101
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049854 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.170073 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.989056 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 64044 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 598 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3343 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7275 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52773 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977234 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 35081259 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 35081259 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69593 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 14758 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 984803 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1337710 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2406864 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1577834 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1577834 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 300 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 300 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 153385 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 153385 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 69593 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 14758 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 984803 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1491095 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2560249 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 69593 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 14758 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 984803 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1491095 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2560249 # number of overall hits
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049893 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.168213 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.989070 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 594 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5550 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54407 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 35127054 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 35127054 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69856 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13439 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 982174 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1337175 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2402644 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1586883 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1586883 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 154161 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 154161 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 69856 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 13439 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 982174 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1491336 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2556805 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 69856 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 13439 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 982174 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1491336 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2556805 # number of overall hits
1106,1112c1104,1110
< system.cpu.l2cache.ReadReq_misses::cpu.inst 16393 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 35895 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 52361 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133756 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133756 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 16339 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 35825 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 52237 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1483 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1483 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133848 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133848 # number of ReadExReq misses
1115,1117c1113,1115
< system.cpu.l2cache.demand_misses::cpu.inst 16393 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 169651 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 186117 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 16339 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 169673 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 186085 # number of demand (read+write) misses
1120,1200c1118,1198
< system.cpu.l2cache.overall_misses::cpu.inst 16393 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 169651 # number of overall misses
< system.cpu.l2cache.overall_misses::total 186117 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6414250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 407500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1255247500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2834689998 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 4096759248 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17266314 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 17266314 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9330791213 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9330791213 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6414250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 407500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1255247500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12165481211 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 13427550461 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6414250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 407500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1255247500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12165481211 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 13427550461 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69661 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 14763 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001196 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1373605 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2459225 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1577834 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1577834 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1744 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1744 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 287141 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 287141 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69661 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 14763 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1001196 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1660746 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2746366 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69661 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 14763 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1001196 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1660746 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2746366 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000976 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000339 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016373 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026132 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021292 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.827982 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.827982 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.465820 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.465820 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000976 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000339 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016373 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102153 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.067768 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000976 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000339 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016373 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102153 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.067768 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 94327.205882 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81500 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76572.164948 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78971.723025 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 78240.660950 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11957.281163 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11957.281163 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69759.795546 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69759.795546 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 94327.205882 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76572.164948 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71708.868271 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72145.749507 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 94327.205882 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76572.164948 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71708.868271 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72145.749507 # average overall miss latency
---
> system.cpu.l2cache.overall_misses::cpu.inst 16339 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 169673 # number of overall misses
> system.cpu.l2cache.overall_misses::total 186085 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6082250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 393250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1247981750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2833529749 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 4087986999 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17399310 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 17399310 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9336961710 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9336961710 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6082250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 393250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1247981750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12170491459 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 13424948709 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6082250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 393250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1247981750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12170491459 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 13424948709 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69924 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13444 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 998513 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1373000 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2454881 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1586883 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1586883 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1792 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1792 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 288009 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 288009 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69924 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 13444 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 998513 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1661009 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2742890 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69924 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 13444 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 998513 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1661009 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2742890 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000972 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000372 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016363 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026092 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021279 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.827567 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.827567 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464735 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.464735 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000972 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000372 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016363 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102151 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.067843 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000972 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000372 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016363 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102151 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.067843 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89444.852941 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78650 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76380.546545 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79093.642680 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.456630 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11732.508429 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11732.508429 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69757.947149 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69757.947149 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89444.852941 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78650 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76380.546545 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71729.099262 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72144.174485 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89444.852941 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78650 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76380.546545 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71729.099262 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72144.174485 # average overall miss latency
1209,1219c1207,1217
< system.cpu.l2cache.writebacks::writebacks 103249 # number of writebacks
< system.cpu.l2cache.writebacks::total 103249 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 103187 # number of writebacks
> system.cpu.l2cache.writebacks::total 103187 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
1222,1228c1220,1226
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16392 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35893 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 52358 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133756 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133756 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16337 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35822 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 52232 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1483 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1483 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133848 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133848 # number of ReadExReq MSHR misses
1231,1233c1229,1231
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16392 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 169649 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 186114 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16337 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 169670 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 186080 # number of demand (read+write) MSHR misses
1236,1301c1234,1299
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16392 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 169649 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 186114 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5576250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 344500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049607750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2389031498 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3444559998 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15363423 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15363423 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7651301287 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7651301287 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5576250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 344500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049607750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10040332785 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 11095861285 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5576250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 344500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049607750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10040332785 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 11095861285 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275596500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275596500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397352000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397352000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672948500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672948500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026131 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021290 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827982 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827982 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465820 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465820 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.067767 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.067767 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68900 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64031.707540 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66559.816622 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65788.609152 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10639.489612 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10639.489612 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57203.424796 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57203.424796 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16337 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 169670 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 186080 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5240250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 330750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1042946750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2388969999 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3437487749 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15771463 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15771463 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7656264290 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7656264290 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5240250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 330750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1042946750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10045234289 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11093752039 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5240250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 330750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1042946750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10045234289 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11093752039 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89281194000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89281194000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401486500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401486500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91682680500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91682680500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026090 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021277 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827567 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827567 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464735 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464735 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102149 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.067841 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102149 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.067841 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66150 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63839.551325 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66690.022863 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65811.911261 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10634.836817 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10634.836817 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57201.185599 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57201.185599 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66150 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63839.551325 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59204.539925 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.185936 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66150 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63839.551325 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59204.539925 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.185936 # average overall mshr miss latency
1309,1313c1307,1311
< system.cpu.toL2Bus.trans_dist::ReadReq 3078150 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3077612 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 13891 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 13891 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1577834 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 3077249 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3076704 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 13905 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 13905 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1586883 # Transaction distribution
1315,1333c1313,1331
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2215 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2215 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 287149 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 287149 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002495 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6134281 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34017 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159331 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8330124 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64076544 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208017731 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1089216 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5381760 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 278565251 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 57093 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4382652 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.010869 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.103688 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 288016 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 288016 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1997133 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6136134 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 33399 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 169113 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8335779 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63904832 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208116125 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1068096 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5832064 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 278921117 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 60473 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4391663 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.010846 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.103577 # Request fanout histogram
1338,1339c1336,1337
< system.cpu.toL2Bus.snoop_fanout::3 4335015 98.91% 98.91% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 47637 1.09% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 4344032 98.92% 98.92% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 47631 1.08% 100.00% # Request fanout histogram
1343,1344c1341,1342
< system.cpu.toL2Bus.snoop_fanout::total 4382652 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4064000382 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 4391663 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4077594873 # Layer occupancy (ticks)
1346c1344
< system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 562500 # Layer occupancy (ticks)
1348c1346
< system.cpu.toL2Bus.respLayer0.occupancy 1506120456 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1502063776 # Layer occupancy (ticks)
1350c1348
< system.cpu.toL2Bus.respLayer1.occupancy 3144694054 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3145123125 # Layer occupancy (ticks)
1352c1350
< system.cpu.toL2Bus.respLayer2.occupancy 25505983 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 25073734 # Layer occupancy (ticks)
1354c1352
< system.cpu.toL2Bus.respLayer3.occupancy 112929117 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 117041135 # Layer occupancy (ticks)
1356,1359c1354,1357
< system.iobus.trans_dist::ReadReq 225688 # Transaction distribution
< system.iobus.trans_dist::ReadResp 225688 # Transaction distribution
< system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
< system.iobus.trans_dist::WriteResp 11001 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 225706 # Transaction distribution
> system.iobus.trans_dist::ReadResp 225706 # Transaction distribution
> system.iobus.trans_dist::WriteReq 57738 # Transaction distribution
> system.iobus.trans_dist::WriteResp 11018 # Transaction distribution
1361,1362c1359,1360
< system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
< system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
---
> system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
> system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
1365c1363
< system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
1375c1373
< system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1381,1386c1379,1384
< system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95274 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95274 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 570106 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 471626 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 570174 # Packet count per connected master and slave (bytes)
1389c1387
< system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
1399c1397
< system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1405,1411c1403,1409
< system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027880 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027880 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 3276514 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 3918684 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.bridge.master::total 242096 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 3276500 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 3915656 # Layer occupancy (ticks)
1417c1415
< system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
1437c1435
< system.iobus.reqLayer14.occupancy 20719000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1447c1445
< system.iobus.reqLayer19.occupancy 448342458 # Layer occupancy (ticks)
---
> system.iobus.reqLayer19.occupancy 448351206 # Layer occupancy (ticks)
1451c1449
< system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 460608000 # Layer occupancy (ticks)
1453c1451
< system.iobus.respLayer1.occupancy 52374503 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 52362260 # Layer occupancy (ticks)
1455c1453
< system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
---
> system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
1457,1458c1455,1456
< system.iocache.tags.replacements 47582 # number of replacements
< system.iocache.tags.tagsinuse 0.103930 # Cycle average of tags in use
---
> system.iocache.tags.replacements 47576 # number of replacements
> system.iocache.tags.tagsinuse 0.091535 # Cycle average of tags in use
1460c1458
< system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks.
1462,1465c1460,1463
< system.iocache.tags.warmup_cycle 4992992710000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103930 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.006496 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 4992994629000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091535 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005721 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.005721 # Average percentage of cache occupancy
1469,1472c1467,1470
< system.iocache.tags.tag_accesses 428733 # Number of tag accesses
< system.iocache.tags.data_accesses 428733 # Number of data accesses
< system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 917 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 428679 # Number of tag accesses
> system.iocache.tags.data_accesses 428679 # Number of data accesses
> system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
1475,1488c1473,1486
< system.iocache.demand_misses::pc.south_bridge.ide 917 # number of demand (read+write) misses
< system.iocache.demand_misses::total 917 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 917 # number of overall misses
< system.iocache.overall_misses::total 917 # number of overall misses
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152376946 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 152376946 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12347668009 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 12347668009 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 152376946 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 152376946 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 152376946 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 152376946 # number of overall miss cycles
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::pc.south_bridge.ide 911 # number of demand (read+write) misses
> system.iocache.demand_misses::total 911 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 911 # number of overall misses
> system.iocache.overall_misses::total 911 # number of overall misses
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147981947 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 147981947 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12360245999 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 12360245999 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 147981947 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 147981947 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 147981947 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 147981947 # number of overall miss cycles
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
1491,1494c1489,1492
< system.iocache.demand_accesses::pc.south_bridge.ide 917 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 917 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 917 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 917 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 911 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 911 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 911 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 911 # number of overall (read+write) accesses
1503,1511c1501,1509
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 166168.970556 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264290.839234 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 264290.839234 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 166168.970556 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 166168.970556 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 70541 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 162439.019759 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264560.059910 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 264560.059910 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 162439.019759 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 162439.019759 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 70832 # number of cycles access was blocked
1513c1511
< system.iocache.blocked::no_mshrs 9150 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 9173 # number of cycles access was blocked
1515c1513
< system.iocache.avg_blocked_cycles::no_mshrs 7.709399 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 7.721792 # average number of cycles each access was blocked
1521,1522c1519,1520
< system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
1525,1536c1523,1534
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 917 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 917 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 917 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 917 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 104665946 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918222015 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918222015 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 104665946 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 104665946 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 911 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 911 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 911 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 911 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 100584447 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9930786019 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9930786019 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 100584447 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 100584447 # number of overall MSHR miss cycles
1545,1552c1543,1550
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 114139.526718 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212290.710938 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212290.710938 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 110411.028540 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212559.632256 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212559.632256 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency
1554,1558c1552,1556
< system.membus.trans_dist::ReadReq 662691 # Transaction distribution
< system.membus.trans_dist::ReadResp 662685 # Transaction distribution
< system.membus.trans_dist::WriteReq 13891 # Transaction distribution
< system.membus.trans_dist::WriteResp 13891 # Transaction distribution
< system.membus.trans_dist::Writeback 149916 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 662583 # Transaction distribution
> system.membus.trans_dist::ReadResp 662574 # Transaction distribution
> system.membus.trans_dist::WriteReq 13905 # Transaction distribution
> system.membus.trans_dist::WriteResp 13905 # Transaction distribution
> system.membus.trans_dist::Writeback 149854 # Transaction distribution
1561,1583c1559,1581
< system.membus.trans_dist::UpgradeReq 2202 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 1731 # Transaction distribution
< system.membus.trans_dist::ReadExReq 133471 # Transaction distribution
< system.membus.trans_dist::ReadExResp 133469 # Transaction distribution
< system.membus.trans_dist::MessageReq 1644 # Transaction distribution
< system.membus.trans_dist::MessageResp 1644 # Transaction distribution
< system.membus.trans_dist::BadAddressError 6 # Transaction distribution
< system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478147 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724773 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1869528 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18458240 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20250435 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::UpgradeReq 2216 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1773 # Transaction distribution
> system.membus.trans_dist::ReadExReq 133558 # Transaction distribution
> system.membus.trans_dist::ReadExResp 133558 # Transaction distribution
> system.membus.trans_dist::MessageReq 1643 # Transaction distribution
> system.membus.trans_dist::MessageResp 1643 # Transaction distribution
> system.membus.trans_dist::BadAddressError 9 # Transaction distribution
> system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471626 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478050 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724758 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141461 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 141461 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1869505 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242096 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18451136 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20243357 # Cumulative packet size per connected master and slave (bytes)
1586,1588c1584,1586
< system.membus.pkt_size::total 26262131 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 1626 # Total snoops (count)
< system.membus.snoop_fanout::samples 385584 # Request fanout histogram
---
> system.membus.pkt_size::total 26255049 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 1599 # Total snoops (count)
> system.membus.snoop_fanout::samples 385491 # Request fanout histogram
1593c1591
< system.membus.snoop_fanout::1 385584 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 385491 100.00% 100.00% # Request fanout histogram
1598,1599c1596,1597
< system.membus.snoop_fanout::total 385584 # Request fanout histogram
< system.membus.reqLayer0.occupancy 251730500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 385491 # Request fanout histogram
> system.membus.reqLayer0.occupancy 251614500 # Layer occupancy (ticks)
1601c1599
< system.membus.reqLayer1.occupancy 583066500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 583372000 # Layer occupancy (ticks)
1603c1601
< system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
1605c1603
< system.membus.reqLayer3.occupancy 1995956000 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1995485500 # Layer occupancy (ticks)
1607c1605
< system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks)
---
> system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
1609c1607
< system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
1611c1609
< system.membus.respLayer2.occupancy 3161502789 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 3161579497 # Layer occupancy (ticks)
1613c1611
< system.membus.respLayer4.occupancy 54989497 # Layer occupancy (ticks)
---
> system.membus.respLayer4.occupancy 54941740 # Layer occupancy (ticks)