7,11c7,11
< host_inst_rate 254798 # Simulator instruction rate (inst/s)
< host_op_rate 503662 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3201100243 # Simulator tick rate (ticks/s)
< host_mem_usage 749084 # Number of bytes of host memory used
< host_seconds 1601.29 # Real time elapsed on the host
---
> host_inst_rate 196886 # Simulator instruction rate (inst/s)
> host_op_rate 389187 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2473535129 # Simulator tick rate (ticks/s)
> host_mem_usage 743248 # Number of bytes of host memory used
> host_seconds 2072.30 # Real time elapsed on the host
429,430d428
< system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
< system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
445,446d442
< system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
453,454c449,450
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60928.460338 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60928.460338 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency