3,5c3,5
< sim_seconds 5.129874 # Number of seconds simulated
< sim_ticks 5129873616500 # Number of ticks simulated
< final_tick 5129873616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.129877 # Number of seconds simulated
> sim_ticks 5129876981500 # Number of ticks simulated
> final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 122712 # Simulator instruction rate (inst/s)
< host_op_rate 242564 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1543734215 # Simulator tick rate (ticks/s)
< host_mem_usage 750608 # Number of bytes of host memory used
< host_seconds 3323.03 # Real time elapsed on the host
< sim_insts 407773893 # Number of instructions simulated
< sim_ops 806048632 # Number of ops (including micro ops) simulated
---
> host_inst_rate 179907 # Simulator instruction rate (inst/s)
> host_op_rate 355619 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2263051238 # Simulator tick rate (ticks/s)
> host_mem_usage 804092 # Number of bytes of host memory used
> host_seconds 2266.80 # Real time elapsed on the host
> sim_insts 407812863 # Number of instructions simulated
> sim_ops 806114915 # Number of ops (including micro ops) simulated
17,24c17,24
< system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 1049344 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10817792 # Number of bytes read from this memory
< system.physmem.bytes_read::total 11900032 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1049344 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1049344 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6600896 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1048192 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10832768 # Number of bytes read from this memory
> system.physmem.bytes_read::total 11913792 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1048192 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1048192 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6597248 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 9590976 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 9587328 # Number of bytes written to this memory
28,33c28,33
< system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 16396 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 169028 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 185938 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 103139 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 16378 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 169262 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 186153 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 103082 # Number of write requests responded to by this memory
35c35
< system.physmem.num_writes::total 149859 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 149802 # Number of write requests responded to by this memory
37,44c37,44
< system.physmem.bw_read::cpu.dtb.walker 823 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 204556 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2108783 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2319751 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 204556 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 204556 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1286756 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.dtb.walker 798 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 204331 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2111701 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2322432 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 204331 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 204331 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1286044 # Write bandwidth from this memory (bytes/s)
46,63c46,63
< system.physmem.bw_write::total 1869632 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1286756 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 588403 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 823 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 204556 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2108783 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4189384 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 185938 # Number of read requests accepted
< system.physmem.writeReqs 149859 # Number of write requests accepted
< system.physmem.readBursts 185938 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 149859 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 11881152 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9589248 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 11900032 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 9590976 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::total 1868920 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1286044 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 588402 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 798 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 204331 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2111701 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4191352 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 186153 # Number of read requests accepted
> system.physmem.writeReqs 149802 # Number of write requests accepted
> system.physmem.readBursts 186153 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 149802 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 11895360 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 18432 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9586112 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 11913792 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 9587328 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue
65,97c65,97
< system.physmem.neitherReadNorWriteReqs 1710 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 11383 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10659 # Per bank write bursts
< system.physmem.perBankRdBursts::2 11850 # Per bank write bursts
< system.physmem.perBankRdBursts::3 11657 # Per bank write bursts
< system.physmem.perBankRdBursts::4 11883 # Per bank write bursts
< system.physmem.perBankRdBursts::5 11508 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11028 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11462 # Per bank write bursts
< system.physmem.perBankRdBursts::8 11217 # Per bank write bursts
< system.physmem.perBankRdBursts::9 11477 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11649 # Per bank write bursts
< system.physmem.perBankRdBursts::11 12129 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11737 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12518 # Per bank write bursts
< system.physmem.perBankRdBursts::14 12268 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11218 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10090 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9375 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9103 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8918 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9314 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9243 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8603 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8925 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9240 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9268 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9747 # Per bank write bursts
< system.physmem.perBankWrBursts::11 9397 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9475 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9702 # Per bank write bursts
< system.physmem.perBankWrBursts::14 10013 # Per bank write bursts
< system.physmem.perBankWrBursts::15 9419 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 1739 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 11465 # Per bank write bursts
> system.physmem.perBankRdBursts::1 11004 # Per bank write bursts
> system.physmem.perBankRdBursts::2 11873 # Per bank write bursts
> system.physmem.perBankRdBursts::3 11540 # Per bank write bursts
> system.physmem.perBankRdBursts::4 11961 # Per bank write bursts
> system.physmem.perBankRdBursts::5 11322 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11640 # Per bank write bursts
> system.physmem.perBankRdBursts::7 11420 # Per bank write bursts
> system.physmem.perBankRdBursts::8 11351 # Per bank write bursts
> system.physmem.perBankRdBursts::9 11861 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11826 # Per bank write bursts
> system.physmem.perBankRdBursts::11 12031 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11538 # Per bank write bursts
> system.physmem.perBankRdBursts::13 12375 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11569 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11089 # Per bank write bursts
> system.physmem.perBankWrBursts::0 10234 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9627 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9640 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9149 # Per bank write bursts
> system.physmem.perBankWrBursts::4 9237 # Per bank write bursts
> system.physmem.perBankWrBursts::5 9047 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8744 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8727 # Per bank write bursts
> system.physmem.perBankWrBursts::8 9070 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9221 # Per bank write bursts
> system.physmem.perBankWrBursts::10 9815 # Per bank write bursts
> system.physmem.perBankWrBursts::11 9405 # Per bank write bursts
> system.physmem.perBankWrBursts::12 9499 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9604 # Per bank write bursts
> system.physmem.perBankWrBursts::14 9640 # Per bank write bursts
> system.physmem.perBankWrBursts::15 9124 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
< system.physmem.totGap 5129873502000 # Total gap between requests
---
> system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
> system.physmem.totGap 5129876930000 # Total gap between requests
107c107
< system.physmem.readPktSize::6 185938 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 186153 # Read request sizes (log2)
114,122c114,122
< system.physmem.writePktSize::6 149859 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 170868 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 11901 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 2132 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 408 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 52 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 149802 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 171145 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 11892 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2095 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 399 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
126,127c126,127
< system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 2274 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 7218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 7696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 7847 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 8666 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 8996 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 9690 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 10286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 11378 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10590 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9936 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9091 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8900 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7829 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7668 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7590 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 193 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 186 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 71875 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 298.717718 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 177.081512 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 320.465816 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 27438 38.17% 38.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17395 24.20% 62.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 7359 10.24% 72.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4225 5.88% 78.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2947 4.10% 82.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2054 2.86% 85.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1404 1.95% 87.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1166 1.62% 89.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7887 10.97% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 71875 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 7354 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.241501 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 560.072825 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 7353 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2222 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2928 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 7174 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 7679 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 7821 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 8641 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 8986 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 9732 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 10392 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 11488 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 10681 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9974 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 9218 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 9052 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7930 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7716 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7761 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7619 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 106 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 110 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 72700 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 295.480165 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 175.038242 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 318.841917 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 28215 38.81% 38.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17447 24.00% 62.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 7490 10.30% 73.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 4112 5.66% 78.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3047 4.19% 82.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2009 2.76% 85.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1387 1.91% 87.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1145 1.57% 89.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7848 10.80% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 72700 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 7372 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 25.211883 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 559.387781 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 7371 99.99% 99.99% # Reads before turning the bus around for writes
230,265c230,268
< system.physmem.rdPerTurnAround::total 7354 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 7354 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.374218 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.656947 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 12.477131 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 6319 85.93% 85.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 51 0.69% 86.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 33 0.45% 87.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 263 3.58% 90.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 273 3.71% 94.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 24 0.33% 94.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 24 0.33% 95.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 15 0.20% 95.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 39 0.53% 95.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 6 0.08% 95.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 3 0.04% 95.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 1 0.01% 95.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 229 3.11% 98.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 5 0.07% 99.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 3 0.04% 99.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 2 0.03% 99.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 25 0.34% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 13 0.18% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 5 0.07% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 2 0.03% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 10 0.14% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 7354 # Writes before turning the bus around for reads
< system.physmem.totQLat 1988147750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5468954000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 928215000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10709.52 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 7372 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 7372 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.317824 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.630780 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 12.249046 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 6322 85.76% 85.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 58 0.79% 86.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 24 0.33% 86.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 276 3.74% 90.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 291 3.95% 94.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 18 0.24% 94.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 12 0.16% 94.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 14 0.19% 95.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 37 0.50% 95.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 4 0.05% 95.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 3 0.04% 95.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 3 0.04% 95.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 249 3.38% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 3 0.04% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 4 0.05% 99.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 4 0.05% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 19 0.26% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 7 0.09% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 2 0.03% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 6 0.08% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.01% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.01% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 7 0.09% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 7372 # Writes before turning the bus around for reads
> system.physmem.totQLat 2030519500 # Total ticks spent queuing
> system.physmem.totMemAccLat 5515488250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 929325000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10924.70 # Average queueing delay per DRAM burst
267c270
< system.physmem.avgMemAccLat 29459.52 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 29674.70 # Average memory access latency per DRAM burst
276,284c279,287
< system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 22.59 # Average write queue length when enqueuing
< system.physmem.readRowHits 152685 # Number of row buffer hits during reads
< system.physmem.writeRowHits 110914 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes
< system.physmem.avgGap 15276710.34 # Average gap between requests
< system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 4923726743250 # Time in different power states
---
> system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.68 # Average write queue length when enqueuing
> system.physmem.readRowHits 152396 # Number of row buffer hits during reads
> system.physmem.writeRowHits 110551 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 73.80 # Row buffer hit rate for writes
> system.physmem.avgGap 15269535.89 # Average gap between requests
> system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 4923406969000 # Time in different power states
287c290
< system.physmem.memoryStateTime::ACT 34849149750 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states
289,291c292,293
< system.membus.throughput 4545861 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 662568 # Transaction distribution
< system.membus.trans_dist::ReadResp 662557 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 662528 # Transaction distribution
> system.membus.trans_dist::ReadResp 662520 # Transaction distribution
294c296
< system.membus.trans_dist::Writeback 103139 # Transaction distribution
---
> system.membus.trans_dist::Writeback 103082 # Transaction distribution
297,305c299,307
< system.membus.trans_dist::UpgradeReq 2217 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 1710 # Transaction distribution
< system.membus.trans_dist::ReadExReq 133156 # Transaction distribution
< system.membus.trans_dist::ReadExResp 133153 # Transaction distribution
< system.membus.trans_dist::MessageReq 1644 # Transaction distribution
< system.membus.trans_dist::MessageResp 1644 # Transaction distribution
< system.membus.trans_dist::BadAddressError 11 # Transaction distribution
< system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::UpgradeReq 2203 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1739 # Transaction distribution
> system.membus.trans_dist::ReadExReq 133413 # Transaction distribution
> system.membus.trans_dist::ReadExResp 133410 # Transaction distribution
> system.membus.trans_dist::MessageReq 1645 # Transaction distribution
> system.membus.trans_dist::MessageResp 1645 # Transaction distribution
> system.membus.trans_dist::BadAddressError 8 # Transaction distribution
> system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
308,325c310,337
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478059 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 22 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724235 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94797 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 94797 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1822320 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18472576 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20264541 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 23289549 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 23289549 # Total data (bytes)
< system.membus.snoop_data_through_bus 30144 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 251288000 # Layer occupancy (ticks)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478447 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724617 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94802 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 94802 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1822709 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18482688 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20274653 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 23299665 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 943 # Total snoops (count)
> system.membus.snoop_fanout::samples 338647 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 338647 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 338647 # Request fanout histogram
> system.membus.reqLayer0.occupancy 251233500 # Layer occupancy (ticks)
327c339
< system.membus.reqLayer1.occupancy 583699000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 583254000 # Layer occupancy (ticks)
329c341
< system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks)
331c343
< system.membus.reqLayer3.occupancy 1574361000 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1574333248 # Layer occupancy (ticks)
333c345
< system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
---
> system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
335c347
< system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks)
337c349
< system.membus.respLayer2.occupancy 3158618040 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 3160566012 # Layer occupancy (ticks)
339c351
< system.membus.respLayer4.occupancy 54966743 # Layer occupancy (ticks)
---
> system.membus.respLayer4.occupancy 55015741 # Layer occupancy (ticks)
341,342c353,354
< system.iocache.tags.replacements 47579 # number of replacements
< system.iocache.tags.tagsinuse 0.103859 # Cycle average of tags in use
---
> system.iocache.tags.replacements 47584 # number of replacements
> system.iocache.tags.tagsinuse 0.103867 # Cycle average of tags in use
344c356
< system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks.
346,349c358,361
< system.iocache.tags.warmup_cycle 4992945696000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103859 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006491 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.006491 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 4992945897000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103867 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006492 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.006492 # Average percentage of cache occupancy
353,354c365,366
< system.iocache.tags.tag_accesses 428706 # Number of tag accesses
< system.iocache.tags.data_accesses 428706 # Number of data accesses
---
> system.iocache.tags.tag_accesses 428751 # Number of tag accesses
> system.iocache.tags.data_accesses 428751 # Number of data accesses
357,370c369,382
< system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
< system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses
< system.iocache.demand_misses::total 914 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses
< system.iocache.overall_misses::total 914 # number of overall misses
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152667446 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 152667446 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 152667446 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 152667446 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 152667446 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 152667446 # number of overall miss cycles
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 919 # number of ReadReq misses
> system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses
> system.iocache.demand_misses::total 919 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses
> system.iocache.overall_misses::total 919 # number of overall misses
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 156299196 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 156299196 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 156299196 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 156299196 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 156299196 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 156299196 # number of overall miss cycles
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses)
373,376c385,388
< system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses
383,388c395,400
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 167032.216630 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 167032.216630 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 167032.216630 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 170075.294886 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 170075.294886 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 170075.294886 # average overall miss latency
397,398c409,410
< system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses
401,412c413,424
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 914 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 914 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 914 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 914 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 105114946 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2850047667 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2850047667 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 105114946 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 105114946 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 108481196 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2843906419 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2843906419 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 108481196 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 108481196 # number of overall MSHR miss cycles
421,428c433,440
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 115005.411379 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61002.732598 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61002.732598 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency
442,444c454,455
< system.iobus.throughput 638663 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 225570 # Transaction distribution
< system.iobus.trans_dist::ReadResp 225570 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 225575 # Transaction distribution
> system.iobus.trans_dist::ReadResp 225575 # Transaction distribution
447,448c458,459
< system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
< system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
---
> system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
> system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
468,498c479,508
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 3276260 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 3276260 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 3918185 # Layer occupancy (ticks)
---
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 569652 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 3276304 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 3920684 # Layer occupancy (ticks)
534c544
< system.iobus.reqLayer18.occupancy 422017356 # Layer occupancy (ticks)
---
> system.iobus.reqLayer18.occupancy 422027356 # Layer occupancy (ticks)
540c550
< system.iobus.respLayer1.occupancy 52370257 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 52381259 # Layer occupancy (ticks)
542c552
< system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
---
> system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
545,549c555,559
< system.cpu.branchPred.lookups 86877356 # Number of BP lookups
< system.cpu.branchPred.condPredicted 86877356 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 902542 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 80133511 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 78163225 # Number of BTB hits
---
> system.cpu.branchPred.lookups 86898883 # Number of BP lookups
> system.cpu.branchPred.condPredicted 86898883 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 901790 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 80120336 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 78166165 # Number of BTB hits
551,553c561,563
< system.cpu.branchPred.BTBHitPct 97.541246 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1555611 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 178528 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 97.560955 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1553548 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 177807 # Number of incorrect RAS predictions.
555c565
< system.cpu.numCycles 449309558 # number of cpu cycles simulated
---
> system.cpu.numCycles 449490093 # number of cpu cycles simulated
558,574c568,584
< system.cpu.fetch.icacheStallCycles 27651859 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 428959611 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 86877356 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 79718836 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 417653044 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1892712 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 141479 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 49827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 205407 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 127451 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 9182196 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 444767 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 5009 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 446775840 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.894723 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.051895 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 27736713 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 428990683 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 86898883 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 79719713 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 417726391 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1890728 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 147536 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 50079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 202600 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 127031 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 405 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 9184683 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 447260 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5357 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 446936119 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.894164 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.051823 # Number of instructions fetched each cycle (Total)
576,584c586,594
< system.cpu.fetch.rateDist::0 281257253 62.95% 62.95% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2318085 0.52% 63.47% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 72134929 16.15% 79.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 1613434 0.36% 79.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2149929 0.48% 80.46% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 2328393 0.52% 80.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 1530698 0.34% 81.32% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1882713 0.42% 81.74% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 81560406 18.26% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 281459283 62.98% 62.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2262059 0.51% 63.48% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 72137620 16.14% 79.62% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 1613997 0.36% 79.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2155091 0.48% 80.47% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 2322801 0.52% 80.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 1535694 0.34% 81.33% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1854025 0.41% 81.74% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 81595549 18.26% 100.00% # Number of instructions fetched each cycle (Total)
588,630c598,640
< system.cpu.fetch.rateDist::total 446775840 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.193357 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.954708 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 23023114 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 264661195 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 150717323 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 7427852 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 946356 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 838299668 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 946356 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 25879231 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 223164657 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 13208529 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 154609969 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 28967098 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 834812666 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 479412 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 12346095 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 191662 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 13684658 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 997151203 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1813191058 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1114665342 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 185 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 963963482 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 33187719 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 468373 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 472487 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 39006494 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 17336272 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 10188880 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1345741 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1123547 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 829275749 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1209290 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 824021244 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 242579 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 23492118 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 36175819 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 154222 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 446775840 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.844373 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 2.418251 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 446936119 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.193328 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.954394 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 23065529 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 264763767 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 150736142 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 7425317 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 945364 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 838360092 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 945364 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 25914691 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 223241691 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 13213057 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 154633432 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 28987884 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 834905613 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 478581 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 12335118 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 182483 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 13727584 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 997265714 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1813395255 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1114768158 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 964051126 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 33214586 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 466449 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 470370 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 38986770 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 17343174 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 10196687 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1348761 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1124760 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 829365293 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1208199 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 824078412 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 244412 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 23515910 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 36291432 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 152927 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 446936119 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.843839 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 2.418170 # Number of insts issued each cycle
632,640c642,650
< system.cpu.iq.issued_per_cycle::0 262561849 58.77% 58.77% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 13882888 3.11% 61.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 10086827 2.26% 64.13% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 6921999 1.55% 65.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 74315249 16.63% 82.32% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 4452451 1.00% 83.31% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 72780033 16.29% 99.60% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 1201096 0.27% 99.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 573448 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 262716607 58.78% 58.78% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 13881580 3.11% 61.89% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 10086185 2.26% 64.14% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 6914821 1.55% 65.69% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 74322504 16.63% 82.32% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 4455510 1.00% 83.32% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 72776226 16.28% 99.60% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 1206411 0.27% 99.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 576275 0.13% 100.00% # Number of insts issued each cycle
644c654
< system.cpu.iq.issued_per_cycle::total 446775840 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 446936119 # Number of insts issued each cycle
646,676c656,686
< system.cpu.iq.fu_full::IntAlu 1974933 71.79% 71.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 151 0.01% 71.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 606 0.02% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 614459 22.33% 94.15% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 161026 5.85% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 1975200 71.80% 71.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 252 0.01% 71.81% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 1109 0.04% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 614218 22.33% 94.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 160061 5.82% 100.00% # attempts to use FU when none available
679,682c689,692
< system.cpu.iq.FU_type_0::No_OpClass 292875 0.04% 0.04% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 795624977 96.55% 96.59% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.61% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 125321 0.02% 96.62% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 293084 0.04% 0.04% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 795671914 96.55% 96.59% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 150614 0.02% 96.61% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 125303 0.02% 96.62% # Type of FU issued
709,710c719,720
< system.cpu.iq.FU_type_0::MemRead 18429310 2.24% 98.86% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 9398312 1.14% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 18435146 2.24% 98.86% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 9402351 1.14% 100.00% # Type of FU issued
713,725c723,735
< system.cpu.iq.FU_type_0::total 824021244 # Type of FU issued
< system.cpu.iq.rate 1.833972 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 2751175 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.003339 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 2097811864 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 853989635 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 819447653 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 217 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 826479445 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 99 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1882501 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 824078412 # Type of FU issued
> system.cpu.iq.rate 1.833363 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 2750840 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.003338 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 2098087999 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 854102050 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 819507550 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 194 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 826536078 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1879985 # Number of loads that had data forwarded from stores
727,730c737,740
< system.cpu.iew.lsq.thread0.squashedLoads 3343168 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 14800 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 14469 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1764190 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 3343174 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 14903 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 14336 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1767440 # Number of stores squashed
733,734c743,744
< system.cpu.iew.lsq.thread0.rescheduledLoads 2224524 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 72794 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 2224972 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 73807 # Number of times an access to memory failed due to the cache being blocked
736,752c746,762
< system.cpu.iew.iewSquashCycles 946356 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 205489198 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 9385897 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 830485039 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 188872 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 17336272 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 10188880 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 713065 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 415930 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 8070911 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 14469 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 518528 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 536731 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1055259 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 822394413 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 18030482 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1492613 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 945364 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 205481336 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 9444308 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 830573492 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 185181 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 17343194 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 10196687 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 711600 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 416792 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 8129202 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 14336 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 515306 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 539272 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1054578 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 822459197 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 18034619 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1483642 # Number of squashed instructions skipped in execute
755,762c765,772
< system.cpu.iew.exec_refs 27200783 # number of memory reference insts executed
< system.cpu.iew.exec_branches 83281301 # Number of branches executed
< system.cpu.iew.exec_stores 9170301 # Number of stores executed
< system.cpu.iew.exec_rate 1.830351 # Inst execution rate
< system.cpu.iew.wb_sent 821885746 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 819447713 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 640810294 # num instructions producing a value
< system.cpu.iew.wb_consumers 1050192124 # num instructions consuming a value
---
> system.cpu.iew.exec_refs 27209233 # number of memory reference insts executed
> system.cpu.iew.exec_branches 83289157 # Number of branches executed
> system.cpu.iew.exec_stores 9174614 # Number of stores executed
> system.cpu.iew.exec_rate 1.829760 # Inst execution rate
> system.cpu.iew.wb_sent 821946704 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 819507606 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 640910074 # num instructions producing a value
> system.cpu.iew.wb_consumers 1050315789 # num instructions consuming a value
764,765c774,775
< system.cpu.iew.wb_rate 1.823793 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.610184 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.823194 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.610207 # average fanout of values written-back
767,772c777,782
< system.cpu.commit.commitSquashedInsts 24342460 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1055068 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 914367 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 443118746 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.819035 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.675250 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 24363502 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1055272 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 913280 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 443273616 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.818549 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.675153 # Number of insts commited each cycle
774,782c784,792
< system.cpu.commit.committed_per_cycle::0 272366005 61.47% 61.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 11194221 2.53% 63.99% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3590232 0.81% 64.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 74521712 16.82% 81.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 2434404 0.55% 82.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1603700 0.36% 82.53% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 952599 0.21% 82.75% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 71009883 16.03% 98.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 5445990 1.23% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 272516770 61.48% 61.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 11195258 2.53% 64.00% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3583043 0.81% 64.81% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 74523250 16.81% 81.62% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 2432181 0.55% 82.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1605992 0.36% 82.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 951269 0.21% 82.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 71009301 16.02% 98.77% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 5456552 1.23% 100.00% # Number of insts commited each cycle
786,788c796,798
< system.cpu.commit.committed_per_cycle::total 443118746 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 407773893 # Number of instructions committed
< system.cpu.commit.committedOps 806048632 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 443273616 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 407812863 # Number of instructions committed
> system.cpu.commit.committedOps 806114915 # Number of ops (including micro ops) committed
790,793c800,803
< system.cpu.commit.refs 22417793 # Number of memory references committed
< system.cpu.commit.loads 13993103 # Number of loads committed
< system.cpu.commit.membars 474875 # Number of memory barriers committed
< system.cpu.commit.branches 82158924 # Number of branches committed
---
> system.cpu.commit.refs 22429266 # Number of memory references committed
> system.cpu.commit.loads 14000019 # Number of loads committed
> system.cpu.commit.membars 474889 # Number of memory barriers committed
> system.cpu.commit.branches 82168190 # Number of branches committed
795,800c805,810
< system.cpu.commit.int_insts 734892496 # Number of committed integer instructions.
< system.cpu.commit.function_calls 1155452 # Number of function calls committed.
< system.cpu.commit.op_class_0::No_OpClass 174150 0.02% 0.02% # Class of committed instruction
< system.cpu.commit.op_class_0::IntAlu 783190673 97.16% 97.19% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 144749 0.02% 97.20% # Class of committed instruction
< system.cpu.commit.op_class_0::IntDiv 121267 0.02% 97.22% # Class of committed instruction
---
> system.cpu.commit.int_insts 734958550 # Number of committed integer instructions.
> system.cpu.commit.function_calls 1155635 # Number of function calls committed.
> system.cpu.commit.op_class_0::No_OpClass 174258 0.02% 0.02% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 783245185 97.16% 97.18% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 144842 0.02% 97.20% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 121364 0.02% 97.22% # Class of committed instruction
827,828c837,838
< system.cpu.commit.op_class_0::MemRead 13993103 1.74% 98.95% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 8424690 1.05% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 14000019 1.74% 98.95% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 8429247 1.05% 100.00% # Class of committed instruction
831,832c841,842
< system.cpu.commit.op_class_0::total 806048632 # Class of committed instruction
< system.cpu.commit.bw_lim_events 5445990 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 806114915 # Class of committed instruction
> system.cpu.commit.bw_lim_events 5456552 # number cycles where commit BW limit reached
834,854c844,863
< system.cpu.rob.rob_reads 1267985613 # The number of ROB reads
< system.cpu.rob.rob_writes 1664458820 # The number of ROB writes
< system.cpu.timesIdled 297027 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 2533718 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 9810435335 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 407773893 # Number of Instructions Simulated
< system.cpu.committedOps 806048632 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 1.101860 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.101860 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.907557 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.907557 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1092201088 # number of integer regfile reads
< system.cpu.int_regfile_writes 655889202 # number of integer regfile writes
< system.cpu.fp_regfile_reads 60 # number of floating regfile reads
< system.cpu.cc_regfile_reads 416095530 # number of cc regfile reads
< system.cpu.cc_regfile_writes 321948927 # number of cc regfile writes
< system.cpu.misc_regfile_reads 265553416 # number of misc regfile reads
< system.cpu.misc_regfile_writes 402606 # number of misc regfile writes
< system.cpu.toL2Bus.throughput 55008962 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 3071462 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3070914 # Transaction distribution
---
> system.cpu.rob.rob_reads 1268217156 # The number of ROB reads
> system.cpu.rob.rob_writes 1664635865 # The number of ROB writes
> system.cpu.timesIdled 297982 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 2553974 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 9810264132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 407812863 # Number of Instructions Simulated
> system.cpu.committedOps 806114915 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 1.102197 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.102197 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.907279 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.907279 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1092267062 # number of integer regfile reads
> system.cpu.int_regfile_writes 655932610 # number of integer regfile writes
> system.cpu.fp_regfile_reads 56 # number of floating regfile reads
> system.cpu.cc_regfile_reads 416128291 # number of cc regfile reads
> system.cpu.cc_regfile_writes 321990784 # number of cc regfile writes
> system.cpu.misc_regfile_reads 265578345 # number of misc regfile reads
> system.cpu.misc_regfile_writes 402863 # number of misc regfile writes
> system.cpu.toL2Bus.trans_dist::ReadReq 3083726 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3083187 # Transaction distribution
857,876c866,897
< system.cpu.toL2Bus.trans_dist::Writeback 1585837 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2242 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2242 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 287030 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 287030 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 11 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1996026 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130754 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30653 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 164256 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8321689 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63869504 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207903453 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 978368 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5729920 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 278481245 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 278457117 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 3731904 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 4072507880 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.trans_dist::Writeback 1587489 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46722 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2231 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2231 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 287826 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 287826 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2007150 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6137120 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34489 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168921 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8347680 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64225408 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208172445 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1082112 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5828032 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 279307997 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 61506 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4398693 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.010831 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.103506 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 4351052 98.92% 98.92% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 47641 1.08% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 4398693 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4081523356 # Layer occupancy (ticks)
878c899
< system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 582000 # Layer occupancy (ticks)
880c901
< system.cpu.toL2Bus.respLayer0.occupancy 1501244795 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1509600495 # Layer occupancy (ticks)
882c903
< system.cpu.toL2Bus.respLayer1.occupancy 3142652109 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3145861612 # Layer occupancy (ticks)
884c905
< system.cpu.toL2Bus.respLayer2.occupancy 23061226 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 26384476 # Layer occupancy (ticks)
886c907
< system.cpu.toL2Bus.respLayer3.occupancy 112150627 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 116845140 # Layer occupancy (ticks)
888,896c909,917
< system.cpu.icache.tags.replacements 997506 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.982226 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 8120756 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 998018 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 8.136883 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 147598371250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.982226 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.996059 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.996059 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 1003070 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.154171 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 8117984 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1003582 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 8.089009 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 147599073250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.154171 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.996395 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.996395 # Average percentage of cache occupancy
898,900c919,921
< system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
902,940c923,961
< system.cpu.icache.tags.tag_accesses 10180257 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 10180257 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 8120756 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 8120756 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 8120756 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 8120756 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 8120756 # number of overall hits
< system.cpu.icache.overall_hits::total 8120756 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1061436 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1061436 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1061436 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1061436 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1061436 # number of overall misses
< system.cpu.icache.overall_misses::total 1061436 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14736249127 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14736249127 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14736249127 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14736249127 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14736249127 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14736249127 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 9182192 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 9182192 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 9182192 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 9182192 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 9182192 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 9182192 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115597 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.115597 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.115597 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.115597 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.115597 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.115597 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13883.313857 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13883.313857 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13883.313857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13883.313857 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 6673 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 10188308 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 10188308 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 8117984 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 8117984 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 8117984 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 8117984 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 8117984 # number of overall hits
> system.cpu.icache.overall_hits::total 8117984 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1066696 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1066696 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1066696 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1066696 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1066696 # number of overall misses
> system.cpu.icache.overall_misses::total 1066696 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14789893561 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14789893561 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14789893561 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14789893561 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14789893561 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14789893561 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 9184680 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 9184680 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 9184680 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 9184680 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 9184680 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 9184680 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116139 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.116139 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.116139 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.116139 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.116139 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.116139 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.143922 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13865.143922 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13865.143922 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13865.143922 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked
942c963
< system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 266 # number of cycles access was blocked
944c965
< system.cpu.icache.avg_blocked_cycles::no_mshrs 22.852740 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 22.943609 # average number of cycles each access was blocked
948,977c969,998
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63371 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 63371 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 63371 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 63371 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 63371 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 63371 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998065 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 998065 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 998065 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 998065 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 998065 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 998065 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095503951 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12095503951 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095503951 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12095503951 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095503951 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12095503951 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108696 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.108696 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.108696 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12118.954127 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12118.954127 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63068 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 63068 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 63068 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 63068 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 63068 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 63068 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1003628 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1003628 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1003628 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1003628 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1003628 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1003628 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143729999 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12143729999 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143729999 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12143729999 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143729999 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12143729999 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109272 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.109272 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.109272 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12099.831809 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12099.831809 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency
979,996c1000,1017
< system.cpu.itb_walker_cache.tags.replacements 14491 # number of replacements
< system.cpu.itb_walker_cache.tags.tagsinuse 6.005977 # Cycle average of tags in use
< system.cpu.itb_walker_cache.tags.total_refs 26506 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.sampled_refs 14506 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.tags.avg_refs 1.827244 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.warmup_cycle 5104029760000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.005977 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375374 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.375374 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
< system.cpu.itb_walker_cache.tags.tag_accesses 99110 # Number of tag accesses
< system.cpu.itb_walker_cache.tags.data_accesses 99110 # Number of data accesses
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26504 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 26504 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.tags.replacements 16690 # number of replacements
> system.cpu.itb_walker_cache.tags.tagsinuse 6.006176 # Cycle average of tags in use
> system.cpu.itb_walker_cache.tags.total_refs 23588 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.sampled_refs 16704 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.tags.avg_refs 1.412117 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.warmup_cycle 5099387464000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006176 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375386 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.375386 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
> system.cpu.itb_walker_cache.tags.tag_accesses 99931 # Number of tag accesses
> system.cpu.itb_walker_cache.tags.data_accesses 99931 # Number of data accesses
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 23592 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 23592 # number of ReadReq hits
999,1016c1020,1037
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26506 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 26506 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26506 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 26506 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15366 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 15366 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15366 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 15366 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15366 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 15366 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 173869741 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 173869741 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 173869741 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 173869741 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 173869741 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 173869741 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41870 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 41870 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 23594 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 23594 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 23594 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 23594 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 17581 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 17581 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 17581 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 17581 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 17581 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 17581 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 194939990 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 194939990 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 194939990 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 194939990 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 194939990 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 194939990 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41173 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 41173 # number of ReadReq accesses(hits+misses)
1019,1034c1040,1055
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41872 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 41872 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41872 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 41872 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.366993 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.366993 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.366976 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.366976 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.366976 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.366976 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11315.224587 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11315.224587 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11315.224587 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11315.224587 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41175 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 41175 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41175 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 41175 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.427003 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.427003 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.426982 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.426982 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.426982 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.426982 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11088.105910 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11088.105910 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11088.105910 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11088.105910 # average overall miss latency
1043,1068c1064,1089
< system.cpu.itb_walker_cache.writebacks::writebacks 2963 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 2963 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15366 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15366 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15366 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 15366 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15366 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 15366 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143113289 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143113289 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143113289 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143113289 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143113289 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143113289 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.366993 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.366993 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.366976 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.366976 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9313.633281 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 3261 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 3261 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 17581 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 17581 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 17581 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 17581 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 17581 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 17581 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159752038 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159752038 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159752038 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159752038 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159752038 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159752038 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.427003 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.427003 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.426982 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.426982 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9086.629771 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency
1070,1078c1091,1099
< system.cpu.dtb_walker_cache.tags.replacements 73624 # number of replacements
< system.cpu.dtb_walker_cache.tags.tagsinuse 15.198399 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 115934 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.sampled_refs 73640 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.avg_refs 1.574335 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 3233327929250 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.198399 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.949900 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_percent::total 0.949900 # Average percentage of cache occupancy
---
> system.cpu.dtb_walker_cache.tags.replacements 76771 # number of replacements
> system.cpu.dtb_walker_cache.tags.tagsinuse 15.789364 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 114792 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.sampled_refs 76787 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.avg_refs 1.494941 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 197445175000 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.789364 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986835 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986835 # Average percentage of cache occupancy
1080,1082c1101,1103
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
---
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
1084,1121c1105,1142
< system.cpu.dtb_walker_cache.tags.tag_accesses 456046 # Number of tag accesses
< system.cpu.dtb_walker_cache.tags.data_accesses 456046 # Number of data accesses
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 115934 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 115934 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 115934 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 115934 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 115934 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 115934 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74726 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 74726 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74726 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 74726 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74726 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 74726 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 911611211 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 911611211 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 911611211 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 911611211 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 911611211 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 911611211 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190660 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 190660 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190660 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 190660 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190660 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 190660 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391933 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391933 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391933 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391933 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391933 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391933 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12199.384565 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12199.384565 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12199.384565 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12199.384565 # average overall miss latency
---
> system.cpu.dtb_walker_cache.tags.tag_accesses 463158 # Number of tag accesses
> system.cpu.dtb_walker_cache.tags.data_accesses 463158 # Number of data accesses
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114792 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 114792 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114792 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 114792 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114792 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 114792 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77858 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 77858 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77858 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 77858 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77858 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 77858 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 943768714 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 943768714 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 943768714 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 943768714 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 943768714 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 943768714 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192650 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 192650 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192650 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 192650 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192650 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 192650 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404142 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404142 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404142 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404142 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404142 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404142 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12121.666547 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12121.666547 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12121.666547 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12121.666547 # average overall miss latency
1130,1155c1151,1176
< system.cpu.dtb_walker_cache.writebacks::writebacks 22207 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 22207 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74726 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74726 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74726 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 74726 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74726 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 74726 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 762035957 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 762035957 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 762035957 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 762035957 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 762035957 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 762035957 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391933 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391933 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391933 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10197.735152 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 21599 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 21599 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77858 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77858 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77858 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 77858 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77858 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 77858 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 787936434 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 787936434 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 787936434 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 787936434 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 787936434 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 787936434 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404142 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404142 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404142 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10120.173059 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency
1157,1161c1178,1182
< system.cpu.dcache.tags.replacements 1659582 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.996805 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 19130892 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1660094 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 11.523981 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 1661725 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.996415 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 19139703 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1662237 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 11.514425 # Average number of references to valid blocks.
1163,1165c1184,1186
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.996805 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.996415 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
1167,1169c1188,1190
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
1171,1229c1192,1250
< system.cpu.dcache.tags.tag_accesses 88336593 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88336593 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 10981431 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 10981431 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8081664 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8081664 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 65027 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 65027 # number of SoftPFReq hits
< system.cpu.dcache.demand_hits::cpu.data 19063095 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 19063095 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 19128122 # number of overall hits
< system.cpu.dcache.overall_hits::total 19128122 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1801191 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1801191 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 333463 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 333463 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 406345 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 406345 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 2134654 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2134654 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2540999 # number of overall misses
< system.cpu.dcache.overall_misses::total 2540999 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 26558757753 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 26558757753 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 12819840878 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 12819840878 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 39378598631 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39378598631 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39378598631 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39378598631 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 12782622 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 12782622 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8415127 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8415127 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 471372 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 471372 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21197749 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21197749 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21669121 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21669121 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140909 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.140909 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039627 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.039627 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862047 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.862047 # miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.100702 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.100702 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.117264 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.117264 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.109071 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.109071 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38444.567697 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38444.567697 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 18447.298078 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 18447.298078 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 15497.290094 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 15497.290094 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 378253 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 88377305 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88377305 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 10986051 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 10986051 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8085611 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8085611 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 65242 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 65242 # number of SoftPFReq hits
> system.cpu.dcache.demand_hits::cpu.data 19071662 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 19071662 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 19136904 # number of overall hits
> system.cpu.dcache.overall_hits::total 19136904 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1801162 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1801162 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 334073 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 334073 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 406623 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 406623 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 2135235 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2135235 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2541858 # number of overall misses
> system.cpu.dcache.overall_misses::total 2541858 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 26563616547 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 26563616547 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 12873735113 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 12873735113 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39437351660 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39437351660 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39437351660 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39437351660 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 12787213 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12787213 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8419684 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8419684 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 471865 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 471865 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21206897 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21206897 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21678762 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21678762 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140856 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.140856 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039678 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.039678 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.861736 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.861736 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.100686 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.100686 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.117251 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.117251 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14748.044067 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14748.044067 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38535.694633 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38535.694633 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 18469.794500 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 18469.794500 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 15515.167118 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 15515.167118 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 377678 # number of cycles access was blocked
1231c1252
< system.cpu.dcache.blocked::no_mshrs 40145 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 40377 # number of cycles access was blocked
1233c1254
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.422170 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353791 # average number of cycles each access was blocked
1237,1292c1258,1313
< system.cpu.dcache.writebacks::writebacks 1560667 # number of writebacks
< system.cpu.dcache.writebacks::total 1560667 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 830878 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 830878 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44317 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 44317 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 875195 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 875195 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 875195 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 875195 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970313 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 970313 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289146 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 289146 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402890 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 402890 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1259459 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1259459 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1662349 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1662349 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12260897766 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 12260897766 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11156657127 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11156657127 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584385500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584385500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23417554893 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23417554893 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29001940393 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 29001940393 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364665000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364665000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539423000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539423000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99904088000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 99904088000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075909 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075909 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034360 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034360 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854718 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854718 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059415 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.059415 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076715 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.076715 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.023392 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.023392 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38584.857224 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38584.857224 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13860.819330 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13860.819330 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18593.344359 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18593.344359 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17446.360778 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 17446.360778 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 1562629 # number of writebacks
> system.cpu.dcache.writebacks::total 1562629 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829779 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 829779 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44137 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 44137 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 873916 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 873916 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 873916 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 873916 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971383 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 971383 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289936 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 289936 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403164 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 403164 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1261319 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1261319 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1664483 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1664483 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264764518 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264764518 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11214941849 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11214941849 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5603688502 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5603688502 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23479706367 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23479706367 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29083394869 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 29083394869 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364659500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364659500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538935000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538935000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903594500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903594500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075965 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075965 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034435 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034435 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854405 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854405 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059477 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.059477 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076779 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.076779 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12626.085198 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12626.085198 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38680.749714 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38680.749714 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13899.277966 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13899.277966 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18615.200728 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18615.200728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.929954 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.929954 # average overall mshr miss latency
1300,1304c1321,1325
< system.cpu.l2cache.tags.replacements 112856 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64816.166677 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3836348 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 176998 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 21.674527 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 112646 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64814.554294 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3852282 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 176740 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 21.796322 # Average number of references to valid blocks.
1306,1312c1327,1333
< system.cpu.l2cache.tags.occ_blocks::writebacks 50391.724726 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.855148 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135532 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3265.471036 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 11143.980235 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.768917 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000227 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50353.205869 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.791697 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140401 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3275.059967 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 11170.356359 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.768329 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000241 # Average percentage of cache occupancy
1314,1443c1335,1464
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049827 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.170044 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.989016 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 64142 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 609 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3329 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5865 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54284 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978729 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 35070365 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 35070365 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67257 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12319 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 981564 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1336552 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2397692 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1585837 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1585837 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 306 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 306 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 153585 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 153585 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 67257 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 12319 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 981564 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1490137 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 67257 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 12319 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 981564 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1490137 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2551277 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.inst 16397 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 35888 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 52356 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1429 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1429 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133434 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133434 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 16397 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 169322 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 185790 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 16397 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 169322 # number of overall misses
< system.cpu.l2cache.overall_misses::total 185790 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5156250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 377750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1256760500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2837055499 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 4099349999 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16426795 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 16426795 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9290345968 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9290345968 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5156250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 377750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1256760500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12127401467 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 13389695967 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5156250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 377750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1256760500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12127401467 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 13389695967 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67323 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 997961 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1372440 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2450048 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1585837 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1585837 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1735 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1735 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 287019 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 287019 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67323 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 12324 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 997961 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1659459 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2737067 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67323 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 12324 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 997961 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1659459 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2737067 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000980 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000406 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016431 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026149 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021369 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823631 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823631 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464896 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.464896 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000980 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000406 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016431 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102034 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.067879 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000980 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000406 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016431 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102034 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.067879 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78125 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75550 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76645.758370 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79053.039986 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 78297.616300 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11495.307908 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11495.307908 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69625.027864 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69625.027864 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78125 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75550 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76645.758370 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71623.306286 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72068.980930 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78125 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75550 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76645.758370 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71623.306286 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72068.980930 # average overall miss latency
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049973 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.170446 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.988992 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 64094 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3429 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5695 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54337 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977997 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 35174951 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 35174951 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69400 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13641 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 987138 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1338009 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2408188 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1587489 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1587489 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 311 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 311 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 154123 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 154123 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 69400 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 13641 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 987138 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1492132 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2562311 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 69400 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 13641 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 987138 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1492132 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2562311 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 64 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 16384 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 35861 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 52315 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1456 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1456 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133693 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133693 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 64 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 16384 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 169554 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 186008 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 64 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 16384 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 169554 # number of overall misses
> system.cpu.l2cache.overall_misses::total 186008 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5398250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1244423000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2844994996 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 4095283246 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17419754 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 17419754 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9341540216 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9341540216 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5398250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1244423000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12186535212 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 13436823462 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5398250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1244423000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12186535212 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 13436823462 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69464 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13647 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1003522 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1373870 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2460503 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1587489 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1587489 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1767 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1767 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 287816 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 287816 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69464 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 13647 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1003522 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1661686 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2748319 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69464 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 13647 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1003522 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1661686 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2748319 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000440 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016326 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026102 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021262 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823995 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823995 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464509 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.464509 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000440 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016326 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102037 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.067681 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000440 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016326 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102037 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.067681 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84347.656250 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77833.333333 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75953.552246 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79333.955997 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 78281.243353 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11964.116758 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11964.116758 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69873.069016 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69873.069016 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84347.656250 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77833.333333 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75953.552246 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71874.064970 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72237.879349 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84347.656250 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77833.333333 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75953.552246 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71874.064970 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72237.879349 # average overall miss latency
1452,1544c1473,1565
< system.cpu.l2cache.writebacks::writebacks 103139 # number of writebacks
< system.cpu.l2cache.writebacks::total 103139 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16396 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35886 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 52353 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1429 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1429 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133434 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133434 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16396 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 169320 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 185787 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16396 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 169320 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 185787 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4346250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 315250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1051024500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2391844499 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3447530499 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14329428 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14329428 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7615118032 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7615118032 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4346250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 315250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1051024500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006962531 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 11062648531 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4346250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1051024500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006962531 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 11062648531 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251423000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251423000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373128500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373128500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624551500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624551500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026148 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021368 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823631 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823631 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464896 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464896 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102033 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.067878 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102033 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.067878 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64102.494511 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66651.187065 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65851.632170 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.591323 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.591323 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57070.297166 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57070.297166 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64102.494511 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.889033 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59544.793398 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64102.494511 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.889033 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59544.793398 # average overall mshr miss latency
---
> system.cpu.l2cache.writebacks::writebacks 103082 # number of writebacks
> system.cpu.l2cache.writebacks::total 103082 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 64 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16378 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35860 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 52308 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1456 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1456 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133693 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133693 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 64 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16378 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 169553 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 186001 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 64 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16378 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 169553 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 186001 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4610750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 391500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1038765000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2399725996 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3443493246 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14596954 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14596954 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7662739284 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7662739284 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4610750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1038765000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10062465280 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11106232530 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4610750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1038765000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10062465280 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11106232530 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251418000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251418000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373087500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373087500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624505500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624505500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026101 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021259 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823995 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823995 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464509 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464509 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.067678 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.067678 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.380495 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57315.934896 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57315.934896 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency