Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.230834 # Number of seconds simulated
4sim_ticks 5230834315000 # Number of ticks simulated
5final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 192642 # Simulator instruction rate (inst/s)
8host_op_rate 380808 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2470040631 # Simulator tick rate (ticks/s)
10host_mem_usage 757076 # Number of bytes of host memory used
11host_seconds 2117.71 # Real time elapsed on the host

7host_inst_rate 185450 # Simulator instruction rate (inst/s)
8host_op_rate 366593 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2377836678 # Simulator tick rate (ticks/s)
10host_mem_usage 757080 # Number of bytes of host memory used
11host_seconds 2199.83 # Real time elapsed on the host

12sim_insts 407959263 # Number of instructions simulated
13sim_ops 806441023 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory
20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21system.physmem.bytes_read::total 11615232 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1022720 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1022720 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 9293760 # Number of bytes written to this memory
25system.physmem.bytes_written::total 9293760 # Number of bytes written to this memory
26system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 15980 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 164935 # Number of read requests responded to by this memory
30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31system.physmem.num_reads::total 181488 # Number of read requests responded to by this memory
32system.physmem.num_writes::writebacks 145215 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 145215 # Number of write requests responded to by this memory
34system.physmem.bw_read::cpu.dtb.walker 1505 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.itb.walker 86 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.inst 195518 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.data 2018003 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::pc.south_bridge.ide 5420 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 2220531 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 195518 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 195518 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1776726 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 1776726 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 1776726 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.dtb.walker 1505 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.itb.walker 86 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.inst 195518 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.data 2018003 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::pc.south_bridge.ide 5420 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 3997258 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.readReqs 181488 # Number of read requests accepted
52system.physmem.writeReqs 145215 # Number of write requests accepted
53system.physmem.readBursts 181488 # Number of DRAM read bursts, including those serviced by the write queue
54system.physmem.writeBursts 145215 # Number of DRAM write bursts, including those merged in the write queue
55system.physmem.bytesReadDRAM 11596608 # Total number of bytes read from DRAM
56system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue
57system.physmem.bytesWritten 9292096 # Total number of bytes written to DRAM
58system.physmem.bytesReadSys 11615232 # Total read bytes from the system interface side
59system.physmem.bytesWrittenSys 9293760 # Total written bytes from the system interface side
60system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue
61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
63system.physmem.perBankRdBursts::0 11156 # Per bank write bursts
64system.physmem.perBankRdBursts::1 11363 # Per bank write bursts
65system.physmem.perBankRdBursts::2 11879 # Per bank write bursts
66system.physmem.perBankRdBursts::3 11399 # Per bank write bursts
67system.physmem.perBankRdBursts::4 11231 # Per bank write bursts
68system.physmem.perBankRdBursts::5 10765 # Per bank write bursts
69system.physmem.perBankRdBursts::6 10426 # Per bank write bursts
70system.physmem.perBankRdBursts::7 10967 # Per bank write bursts
71system.physmem.perBankRdBursts::8 10953 # Per bank write bursts
72system.physmem.perBankRdBursts::9 10767 # Per bank write bursts
73system.physmem.perBankRdBursts::10 11374 # Per bank write bursts
74system.physmem.perBankRdBursts::11 11178 # Per bank write bursts
75system.physmem.perBankRdBursts::12 12058 # Per bank write bursts
76system.physmem.perBankRdBursts::13 12613 # Per bank write bursts
77system.physmem.perBankRdBursts::14 11821 # Per bank write bursts
78system.physmem.perBankRdBursts::15 11247 # Per bank write bursts
79system.physmem.perBankWrBursts::0 9305 # Per bank write bursts
80system.physmem.perBankWrBursts::1 9167 # Per bank write bursts
81system.physmem.perBankWrBursts::2 9550 # Per bank write bursts
82system.physmem.perBankWrBursts::3 8690 # Per bank write bursts
83system.physmem.perBankWrBursts::4 9047 # Per bank write bursts
84system.physmem.perBankWrBursts::5 8729 # Per bank write bursts
85system.physmem.perBankWrBursts::6 8333 # Per bank write bursts
86system.physmem.perBankWrBursts::7 8814 # Per bank write bursts
87system.physmem.perBankWrBursts::8 9019 # Per bank write bursts
88system.physmem.perBankWrBursts::9 9026 # Per bank write bursts
89system.physmem.perBankWrBursts::10 9076 # Per bank write bursts
90system.physmem.perBankWrBursts::11 9210 # Per bank write bursts
91system.physmem.perBankWrBursts::12 9034 # Per bank write bursts
92system.physmem.perBankWrBursts::13 9699 # Per bank write bursts
93system.physmem.perBankWrBursts::14 9456 # Per bank write bursts
94system.physmem.perBankWrBursts::15 9034 # Per bank write bursts
95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
97system.physmem.totGap 5230834265500 # Total gap between requests
98system.physmem.readPktSize::0 0 # Read request sizes (log2)
99system.physmem.readPktSize::1 0 # Read request sizes (log2)
100system.physmem.readPktSize::2 0 # Read request sizes (log2)
101system.physmem.readPktSize::3 0 # Read request sizes (log2)
102system.physmem.readPktSize::4 0 # Read request sizes (log2)
103system.physmem.readPktSize::5 0 # Read request sizes (log2)
104system.physmem.readPktSize::6 181488 # Read request sizes (log2)
105system.physmem.writePktSize::0 0 # Write request sizes (log2)
106system.physmem.writePktSize::1 0 # Write request sizes (log2)
107system.physmem.writePktSize::2 0 # Write request sizes (log2)
108system.physmem.writePktSize::3 0 # Write request sizes (log2)
109system.physmem.writePktSize::4 0 # Write request sizes (log2)
110system.physmem.writePktSize::5 0 # Write request sizes (log2)
111system.physmem.writePktSize::6 145215 # Write request sizes (log2)
112system.physmem.rdQLenPdf::0 166675 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::1 11921 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::2 1850 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::3 432 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::15 2267 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::16 3633 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::17 8265 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::18 7318 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::19 8380 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::20 7437 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::21 7226 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::22 7798 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::23 8440 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::24 8350 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::25 8614 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::26 9831 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::28 9257 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::29 10500 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::30 8515 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::31 8071 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::32 8097 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::33 1363 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::35 207 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::36 202 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::45 195 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::46 74 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
208system.physmem.bytesPerActivate::samples 71822 # Bytes accessed per row activation
209system.physmem.bytesPerActivate::mean 290.839019 # Bytes accessed per row activation
210system.physmem.bytesPerActivate::gmean 172.771532 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::stdev 314.503983 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::0-127 28254 39.34% 39.34% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::128-255 17135 23.86% 63.20% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::256-383 7363 10.25% 73.45% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::384-511 4141 5.77% 79.21% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::512-639 2915 4.06% 83.27% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::640-767 2283 3.18% 86.45% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::768-895 1315 1.83% 88.28% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::896-1023 1115 1.55% 89.83% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::1024-1151 7301 10.17% 100.00% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::total 71822 # Bytes accessed per row activation
222system.physmem.rdPerTurnAround::samples 6865 # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::mean 26.391843 # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::stdev 580.532608 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::0-2047 6864 99.99% 99.99% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::total 6865 # Reads before turning the bus around for writes
228system.physmem.wrPerTurnAround::samples 6865 # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::mean 21.149162 # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::gmean 18.881845 # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::stdev 15.152110 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::16-19 5944 86.58% 86.58% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::20-23 183 2.67% 89.25% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::24-27 31 0.45% 89.70% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::28-31 44 0.64% 90.34% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::32-35 19 0.28% 90.62% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::36-39 17 0.25% 90.87% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::40-43 108 1.57% 92.44% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::44-47 6 0.09% 92.53% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::48-51 159 2.32% 94.84% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::52-55 12 0.17% 95.02% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::56-59 10 0.15% 95.16% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::60-63 18 0.26% 95.43% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::64-67 123 1.79% 97.22% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::68-71 3 0.04% 97.26% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::72-75 4 0.06% 97.32% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::76-79 32 0.47% 97.79% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::80-83 120 1.75% 99.53% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::108-111 1 0.01% 99.56% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::112-115 1 0.01% 99.58% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::128-131 13 0.19% 99.77% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::132-135 1 0.01% 99.78% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::140-143 5 0.07% 99.87% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::144-147 1 0.01% 99.88% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::total 6865 # Writes before turning the bus around for reads
263system.physmem.totQLat 2046328821 # Total ticks spent queuing
264system.physmem.totMemAccLat 5443772571 # Total ticks spent from burst creation until serviced by the DRAM
265system.physmem.totBusLat 905985000 # Total ticks spent in databus transfers
266system.physmem.avgQLat 11293.39 # Average queueing delay per DRAM burst
267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
268system.physmem.avgMemAccLat 30043.39 # Average memory access latency per DRAM burst
269system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
270system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
271system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
272system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
274system.physmem.busUtil 0.03 # Data bus utilization in percentage
275system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
276system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
277system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
278system.physmem.avgWrQLen 22.32 # Average write queue length when enqueuing
279system.physmem.readRowHits 147319 # Number of row buffer hits during reads
280system.physmem.writeRowHits 107244 # Number of row buffer hits during writes
281system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
282system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes
283system.physmem.avgGap 16010977.14 # Average gap between requests
284system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined
285system.physmem_0.actEnergy 266013720 # Energy for activate commands per rank (pJ)
286system.physmem_0.preEnergy 145146375 # Energy for precharge commands per rank (pJ)
287system.physmem_0.readEnergy 695643000 # Energy for read commands per rank (pJ)
288system.physmem_0.writeEnergy 464194800 # Energy for write commands per rank (pJ)
289system.physmem_0.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
290system.physmem_0.actBackEnergy 136227969945 # Energy for active background per rank (pJ)
291system.physmem_0.preBackEnergy 3019002265500 # Energy for precharge background per rank (pJ)
292system.physmem_0.totalEnergy 3498453875580 # Total energy per rank (pJ)
293system.physmem_0.averagePower 668.813765 # Core power per rank (mW)
294system.physmem_0.memoryStateTime::IDLE 5022288614990 # Time in different power states
295system.physmem_0.memoryStateTime::REF 174669040000 # Time in different power states
296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
297system.physmem_0.memoryStateTime::ACT 33876500010 # Time in different power states
298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
299system.physmem_1.actEnergy 276960600 # Energy for activate commands per rank (pJ)
300system.physmem_1.preEnergy 151119375 # Energy for precharge commands per rank (pJ)
301system.physmem_1.readEnergy 717685800 # Energy for read commands per rank (pJ)
302system.physmem_1.writeEnergy 476629920 # Energy for write commands per rank (pJ)
303system.physmem_1.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
304system.physmem_1.actBackEnergy 136555945380 # Energy for active background per rank (pJ)
305system.physmem_1.preBackEnergy 3018714567750 # Energy for precharge background per rank (pJ)
306system.physmem_1.totalEnergy 3498545551065 # Total energy per rank (pJ)
307system.physmem_1.averagePower 668.831291 # Core power per rank (mW)
308system.physmem_1.memoryStateTime::IDLE 5021804288475 # Time in different power states
309system.physmem_1.memoryStateTime::REF 174669040000 # Time in different power states
310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
311system.physmem_1.memoryStateTime::ACT 34360826525 # Time in different power states
312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
313system.cpu.branchPred.lookups 94759510 # Number of BP lookups
314system.cpu.branchPred.condPredicted 94759510 # Number of conditional branches predicted
315system.cpu.branchPred.condIncorrect 2569243 # Number of conditional branches incorrect
316system.cpu.branchPred.BTBLookups 91334471 # Number of BTB lookups
317system.cpu.branchPred.BTBHits 0 # Number of BTB hits
318system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
319system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
320system.cpu.branchPred.usedRAS 2549727 # Number of times the RAS was used to get a target.
321system.cpu.branchPred.RASInCorrect 537871 # Number of incorrect RAS predictions.
322system.cpu.branchPred.indirectLookups 91334471 # Number of indirect predictor lookups.
323system.cpu.branchPred.indirectHits 76457686 # Number of indirect target hits.
324system.cpu.branchPred.indirectMisses 14876785 # Number of indirect misses.
325system.cpu.branchPredindirectMispredicted 1743030 # Number of mispredicted indirect branches.
326system.cpu_clk_domain.clock 500 # Clock period in ticks
327system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
328system.cpu.numCycles 480891878 # number of cpu cycles simulated
329system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
330system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
331system.cpu.fetch.icacheStallCycles 31923465 # Number of cycles fetch is stalled on an Icache miss
332system.cpu.fetch.Insts 465887359 # Number of instructions fetch has processed
333system.cpu.fetch.Branches 94759510 # Number of branches that fetch encountered
334system.cpu.fetch.predictedBranches 79007413 # Number of branches that fetch has predicted taken
335system.cpu.fetch.Cycles 440671990 # Number of cycles fetch has run and was not squashing or blocked
336system.cpu.fetch.SquashCycles 5255038 # Number of cycles fetch has spent squashing
337system.cpu.fetch.TlbCycles 191860 # Number of cycles fetch has spent waiting for tlb
338system.cpu.fetch.MiscStallCycles 57153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
339system.cpu.fetch.PendingTrapStallCycles 353002 # Number of stall cycles due to pending traps
340system.cpu.fetch.PendingQuiesceStallCycles 55 # Number of stall cycles due to pending quiesce instructions
341system.cpu.fetch.IcacheWaitRetryStallCycles 773 # Number of stall cycles due to full MSHR
342system.cpu.fetch.CacheLines 12757750 # Number of cache lines fetched
343system.cpu.fetch.IcacheSquashes 1092264 # Number of outstanding Icache misses that were squashed
344system.cpu.fetch.ItlbSquashes 5767 # Number of outstanding ITLB misses that were squashed
345system.cpu.fetch.rateDist::samples 475825817 # Number of instructions fetched each cycle (Total)
346system.cpu.fetch.rateDist::mean 1.921076 # Number of instructions fetched each cycle (Total)
347system.cpu.fetch.rateDist::stdev 3.087709 # Number of instructions fetched each cycle (Total)
348system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
349system.cpu.fetch.rateDist::0 301327473 63.33% 63.33% # Number of instructions fetched each cycle (Total)
350system.cpu.fetch.rateDist::1 2357212 0.50% 63.82% # Number of instructions fetched each cycle (Total)
351system.cpu.fetch.rateDist::2 72486885 15.23% 79.06% # Number of instructions fetched each cycle (Total)
352system.cpu.fetch.rateDist::3 1661724 0.35% 79.41% # Number of instructions fetched each cycle (Total)
353system.cpu.fetch.rateDist::4 2316398 0.49% 79.89% # Number of instructions fetched each cycle (Total)
354system.cpu.fetch.rateDist::5 2498634 0.53% 80.42% # Number of instructions fetched each cycle (Total)
355system.cpu.fetch.rateDist::6 1681394 0.35% 80.77% # Number of instructions fetched each cycle (Total)
356system.cpu.fetch.rateDist::7 2034597 0.43% 81.20% # Number of instructions fetched each cycle (Total)
357system.cpu.fetch.rateDist::8 89461500 18.80% 100.00% # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
359system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.rateDist::total 475825817 # Number of instructions fetched each cycle (Total)
362system.cpu.fetch.branchRate 0.197050 # Number of branch fetches per cycle
363system.cpu.fetch.rate 0.968799 # Number of inst fetches per cycle
364system.cpu.decode.IdleCycles 27555997 # Number of cycles decode is idle
365system.cpu.decode.BlockedCycles 279962496 # Number of cycles decode is blocked
366system.cpu.decode.RunCycles 157784659 # Number of cycles decode is running
367system.cpu.decode.UnblockCycles 7895146 # Number of cycles decode is unblocking
368system.cpu.decode.SquashCycles 2627519 # Number of cycles decode is squashing
369system.cpu.decode.DecodedInsts 893342997 # Number of instructions handled by decode
370system.cpu.rename.SquashCycles 2627519 # Number of cycles rename is squashing
371system.cpu.rename.IdleCycles 31132089 # Number of cycles rename is idle
372system.cpu.rename.BlockCycles 232770175 # Number of cycles rename is blocking
373system.cpu.rename.serializeStallCycles 13972853 # count of cycles rename stalled for serializing inst
374system.cpu.rename.RunCycles 161343580 # Number of cycles rename is running
375system.cpu.rename.UnblockCycles 33979601 # Number of cycles rename is unblocking
376system.cpu.rename.RenamedInsts 881934442 # Number of instructions processed by rename
377system.cpu.rename.ROBFullEvents 459863 # Number of times rename has blocked due to ROB full
378system.cpu.rename.IQFullEvents 11536689 # Number of times rename has blocked due to IQ full
379system.cpu.rename.LQFullEvents 128312 # Number of times rename has blocked due to LQ full
380system.cpu.rename.SQFullEvents 19728876 # Number of times rename has blocked due to SQ full
381system.cpu.rename.RenamedOperands 1046728889 # Number of destination operands rename has renamed
382system.cpu.rename.RenameLookups 1924876453 # Number of register rename lookups that rename has made
383system.cpu.rename.int_rename_lookups 1183291014 # Number of integer rename lookups
384system.cpu.rename.fp_rename_lookups 238 # Number of floating rename lookups
385system.cpu.rename.CommittedMaps 964344248 # Number of HB maps that are committed
386system.cpu.rename.UndoneMaps 82384633 # Number of HB maps that are undone due to squashing
387system.cpu.rename.serializingInsts 601367 # count of serializing insts renamed
388system.cpu.rename.tempSerializingInsts 610252 # count of temporary serializing insts renamed
389system.cpu.rename.skidInsts 38099382 # count of insts added to the skid buffer
390system.cpu.memDep0.insertedLoads 22094008 # Number of loads inserted to the mem dependence unit.
391system.cpu.memDep0.insertedStores 12941388 # Number of stores inserted to the mem dependence unit.
392system.cpu.memDep0.conflictingLoads 1476239 # Number of conflicting loads.
393system.cpu.memDep0.conflictingStores 1186105 # Number of conflicting stores.
394system.cpu.iq.iqInstsAdded 863334374 # Number of instructions added to the IQ (excludes non-spec)
395system.cpu.iq.iqNonSpecInstsAdded 1274378 # Number of non-speculative instructions added to the IQ
396system.cpu.iq.iqInstsIssued 846301447 # Number of instructions issued
397system.cpu.iq.iqSquashedInstsIssued 1080231 # Number of squashed instructions issued
398system.cpu.iq.iqSquashedInstsExamined 58167725 # Number of squashed instructions iterated over during squash; mainly for profiling
399system.cpu.iq.iqSquashedOperandsExamined 86490196 # Number of squashed operands that are examined and possibly removed from graph
400system.cpu.iq.iqSquashedNonSpecRemoved 262880 # Number of squashed non-spec instructions that were removed
401system.cpu.iq.issued_per_cycle::samples 475825817 # Number of insts issued each cycle
402system.cpu.iq.issued_per_cycle::mean 1.778595 # Number of insts issued each cycle
403system.cpu.iq.issued_per_cycle::stdev 2.407570 # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::0 287398661 60.40% 60.40% # Number of insts issued each cycle
406system.cpu.iq.issued_per_cycle::1 14176451 2.98% 63.38% # Number of insts issued each cycle
407system.cpu.iq.issued_per_cycle::2 10047775 2.11% 65.49% # Number of insts issued each cycle
408system.cpu.iq.issued_per_cycle::3 7166598 1.51% 67.00% # Number of insts issued each cycle
409system.cpu.iq.issued_per_cycle::4 75162617 15.80% 82.79% # Number of insts issued each cycle
410system.cpu.iq.issued_per_cycle::5 5098284 1.07% 83.86% # Number of insts issued each cycle
411system.cpu.iq.issued_per_cycle::6 73991117 15.55% 99.41% # Number of insts issued each cycle
412system.cpu.iq.issued_per_cycle::7 1833450 0.39% 99.80% # Number of insts issued each cycle
413system.cpu.iq.issued_per_cycle::8 950864 0.20% 100.00% # Number of insts issued each cycle
414system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
415system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
416system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
417system.cpu.iq.issued_per_cycle::total 475825817 # Number of insts issued each cycle
418system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
419system.cpu.iq.fu_full::IntAlu 2341238 73.82% 73.82% # attempts to use FU when none available
420system.cpu.iq.fu_full::IntMult 0 0.00% 73.82% # attempts to use FU when none available
421system.cpu.iq.fu_full::IntDiv 0 0.00% 73.82% # attempts to use FU when none available
422system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.82% # attempts to use FU when none available
423system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.82% # attempts to use FU when none available
424system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.82% # attempts to use FU when none available
425system.cpu.iq.fu_full::FloatMult 0 0.00% 73.82% # attempts to use FU when none available
426system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.82% # attempts to use FU when none available
427system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.82% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.82% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.82% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.82% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.82% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.82% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdMult 0 0.00% 73.82% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.82% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdShift 0 0.00% 73.82% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.82% # attempts to use FU when none available
438system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.82% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.82% # attempts to use FU when none available
440system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.82% # attempts to use FU when none available
441system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.82% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.82% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.82% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.82% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.82% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.82% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
448system.cpu.iq.fu_full::MemRead 650739 20.52% 94.34% # attempts to use FU when none available
449system.cpu.iq.fu_full::MemWrite 179640 5.66% 100.00% # attempts to use FU when none available
450system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
451system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
452system.cpu.iq.FU_type_0::No_OpClass 356316 0.04% 0.04% # Type of FU issued
453system.cpu.iq.FU_type_0::IntAlu 813370459 96.11% 96.15% # Type of FU issued
454system.cpu.iq.FU_type_0::IntMult 158919 0.02% 96.17% # Type of FU issued
455system.cpu.iq.FU_type_0::IntDiv 125217 0.01% 96.18% # Type of FU issued
456system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.18% # Type of FU issued
457system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.18% # Type of FU issued
458system.cpu.iq.FU_type_0::FloatCvt 33 0.00% 96.18% # Type of FU issued
459system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.18% # Type of FU issued
460system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.18% # Type of FU issued
461system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.18% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.18% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.18% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.18% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.18% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.18% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.18% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.18% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.18% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.18% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.18% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.18% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.18% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.18% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.18% # Type of FU issued
476system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.18% # Type of FU issued
477system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.18% # Type of FU issued
478system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.18% # Type of FU issued
479system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.18% # Type of FU issued
480system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.18% # Type of FU issued
481system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.18% # Type of FU issued
482system.cpu.iq.FU_type_0::MemRead 21536842 2.54% 98.73% # Type of FU issued
483system.cpu.iq.FU_type_0::MemWrite 10753661 1.27% 100.00% # Type of FU issued
484system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
485system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
486system.cpu.iq.FU_type_0::total 846301447 # Type of FU issued
487system.cpu.iq.rate 1.759858 # Inst issue rate
488system.cpu.iq.fu_busy_cnt 3171617 # FU busy when requested
489system.cpu.iq.fu_busy_rate 0.003748 # FU busy rate (busy events/executed inst)
490system.cpu.iq.int_inst_queue_reads 2172680182 # Number of integer instruction queue reads
491system.cpu.iq.int_inst_queue_writes 922790965 # Number of integer instruction queue writes
492system.cpu.iq.int_inst_queue_wakeup_accesses 836180835 # Number of integer instruction queue wakeup accesses
493system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads
494system.cpu.iq.fp_inst_queue_writes 370 # Number of floating instruction queue writes
495system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
496system.cpu.iq.int_alu_accesses 849116572 # Number of integer alu accesses
497system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses
498system.cpu.iew.lsq.thread0.forwLoads 1830080 # Number of loads that had data forwarded from stores
499system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
500system.cpu.iew.lsq.thread0.squashedLoads 8142730 # Number of loads squashed
501system.cpu.iew.lsq.thread0.ignoredResponses 39108 # Number of memory responses ignored because the instruction is squashed
502system.cpu.iew.lsq.thread0.memOrderViolation 18452 # Number of memory ordering violations
503system.cpu.iew.lsq.thread0.squashedStores 4524667 # Number of stores squashed
504system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
505system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
506system.cpu.iew.lsq.thread0.rescheduledLoads 2096489 # Number of loads that were rescheduled
507system.cpu.iew.lsq.thread0.cacheBlocked 69686 # Number of times an access to memory failed due to the cache being blocked
508system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
509system.cpu.iew.iewSquashCycles 2627519 # Number of cycles IEW is squashing
510system.cpu.iew.iewBlockCycles 209544850 # Number of cycles IEW is blocking
511system.cpu.iew.iewUnblockCycles 15006849 # Number of cycles IEW is unblocking
512system.cpu.iew.iewDispatchedInsts 864608752 # Number of instructions dispatched to IQ
513system.cpu.iew.iewDispSquashedInsts 226211 # Number of squashed instructions skipped by dispatch
514system.cpu.iew.iewDispLoadInsts 22094027 # Number of dispatched load instructions
515system.cpu.iew.iewDispStoreInsts 12941388 # Number of dispatched store instructions
516system.cpu.iew.iewDispNonSpecInsts 792823 # Number of dispatched non-speculative instructions
517system.cpu.iew.iewIQFullEvents 380512 # Number of times the IQ has become full, causing a stall
518system.cpu.iew.iewLSQFullEvents 13811616 # Number of times the LSQ has become full, causing a stall
519system.cpu.iew.memOrderViolationEvents 18452 # Number of memory order violations
520system.cpu.iew.predictedTakenIncorrect 814414 # Number of branches that were predicted taken incorrectly
521system.cpu.iew.predictedNotTakenIncorrect 2555334 # Number of branches that were predicted not taken incorrectly
522system.cpu.iew.branchMispredicts 3369748 # Number of branch mispredicts detected at execute
523system.cpu.iew.iewExecutedInsts 840380811 # Number of executed instructions
524system.cpu.iew.iewExecLoadInsts 20115901 # Number of load instructions executed
525system.cpu.iew.iewExecSquashedInsts 5466441 # Number of squashed instructions skipped in execute
526system.cpu.iew.exec_swp 0 # number of swp insts executed
527system.cpu.iew.exec_nop 0 # number of nop insts executed
528system.cpu.iew.exec_refs 30041341 # number of memory reference insts executed
529system.cpu.iew.exec_branches 84810471 # Number of branches executed
530system.cpu.iew.exec_stores 9925440 # Number of stores executed
531system.cpu.iew.exec_rate 1.747546 # Inst execution rate
532system.cpu.iew.wb_sent 839049436 # cumulative count of insts sent to commit
533system.cpu.iew.wb_count 836180959 # cumulative count of insts written-back
534system.cpu.iew.wb_producers 651539387 # num instructions producing a value
535system.cpu.iew.wb_consumers 1065055120 # num instructions consuming a value
536system.cpu.iew.wb_rate 1.738813 # insts written-back per cycle
537system.cpu.iew.wb_fanout 0.611742 # average fanout of values written-back
538system.cpu.commit.commitSquashedInsts 58084156 # The number of squashed insts skipped by commit
539system.cpu.commit.commitNonSpecStalls 1011498 # The number of times commit has been forced to stall to communicate backwards
540system.cpu.commit.branchMispredicts 2594633 # The number of times a branch was mispredicted
541system.cpu.commit.committed_per_cycle::samples 466580325 # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::mean 1.728408 # Number of insts commited each cycle
543system.cpu.commit.committed_per_cycle::stdev 2.632712 # Number of insts commited each cycle
544system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
545system.cpu.commit.committed_per_cycle::0 295124018 63.25% 63.25% # Number of insts commited each cycle
546system.cpu.commit.committed_per_cycle::1 11517659 2.47% 65.72% # Number of insts commited each cycle
547system.cpu.commit.committed_per_cycle::2 3731538 0.80% 66.52% # Number of insts commited each cycle
548system.cpu.commit.committed_per_cycle::3 74584029 15.99% 82.51% # Number of insts commited each cycle
549system.cpu.commit.committed_per_cycle::4 2769867 0.59% 83.10% # Number of insts commited each cycle
550system.cpu.commit.committed_per_cycle::5 1676646 0.36% 83.46% # Number of insts commited each cycle
551system.cpu.commit.committed_per_cycle::6 1039317 0.22% 83.68% # Number of insts commited each cycle
552system.cpu.commit.committed_per_cycle::7 71088407 15.24% 98.92% # Number of insts commited each cycle
553system.cpu.commit.committed_per_cycle::8 5048844 1.08% 100.00% # Number of insts commited each cycle
554system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
555system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
556system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
557system.cpu.commit.committed_per_cycle::total 466580325 # Number of insts commited each cycle
558system.cpu.commit.committedInsts 407959263 # Number of instructions committed
559system.cpu.commit.committedOps 806441023 # Number of ops (including micro ops) committed
560system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
561system.cpu.commit.refs 22368017 # Number of memory references committed
562system.cpu.commit.loads 13951296 # Number of loads committed
563system.cpu.commit.membars 447981 # Number of memory barriers committed
564system.cpu.commit.branches 82209281 # Number of branches committed
565system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
566system.cpu.commit.int_insts 735219945 # Number of committed integer instructions.
567system.cpu.commit.function_calls 1155854 # Number of function calls committed.
568system.cpu.commit.op_class_0::No_OpClass 172239 0.02% 0.02% # Class of committed instruction
569system.cpu.commit.op_class_0::IntAlu 783638607 97.17% 97.19% # Class of committed instruction
570system.cpu.commit.op_class_0::IntMult 143690 0.02% 97.21% # Class of committed instruction
571system.cpu.commit.op_class_0::IntDiv 121021 0.02% 97.23% # Class of committed instruction
572system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.23% # Class of committed instruction
573system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.23% # Class of committed instruction
574system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.23% # Class of committed instruction
575system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.23% # Class of committed instruction
576system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.23% # Class of committed instruction
577system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.23% # Class of committed instruction
578system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.23% # Class of committed instruction
579system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.23% # Class of committed instruction
580system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.23% # Class of committed instruction
581system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.23% # Class of committed instruction
582system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.23% # Class of committed instruction
583system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.23% # Class of committed instruction
584system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.23% # Class of committed instruction
585system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.23% # Class of committed instruction
586system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.23% # Class of committed instruction
587system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.23% # Class of committed instruction
588system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.23% # Class of committed instruction
589system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.23% # Class of committed instruction
590system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.23% # Class of committed instruction
591system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.23% # Class of committed instruction
592system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.23% # Class of committed instruction
593system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.23% # Class of committed instruction
594system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.23% # Class of committed instruction
595system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.23% # Class of committed instruction
596system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.23% # Class of committed instruction
597system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.23% # Class of committed instruction
598system.cpu.commit.op_class_0::MemRead 13948729 1.73% 98.96% # Class of committed instruction
599system.cpu.commit.op_class_0::MemWrite 8416721 1.04% 100.00% # Class of committed instruction
600system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
601system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
602system.cpu.commit.op_class_0::total 806441023 # Class of committed instruction
603system.cpu.commit.bw_lim_events 5048844 # number cycles where commit BW limit reached
604system.cpu.rob.rob_reads 1325977641 # The number of ROB reads
605system.cpu.rob.rob_writes 1738470998 # The number of ROB writes
606system.cpu.timesIdled 409236 # Number of times that the entire CPU went into an idle state and unscheduled itself
607system.cpu.idleCycles 5066061 # Total number of cycles that the CPU has spent unscheduled due to idling
608system.cpu.quiesceCycles 9980774176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
609system.cpu.committedInsts 407959263 # Number of Instructions Simulated
610system.cpu.committedOps 806441023 # Number of Ops (including micro ops) Simulated
611system.cpu.cpi 1.178774 # CPI: Cycles Per Instruction
612system.cpu.cpi_total 1.178774 # CPI: Total CPI of All Threads
613system.cpu.ipc 0.848339 # IPC: Instructions Per Cycle
614system.cpu.ipc_total 0.848339 # IPC: Total IPC of All Threads
615system.cpu.int_regfile_reads 1112363546 # number of integer regfile reads
616system.cpu.int_regfile_writes 669949193 # number of integer regfile writes
617system.cpu.fp_regfile_reads 124 # number of floating regfile reads
618system.cpu.cc_regfile_reads 420347609 # number of cc regfile reads
619system.cpu.cc_regfile_writes 325273387 # number of cc regfile writes
620system.cpu.misc_regfile_reads 273375214 # number of misc regfile reads
621system.cpu.misc_regfile_writes 400822 # number of misc regfile writes
622system.cpu.dcache.tags.replacements 1703381 # number of replacements
623system.cpu.dcache.tags.tagsinuse 511.994824 # Cycle average of tags in use
624system.cpu.dcache.tags.total_refs 21315243 # Total number of references to valid blocks.
625system.cpu.dcache.tags.sampled_refs 1703893 # Sample count of references to valid blocks.
626system.cpu.dcache.tags.avg_refs 12.509731 # Average number of references to valid blocks.
627system.cpu.dcache.tags.warmup_cycle 65900500 # Cycle when the warmup percentage was hit.
628system.cpu.dcache.tags.occ_blocks::cpu.data 511.994824 # Average occupied blocks per requestor
629system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
630system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
631system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
632system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
633system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
634system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
635system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
636system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
637system.cpu.dcache.tags.tag_accesses 97435588 # Number of tag accesses
638system.cpu.dcache.tags.data_accesses 97435588 # Number of data accesses
639system.cpu.dcache.ReadReq_hits::cpu.data 13163533 # number of ReadReq hits
640system.cpu.dcache.ReadReq_hits::total 13163533 # number of ReadReq hits
641system.cpu.dcache.WriteReq_hits::cpu.data 8077773 # number of WriteReq hits
642system.cpu.dcache.WriteReq_hits::total 8077773 # number of WriteReq hits
643system.cpu.dcache.SoftPFReq_hits::cpu.data 71009 # number of SoftPFReq hits
644system.cpu.dcache.SoftPFReq_hits::total 71009 # number of SoftPFReq hits
645system.cpu.dcache.demand_hits::cpu.data 21241306 # number of demand (read+write) hits
646system.cpu.dcache.demand_hits::total 21241306 # number of demand (read+write) hits
647system.cpu.dcache.overall_hits::cpu.data 21312315 # number of overall hits
648system.cpu.dcache.overall_hits::total 21312315 # number of overall hits
649system.cpu.dcache.ReadReq_misses::cpu.data 1883327 # number of ReadReq misses
650system.cpu.dcache.ReadReq_misses::total 1883327 # number of ReadReq misses
651system.cpu.dcache.WriteReq_misses::cpu.data 329239 # number of WriteReq misses
652system.cpu.dcache.WriteReq_misses::total 329239 # number of WriteReq misses
653system.cpu.dcache.SoftPFReq_misses::cpu.data 408040 # number of SoftPFReq misses
654system.cpu.dcache.SoftPFReq_misses::total 408040 # number of SoftPFReq misses
655system.cpu.dcache.demand_misses::cpu.data 2212566 # number of demand (read+write) misses
656system.cpu.dcache.demand_misses::total 2212566 # number of demand (read+write) misses
657system.cpu.dcache.overall_misses::cpu.data 2620606 # number of overall misses
658system.cpu.dcache.overall_misses::total 2620606 # number of overall misses
659system.cpu.dcache.ReadReq_miss_latency::cpu.data 31677233500 # number of ReadReq miss cycles
660system.cpu.dcache.ReadReq_miss_latency::total 31677233500 # number of ReadReq miss cycles
661system.cpu.dcache.WriteReq_miss_latency::cpu.data 20451778744 # number of WriteReq miss cycles
662system.cpu.dcache.WriteReq_miss_latency::total 20451778744 # number of WriteReq miss cycles
663system.cpu.dcache.demand_miss_latency::cpu.data 52129012244 # number of demand (read+write) miss cycles
664system.cpu.dcache.demand_miss_latency::total 52129012244 # number of demand (read+write) miss cycles
665system.cpu.dcache.overall_miss_latency::cpu.data 52129012244 # number of overall miss cycles
666system.cpu.dcache.overall_miss_latency::total 52129012244 # number of overall miss cycles
667system.cpu.dcache.ReadReq_accesses::cpu.data 15046860 # number of ReadReq accesses(hits+misses)
668system.cpu.dcache.ReadReq_accesses::total 15046860 # number of ReadReq accesses(hits+misses)
669system.cpu.dcache.WriteReq_accesses::cpu.data 8407012 # number of WriteReq accesses(hits+misses)
670system.cpu.dcache.WriteReq_accesses::total 8407012 # number of WriteReq accesses(hits+misses)
671system.cpu.dcache.SoftPFReq_accesses::cpu.data 479049 # number of SoftPFReq accesses(hits+misses)
672system.cpu.dcache.SoftPFReq_accesses::total 479049 # number of SoftPFReq accesses(hits+misses)
673system.cpu.dcache.demand_accesses::cpu.data 23453872 # number of demand (read+write) accesses
674system.cpu.dcache.demand_accesses::total 23453872 # number of demand (read+write) accesses
675system.cpu.dcache.overall_accesses::cpu.data 23932921 # number of overall (read+write) accesses
676system.cpu.dcache.overall_accesses::total 23932921 # number of overall (read+write) accesses
677system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125164 # miss rate for ReadReq accesses
678system.cpu.dcache.ReadReq_miss_rate::total 0.125164 # miss rate for ReadReq accesses
679system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039162 # miss rate for WriteReq accesses
680system.cpu.dcache.WriteReq_miss_rate::total 0.039162 # miss rate for WriteReq accesses
681system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.851771 # miss rate for SoftPFReq accesses
682system.cpu.dcache.SoftPFReq_miss_rate::total 0.851771 # miss rate for SoftPFReq accesses
683system.cpu.dcache.demand_miss_rate::cpu.data 0.094337 # miss rate for demand accesses
684system.cpu.dcache.demand_miss_rate::total 0.094337 # miss rate for demand accesses
685system.cpu.dcache.overall_miss_rate::cpu.data 0.109498 # miss rate for overall accesses
686system.cpu.dcache.overall_miss_rate::total 0.109498 # miss rate for overall accesses
687system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16819.826562 # average ReadReq miss latency
688system.cpu.dcache.ReadReq_avg_miss_latency::total 16819.826562 # average ReadReq miss latency
689system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62118.335750 # average WriteReq miss latency
690system.cpu.dcache.WriteReq_avg_miss_latency::total 62118.335750 # average WriteReq miss latency
691system.cpu.dcache.demand_avg_miss_latency::cpu.data 23560.432658 # average overall miss latency
692system.cpu.dcache.demand_avg_miss_latency::total 23560.432658 # average overall miss latency
693system.cpu.dcache.overall_avg_miss_latency::cpu.data 19891.968592 # average overall miss latency
694system.cpu.dcache.overall_avg_miss_latency::total 19891.968592 # average overall miss latency
695system.cpu.dcache.blocked_cycles::no_mshrs 529664 # number of cycles access was blocked
696system.cpu.dcache.blocked_cycles::no_targets 193 # number of cycles access was blocked
697system.cpu.dcache.blocked::no_mshrs 52278 # number of cycles access was blocked
698system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
699system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.131681 # average number of cycles each access was blocked
700system.cpu.dcache.avg_blocked_cycles::no_targets 96.500000 # average number of cycles each access was blocked

701system.cpu.dcache.fast_writes 0 # number of fast writes performed
702system.cpu.dcache.cache_copies 0 # number of cache copies performed

703system.cpu.dcache.writebacks::writebacks 1592887 # number of writebacks
704system.cpu.dcache.writebacks::total 1592887 # number of writebacks
705system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868287 # number of ReadReq MSHR hits
706system.cpu.dcache.ReadReq_mshr_hits::total 868287 # number of ReadReq MSHR hits
707system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42120 # number of WriteReq MSHR hits
708system.cpu.dcache.WriteReq_mshr_hits::total 42120 # number of WriteReq MSHR hits
709system.cpu.dcache.demand_mshr_hits::cpu.data 910407 # number of demand (read+write) MSHR hits
710system.cpu.dcache.demand_mshr_hits::total 910407 # number of demand (read+write) MSHR hits
711system.cpu.dcache.overall_mshr_hits::cpu.data 910407 # number of overall MSHR hits
712system.cpu.dcache.overall_mshr_hits::total 910407 # number of overall MSHR hits
713system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1015040 # number of ReadReq MSHR misses
714system.cpu.dcache.ReadReq_mshr_misses::total 1015040 # number of ReadReq MSHR misses
715system.cpu.dcache.WriteReq_mshr_misses::cpu.data 287119 # number of WriteReq MSHR misses
716system.cpu.dcache.WriteReq_mshr_misses::total 287119 # number of WriteReq MSHR misses
717system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 404591 # number of SoftPFReq MSHR misses
718system.cpu.dcache.SoftPFReq_mshr_misses::total 404591 # number of SoftPFReq MSHR misses
719system.cpu.dcache.demand_mshr_misses::cpu.data 1302159 # number of demand (read+write) MSHR misses
720system.cpu.dcache.demand_mshr_misses::total 1302159 # number of demand (read+write) MSHR misses
721system.cpu.dcache.overall_mshr_misses::cpu.data 1706750 # number of overall MSHR misses
722system.cpu.dcache.overall_mshr_misses::total 1706750 # number of overall MSHR misses
723system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
724system.cpu.dcache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
725system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
726system.cpu.dcache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
727system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
728system.cpu.dcache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
729system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15261276000 # number of ReadReq MSHR miss cycles
730system.cpu.dcache.ReadReq_mshr_miss_latency::total 15261276000 # number of ReadReq MSHR miss cycles
731system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18535708244 # number of WriteReq MSHR miss cycles
732system.cpu.dcache.WriteReq_mshr_miss_latency::total 18535708244 # number of WriteReq MSHR miss cycles
733system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6777922000 # number of SoftPFReq MSHR miss cycles
734system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6777922000 # number of SoftPFReq MSHR miss cycles
735system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33796984244 # number of demand (read+write) MSHR miss cycles
736system.cpu.dcache.demand_mshr_miss_latency::total 33796984244 # number of demand (read+write) MSHR miss cycles
737system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244 # number of overall MSHR miss cycles
738system.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles
739system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles
740system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles

701system.cpu.dcache.writebacks::writebacks 1592887 # number of writebacks
702system.cpu.dcache.writebacks::total 1592887 # number of writebacks
703system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868287 # number of ReadReq MSHR hits
704system.cpu.dcache.ReadReq_mshr_hits::total 868287 # number of ReadReq MSHR hits
705system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42120 # number of WriteReq MSHR hits
706system.cpu.dcache.WriteReq_mshr_hits::total 42120 # number of WriteReq MSHR hits
707system.cpu.dcache.demand_mshr_hits::cpu.data 910407 # number of demand (read+write) MSHR hits
708system.cpu.dcache.demand_mshr_hits::total 910407 # number of demand (read+write) MSHR hits
709system.cpu.dcache.overall_mshr_hits::cpu.data 910407 # number of overall MSHR hits
710system.cpu.dcache.overall_mshr_hits::total 910407 # number of overall MSHR hits
711system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1015040 # number of ReadReq MSHR misses
712system.cpu.dcache.ReadReq_mshr_misses::total 1015040 # number of ReadReq MSHR misses
713system.cpu.dcache.WriteReq_mshr_misses::cpu.data 287119 # number of WriteReq MSHR misses
714system.cpu.dcache.WriteReq_mshr_misses::total 287119 # number of WriteReq MSHR misses
715system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 404591 # number of SoftPFReq MSHR misses
716system.cpu.dcache.SoftPFReq_mshr_misses::total 404591 # number of SoftPFReq MSHR misses
717system.cpu.dcache.demand_mshr_misses::cpu.data 1302159 # number of demand (read+write) MSHR misses
718system.cpu.dcache.demand_mshr_misses::total 1302159 # number of demand (read+write) MSHR misses
719system.cpu.dcache.overall_mshr_misses::cpu.data 1706750 # number of overall MSHR misses
720system.cpu.dcache.overall_mshr_misses::total 1706750 # number of overall MSHR misses
721system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
722system.cpu.dcache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
723system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
724system.cpu.dcache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
725system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
726system.cpu.dcache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
727system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15261276000 # number of ReadReq MSHR miss cycles
728system.cpu.dcache.ReadReq_mshr_miss_latency::total 15261276000 # number of ReadReq MSHR miss cycles
729system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18535708244 # number of WriteReq MSHR miss cycles
730system.cpu.dcache.WriteReq_mshr_miss_latency::total 18535708244 # number of WriteReq MSHR miss cycles
731system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6777922000 # number of SoftPFReq MSHR miss cycles
732system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6777922000 # number of SoftPFReq MSHR miss cycles
733system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33796984244 # number of demand (read+write) MSHR miss cycles
734system.cpu.dcache.demand_mshr_miss_latency::total 33796984244 # number of demand (read+write) MSHR miss cycles
735system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244 # number of overall MSHR miss cycles
736system.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles
737system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles
738system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles

741system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2788550500 # number of WriteReq MSHR uncacheable cycles
742system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2788550500 # number of WriteReq MSHR uncacheable cycles
743system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100905771500 # number of overall MSHR uncacheable cycles
744system.cpu.dcache.overall_mshr_uncacheable_latency::total 100905771500 # number of overall MSHR uncacheable cycles

739system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles
740system.cpu.dcache.overall_mshr_uncacheable_latency::total 98117221000 # number of overall MSHR uncacheable cycles

745system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses
746system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses
747system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses
748system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034152 # mshr miss rate for WriteReq accesses
749system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.844571 # mshr miss rate for SoftPFReq accesses
750system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.844571 # mshr miss rate for SoftPFReq accesses
751system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055520 # mshr miss rate for demand accesses
752system.cpu.dcache.demand_mshr_miss_rate::total 0.055520 # mshr miss rate for demand accesses
753system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071314 # mshr miss rate for overall accesses
754system.cpu.dcache.overall_mshr_miss_rate::total 0.071314 # mshr miss rate for overall accesses
755system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15035.147383 # average ReadReq mshr miss latency
756system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15035.147383 # average ReadReq mshr miss latency
757system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64557.581505 # average WriteReq mshr miss latency
758system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64557.581505 # average WriteReq mshr miss latency
759system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency
760system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency
761system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency
762system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency
763system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency
764system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency
765system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency
766system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency

741system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses
742system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses
743system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses
744system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034152 # mshr miss rate for WriteReq accesses
745system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.844571 # mshr miss rate for SoftPFReq accesses
746system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.844571 # mshr miss rate for SoftPFReq accesses
747system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055520 # mshr miss rate for demand accesses
748system.cpu.dcache.demand_mshr_miss_rate::total 0.055520 # mshr miss rate for demand accesses
749system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071314 # mshr miss rate for overall accesses
750system.cpu.dcache.overall_mshr_miss_rate::total 0.071314 # mshr miss rate for overall accesses
751system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15035.147383 # average ReadReq mshr miss latency
752system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15035.147383 # average ReadReq mshr miss latency
753system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64557.581505 # average WriteReq mshr miss latency
754system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64557.581505 # average WriteReq mshr miss latency
755system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency
756system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency
757system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency
758system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency
759system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency
760system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency
761system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency
762system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency

767system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199552.776585 # average WriteReq mshr uncacheable latency
768system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199552.776585 # average WriteReq mshr uncacheable latency
769system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171769.123330 # average overall mshr uncacheable latency
770system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171769.123330 # average overall mshr uncacheable latency
771system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

763system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency
764system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency

772system.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements
773system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use
774system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks.
775system.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks.
776system.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks.
777system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit.
778system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor
779system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.991584 # Average percentage of cache occupancy
780system.cpu.dtb_walker_cache.tags.occ_percent::total 0.991584 # Average percentage of cache occupancy
781system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
782system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
783system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
784system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
785system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
786system.cpu.dtb_walker_cache.tags.tag_accesses 1086216 # Number of tag accesses
787system.cpu.dtb_walker_cache.tags.data_accesses 1086216 # Number of data accesses
788system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 319137 # number of ReadReq hits
789system.cpu.dtb_walker_cache.ReadReq_hits::total 319137 # number of ReadReq hits
790system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 319137 # number of demand (read+write) hits
791system.cpu.dtb_walker_cache.demand_hits::total 319137 # number of demand (read+write) hits
792system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 319137 # number of overall hits
793system.cpu.dtb_walker_cache.overall_hits::total 319137 # number of overall hits
794system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 149314 # number of ReadReq misses
795system.cpu.dtb_walker_cache.ReadReq_misses::total 149314 # number of ReadReq misses
796system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 149314 # number of demand (read+write) misses
797system.cpu.dtb_walker_cache.demand_misses::total 149314 # number of demand (read+write) misses
798system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 149314 # number of overall misses
799system.cpu.dtb_walker_cache.overall_misses::total 149314 # number of overall misses
800system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1956836500 # number of ReadReq miss cycles
801system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1956836500 # number of ReadReq miss cycles
802system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1956836500 # number of demand (read+write) miss cycles
803system.cpu.dtb_walker_cache.demand_miss_latency::total 1956836500 # number of demand (read+write) miss cycles
804system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1956836500 # number of overall miss cycles
805system.cpu.dtb_walker_cache.overall_miss_latency::total 1956836500 # number of overall miss cycles
806system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 468451 # number of ReadReq accesses(hits+misses)
807system.cpu.dtb_walker_cache.ReadReq_accesses::total 468451 # number of ReadReq accesses(hits+misses)
808system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 468451 # number of demand (read+write) accesses
809system.cpu.dtb_walker_cache.demand_accesses::total 468451 # number of demand (read+write) accesses
810system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 468451 # number of overall (read+write) accesses
811system.cpu.dtb_walker_cache.overall_accesses::total 468451 # number of overall (read+write) accesses
812system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.318740 # miss rate for ReadReq accesses
813system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.318740 # miss rate for ReadReq accesses
814system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.318740 # miss rate for demand accesses
815system.cpu.dtb_walker_cache.demand_miss_rate::total 0.318740 # miss rate for demand accesses
816system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.318740 # miss rate for overall accesses
817system.cpu.dtb_walker_cache.overall_miss_rate::total 0.318740 # miss rate for overall accesses
818system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13105.512544 # average ReadReq miss latency
819system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13105.512544 # average ReadReq miss latency
820system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
821system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13105.512544 # average overall miss latency
822system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
823system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544 # average overall miss latency
824system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
825system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
826system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
827system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
828system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
829system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

765system.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements
766system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use
767system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks.
768system.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks.
769system.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks.
770system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit.
771system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor
772system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.991584 # Average percentage of cache occupancy
773system.cpu.dtb_walker_cache.tags.occ_percent::total 0.991584 # Average percentage of cache occupancy
774system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
775system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
776system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
777system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
778system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
779system.cpu.dtb_walker_cache.tags.tag_accesses 1086216 # Number of tag accesses
780system.cpu.dtb_walker_cache.tags.data_accesses 1086216 # Number of data accesses
781system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 319137 # number of ReadReq hits
782system.cpu.dtb_walker_cache.ReadReq_hits::total 319137 # number of ReadReq hits
783system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 319137 # number of demand (read+write) hits
784system.cpu.dtb_walker_cache.demand_hits::total 319137 # number of demand (read+write) hits
785system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 319137 # number of overall hits
786system.cpu.dtb_walker_cache.overall_hits::total 319137 # number of overall hits
787system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 149314 # number of ReadReq misses
788system.cpu.dtb_walker_cache.ReadReq_misses::total 149314 # number of ReadReq misses
789system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 149314 # number of demand (read+write) misses
790system.cpu.dtb_walker_cache.demand_misses::total 149314 # number of demand (read+write) misses
791system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 149314 # number of overall misses
792system.cpu.dtb_walker_cache.overall_misses::total 149314 # number of overall misses
793system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1956836500 # number of ReadReq miss cycles
794system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1956836500 # number of ReadReq miss cycles
795system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1956836500 # number of demand (read+write) miss cycles
796system.cpu.dtb_walker_cache.demand_miss_latency::total 1956836500 # number of demand (read+write) miss cycles
797system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1956836500 # number of overall miss cycles
798system.cpu.dtb_walker_cache.overall_miss_latency::total 1956836500 # number of overall miss cycles
799system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 468451 # number of ReadReq accesses(hits+misses)
800system.cpu.dtb_walker_cache.ReadReq_accesses::total 468451 # number of ReadReq accesses(hits+misses)
801system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 468451 # number of demand (read+write) accesses
802system.cpu.dtb_walker_cache.demand_accesses::total 468451 # number of demand (read+write) accesses
803system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 468451 # number of overall (read+write) accesses
804system.cpu.dtb_walker_cache.overall_accesses::total 468451 # number of overall (read+write) accesses
805system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.318740 # miss rate for ReadReq accesses
806system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.318740 # miss rate for ReadReq accesses
807system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.318740 # miss rate for demand accesses
808system.cpu.dtb_walker_cache.demand_miss_rate::total 0.318740 # miss rate for demand accesses
809system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.318740 # miss rate for overall accesses
810system.cpu.dtb_walker_cache.overall_miss_rate::total 0.318740 # miss rate for overall accesses
811system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13105.512544 # average ReadReq miss latency
812system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13105.512544 # average ReadReq miss latency
813system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
814system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13105.512544 # average overall miss latency
815system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
816system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544 # average overall miss latency
817system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
818system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
819system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
820system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
821system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
822system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

830system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
831system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed

832system.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks
833system.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks
834system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses
835system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 149314 # number of ReadReq MSHR misses
836system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 149314 # number of demand (read+write) MSHR misses
837system.cpu.dtb_walker_cache.demand_mshr_misses::total 149314 # number of demand (read+write) MSHR misses
838system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 149314 # number of overall MSHR misses
839system.cpu.dtb_walker_cache.overall_mshr_misses::total 149314 # number of overall MSHR misses
840system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of ReadReq MSHR miss cycles
841system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1807522500 # number of ReadReq MSHR miss cycles
842system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of demand (read+write) MSHR miss cycles
843system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1807522500 # number of demand (read+write) MSHR miss cycles
844system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of overall MSHR miss cycles
845system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1807522500 # number of overall MSHR miss cycles
846system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for ReadReq accesses
847system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.318740 # mshr miss rate for ReadReq accesses
848system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for demand accesses
849system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.318740 # mshr miss rate for demand accesses
850system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for overall accesses
851system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.318740 # mshr miss rate for overall accesses
852system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average ReadReq mshr miss latency
853system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544 # average ReadReq mshr miss latency
854system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
855system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
856system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
857system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency

823system.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks
824system.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks
825system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses
826system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 149314 # number of ReadReq MSHR misses
827system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 149314 # number of demand (read+write) MSHR misses
828system.cpu.dtb_walker_cache.demand_mshr_misses::total 149314 # number of demand (read+write) MSHR misses
829system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 149314 # number of overall MSHR misses
830system.cpu.dtb_walker_cache.overall_mshr_misses::total 149314 # number of overall MSHR misses
831system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of ReadReq MSHR miss cycles
832system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1807522500 # number of ReadReq MSHR miss cycles
833system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of demand (read+write) MSHR miss cycles
834system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1807522500 # number of demand (read+write) MSHR miss cycles
835system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of overall MSHR miss cycles
836system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1807522500 # number of overall MSHR miss cycles
837system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for ReadReq accesses
838system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.318740 # mshr miss rate for ReadReq accesses
839system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for demand accesses
840system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.318740 # mshr miss rate for demand accesses
841system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for overall accesses
842system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.318740 # mshr miss rate for overall accesses
843system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average ReadReq mshr miss latency
844system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544 # average ReadReq mshr miss latency
845system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
846system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
847system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
848system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency

858system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate

859system.cpu.icache.tags.replacements 1273398 # number of replacements
860system.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use
861system.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks.
862system.cpu.icache.tags.sampled_refs 1273910 # Sample count of references to valid blocks.
863system.cpu.icache.tags.avg_refs 8.881310 # Average number of references to valid blocks.
864system.cpu.icache.tags.warmup_cycle 150946764500 # Cycle when the warmup percentage was hit.
865system.cpu.icache.tags.occ_blocks::cpu.inst 510.770567 # Average occupied blocks per requestor
866system.cpu.icache.tags.occ_percent::cpu.inst 0.997599 # Average percentage of cache occupancy
867system.cpu.icache.tags.occ_percent::total 0.997599 # Average percentage of cache occupancy
868system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
869system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
870system.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
871system.cpu.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
872system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
873system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
874system.cpu.icache.tags.tag_accesses 14031709 # Number of tag accesses
875system.cpu.icache.tags.data_accesses 14031709 # Number of data accesses
876system.cpu.icache.ReadReq_hits::cpu.inst 11313989 # number of ReadReq hits
877system.cpu.icache.ReadReq_hits::total 11313989 # number of ReadReq hits
878system.cpu.icache.demand_hits::cpu.inst 11313989 # number of demand (read+write) hits
879system.cpu.icache.demand_hits::total 11313989 # number of demand (read+write) hits
880system.cpu.icache.overall_hits::cpu.inst 11313989 # number of overall hits
881system.cpu.icache.overall_hits::total 11313989 # number of overall hits
882system.cpu.icache.ReadReq_misses::cpu.inst 1443748 # number of ReadReq misses
883system.cpu.icache.ReadReq_misses::total 1443748 # number of ReadReq misses
884system.cpu.icache.demand_misses::cpu.inst 1443748 # number of demand (read+write) misses
885system.cpu.icache.demand_misses::total 1443748 # number of demand (read+write) misses
886system.cpu.icache.overall_misses::cpu.inst 1443748 # number of overall misses
887system.cpu.icache.overall_misses::total 1443748 # number of overall misses
888system.cpu.icache.ReadReq_miss_latency::cpu.inst 20254966986 # number of ReadReq miss cycles
889system.cpu.icache.ReadReq_miss_latency::total 20254966986 # number of ReadReq miss cycles
890system.cpu.icache.demand_miss_latency::cpu.inst 20254966986 # number of demand (read+write) miss cycles
891system.cpu.icache.demand_miss_latency::total 20254966986 # number of demand (read+write) miss cycles
892system.cpu.icache.overall_miss_latency::cpu.inst 20254966986 # number of overall miss cycles
893system.cpu.icache.overall_miss_latency::total 20254966986 # number of overall miss cycles
894system.cpu.icache.ReadReq_accesses::cpu.inst 12757737 # number of ReadReq accesses(hits+misses)
895system.cpu.icache.ReadReq_accesses::total 12757737 # number of ReadReq accesses(hits+misses)
896system.cpu.icache.demand_accesses::cpu.inst 12757737 # number of demand (read+write) accesses
897system.cpu.icache.demand_accesses::total 12757737 # number of demand (read+write) accesses
898system.cpu.icache.overall_accesses::cpu.inst 12757737 # number of overall (read+write) accesses
899system.cpu.icache.overall_accesses::total 12757737 # number of overall (read+write) accesses
900system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.113166 # miss rate for ReadReq accesses
901system.cpu.icache.ReadReq_miss_rate::total 0.113166 # miss rate for ReadReq accesses
902system.cpu.icache.demand_miss_rate::cpu.inst 0.113166 # miss rate for demand accesses
903system.cpu.icache.demand_miss_rate::total 0.113166 # miss rate for demand accesses
904system.cpu.icache.overall_miss_rate::cpu.inst 0.113166 # miss rate for overall accesses
905system.cpu.icache.overall_miss_rate::total 0.113166 # miss rate for overall accesses
906system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14029.433797 # average ReadReq miss latency
907system.cpu.icache.ReadReq_avg_miss_latency::total 14029.433797 # average ReadReq miss latency
908system.cpu.icache.demand_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
909system.cpu.icache.demand_avg_miss_latency::total 14029.433797 # average overall miss latency
910system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
911system.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency
912system.cpu.icache.blocked_cycles::no_mshrs 10512 # number of cycles access was blocked
913system.cpu.icache.blocked_cycles::no_targets 700 # number of cycles access was blocked
914system.cpu.icache.blocked::no_mshrs 591 # number of cycles access was blocked
915system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
916system.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked
917system.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked

849system.cpu.icache.tags.replacements 1273398 # number of replacements
850system.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use
851system.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks.
852system.cpu.icache.tags.sampled_refs 1273910 # Sample count of references to valid blocks.
853system.cpu.icache.tags.avg_refs 8.881310 # Average number of references to valid blocks.
854system.cpu.icache.tags.warmup_cycle 150946764500 # Cycle when the warmup percentage was hit.
855system.cpu.icache.tags.occ_blocks::cpu.inst 510.770567 # Average occupied blocks per requestor
856system.cpu.icache.tags.occ_percent::cpu.inst 0.997599 # Average percentage of cache occupancy
857system.cpu.icache.tags.occ_percent::total 0.997599 # Average percentage of cache occupancy
858system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
859system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
860system.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
861system.cpu.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
862system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
863system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
864system.cpu.icache.tags.tag_accesses 14031709 # Number of tag accesses
865system.cpu.icache.tags.data_accesses 14031709 # Number of data accesses
866system.cpu.icache.ReadReq_hits::cpu.inst 11313989 # number of ReadReq hits
867system.cpu.icache.ReadReq_hits::total 11313989 # number of ReadReq hits
868system.cpu.icache.demand_hits::cpu.inst 11313989 # number of demand (read+write) hits
869system.cpu.icache.demand_hits::total 11313989 # number of demand (read+write) hits
870system.cpu.icache.overall_hits::cpu.inst 11313989 # number of overall hits
871system.cpu.icache.overall_hits::total 11313989 # number of overall hits
872system.cpu.icache.ReadReq_misses::cpu.inst 1443748 # number of ReadReq misses
873system.cpu.icache.ReadReq_misses::total 1443748 # number of ReadReq misses
874system.cpu.icache.demand_misses::cpu.inst 1443748 # number of demand (read+write) misses
875system.cpu.icache.demand_misses::total 1443748 # number of demand (read+write) misses
876system.cpu.icache.overall_misses::cpu.inst 1443748 # number of overall misses
877system.cpu.icache.overall_misses::total 1443748 # number of overall misses
878system.cpu.icache.ReadReq_miss_latency::cpu.inst 20254966986 # number of ReadReq miss cycles
879system.cpu.icache.ReadReq_miss_latency::total 20254966986 # number of ReadReq miss cycles
880system.cpu.icache.demand_miss_latency::cpu.inst 20254966986 # number of demand (read+write) miss cycles
881system.cpu.icache.demand_miss_latency::total 20254966986 # number of demand (read+write) miss cycles
882system.cpu.icache.overall_miss_latency::cpu.inst 20254966986 # number of overall miss cycles
883system.cpu.icache.overall_miss_latency::total 20254966986 # number of overall miss cycles
884system.cpu.icache.ReadReq_accesses::cpu.inst 12757737 # number of ReadReq accesses(hits+misses)
885system.cpu.icache.ReadReq_accesses::total 12757737 # number of ReadReq accesses(hits+misses)
886system.cpu.icache.demand_accesses::cpu.inst 12757737 # number of demand (read+write) accesses
887system.cpu.icache.demand_accesses::total 12757737 # number of demand (read+write) accesses
888system.cpu.icache.overall_accesses::cpu.inst 12757737 # number of overall (read+write) accesses
889system.cpu.icache.overall_accesses::total 12757737 # number of overall (read+write) accesses
890system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.113166 # miss rate for ReadReq accesses
891system.cpu.icache.ReadReq_miss_rate::total 0.113166 # miss rate for ReadReq accesses
892system.cpu.icache.demand_miss_rate::cpu.inst 0.113166 # miss rate for demand accesses
893system.cpu.icache.demand_miss_rate::total 0.113166 # miss rate for demand accesses
894system.cpu.icache.overall_miss_rate::cpu.inst 0.113166 # miss rate for overall accesses
895system.cpu.icache.overall_miss_rate::total 0.113166 # miss rate for overall accesses
896system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14029.433797 # average ReadReq miss latency
897system.cpu.icache.ReadReq_avg_miss_latency::total 14029.433797 # average ReadReq miss latency
898system.cpu.icache.demand_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
899system.cpu.icache.demand_avg_miss_latency::total 14029.433797 # average overall miss latency
900system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
901system.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency
902system.cpu.icache.blocked_cycles::no_mshrs 10512 # number of cycles access was blocked
903system.cpu.icache.blocked_cycles::no_targets 700 # number of cycles access was blocked
904system.cpu.icache.blocked::no_mshrs 591 # number of cycles access was blocked
905system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
906system.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked
907system.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked

918system.cpu.icache.fast_writes 0 # number of fast writes performed
919system.cpu.icache.cache_copies 0 # number of cache copies performed

920system.cpu.icache.writebacks::writebacks 1273398 # number of writebacks
921system.cpu.icache.writebacks::total 1273398 # number of writebacks
922system.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits
923system.cpu.icache.ReadReq_mshr_hits::total 169776 # number of ReadReq MSHR hits
924system.cpu.icache.demand_mshr_hits::cpu.inst 169776 # number of demand (read+write) MSHR hits
925system.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits
926system.cpu.icache.overall_mshr_hits::cpu.inst 169776 # number of overall MSHR hits
927system.cpu.icache.overall_mshr_hits::total 169776 # number of overall MSHR hits
928system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1273972 # number of ReadReq MSHR misses
929system.cpu.icache.ReadReq_mshr_misses::total 1273972 # number of ReadReq MSHR misses
930system.cpu.icache.demand_mshr_misses::cpu.inst 1273972 # number of demand (read+write) MSHR misses
931system.cpu.icache.demand_mshr_misses::total 1273972 # number of demand (read+write) MSHR misses
932system.cpu.icache.overall_mshr_misses::cpu.inst 1273972 # number of overall MSHR misses
933system.cpu.icache.overall_mshr_misses::total 1273972 # number of overall MSHR misses
934system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329222989 # number of ReadReq MSHR miss cycles
935system.cpu.icache.ReadReq_mshr_miss_latency::total 17329222989 # number of ReadReq MSHR miss cycles
936system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329222989 # number of demand (read+write) MSHR miss cycles
937system.cpu.icache.demand_mshr_miss_latency::total 17329222989 # number of demand (read+write) MSHR miss cycles
938system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329222989 # number of overall MSHR miss cycles
939system.cpu.icache.overall_mshr_miss_latency::total 17329222989 # number of overall MSHR miss cycles
940system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for ReadReq accesses
941system.cpu.icache.ReadReq_mshr_miss_rate::total 0.099859 # mshr miss rate for ReadReq accesses
942system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for demand accesses
943system.cpu.icache.demand_mshr_miss_rate::total 0.099859 # mshr miss rate for demand accesses
944system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses
945system.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses
946system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency
947system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency
948system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
949system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
950system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
951system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency

908system.cpu.icache.writebacks::writebacks 1273398 # number of writebacks
909system.cpu.icache.writebacks::total 1273398 # number of writebacks
910system.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits
911system.cpu.icache.ReadReq_mshr_hits::total 169776 # number of ReadReq MSHR hits
912system.cpu.icache.demand_mshr_hits::cpu.inst 169776 # number of demand (read+write) MSHR hits
913system.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits
914system.cpu.icache.overall_mshr_hits::cpu.inst 169776 # number of overall MSHR hits
915system.cpu.icache.overall_mshr_hits::total 169776 # number of overall MSHR hits
916system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1273972 # number of ReadReq MSHR misses
917system.cpu.icache.ReadReq_mshr_misses::total 1273972 # number of ReadReq MSHR misses
918system.cpu.icache.demand_mshr_misses::cpu.inst 1273972 # number of demand (read+write) MSHR misses
919system.cpu.icache.demand_mshr_misses::total 1273972 # number of demand (read+write) MSHR misses
920system.cpu.icache.overall_mshr_misses::cpu.inst 1273972 # number of overall MSHR misses
921system.cpu.icache.overall_mshr_misses::total 1273972 # number of overall MSHR misses
922system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329222989 # number of ReadReq MSHR miss cycles
923system.cpu.icache.ReadReq_mshr_miss_latency::total 17329222989 # number of ReadReq MSHR miss cycles
924system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329222989 # number of demand (read+write) MSHR miss cycles
925system.cpu.icache.demand_mshr_miss_latency::total 17329222989 # number of demand (read+write) MSHR miss cycles
926system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329222989 # number of overall MSHR miss cycles
927system.cpu.icache.overall_mshr_miss_latency::total 17329222989 # number of overall MSHR miss cycles
928system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for ReadReq accesses
929system.cpu.icache.ReadReq_mshr_miss_rate::total 0.099859 # mshr miss rate for ReadReq accesses
930system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for demand accesses
931system.cpu.icache.demand_mshr_miss_rate::total 0.099859 # mshr miss rate for demand accesses
932system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses
933system.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses
934system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency
935system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency
936system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
937system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
938system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
939system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency

952system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

953system.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements
954system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use
955system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks.
956system.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks.
957system.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks.
958system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit.
959system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor
960system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy
961system.cpu.itb_walker_cache.tags.occ_percent::total 0.503065 # Average percentage of cache occupancy
962system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
963system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
964system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
965system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
966system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
967system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
968system.cpu.itb_walker_cache.tags.tag_accesses 146624 # Number of tag accesses
969system.cpu.itb_walker_cache.tags.data_accesses 146624 # Number of data accesses
970system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 49439 # number of ReadReq hits
971system.cpu.itb_walker_cache.ReadReq_hits::total 49439 # number of ReadReq hits
972system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
973system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
974system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 49441 # number of demand (read+write) hits
975system.cpu.itb_walker_cache.demand_hits::total 49441 # number of demand (read+write) hits
976system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 49441 # number of overall hits
977system.cpu.itb_walker_cache.overall_hits::total 49441 # number of overall hits
978system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15914 # number of ReadReq misses
979system.cpu.itb_walker_cache.ReadReq_misses::total 15914 # number of ReadReq misses
980system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15914 # number of demand (read+write) misses
981system.cpu.itb_walker_cache.demand_misses::total 15914 # number of demand (read+write) misses
982system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15914 # number of overall misses
983system.cpu.itb_walker_cache.overall_misses::total 15914 # number of overall misses
984system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193233000 # number of ReadReq miss cycles
985system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193233000 # number of ReadReq miss cycles
986system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193233000 # number of demand (read+write) miss cycles
987system.cpu.itb_walker_cache.demand_miss_latency::total 193233000 # number of demand (read+write) miss cycles
988system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193233000 # number of overall miss cycles
989system.cpu.itb_walker_cache.overall_miss_latency::total 193233000 # number of overall miss cycles
990system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 65353 # number of ReadReq accesses(hits+misses)
991system.cpu.itb_walker_cache.ReadReq_accesses::total 65353 # number of ReadReq accesses(hits+misses)
992system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
993system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
994system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 65355 # number of demand (read+write) accesses
995system.cpu.itb_walker_cache.demand_accesses::total 65355 # number of demand (read+write) accesses
996system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 65355 # number of overall (read+write) accesses
997system.cpu.itb_walker_cache.overall_accesses::total 65355 # number of overall (read+write) accesses
998system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.243508 # miss rate for ReadReq accesses
999system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.243508 # miss rate for ReadReq accesses
1000system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.243501 # miss rate for demand accesses
1001system.cpu.itb_walker_cache.demand_miss_rate::total 0.243501 # miss rate for demand accesses
1002system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.243501 # miss rate for overall accesses
1003system.cpu.itb_walker_cache.overall_miss_rate::total 0.243501 # miss rate for overall accesses
1004system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12142.327510 # average ReadReq miss latency
1005system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12142.327510 # average ReadReq miss latency
1006system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
1007system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12142.327510 # average overall miss latency
1008system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
1009system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510 # average overall miss latency
1010system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1011system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1012system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1013system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1014system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1015system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

940system.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements
941system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use
942system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks.
943system.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks.
944system.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks.
945system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit.
946system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor
947system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy
948system.cpu.itb_walker_cache.tags.occ_percent::total 0.503065 # Average percentage of cache occupancy
949system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
950system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
951system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
952system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
953system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
954system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
955system.cpu.itb_walker_cache.tags.tag_accesses 146624 # Number of tag accesses
956system.cpu.itb_walker_cache.tags.data_accesses 146624 # Number of data accesses
957system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 49439 # number of ReadReq hits
958system.cpu.itb_walker_cache.ReadReq_hits::total 49439 # number of ReadReq hits
959system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
960system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
961system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 49441 # number of demand (read+write) hits
962system.cpu.itb_walker_cache.demand_hits::total 49441 # number of demand (read+write) hits
963system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 49441 # number of overall hits
964system.cpu.itb_walker_cache.overall_hits::total 49441 # number of overall hits
965system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15914 # number of ReadReq misses
966system.cpu.itb_walker_cache.ReadReq_misses::total 15914 # number of ReadReq misses
967system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15914 # number of demand (read+write) misses
968system.cpu.itb_walker_cache.demand_misses::total 15914 # number of demand (read+write) misses
969system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15914 # number of overall misses
970system.cpu.itb_walker_cache.overall_misses::total 15914 # number of overall misses
971system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193233000 # number of ReadReq miss cycles
972system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193233000 # number of ReadReq miss cycles
973system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193233000 # number of demand (read+write) miss cycles
974system.cpu.itb_walker_cache.demand_miss_latency::total 193233000 # number of demand (read+write) miss cycles
975system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193233000 # number of overall miss cycles
976system.cpu.itb_walker_cache.overall_miss_latency::total 193233000 # number of overall miss cycles
977system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 65353 # number of ReadReq accesses(hits+misses)
978system.cpu.itb_walker_cache.ReadReq_accesses::total 65353 # number of ReadReq accesses(hits+misses)
979system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
980system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
981system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 65355 # number of demand (read+write) accesses
982system.cpu.itb_walker_cache.demand_accesses::total 65355 # number of demand (read+write) accesses
983system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 65355 # number of overall (read+write) accesses
984system.cpu.itb_walker_cache.overall_accesses::total 65355 # number of overall (read+write) accesses
985system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.243508 # miss rate for ReadReq accesses
986system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.243508 # miss rate for ReadReq accesses
987system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.243501 # miss rate for demand accesses
988system.cpu.itb_walker_cache.demand_miss_rate::total 0.243501 # miss rate for demand accesses
989system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.243501 # miss rate for overall accesses
990system.cpu.itb_walker_cache.overall_miss_rate::total 0.243501 # miss rate for overall accesses
991system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12142.327510 # average ReadReq miss latency
992system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12142.327510 # average ReadReq miss latency
993system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
994system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12142.327510 # average overall miss latency
995system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
996system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510 # average overall miss latency
997system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
998system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
999system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1000system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1001system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1002system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1016system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1017system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed

1018system.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks
1019system.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks
1020system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses
1021system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses
1022system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15914 # number of demand (read+write) MSHR misses
1023system.cpu.itb_walker_cache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses
1024system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15914 # number of overall MSHR misses
1025system.cpu.itb_walker_cache.overall_mshr_misses::total 15914 # number of overall MSHR misses
1026system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 177319000 # number of ReadReq MSHR miss cycles
1027system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 177319000 # number of ReadReq MSHR miss cycles
1028system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 177319000 # number of demand (read+write) MSHR miss cycles
1029system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 177319000 # number of demand (read+write) MSHR miss cycles
1030system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 177319000 # number of overall MSHR miss cycles
1031system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 177319000 # number of overall MSHR miss cycles
1032system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.243508 # mshr miss rate for ReadReq accesses
1033system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.243508 # mshr miss rate for ReadReq accesses
1034system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for demand accesses
1035system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.243501 # mshr miss rate for demand accesses
1036system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses
1037system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.243501 # mshr miss rate for overall accesses
1038system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average ReadReq mshr miss latency
1039system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency
1040system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
1041system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
1042system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
1043system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency

1003system.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks
1004system.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks
1005system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses
1006system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses
1007system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15914 # number of demand (read+write) MSHR misses
1008system.cpu.itb_walker_cache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses
1009system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15914 # number of overall MSHR misses
1010system.cpu.itb_walker_cache.overall_mshr_misses::total 15914 # number of overall MSHR misses
1011system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 177319000 # number of ReadReq MSHR miss cycles
1012system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 177319000 # number of ReadReq MSHR miss cycles
1013system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 177319000 # number of demand (read+write) MSHR miss cycles
1014system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 177319000 # number of demand (read+write) MSHR miss cycles
1015system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 177319000 # number of overall MSHR miss cycles
1016system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 177319000 # number of overall MSHR miss cycles
1017system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.243508 # mshr miss rate for ReadReq accesses
1018system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.243508 # mshr miss rate for ReadReq accesses
1019system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for demand accesses
1020system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.243501 # mshr miss rate for demand accesses
1021system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses
1022system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.243501 # mshr miss rate for overall accesses
1023system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average ReadReq mshr miss latency
1024system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency
1025system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
1026system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
1027system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
1028system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency

1044system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate

1045system.cpu.l2cache.tags.replacements 108236 # number of replacements
1046system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use
1047system.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks.
1048system.cpu.l2cache.tags.sampled_refs 172394 # Sample count of references to valid blocks.
1049system.cpu.l2cache.tags.avg_refs 33.136246 # Average number of references to valid blocks.
1050system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1051system.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804 # Average occupied blocks per requestor
1052system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 58.288371 # Average occupied blocks per requestor
1053system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.037525 # Average occupied blocks per requestor
1054system.cpu.l2cache.tags.occ_blocks::cpu.inst 3440.033923 # Average occupied blocks per requestor
1055system.cpu.l2cache.tags.occ_blocks::cpu.data 12323.035126 # Average occupied blocks per requestor
1056system.cpu.l2cache.tags.occ_percent::writebacks 0.746636 # Average percentage of cache occupancy
1057system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000889 # Average percentage of cache occupancy
1058system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000046 # Average percentage of cache occupancy
1059system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052491 # Average percentage of cache occupancy
1060system.cpu.l2cache.tags.occ_percent::cpu.data 0.188035 # Average percentage of cache occupancy
1061system.cpu.l2cache.tags.occ_percent::total 0.988097 # Average percentage of cache occupancy
1062system.cpu.l2cache.tags.occ_task_id_blocks::1024 64158 # Occupied blocks per task id
1063system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
1064system.cpu.l2cache.tags.age_task_id_blocks_1024::1 567 # Occupied blocks per task id
1065system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2466 # Occupied blocks per task id
1066system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3980 # Occupied blocks per task id
1067system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57082 # Occupied blocks per task id
1068system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978973 # Percentage of cache occupancy per task id
1069system.cpu.l2cache.tags.tag_accesses 49981831 # Number of tag accesses
1070system.cpu.l2cache.tags.data_accesses 49981831 # Number of data accesses
1071system.cpu.l2cache.WritebackDirty_hits::writebacks 1631474 # number of WritebackDirty hits
1072system.cpu.l2cache.WritebackDirty_hits::total 1631474 # number of WritebackDirty hits
1073system.cpu.l2cache.WritebackClean_hits::writebacks 1270391 # number of WritebackClean hits
1074system.cpu.l2cache.WritebackClean_hits::total 1270391 # number of WritebackClean hits
1075system.cpu.l2cache.UpgradeReq_hits::cpu.data 340 # number of UpgradeReq hits
1076system.cpu.l2cache.UpgradeReq_hits::total 340 # number of UpgradeReq hits
1077system.cpu.l2cache.ReadExReq_hits::cpu.data 157196 # number of ReadExReq hits
1078system.cpu.l2cache.ReadExReq_hits::total 157196 # number of ReadExReq hits
1079system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1257840 # number of ReadCleanReq hits
1080system.cpu.l2cache.ReadCleanReq_hits::total 1257840 # number of ReadCleanReq hits
1081system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 140642 # number of ReadSharedReq hits
1082system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 13110 # number of ReadSharedReq hits
1083system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1380239 # number of ReadSharedReq hits
1084system.cpu.l2cache.ReadSharedReq_hits::total 1533991 # number of ReadSharedReq hits
1085system.cpu.l2cache.demand_hits::cpu.dtb.walker 140642 # number of demand (read+write) hits
1086system.cpu.l2cache.demand_hits::cpu.itb.walker 13110 # number of demand (read+write) hits
1087system.cpu.l2cache.demand_hits::cpu.inst 1257840 # number of demand (read+write) hits
1088system.cpu.l2cache.demand_hits::cpu.data 1537435 # number of demand (read+write) hits
1089system.cpu.l2cache.demand_hits::total 2949027 # number of demand (read+write) hits
1090system.cpu.l2cache.overall_hits::cpu.dtb.walker 140642 # number of overall hits
1091system.cpu.l2cache.overall_hits::cpu.itb.walker 13110 # number of overall hits
1092system.cpu.l2cache.overall_hits::cpu.inst 1257840 # number of overall hits
1093system.cpu.l2cache.overall_hits::cpu.data 1537435 # number of overall hits
1094system.cpu.l2cache.overall_hits::total 2949027 # number of overall hits
1095system.cpu.l2cache.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses
1096system.cpu.l2cache.UpgradeReq_misses::total 1498 # number of UpgradeReq misses
1097system.cpu.l2cache.ReadExReq_misses::cpu.data 127805 # number of ReadExReq misses
1098system.cpu.l2cache.ReadExReq_misses::total 127805 # number of ReadExReq misses
1099system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15982 # number of ReadCleanReq misses
1100system.cpu.l2cache.ReadCleanReq_misses::total 15982 # number of ReadCleanReq misses
1101system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 124 # number of ReadSharedReq misses
1102system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 7 # number of ReadSharedReq misses
1103system.cpu.l2cache.ReadSharedReq_misses::cpu.data 38662 # number of ReadSharedReq misses
1104system.cpu.l2cache.ReadSharedReq_misses::total 38793 # number of ReadSharedReq misses
1105system.cpu.l2cache.demand_misses::cpu.dtb.walker 124 # number of demand (read+write) misses
1106system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1107system.cpu.l2cache.demand_misses::cpu.inst 15982 # number of demand (read+write) misses
1108system.cpu.l2cache.demand_misses::cpu.data 166467 # number of demand (read+write) misses
1109system.cpu.l2cache.demand_misses::total 182580 # number of demand (read+write) misses
1110system.cpu.l2cache.overall_misses::cpu.dtb.walker 124 # number of overall misses
1111system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1112system.cpu.l2cache.overall_misses::cpu.inst 15982 # number of overall misses
1113system.cpu.l2cache.overall_misses::cpu.data 166467 # number of overall misses
1114system.cpu.l2cache.overall_misses::total 182580 # number of overall misses
1115system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60579000 # number of UpgradeReq miss cycles
1116system.cpu.l2cache.UpgradeReq_miss_latency::total 60579000 # number of UpgradeReq miss cycles
1117system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16318726500 # number of ReadExReq miss cycles
1118system.cpu.l2cache.ReadExReq_miss_latency::total 16318726500 # number of ReadExReq miss cycles
1119system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2135667000 # number of ReadCleanReq miss cycles
1120system.cpu.l2cache.ReadCleanReq_miss_latency::total 2135667000 # number of ReadCleanReq miss cycles
1121system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 17077500 # number of ReadSharedReq miss cycles
1122system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 945500 # number of ReadSharedReq miss cycles
1123system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5106603500 # number of ReadSharedReq miss cycles
1124system.cpu.l2cache.ReadSharedReq_miss_latency::total 5124626500 # number of ReadSharedReq miss cycles
1125system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17077500 # number of demand (read+write) miss cycles
1126system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 945500 # number of demand (read+write) miss cycles
1127system.cpu.l2cache.demand_miss_latency::cpu.inst 2135667000 # number of demand (read+write) miss cycles
1128system.cpu.l2cache.demand_miss_latency::cpu.data 21425330000 # number of demand (read+write) miss cycles
1129system.cpu.l2cache.demand_miss_latency::total 23579020000 # number of demand (read+write) miss cycles
1130system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17077500 # number of overall miss cycles
1131system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 945500 # number of overall miss cycles
1132system.cpu.l2cache.overall_miss_latency::cpu.inst 2135667000 # number of overall miss cycles
1133system.cpu.l2cache.overall_miss_latency::cpu.data 21425330000 # number of overall miss cycles
1134system.cpu.l2cache.overall_miss_latency::total 23579020000 # number of overall miss cycles
1135system.cpu.l2cache.WritebackDirty_accesses::writebacks 1631474 # number of WritebackDirty accesses(hits+misses)
1136system.cpu.l2cache.WritebackDirty_accesses::total 1631474 # number of WritebackDirty accesses(hits+misses)
1137system.cpu.l2cache.WritebackClean_accesses::writebacks 1270391 # number of WritebackClean accesses(hits+misses)
1138system.cpu.l2cache.WritebackClean_accesses::total 1270391 # number of WritebackClean accesses(hits+misses)
1139system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1838 # number of UpgradeReq accesses(hits+misses)
1140system.cpu.l2cache.UpgradeReq_accesses::total 1838 # number of UpgradeReq accesses(hits+misses)
1141system.cpu.l2cache.ReadExReq_accesses::cpu.data 285001 # number of ReadExReq accesses(hits+misses)
1142system.cpu.l2cache.ReadExReq_accesses::total 285001 # number of ReadExReq accesses(hits+misses)
1143system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1273822 # number of ReadCleanReq accesses(hits+misses)
1144system.cpu.l2cache.ReadCleanReq_accesses::total 1273822 # number of ReadCleanReq accesses(hits+misses)
1145system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 140766 # number of ReadSharedReq accesses(hits+misses)
1146system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 13117 # number of ReadSharedReq accesses(hits+misses)
1147system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1418901 # number of ReadSharedReq accesses(hits+misses)
1148system.cpu.l2cache.ReadSharedReq_accesses::total 1572784 # number of ReadSharedReq accesses(hits+misses)
1149system.cpu.l2cache.demand_accesses::cpu.dtb.walker 140766 # number of demand (read+write) accesses
1150system.cpu.l2cache.demand_accesses::cpu.itb.walker 13117 # number of demand (read+write) accesses
1151system.cpu.l2cache.demand_accesses::cpu.inst 1273822 # number of demand (read+write) accesses
1152system.cpu.l2cache.demand_accesses::cpu.data 1703902 # number of demand (read+write) accesses
1153system.cpu.l2cache.demand_accesses::total 3131607 # number of demand (read+write) accesses
1154system.cpu.l2cache.overall_accesses::cpu.dtb.walker 140766 # number of overall (read+write) accesses
1155system.cpu.l2cache.overall_accesses::cpu.itb.walker 13117 # number of overall (read+write) accesses
1156system.cpu.l2cache.overall_accesses::cpu.inst 1273822 # number of overall (read+write) accesses
1157system.cpu.l2cache.overall_accesses::cpu.data 1703902 # number of overall (read+write) accesses
1158system.cpu.l2cache.overall_accesses::total 3131607 # number of overall (read+write) accesses
1159system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815016 # miss rate for UpgradeReq accesses
1160system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815016 # miss rate for UpgradeReq accesses
1161system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.448437 # miss rate for ReadExReq accesses
1162system.cpu.l2cache.ReadExReq_miss_rate::total 0.448437 # miss rate for ReadExReq accesses
1163system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.012546 # miss rate for ReadCleanReq accesses
1164system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.012546 # miss rate for ReadCleanReq accesses
1165system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000881 # miss rate for ReadSharedReq accesses
1166system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000534 # miss rate for ReadSharedReq accesses
1167system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.027248 # miss rate for ReadSharedReq accesses
1168system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024665 # miss rate for ReadSharedReq accesses
1169system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000881 # miss rate for demand accesses
1170system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000534 # miss rate for demand accesses
1171system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012546 # miss rate for demand accesses
1172system.cpu.l2cache.demand_miss_rate::cpu.data 0.097698 # miss rate for demand accesses
1173system.cpu.l2cache.demand_miss_rate::total 0.058302 # miss rate for demand accesses
1174system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000881 # miss rate for overall accesses
1175system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000534 # miss rate for overall accesses
1176system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012546 # miss rate for overall accesses
1177system.cpu.l2cache.overall_miss_rate::cpu.data 0.097698 # miss rate for overall accesses
1178system.cpu.l2cache.overall_miss_rate::total 0.058302 # miss rate for overall accesses
1179system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40439.919893 # average UpgradeReq miss latency
1180system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40439.919893 # average UpgradeReq miss latency
1181system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127684.570244 # average ReadExReq miss latency
1182system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127684.570244 # average ReadExReq miss latency
1183system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 133629.520711 # average ReadCleanReq miss latency
1184system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 133629.520711 # average ReadCleanReq miss latency
1185system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 137721.774194 # average ReadSharedReq miss latency
1186system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135071.428571 # average ReadSharedReq miss latency
1187system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132083.272981 # average ReadSharedReq miss latency
1188system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132101.835383 # average ReadSharedReq miss latency
1189system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
1190system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
1191system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
1192system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
1193system.cpu.l2cache.demand_avg_miss_latency::total 129143.498740 # average overall miss latency
1194system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
1195system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
1196system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
1197system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
1198system.cpu.l2cache.overall_avg_miss_latency::total 129143.498740 # average overall miss latency
1199system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1200system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1201system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1202system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1203system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1204system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1029system.cpu.l2cache.tags.replacements 108236 # number of replacements
1030system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use
1031system.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks.
1032system.cpu.l2cache.tags.sampled_refs 172394 # Sample count of references to valid blocks.
1033system.cpu.l2cache.tags.avg_refs 33.136246 # Average number of references to valid blocks.
1034system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1035system.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804 # Average occupied blocks per requestor
1036system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 58.288371 # Average occupied blocks per requestor
1037system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.037525 # Average occupied blocks per requestor
1038system.cpu.l2cache.tags.occ_blocks::cpu.inst 3440.033923 # Average occupied blocks per requestor
1039system.cpu.l2cache.tags.occ_blocks::cpu.data 12323.035126 # Average occupied blocks per requestor
1040system.cpu.l2cache.tags.occ_percent::writebacks 0.746636 # Average percentage of cache occupancy
1041system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000889 # Average percentage of cache occupancy
1042system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000046 # Average percentage of cache occupancy
1043system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052491 # Average percentage of cache occupancy
1044system.cpu.l2cache.tags.occ_percent::cpu.data 0.188035 # Average percentage of cache occupancy
1045system.cpu.l2cache.tags.occ_percent::total 0.988097 # Average percentage of cache occupancy
1046system.cpu.l2cache.tags.occ_task_id_blocks::1024 64158 # Occupied blocks per task id
1047system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
1048system.cpu.l2cache.tags.age_task_id_blocks_1024::1 567 # Occupied blocks per task id
1049system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2466 # Occupied blocks per task id
1050system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3980 # Occupied blocks per task id
1051system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57082 # Occupied blocks per task id
1052system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978973 # Percentage of cache occupancy per task id
1053system.cpu.l2cache.tags.tag_accesses 49981831 # Number of tag accesses
1054system.cpu.l2cache.tags.data_accesses 49981831 # Number of data accesses
1055system.cpu.l2cache.WritebackDirty_hits::writebacks 1631474 # number of WritebackDirty hits
1056system.cpu.l2cache.WritebackDirty_hits::total 1631474 # number of WritebackDirty hits
1057system.cpu.l2cache.WritebackClean_hits::writebacks 1270391 # number of WritebackClean hits
1058system.cpu.l2cache.WritebackClean_hits::total 1270391 # number of WritebackClean hits
1059system.cpu.l2cache.UpgradeReq_hits::cpu.data 340 # number of UpgradeReq hits
1060system.cpu.l2cache.UpgradeReq_hits::total 340 # number of UpgradeReq hits
1061system.cpu.l2cache.ReadExReq_hits::cpu.data 157196 # number of ReadExReq hits
1062system.cpu.l2cache.ReadExReq_hits::total 157196 # number of ReadExReq hits
1063system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1257840 # number of ReadCleanReq hits
1064system.cpu.l2cache.ReadCleanReq_hits::total 1257840 # number of ReadCleanReq hits
1065system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 140642 # number of ReadSharedReq hits
1066system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 13110 # number of ReadSharedReq hits
1067system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1380239 # number of ReadSharedReq hits
1068system.cpu.l2cache.ReadSharedReq_hits::total 1533991 # number of ReadSharedReq hits
1069system.cpu.l2cache.demand_hits::cpu.dtb.walker 140642 # number of demand (read+write) hits
1070system.cpu.l2cache.demand_hits::cpu.itb.walker 13110 # number of demand (read+write) hits
1071system.cpu.l2cache.demand_hits::cpu.inst 1257840 # number of demand (read+write) hits
1072system.cpu.l2cache.demand_hits::cpu.data 1537435 # number of demand (read+write) hits
1073system.cpu.l2cache.demand_hits::total 2949027 # number of demand (read+write) hits
1074system.cpu.l2cache.overall_hits::cpu.dtb.walker 140642 # number of overall hits
1075system.cpu.l2cache.overall_hits::cpu.itb.walker 13110 # number of overall hits
1076system.cpu.l2cache.overall_hits::cpu.inst 1257840 # number of overall hits
1077system.cpu.l2cache.overall_hits::cpu.data 1537435 # number of overall hits
1078system.cpu.l2cache.overall_hits::total 2949027 # number of overall hits
1079system.cpu.l2cache.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses
1080system.cpu.l2cache.UpgradeReq_misses::total 1498 # number of UpgradeReq misses
1081system.cpu.l2cache.ReadExReq_misses::cpu.data 127805 # number of ReadExReq misses
1082system.cpu.l2cache.ReadExReq_misses::total 127805 # number of ReadExReq misses
1083system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15982 # number of ReadCleanReq misses
1084system.cpu.l2cache.ReadCleanReq_misses::total 15982 # number of ReadCleanReq misses
1085system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 124 # number of ReadSharedReq misses
1086system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 7 # number of ReadSharedReq misses
1087system.cpu.l2cache.ReadSharedReq_misses::cpu.data 38662 # number of ReadSharedReq misses
1088system.cpu.l2cache.ReadSharedReq_misses::total 38793 # number of ReadSharedReq misses
1089system.cpu.l2cache.demand_misses::cpu.dtb.walker 124 # number of demand (read+write) misses
1090system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1091system.cpu.l2cache.demand_misses::cpu.inst 15982 # number of demand (read+write) misses
1092system.cpu.l2cache.demand_misses::cpu.data 166467 # number of demand (read+write) misses
1093system.cpu.l2cache.demand_misses::total 182580 # number of demand (read+write) misses
1094system.cpu.l2cache.overall_misses::cpu.dtb.walker 124 # number of overall misses
1095system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1096system.cpu.l2cache.overall_misses::cpu.inst 15982 # number of overall misses
1097system.cpu.l2cache.overall_misses::cpu.data 166467 # number of overall misses
1098system.cpu.l2cache.overall_misses::total 182580 # number of overall misses
1099system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60579000 # number of UpgradeReq miss cycles
1100system.cpu.l2cache.UpgradeReq_miss_latency::total 60579000 # number of UpgradeReq miss cycles
1101system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16318726500 # number of ReadExReq miss cycles
1102system.cpu.l2cache.ReadExReq_miss_latency::total 16318726500 # number of ReadExReq miss cycles
1103system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2135667000 # number of ReadCleanReq miss cycles
1104system.cpu.l2cache.ReadCleanReq_miss_latency::total 2135667000 # number of ReadCleanReq miss cycles
1105system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 17077500 # number of ReadSharedReq miss cycles
1106system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 945500 # number of ReadSharedReq miss cycles
1107system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5106603500 # number of ReadSharedReq miss cycles
1108system.cpu.l2cache.ReadSharedReq_miss_latency::total 5124626500 # number of ReadSharedReq miss cycles
1109system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17077500 # number of demand (read+write) miss cycles
1110system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 945500 # number of demand (read+write) miss cycles
1111system.cpu.l2cache.demand_miss_latency::cpu.inst 2135667000 # number of demand (read+write) miss cycles
1112system.cpu.l2cache.demand_miss_latency::cpu.data 21425330000 # number of demand (read+write) miss cycles
1113system.cpu.l2cache.demand_miss_latency::total 23579020000 # number of demand (read+write) miss cycles
1114system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17077500 # number of overall miss cycles
1115system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 945500 # number of overall miss cycles
1116system.cpu.l2cache.overall_miss_latency::cpu.inst 2135667000 # number of overall miss cycles
1117system.cpu.l2cache.overall_miss_latency::cpu.data 21425330000 # number of overall miss cycles
1118system.cpu.l2cache.overall_miss_latency::total 23579020000 # number of overall miss cycles
1119system.cpu.l2cache.WritebackDirty_accesses::writebacks 1631474 # number of WritebackDirty accesses(hits+misses)
1120system.cpu.l2cache.WritebackDirty_accesses::total 1631474 # number of WritebackDirty accesses(hits+misses)
1121system.cpu.l2cache.WritebackClean_accesses::writebacks 1270391 # number of WritebackClean accesses(hits+misses)
1122system.cpu.l2cache.WritebackClean_accesses::total 1270391 # number of WritebackClean accesses(hits+misses)
1123system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1838 # number of UpgradeReq accesses(hits+misses)
1124system.cpu.l2cache.UpgradeReq_accesses::total 1838 # number of UpgradeReq accesses(hits+misses)
1125system.cpu.l2cache.ReadExReq_accesses::cpu.data 285001 # number of ReadExReq accesses(hits+misses)
1126system.cpu.l2cache.ReadExReq_accesses::total 285001 # number of ReadExReq accesses(hits+misses)
1127system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1273822 # number of ReadCleanReq accesses(hits+misses)
1128system.cpu.l2cache.ReadCleanReq_accesses::total 1273822 # number of ReadCleanReq accesses(hits+misses)
1129system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 140766 # number of ReadSharedReq accesses(hits+misses)
1130system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 13117 # number of ReadSharedReq accesses(hits+misses)
1131system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1418901 # number of ReadSharedReq accesses(hits+misses)
1132system.cpu.l2cache.ReadSharedReq_accesses::total 1572784 # number of ReadSharedReq accesses(hits+misses)
1133system.cpu.l2cache.demand_accesses::cpu.dtb.walker 140766 # number of demand (read+write) accesses
1134system.cpu.l2cache.demand_accesses::cpu.itb.walker 13117 # number of demand (read+write) accesses
1135system.cpu.l2cache.demand_accesses::cpu.inst 1273822 # number of demand (read+write) accesses
1136system.cpu.l2cache.demand_accesses::cpu.data 1703902 # number of demand (read+write) accesses
1137system.cpu.l2cache.demand_accesses::total 3131607 # number of demand (read+write) accesses
1138system.cpu.l2cache.overall_accesses::cpu.dtb.walker 140766 # number of overall (read+write) accesses
1139system.cpu.l2cache.overall_accesses::cpu.itb.walker 13117 # number of overall (read+write) accesses
1140system.cpu.l2cache.overall_accesses::cpu.inst 1273822 # number of overall (read+write) accesses
1141system.cpu.l2cache.overall_accesses::cpu.data 1703902 # number of overall (read+write) accesses
1142system.cpu.l2cache.overall_accesses::total 3131607 # number of overall (read+write) accesses
1143system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815016 # miss rate for UpgradeReq accesses
1144system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815016 # miss rate for UpgradeReq accesses
1145system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.448437 # miss rate for ReadExReq accesses
1146system.cpu.l2cache.ReadExReq_miss_rate::total 0.448437 # miss rate for ReadExReq accesses
1147system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.012546 # miss rate for ReadCleanReq accesses
1148system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.012546 # miss rate for ReadCleanReq accesses
1149system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000881 # miss rate for ReadSharedReq accesses
1150system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000534 # miss rate for ReadSharedReq accesses
1151system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.027248 # miss rate for ReadSharedReq accesses
1152system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024665 # miss rate for ReadSharedReq accesses
1153system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000881 # miss rate for demand accesses
1154system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000534 # miss rate for demand accesses
1155system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012546 # miss rate for demand accesses
1156system.cpu.l2cache.demand_miss_rate::cpu.data 0.097698 # miss rate for demand accesses
1157system.cpu.l2cache.demand_miss_rate::total 0.058302 # miss rate for demand accesses
1158system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000881 # miss rate for overall accesses
1159system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000534 # miss rate for overall accesses
1160system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012546 # miss rate for overall accesses
1161system.cpu.l2cache.overall_miss_rate::cpu.data 0.097698 # miss rate for overall accesses
1162system.cpu.l2cache.overall_miss_rate::total 0.058302 # miss rate for overall accesses
1163system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40439.919893 # average UpgradeReq miss latency
1164system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40439.919893 # average UpgradeReq miss latency
1165system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127684.570244 # average ReadExReq miss latency
1166system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127684.570244 # average ReadExReq miss latency
1167system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 133629.520711 # average ReadCleanReq miss latency
1168system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 133629.520711 # average ReadCleanReq miss latency
1169system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 137721.774194 # average ReadSharedReq miss latency
1170system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135071.428571 # average ReadSharedReq miss latency
1171system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132083.272981 # average ReadSharedReq miss latency
1172system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132101.835383 # average ReadSharedReq miss latency
1173system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
1174system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
1175system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
1176system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
1177system.cpu.l2cache.demand_avg_miss_latency::total 129143.498740 # average overall miss latency
1178system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
1179system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
1180system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
1181system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
1182system.cpu.l2cache.overall_avg_miss_latency::total 129143.498740 # average overall miss latency
1183system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1184system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1185system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1186system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1187system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1188system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1205system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1206system.cpu.l2cache.cache_copies 0 # number of cache copies performed

1207system.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks
1208system.cpu.l2cache.writebacks::total 98548 # number of writebacks
1209system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
1210system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
1211system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.dtb.walker 1 # number of ReadSharedReq MSHR hits
1212system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
1213system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
1214system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1215system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1216system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
1217system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1218system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1219system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
1220system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
1221system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses
1222system.cpu.l2cache.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses
1223system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127805 # number of ReadExReq MSHR misses
1224system.cpu.l2cache.ReadExReq_mshr_misses::total 127805 # number of ReadExReq MSHR misses
1225system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15980 # number of ReadCleanReq MSHR misses
1226system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15980 # number of ReadCleanReq MSHR misses
1227system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 123 # number of ReadSharedReq MSHR misses
1228system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 7 # number of ReadSharedReq MSHR misses
1229system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 38662 # number of ReadSharedReq MSHR misses
1230system.cpu.l2cache.ReadSharedReq_mshr_misses::total 38792 # number of ReadSharedReq MSHR misses
1231system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 123 # number of demand (read+write) MSHR misses
1232system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1233system.cpu.l2cache.demand_mshr_misses::cpu.inst 15980 # number of demand (read+write) MSHR misses
1234system.cpu.l2cache.demand_mshr_misses::cpu.data 166467 # number of demand (read+write) MSHR misses
1235system.cpu.l2cache.demand_mshr_misses::total 182577 # number of demand (read+write) MSHR misses
1236system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 123 # number of overall MSHR misses
1237system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1238system.cpu.l2cache.overall_mshr_misses::cpu.inst 15980 # number of overall MSHR misses
1239system.cpu.l2cache.overall_mshr_misses::cpu.data 166467 # number of overall MSHR misses
1240system.cpu.l2cache.overall_mshr_misses::total 182577 # number of overall MSHR misses
1241system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
1242system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
1243system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
1244system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
1245system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
1246system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
1247system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102897000 # number of UpgradeReq MSHR miss cycles
1248system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102897000 # number of UpgradeReq MSHR miss cycles
1249system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15040676500 # number of ReadExReq MSHR miss cycles
1250system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15040676500 # number of ReadExReq MSHR miss cycles
1251system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1975642505 # number of ReadCleanReq MSHR miss cycles
1252system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1975642505 # number of ReadCleanReq MSHR miss cycles
1253system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 15740000 # number of ReadSharedReq MSHR miss cycles
1254system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 875500 # number of ReadSharedReq MSHR miss cycles
1255system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4799287008 # number of ReadSharedReq MSHR miss cycles
1256system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4815902508 # number of ReadSharedReq MSHR miss cycles
1257system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15740000 # number of demand (read+write) MSHR miss cycles
1258system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 875500 # number of demand (read+write) MSHR miss cycles
1259system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1975642505 # number of demand (read+write) MSHR miss cycles
1260system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19839963508 # number of demand (read+write) MSHR miss cycles
1261system.cpu.l2cache.demand_mshr_miss_latency::total 21832221513 # number of demand (read+write) MSHR miss cycles
1262system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15740000 # number of overall MSHR miss cycles
1263system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 875500 # number of overall MSHR miss cycles
1264system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1975642505 # number of overall MSHR miss cycles
1265system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508 # number of overall MSHR miss cycles
1266system.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles
1267system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles
1268system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles

1189system.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks
1190system.cpu.l2cache.writebacks::total 98548 # number of writebacks
1191system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
1192system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
1193system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.dtb.walker 1 # number of ReadSharedReq MSHR hits
1194system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
1195system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
1196system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1197system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1198system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
1199system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1200system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1201system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
1202system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
1203system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses
1204system.cpu.l2cache.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses
1205system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127805 # number of ReadExReq MSHR misses
1206system.cpu.l2cache.ReadExReq_mshr_misses::total 127805 # number of ReadExReq MSHR misses
1207system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15980 # number of ReadCleanReq MSHR misses
1208system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15980 # number of ReadCleanReq MSHR misses
1209system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 123 # number of ReadSharedReq MSHR misses
1210system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 7 # number of ReadSharedReq MSHR misses
1211system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 38662 # number of ReadSharedReq MSHR misses
1212system.cpu.l2cache.ReadSharedReq_mshr_misses::total 38792 # number of ReadSharedReq MSHR misses
1213system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 123 # number of demand (read+write) MSHR misses
1214system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1215system.cpu.l2cache.demand_mshr_misses::cpu.inst 15980 # number of demand (read+write) MSHR misses
1216system.cpu.l2cache.demand_mshr_misses::cpu.data 166467 # number of demand (read+write) MSHR misses
1217system.cpu.l2cache.demand_mshr_misses::total 182577 # number of demand (read+write) MSHR misses
1218system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 123 # number of overall MSHR misses
1219system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1220system.cpu.l2cache.overall_mshr_misses::cpu.inst 15980 # number of overall MSHR misses
1221system.cpu.l2cache.overall_mshr_misses::cpu.data 166467 # number of overall MSHR misses
1222system.cpu.l2cache.overall_mshr_misses::total 182577 # number of overall MSHR misses
1223system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
1224system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
1225system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
1226system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
1227system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
1228system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
1229system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102897000 # number of UpgradeReq MSHR miss cycles
1230system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102897000 # number of UpgradeReq MSHR miss cycles
1231system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15040676500 # number of ReadExReq MSHR miss cycles
1232system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15040676500 # number of ReadExReq MSHR miss cycles
1233system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1975642505 # number of ReadCleanReq MSHR miss cycles
1234system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1975642505 # number of ReadCleanReq MSHR miss cycles
1235system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 15740000 # number of ReadSharedReq MSHR miss cycles
1236system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 875500 # number of ReadSharedReq MSHR miss cycles
1237system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4799287008 # number of ReadSharedReq MSHR miss cycles
1238system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4815902508 # number of ReadSharedReq MSHR miss cycles
1239system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15740000 # number of demand (read+write) MSHR miss cycles
1240system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 875500 # number of demand (read+write) MSHR miss cycles
1241system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1975642505 # number of demand (read+write) MSHR miss cycles
1242system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19839963508 # number of demand (read+write) MSHR miss cycles
1243system.cpu.l2cache.demand_mshr_miss_latency::total 21832221513 # number of demand (read+write) MSHR miss cycles
1244system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15740000 # number of overall MSHR miss cycles
1245system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 875500 # number of overall MSHR miss cycles
1246system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1975642505 # number of overall MSHR miss cycles
1247system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508 # number of overall MSHR miss cycles
1248system.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles
1249system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles
1250system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles

1269system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2627781000 # number of WriteReq MSHR uncacheable cycles
1270system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2627781000 # number of WriteReq MSHR uncacheable cycles
1271system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93576407000 # number of overall MSHR uncacheable cycles
1272system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93576407000 # number of overall MSHR uncacheable cycles

1251system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles
1252system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles

1273system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1274system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1275system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses
1276system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses
1277system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses
1278system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses
1279system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses
1280system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses
1281system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for ReadSharedReq accesses
1282system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for ReadSharedReq accesses
1283system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.027248 # mshr miss rate for ReadSharedReq accesses
1284system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024665 # mshr miss rate for ReadSharedReq accesses
1285system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for demand accesses
1286system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for demand accesses
1287system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for demand accesses
1288system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for demand accesses
1289system.cpu.l2cache.demand_mshr_miss_rate::total 0.058301 # mshr miss rate for demand accesses
1290system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for overall accesses
1291system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for overall accesses
1292system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for overall accesses
1293system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for overall accesses
1294system.cpu.l2cache.overall_mshr_miss_rate::total 0.058301 # mshr miss rate for overall accesses
1295system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115 # average UpgradeReq mshr miss latency
1296system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115 # average UpgradeReq mshr miss latency
1297system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244 # average ReadExReq mshr miss latency
1298system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244 # average ReadExReq mshr miss latency
1299system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809 # average ReadCleanReq mshr miss latency
1300system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809 # average ReadCleanReq mshr miss latency
1301system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average ReadSharedReq mshr miss latency
1302system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average ReadSharedReq mshr miss latency
1303system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333 # average ReadSharedReq mshr miss latency
1304system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937 # average ReadSharedReq mshr miss latency
1305system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
1306system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
1307system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
1308system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
1309system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
1310system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
1311system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
1312system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
1313system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
1314system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
1315system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency
1316system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency

1253system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1254system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1255system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses
1256system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses
1257system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses
1258system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses
1259system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses
1260system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses
1261system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for ReadSharedReq accesses
1262system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for ReadSharedReq accesses
1263system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.027248 # mshr miss rate for ReadSharedReq accesses
1264system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024665 # mshr miss rate for ReadSharedReq accesses
1265system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for demand accesses
1266system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for demand accesses
1267system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for demand accesses
1268system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for demand accesses
1269system.cpu.l2cache.demand_mshr_miss_rate::total 0.058301 # mshr miss rate for demand accesses
1270system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for overall accesses
1271system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for overall accesses
1272system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for overall accesses
1273system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for overall accesses
1274system.cpu.l2cache.overall_mshr_miss_rate::total 0.058301 # mshr miss rate for overall accesses
1275system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115 # average UpgradeReq mshr miss latency
1276system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115 # average UpgradeReq mshr miss latency
1277system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244 # average ReadExReq mshr miss latency
1278system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244 # average ReadExReq mshr miss latency
1279system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809 # average ReadCleanReq mshr miss latency
1280system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809 # average ReadCleanReq mshr miss latency
1281system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average ReadSharedReq mshr miss latency
1282system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average ReadSharedReq mshr miss latency
1283system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333 # average ReadSharedReq mshr miss latency
1284system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937 # average ReadSharedReq mshr miss latency
1285system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
1286system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
1287system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
1288system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
1289system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
1290system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
1291system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
1292system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
1293system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
1294system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
1295system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency
1296system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency

1317system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188047.874624 # average WriteReq mshr uncacheable latency
1318system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188047.874624 # average WriteReq mshr uncacheable latency
1319system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159292.547451 # average overall mshr uncacheable latency
1320system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159292.547451 # average overall mshr uncacheable latency
1321system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1297system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency
1298system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency

1322system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter.
1323system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1324system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1325system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter.
1326system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1327system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1328system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution
1329system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution
1330system.cpu.toL2Bus.trans_dist::WriteReq 13974 # Transaction distribution
1331system.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution
1332system.cpu.toL2Bus.trans_dist::WritebackDirty 1776699 # Transaction distribution
1333system.cpu.toL2Bus.trans_dist::WritebackClean 1273398 # Transaction distribution
1334system.cpu.toL2Bus.trans_dist::CleanEvict 245932 # Transaction distribution
1335system.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution
1336system.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution
1337system.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution
1338system.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution
1339system.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution
1340system.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution
1341system.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution
1342system.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution
1343system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
1344system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes)
1345system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes)
1346system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes)
1347system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes)
1348system.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes)
1349system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes)
1350system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes)
1351system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes)
1352system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes)
1353system.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes)
1354system.cpu.toL2Bus.snoops 217979 # Total snoops (count)
1355system.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram
1356system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
1357system.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram
1358system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1359system.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram
1360system.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram
1361system.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram
1362system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
1363system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1364system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1365system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1366system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1367system.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram
1368system.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks)
1369system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1370system.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks)
1371system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1372system.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks)
1373system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1374system.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks)
1375system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1376system.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks)
1377system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1378system.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks)
1379system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1380system.iobus.trans_dist::ReadReq 212035 # Transaction distribution
1381system.iobus.trans_dist::ReadResp 212035 # Transaction distribution
1382system.iobus.trans_dist::WriteReq 57756 # Transaction distribution
1383system.iobus.trans_dist::WriteResp 57756 # Transaction distribution
1384system.iobus.trans_dist::MessageReq 1666 # Transaction distribution
1385system.iobus.trans_dist::MessageResp 1666 # Transaction distribution
1386system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1387system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1388system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1389system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1390system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
1391system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1392system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1393system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
1394system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1395system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1396system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1397system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1398system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1399system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1400system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1401system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1402system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
1403system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes)
1404system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
1405system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
1406system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes)
1407system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes)
1408system.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes)
1409system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1410system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1411system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1412system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1413system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
1414system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1415system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1416system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
1417system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1418system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1419system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1420system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1421system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1422system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1423system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1424system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1425system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
1426system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes)
1427system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
1428system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
1429system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes)
1430system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes)
1431system.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes)
1432system.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks)
1433system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1434system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks)
1435system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1436system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1437system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1438system.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks)
1439system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1440system.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks)
1441system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1442system.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks)
1443system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1444system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
1445system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1446system.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks)
1447system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1448system.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks)
1449system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1450system.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks)
1451system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1452system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
1453system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1454system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
1455system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
1456system.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks)
1457system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1458system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
1459system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1460system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
1461system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1462system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1463system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1464system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
1465system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1466system.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks)
1467system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1468system.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks)
1469system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1470system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks)
1471system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1472system.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks)
1473system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1474system.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks)
1475system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1476system.iocache.tags.replacements 47572 # number of replacements
1477system.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use
1478system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1479system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
1480system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1481system.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit.
1482system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor
1483system.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy
1484system.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy
1485system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1486system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1487system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1488system.iocache.tags.tag_accesses 428643 # Number of tag accesses
1489system.iocache.tags.data_accesses 428643 # Number of data accesses
1490system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
1491system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
1492system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
1493system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses

1299system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter.
1300system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1301system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1302system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter.
1303system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1304system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1305system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution
1306system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution
1307system.cpu.toL2Bus.trans_dist::WriteReq 13974 # Transaction distribution
1308system.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution
1309system.cpu.toL2Bus.trans_dist::WritebackDirty 1776699 # Transaction distribution
1310system.cpu.toL2Bus.trans_dist::WritebackClean 1273398 # Transaction distribution
1311system.cpu.toL2Bus.trans_dist::CleanEvict 245932 # Transaction distribution
1312system.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution
1313system.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution
1314system.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution
1315system.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution
1316system.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution
1317system.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution
1318system.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution
1319system.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution
1320system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
1321system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes)
1322system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes)
1323system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes)
1324system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes)
1325system.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes)
1326system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes)
1327system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes)
1328system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes)
1329system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes)
1330system.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes)
1331system.cpu.toL2Bus.snoops 217979 # Total snoops (count)
1332system.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram
1333system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
1334system.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram
1335system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1336system.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram
1337system.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram
1338system.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram
1339system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
1340system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1341system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1342system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1343system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1344system.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram
1345system.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks)
1346system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1347system.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks)
1348system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1349system.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks)
1350system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1351system.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks)
1352system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1353system.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks)
1354system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1355system.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks)
1356system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1357system.iobus.trans_dist::ReadReq 212035 # Transaction distribution
1358system.iobus.trans_dist::ReadResp 212035 # Transaction distribution
1359system.iobus.trans_dist::WriteReq 57756 # Transaction distribution
1360system.iobus.trans_dist::WriteResp 57756 # Transaction distribution
1361system.iobus.trans_dist::MessageReq 1666 # Transaction distribution
1362system.iobus.trans_dist::MessageResp 1666 # Transaction distribution
1363system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1364system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1365system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1366system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1367system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
1368system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1369system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1370system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
1371system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1372system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1373system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1374system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1375system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1376system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1377system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1378system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1379system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
1380system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes)
1381system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
1382system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
1383system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes)
1384system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes)
1385system.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes)
1386system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1387system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1388system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1389system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1390system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
1391system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1392system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1393system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
1394system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1395system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1396system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1397system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1398system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1399system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1400system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1401system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1402system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
1403system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes)
1404system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
1405system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
1406system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes)
1407system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes)
1408system.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes)
1409system.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks)
1410system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1411system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks)
1412system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1413system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1414system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1415system.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks)
1416system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1417system.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks)
1418system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1419system.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks)
1420system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1421system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
1422system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1423system.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks)
1424system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1425system.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks)
1426system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1427system.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks)
1428system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1429system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
1430system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1431system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
1432system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
1433system.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks)
1434system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1435system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
1436system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1437system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
1438system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1439system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1440system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1441system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
1442system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1443system.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks)
1444system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1445system.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks)
1446system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1447system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks)
1448system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1449system.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks)
1450system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1451system.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks)
1452system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1453system.iocache.tags.replacements 47572 # number of replacements
1454system.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use
1455system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1456system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
1457system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1458system.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit.
1459system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor
1460system.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy
1461system.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy
1462system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1463system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1464system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1465system.iocache.tags.tag_accesses 428643 # Number of tag accesses
1466system.iocache.tags.data_accesses 428643 # Number of data accesses
1467system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
1468system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
1469system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
1470system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses

1494system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
1495system.iocache.demand_misses::total 907 # number of demand (read+write) misses
1496system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
1497system.iocache.overall_misses::total 907 # number of overall misses

1471system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
1472system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
1473system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
1474system.iocache.overall_misses::total 47627 # number of overall misses

1498system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles
1499system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles
1500system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles
1501system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles

1475system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles
1476system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles
1477system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles
1478system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles

1502system.iocache.demand_miss_latency::pc.south_bridge.ide 150838200 # number of demand (read+write) miss cycles
1503system.iocache.demand_miss_latency::total 150838200 # number of demand (read+write) miss cycles
1504system.iocache.overall_miss_latency::pc.south_bridge.ide 150838200 # number of overall miss cycles
1505system.iocache.overall_miss_latency::total 150838200 # number of overall miss cycles

1479system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
1480system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
1481system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
1482system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles

1506system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
1507system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
1508system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
1509system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)

1483system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
1484system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
1485system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
1486system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)

1510system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
1511system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
1512system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
1513system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses

1487system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
1488system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
1489system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
1490system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses

1514system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1515system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1516system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
1517system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1518system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1519system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1520system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1521system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1522system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency
1523system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency
1524system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency
1525system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency

1491system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1492system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1493system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
1494system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1495system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1496system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1497system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1498system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1499system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency
1500system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency
1501system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency
1502system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency

1526system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency
1527system.iocache.demand_avg_miss_latency::total 166304.520397 # average overall miss latency
1528system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency
1529system.iocache.overall_avg_miss_latency::total 166304.520397 # average overall miss latency

1503system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
1504system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
1505system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
1506system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency

1530system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
1531system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1532system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
1533system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1534system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
1535system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1507system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
1508system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1509system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
1510system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1511system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
1512system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1536system.iocache.fast_writes 0 # number of fast writes performed
1537system.iocache.cache_copies 0 # number of cache copies performed

1538system.iocache.writebacks::writebacks 46667 # number of writebacks
1539system.iocache.writebacks::total 46667 # number of writebacks
1540system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
1541system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
1542system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
1543system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses

1513system.iocache.writebacks::writebacks 46667 # number of writebacks
1514system.iocache.writebacks::total 46667 # number of writebacks
1515system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
1516system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
1517system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
1518system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses

1544system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
1545system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
1546system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
1547system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses

1519system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
1520system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
1521system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
1522system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses

1548system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles
1549system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles
1550system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles
1551system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles

1523system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles
1524system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles
1525system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles
1526system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles

1552system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of demand (read+write) MSHR miss cycles
1553system.iocache.demand_mshr_miss_latency::total 105488200 # number of demand (read+write) MSHR miss cycles
1554system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of overall MSHR miss cycles
1555system.iocache.overall_mshr_miss_latency::total 105488200 # number of overall MSHR miss cycles

1527system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
1528system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
1529system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
1530system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles

1556system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1557system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1558system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
1559system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1560system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1561system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1562system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1563system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1564system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency
1565system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency
1566system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency
1567system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency

1531system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1532system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1533system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
1534system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1535system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1536system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1537system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1538system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1539system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency
1540system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency
1541system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency
1542system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency

1568system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency
1569system.iocache.demand_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency
1570system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency
1571system.iocache.overall_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency
1572system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate

1543system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
1544system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
1545system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
1546system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency