Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.122213 # Number of seconds simulated
4sim_ticks 5122212682000 # Number of ticks simulated
5final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 132606 # Simulator instruction rate (inst/s)
8host_op_rate 262116 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1665061517 # Simulator tick rate (ticks/s)
10host_mem_usage 804736 # Number of bytes of host memory used
11host_seconds 3076.29 # Real time elapsed on the host

7host_inst_rate 178126 # Simulator instruction rate (inst/s)
8host_op_rate 352092 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2236626113 # Simulator tick rate (ticks/s)
10host_mem_usage 810964 # Number of bytes of host memory used
11host_seconds 2290.15 # Real time elapsed on the host

12sim_insts 407934867 # Number of instructions simulated
13sim_ops 806343968 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 10801152 # Number of bytes read from this memory
20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21system.physmem.bytes_read::total 11881280 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 9569088 # Number of bytes written to this memory
25system.physmem.bytes_written::total 9569088 # Number of bytes written to this memory
26system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 168768 # Number of read requests responded to by this memory
30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31system.physmem.num_reads::total 185645 # Number of read requests responded to by this memory
32system.physmem.num_writes::writebacks 149517 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 149517 # Number of write requests responded to by this memory
34system.physmem.bw_read::cpu.dtb.walker 825 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.inst 204424 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.data 2108689 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 2319560 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 204424 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 204424 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1868155 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 1868155 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 1868155 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.dtb.walker 825 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.inst 204424 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.data 2108689 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 4187715 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.readReqs 185645 # Number of read requests accepted
52system.physmem.writeReqs 196237 # Number of write requests accepted
53system.physmem.readBursts 185645 # Number of DRAM read bursts, including those serviced by the write queue
54system.physmem.writeBursts 196237 # Number of DRAM write bursts, including those merged in the write queue
55system.physmem.bytesReadDRAM 11872960 # Total number of bytes read from DRAM
56system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
57system.physmem.bytesWritten 10880320 # Total number of bytes written to DRAM
58system.physmem.bytesReadSys 11881280 # Total read bytes from the system interface side
59system.physmem.bytesWrittenSys 12559168 # Total written bytes from the system interface side
60system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
61system.physmem.mergedWrBursts 26214 # Number of DRAM write bursts merged with an existing one
62system.physmem.neitherReadNorWriteReqs 1708 # Number of requests that are neither read nor write
63system.physmem.perBankRdBursts::0 11253 # Per bank write bursts
64system.physmem.perBankRdBursts::1 10547 # Per bank write bursts
65system.physmem.perBankRdBursts::2 11972 # Per bank write bursts
66system.physmem.perBankRdBursts::3 11655 # Per bank write bursts
67system.physmem.perBankRdBursts::4 11971 # Per bank write bursts
68system.physmem.perBankRdBursts::5 11254 # Per bank write bursts
69system.physmem.perBankRdBursts::6 11364 # Per bank write bursts
70system.physmem.perBankRdBursts::7 11315 # Per bank write bursts
71system.physmem.perBankRdBursts::8 11445 # Per bank write bursts
72system.physmem.perBankRdBursts::9 11672 # Per bank write bursts
73system.physmem.perBankRdBursts::10 11062 # Per bank write bursts
74system.physmem.perBankRdBursts::11 11423 # Per bank write bursts
75system.physmem.perBankRdBursts::12 12308 # Per bank write bursts
76system.physmem.perBankRdBursts::13 12737 # Per bank write bursts
77system.physmem.perBankRdBursts::14 11748 # Per bank write bursts
78system.physmem.perBankRdBursts::15 11789 # Per bank write bursts
79system.physmem.perBankWrBursts::0 11864 # Per bank write bursts
80system.physmem.perBankWrBursts::1 10686 # Per bank write bursts
81system.physmem.perBankWrBursts::2 10651 # Per bank write bursts
82system.physmem.perBankWrBursts::3 9860 # Per bank write bursts
83system.physmem.perBankWrBursts::4 10294 # Per bank write bursts
84system.physmem.perBankWrBursts::5 10368 # Per bank write bursts
85system.physmem.perBankWrBursts::6 9733 # Per bank write bursts
86system.physmem.perBankWrBursts::7 9712 # Per bank write bursts
87system.physmem.perBankWrBursts::8 9632 # Per bank write bursts
88system.physmem.perBankWrBursts::9 10471 # Per bank write bursts
89system.physmem.perBankWrBursts::10 10725 # Per bank write bursts
90system.physmem.perBankWrBursts::11 10392 # Per bank write bursts
91system.physmem.perBankWrBursts::12 11457 # Per bank write bursts
92system.physmem.perBankWrBursts::13 11384 # Per bank write bursts
93system.physmem.perBankWrBursts::14 11667 # Per bank write bursts
94system.physmem.perBankWrBursts::15 11109 # Per bank write bursts
95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96system.physmem.numWrRetry 85 # Number of times write queue was full causing retry
97system.physmem.totGap 5122212630000 # Total gap between requests
98system.physmem.readPktSize::0 0 # Read request sizes (log2)
99system.physmem.readPktSize::1 0 # Read request sizes (log2)
100system.physmem.readPktSize::2 0 # Read request sizes (log2)
101system.physmem.readPktSize::3 0 # Read request sizes (log2)
102system.physmem.readPktSize::4 0 # Read request sizes (log2)
103system.physmem.readPktSize::5 0 # Read request sizes (log2)
104system.physmem.readPktSize::6 185645 # Read request sizes (log2)
105system.physmem.writePktSize::0 0 # Write request sizes (log2)
106system.physmem.writePktSize::1 0 # Write request sizes (log2)
107system.physmem.writePktSize::2 0 # Write request sizes (log2)
108system.physmem.writePktSize::3 0 # Write request sizes (log2)
109system.physmem.writePktSize::4 0 # Write request sizes (log2)
110system.physmem.writePktSize::5 0 # Write request sizes (log2)
111system.physmem.writePktSize::6 196237 # Write request sizes (log2)
112system.physmem.rdQLenPdf::0 171240 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::1 11542 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::2 1948 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::3 451 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::15 1627 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::16 1832 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::17 6256 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::18 6771 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::19 7099 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::20 7167 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::21 7342 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::22 7542 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::24 7845 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::25 7971 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::26 9622 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::27 8300 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::28 7727 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::29 10480 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::30 8737 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::31 8045 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::32 7914 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::33 1477 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::34 1264 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::35 1705 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::36 2725 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::37 2849 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::38 2539 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::39 2444 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::40 3285 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::41 2479 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::42 2385 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::43 2208 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::44 2459 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::45 2080 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::46 1741 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::47 1599 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::48 1189 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::49 975 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::51 399 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::52 342 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::53 363 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::54 239 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::56 292 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::57 197 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::58 189 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::59 194 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::61 152 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::62 120 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see
208system.physmem.bytesPerActivate::samples 73901 # Bytes accessed per row activation
209system.physmem.bytesPerActivate::mean 307.887796 # Bytes accessed per row activation
210system.physmem.bytesPerActivate::gmean 180.352303 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::stdev 329.737558 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::0-127 28243 38.22% 38.22% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::128-255 17330 23.45% 61.67% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::256-383 7468 10.11% 71.77% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::384-511 4217 5.71% 77.48% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::512-639 3016 4.08% 81.56% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::640-767 1973 2.67% 84.23% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::768-895 1390 1.88% 86.11% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::896-1023 1267 1.71% 87.83% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::1024-1151 8997 12.17% 100.00% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::total 73901 # Bytes accessed per row activation
222system.physmem.rdPerTurnAround::samples 6788 # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::mean 27.329258 # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::stdev 584.024068 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::0-2047 6787 99.99% 99.99% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::total 6788 # Reads before turning the bus around for writes
228system.physmem.wrPerTurnAround::samples 6788 # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::mean 25.044932 # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::gmean 18.591825 # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::stdev 43.260290 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::16-31 6382 94.02% 94.02% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::32-47 87 1.28% 95.30% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::48-63 9 0.13% 95.43% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::64-79 9 0.13% 95.57% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::80-95 22 0.32% 95.89% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::96-111 15 0.22% 96.11% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::112-127 29 0.43% 96.54% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::128-143 26 0.38% 96.92% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::144-159 35 0.52% 97.44% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::160-175 9 0.13% 97.57% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::176-191 41 0.60% 98.17% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::192-207 54 0.80% 98.97% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::208-223 7 0.10% 99.07% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::224-239 6 0.09% 99.16% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::256-271 1 0.01% 99.18% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::272-287 4 0.06% 99.23% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::288-303 2 0.03% 99.26% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::304-319 4 0.06% 99.32% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::320-335 3 0.04% 99.37% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::336-351 5 0.07% 99.44% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::352-367 19 0.28% 99.72% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::368-383 6 0.09% 99.81% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::384-399 1 0.01% 99.82% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::400-415 1 0.01% 99.84% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::464-479 1 0.01% 99.85% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::480-495 1 0.01% 99.87% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::496-511 3 0.04% 99.91% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::512-527 1 0.01% 99.93% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::544-559 1 0.01% 99.94% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::560-575 4 0.06% 100.00% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::total 6788 # Writes before turning the bus around for reads
263system.physmem.totQLat 2015945224 # Total ticks spent queuing
264system.physmem.totMemAccLat 5494351474 # Total ticks spent from burst creation until serviced by the DRAM
265system.physmem.totBusLat 927575000 # Total ticks spent in databus transfers
266system.physmem.avgQLat 10866.75 # Average queueing delay per DRAM burst
267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
268system.physmem.avgMemAccLat 29616.75 # Average memory access latency per DRAM burst
269system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
270system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s
271system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
272system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
274system.physmem.busUtil 0.03 # Data bus utilization in percentage
275system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
276system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
277system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
278system.physmem.avgWrQLen 22.03 # Average write queue length when enqueuing
279system.physmem.readRowHits 152167 # Number of row buffer hits during reads
280system.physmem.writeRowHits 129451 # Number of row buffer hits during writes
281system.physmem.readRowHitRate 82.02 # Row buffer hit rate for reads
282system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
283system.physmem.avgGap 13413076.89 # Average gap between requests
284system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined
285system.physmem_0.actEnergy 269256960 # Energy for activate commands per rank (pJ)
286system.physmem_0.preEnergy 146916000 # Energy for precharge commands per rank (pJ)
287system.physmem_0.readEnergy 712374000 # Energy for read commands per rank (pJ)
288system.physmem_0.writeEnergy 538928640 # Energy for write commands per rank (pJ)
289system.physmem_0.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ)
290system.physmem_0.actBackEnergy 129214187775 # Energy for active background per rank (pJ)
291system.physmem_0.preBackEnergy 2959979121750 # Energy for precharge background per rank (pJ)
292system.physmem_0.totalEnergy 3425418506805 # Total energy per rank (pJ)
293system.physmem_0.averagePower 668.738637 # Core power per rank (mW)
294system.physmem_0.memoryStateTime::IDLE 4924130039468 # Time in different power states
295system.physmem_0.memoryStateTime::REF 171041780000 # Time in different power states
296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
297system.physmem_0.memoryStateTime::ACT 27040752032 # Time in different power states
298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
299system.physmem_1.actEnergy 289434600 # Energy for activate commands per rank (pJ)
300system.physmem_1.preEnergy 157925625 # Energy for precharge commands per rank (pJ)
301system.physmem_1.readEnergy 734635200 # Energy for read commands per rank (pJ)
302system.physmem_1.writeEnergy 562703760 # Energy for write commands per rank (pJ)
303system.physmem_1.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ)
304system.physmem_1.actBackEnergy 129751534755 # Energy for active background per rank (pJ)
305system.physmem_1.preBackEnergy 2959507764750 # Energy for precharge background per rank (pJ)
306system.physmem_1.totalEnergy 3425561720370 # Total energy per rank (pJ)
307system.physmem_1.averagePower 668.766596 # Core power per rank (mW)
308system.physmem_1.memoryStateTime::IDLE 4923333713433 # Time in different power states
309system.physmem_1.memoryStateTime::REF 171041780000 # Time in different power states
310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
311system.physmem_1.memoryStateTime::ACT 27832687817 # Time in different power states
312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
313system.cpu.branchPred.lookups 86818912 # Number of BP lookups
314system.cpu.branchPred.condPredicted 86818912 # Number of conditional branches predicted
315system.cpu.branchPred.condIncorrect 895085 # Number of conditional branches incorrect
316system.cpu.branchPred.BTBLookups 80098723 # Number of BTB lookups
317system.cpu.branchPred.BTBHits 78142837 # Number of BTB hits
318system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
319system.cpu.branchPred.BTBHitPct 97.558156 # BTB Hit Percentage
320system.cpu.branchPred.usedRAS 1551403 # Number of times the RAS was used to get a target.
321system.cpu.branchPred.RASInCorrect 180089 # Number of incorrect RAS predictions.
322system.cpu_clk_domain.clock 500 # Clock period in ticks
323system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
324system.cpu.numCycles 449999443 # number of cpu cycles simulated
325system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
326system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
327system.cpu.fetch.icacheStallCycles 27536923 # Number of cycles fetch is stalled on an Icache miss
328system.cpu.fetch.Insts 428761982 # Number of instructions fetch has processed
329system.cpu.fetch.Branches 86818912 # Number of branches that fetch encountered
330system.cpu.fetch.predictedBranches 79694240 # Number of branches that fetch has predicted taken
331system.cpu.fetch.Cycles 418469892 # Number of cycles fetch has run and was not squashing or blocked
332system.cpu.fetch.SquashCycles 1877186 # Number of cycles fetch has spent squashing
333system.cpu.fetch.TlbCycles 142405 # Number of cycles fetch has spent waiting for tlb
334system.cpu.fetch.MiscStallCycles 58257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
335system.cpu.fetch.PendingTrapStallCycles 203994 # Number of stall cycles due to pending traps
336system.cpu.fetch.PendingQuiesceStallCycles 110 # Number of stall cycles due to pending quiesce instructions
337system.cpu.fetch.IcacheWaitRetryStallCycles 541 # Number of stall cycles due to full MSHR
338system.cpu.fetch.CacheLines 9116293 # Number of cache lines fetched
339system.cpu.fetch.IcacheSquashes 453128 # Number of outstanding Icache misses that were squashed
340system.cpu.fetch.ItlbSquashes 4723 # Number of outstanding ITLB misses that were squashed
341system.cpu.fetch.rateDist::samples 447350715 # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.rateDist::mean 1.891249 # Number of instructions fetched each cycle (Total)
343system.cpu.fetch.rateDist::stdev 3.050769 # Number of instructions fetched each cycle (Total)
344system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
345system.cpu.fetch.rateDist::0 282061925 63.05% 63.05% # Number of instructions fetched each cycle (Total)
346system.cpu.fetch.rateDist::1 2147503 0.48% 63.53% # Number of instructions fetched each cycle (Total)
347system.cpu.fetch.rateDist::2 72168287 16.13% 79.66% # Number of instructions fetched each cycle (Total)
348system.cpu.fetch.rateDist::3 1568006 0.35% 80.01% # Number of instructions fetched each cycle (Total)
349system.cpu.fetch.rateDist::4 2127596 0.48% 80.49% # Number of instructions fetched each cycle (Total)
350system.cpu.fetch.rateDist::5 2318806 0.52% 81.01% # Number of instructions fetched each cycle (Total)
351system.cpu.fetch.rateDist::6 1512611 0.34% 81.35% # Number of instructions fetched each cycle (Total)
352system.cpu.fetch.rateDist::7 1884650 0.42% 81.77% # Number of instructions fetched each cycle (Total)
353system.cpu.fetch.rateDist::8 81561331 18.23% 100.00% # Number of instructions fetched each cycle (Total)
354system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
355system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
356system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
357system.cpu.fetch.rateDist::total 447350715 # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.branchRate 0.192931 # Number of branch fetches per cycle
359system.cpu.fetch.rate 0.952806 # Number of inst fetches per cycle
360system.cpu.decode.IdleCycles 22908567 # Number of cycles decode is idle
361system.cpu.decode.BlockedCycles 265367852 # Number of cycles decode is blocked
362system.cpu.decode.RunCycles 150702709 # Number of cycles decode is running
363system.cpu.decode.UnblockCycles 7432994 # Number of cycles decode is unblocking
364system.cpu.decode.SquashCycles 938593 # Number of cycles decode is squashing
365system.cpu.decode.DecodedInsts 837990299 # Number of instructions handled by decode
366system.cpu.rename.SquashCycles 938593 # Number of cycles rename is squashing
367system.cpu.rename.IdleCycles 25758226 # Number of cycles rename is idle
368system.cpu.rename.BlockCycles 223276953 # Number of cycles rename is blocking
369system.cpu.rename.serializeStallCycles 12890661 # count of cycles rename stalled for serializing inst
370system.cpu.rename.RunCycles 154592541 # Number of cycles rename is running
371system.cpu.rename.UnblockCycles 29893741 # Number of cycles rename is unblocking
372system.cpu.rename.RenamedInsts 834466404 # Number of instructions processed by rename
373system.cpu.rename.ROBFullEvents 451836 # Number of times rename has blocked due to ROB full
374system.cpu.rename.IQFullEvents 12178537 # Number of times rename has blocked due to IQ full
375system.cpu.rename.LQFullEvents 145180 # Number of times rename has blocked due to LQ full
376system.cpu.rename.SQFullEvents 14794285 # Number of times rename has blocked due to SQ full
377system.cpu.rename.RenamedOperands 996780528 # Number of destination operands rename has renamed
378system.cpu.rename.RenameLookups 1812316725 # Number of register rename lookups that rename has made
379system.cpu.rename.int_rename_lookups 1114082490 # Number of integer rename lookups
380system.cpu.rename.fp_rename_lookups 470 # Number of floating rename lookups
381system.cpu.rename.CommittedMaps 964296204 # Number of HB maps that are committed
382system.cpu.rename.UndoneMaps 32484322 # Number of HB maps that are undone due to squashing
383system.cpu.rename.serializingInsts 461178 # count of serializing insts renamed
384system.cpu.rename.tempSerializingInsts 464876 # count of temporary serializing insts renamed
385system.cpu.rename.skidInsts 38644871 # count of insts added to the skid buffer
386system.cpu.memDep0.insertedLoads 17242919 # Number of loads inserted to the mem dependence unit.
387system.cpu.memDep0.insertedStores 10123129 # Number of stores inserted to the mem dependence unit.
388system.cpu.memDep0.conflictingLoads 1280249 # Number of conflicting loads.
389system.cpu.memDep0.conflictingStores 1072002 # Number of conflicting stores.
390system.cpu.iq.iqInstsAdded 828945592 # Number of instructions added to the IQ (excludes non-spec)
391system.cpu.iq.iqNonSpecInstsAdded 1192163 # Number of non-speculative instructions added to the IQ
392system.cpu.iq.iqInstsIssued 823760090 # Number of instructions issued
393system.cpu.iq.iqSquashedInstsIssued 244912 # Number of squashed instructions issued
394system.cpu.iq.iqSquashedInstsExamined 23793782 # Number of squashed instructions iterated over during squash; mainly for profiling
395system.cpu.iq.iqSquashedOperandsExamined 35793426 # Number of squashed operands that are examined and possibly removed from graph
396system.cpu.iq.iqSquashedNonSpecRemoved 146866 # Number of squashed non-spec instructions that were removed
397system.cpu.iq.issued_per_cycle::samples 447350715 # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::mean 1.841419 # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::stdev 2.417821 # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
401system.cpu.iq.issued_per_cycle::0 263279849 58.85% 58.85% # Number of insts issued each cycle
402system.cpu.iq.issued_per_cycle::1 13891965 3.11% 61.96% # Number of insts issued each cycle
403system.cpu.iq.issued_per_cycle::2 9851915 2.20% 64.16% # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::3 7048956 1.58% 65.74% # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::4 74303394 16.61% 82.35% # Number of insts issued each cycle
406system.cpu.iq.issued_per_cycle::5 4391366 0.98% 83.33% # Number of insts issued each cycle
407system.cpu.iq.issued_per_cycle::6 72807233 16.28% 99.60% # Number of insts issued each cycle
408system.cpu.iq.issued_per_cycle::7 1204673 0.27% 99.87% # Number of insts issued each cycle
409system.cpu.iq.issued_per_cycle::8 571364 0.13% 100.00% # Number of insts issued each cycle
410system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
411system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
412system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
413system.cpu.iq.issued_per_cycle::total 447350715 # Number of insts issued each cycle
414system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
415system.cpu.iq.fu_full::IntAlu 1986394 72.18% 72.18% # attempts to use FU when none available
416system.cpu.iq.fu_full::IntMult 0 0.00% 72.18% # attempts to use FU when none available
417system.cpu.iq.fu_full::IntDiv 0 0.00% 72.18% # attempts to use FU when none available
418system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.18% # attempts to use FU when none available
419system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.18% # attempts to use FU when none available
420system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.18% # attempts to use FU when none available
421system.cpu.iq.fu_full::FloatMult 0 0.00% 72.18% # attempts to use FU when none available
422system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.18% # attempts to use FU when none available
423system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.18% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.18% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.18% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.18% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.18% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.18% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.18% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdMult 0 0.00% 72.18% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.18% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdShift 0 0.00% 72.18% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.18% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.18% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.18% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.18% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.18% # attempts to use FU when none available
438system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.18% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.18% # attempts to use FU when none available
440system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.18% # attempts to use FU when none available
441system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.18% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.18% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.18% # attempts to use FU when none available
444system.cpu.iq.fu_full::MemRead 608344 22.10% 94.28% # attempts to use FU when none available
445system.cpu.iq.fu_full::MemWrite 157420 5.72% 100.00% # attempts to use FU when none available
446system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
447system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
448system.cpu.iq.FU_type_0::No_OpClass 285236 0.03% 0.03% # Type of FU issued
449system.cpu.iq.FU_type_0::IntAlu 795541833 96.57% 96.61% # Type of FU issued
450system.cpu.iq.FU_type_0::IntMult 150365 0.02% 96.63% # Type of FU issued
451system.cpu.iq.FU_type_0::IntDiv 127447 0.02% 96.64% # Type of FU issued
452system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued
453system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued
454system.cpu.iq.FU_type_0::FloatCvt 108 0.00% 96.64% # Type of FU issued
455system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued
456system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued
457system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.64% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.64% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.64% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.64% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.64% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.64% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.64% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.64% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.64% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.64% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.64% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.64% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.64% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.64% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.64% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.64% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued
476system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued
477system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued
478system.cpu.iq.FU_type_0::MemRead 18320687 2.22% 98.87% # Type of FU issued
479system.cpu.iq.FU_type_0::MemWrite 9334414 1.13% 100.00% # Type of FU issued
480system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
481system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
482system.cpu.iq.FU_type_0::total 823760090 # Type of FU issued
483system.cpu.iq.rate 1.830580 # Inst issue rate
484system.cpu.iq.fu_busy_cnt 2752158 # FU busy when requested
485system.cpu.iq.fu_busy_rate 0.003341 # FU busy rate (busy events/executed inst)
486system.cpu.iq.int_inst_queue_reads 2097867450 # Number of integer instruction queue reads
487system.cpu.iq.int_inst_queue_writes 853943468 # Number of integer instruction queue writes
488system.cpu.iq.int_inst_queue_wakeup_accesses 819213197 # Number of integer instruction queue wakeup accesses
489system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads
490system.cpu.iq.fp_inst_queue_writes 630 # Number of floating instruction queue writes
491system.cpu.iq.fp_inst_queue_wakeup_accesses 182 # Number of floating instruction queue wakeup accesses
492system.cpu.iq.int_alu_accesses 826226763 # Number of integer alu accesses
493system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses
494system.cpu.iew.lsq.thread0.forwLoads 1860072 # Number of loads that had data forwarded from stores
495system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
496system.cpu.iew.lsq.thread0.squashedLoads 3252614 # Number of loads squashed
497system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed
498system.cpu.iew.lsq.thread0.memOrderViolation 14318 # Number of memory ordering violations
499system.cpu.iew.lsq.thread0.squashedStores 1702580 # Number of stores squashed
500system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
501system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
502system.cpu.iew.lsq.thread0.rescheduledLoads 2208153 # Number of loads that were rescheduled
503system.cpu.iew.lsq.thread0.cacheBlocked 72229 # Number of times an access to memory failed due to the cache being blocked
504system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
505system.cpu.iew.iewSquashCycles 938593 # Number of cycles IEW is squashing
506system.cpu.iew.iewBlockCycles 204923881 # Number of cycles IEW is blocking
507system.cpu.iew.iewUnblockCycles 10223668 # Number of cycles IEW is unblocking
508system.cpu.iew.iewDispatchedInsts 830137755 # Number of instructions dispatched to IQ
509system.cpu.iew.iewDispSquashedInsts 158534 # Number of squashed instructions skipped by dispatch
510system.cpu.iew.iewDispLoadInsts 17242919 # Number of dispatched load instructions
511system.cpu.iew.iewDispStoreInsts 10123129 # Number of dispatched store instructions
512system.cpu.iew.iewDispNonSpecInsts 698460 # Number of dispatched non-speculative instructions
513system.cpu.iew.iewIQFullEvents 397050 # Number of times the IQ has become full, causing a stall
514system.cpu.iew.iewLSQFullEvents 8973453 # Number of times the LSQ has become full, causing a stall
515system.cpu.iew.memOrderViolationEvents 14318 # Number of memory order violations
516system.cpu.iew.predictedTakenIncorrect 514177 # Number of branches that were predicted taken incorrectly
517system.cpu.iew.predictedNotTakenIncorrect 531213 # Number of branches that were predicted not taken incorrectly
518system.cpu.iew.branchMispredicts 1045390 # Number of branch mispredicts detected at execute
519system.cpu.iew.iewExecutedInsts 822137992 # Number of executed instructions
520system.cpu.iew.iewExecLoadInsts 17928402 # Number of load instructions executed
521system.cpu.iew.iewExecSquashedInsts 1491599 # Number of squashed instructions skipped in execute
522system.cpu.iew.exec_swp 0 # number of swp insts executed
523system.cpu.iew.exec_nop 0 # number of nop insts executed
524system.cpu.iew.exec_refs 27038601 # number of memory reference insts executed
525system.cpu.iew.exec_branches 83256358 # Number of branches executed
526system.cpu.iew.exec_stores 9110199 # Number of stores executed
527system.cpu.iew.exec_rate 1.826976 # Inst execution rate
528system.cpu.iew.wb_sent 821634339 # cumulative count of insts sent to commit
529system.cpu.iew.wb_count 819213379 # cumulative count of insts written-back
530system.cpu.iew.wb_producers 640695638 # num instructions producing a value
531system.cpu.iew.wb_consumers 1049922326 # num instructions consuming a value
532system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
533system.cpu.iew.wb_rate 1.820476 # insts written-back per cycle
534system.cpu.iew.wb_fanout 0.610231 # average fanout of values written-back
535system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
536system.cpu.commit.commitSquashedInsts 23667492 # The number of squashed insts skipped by commit
537system.cpu.commit.commitNonSpecStalls 1045297 # The number of times commit has been forced to stall to communicate backwards
538system.cpu.commit.branchMispredicts 906773 # The number of times a branch was mispredicted
539system.cpu.commit.committed_per_cycle::samples 443789392 # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::mean 1.816952 # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::stdev 2.674122 # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
543system.cpu.commit.committed_per_cycle::0 272960111 61.51% 61.51% # Number of insts commited each cycle
544system.cpu.commit.committed_per_cycle::1 11180384 2.52% 64.03% # Number of insts commited each cycle
545system.cpu.commit.committed_per_cycle::2 3592831 0.81% 64.84% # Number of insts commited each cycle
546system.cpu.commit.committed_per_cycle::3 74586039 16.81% 81.64% # Number of insts commited each cycle
547system.cpu.commit.committed_per_cycle::4 2426818 0.55% 82.19% # Number of insts commited each cycle
548system.cpu.commit.committed_per_cycle::5 1631046 0.37% 82.56% # Number of insts commited each cycle
549system.cpu.commit.committed_per_cycle::6 941888 0.21% 82.77% # Number of insts commited each cycle
550system.cpu.commit.committed_per_cycle::7 71056225 16.01% 98.78% # Number of insts commited each cycle
551system.cpu.commit.committed_per_cycle::8 5414050 1.22% 100.00% # Number of insts commited each cycle
552system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
553system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
554system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
555system.cpu.commit.committed_per_cycle::total 443789392 # Number of insts commited each cycle
556system.cpu.commit.committedInsts 407934867 # Number of instructions committed
557system.cpu.commit.committedOps 806343968 # Number of ops (including micro ops) committed
558system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
559system.cpu.commit.refs 22410853 # Number of memory references committed
560system.cpu.commit.loads 13990304 # Number of loads committed
561system.cpu.commit.membars 471837 # Number of memory barriers committed
562system.cpu.commit.branches 82192569 # Number of branches committed
563system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
564system.cpu.commit.int_insts 735158454 # Number of committed integer instructions.
565system.cpu.commit.function_calls 1155650 # Number of function calls committed.
566system.cpu.commit.op_class_0::No_OpClass 171552 0.02% 0.02% # Class of committed instruction
567system.cpu.commit.op_class_0::IntAlu 783497766 97.17% 97.19% # Class of committed instruction
568system.cpu.commit.op_class_0::IntMult 144918 0.02% 97.21% # Class of committed instruction
569system.cpu.commit.op_class_0::IntDiv 121442 0.02% 97.22% # Class of committed instruction
570system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
571system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
572system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
573system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
574system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
575system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
576system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
577system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
578system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
579system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
580system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
581system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
582system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
583system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
584system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
585system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
586system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
587system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
588system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
589system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
590system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
591system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
592system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
593system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
594system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
595system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
596system.cpu.commit.op_class_0::MemRead 13987725 1.73% 98.96% # Class of committed instruction
597system.cpu.commit.op_class_0::MemWrite 8420549 1.04% 100.00% # Class of committed instruction
598system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
599system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
600system.cpu.commit.op_class_0::total 806343968 # Class of committed instruction
601system.cpu.commit.bw_lim_events 5414050 # number cycles where commit BW limit reached
602system.cpu.rob.rob_reads 1268308634 # The number of ROB reads
603system.cpu.rob.rob_writes 1663603607 # The number of ROB writes
604system.cpu.timesIdled 289860 # Number of times that the entire CPU went into an idle state and unscheduled itself
605system.cpu.idleCycles 2648728 # Total number of cycles that the CPU has spent unscheduled due to idling
606system.cpu.quiesceCycles 9794423343 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
607system.cpu.committedInsts 407934867 # Number of Instructions Simulated
608system.cpu.committedOps 806343968 # Number of Ops (including micro ops) Simulated
609system.cpu.cpi 1.103116 # CPI: Cycles Per Instruction
610system.cpu.cpi_total 1.103116 # CPI: Total CPI of All Threads
611system.cpu.ipc 0.906523 # IPC: Instructions Per Cycle
612system.cpu.ipc_total 0.906523 # IPC: Total IPC of All Threads
613system.cpu.int_regfile_reads 1091825743 # number of integer regfile reads
614system.cpu.int_regfile_writes 655727641 # number of integer regfile writes
615system.cpu.fp_regfile_reads 182 # number of floating regfile reads
616system.cpu.cc_regfile_reads 416065488 # number of cc regfile reads
617system.cpu.cc_regfile_writes 321934300 # number of cc regfile writes
618system.cpu.misc_regfile_reads 265346710 # number of misc regfile reads
619system.cpu.misc_regfile_writes 399949 # number of misc regfile writes
620system.cpu.dcache.tags.replacements 1659310 # number of replacements
621system.cpu.dcache.tags.tagsinuse 511.993990 # Cycle average of tags in use
622system.cpu.dcache.tags.total_refs 19061899 # Total number of references to valid blocks.
623system.cpu.dcache.tags.sampled_refs 1659822 # Sample count of references to valid blocks.
624system.cpu.dcache.tags.avg_refs 11.484303 # Average number of references to valid blocks.
625system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit.
626system.cpu.dcache.tags.occ_blocks::cpu.data 511.993990 # Average occupied blocks per requestor
627system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy
628system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy
629system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
630system.cpu.dcache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
631system.cpu.dcache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id
632system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
633system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
634system.cpu.dcache.tags.tag_accesses 88087332 # Number of tag accesses
635system.cpu.dcache.tags.data_accesses 88087332 # Number of data accesses
636system.cpu.dcache.ReadReq_hits::cpu.data 10917280 # number of ReadReq hits
637system.cpu.dcache.ReadReq_hits::total 10917280 # number of ReadReq hits
638system.cpu.dcache.WriteReq_hits::cpu.data 8077307 # number of WriteReq hits
639system.cpu.dcache.WriteReq_hits::total 8077307 # number of WriteReq hits
640system.cpu.dcache.SoftPFReq_hits::cpu.data 64579 # number of SoftPFReq hits
641system.cpu.dcache.SoftPFReq_hits::total 64579 # number of SoftPFReq hits
642system.cpu.dcache.demand_hits::cpu.data 18994587 # number of demand (read+write) hits
643system.cpu.dcache.demand_hits::total 18994587 # number of demand (read+write) hits
644system.cpu.dcache.overall_hits::cpu.data 19059166 # number of overall hits
645system.cpu.dcache.overall_hits::total 19059166 # number of overall hits
646system.cpu.dcache.ReadReq_misses::cpu.data 1807757 # number of ReadReq misses
647system.cpu.dcache.ReadReq_misses::total 1807757 # number of ReadReq misses
648system.cpu.dcache.WriteReq_misses::cpu.data 333541 # number of WriteReq misses
649system.cpu.dcache.WriteReq_misses::total 333541 # number of WriteReq misses
650system.cpu.dcache.SoftPFReq_misses::cpu.data 406408 # number of SoftPFReq misses
651system.cpu.dcache.SoftPFReq_misses::total 406408 # number of SoftPFReq misses
652system.cpu.dcache.demand_misses::cpu.data 2141298 # number of demand (read+write) misses
653system.cpu.dcache.demand_misses::total 2141298 # number of demand (read+write) misses
654system.cpu.dcache.overall_misses::cpu.data 2547706 # number of overall misses
655system.cpu.dcache.overall_misses::total 2547706 # number of overall misses
656system.cpu.dcache.ReadReq_miss_latency::cpu.data 27202744445 # number of ReadReq miss cycles
657system.cpu.dcache.ReadReq_miss_latency::total 27202744445 # number of ReadReq miss cycles
658system.cpu.dcache.WriteReq_miss_latency::cpu.data 13955718277 # number of WriteReq miss cycles
659system.cpu.dcache.WriteReq_miss_latency::total 13955718277 # number of WriteReq miss cycles
660system.cpu.dcache.demand_miss_latency::cpu.data 41158462722 # number of demand (read+write) miss cycles
661system.cpu.dcache.demand_miss_latency::total 41158462722 # number of demand (read+write) miss cycles
662system.cpu.dcache.overall_miss_latency::cpu.data 41158462722 # number of overall miss cycles
663system.cpu.dcache.overall_miss_latency::total 41158462722 # number of overall miss cycles
664system.cpu.dcache.ReadReq_accesses::cpu.data 12725037 # number of ReadReq accesses(hits+misses)
665system.cpu.dcache.ReadReq_accesses::total 12725037 # number of ReadReq accesses(hits+misses)
666system.cpu.dcache.WriteReq_accesses::cpu.data 8410848 # number of WriteReq accesses(hits+misses)
667system.cpu.dcache.WriteReq_accesses::total 8410848 # number of WriteReq accesses(hits+misses)
668system.cpu.dcache.SoftPFReq_accesses::cpu.data 470987 # number of SoftPFReq accesses(hits+misses)
669system.cpu.dcache.SoftPFReq_accesses::total 470987 # number of SoftPFReq accesses(hits+misses)
670system.cpu.dcache.demand_accesses::cpu.data 21135885 # number of demand (read+write) accesses
671system.cpu.dcache.demand_accesses::total 21135885 # number of demand (read+write) accesses
672system.cpu.dcache.overall_accesses::cpu.data 21606872 # number of overall (read+write) accesses
673system.cpu.dcache.overall_accesses::total 21606872 # number of overall (read+write) accesses
674system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142063 # miss rate for ReadReq accesses
675system.cpu.dcache.ReadReq_miss_rate::total 0.142063 # miss rate for ReadReq accesses
676system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039656 # miss rate for WriteReq accesses
677system.cpu.dcache.WriteReq_miss_rate::total 0.039656 # miss rate for WriteReq accesses
678system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862886 # miss rate for SoftPFReq accesses
679system.cpu.dcache.SoftPFReq_miss_rate::total 0.862886 # miss rate for SoftPFReq accesses
680system.cpu.dcache.demand_miss_rate::cpu.data 0.101311 # miss rate for demand accesses
681system.cpu.dcache.demand_miss_rate::total 0.101311 # miss rate for demand accesses
682system.cpu.dcache.overall_miss_rate::cpu.data 0.117912 # miss rate for overall accesses
683system.cpu.dcache.overall_miss_rate::total 0.117912 # miss rate for overall accesses
684system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15047.788196 # average ReadReq miss latency
685system.cpu.dcache.ReadReq_avg_miss_latency::total 15047.788196 # average ReadReq miss latency
686system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41841.087833 # average WriteReq miss latency
687system.cpu.dcache.WriteReq_avg_miss_latency::total 41841.087833 # average WriteReq miss latency
688system.cpu.dcache.demand_avg_miss_latency::cpu.data 19221.267998 # average overall miss latency
689system.cpu.dcache.demand_avg_miss_latency::total 19221.267998 # average overall miss latency
690system.cpu.dcache.overall_avg_miss_latency::cpu.data 16155.106877 # average overall miss latency
691system.cpu.dcache.overall_avg_miss_latency::total 16155.106877 # average overall miss latency
692system.cpu.dcache.blocked_cycles::no_mshrs 414660 # number of cycles access was blocked
693system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
694system.cpu.dcache.blocked::no_mshrs 43514 # number of cycles access was blocked
695system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
696system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.529347 # average number of cycles each access was blocked
697system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
698system.cpu.dcache.fast_writes 0 # number of fast writes performed
699system.cpu.dcache.cache_copies 0 # number of cache copies performed
700system.cpu.dcache.writebacks::writebacks 1560749 # number of writebacks
701system.cpu.dcache.writebacks::total 1560749 # number of writebacks
702system.cpu.dcache.ReadReq_mshr_hits::cpu.data 839489 # number of ReadReq MSHR hits
703system.cpu.dcache.ReadReq_mshr_hits::total 839489 # number of ReadReq MSHR hits
704system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42702 # number of WriteReq MSHR hits
705system.cpu.dcache.WriteReq_mshr_hits::total 42702 # number of WriteReq MSHR hits
706system.cpu.dcache.demand_mshr_hits::cpu.data 882191 # number of demand (read+write) MSHR hits
707system.cpu.dcache.demand_mshr_hits::total 882191 # number of demand (read+write) MSHR hits
708system.cpu.dcache.overall_mshr_hits::cpu.data 882191 # number of overall MSHR hits
709system.cpu.dcache.overall_mshr_hits::total 882191 # number of overall MSHR hits
710system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968268 # number of ReadReq MSHR misses
711system.cpu.dcache.ReadReq_mshr_misses::total 968268 # number of ReadReq MSHR misses
712system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290839 # number of WriteReq MSHR misses
713system.cpu.dcache.WriteReq_mshr_misses::total 290839 # number of WriteReq MSHR misses
714system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402958 # number of SoftPFReq MSHR misses
715system.cpu.dcache.SoftPFReq_mshr_misses::total 402958 # number of SoftPFReq MSHR misses
716system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 # number of demand (read+write) MSHR misses
717system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses
718system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses
719system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses

720system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable
721system.cpu.dcache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable
722system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable
723system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
724system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
725system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses

720system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles
721system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles
722system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles
723system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles
724system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles
725system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles
726system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles
727system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles
728system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31139357841 # number of overall MSHR miss cycles
729system.cpu.dcache.overall_mshr_miss_latency::total 31139357841 # number of overall MSHR miss cycles
730system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97454292000 # number of ReadReq MSHR uncacheable cycles
731system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97454292000 # number of ReadReq MSHR uncacheable cycles
732system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593348000 # number of WriteReq MSHR uncacheable cycles
733system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593348000 # number of WriteReq MSHR uncacheable cycles
734system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100047640000 # number of overall MSHR uncacheable cycles
735system.cpu.dcache.overall_mshr_uncacheable_latency::total 100047640000 # number of overall MSHR uncacheable cycles
736system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076092 # mshr miss rate for ReadReq accesses
737system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076092 # mshr miss rate for ReadReq accesses
738system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034579 # mshr miss rate for WriteReq accesses
739system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034579 # mshr miss rate for WriteReq accesses
740system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855561 # mshr miss rate for SoftPFReq accesses
741system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855561 # mshr miss rate for SoftPFReq accesses
742system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059572 # mshr miss rate for demand accesses
743system.cpu.dcache.demand_mshr_miss_rate::total 0.059572 # mshr miss rate for demand accesses
744system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for overall accesses
745system.cpu.dcache.overall_mshr_miss_rate::total 0.076923 # mshr miss rate for overall accesses
746system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13255.078933 # average ReadReq mshr miss latency
747system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13255.078933 # average ReadReq mshr miss latency
748system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency
749system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency
750system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency
751system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency
752system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency
753system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency
754system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency
755system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency

726system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles
727system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles
728system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles
729system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles
730system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles
731system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles
732system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles
733system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles
734system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31139357841 # number of overall MSHR miss cycles
735system.cpu.dcache.overall_mshr_miss_latency::total 31139357841 # number of overall MSHR miss cycles
736system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97454292000 # number of ReadReq MSHR uncacheable cycles
737system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97454292000 # number of ReadReq MSHR uncacheable cycles
738system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593348000 # number of WriteReq MSHR uncacheable cycles
739system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593348000 # number of WriteReq MSHR uncacheable cycles
740system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100047640000 # number of overall MSHR uncacheable cycles
741system.cpu.dcache.overall_mshr_uncacheable_latency::total 100047640000 # number of overall MSHR uncacheable cycles
742system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076092 # mshr miss rate for ReadReq accesses
743system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076092 # mshr miss rate for ReadReq accesses
744system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034579 # mshr miss rate for WriteReq accesses
745system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034579 # mshr miss rate for WriteReq accesses
746system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855561 # mshr miss rate for SoftPFReq accesses
747system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855561 # mshr miss rate for SoftPFReq accesses
748system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059572 # mshr miss rate for demand accesses
749system.cpu.dcache.demand_mshr_miss_rate::total 0.059572 # mshr miss rate for demand accesses
750system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for overall accesses
751system.cpu.dcache.overall_mshr_miss_rate::total 0.076923 # mshr miss rate for overall accesses
752system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13255.078933 # average ReadReq mshr miss latency
753system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13255.078933 # average ReadReq mshr miss latency
754system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency
755system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency
756system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency
757system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency
758system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency
759system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency
760system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency
761system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency

756system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
757system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
758system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
759system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
760system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
761system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

762system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604 # average ReadReq mshr uncacheable latency
763system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency
764system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483 # average WriteReq mshr uncacheable latency
765system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency
766system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590 # average overall mshr uncacheable latency
767system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency

762system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
763system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements
764system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use
765system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks.
766system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks.
767system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks.
768system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit.
769system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor
770system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.828986 # Average percentage of cache occupancy
771system.cpu.dtb_walker_cache.tags.occ_percent::total 0.828986 # Average percentage of cache occupancy
772system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
773system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
774system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
775system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
776system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
777system.cpu.dtb_walker_cache.tags.tag_accesses 446439 # Number of tag accesses
778system.cpu.dtb_walker_cache.tags.data_accesses 446439 # Number of data accesses
779system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 104946 # number of ReadReq hits
780system.cpu.dtb_walker_cache.ReadReq_hits::total 104946 # number of ReadReq hits
781system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 104946 # number of demand (read+write) hits
782system.cpu.dtb_walker_cache.demand_hits::total 104946 # number of demand (read+write) hits
783system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 104946 # number of overall hits
784system.cpu.dtb_walker_cache.overall_hits::total 104946 # number of overall hits
785system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 78849 # number of ReadReq misses
786system.cpu.dtb_walker_cache.ReadReq_misses::total 78849 # number of ReadReq misses
787system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 78849 # number of demand (read+write) misses
788system.cpu.dtb_walker_cache.demand_misses::total 78849 # number of demand (read+write) misses
789system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 78849 # number of overall misses
790system.cpu.dtb_walker_cache.overall_misses::total 78849 # number of overall misses
791system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 941548961 # number of ReadReq miss cycles
792system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 941548961 # number of ReadReq miss cycles
793system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 941548961 # number of demand (read+write) miss cycles
794system.cpu.dtb_walker_cache.demand_miss_latency::total 941548961 # number of demand (read+write) miss cycles
795system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 941548961 # number of overall miss cycles
796system.cpu.dtb_walker_cache.overall_miss_latency::total 941548961 # number of overall miss cycles
797system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 183795 # number of ReadReq accesses(hits+misses)
798system.cpu.dtb_walker_cache.ReadReq_accesses::total 183795 # number of ReadReq accesses(hits+misses)
799system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 183795 # number of demand (read+write) accesses
800system.cpu.dtb_walker_cache.demand_accesses::total 183795 # number of demand (read+write) accesses
801system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 183795 # number of overall (read+write) accesses
802system.cpu.dtb_walker_cache.overall_accesses::total 183795 # number of overall (read+write) accesses
803system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429005 # miss rate for ReadReq accesses
804system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429005 # miss rate for ReadReq accesses
805system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429005 # miss rate for demand accesses
806system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429005 # miss rate for demand accesses
807system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429005 # miss rate for overall accesses
808system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429005 # miss rate for overall accesses
809system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11941.165532 # average ReadReq miss latency
810system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11941.165532 # average ReadReq miss latency
811system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
812system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11941.165532 # average overall miss latency
813system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
814system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11941.165532 # average overall miss latency
815system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
816system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
817system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
818system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
819system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
820system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
821system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
822system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
823system.cpu.dtb_walker_cache.writebacks::writebacks 22745 # number of writebacks
824system.cpu.dtb_walker_cache.writebacks::total 22745 # number of writebacks
825system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 78849 # number of ReadReq MSHR misses
826system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 78849 # number of ReadReq MSHR misses
827system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 78849 # number of demand (read+write) MSHR misses
828system.cpu.dtb_walker_cache.demand_mshr_misses::total 78849 # number of demand (read+write) MSHR misses
829system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 78849 # number of overall MSHR misses
830system.cpu.dtb_walker_cache.overall_mshr_misses::total 78849 # number of overall MSHR misses
831system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 823159683 # number of ReadReq MSHR miss cycles
832system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 823159683 # number of ReadReq MSHR miss cycles
833system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 823159683 # number of demand (read+write) MSHR miss cycles
834system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 823159683 # number of demand (read+write) MSHR miss cycles
835system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 823159683 # number of overall MSHR miss cycles
836system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 823159683 # number of overall MSHR miss cycles
837system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for ReadReq accesses
838system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429005 # mshr miss rate for ReadReq accesses
839system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for demand accesses
840system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429005 # mshr miss rate for demand accesses
841system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for overall accesses
842system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429005 # mshr miss rate for overall accesses
843system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average ReadReq mshr miss latency
844system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10439.697181 # average ReadReq mshr miss latency
845system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
846system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
847system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
848system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
849system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
850system.cpu.icache.tags.replacements 996925 # number of replacements
851system.cpu.icache.tags.tagsinuse 509.357790 # Cycle average of tags in use
852system.cpu.icache.tags.total_refs 8050243 # Total number of references to valid blocks.
853system.cpu.icache.tags.sampled_refs 997437 # Sample count of references to valid blocks.
854system.cpu.icache.tags.avg_refs 8.070929 # Average number of references to valid blocks.
855system.cpu.icache.tags.warmup_cycle 148006664250 # Cycle when the warmup percentage was hit.
856system.cpu.icache.tags.occ_blocks::cpu.inst 509.357790 # Average occupied blocks per requestor
857system.cpu.icache.tags.occ_percent::cpu.inst 0.994839 # Average percentage of cache occupancy
858system.cpu.icache.tags.occ_percent::total 0.994839 # Average percentage of cache occupancy
859system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
860system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
861system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
862system.cpu.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id
863system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
864system.cpu.icache.tags.tag_accesses 10113779 # Number of tag accesses
865system.cpu.icache.tags.data_accesses 10113779 # Number of data accesses
866system.cpu.icache.ReadReq_hits::cpu.inst 8050243 # number of ReadReq hits
867system.cpu.icache.ReadReq_hits::total 8050243 # number of ReadReq hits
868system.cpu.icache.demand_hits::cpu.inst 8050243 # number of demand (read+write) hits
869system.cpu.icache.demand_hits::total 8050243 # number of demand (read+write) hits
870system.cpu.icache.overall_hits::cpu.inst 8050243 # number of overall hits
871system.cpu.icache.overall_hits::total 8050243 # number of overall hits
872system.cpu.icache.ReadReq_misses::cpu.inst 1066046 # number of ReadReq misses
873system.cpu.icache.ReadReq_misses::total 1066046 # number of ReadReq misses
874system.cpu.icache.demand_misses::cpu.inst 1066046 # number of demand (read+write) misses
875system.cpu.icache.demand_misses::total 1066046 # number of demand (read+write) misses
876system.cpu.icache.overall_misses::cpu.inst 1066046 # number of overall misses
877system.cpu.icache.overall_misses::total 1066046 # number of overall misses
878system.cpu.icache.ReadReq_miss_latency::cpu.inst 14875004411 # number of ReadReq miss cycles
879system.cpu.icache.ReadReq_miss_latency::total 14875004411 # number of ReadReq miss cycles
880system.cpu.icache.demand_miss_latency::cpu.inst 14875004411 # number of demand (read+write) miss cycles
881system.cpu.icache.demand_miss_latency::total 14875004411 # number of demand (read+write) miss cycles
882system.cpu.icache.overall_miss_latency::cpu.inst 14875004411 # number of overall miss cycles
883system.cpu.icache.overall_miss_latency::total 14875004411 # number of overall miss cycles
884system.cpu.icache.ReadReq_accesses::cpu.inst 9116289 # number of ReadReq accesses(hits+misses)
885system.cpu.icache.ReadReq_accesses::total 9116289 # number of ReadReq accesses(hits+misses)
886system.cpu.icache.demand_accesses::cpu.inst 9116289 # number of demand (read+write) accesses
887system.cpu.icache.demand_accesses::total 9116289 # number of demand (read+write) accesses
888system.cpu.icache.overall_accesses::cpu.inst 9116289 # number of overall (read+write) accesses
889system.cpu.icache.overall_accesses::total 9116289 # number of overall (read+write) accesses
890system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116939 # miss rate for ReadReq accesses
891system.cpu.icache.ReadReq_miss_rate::total 0.116939 # miss rate for ReadReq accesses
892system.cpu.icache.demand_miss_rate::cpu.inst 0.116939 # miss rate for demand accesses
893system.cpu.icache.demand_miss_rate::total 0.116939 # miss rate for demand accesses
894system.cpu.icache.overall_miss_rate::cpu.inst 0.116939 # miss rate for overall accesses
895system.cpu.icache.overall_miss_rate::total 0.116939 # miss rate for overall accesses
896system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13953.435791 # average ReadReq miss latency
897system.cpu.icache.ReadReq_avg_miss_latency::total 13953.435791 # average ReadReq miss latency
898system.cpu.icache.demand_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
899system.cpu.icache.demand_avg_miss_latency::total 13953.435791 # average overall miss latency
900system.cpu.icache.overall_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
901system.cpu.icache.overall_avg_miss_latency::total 13953.435791 # average overall miss latency
902system.cpu.icache.blocked_cycles::no_mshrs 7127 # number of cycles access was blocked
903system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
904system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked
905system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
906system.cpu.icache.avg_blocked_cycles::no_mshrs 20.900293 # average number of cycles each access was blocked
907system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
908system.cpu.icache.fast_writes 0 # number of fast writes performed
909system.cpu.icache.cache_copies 0 # number of cache copies performed
910system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68556 # number of ReadReq MSHR hits
911system.cpu.icache.ReadReq_mshr_hits::total 68556 # number of ReadReq MSHR hits
912system.cpu.icache.demand_mshr_hits::cpu.inst 68556 # number of demand (read+write) MSHR hits
913system.cpu.icache.demand_mshr_hits::total 68556 # number of demand (read+write) MSHR hits
914system.cpu.icache.overall_mshr_hits::cpu.inst 68556 # number of overall MSHR hits
915system.cpu.icache.overall_mshr_hits::total 68556 # number of overall MSHR hits
916system.cpu.icache.ReadReq_mshr_misses::cpu.inst 997490 # number of ReadReq MSHR misses
917system.cpu.icache.ReadReq_mshr_misses::total 997490 # number of ReadReq MSHR misses
918system.cpu.icache.demand_mshr_misses::cpu.inst 997490 # number of demand (read+write) MSHR misses
919system.cpu.icache.demand_mshr_misses::total 997490 # number of demand (read+write) MSHR misses
920system.cpu.icache.overall_mshr_misses::cpu.inst 997490 # number of overall MSHR misses
921system.cpu.icache.overall_mshr_misses::total 997490 # number of overall MSHR misses
922system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12688553873 # number of ReadReq MSHR miss cycles
923system.cpu.icache.ReadReq_mshr_miss_latency::total 12688553873 # number of ReadReq MSHR miss cycles
924system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12688553873 # number of demand (read+write) MSHR miss cycles
925system.cpu.icache.demand_mshr_miss_latency::total 12688553873 # number of demand (read+write) MSHR miss cycles
926system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12688553873 # number of overall MSHR miss cycles
927system.cpu.icache.overall_mshr_miss_latency::total 12688553873 # number of overall MSHR miss cycles
928system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for ReadReq accesses
929system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109418 # mshr miss rate for ReadReq accesses
930system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for demand accesses
931system.cpu.icache.demand_mshr_miss_rate::total 0.109418 # mshr miss rate for demand accesses
932system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for overall accesses
933system.cpu.icache.overall_mshr_miss_rate::total 0.109418 # mshr miss rate for overall accesses
934system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12720.482284 # average ReadReq mshr miss latency
935system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12720.482284 # average ReadReq mshr miss latency
936system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
937system.cpu.icache.demand_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
938system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
939system.cpu.icache.overall_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
940system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
941system.cpu.itb_walker_cache.tags.replacements 13512 # number of replacements
942system.cpu.itb_walker_cache.tags.tagsinuse 6.614352 # Cycle average of tags in use
943system.cpu.itb_walker_cache.tags.total_refs 26763 # Total number of references to valid blocks.
944system.cpu.itb_walker_cache.tags.sampled_refs 13525 # Sample count of references to valid blocks.
945system.cpu.itb_walker_cache.tags.avg_refs 1.978780 # Average number of references to valid blocks.
946system.cpu.itb_walker_cache.tags.warmup_cycle 5101180103500 # Cycle when the warmup percentage was hit.
947system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.614352 # Average occupied blocks per requestor
948system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.413397 # Average percentage of cache occupancy
949system.cpu.itb_walker_cache.tags.occ_percent::total 0.413397 # Average percentage of cache occupancy
950system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
951system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
952system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
953system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
954system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
955system.cpu.itb_walker_cache.tags.tag_accesses 96721 # Number of tag accesses
956system.cpu.itb_walker_cache.tags.data_accesses 96721 # Number of data accesses
957system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26775 # number of ReadReq hits
958system.cpu.itb_walker_cache.ReadReq_hits::total 26775 # number of ReadReq hits
959system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
960system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
961system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26777 # number of demand (read+write) hits
962system.cpu.itb_walker_cache.demand_hits::total 26777 # number of demand (read+write) hits
963system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26777 # number of overall hits
964system.cpu.itb_walker_cache.overall_hits::total 26777 # number of overall hits
965system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14389 # number of ReadReq misses
966system.cpu.itb_walker_cache.ReadReq_misses::total 14389 # number of ReadReq misses
967system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14389 # number of demand (read+write) misses
968system.cpu.itb_walker_cache.demand_misses::total 14389 # number of demand (read+write) misses
969system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14389 # number of overall misses
970system.cpu.itb_walker_cache.overall_misses::total 14389 # number of overall misses
971system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168738994 # number of ReadReq miss cycles
972system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168738994 # number of ReadReq miss cycles
973system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168738994 # number of demand (read+write) miss cycles
974system.cpu.itb_walker_cache.demand_miss_latency::total 168738994 # number of demand (read+write) miss cycles
975system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168738994 # number of overall miss cycles
976system.cpu.itb_walker_cache.overall_miss_latency::total 168738994 # number of overall miss cycles
977system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41164 # number of ReadReq accesses(hits+misses)
978system.cpu.itb_walker_cache.ReadReq_accesses::total 41164 # number of ReadReq accesses(hits+misses)
979system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
980system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
981system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41166 # number of demand (read+write) accesses
982system.cpu.itb_walker_cache.demand_accesses::total 41166 # number of demand (read+write) accesses
983system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41166 # number of overall (read+write) accesses
984system.cpu.itb_walker_cache.overall_accesses::total 41166 # number of overall (read+write) accesses
985system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349553 # miss rate for ReadReq accesses
986system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349553 # miss rate for ReadReq accesses
987system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349536 # miss rate for demand accesses
988system.cpu.itb_walker_cache.demand_miss_rate::total 0.349536 # miss rate for demand accesses
989system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349536 # miss rate for overall accesses
990system.cpu.itb_walker_cache.overall_miss_rate::total 0.349536 # miss rate for overall accesses
991system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11726.943776 # average ReadReq miss latency
992system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11726.943776 # average ReadReq miss latency
993system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
994system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11726.943776 # average overall miss latency
995system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
996system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11726.943776 # average overall miss latency
997system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
998system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
999system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1000system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1001system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1002system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1003system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1004system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1005system.cpu.itb_walker_cache.writebacks::writebacks 3066 # number of writebacks
1006system.cpu.itb_walker_cache.writebacks::total 3066 # number of writebacks
1007system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14389 # number of ReadReq MSHR misses
1008system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14389 # number of ReadReq MSHR misses
1009system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14389 # number of demand (read+write) MSHR misses
1010system.cpu.itb_walker_cache.demand_mshr_misses::total 14389 # number of demand (read+write) MSHR misses
1011system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14389 # number of overall MSHR misses
1012system.cpu.itb_walker_cache.overall_mshr_misses::total 14389 # number of overall MSHR misses
1013system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147144512 # number of ReadReq MSHR miss cycles
1014system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147144512 # number of ReadReq MSHR miss cycles
1015system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147144512 # number of demand (read+write) MSHR miss cycles
1016system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147144512 # number of demand (read+write) MSHR miss cycles
1017system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147144512 # number of overall MSHR miss cycles
1018system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147144512 # number of overall MSHR miss cycles
1019system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.349553 # mshr miss rate for ReadReq accesses
1020system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.349553 # mshr miss rate for ReadReq accesses
1021system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for demand accesses
1022system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.349536 # mshr miss rate for demand accesses
1023system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for overall accesses
1024system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.349536 # mshr miss rate for overall accesses
1025system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average ReadReq mshr miss latency
1026system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10226.180555 # average ReadReq mshr miss latency
1027system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
1028system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
1029system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
1030system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
1031system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1032system.cpu.l2cache.tags.replacements 112729 # number of replacements
1033system.cpu.l2cache.tags.tagsinuse 64831.922119 # Cycle average of tags in use
1034system.cpu.l2cache.tags.total_refs 3833002 # Total number of references to valid blocks.
1035system.cpu.l2cache.tags.sampled_refs 176853 # Sample count of references to valid blocks.
1036system.cpu.l2cache.tags.avg_refs 21.673378 # Average number of references to valid blocks.
1037system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1038system.cpu.l2cache.tags.occ_blocks::writebacks 50534.450143 # Average occupied blocks per requestor
1039system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.577905 # Average occupied blocks per requestor
1040system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.126849 # Average occupied blocks per requestor
1041system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.817202 # Average occupied blocks per requestor
1042system.cpu.l2cache.tags.occ_blocks::cpu.data 11175.950019 # Average occupied blocks per requestor
1043system.cpu.l2cache.tags.occ_percent::writebacks 0.771095 # Average percentage of cache occupancy
1044system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000222 # Average percentage of cache occupancy
1045system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy
1046system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047391 # Average percentage of cache occupancy
1047system.cpu.l2cache.tags.occ_percent::cpu.data 0.170531 # Average percentage of cache occupancy
1048system.cpu.l2cache.tags.occ_percent::total 0.989257 # Average percentage of cache occupancy
1049system.cpu.l2cache.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id
1050system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
1051system.cpu.l2cache.tags.age_task_id_blocks_1024::1 694 # Occupied blocks per task id
1052system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3262 # Occupied blocks per task id
1053system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7383 # Occupied blocks per task id
1054system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id
1055system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id
1056system.cpu.l2cache.tags.tag_accesses 35081373 # Number of tag accesses
1057system.cpu.l2cache.tags.data_accesses 35081373 # Number of data accesses
1058system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68578 # number of ReadReq hits
1059system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12140 # number of ReadReq hits
1060system.cpu.l2cache.ReadReq_hits::cpu.inst 981027 # number of ReadReq hits
1061system.cpu.l2cache.ReadReq_hits::cpu.data 1334830 # number of ReadReq hits
1062system.cpu.l2cache.ReadReq_hits::total 2396575 # number of ReadReq hits
1063system.cpu.l2cache.Writeback_hits::writebacks 1586560 # number of Writeback hits
1064system.cpu.l2cache.Writeback_hits::total 1586560 # number of Writeback hits
1065system.cpu.l2cache.UpgradeReq_hits::cpu.data 310 # number of UpgradeReq hits
1066system.cpu.l2cache.UpgradeReq_hits::total 310 # number of UpgradeReq hits
1067system.cpu.l2cache.ReadExReq_hits::cpu.data 154702 # number of ReadExReq hits
1068system.cpu.l2cache.ReadExReq_hits::total 154702 # number of ReadExReq hits
1069system.cpu.l2cache.demand_hits::cpu.dtb.walker 68578 # number of demand (read+write) hits
1070system.cpu.l2cache.demand_hits::cpu.itb.walker 12140 # number of demand (read+write) hits
1071system.cpu.l2cache.demand_hits::cpu.inst 981027 # number of demand (read+write) hits
1072system.cpu.l2cache.demand_hits::cpu.data 1489532 # number of demand (read+write) hits
1073system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits
1074system.cpu.l2cache.overall_hits::cpu.dtb.walker 68578 # number of overall hits
1075system.cpu.l2cache.overall_hits::cpu.itb.walker 12140 # number of overall hits
1076system.cpu.l2cache.overall_hits::cpu.inst 981027 # number of overall hits
1077system.cpu.l2cache.overall_hits::cpu.data 1489532 # number of overall hits
1078system.cpu.l2cache.overall_hits::total 2551277 # number of overall hits
1079system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses
1080system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
1081system.cpu.l2cache.ReadReq_misses::cpu.inst 16363 # number of ReadReq misses
1082system.cpu.l2cache.ReadReq_misses::cpu.data 35684 # number of ReadReq misses
1083system.cpu.l2cache.ReadReq_misses::total 52120 # number of ReadReq misses
1084system.cpu.l2cache.UpgradeReq_misses::cpu.data 1439 # number of UpgradeReq misses
1085system.cpu.l2cache.UpgradeReq_misses::total 1439 # number of UpgradeReq misses
1086system.cpu.l2cache.ReadExReq_misses::cpu.data 134046 # number of ReadExReq misses
1087system.cpu.l2cache.ReadExReq_misses::total 134046 # number of ReadExReq misses
1088system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses
1089system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1090system.cpu.l2cache.demand_misses::cpu.inst 16363 # number of demand (read+write) misses
1091system.cpu.l2cache.demand_misses::cpu.data 169730 # number of demand (read+write) misses
1092system.cpu.l2cache.demand_misses::total 186166 # number of demand (read+write) misses
1093system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses
1094system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1095system.cpu.l2cache.overall_misses::cpu.inst 16363 # number of overall misses
1096system.cpu.l2cache.overall_misses::cpu.data 169730 # number of overall misses
1097system.cpu.l2cache.overall_misses::total 186166 # number of overall misses
1098system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6097000 # number of ReadReq miss cycles
1099system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 666500 # number of ReadReq miss cycles
1100system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1366410532 # number of ReadReq miss cycles
1101system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3072121000 # number of ReadReq miss cycles
1102system.cpu.l2cache.ReadReq_miss_latency::total 4445295032 # number of ReadReq miss cycles
1103system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22717321 # number of UpgradeReq miss cycles
1104system.cpu.l2cache.UpgradeReq_miss_latency::total 22717321 # number of UpgradeReq miss cycles
1105system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10374564266 # number of ReadExReq miss cycles
1106system.cpu.l2cache.ReadExReq_miss_latency::total 10374564266 # number of ReadExReq miss cycles
1107system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6097000 # number of demand (read+write) miss cycles
1108system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 666500 # number of demand (read+write) miss cycles
1109system.cpu.l2cache.demand_miss_latency::cpu.inst 1366410532 # number of demand (read+write) miss cycles
1110system.cpu.l2cache.demand_miss_latency::cpu.data 13446685266 # number of demand (read+write) miss cycles
1111system.cpu.l2cache.demand_miss_latency::total 14819859298 # number of demand (read+write) miss cycles
1112system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6097000 # number of overall miss cycles
1113system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 666500 # number of overall miss cycles
1114system.cpu.l2cache.overall_miss_latency::cpu.inst 1366410532 # number of overall miss cycles
1115system.cpu.l2cache.overall_miss_latency::cpu.data 13446685266 # number of overall miss cycles
1116system.cpu.l2cache.overall_miss_latency::total 14819859298 # number of overall miss cycles
1117system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68644 # number of ReadReq accesses(hits+misses)
1118system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12147 # number of ReadReq accesses(hits+misses)
1119system.cpu.l2cache.ReadReq_accesses::cpu.inst 997390 # number of ReadReq accesses(hits+misses)
1120system.cpu.l2cache.ReadReq_accesses::cpu.data 1370514 # number of ReadReq accesses(hits+misses)
1121system.cpu.l2cache.ReadReq_accesses::total 2448695 # number of ReadReq accesses(hits+misses)
1122system.cpu.l2cache.Writeback_accesses::writebacks 1586560 # number of Writeback accesses(hits+misses)
1123system.cpu.l2cache.Writeback_accesses::total 1586560 # number of Writeback accesses(hits+misses)
1124system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1749 # number of UpgradeReq accesses(hits+misses)
1125system.cpu.l2cache.UpgradeReq_accesses::total 1749 # number of UpgradeReq accesses(hits+misses)
1126system.cpu.l2cache.ReadExReq_accesses::cpu.data 288748 # number of ReadExReq accesses(hits+misses)
1127system.cpu.l2cache.ReadExReq_accesses::total 288748 # number of ReadExReq accesses(hits+misses)
1128system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68644 # number of demand (read+write) accesses
1129system.cpu.l2cache.demand_accesses::cpu.itb.walker 12147 # number of demand (read+write) accesses
1130system.cpu.l2cache.demand_accesses::cpu.inst 997390 # number of demand (read+write) accesses
1131system.cpu.l2cache.demand_accesses::cpu.data 1659262 # number of demand (read+write) accesses
1132system.cpu.l2cache.demand_accesses::total 2737443 # number of demand (read+write) accesses
1133system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68644 # number of overall (read+write) accesses
1134system.cpu.l2cache.overall_accesses::cpu.itb.walker 12147 # number of overall (read+write) accesses
1135system.cpu.l2cache.overall_accesses::cpu.inst 997390 # number of overall (read+write) accesses
1136system.cpu.l2cache.overall_accesses::cpu.data 1659262 # number of overall (read+write) accesses
1137system.cpu.l2cache.overall_accesses::total 2737443 # number of overall (read+write) accesses
1138system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses
1139system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000576 # miss rate for ReadReq accesses
1140system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016406 # miss rate for ReadReq accesses
1141system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026037 # miss rate for ReadReq accesses
1142system.cpu.l2cache.ReadReq_miss_rate::total 0.021285 # miss rate for ReadReq accesses
1143system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.822756 # miss rate for UpgradeReq accesses
1144system.cpu.l2cache.UpgradeReq_miss_rate::total 0.822756 # miss rate for UpgradeReq accesses
1145system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464232 # miss rate for ReadExReq accesses
1146system.cpu.l2cache.ReadExReq_miss_rate::total 0.464232 # miss rate for ReadExReq accesses
1147system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses
1148system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000576 # miss rate for demand accesses
1149system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016406 # miss rate for demand accesses
1150system.cpu.l2cache.demand_miss_rate::cpu.data 0.102292 # miss rate for demand accesses
1151system.cpu.l2cache.demand_miss_rate::total 0.068007 # miss rate for demand accesses
1152system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses
1153system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000576 # miss rate for overall accesses
1154system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016406 # miss rate for overall accesses
1155system.cpu.l2cache.overall_miss_rate::cpu.data 0.102292 # miss rate for overall accesses
1156system.cpu.l2cache.overall_miss_rate::total 0.068007 # miss rate for overall accesses
1157system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92378.787879 # average ReadReq miss latency
1158system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 95214.285714 # average ReadReq miss latency
1159system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83506.113304 # average ReadReq miss latency
1160system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86092.394350 # average ReadReq miss latency
1161system.cpu.l2cache.ReadReq_avg_miss_latency::total 85289.620721 # average ReadReq miss latency
1162system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15786.880473 # average UpgradeReq miss latency
1163system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15786.880473 # average UpgradeReq miss latency
1164system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77395.552765 # average ReadExReq miss latency
1165system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77395.552765 # average ReadExReq miss latency
1166system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
1167system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
1168system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
1169system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
1170system.cpu.l2cache.demand_avg_miss_latency::total 79605.617019 # average overall miss latency
1171system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
1172system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
1173system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
1174system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
1175system.cpu.l2cache.overall_avg_miss_latency::total 79605.617019 # average overall miss latency
1176system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1177system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1178system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1179system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1180system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1181system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1182system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1183system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1184system.cpu.l2cache.writebacks::writebacks 102850 # number of writebacks
1185system.cpu.l2cache.writebacks::total 102850 # number of writebacks
1186system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
1187system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1188system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1189system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1190system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1191system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1192system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1193system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1194system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1195system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses
1196system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
1197system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16361 # number of ReadReq MSHR misses
1198system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35683 # number of ReadReq MSHR misses
1199system.cpu.l2cache.ReadReq_mshr_misses::total 52117 # number of ReadReq MSHR misses
1200system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1439 # number of UpgradeReq MSHR misses
1201system.cpu.l2cache.UpgradeReq_mshr_misses::total 1439 # number of UpgradeReq MSHR misses
1202system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134046 # number of ReadExReq MSHR misses
1203system.cpu.l2cache.ReadExReq_mshr_misses::total 134046 # number of ReadExReq MSHR misses
1204system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses
1205system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1206system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses
1207system.cpu.l2cache.demand_mshr_misses::cpu.data 169729 # number of demand (read+write) MSHR misses
1208system.cpu.l2cache.demand_mshr_misses::total 186163 # number of demand (read+write) MSHR misses
1209system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses
1210system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1211system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses
1212system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses
1213system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses

768system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
769system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements
770system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use
771system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks.
772system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks.
773system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks.
774system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit.
775system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor
776system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.828986 # Average percentage of cache occupancy
777system.cpu.dtb_walker_cache.tags.occ_percent::total 0.828986 # Average percentage of cache occupancy
778system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
779system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
780system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
781system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
782system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
783system.cpu.dtb_walker_cache.tags.tag_accesses 446439 # Number of tag accesses
784system.cpu.dtb_walker_cache.tags.data_accesses 446439 # Number of data accesses
785system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 104946 # number of ReadReq hits
786system.cpu.dtb_walker_cache.ReadReq_hits::total 104946 # number of ReadReq hits
787system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 104946 # number of demand (read+write) hits
788system.cpu.dtb_walker_cache.demand_hits::total 104946 # number of demand (read+write) hits
789system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 104946 # number of overall hits
790system.cpu.dtb_walker_cache.overall_hits::total 104946 # number of overall hits
791system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 78849 # number of ReadReq misses
792system.cpu.dtb_walker_cache.ReadReq_misses::total 78849 # number of ReadReq misses
793system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 78849 # number of demand (read+write) misses
794system.cpu.dtb_walker_cache.demand_misses::total 78849 # number of demand (read+write) misses
795system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 78849 # number of overall misses
796system.cpu.dtb_walker_cache.overall_misses::total 78849 # number of overall misses
797system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 941548961 # number of ReadReq miss cycles
798system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 941548961 # number of ReadReq miss cycles
799system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 941548961 # number of demand (read+write) miss cycles
800system.cpu.dtb_walker_cache.demand_miss_latency::total 941548961 # number of demand (read+write) miss cycles
801system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 941548961 # number of overall miss cycles
802system.cpu.dtb_walker_cache.overall_miss_latency::total 941548961 # number of overall miss cycles
803system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 183795 # number of ReadReq accesses(hits+misses)
804system.cpu.dtb_walker_cache.ReadReq_accesses::total 183795 # number of ReadReq accesses(hits+misses)
805system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 183795 # number of demand (read+write) accesses
806system.cpu.dtb_walker_cache.demand_accesses::total 183795 # number of demand (read+write) accesses
807system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 183795 # number of overall (read+write) accesses
808system.cpu.dtb_walker_cache.overall_accesses::total 183795 # number of overall (read+write) accesses
809system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429005 # miss rate for ReadReq accesses
810system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429005 # miss rate for ReadReq accesses
811system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429005 # miss rate for demand accesses
812system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429005 # miss rate for demand accesses
813system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429005 # miss rate for overall accesses
814system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429005 # miss rate for overall accesses
815system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11941.165532 # average ReadReq miss latency
816system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11941.165532 # average ReadReq miss latency
817system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
818system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11941.165532 # average overall miss latency
819system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
820system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11941.165532 # average overall miss latency
821system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
822system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
823system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
824system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
825system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
826system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
827system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
828system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
829system.cpu.dtb_walker_cache.writebacks::writebacks 22745 # number of writebacks
830system.cpu.dtb_walker_cache.writebacks::total 22745 # number of writebacks
831system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 78849 # number of ReadReq MSHR misses
832system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 78849 # number of ReadReq MSHR misses
833system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 78849 # number of demand (read+write) MSHR misses
834system.cpu.dtb_walker_cache.demand_mshr_misses::total 78849 # number of demand (read+write) MSHR misses
835system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 78849 # number of overall MSHR misses
836system.cpu.dtb_walker_cache.overall_mshr_misses::total 78849 # number of overall MSHR misses
837system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 823159683 # number of ReadReq MSHR miss cycles
838system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 823159683 # number of ReadReq MSHR miss cycles
839system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 823159683 # number of demand (read+write) MSHR miss cycles
840system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 823159683 # number of demand (read+write) MSHR miss cycles
841system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 823159683 # number of overall MSHR miss cycles
842system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 823159683 # number of overall MSHR miss cycles
843system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for ReadReq accesses
844system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429005 # mshr miss rate for ReadReq accesses
845system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for demand accesses
846system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429005 # mshr miss rate for demand accesses
847system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for overall accesses
848system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429005 # mshr miss rate for overall accesses
849system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average ReadReq mshr miss latency
850system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10439.697181 # average ReadReq mshr miss latency
851system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
852system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
853system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
854system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
855system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
856system.cpu.icache.tags.replacements 996925 # number of replacements
857system.cpu.icache.tags.tagsinuse 509.357790 # Cycle average of tags in use
858system.cpu.icache.tags.total_refs 8050243 # Total number of references to valid blocks.
859system.cpu.icache.tags.sampled_refs 997437 # Sample count of references to valid blocks.
860system.cpu.icache.tags.avg_refs 8.070929 # Average number of references to valid blocks.
861system.cpu.icache.tags.warmup_cycle 148006664250 # Cycle when the warmup percentage was hit.
862system.cpu.icache.tags.occ_blocks::cpu.inst 509.357790 # Average occupied blocks per requestor
863system.cpu.icache.tags.occ_percent::cpu.inst 0.994839 # Average percentage of cache occupancy
864system.cpu.icache.tags.occ_percent::total 0.994839 # Average percentage of cache occupancy
865system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
866system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
867system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
868system.cpu.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id
869system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
870system.cpu.icache.tags.tag_accesses 10113779 # Number of tag accesses
871system.cpu.icache.tags.data_accesses 10113779 # Number of data accesses
872system.cpu.icache.ReadReq_hits::cpu.inst 8050243 # number of ReadReq hits
873system.cpu.icache.ReadReq_hits::total 8050243 # number of ReadReq hits
874system.cpu.icache.demand_hits::cpu.inst 8050243 # number of demand (read+write) hits
875system.cpu.icache.demand_hits::total 8050243 # number of demand (read+write) hits
876system.cpu.icache.overall_hits::cpu.inst 8050243 # number of overall hits
877system.cpu.icache.overall_hits::total 8050243 # number of overall hits
878system.cpu.icache.ReadReq_misses::cpu.inst 1066046 # number of ReadReq misses
879system.cpu.icache.ReadReq_misses::total 1066046 # number of ReadReq misses
880system.cpu.icache.demand_misses::cpu.inst 1066046 # number of demand (read+write) misses
881system.cpu.icache.demand_misses::total 1066046 # number of demand (read+write) misses
882system.cpu.icache.overall_misses::cpu.inst 1066046 # number of overall misses
883system.cpu.icache.overall_misses::total 1066046 # number of overall misses
884system.cpu.icache.ReadReq_miss_latency::cpu.inst 14875004411 # number of ReadReq miss cycles
885system.cpu.icache.ReadReq_miss_latency::total 14875004411 # number of ReadReq miss cycles
886system.cpu.icache.demand_miss_latency::cpu.inst 14875004411 # number of demand (read+write) miss cycles
887system.cpu.icache.demand_miss_latency::total 14875004411 # number of demand (read+write) miss cycles
888system.cpu.icache.overall_miss_latency::cpu.inst 14875004411 # number of overall miss cycles
889system.cpu.icache.overall_miss_latency::total 14875004411 # number of overall miss cycles
890system.cpu.icache.ReadReq_accesses::cpu.inst 9116289 # number of ReadReq accesses(hits+misses)
891system.cpu.icache.ReadReq_accesses::total 9116289 # number of ReadReq accesses(hits+misses)
892system.cpu.icache.demand_accesses::cpu.inst 9116289 # number of demand (read+write) accesses
893system.cpu.icache.demand_accesses::total 9116289 # number of demand (read+write) accesses
894system.cpu.icache.overall_accesses::cpu.inst 9116289 # number of overall (read+write) accesses
895system.cpu.icache.overall_accesses::total 9116289 # number of overall (read+write) accesses
896system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116939 # miss rate for ReadReq accesses
897system.cpu.icache.ReadReq_miss_rate::total 0.116939 # miss rate for ReadReq accesses
898system.cpu.icache.demand_miss_rate::cpu.inst 0.116939 # miss rate for demand accesses
899system.cpu.icache.demand_miss_rate::total 0.116939 # miss rate for demand accesses
900system.cpu.icache.overall_miss_rate::cpu.inst 0.116939 # miss rate for overall accesses
901system.cpu.icache.overall_miss_rate::total 0.116939 # miss rate for overall accesses
902system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13953.435791 # average ReadReq miss latency
903system.cpu.icache.ReadReq_avg_miss_latency::total 13953.435791 # average ReadReq miss latency
904system.cpu.icache.demand_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
905system.cpu.icache.demand_avg_miss_latency::total 13953.435791 # average overall miss latency
906system.cpu.icache.overall_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
907system.cpu.icache.overall_avg_miss_latency::total 13953.435791 # average overall miss latency
908system.cpu.icache.blocked_cycles::no_mshrs 7127 # number of cycles access was blocked
909system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
910system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked
911system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
912system.cpu.icache.avg_blocked_cycles::no_mshrs 20.900293 # average number of cycles each access was blocked
913system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
914system.cpu.icache.fast_writes 0 # number of fast writes performed
915system.cpu.icache.cache_copies 0 # number of cache copies performed
916system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68556 # number of ReadReq MSHR hits
917system.cpu.icache.ReadReq_mshr_hits::total 68556 # number of ReadReq MSHR hits
918system.cpu.icache.demand_mshr_hits::cpu.inst 68556 # number of demand (read+write) MSHR hits
919system.cpu.icache.demand_mshr_hits::total 68556 # number of demand (read+write) MSHR hits
920system.cpu.icache.overall_mshr_hits::cpu.inst 68556 # number of overall MSHR hits
921system.cpu.icache.overall_mshr_hits::total 68556 # number of overall MSHR hits
922system.cpu.icache.ReadReq_mshr_misses::cpu.inst 997490 # number of ReadReq MSHR misses
923system.cpu.icache.ReadReq_mshr_misses::total 997490 # number of ReadReq MSHR misses
924system.cpu.icache.demand_mshr_misses::cpu.inst 997490 # number of demand (read+write) MSHR misses
925system.cpu.icache.demand_mshr_misses::total 997490 # number of demand (read+write) MSHR misses
926system.cpu.icache.overall_mshr_misses::cpu.inst 997490 # number of overall MSHR misses
927system.cpu.icache.overall_mshr_misses::total 997490 # number of overall MSHR misses
928system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12688553873 # number of ReadReq MSHR miss cycles
929system.cpu.icache.ReadReq_mshr_miss_latency::total 12688553873 # number of ReadReq MSHR miss cycles
930system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12688553873 # number of demand (read+write) MSHR miss cycles
931system.cpu.icache.demand_mshr_miss_latency::total 12688553873 # number of demand (read+write) MSHR miss cycles
932system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12688553873 # number of overall MSHR miss cycles
933system.cpu.icache.overall_mshr_miss_latency::total 12688553873 # number of overall MSHR miss cycles
934system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for ReadReq accesses
935system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109418 # mshr miss rate for ReadReq accesses
936system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for demand accesses
937system.cpu.icache.demand_mshr_miss_rate::total 0.109418 # mshr miss rate for demand accesses
938system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for overall accesses
939system.cpu.icache.overall_mshr_miss_rate::total 0.109418 # mshr miss rate for overall accesses
940system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12720.482284 # average ReadReq mshr miss latency
941system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12720.482284 # average ReadReq mshr miss latency
942system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
943system.cpu.icache.demand_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
944system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
945system.cpu.icache.overall_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
946system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
947system.cpu.itb_walker_cache.tags.replacements 13512 # number of replacements
948system.cpu.itb_walker_cache.tags.tagsinuse 6.614352 # Cycle average of tags in use
949system.cpu.itb_walker_cache.tags.total_refs 26763 # Total number of references to valid blocks.
950system.cpu.itb_walker_cache.tags.sampled_refs 13525 # Sample count of references to valid blocks.
951system.cpu.itb_walker_cache.tags.avg_refs 1.978780 # Average number of references to valid blocks.
952system.cpu.itb_walker_cache.tags.warmup_cycle 5101180103500 # Cycle when the warmup percentage was hit.
953system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.614352 # Average occupied blocks per requestor
954system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.413397 # Average percentage of cache occupancy
955system.cpu.itb_walker_cache.tags.occ_percent::total 0.413397 # Average percentage of cache occupancy
956system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
957system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
958system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
959system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
960system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
961system.cpu.itb_walker_cache.tags.tag_accesses 96721 # Number of tag accesses
962system.cpu.itb_walker_cache.tags.data_accesses 96721 # Number of data accesses
963system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26775 # number of ReadReq hits
964system.cpu.itb_walker_cache.ReadReq_hits::total 26775 # number of ReadReq hits
965system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
966system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
967system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26777 # number of demand (read+write) hits
968system.cpu.itb_walker_cache.demand_hits::total 26777 # number of demand (read+write) hits
969system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26777 # number of overall hits
970system.cpu.itb_walker_cache.overall_hits::total 26777 # number of overall hits
971system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14389 # number of ReadReq misses
972system.cpu.itb_walker_cache.ReadReq_misses::total 14389 # number of ReadReq misses
973system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14389 # number of demand (read+write) misses
974system.cpu.itb_walker_cache.demand_misses::total 14389 # number of demand (read+write) misses
975system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14389 # number of overall misses
976system.cpu.itb_walker_cache.overall_misses::total 14389 # number of overall misses
977system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168738994 # number of ReadReq miss cycles
978system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168738994 # number of ReadReq miss cycles
979system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168738994 # number of demand (read+write) miss cycles
980system.cpu.itb_walker_cache.demand_miss_latency::total 168738994 # number of demand (read+write) miss cycles
981system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168738994 # number of overall miss cycles
982system.cpu.itb_walker_cache.overall_miss_latency::total 168738994 # number of overall miss cycles
983system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41164 # number of ReadReq accesses(hits+misses)
984system.cpu.itb_walker_cache.ReadReq_accesses::total 41164 # number of ReadReq accesses(hits+misses)
985system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
986system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
987system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41166 # number of demand (read+write) accesses
988system.cpu.itb_walker_cache.demand_accesses::total 41166 # number of demand (read+write) accesses
989system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41166 # number of overall (read+write) accesses
990system.cpu.itb_walker_cache.overall_accesses::total 41166 # number of overall (read+write) accesses
991system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349553 # miss rate for ReadReq accesses
992system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349553 # miss rate for ReadReq accesses
993system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349536 # miss rate for demand accesses
994system.cpu.itb_walker_cache.demand_miss_rate::total 0.349536 # miss rate for demand accesses
995system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349536 # miss rate for overall accesses
996system.cpu.itb_walker_cache.overall_miss_rate::total 0.349536 # miss rate for overall accesses
997system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11726.943776 # average ReadReq miss latency
998system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11726.943776 # average ReadReq miss latency
999system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
1000system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11726.943776 # average overall miss latency
1001system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
1002system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11726.943776 # average overall miss latency
1003system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1004system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1005system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1006system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1007system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1008system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1009system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1010system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1011system.cpu.itb_walker_cache.writebacks::writebacks 3066 # number of writebacks
1012system.cpu.itb_walker_cache.writebacks::total 3066 # number of writebacks
1013system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14389 # number of ReadReq MSHR misses
1014system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14389 # number of ReadReq MSHR misses
1015system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14389 # number of demand (read+write) MSHR misses
1016system.cpu.itb_walker_cache.demand_mshr_misses::total 14389 # number of demand (read+write) MSHR misses
1017system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14389 # number of overall MSHR misses
1018system.cpu.itb_walker_cache.overall_mshr_misses::total 14389 # number of overall MSHR misses
1019system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147144512 # number of ReadReq MSHR miss cycles
1020system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147144512 # number of ReadReq MSHR miss cycles
1021system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147144512 # number of demand (read+write) MSHR miss cycles
1022system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147144512 # number of demand (read+write) MSHR miss cycles
1023system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147144512 # number of overall MSHR miss cycles
1024system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147144512 # number of overall MSHR miss cycles
1025system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.349553 # mshr miss rate for ReadReq accesses
1026system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.349553 # mshr miss rate for ReadReq accesses
1027system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for demand accesses
1028system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.349536 # mshr miss rate for demand accesses
1029system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for overall accesses
1030system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.349536 # mshr miss rate for overall accesses
1031system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average ReadReq mshr miss latency
1032system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10226.180555 # average ReadReq mshr miss latency
1033system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
1034system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
1035system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
1036system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
1037system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1038system.cpu.l2cache.tags.replacements 112729 # number of replacements
1039system.cpu.l2cache.tags.tagsinuse 64831.922119 # Cycle average of tags in use
1040system.cpu.l2cache.tags.total_refs 3833002 # Total number of references to valid blocks.
1041system.cpu.l2cache.tags.sampled_refs 176853 # Sample count of references to valid blocks.
1042system.cpu.l2cache.tags.avg_refs 21.673378 # Average number of references to valid blocks.
1043system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1044system.cpu.l2cache.tags.occ_blocks::writebacks 50534.450143 # Average occupied blocks per requestor
1045system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.577905 # Average occupied blocks per requestor
1046system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.126849 # Average occupied blocks per requestor
1047system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.817202 # Average occupied blocks per requestor
1048system.cpu.l2cache.tags.occ_blocks::cpu.data 11175.950019 # Average occupied blocks per requestor
1049system.cpu.l2cache.tags.occ_percent::writebacks 0.771095 # Average percentage of cache occupancy
1050system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000222 # Average percentage of cache occupancy
1051system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy
1052system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047391 # Average percentage of cache occupancy
1053system.cpu.l2cache.tags.occ_percent::cpu.data 0.170531 # Average percentage of cache occupancy
1054system.cpu.l2cache.tags.occ_percent::total 0.989257 # Average percentage of cache occupancy
1055system.cpu.l2cache.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id
1056system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
1057system.cpu.l2cache.tags.age_task_id_blocks_1024::1 694 # Occupied blocks per task id
1058system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3262 # Occupied blocks per task id
1059system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7383 # Occupied blocks per task id
1060system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id
1061system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id
1062system.cpu.l2cache.tags.tag_accesses 35081373 # Number of tag accesses
1063system.cpu.l2cache.tags.data_accesses 35081373 # Number of data accesses
1064system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68578 # number of ReadReq hits
1065system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12140 # number of ReadReq hits
1066system.cpu.l2cache.ReadReq_hits::cpu.inst 981027 # number of ReadReq hits
1067system.cpu.l2cache.ReadReq_hits::cpu.data 1334830 # number of ReadReq hits
1068system.cpu.l2cache.ReadReq_hits::total 2396575 # number of ReadReq hits
1069system.cpu.l2cache.Writeback_hits::writebacks 1586560 # number of Writeback hits
1070system.cpu.l2cache.Writeback_hits::total 1586560 # number of Writeback hits
1071system.cpu.l2cache.UpgradeReq_hits::cpu.data 310 # number of UpgradeReq hits
1072system.cpu.l2cache.UpgradeReq_hits::total 310 # number of UpgradeReq hits
1073system.cpu.l2cache.ReadExReq_hits::cpu.data 154702 # number of ReadExReq hits
1074system.cpu.l2cache.ReadExReq_hits::total 154702 # number of ReadExReq hits
1075system.cpu.l2cache.demand_hits::cpu.dtb.walker 68578 # number of demand (read+write) hits
1076system.cpu.l2cache.demand_hits::cpu.itb.walker 12140 # number of demand (read+write) hits
1077system.cpu.l2cache.demand_hits::cpu.inst 981027 # number of demand (read+write) hits
1078system.cpu.l2cache.demand_hits::cpu.data 1489532 # number of demand (read+write) hits
1079system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits
1080system.cpu.l2cache.overall_hits::cpu.dtb.walker 68578 # number of overall hits
1081system.cpu.l2cache.overall_hits::cpu.itb.walker 12140 # number of overall hits
1082system.cpu.l2cache.overall_hits::cpu.inst 981027 # number of overall hits
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1085system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses
1086system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
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1089system.cpu.l2cache.ReadReq_misses::total 52120 # number of ReadReq misses
1090system.cpu.l2cache.UpgradeReq_misses::cpu.data 1439 # number of UpgradeReq misses
1091system.cpu.l2cache.UpgradeReq_misses::total 1439 # number of UpgradeReq misses
1092system.cpu.l2cache.ReadExReq_misses::cpu.data 134046 # number of ReadExReq misses
1093system.cpu.l2cache.ReadExReq_misses::total 134046 # number of ReadExReq misses
1094system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses
1095system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1096system.cpu.l2cache.demand_misses::cpu.inst 16363 # number of demand (read+write) misses
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1098system.cpu.l2cache.demand_misses::total 186166 # number of demand (read+write) misses
1099system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses
1100system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1101system.cpu.l2cache.overall_misses::cpu.inst 16363 # number of overall misses
1102system.cpu.l2cache.overall_misses::cpu.data 169730 # number of overall misses
1103system.cpu.l2cache.overall_misses::total 186166 # number of overall misses
1104system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6097000 # number of ReadReq miss cycles
1105system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 666500 # number of ReadReq miss cycles
1106system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1366410532 # number of ReadReq miss cycles
1107system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3072121000 # number of ReadReq miss cycles
1108system.cpu.l2cache.ReadReq_miss_latency::total 4445295032 # number of ReadReq miss cycles
1109system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22717321 # number of UpgradeReq miss cycles
1110system.cpu.l2cache.UpgradeReq_miss_latency::total 22717321 # number of UpgradeReq miss cycles
1111system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10374564266 # number of ReadExReq miss cycles
1112system.cpu.l2cache.ReadExReq_miss_latency::total 10374564266 # number of ReadExReq miss cycles
1113system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6097000 # number of demand (read+write) miss cycles
1114system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 666500 # number of demand (read+write) miss cycles
1115system.cpu.l2cache.demand_miss_latency::cpu.inst 1366410532 # number of demand (read+write) miss cycles
1116system.cpu.l2cache.demand_miss_latency::cpu.data 13446685266 # number of demand (read+write) miss cycles
1117system.cpu.l2cache.demand_miss_latency::total 14819859298 # number of demand (read+write) miss cycles
1118system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6097000 # number of overall miss cycles
1119system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 666500 # number of overall miss cycles
1120system.cpu.l2cache.overall_miss_latency::cpu.inst 1366410532 # number of overall miss cycles
1121system.cpu.l2cache.overall_miss_latency::cpu.data 13446685266 # number of overall miss cycles
1122system.cpu.l2cache.overall_miss_latency::total 14819859298 # number of overall miss cycles
1123system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68644 # number of ReadReq accesses(hits+misses)
1124system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12147 # number of ReadReq accesses(hits+misses)
1125system.cpu.l2cache.ReadReq_accesses::cpu.inst 997390 # number of ReadReq accesses(hits+misses)
1126system.cpu.l2cache.ReadReq_accesses::cpu.data 1370514 # number of ReadReq accesses(hits+misses)
1127system.cpu.l2cache.ReadReq_accesses::total 2448695 # number of ReadReq accesses(hits+misses)
1128system.cpu.l2cache.Writeback_accesses::writebacks 1586560 # number of Writeback accesses(hits+misses)
1129system.cpu.l2cache.Writeback_accesses::total 1586560 # number of Writeback accesses(hits+misses)
1130system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1749 # number of UpgradeReq accesses(hits+misses)
1131system.cpu.l2cache.UpgradeReq_accesses::total 1749 # number of UpgradeReq accesses(hits+misses)
1132system.cpu.l2cache.ReadExReq_accesses::cpu.data 288748 # number of ReadExReq accesses(hits+misses)
1133system.cpu.l2cache.ReadExReq_accesses::total 288748 # number of ReadExReq accesses(hits+misses)
1134system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68644 # number of demand (read+write) accesses
1135system.cpu.l2cache.demand_accesses::cpu.itb.walker 12147 # number of demand (read+write) accesses
1136system.cpu.l2cache.demand_accesses::cpu.inst 997390 # number of demand (read+write) accesses
1137system.cpu.l2cache.demand_accesses::cpu.data 1659262 # number of demand (read+write) accesses
1138system.cpu.l2cache.demand_accesses::total 2737443 # number of demand (read+write) accesses
1139system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68644 # number of overall (read+write) accesses
1140system.cpu.l2cache.overall_accesses::cpu.itb.walker 12147 # number of overall (read+write) accesses
1141system.cpu.l2cache.overall_accesses::cpu.inst 997390 # number of overall (read+write) accesses
1142system.cpu.l2cache.overall_accesses::cpu.data 1659262 # number of overall (read+write) accesses
1143system.cpu.l2cache.overall_accesses::total 2737443 # number of overall (read+write) accesses
1144system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses
1145system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000576 # miss rate for ReadReq accesses
1146system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016406 # miss rate for ReadReq accesses
1147system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026037 # miss rate for ReadReq accesses
1148system.cpu.l2cache.ReadReq_miss_rate::total 0.021285 # miss rate for ReadReq accesses
1149system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.822756 # miss rate for UpgradeReq accesses
1150system.cpu.l2cache.UpgradeReq_miss_rate::total 0.822756 # miss rate for UpgradeReq accesses
1151system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464232 # miss rate for ReadExReq accesses
1152system.cpu.l2cache.ReadExReq_miss_rate::total 0.464232 # miss rate for ReadExReq accesses
1153system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses
1154system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000576 # miss rate for demand accesses
1155system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016406 # miss rate for demand accesses
1156system.cpu.l2cache.demand_miss_rate::cpu.data 0.102292 # miss rate for demand accesses
1157system.cpu.l2cache.demand_miss_rate::total 0.068007 # miss rate for demand accesses
1158system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses
1159system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000576 # miss rate for overall accesses
1160system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016406 # miss rate for overall accesses
1161system.cpu.l2cache.overall_miss_rate::cpu.data 0.102292 # miss rate for overall accesses
1162system.cpu.l2cache.overall_miss_rate::total 0.068007 # miss rate for overall accesses
1163system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92378.787879 # average ReadReq miss latency
1164system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 95214.285714 # average ReadReq miss latency
1165system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83506.113304 # average ReadReq miss latency
1166system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86092.394350 # average ReadReq miss latency
1167system.cpu.l2cache.ReadReq_avg_miss_latency::total 85289.620721 # average ReadReq miss latency
1168system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15786.880473 # average UpgradeReq miss latency
1169system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15786.880473 # average UpgradeReq miss latency
1170system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77395.552765 # average ReadExReq miss latency
1171system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77395.552765 # average ReadExReq miss latency
1172system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
1173system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
1174system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
1175system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
1176system.cpu.l2cache.demand_avg_miss_latency::total 79605.617019 # average overall miss latency
1177system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
1178system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
1179system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
1180system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
1181system.cpu.l2cache.overall_avg_miss_latency::total 79605.617019 # average overall miss latency
1182system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1183system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1184system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1185system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1186system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1187system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1188system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1189system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1190system.cpu.l2cache.writebacks::writebacks 102850 # number of writebacks
1191system.cpu.l2cache.writebacks::total 102850 # number of writebacks
1192system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
1193system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1194system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1195system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1196system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1197system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1198system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1199system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1200system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1201system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses
1202system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
1203system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16361 # number of ReadReq MSHR misses
1204system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35683 # number of ReadReq MSHR misses
1205system.cpu.l2cache.ReadReq_mshr_misses::total 52117 # number of ReadReq MSHR misses
1206system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1439 # number of UpgradeReq MSHR misses
1207system.cpu.l2cache.UpgradeReq_mshr_misses::total 1439 # number of UpgradeReq MSHR misses
1208system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134046 # number of ReadExReq MSHR misses
1209system.cpu.l2cache.ReadExReq_mshr_misses::total 134046 # number of ReadExReq MSHR misses
1210system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses
1211system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1212system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses
1213system.cpu.l2cache.demand_mshr_misses::cpu.data 169729 # number of demand (read+write) MSHR misses
1214system.cpu.l2cache.demand_mshr_misses::total 186163 # number of demand (read+write) MSHR misses
1215system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses
1216system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1217system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses
1218system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses
1219system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses

1220system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable
1221system.cpu.l2cache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable
1222system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable
1223system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
1224system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
1225system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses

1214system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles
1215system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles
1216system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles
1217system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2626180250 # number of ReadReq MSHR miss cycles
1218system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3793540968 # number of ReadReq MSHR miss cycles
1219system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles
1220system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles
1221system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8698623734 # number of ReadExReq MSHR miss cycles
1222system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8698623734 # number of ReadExReq MSHR miss cycles
1223system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5264500 # number of demand (read+write) MSHR miss cycles
1224system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 578000 # number of demand (read+write) MSHR miss cycles
1225system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1161518218 # number of demand (read+write) MSHR miss cycles
1226system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11324803984 # number of demand (read+write) MSHR miss cycles
1227system.cpu.l2cache.demand_mshr_miss_latency::total 12492164702 # number of demand (read+write) MSHR miss cycles
1228system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5264500 # number of overall MSHR miss cycles
1229system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 578000 # number of overall MSHR miss cycles
1230system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1161518218 # number of overall MSHR miss cycles
1231system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11324803984 # number of overall MSHR miss cycles
1232system.cpu.l2cache.overall_mshr_miss_latency::total 12492164702 # number of overall MSHR miss cycles
1233system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88988446000 # number of ReadReq MSHR uncacheable cycles
1234system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88988446000 # number of ReadReq MSHR uncacheable cycles
1235system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411352000 # number of WriteReq MSHR uncacheable cycles
1236system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411352000 # number of WriteReq MSHR uncacheable cycles
1237system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91399798000 # number of overall MSHR uncacheable cycles
1238system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91399798000 # number of overall MSHR uncacheable cycles
1239system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses
1240system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for ReadReq accesses
1241system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for ReadReq accesses
1242system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026036 # mshr miss rate for ReadReq accesses
1243system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021284 # mshr miss rate for ReadReq accesses
1244system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.822756 # mshr miss rate for UpgradeReq accesses
1245system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.822756 # mshr miss rate for UpgradeReq accesses
1246system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464232 # mshr miss rate for ReadExReq accesses
1247system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464232 # mshr miss rate for ReadExReq accesses
1248system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses
1249system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for demand accesses
1250system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for demand accesses
1251system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for demand accesses
1252system.cpu.l2cache.demand_mshr_miss_rate::total 0.068006 # mshr miss rate for demand accesses
1253system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses
1254system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for overall accesses
1255system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for overall accesses
1256system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for overall accesses
1257system.cpu.l2cache.overall_mshr_miss_rate::total 0.068006 # mshr miss rate for overall accesses
1258system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average ReadReq mshr miss latency
1259system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average ReadReq mshr miss latency
1260system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70993.106656 # average ReadReq mshr miss latency
1261system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73597.518426 # average ReadReq mshr miss latency
1262system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72788.935817 # average ReadReq mshr miss latency
1263system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18378.332175 # average UpgradeReq mshr miss latency
1264system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18378.332175 # average UpgradeReq mshr miss latency
1265system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64892.825851 # average ReadExReq mshr miss latency
1266system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64892.825851 # average ReadExReq mshr miss latency
1267system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
1268system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
1269system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
1270system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
1271system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
1272system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
1273system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
1274system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
1275system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
1276system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency

1226system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles
1227system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles
1228system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles
1229system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2626180250 # number of ReadReq MSHR miss cycles
1230system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3793540968 # number of ReadReq MSHR miss cycles
1231system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles
1232system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles
1233system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8698623734 # number of ReadExReq MSHR miss cycles
1234system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8698623734 # number of ReadExReq MSHR miss cycles
1235system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5264500 # number of demand (read+write) MSHR miss cycles
1236system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 578000 # number of demand (read+write) MSHR miss cycles
1237system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1161518218 # number of demand (read+write) MSHR miss cycles
1238system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11324803984 # number of demand (read+write) MSHR miss cycles
1239system.cpu.l2cache.demand_mshr_miss_latency::total 12492164702 # number of demand (read+write) MSHR miss cycles
1240system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5264500 # number of overall MSHR miss cycles
1241system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 578000 # number of overall MSHR miss cycles
1242system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1161518218 # number of overall MSHR miss cycles
1243system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11324803984 # number of overall MSHR miss cycles
1244system.cpu.l2cache.overall_mshr_miss_latency::total 12492164702 # number of overall MSHR miss cycles
1245system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88988446000 # number of ReadReq MSHR uncacheable cycles
1246system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88988446000 # number of ReadReq MSHR uncacheable cycles
1247system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411352000 # number of WriteReq MSHR uncacheable cycles
1248system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411352000 # number of WriteReq MSHR uncacheable cycles
1249system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91399798000 # number of overall MSHR uncacheable cycles
1250system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91399798000 # number of overall MSHR uncacheable cycles
1251system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses
1252system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for ReadReq accesses
1253system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for ReadReq accesses
1254system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026036 # mshr miss rate for ReadReq accesses
1255system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021284 # mshr miss rate for ReadReq accesses
1256system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.822756 # mshr miss rate for UpgradeReq accesses
1257system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.822756 # mshr miss rate for UpgradeReq accesses
1258system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464232 # mshr miss rate for ReadExReq accesses
1259system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464232 # mshr miss rate for ReadExReq accesses
1260system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses
1261system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for demand accesses
1262system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for demand accesses
1263system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for demand accesses
1264system.cpu.l2cache.demand_mshr_miss_rate::total 0.068006 # mshr miss rate for demand accesses
1265system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses
1266system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for overall accesses
1267system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for overall accesses
1268system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for overall accesses
1269system.cpu.l2cache.overall_mshr_miss_rate::total 0.068006 # mshr miss rate for overall accesses
1270system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average ReadReq mshr miss latency
1271system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average ReadReq mshr miss latency
1272system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70993.106656 # average ReadReq mshr miss latency
1273system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73597.518426 # average ReadReq mshr miss latency
1274system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72788.935817 # average ReadReq mshr miss latency
1275system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18378.332175 # average UpgradeReq mshr miss latency
1276system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18378.332175 # average UpgradeReq mshr miss latency
1277system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64892.825851 # average ReadExReq mshr miss latency
1278system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64892.825851 # average ReadExReq mshr miss latency
1279system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
1280system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
1281system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
1282system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
1283system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
1284system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
1285system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
1286system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
1287system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
1288system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency

1277system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1278system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1279system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1280system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1281system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1282system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

1289system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686 # average ReadReq mshr uncacheable latency
1290system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency
1291system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873 # average WriteReq mshr uncacheable latency
1292system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency
1293system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233 # average overall mshr uncacheable latency
1294system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency

1283system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1284system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution
1285system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution
1286system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution
1287system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution
1288system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution
1289system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution
1290system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution
1291system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
1292system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution
1293system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution

1295system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1296system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution
1297system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution
1298system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution
1299system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution
1300system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution
1301system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution
1302system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution
1303system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
1304system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution
1305system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution

1306system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution

1294system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
1295system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes)
1296system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes)
1297system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes)
1298system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes)
1299system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes)
1300system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes)
1301system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes)
1302system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes)
1303system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes)
1304system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes)

1307system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
1308system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes)
1309system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes)
1310system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes)
1311system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes)
1312system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes)
1313system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes)
1314system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes)
1315system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes)
1316system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes)
1317system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes)

1305system.cpu.toL2Bus.snoops 61672 # Total snoops (count)
1306system.cpu.toL2Bus.snoop_fanout::samples 4387054 # Request fanout histogram
1307system.cpu.toL2Bus.snoop_fanout::mean 3.010870 # Request fanout histogram
1308system.cpu.toL2Bus.snoop_fanout::stdev 0.103692 # Request fanout histogram

1318system.cpu.toL2Bus.snoops 63315 # Total snoops (count)
1319system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram
1320system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram
1321system.cpu.toL2Bus.snoop_fanout::stdev 0.098766 # Request fanout histogram

1309system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1310system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1311system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1312system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram

1322system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1323system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1324system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1325system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram

1313system.cpu.toL2Bus.snoop_fanout::3 4339366 98.91% 98.91% # Request fanout histogram
1314system.cpu.toL2Bus.snoop_fanout::4 47688 1.09% 100.00% # Request fanout histogram

1326system.cpu.toL2Bus.snoop_fanout::3 4957986 99.01% 99.01% # Request fanout histogram
1327system.cpu.toL2Bus.snoop_fanout::4 49331 0.99% 100.00% # Request fanout histogram

1315system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1316system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1317system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram

1328system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1329system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1330system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram

1318system.cpu.toL2Bus.snoop_fanout::total 4387054 # Request fanout histogram

1331system.cpu.toL2Bus.snoop_fanout::total 5007317 # Request fanout histogram

1319system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks)
1320system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1321system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks)
1322system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1323system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks)
1324system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1325system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks)
1326system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1327system.cpu.toL2Bus.respLayer2.occupancy 21588991 # Layer occupancy (ticks)
1328system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1329system.cpu.toL2Bus.respLayer3.occupancy 118331389 # Layer occupancy (ticks)
1330system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1331system.iobus.trans_dist::ReadReq 223899 # Transaction distribution
1332system.iobus.trans_dist::ReadResp 223899 # Transaction distribution
1333system.iobus.trans_dist::WriteReq 57753 # Transaction distribution
1334system.iobus.trans_dist::WriteResp 11033 # Transaction distribution
1335system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1336system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
1337system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
1338system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1339system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1340system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1341system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1342system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1343system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1344system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1345system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1346system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes)
1347system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1348system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1349system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1350system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1351system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1352system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1353system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1354system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1355system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1356system.iobus.pkt_count_system.bridge.master::total 468050 # Packet count per connected master and slave (bytes)
1357system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
1358system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
1359system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
1360system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
1361system.iobus.pkt_count::total 566590 # Packet count per connected master and slave (bytes)
1362system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1363system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1364system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1365system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1366system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1367system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1368system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1369system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1370system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes)
1371system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1372system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1373system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1374system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1375system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1376system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1377system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1378system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1379system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1380system.iobus.pkt_size_system.bridge.master::total 240311 # Cumulative packet size per connected master and slave (bytes)
1381system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
1382system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
1383system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
1384system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1385system.iobus.pkt_size::total 3274683 # Cumulative packet size per connected master and slave (bytes)
1386system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks)
1387system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1388system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1389system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1390system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1391system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1392system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
1393system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1394system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1395system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1396system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1397system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1398system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1399system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1400system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1401system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1402system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1403system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1404system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks)
1405system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1406system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1407system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1408system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1409system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1410system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1411system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1412system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1413system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1414system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1415system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1416system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1417system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1418system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1419system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1420system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1421system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1422system.iobus.reqLayer19.occupancy 257302678 # Layer occupancy (ticks)
1423system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1424system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1425system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1426system.iobus.respLayer0.occupancy 457017000 # Layer occupancy (ticks)
1427system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1428system.iobus.respLayer1.occupancy 50364257 # Layer occupancy (ticks)
1429system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1430system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
1431system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1432system.iocache.tags.replacements 47572 # number of replacements
1433system.iocache.tags.tagsinuse 0.078977 # Cycle average of tags in use
1434system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1435system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
1436system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1437system.iocache.tags.warmup_cycle 4993305876000 # Cycle when the warmup percentage was hit.
1438system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.078977 # Average occupied blocks per requestor
1439system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004936 # Average percentage of cache occupancy
1440system.iocache.tags.occ_percent::total 0.004936 # Average percentage of cache occupancy
1441system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1442system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1443system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1444system.iocache.tags.tag_accesses 428643 # Number of tag accesses
1445system.iocache.tags.data_accesses 428643 # Number of data accesses
1446system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
1447system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
1448system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
1449system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
1450system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
1451system.iocache.demand_misses::total 907 # number of demand (read+write) misses
1452system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
1453system.iocache.overall_misses::total 907 # number of overall misses
1454system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142095944 # number of ReadReq miss cycles
1455system.iocache.ReadReq_miss_latency::total 142095944 # number of ReadReq miss cycles
1456system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8602345477 # number of WriteInvalidateReq miss cycles
1457system.iocache.WriteInvalidateReq_miss_latency::total 8602345477 # number of WriteInvalidateReq miss cycles
1458system.iocache.demand_miss_latency::pc.south_bridge.ide 142095944 # number of demand (read+write) miss cycles
1459system.iocache.demand_miss_latency::total 142095944 # number of demand (read+write) miss cycles
1460system.iocache.overall_miss_latency::pc.south_bridge.ide 142095944 # number of overall miss cycles
1461system.iocache.overall_miss_latency::total 142095944 # number of overall miss cycles
1462system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
1463system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
1464system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1465system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1466system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
1467system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
1468system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
1469system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
1470system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1471system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1472system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
1473system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1474system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1475system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1476system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1477system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1478system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average ReadReq miss latency
1479system.iocache.ReadReq_avg_miss_latency::total 156665.869901 # average ReadReq miss latency
1480system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 184125.545313 # average WriteInvalidateReq miss latency
1481system.iocache.WriteInvalidateReq_avg_miss_latency::total 184125.545313 # average WriteInvalidateReq miss latency
1482system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
1483system.iocache.demand_avg_miss_latency::total 156665.869901 # average overall miss latency
1484system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
1485system.iocache.overall_avg_miss_latency::total 156665.869901 # average overall miss latency
1486system.iocache.blocked_cycles::no_mshrs 29724 # number of cycles access was blocked
1487system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1488system.iocache.blocked::no_mshrs 4480 # number of cycles access was blocked
1489system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1490system.iocache.avg_blocked_cycles::no_mshrs 6.634821 # average number of cycles each access was blocked
1491system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1492system.iocache.fast_writes 0 # number of fast writes performed
1493system.iocache.cache_copies 0 # number of cache copies performed
1494system.iocache.writebacks::writebacks 46667 # number of writebacks
1495system.iocache.writebacks::total 46667 # number of writebacks
1496system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
1497system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
1498system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
1499system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
1500system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
1501system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
1502system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
1503system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses
1504system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of ReadReq MSHR miss cycles
1505system.iocache.ReadReq_mshr_miss_latency::total 94520448 # number of ReadReq MSHR miss cycles
1506system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6172895487 # number of WriteInvalidateReq MSHR miss cycles
1507system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6172895487 # number of WriteInvalidateReq MSHR miss cycles
1508system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of demand (read+write) MSHR miss cycles
1509system.iocache.demand_mshr_miss_latency::total 94520448 # number of demand (read+write) MSHR miss cycles
1510system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of overall MSHR miss cycles
1511system.iocache.overall_mshr_miss_latency::total 94520448 # number of overall MSHR miss cycles
1512system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1513system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1514system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1515system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1516system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1517system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1518system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1519system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1520system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average ReadReq mshr miss latency
1521system.iocache.ReadReq_avg_mshr_miss_latency::total 104212.180816 # average ReadReq mshr miss latency
1522system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 132125.331485 # average WriteInvalidateReq mshr miss latency
1523system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132125.331485 # average WriteInvalidateReq mshr miss latency
1524system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
1525system.iocache.demand_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
1526system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
1527system.iocache.overall_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
1528system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1529system.membus.trans_dist::ReadReq 657725 # Transaction distribution
1530system.membus.trans_dist::ReadResp 657721 # Transaction distribution
1531system.membus.trans_dist::WriteReq 13919 # Transaction distribution
1532system.membus.trans_dist::WriteResp 13919 # Transaction distribution
1533system.membus.trans_dist::Writeback 149517 # Transaction distribution
1534system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1535system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1536system.membus.trans_dist::UpgradeReq 2208 # Transaction distribution
1537system.membus.trans_dist::UpgradeResp 1727 # Transaction distribution
1538system.membus.trans_dist::ReadExReq 133760 # Transaction distribution
1539system.membus.trans_dist::ReadExResp 133758 # Transaction distribution
1540system.membus.trans_dist::MessageReq 1643 # Transaction distribution
1541system.membus.trans_dist::MessageResp 1643 # Transaction distribution
1542system.membus.trans_dist::BadAddressError 4 # Transaction distribution
1543system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
1544system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
1545system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468050 # Packet count per connected master and slave (bytes)
1546system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769190 # Packet count per connected master and slave (bytes)
1547system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477841 # Packet count per connected master and slave (bytes)
1548system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes)
1549system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1715089 # Packet count per connected master and slave (bytes)
1550system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141457 # Packet count per connected master and slave (bytes)
1551system.membus.pkt_count_system.iocache.mem_side::total 141457 # Packet count per connected master and slave (bytes)
1552system.membus.pkt_count::total 1859832 # Packet count per connected master and slave (bytes)
1553system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
1554system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1555system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes)
1556system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes)
1557system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes)
1558system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes)
1559system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
1560system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
1561system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes)
1562system.membus.snoops 1635 # Total snoops (count)

1332system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks)
1333system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1334system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks)
1335system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1336system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks)
1337system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1338system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks)
1339system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1340system.cpu.toL2Bus.respLayer2.occupancy 21588991 # Layer occupancy (ticks)
1341system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1342system.cpu.toL2Bus.respLayer3.occupancy 118331389 # Layer occupancy (ticks)
1343system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1344system.iobus.trans_dist::ReadReq 223899 # Transaction distribution
1345system.iobus.trans_dist::ReadResp 223899 # Transaction distribution
1346system.iobus.trans_dist::WriteReq 57753 # Transaction distribution
1347system.iobus.trans_dist::WriteResp 11033 # Transaction distribution
1348system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1349system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
1350system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
1351system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1352system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1353system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1354system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1355system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1356system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1357system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1358system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1359system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes)
1360system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1361system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1362system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1363system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1364system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1365system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1366system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1367system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1368system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1369system.iobus.pkt_count_system.bridge.master::total 468050 # Packet count per connected master and slave (bytes)
1370system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
1371system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
1372system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
1373system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
1374system.iobus.pkt_count::total 566590 # Packet count per connected master and slave (bytes)
1375system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1376system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1377system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1378system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1379system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1380system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1381system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1382system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1383system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes)
1384system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1385system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1386system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1387system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1388system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1389system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1390system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1391system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1392system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1393system.iobus.pkt_size_system.bridge.master::total 240311 # Cumulative packet size per connected master and slave (bytes)
1394system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
1395system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
1396system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
1397system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1398system.iobus.pkt_size::total 3274683 # Cumulative packet size per connected master and slave (bytes)
1399system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks)
1400system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1401system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1402system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1403system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1404system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1405system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
1406system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1407system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1408system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1409system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1410system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1411system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1412system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1413system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1414system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1415system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1416system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1417system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks)
1418system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1419system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1420system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1421system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1422system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1423system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1424system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1425system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1426system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1427system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1428system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1429system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1430system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1431system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1432system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1433system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1434system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1435system.iobus.reqLayer19.occupancy 257302678 # Layer occupancy (ticks)
1436system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1437system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1438system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1439system.iobus.respLayer0.occupancy 457017000 # Layer occupancy (ticks)
1440system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1441system.iobus.respLayer1.occupancy 50364257 # Layer occupancy (ticks)
1442system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1443system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
1444system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1445system.iocache.tags.replacements 47572 # number of replacements
1446system.iocache.tags.tagsinuse 0.078977 # Cycle average of tags in use
1447system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1448system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
1449system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1450system.iocache.tags.warmup_cycle 4993305876000 # Cycle when the warmup percentage was hit.
1451system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.078977 # Average occupied blocks per requestor
1452system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004936 # Average percentage of cache occupancy
1453system.iocache.tags.occ_percent::total 0.004936 # Average percentage of cache occupancy
1454system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1455system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1456system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1457system.iocache.tags.tag_accesses 428643 # Number of tag accesses
1458system.iocache.tags.data_accesses 428643 # Number of data accesses
1459system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
1460system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
1461system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
1462system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
1463system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
1464system.iocache.demand_misses::total 907 # number of demand (read+write) misses
1465system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
1466system.iocache.overall_misses::total 907 # number of overall misses
1467system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142095944 # number of ReadReq miss cycles
1468system.iocache.ReadReq_miss_latency::total 142095944 # number of ReadReq miss cycles
1469system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8602345477 # number of WriteInvalidateReq miss cycles
1470system.iocache.WriteInvalidateReq_miss_latency::total 8602345477 # number of WriteInvalidateReq miss cycles
1471system.iocache.demand_miss_latency::pc.south_bridge.ide 142095944 # number of demand (read+write) miss cycles
1472system.iocache.demand_miss_latency::total 142095944 # number of demand (read+write) miss cycles
1473system.iocache.overall_miss_latency::pc.south_bridge.ide 142095944 # number of overall miss cycles
1474system.iocache.overall_miss_latency::total 142095944 # number of overall miss cycles
1475system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
1476system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
1477system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1478system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1479system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
1480system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
1481system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
1482system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
1483system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1484system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1485system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
1486system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1487system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1488system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1489system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1490system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1491system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average ReadReq miss latency
1492system.iocache.ReadReq_avg_miss_latency::total 156665.869901 # average ReadReq miss latency
1493system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 184125.545313 # average WriteInvalidateReq miss latency
1494system.iocache.WriteInvalidateReq_avg_miss_latency::total 184125.545313 # average WriteInvalidateReq miss latency
1495system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
1496system.iocache.demand_avg_miss_latency::total 156665.869901 # average overall miss latency
1497system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
1498system.iocache.overall_avg_miss_latency::total 156665.869901 # average overall miss latency
1499system.iocache.blocked_cycles::no_mshrs 29724 # number of cycles access was blocked
1500system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1501system.iocache.blocked::no_mshrs 4480 # number of cycles access was blocked
1502system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1503system.iocache.avg_blocked_cycles::no_mshrs 6.634821 # average number of cycles each access was blocked
1504system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1505system.iocache.fast_writes 0 # number of fast writes performed
1506system.iocache.cache_copies 0 # number of cache copies performed
1507system.iocache.writebacks::writebacks 46667 # number of writebacks
1508system.iocache.writebacks::total 46667 # number of writebacks
1509system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
1510system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
1511system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
1512system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
1513system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
1514system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
1515system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
1516system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses
1517system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of ReadReq MSHR miss cycles
1518system.iocache.ReadReq_mshr_miss_latency::total 94520448 # number of ReadReq MSHR miss cycles
1519system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6172895487 # number of WriteInvalidateReq MSHR miss cycles
1520system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6172895487 # number of WriteInvalidateReq MSHR miss cycles
1521system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of demand (read+write) MSHR miss cycles
1522system.iocache.demand_mshr_miss_latency::total 94520448 # number of demand (read+write) MSHR miss cycles
1523system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of overall MSHR miss cycles
1524system.iocache.overall_mshr_miss_latency::total 94520448 # number of overall MSHR miss cycles
1525system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1526system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1527system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1528system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1529system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1530system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1531system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1532system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1533system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average ReadReq mshr miss latency
1534system.iocache.ReadReq_avg_mshr_miss_latency::total 104212.180816 # average ReadReq mshr miss latency
1535system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 132125.331485 # average WriteInvalidateReq mshr miss latency
1536system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132125.331485 # average WriteInvalidateReq mshr miss latency
1537system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
1538system.iocache.demand_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
1539system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
1540system.iocache.overall_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
1541system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1542system.membus.trans_dist::ReadReq 657725 # Transaction distribution
1543system.membus.trans_dist::ReadResp 657721 # Transaction distribution
1544system.membus.trans_dist::WriteReq 13919 # Transaction distribution
1545system.membus.trans_dist::WriteResp 13919 # Transaction distribution
1546system.membus.trans_dist::Writeback 149517 # Transaction distribution
1547system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1548system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1549system.membus.trans_dist::UpgradeReq 2208 # Transaction distribution
1550system.membus.trans_dist::UpgradeResp 1727 # Transaction distribution
1551system.membus.trans_dist::ReadExReq 133760 # Transaction distribution
1552system.membus.trans_dist::ReadExResp 133758 # Transaction distribution
1553system.membus.trans_dist::MessageReq 1643 # Transaction distribution
1554system.membus.trans_dist::MessageResp 1643 # Transaction distribution
1555system.membus.trans_dist::BadAddressError 4 # Transaction distribution
1556system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
1557system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
1558system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468050 # Packet count per connected master and slave (bytes)
1559system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769190 # Packet count per connected master and slave (bytes)
1560system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477841 # Packet count per connected master and slave (bytes)
1561system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes)
1562system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1715089 # Packet count per connected master and slave (bytes)
1563system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141457 # Packet count per connected master and slave (bytes)
1564system.membus.pkt_count_system.iocache.mem_side::total 141457 # Packet count per connected master and slave (bytes)
1565system.membus.pkt_count::total 1859832 # Packet count per connected master and slave (bytes)
1566system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
1567system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1568system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes)
1569system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes)
1570system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes)
1571system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes)
1572system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
1573system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
1574system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes)
1575system.membus.snoops 1635 # Total snoops (count)

1563system.membus.snoop_fanout::samples 385314 # Request fanout histogram
1564system.membus.snoop_fanout::mean 1 # Request fanout histogram
1565system.membus.snoop_fanout::stdev 0 # Request fanout histogram

1576system.membus.snoop_fanout::samples 1005577 # Request fanout histogram
1577system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram
1578system.membus.snoop_fanout::stdev 0.040388 # Request fanout histogram

1566system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1567system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1579system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1580system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1568system.membus.snoop_fanout::1 385314 100.00% 100.00% # Request fanout histogram
1569system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram

1581system.membus.snoop_fanout::1 1003934 99.84% 99.84% # Request fanout histogram
1582system.membus.snoop_fanout::2 1643 0.16% 100.00% # Request fanout histogram

1570system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1571system.membus.snoop_fanout::min_value 1 # Request fanout histogram

1583system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1584system.membus.snoop_fanout::min_value 1 # Request fanout histogram

1572system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1573system.membus.snoop_fanout::total 385314 # Request fanout histogram

1585system.membus.snoop_fanout::max_value 2 # Request fanout histogram
1586system.membus.snoop_fanout::total 1005577 # Request fanout histogram