Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

stats.txt (10530:533ec854b2f1)	stats.txt (10535:4ccec5baf82c)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.125902 # Number of seconds simulated 4sim_ticks 5125902116500 # Number of ticks simulated 5final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.125902 # Number of seconds simulated 4sim_ticks 5125902116500 # Number of ticks simulated 5final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 134346 # Simulator instruction rate (inst/s) 8host_op_rate 265563 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1687822207 # Simulator tick rate (ticks/s) 10host_mem_usage 793660 # Number of bytes of host memory used 11host_seconds 3036.99 # Real time elapsed on the host	7host_inst_rate 182847 # Simulator instruction rate (inst/s) 8host_op_rate 361437 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2297162464 # Simulator tick rate (ticks/s) 10host_mem_usage 805240 # Number of bytes of host memory used 11host_seconds 2231.41 # Real time elapsed on the host
12sim_insts 408006726 # Number of instructions simulated 13sim_ops 806511598 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 408006726 # Number of instructions simulated 13sim_ops 806511598 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory	16system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory
	20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory	21system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory	27system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory
	31system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory	32system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
36system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)	36system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)
	40system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s)	41system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)	48system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)
	52system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 185800 # Number of read requests accepted 55system.physmem.writeReqs 149916 # Number of write requests accepted 56system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 11891200 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 9594624 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 234 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 1736 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11489 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10946 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11982 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11463 # Per bank write bursts 70system.physmem.perBankRdBursts::4 11671 # Per bank write bursts 71system.physmem.perBankRdBursts::5 11298 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11252 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11687 # Per bank write bursts 74system.physmem.perBankRdBursts::8 11071 # Per bank write bursts 75system.physmem.perBankRdBursts::9 11217 # Per bank write bursts 76system.physmem.perBankRdBursts::10 11355 # Per bank write bursts 77system.physmem.perBankRdBursts::11 12125 # Per bank write bursts 78system.physmem.perBankRdBursts::12 11861 # Per bank write bursts 79system.physmem.perBankRdBursts::13 12651 # Per bank write bursts 80system.physmem.perBankRdBursts::14 12184 # Per bank write bursts 81system.physmem.perBankRdBursts::15 11314 # Per bank write bursts 82system.physmem.perBankWrBursts::0 9710 # Per bank write bursts 83system.physmem.perBankWrBursts::1 9082 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8978 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8996 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9462 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9601 # Per bank write bursts 88system.physmem.perBankWrBursts::6 9097 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8837 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9327 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9159 # Per bank write bursts 92system.physmem.perBankWrBursts::10 9532 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9463 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9618 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9862 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9881 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9285 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 4 # Number of times write queue was full causing retry 100system.physmem.totGap 5125902065000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 185800 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 149916 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 170703 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 12067 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2038 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 421 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2237 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2934 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7172 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 7637 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 7787 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 8527 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 8842 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 9565 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 10246 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11384 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10610 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9929 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 9208 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 9073 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7958 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7723 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7760 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7617 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 249 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 222 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 205 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 183 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 121 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 72846 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 294.719271 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 174.256286 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 318.919065 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 28471 39.08% 39.08% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 17446 23.95% 63.03% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 7310 10.03% 73.07% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 4243 5.82% 78.89% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2987 4.10% 82.99% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1984 2.72% 85.72% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1403 1.93% 87.64% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1126 1.55% 89.19% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7876 10.81% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 72846 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 7377 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 25.152094 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 560.212559 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 7376 99.99% 99.99% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 7377 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 7377 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.318558 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.615023 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.539295 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 6330 85.81% 85.81% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 64 0.87% 86.67% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 33 0.45% 87.12% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 268 3.63% 90.76% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 287 3.89% 94.65% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 24 0.33% 94.97% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 24 0.33% 95.30% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 16 0.22% 95.51% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 20 0.27% 95.78% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 2 0.03% 95.81% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 6 0.08% 95.89% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 2 0.03% 95.92% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 237 3.21% 99.13% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 3 0.04% 99.17% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 2 0.03% 99.20% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 11 0.15% 99.39% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::92-95 1 0.01% 99.40% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::96-99 12 0.16% 99.57% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 3 0.04% 99.62% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::108-111 2 0.03% 99.65% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::112-115 6 0.08% 99.73% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::116-119 3 0.04% 99.77% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.01% 99.78% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 13 0.18% 99.96% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::136-139 1 0.01% 99.97% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 7377 # Writes before turning the bus around for reads 265system.physmem.totQLat 2068154250 # Total ticks spent queuing 266system.physmem.totMemAccLat 5547516750 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 927830000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 11145.11 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 29895.11 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.03 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 21.36 # Average write queue length when enqueuing 281system.physmem.readRowHits 151753 # Number of row buffer hits during reads 282system.physmem.writeRowHits 110856 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes 285system.physmem.avgGap 15268566.48 # Average gap between requests 286system.physmem.pageHitRate 78.28 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 4919748958000 # Time in different power states 288system.physmem.memoryStateTime::REF 171165020000 # Time in different power states 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 290system.physmem.memoryStateTime::ACT 34988035500 # Time in different power states 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 292system.physmem.actEnergy::0 267185520 # Energy for activate commands per rank (pJ) 293system.physmem.actEnergy::1 283530240 # Energy for activate commands per rank (pJ) 294system.physmem.preEnergy::0 145785750 # Energy for precharge commands per rank (pJ) 295system.physmem.preEnergy::1 154704000 # Energy for precharge commands per rank (pJ) 296system.physmem.readEnergy::0 715946400 # Energy for read commands per rank (pJ) 297system.physmem.readEnergy::1 731460600 # Energy for read commands per rank (pJ) 298system.physmem.writeEnergy::0 477984240 # Energy for write commands per rank (pJ) 299system.physmem.writeEnergy::1 493302960 # Energy for write commands per rank (pJ) 300system.physmem.refreshEnergy::0 334798779120 # Energy for refresh commands per rank (pJ) 301system.physmem.refreshEnergy::1 334798779120 # Energy for refresh commands per rank (pJ) 302system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ) 303system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ) 304system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ) 305system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ) 306system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ) 307system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ) 308system.physmem.averagePower::0 668.726542 # Core power per rank (mW) 309system.physmem.averagePower::1 668.742609 # Core power per rank (mW)	53system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 185800 # Number of read requests accepted 55system.physmem.writeReqs 149916 # Number of write requests accepted 56system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 11891200 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 9594624 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 234 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 1736 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11489 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10946 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11982 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11463 # Per bank write bursts 70system.physmem.perBankRdBursts::4 11671 # Per bank write bursts 71system.physmem.perBankRdBursts::5 11298 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11252 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11687 # Per bank write bursts 74system.physmem.perBankRdBursts::8 11071 # Per bank write bursts 75system.physmem.perBankRdBursts::9 11217 # Per bank write bursts 76system.physmem.perBankRdBursts::10 11355 # Per bank write bursts 77system.physmem.perBankRdBursts::11 12125 # Per bank write bursts 78system.physmem.perBankRdBursts::12 11861 # Per bank write bursts 79system.physmem.perBankRdBursts::13 12651 # Per bank write bursts 80system.physmem.perBankRdBursts::14 12184 # Per bank write bursts 81system.physmem.perBankRdBursts::15 11314 # Per bank write bursts 82system.physmem.perBankWrBursts::0 9710 # Per bank write bursts 83system.physmem.perBankWrBursts::1 9082 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8978 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8996 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9462 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9601 # Per bank write bursts 88system.physmem.perBankWrBursts::6 9097 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8837 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9327 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9159 # Per bank write bursts 92system.physmem.perBankWrBursts::10 9532 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9463 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9618 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9862 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9881 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9285 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 4 # Number of times write queue was full causing retry 100system.physmem.totGap 5125902065000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 185800 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 149916 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 170703 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 12067 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2038 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 421 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2237 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2934 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7172 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 7637 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 7787 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 8527 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 8842 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 9565 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 10246 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11384 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10610 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9929 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 9208 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 9073 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7958 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7723 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7760 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7617 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 249 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 222 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 205 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 183 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 121 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 72846 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 294.719271 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 174.256286 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 318.919065 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 28471 39.08% 39.08% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 17446 23.95% 63.03% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 7310 10.03% 73.07% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 4243 5.82% 78.89% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2987 4.10% 82.99% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1984 2.72% 85.72% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1403 1.93% 87.64% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1126 1.55% 89.19% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7876 10.81% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 72846 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 7377 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 25.152094 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 560.212559 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 7376 99.99% 99.99% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 7377 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 7377 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.318558 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.615023 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.539295 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 6330 85.81% 85.81% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 64 0.87% 86.67% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 33 0.45% 87.12% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 268 3.63% 90.76% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 287 3.89% 94.65% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 24 0.33% 94.97% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 24 0.33% 95.30% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 16 0.22% 95.51% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 20 0.27% 95.78% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 2 0.03% 95.81% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 6 0.08% 95.89% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 2 0.03% 95.92% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 237 3.21% 99.13% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 3 0.04% 99.17% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 2 0.03% 99.20% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 11 0.15% 99.39% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::92-95 1 0.01% 99.40% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::96-99 12 0.16% 99.57% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 3 0.04% 99.62% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::108-111 2 0.03% 99.65% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::112-115 6 0.08% 99.73% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::116-119 3 0.04% 99.77% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.01% 99.78% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 13 0.18% 99.96% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::136-139 1 0.01% 99.97% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 7377 # Writes before turning the bus around for reads 265system.physmem.totQLat 2068154250 # Total ticks spent queuing 266system.physmem.totMemAccLat 5547516750 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 927830000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 11145.11 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 29895.11 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.03 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 21.36 # Average write queue length when enqueuing 281system.physmem.readRowHits 151753 # Number of row buffer hits during reads 282system.physmem.writeRowHits 110856 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes 285system.physmem.avgGap 15268566.48 # Average gap between requests 286system.physmem.pageHitRate 78.28 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 4919748958000 # Time in different power states 288system.physmem.memoryStateTime::REF 171165020000 # Time in different power states 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 290system.physmem.memoryStateTime::ACT 34988035500 # Time in different power states 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 292system.physmem.actEnergy::0 267185520 # Energy for activate commands per rank (pJ) 293system.physmem.actEnergy::1 283530240 # Energy for activate commands per rank (pJ) 294system.physmem.preEnergy::0 145785750 # Energy for precharge commands per rank (pJ) 295system.physmem.preEnergy::1 154704000 # Energy for precharge commands per rank (pJ) 296system.physmem.readEnergy::0 715946400 # Energy for read commands per rank (pJ) 297system.physmem.readEnergy::1 731460600 # Energy for read commands per rank (pJ) 298system.physmem.writeEnergy::0 477984240 # Energy for write commands per rank (pJ) 299system.physmem.writeEnergy::1 493302960 # Energy for write commands per rank (pJ) 300system.physmem.refreshEnergy::0 334798779120 # Energy for refresh commands per rank (pJ) 301system.physmem.refreshEnergy::1 334798779120 # Energy for refresh commands per rank (pJ) 302system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ) 303system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ) 304system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ) 305system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ) 306system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ) 307system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ) 308system.physmem.averagePower::0 668.726542 # Core power per rank (mW) 309system.physmem.averagePower::1 668.742609 # Core power per rank (mW)
310system.membus.trans_dist::ReadReq 662592 # Transaction distribution 311system.membus.trans_dist::ReadResp 662582 # Transaction distribution 312system.membus.trans_dist::WriteReq 13889 # Transaction distribution 313system.membus.trans_dist::WriteResp 13889 # Transaction distribution 314system.membus.trans_dist::Writeback 103196 # Transaction distribution 315system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 316system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 317system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution 318system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution 319system.membus.trans_dist::ReadExReq 133104 # Transaction distribution 320system.membus.trans_dist::ReadExResp 133101 # Transaction distribution 321system.membus.trans_dist::MessageReq 1644 # Transaction distribution 322system.membus.trans_dist::MessageResp 1644 # Transaction distribution 323system.membus.trans_dist::BadAddressError 10 # Transaction distribution 324system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) 325system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes) 334system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) 335system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) 336system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) 337system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) 338system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes) 339system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes) 340system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 341system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 342system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes) 343system.membus.snoops 949 # Total snoops (count) 344system.membus.snoop_fanout::samples 338415 # Request fanout histogram 345system.membus.snoop_fanout::mean 1 # Request fanout histogram 346system.membus.snoop_fanout::stdev 0 # Request fanout histogram 347system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 348system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 349system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram 350system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 351system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 352system.membus.snoop_fanout::min_value 1 # Request fanout histogram 353system.membus.snoop_fanout::max_value 1 # Request fanout histogram 354system.membus.snoop_fanout::total 338415 # Request fanout histogram 355system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks) 356system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 357system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks) 358system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 359system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) 360system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 361system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks) 362system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 363system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) 364system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 365system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) 366system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 367system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks) 368system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 369system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks) 370system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 371system.iocache.tags.replacements 47575 # number of replacements 372system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use 373system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 374system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. 375system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 376system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit. 377system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor 378system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy 379system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy 380system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 381system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 382system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 383system.iocache.tags.tag_accesses 428670 # Number of tag accesses 384system.iocache.tags.data_accesses 428670 # Number of data accesses 385system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 386system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits 387system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses 388system.iocache.ReadReq_misses::total 910 # number of ReadReq misses 389system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses 390system.iocache.demand_misses::total 910 # number of demand (read+write) misses 391system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses 392system.iocache.overall_misses::total 910 # number of overall misses 393system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles 394system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles 395system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles 396system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles 397system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles 398system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles 399system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) 400system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) 401system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 402system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 403system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses 404system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses 405system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses 406system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses 407system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 408system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 409system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 410system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 411system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 412system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 413system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency 414system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency 415system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency 416system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency 417system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency 418system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency 419system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 420system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 422system.iocache.blocked::no_targets 0 # number of cycles access was blocked 423system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 424system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.iocache.fast_writes 46720 # number of fast writes performed 426system.iocache.cache_copies 0 # number of cache copies performed 427system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses 428system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses 429system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses 430system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses 431system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses 432system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses 433system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles 434system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles 435system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles 436system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles 437system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles 438system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles 439system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles 440system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles 441system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 442system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 443system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 444system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 445system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 446system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 447system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency 448system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency 449system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 450system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 451system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 452system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 453system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 454system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 455system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 457system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 458system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 459system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 460system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 461system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 462system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 463system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 464system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 465system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 466system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 467system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 468system.iobus.trans_dist::ReadReq 225681 # Transaction distribution 469system.iobus.trans_dist::ReadResp 225681 # Transaction distribution 470system.iobus.trans_dist::WriteReq 57721 # Transaction distribution 471system.iobus.trans_dist::WriteResp 57721 # Transaction distribution 472system.iobus.trans_dist::MessageReq 1644 # Transaction distribution 473system.iobus.trans_dist::MessageResp 1644 # Transaction distribution 474system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 475system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 477system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 479system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 485system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 486system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) 487system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 488system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 489system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 490system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 491system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 492system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) 493system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) 494system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) 495system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) 496system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) 497system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes) 498system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 504system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 505system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 506system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 507system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 508system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 509system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 510system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) 511system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 512system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 513system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 514system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 515system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 516system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) 517system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) 518system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) 519system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) 520system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) 521system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes) 522system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) 523system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 524system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 525system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 526system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 527system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 528system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) 529system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 530system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 531system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 532system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 533system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 534system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 535system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 536system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 537system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 538system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 539system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 540system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 541system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 542system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 543system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 544system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 545system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 546system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 547system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 548system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) 549system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 550system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 551system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 552system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 553system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 554system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 555system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 556system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 557system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 558system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks) 559system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 560system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 561system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 562system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) 563system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 564system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks) 565system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 566system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) 567system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 568system.cpu_clk_domain.clock 500 # Clock period in ticks
569system.cpu.branchPred.lookups 86911006 # Number of BP lookups 570system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted 571system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect 572system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups 573system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits 574system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 575system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage 576system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target. 577system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.	310system.cpu.branchPred.lookups 86911006 # Number of BP lookups 311system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted 312system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect 313system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups 314system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits 315system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 316system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage 317system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target. 318system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.
	319system.cpu_clk_domain.clock 500 # Clock period in ticks
578system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 579system.cpu.numCycles 449563158 # number of cpu cycles simulated 580system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 581system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 582system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss 583system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed 584system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered 585system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken 586system.cpu.fetch.Cycles 417985667 # Number of cycles fetch has run and was not squashing or blocked 587system.cpu.fetch.SquashCycles 1891240 # Number of cycles fetch has spent squashing 588system.cpu.fetch.TlbCycles 143316 # Number of cycles fetch has spent waiting for tlb 589system.cpu.fetch.MiscStallCycles 50930 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 590system.cpu.fetch.PendingTrapStallCycles 210883 # Number of stall cycles due to pending traps 591system.cpu.fetch.PendingQuiesceStallCycles 127962 # Number of stall cycles due to pending quiesce instructions 592system.cpu.fetch.IcacheWaitRetryStallCycles 502 # Number of stall cycles due to full MSHR 593system.cpu.fetch.CacheLines 9183903 # Number of cache lines fetched 594system.cpu.fetch.IcacheSquashes 446388 # Number of outstanding Icache misses that were squashed 595system.cpu.fetch.ItlbSquashes 4881 # Number of outstanding ITLB misses that were squashed 596system.cpu.fetch.rateDist::samples 447018024 # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::mean 1.894555 # Number of instructions fetched each cycle (Total) 598system.cpu.fetch.rateDist::stdev 3.051977 # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 600system.cpu.fetch.rateDist::0 281457902 62.96% 62.96% # Number of instructions fetched each cycle (Total) 601system.cpu.fetch.rateDist::1 2285728 0.51% 63.47% # Number of instructions fetched each cycle (Total) 602system.cpu.fetch.rateDist::2 72178245 16.15% 79.62% # Number of instructions fetched each cycle (Total) 603system.cpu.fetch.rateDist::3 1597297 0.36% 79.98% # Number of instructions fetched each cycle (Total) 604system.cpu.fetch.rateDist::4 2150673 0.48% 80.46% # Number of instructions fetched each cycle (Total) 605system.cpu.fetch.rateDist::5 2329203 0.52% 80.98% # Number of instructions fetched each cycle (Total) 606system.cpu.fetch.rateDist::6 1531441 0.34% 81.32% # Number of instructions fetched each cycle (Total) 607system.cpu.fetch.rateDist::7 1871505 0.42% 81.74% # Number of instructions fetched each cycle (Total) 608system.cpu.fetch.rateDist::8 81616030 18.26% 100.00% # Number of instructions fetched each cycle (Total) 609system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 610system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 611system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 612system.cpu.fetch.rateDist::total 447018024 # Number of instructions fetched each cycle (Total) 613system.cpu.fetch.branchRate 0.193323 # Number of branch fetches per cycle 614system.cpu.fetch.rate 0.954576 # Number of inst fetches per cycle 615system.cpu.decode.IdleCycles 22975502 # Number of cycles decode is idle 616system.cpu.decode.BlockedCycles 264891753 # Number of cycles decode is blocked 617system.cpu.decode.RunCycles 150781344 # Number of cycles decode is running 618system.cpu.decode.UnblockCycles 7423805 # Number of cycles decode is unblocking 619system.cpu.decode.SquashCycles 945620 # Number of cycles decode is squashing 620system.cpu.decode.DecodedInsts 838588132 # Number of instructions handled by decode 621system.cpu.rename.SquashCycles 945620 # Number of cycles rename is squashing 622system.cpu.rename.IdleCycles 25820685 # Number of cycles rename is idle 623system.cpu.rename.BlockCycles 223318475 # Number of cycles rename is blocking 624system.cpu.rename.serializeStallCycles 13301995 # count of cycles rename stalled for serializing inst 625system.cpu.rename.RunCycles 154670533 # Number of cycles rename is running 626system.cpu.rename.UnblockCycles 28960716 # Number of cycles rename is unblocking 627system.cpu.rename.RenamedInsts 835102889 # Number of instructions processed by rename 628system.cpu.rename.ROBFullEvents 477440 # Number of times rename has blocked due to ROB full 629system.cpu.rename.IQFullEvents 12397064 # Number of times rename has blocked due to IQ full 630system.cpu.rename.LQFullEvents 181319 # Number of times rename has blocked due to LQ full 631system.cpu.rename.SQFullEvents 13705397 # Number of times rename has blocked due to SQ full 632system.cpu.rename.RenamedOperands 997542850 # Number of destination operands rename has renamed 633system.cpu.rename.RenameLookups 1813799502 # Number of register rename lookups that rename has made 634system.cpu.rename.int_rename_lookups 1115056777 # Number of integer rename lookups 635system.cpu.rename.fp_rename_lookups 257 # Number of floating rename lookups 636system.cpu.rename.CommittedMaps 964533940 # Number of HB maps that are committed 637system.cpu.rename.UndoneMaps 33008908 # Number of HB maps that are undone due to squashing 638system.cpu.rename.serializingInsts 469072 # count of serializing insts renamed 639system.cpu.rename.tempSerializingInsts 473209 # count of temporary serializing insts renamed 640system.cpu.rename.skidInsts 39003947 # count of insts added to the skid buffer 641system.cpu.memDep0.insertedLoads 17327064 # Number of loads inserted to the mem dependence unit. 642system.cpu.memDep0.insertedStores 10187947 # Number of stores inserted to the mem dependence unit. 643system.cpu.memDep0.conflictingLoads 1305152 # Number of conflicting loads. 644system.cpu.memDep0.conflictingStores 1075480 # Number of conflicting stores. 645system.cpu.iq.iqInstsAdded 829577990 # Number of instructions added to the IQ (excludes non-spec) 646system.cpu.iq.iqNonSpecInstsAdded 1211603 # Number of non-speculative instructions added to the IQ 647system.cpu.iq.iqInstsIssued 824337264 # Number of instructions issued 648system.cpu.iq.iqSquashedInstsIssued 238496 # Number of squashed instructions issued 649system.cpu.iq.iqSquashedInstsExamined 23343623 # Number of squashed instructions iterated over during squash; mainly for profiling 650system.cpu.iq.iqSquashedOperandsExamined 36066469 # Number of squashed operands that are examined and possibly removed from graph 651system.cpu.iq.iqSquashedNonSpecRemoved 155814 # Number of squashed non-spec instructions that were removed 652system.cpu.iq.issued_per_cycle::samples 447018024 # Number of insts issued each cycle 653system.cpu.iq.issued_per_cycle::mean 1.844081 # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::stdev 2.418172 # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::0 262761301 58.78% 58.78% # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::1 13855312 3.10% 61.88% # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::2 10080747 2.26% 64.14% # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::3 6920313 1.55% 65.68% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::4 74355494 16.63% 82.32% # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::5 4460811 1.00% 83.32% # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::6 72820656 16.29% 99.61% # Number of insts issued each cycle 663system.cpu.iq.issued_per_cycle::7 1197568 0.27% 99.87% # Number of insts issued each cycle 664system.cpu.iq.issued_per_cycle::8 565822 0.13% 100.00% # Number of insts issued each cycle 665system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 666system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 667system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 668system.cpu.iq.issued_per_cycle::total 447018024 # Number of insts issued each cycle 669system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 670system.cpu.iq.fu_full::IntAlu 1976611 71.80% 71.80% # attempts to use FU when none available 671system.cpu.iq.fu_full::IntMult 212 0.01% 71.80% # attempts to use FU when none available 672system.cpu.iq.fu_full::IntDiv 1052 0.04% 71.84% # attempts to use FU when none available 673system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.84% # attempts to use FU when none available 674system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.84% # attempts to use FU when none available 675system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.84% # attempts to use FU when none available 676system.cpu.iq.fu_full::FloatMult 0 0.00% 71.84% # attempts to use FU when none available 677system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.84% # attempts to use FU when none available 678system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.84% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.84% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.84% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.84% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.84% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.84% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.84% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdMult 0 0.00% 71.84% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.84% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdShift 0 0.00% 71.84% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.84% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.84% # attempts to use FU when none available 690system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.84% # attempts to use FU when none available 691system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.84% # attempts to use FU when none available 692system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.84% # attempts to use FU when none available 693system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.84% # attempts to use FU when none available 694system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.84% # attempts to use FU when none available 695system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.84% # attempts to use FU when none available 696system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.84% # attempts to use FU when none available 697system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.84% # attempts to use FU when none available 698system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.84% # attempts to use FU when none available 699system.cpu.iq.fu_full::MemRead 614146 22.31% 94.15% # attempts to use FU when none available 700system.cpu.iq.fu_full::MemWrite 161054 5.85% 100.00% # attempts to use FU when none available 701system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 702system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 703system.cpu.iq.FU_type_0::No_OpClass 292817 0.04% 0.04% # Type of FU issued 704system.cpu.iq.FU_type_0::IntAlu 795957789 96.56% 96.59% # Type of FU issued 705system.cpu.iq.FU_type_0::IntMult 150640 0.02% 96.61% # Type of FU issued 706system.cpu.iq.FU_type_0::IntDiv 125262 0.02% 96.63% # Type of FU issued 707system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued 708system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued 709system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued 710system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued 711system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued 712system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued 715system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued 716system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued 717system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued 718system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued 719system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued 724system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued 725system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued 726system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued 727system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued 728system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued 729system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued 730system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued 731system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued 732system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued 733system.cpu.iq.FU_type_0::MemRead 18413325 2.23% 98.86% # Type of FU issued 734system.cpu.iq.FU_type_0::MemWrite 9397431 1.14% 100.00% # Type of FU issued 735system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 736system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 737system.cpu.iq.FU_type_0::total 824337264 # Type of FU issued 738system.cpu.iq.rate 1.833641 # Inst issue rate 739system.cpu.iq.fu_busy_cnt 2753075 # FU busy when requested 740system.cpu.iq.fu_busy_rate 0.003340 # FU busy rate (busy events/executed inst) 741system.cpu.iq.int_inst_queue_reads 2098683906 # Number of integer instruction queue reads 742system.cpu.iq.int_inst_queue_writes 854145561 # Number of integer instruction queue writes 743system.cpu.iq.int_inst_queue_wakeup_accesses 819784123 # Number of integer instruction queue wakeup accesses 744system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads 745system.cpu.iq.fp_inst_queue_writes 406 # Number of floating instruction queue writes 746system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses 747system.cpu.iq.int_alu_accesses 826797420 # Number of integer alu accesses 748system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses 749system.cpu.iew.lsq.thread0.forwLoads 1878905 # Number of loads that had data forwarded from stores 750system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 751system.cpu.iew.lsq.thread0.squashedLoads 3325392 # Number of loads squashed 752system.cpu.iew.lsq.thread0.ignoredResponses 14284 # Number of memory responses ignored because the instruction is squashed 753system.cpu.iew.lsq.thread0.memOrderViolation 14518 # Number of memory ordering violations 754system.cpu.iew.lsq.thread0.squashedStores 1760345 # Number of stores squashed 755system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 756system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 757system.cpu.iew.lsq.thread0.rescheduledLoads 2224613 # Number of loads that were rescheduled 758system.cpu.iew.lsq.thread0.cacheBlocked 71287 # Number of times an access to memory failed due to the cache being blocked 759system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 760system.cpu.iew.iewSquashCycles 945620 # Number of cycles IEW is squashing 761system.cpu.iew.iewBlockCycles 205593402 # Number of cycles IEW is blocking 762system.cpu.iew.iewUnblockCycles 9425350 # Number of cycles IEW is unblocking 763system.cpu.iew.iewDispatchedInsts 830789593 # Number of instructions dispatched to IQ 764system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch 765system.cpu.iew.iewDispLoadInsts 17327064 # Number of dispatched load instructions 766system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions 767system.cpu.iew.iewDispNonSpecInsts 714327 # Number of dispatched non-speculative instructions 768system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall 769system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall 770system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations 771system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly	320system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 321system.cpu.numCycles 449563158 # number of cpu cycles simulated 322system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 323system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 324system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss 325system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed 326system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered 327system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken 328system.cpu.fetch.Cycles 417985667 # Number of cycles fetch has run and was not squashing or blocked 329system.cpu.fetch.SquashCycles 1891240 # Number of cycles fetch has spent squashing 330system.cpu.fetch.TlbCycles 143316 # Number of cycles fetch has spent waiting for tlb 331system.cpu.fetch.MiscStallCycles 50930 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 332system.cpu.fetch.PendingTrapStallCycles 210883 # Number of stall cycles due to pending traps 333system.cpu.fetch.PendingQuiesceStallCycles 127962 # Number of stall cycles due to pending quiesce instructions 334system.cpu.fetch.IcacheWaitRetryStallCycles 502 # Number of stall cycles due to full MSHR 335system.cpu.fetch.CacheLines 9183903 # Number of cache lines fetched 336system.cpu.fetch.IcacheSquashes 446388 # Number of outstanding Icache misses that were squashed 337system.cpu.fetch.ItlbSquashes 4881 # Number of outstanding ITLB misses that were squashed 338system.cpu.fetch.rateDist::samples 447018024 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::mean 1.894555 # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::stdev 3.051977 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::0 281457902 62.96% 62.96% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::1 2285728 0.51% 63.47% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::2 72178245 16.15% 79.62% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::3 1597297 0.36% 79.98% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::4 2150673 0.48% 80.46% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::5 2329203 0.52% 80.98% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::6 1531441 0.34% 81.32% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::7 1871505 0.42% 81.74% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::8 81616030 18.26% 100.00% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::total 447018024 # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.branchRate 0.193323 # Number of branch fetches per cycle 356system.cpu.fetch.rate 0.954576 # Number of inst fetches per cycle 357system.cpu.decode.IdleCycles 22975502 # Number of cycles decode is idle 358system.cpu.decode.BlockedCycles 264891753 # Number of cycles decode is blocked 359system.cpu.decode.RunCycles 150781344 # Number of cycles decode is running 360system.cpu.decode.UnblockCycles 7423805 # Number of cycles decode is unblocking 361system.cpu.decode.SquashCycles 945620 # Number of cycles decode is squashing 362system.cpu.decode.DecodedInsts 838588132 # Number of instructions handled by decode 363system.cpu.rename.SquashCycles 945620 # Number of cycles rename is squashing 364system.cpu.rename.IdleCycles 25820685 # Number of cycles rename is idle 365system.cpu.rename.BlockCycles 223318475 # Number of cycles rename is blocking 366system.cpu.rename.serializeStallCycles 13301995 # count of cycles rename stalled for serializing inst 367system.cpu.rename.RunCycles 154670533 # Number of cycles rename is running 368system.cpu.rename.UnblockCycles 28960716 # Number of cycles rename is unblocking 369system.cpu.rename.RenamedInsts 835102889 # Number of instructions processed by rename 370system.cpu.rename.ROBFullEvents 477440 # Number of times rename has blocked due to ROB full 371system.cpu.rename.IQFullEvents 12397064 # Number of times rename has blocked due to IQ full 372system.cpu.rename.LQFullEvents 181319 # Number of times rename has blocked due to LQ full 373system.cpu.rename.SQFullEvents 13705397 # Number of times rename has blocked due to SQ full 374system.cpu.rename.RenamedOperands 997542850 # Number of destination operands rename has renamed 375system.cpu.rename.RenameLookups 1813799502 # Number of register rename lookups that rename has made 376system.cpu.rename.int_rename_lookups 1115056777 # Number of integer rename lookups 377system.cpu.rename.fp_rename_lookups 257 # Number of floating rename lookups 378system.cpu.rename.CommittedMaps 964533940 # Number of HB maps that are committed 379system.cpu.rename.UndoneMaps 33008908 # Number of HB maps that are undone due to squashing 380system.cpu.rename.serializingInsts 469072 # count of serializing insts renamed 381system.cpu.rename.tempSerializingInsts 473209 # count of temporary serializing insts renamed 382system.cpu.rename.skidInsts 39003947 # count of insts added to the skid buffer 383system.cpu.memDep0.insertedLoads 17327064 # Number of loads inserted to the mem dependence unit. 384system.cpu.memDep0.insertedStores 10187947 # Number of stores inserted to the mem dependence unit. 385system.cpu.memDep0.conflictingLoads 1305152 # Number of conflicting loads. 386system.cpu.memDep0.conflictingStores 1075480 # Number of conflicting stores. 387system.cpu.iq.iqInstsAdded 829577990 # Number of instructions added to the IQ (excludes non-spec) 388system.cpu.iq.iqNonSpecInstsAdded 1211603 # Number of non-speculative instructions added to the IQ 389system.cpu.iq.iqInstsIssued 824337264 # Number of instructions issued 390system.cpu.iq.iqSquashedInstsIssued 238496 # Number of squashed instructions issued 391system.cpu.iq.iqSquashedInstsExamined 23343623 # Number of squashed instructions iterated over during squash; mainly for profiling 392system.cpu.iq.iqSquashedOperandsExamined 36066469 # Number of squashed operands that are examined and possibly removed from graph 393system.cpu.iq.iqSquashedNonSpecRemoved 155814 # Number of squashed non-spec instructions that were removed 394system.cpu.iq.issued_per_cycle::samples 447018024 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::mean 1.844081 # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::stdev 2.418172 # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::0 262761301 58.78% 58.78% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::1 13855312 3.10% 61.88% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::2 10080747 2.26% 64.14% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::3 6920313 1.55% 65.68% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::4 74355494 16.63% 82.32% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::5 4460811 1.00% 83.32% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::6 72820656 16.29% 99.61% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::7 1197568 0.27% 99.87% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::8 565822 0.13% 100.00% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 410system.cpu.iq.issued_per_cycle::total 447018024 # Number of insts issued each cycle 411system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 412system.cpu.iq.fu_full::IntAlu 1976611 71.80% 71.80% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntMult 212 0.01% 71.80% # attempts to use FU when none available 414system.cpu.iq.fu_full::IntDiv 1052 0.04% 71.84% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.84% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.84% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.84% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatMult 0 0.00% 71.84% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.84% # attempts to use FU when none available 420system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.84% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.84% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.84% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.84% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.84% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.84% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.84% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMult 0 0.00% 71.84% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.84% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdShift 0 0.00% 71.84% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.84% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.84% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.84% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.84% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.84% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.84% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.84% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.84% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.84% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.84% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.84% # attempts to use FU when none available 441system.cpu.iq.fu_full::MemRead 614146 22.31% 94.15% # attempts to use FU when none available 442system.cpu.iq.fu_full::MemWrite 161054 5.85% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 444system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 445system.cpu.iq.FU_type_0::No_OpClass 292817 0.04% 0.04% # Type of FU issued 446system.cpu.iq.FU_type_0::IntAlu 795957789 96.56% 96.59% # Type of FU issued 447system.cpu.iq.FU_type_0::IntMult 150640 0.02% 96.61% # Type of FU issued 448system.cpu.iq.FU_type_0::IntDiv 125262 0.02% 96.63% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued 475system.cpu.iq.FU_type_0::MemRead 18413325 2.23% 98.86% # Type of FU issued 476system.cpu.iq.FU_type_0::MemWrite 9397431 1.14% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 479system.cpu.iq.FU_type_0::total 824337264 # Type of FU issued 480system.cpu.iq.rate 1.833641 # Inst issue rate 481system.cpu.iq.fu_busy_cnt 2753075 # FU busy when requested 482system.cpu.iq.fu_busy_rate 0.003340 # FU busy rate (busy events/executed inst) 483system.cpu.iq.int_inst_queue_reads 2098683906 # Number of integer instruction queue reads 484system.cpu.iq.int_inst_queue_writes 854145561 # Number of integer instruction queue writes 485system.cpu.iq.int_inst_queue_wakeup_accesses 819784123 # Number of integer instruction queue wakeup accesses 486system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads 487system.cpu.iq.fp_inst_queue_writes 406 # Number of floating instruction queue writes 488system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses 489system.cpu.iq.int_alu_accesses 826797420 # Number of integer alu accesses 490system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses 491system.cpu.iew.lsq.thread0.forwLoads 1878905 # Number of loads that had data forwarded from stores 492system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 493system.cpu.iew.lsq.thread0.squashedLoads 3325392 # Number of loads squashed 494system.cpu.iew.lsq.thread0.ignoredResponses 14284 # Number of memory responses ignored because the instruction is squashed 495system.cpu.iew.lsq.thread0.memOrderViolation 14518 # Number of memory ordering violations 496system.cpu.iew.lsq.thread0.squashedStores 1760345 # Number of stores squashed 497system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 498system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 499system.cpu.iew.lsq.thread0.rescheduledLoads 2224613 # Number of loads that were rescheduled 500system.cpu.iew.lsq.thread0.cacheBlocked 71287 # Number of times an access to memory failed due to the cache being blocked 501system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 502system.cpu.iew.iewSquashCycles 945620 # Number of cycles IEW is squashing 503system.cpu.iew.iewBlockCycles 205593402 # Number of cycles IEW is blocking 504system.cpu.iew.iewUnblockCycles 9425350 # Number of cycles IEW is unblocking 505system.cpu.iew.iewDispatchedInsts 830789593 # Number of instructions dispatched to IQ 506system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch 507system.cpu.iew.iewDispLoadInsts 17327064 # Number of dispatched load instructions 508system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions 509system.cpu.iew.iewDispNonSpecInsts 714327 # Number of dispatched non-speculative instructions 510system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall 511system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall 512system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations 513system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly
772system.cpu.iew.predictedNotTakenIncorrect 536897 # Number of branches that were predicted not taken incorrectly 773system.cpu.iew.branchMispredicts 1052437 # Number of branch mispredicts detected at execute	514system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly 515system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute
774system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions 775system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed 776system.cpu.iew.iewExecSquashedInsts 1477348 # Number of squashed instructions skipped in execute 777system.cpu.iew.exec_swp 0 # number of swp insts executed 778system.cpu.iew.exec_nop 0 # number of nop insts executed 779system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed 780system.cpu.iew.exec_branches 83308581 # Number of branches executed 781system.cpu.iew.exec_stores 9169768 # Number of stores executed 782system.cpu.iew.exec_rate 1.830056 # Inst execution rate 783system.cpu.iew.wb_sent 822221777 # cumulative count of insts sent to commit 784system.cpu.iew.wb_count 819784184 # cumulative count of insts written-back 785system.cpu.iew.wb_producers 641108962 # num instructions producing a value 786system.cpu.iew.wb_consumers 1050701242 # num instructions consuming a value 787system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 788system.cpu.iew.wb_rate 1.823513 # insts written-back per cycle 789system.cpu.iew.wb_fanout 0.610172 # average fanout of values written-back 790system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 791system.cpu.commit.commitSquashedInsts 24183935 # The number of squashed insts skipped by commit 792system.cpu.commit.commitNonSpecStalls 1055789 # The number of times commit has been forced to stall to communicate backwards 793system.cpu.commit.branchMispredicts 913678 # The number of times a branch was mispredicted 794system.cpu.commit.committed_per_cycle::samples 443381671 # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::mean 1.819001 # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::stdev 2.675688 # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::0 272578077 61.48% 61.48% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::1 11201647 2.53% 64.00% # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::2 3542666 0.80% 64.80% # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::3 74562549 16.82% 81.62% # Number of insts commited each cycle 802system.cpu.commit.committed_per_cycle::4 2432578 0.55% 82.17% # Number of insts commited each cycle 803system.cpu.commit.committed_per_cycle::5 1609465 0.36% 82.53% # Number of insts commited each cycle 804system.cpu.commit.committed_per_cycle::6 914477 0.21% 82.74% # Number of insts commited each cycle 805system.cpu.commit.committed_per_cycle::7 71049223 16.02% 98.76% # Number of insts commited each cycle 806system.cpu.commit.committed_per_cycle::8 5490989 1.24% 100.00% # Number of insts commited each cycle 807system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 808system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 809system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 810system.cpu.commit.committed_per_cycle::total 443381671 # Number of insts commited each cycle 811system.cpu.commit.committedInsts 408006726 # Number of instructions committed 812system.cpu.commit.committedOps 806511598 # Number of ops (including micro ops) committed 813system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 814system.cpu.commit.refs 22429273 # Number of memory references committed 815system.cpu.commit.loads 14001671 # Number of loads committed 816system.cpu.commit.membars 475333 # Number of memory barriers committed 817system.cpu.commit.branches 82207365 # Number of branches committed 818system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 819system.cpu.commit.int_insts 735317995 # Number of committed integer instructions. 820system.cpu.commit.function_calls 1155841 # Number of function calls committed. 821system.cpu.commit.op_class_0::No_OpClass 174216 0.02% 0.02% # Class of committed instruction 822system.cpu.commit.op_class_0::IntAlu 783641693 97.16% 97.19% # Class of committed instruction 823system.cpu.commit.op_class_0::IntMult 144853 0.02% 97.20% # Class of committed instruction 824system.cpu.commit.op_class_0::IntDiv 121563 0.02% 97.22% # Class of committed instruction 825system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 826system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 827system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction 828system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 829system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 830system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 832system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction 833system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction 834system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction 842system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction 843system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 844system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 845system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 846system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 847system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 848system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 849system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 850system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction 851system.cpu.commit.op_class_0::MemRead 14001671 1.74% 98.96% # Class of committed instruction 852system.cpu.commit.op_class_0::MemWrite 8427602 1.04% 100.00% # Class of committed instruction 853system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 854system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 855system.cpu.commit.op_class_0::total 806511598 # Class of committed instruction 856system.cpu.commit.bw_lim_events 5490989 # number cycles where commit BW limit reached 857system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 858system.cpu.rob.rob_reads 1268507964 # The number of ROB reads 859system.cpu.rob.rob_writes 1665044622 # The number of ROB writes 860system.cpu.timesIdled 294262 # Number of times that the entire CPU went into an idle state and unscheduled itself 861system.cpu.idleCycles 2545134 # Total number of cycles that the CPU has spent unscheduled due to idling 862system.cpu.quiesceCycles 9802241311 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 863system.cpu.committedInsts 408006726 # Number of Instructions Simulated 864system.cpu.committedOps 806511598 # Number of Ops (including micro ops) Simulated 865system.cpu.cpi 1.101852 # CPI: Cycles Per Instruction 866system.cpu.cpi_total 1.101852 # CPI: Total CPI of All Threads 867system.cpu.ipc 0.907563 # IPC: Instructions Per Cycle 868system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads 869system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads 870system.cpu.int_regfile_writes 656162059 # number of integer regfile writes 871system.cpu.fp_regfile_reads 61 # number of floating regfile reads 872system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads 873system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes 874system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads 875system.cpu.misc_regfile_writes 402647 # number of misc regfile writes	516system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions 517system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed 518system.cpu.iew.iewExecSquashedInsts 1477348 # Number of squashed instructions skipped in execute 519system.cpu.iew.exec_swp 0 # number of swp insts executed 520system.cpu.iew.exec_nop 0 # number of nop insts executed 521system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed 522system.cpu.iew.exec_branches 83308581 # Number of branches executed 523system.cpu.iew.exec_stores 9169768 # Number of stores executed 524system.cpu.iew.exec_rate 1.830056 # Inst execution rate 525system.cpu.iew.wb_sent 822221777 # cumulative count of insts sent to commit 526system.cpu.iew.wb_count 819784184 # cumulative count of insts written-back 527system.cpu.iew.wb_producers 641108962 # num instructions producing a value 528system.cpu.iew.wb_consumers 1050701242 # num instructions consuming a value 529system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 530system.cpu.iew.wb_rate 1.823513 # insts written-back per cycle 531system.cpu.iew.wb_fanout 0.610172 # average fanout of values written-back 532system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 533system.cpu.commit.commitSquashedInsts 24183935 # The number of squashed insts skipped by commit 534system.cpu.commit.commitNonSpecStalls 1055789 # The number of times commit has been forced to stall to communicate backwards 535system.cpu.commit.branchMispredicts 913678 # The number of times a branch was mispredicted 536system.cpu.commit.committed_per_cycle::samples 443381671 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::mean 1.819001 # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::stdev 2.675688 # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::0 272578077 61.48% 61.48% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::1 11201647 2.53% 64.00% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::2 3542666 0.80% 64.80% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::3 74562549 16.82% 81.62% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::4 2432578 0.55% 82.17% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::5 1609465 0.36% 82.53% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::6 914477 0.21% 82.74% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::7 71049223 16.02% 98.76% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::8 5490989 1.24% 100.00% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 552system.cpu.commit.committed_per_cycle::total 443381671 # Number of insts commited each cycle 553system.cpu.commit.committedInsts 408006726 # Number of instructions committed 554system.cpu.commit.committedOps 806511598 # Number of ops (including micro ops) committed 555system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 556system.cpu.commit.refs 22429273 # Number of memory references committed 557system.cpu.commit.loads 14001671 # Number of loads committed 558system.cpu.commit.membars 475333 # Number of memory barriers committed 559system.cpu.commit.branches 82207365 # Number of branches committed 560system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 561system.cpu.commit.int_insts 735317995 # Number of committed integer instructions. 562system.cpu.commit.function_calls 1155841 # Number of function calls committed. 563system.cpu.commit.op_class_0::No_OpClass 174216 0.02% 0.02% # Class of committed instruction 564system.cpu.commit.op_class_0::IntAlu 783641693 97.16% 97.19% # Class of committed instruction 565system.cpu.commit.op_class_0::IntMult 144853 0.02% 97.20% # Class of committed instruction 566system.cpu.commit.op_class_0::IntDiv 121563 0.02% 97.22% # Class of committed instruction 567system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 568system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 569system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction 570system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 571system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 572system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction 577system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction 578system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction 579system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction 580system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction 581system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction 582system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction 583system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction 584system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction 585system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 586system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 587system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 588system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 589system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 590system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 591system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 592system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction 593system.cpu.commit.op_class_0::MemRead 14001671 1.74% 98.96% # Class of committed instruction 594system.cpu.commit.op_class_0::MemWrite 8427602 1.04% 100.00% # Class of committed instruction 595system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 596system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 597system.cpu.commit.op_class_0::total 806511598 # Class of committed instruction 598system.cpu.commit.bw_lim_events 5490989 # number cycles where commit BW limit reached 599system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 600system.cpu.rob.rob_reads 1268507964 # The number of ROB reads 601system.cpu.rob.rob_writes 1665044622 # The number of ROB writes 602system.cpu.timesIdled 294262 # Number of times that the entire CPU went into an idle state and unscheduled itself 603system.cpu.idleCycles 2545134 # Total number of cycles that the CPU has spent unscheduled due to idling 604system.cpu.quiesceCycles 9802241311 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 605system.cpu.committedInsts 408006726 # Number of Instructions Simulated 606system.cpu.committedOps 806511598 # Number of Ops (including micro ops) Simulated 607system.cpu.cpi 1.101852 # CPI: Cycles Per Instruction 608system.cpu.cpi_total 1.101852 # CPI: Total CPI of All Threads 609system.cpu.ipc 0.907563 # IPC: Instructions Per Cycle 610system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads 611system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads 612system.cpu.int_regfile_writes 656162059 # number of integer regfile writes 613system.cpu.fp_regfile_reads 61 # number of floating regfile reads 614system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads 615system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes 616system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads 617system.cpu.misc_regfile_writes 402647 # number of misc regfile writes
876system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution 877system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution 879system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution 881system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution 883system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution 884system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution 885system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution 887system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes) 888system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes) 889system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes) 890system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes) 891system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes) 892system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes) 893system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes) 894system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes) 895system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes) 896system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes) 897system.cpu.toL2Bus.snoops 58568 # Total snoops (count) 898system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram 899system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram 900system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram 901system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 902system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 903system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram 911system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks) 912system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 913system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) 914system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 915system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks) 916system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 917system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks) 918system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 919system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks) 920system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)	618system.cpu.dcache.tags.replacements 1657683 # number of replacements 619system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use 620system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks. 621system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks. 622system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks. 623system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. 624system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor 625system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy 626system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy 627system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 629system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 630system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 631system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 632system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses 633system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses 634system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits 635system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits 636system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits 637system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits 638system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits 639system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits 640system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits 641system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits 642system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits 643system.cpu.dcache.overall_hits::total 19128334 # number of overall hits 644system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses 645system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses 646system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses 647system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses 648system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses 649system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses 650system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses 651system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses 652system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses 653system.cpu.dcache.overall_misses::total 2535648 # number of overall misses 654system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles 655system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles 656system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles 657system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles 658system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles 659system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles 660system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles 661system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles 662system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses) 663system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses) 664system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses) 665system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses) 666system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses) 667system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses) 668system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses 669system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses 670system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses 671system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses 672system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses 674system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses 676system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses 677system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses 678system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses 679system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses 680system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses 681system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency 683system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency 684system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency 685system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency 686system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency 687system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency 688system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency 689system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency 690system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked 691system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 692system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked 693system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 694system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked 695system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 696system.cpu.dcache.fast_writes 0 # number of fast writes performed 697system.cpu.dcache.cache_copies 0 # number of cache copies performed 698system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks 699system.cpu.dcache.writebacks::total 1559289 # number of writebacks 700system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits 701system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits 702system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits 703system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits 704system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits 705system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits 706system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits 707system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits 708system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses 709system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses 710system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses 711system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses 712system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses 713system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses 714system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses 715system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses 716system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses 717system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses 718system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles 719system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles 720system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles 721system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles 722system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles 723system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles 724system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles 725system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles 726system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles 727system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles 728system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles 729system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles 730system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles 731system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles 732system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles 733system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles 734system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses 735system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses 736system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses 737system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses 738system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses 739system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses 740system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses 741system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses 742system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses 743system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency 745system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency 747system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency 748system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency 749system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency 750system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency 751system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency 752system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency 753system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency 754system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 755system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 756system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 757system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 758system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 759system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 760system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 761system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements 762system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use 763system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks. 764system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks. 765system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks. 766system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit. 767system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor 768system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy 769system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy 770system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 771system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 772system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 773system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 774system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 775system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses 776system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses 777system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits 778system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits 779system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits 780system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits 781system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits 782system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits 783system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses 784system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses 785system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses 786system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses 787system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses 788system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses 789system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles 790system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles 791system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles 792system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles 793system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles 794system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles 795system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses) 796system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses) 797system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses 798system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses 799system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses 800system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses 801system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses 802system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses 804system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses 805system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses 806system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses 807system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency 808system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency 809system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency 810system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency 811system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency 812system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency 813system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 820system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 821system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks 822system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks 823system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses 824system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses 825system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses 826system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses 827system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses 828system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses 829system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles 830system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles 831system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles 832system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles 833system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles 834system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles 835system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses 836system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses 837system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses 838system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses 839system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses 840system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses 841system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency 842system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency 843system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency 844system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency 845system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency 846system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency 847system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
923system.cpu.icache.tags.replacements 994393 # number of replacements 924system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use 925system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks. 926system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks. 927system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks. 928system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit. 929system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor 930system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy 931system.cpu.icache.tags.occ_percent::total 0.996163 # Average percentage of cache occupancy 932system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 933system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 934system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 935system.cpu.icache.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id 936system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 937system.cpu.icache.tags.tag_accesses 10178850 # Number of tag accesses 938system.cpu.icache.tags.data_accesses 10178850 # Number of data accesses 939system.cpu.icache.ReadReq_hits::cpu.inst 8125717 # number of ReadReq hits 940system.cpu.icache.ReadReq_hits::total 8125717 # number of ReadReq hits 941system.cpu.icache.demand_hits::cpu.inst 8125717 # number of demand (read+write) hits 942system.cpu.icache.demand_hits::total 8125717 # number of demand (read+write) hits 943system.cpu.icache.overall_hits::cpu.inst 8125717 # number of overall hits 944system.cpu.icache.overall_hits::total 8125717 # number of overall hits 945system.cpu.icache.ReadReq_misses::cpu.inst 1058185 # number of ReadReq misses 946system.cpu.icache.ReadReq_misses::total 1058185 # number of ReadReq misses 947system.cpu.icache.demand_misses::cpu.inst 1058185 # number of demand (read+write) misses 948system.cpu.icache.demand_misses::total 1058185 # number of demand (read+write) misses 949system.cpu.icache.overall_misses::cpu.inst 1058185 # number of overall misses 950system.cpu.icache.overall_misses::total 1058185 # number of overall misses 951system.cpu.icache.ReadReq_miss_latency::cpu.inst 14693875503 # number of ReadReq miss cycles 952system.cpu.icache.ReadReq_miss_latency::total 14693875503 # number of ReadReq miss cycles 953system.cpu.icache.demand_miss_latency::cpu.inst 14693875503 # number of demand (read+write) miss cycles 954system.cpu.icache.demand_miss_latency::total 14693875503 # number of demand (read+write) miss cycles 955system.cpu.icache.overall_miss_latency::cpu.inst 14693875503 # number of overall miss cycles 956system.cpu.icache.overall_miss_latency::total 14693875503 # number of overall miss cycles 957system.cpu.icache.ReadReq_accesses::cpu.inst 9183902 # number of ReadReq accesses(hits+misses) 958system.cpu.icache.ReadReq_accesses::total 9183902 # number of ReadReq accesses(hits+misses) 959system.cpu.icache.demand_accesses::cpu.inst 9183902 # number of demand (read+write) accesses 960system.cpu.icache.demand_accesses::total 9183902 # number of demand (read+write) accesses 961system.cpu.icache.overall_accesses::cpu.inst 9183902 # number of overall (read+write) accesses 962system.cpu.icache.overall_accesses::total 9183902 # number of overall (read+write) accesses 963system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115222 # miss rate for ReadReq accesses 964system.cpu.icache.ReadReq_miss_rate::total 0.115222 # miss rate for ReadReq accesses 965system.cpu.icache.demand_miss_rate::cpu.inst 0.115222 # miss rate for demand accesses 966system.cpu.icache.demand_miss_rate::total 0.115222 # miss rate for demand accesses 967system.cpu.icache.overall_miss_rate::cpu.inst 0.115222 # miss rate for overall accesses 968system.cpu.icache.overall_miss_rate::total 0.115222 # miss rate for overall accesses 969system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069 # average ReadReq miss latency 970system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069 # average ReadReq miss latency 971system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency 972system.cpu.icache.demand_avg_miss_latency::total 13885.923069 # average overall miss latency 973system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency 974system.cpu.icache.overall_avg_miss_latency::total 13885.923069 # average overall miss latency 975system.cpu.icache.blocked_cycles::no_mshrs 7023 # number of cycles access was blocked 976system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 977system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked 978system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 979system.cpu.icache.avg_blocked_cycles::no_mshrs 23.646465 # average number of cycles each access was blocked 980system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 981system.cpu.icache.fast_writes 0 # number of fast writes performed 982system.cpu.icache.cache_copies 0 # number of cache copies performed 983system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63237 # number of ReadReq MSHR hits 984system.cpu.icache.ReadReq_mshr_hits::total 63237 # number of ReadReq MSHR hits 985system.cpu.icache.demand_mshr_hits::cpu.inst 63237 # number of demand (read+write) MSHR hits 986system.cpu.icache.demand_mshr_hits::total 63237 # number of demand (read+write) MSHR hits 987system.cpu.icache.overall_mshr_hits::cpu.inst 63237 # number of overall MSHR hits 988system.cpu.icache.overall_mshr_hits::total 63237 # number of overall MSHR hits 989system.cpu.icache.ReadReq_mshr_misses::cpu.inst 994948 # number of ReadReq MSHR misses 990system.cpu.icache.ReadReq_mshr_misses::total 994948 # number of ReadReq MSHR misses 991system.cpu.icache.demand_mshr_misses::cpu.inst 994948 # number of demand (read+write) MSHR misses 992system.cpu.icache.demand_mshr_misses::total 994948 # number of demand (read+write) MSHR misses 993system.cpu.icache.overall_mshr_misses::cpu.inst 994948 # number of overall MSHR misses 994system.cpu.icache.overall_mshr_misses::total 994948 # number of overall MSHR misses 995system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12059629101 # number of ReadReq MSHR miss cycles 996system.cpu.icache.ReadReq_mshr_miss_latency::total 12059629101 # number of ReadReq MSHR miss cycles 997system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12059629101 # number of demand (read+write) MSHR miss cycles 998system.cpu.icache.demand_mshr_miss_latency::total 12059629101 # number of demand (read+write) MSHR miss cycles 999system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12059629101 # number of overall MSHR miss cycles 1000system.cpu.icache.overall_mshr_miss_latency::total 12059629101 # number of overall MSHR miss cycles 1001system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for ReadReq accesses 1002system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108336 # mshr miss rate for ReadReq accesses 1003system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for demand accesses 1004system.cpu.icache.demand_mshr_miss_rate::total 0.108336 # mshr miss rate for demand accesses 1005system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for overall accesses 1006system.cpu.icache.overall_mshr_miss_rate::total 0.108336 # mshr miss rate for overall accesses 1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704 # average ReadReq mshr miss latency 1008system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704 # average ReadReq mshr miss latency 1009system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency 1010system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency 1011system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency 1012system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency 1013system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1014system.cpu.itb_walker_cache.tags.replacements 14092 # number of replacements 1015system.cpu.itb_walker_cache.tags.tagsinuse 6.014059 # Cycle average of tags in use 1016system.cpu.itb_walker_cache.tags.total_refs 26262 # Total number of references to valid blocks. 1017system.cpu.itb_walker_cache.tags.sampled_refs 14107 # Sample count of references to valid blocks. 1018system.cpu.itb_walker_cache.tags.avg_refs 1.861629 # Average number of references to valid blocks. 1019system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000 # Cycle when the warmup percentage was hit. 1020system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.014059 # Average occupied blocks per requestor 1021system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375879 # Average percentage of cache occupancy 1022system.cpu.itb_walker_cache.tags.occ_percent::total 0.375879 # Average percentage of cache occupancy 1023system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 1024system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1025system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 1026system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 1027system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 1028system.cpu.itb_walker_cache.tags.tag_accesses 97491 # Number of tag accesses 1029system.cpu.itb_walker_cache.tags.data_accesses 97491 # Number of data accesses 1030system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26263 # number of ReadReq hits 1031system.cpu.itb_walker_cache.ReadReq_hits::total 26263 # number of ReadReq hits 1032system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1033system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 1034system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26265 # number of demand (read+write) hits 1035system.cpu.itb_walker_cache.demand_hits::total 26265 # number of demand (read+write) hits 1036system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26265 # number of overall hits 1037system.cpu.itb_walker_cache.overall_hits::total 26265 # number of overall hits 1038system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14987 # number of ReadReq misses 1039system.cpu.itb_walker_cache.ReadReq_misses::total 14987 # number of ReadReq misses 1040system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14987 # number of demand (read+write) misses 1041system.cpu.itb_walker_cache.demand_misses::total 14987 # number of demand (read+write) misses 1042system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14987 # number of overall misses 1043system.cpu.itb_walker_cache.overall_misses::total 14987 # number of overall misses 1044system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 174073497 # number of ReadReq miss cycles 1045system.cpu.itb_walker_cache.ReadReq_miss_latency::total 174073497 # number of ReadReq miss cycles 1046system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174073497 # number of demand (read+write) miss cycles 1047system.cpu.itb_walker_cache.demand_miss_latency::total 174073497 # number of demand (read+write) miss cycles 1048system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174073497 # number of overall miss cycles 1049system.cpu.itb_walker_cache.overall_miss_latency::total 174073497 # number of overall miss cycles 1050system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41250 # number of ReadReq accesses(hits+misses) 1051system.cpu.itb_walker_cache.ReadReq_accesses::total 41250 # number of ReadReq accesses(hits+misses) 1052system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1053system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 1054system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41252 # number of demand (read+write) accesses 1055system.cpu.itb_walker_cache.demand_accesses::total 41252 # number of demand (read+write) accesses 1056system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41252 # number of overall (read+write) accesses 1057system.cpu.itb_walker_cache.overall_accesses::total 41252 # number of overall (read+write) accesses 1058system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363321 # miss rate for ReadReq accesses 1059system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363321 # miss rate for ReadReq accesses 1060system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363304 # miss rate for demand accesses 1061system.cpu.itb_walker_cache.demand_miss_rate::total 0.363304 # miss rate for demand accesses 1062system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363304 # miss rate for overall accesses 1063system.cpu.itb_walker_cache.overall_miss_rate::total 0.363304 # miss rate for overall accesses 1064system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104 # average ReadReq miss latency 1065system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104 # average ReadReq miss latency 1066system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency 1067system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104 # average overall miss latency 1068system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency 1069system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104 # average overall miss latency 1070system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1077system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 1078system.cpu.itb_walker_cache.writebacks::writebacks 3303 # number of writebacks 1079system.cpu.itb_walker_cache.writebacks::total 3303 # number of writebacks 1080system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14987 # number of ReadReq MSHR misses 1081system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14987 # number of ReadReq MSHR misses 1082system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14987 # number of demand (read+write) MSHR misses 1083system.cpu.itb_walker_cache.demand_mshr_misses::total 14987 # number of demand (read+write) MSHR misses 1084system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14987 # number of overall MSHR misses 1085system.cpu.itb_walker_cache.overall_mshr_misses::total 14987 # number of overall MSHR misses 1086system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 144083525 # number of ReadReq MSHR miss cycles 1087system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144083525 # number of ReadReq MSHR miss cycles 1088system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144083525 # number of demand (read+write) MSHR miss cycles 1089system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144083525 # number of demand (read+write) MSHR miss cycles 1090system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144083525 # number of overall MSHR miss cycles 1091system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144083525 # number of overall MSHR miss cycles 1092system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363321 # mshr miss rate for ReadReq accesses 1093system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363321 # mshr miss rate for ReadReq accesses 1094system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for demand accesses 1095system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363304 # mshr miss rate for demand accesses 1096system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for overall accesses 1097system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses 1098system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency 1099system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency 1100system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency 1101system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency 1102system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency 1103system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency 1104system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate	848system.cpu.icache.tags.replacements 994393 # number of replacements 849system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use 850system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks. 851system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks. 852system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks. 853system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit. 854system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor 855system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy 856system.cpu.icache.tags.occ_percent::total 0.996163 # Average percentage of cache occupancy 857system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 858system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 859system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 860system.cpu.icache.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id 861system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 862system.cpu.icache.tags.tag_accesses 10178850 # Number of tag accesses 863system.cpu.icache.tags.data_accesses 10178850 # Number of data accesses 864system.cpu.icache.ReadReq_hits::cpu.inst 8125717 # number of ReadReq hits 865system.cpu.icache.ReadReq_hits::total 8125717 # number of ReadReq hits 866system.cpu.icache.demand_hits::cpu.inst 8125717 # number of demand (read+write) hits 867system.cpu.icache.demand_hits::total 8125717 # number of demand (read+write) hits 868system.cpu.icache.overall_hits::cpu.inst 8125717 # number of overall hits 869system.cpu.icache.overall_hits::total 8125717 # number of overall hits 870system.cpu.icache.ReadReq_misses::cpu.inst 1058185 # number of ReadReq misses 871system.cpu.icache.ReadReq_misses::total 1058185 # number of ReadReq misses 872system.cpu.icache.demand_misses::cpu.inst 1058185 # number of demand (read+write) misses 873system.cpu.icache.demand_misses::total 1058185 # number of demand (read+write) misses 874system.cpu.icache.overall_misses::cpu.inst 1058185 # number of overall misses 875system.cpu.icache.overall_misses::total 1058185 # number of overall misses 876system.cpu.icache.ReadReq_miss_latency::cpu.inst 14693875503 # number of ReadReq miss cycles 877system.cpu.icache.ReadReq_miss_latency::total 14693875503 # number of ReadReq miss cycles 878system.cpu.icache.demand_miss_latency::cpu.inst 14693875503 # number of demand (read+write) miss cycles 879system.cpu.icache.demand_miss_latency::total 14693875503 # number of demand (read+write) miss cycles 880system.cpu.icache.overall_miss_latency::cpu.inst 14693875503 # number of overall miss cycles 881system.cpu.icache.overall_miss_latency::total 14693875503 # number of overall miss cycles 882system.cpu.icache.ReadReq_accesses::cpu.inst 9183902 # number of ReadReq accesses(hits+misses) 883system.cpu.icache.ReadReq_accesses::total 9183902 # number of ReadReq accesses(hits+misses) 884system.cpu.icache.demand_accesses::cpu.inst 9183902 # number of demand (read+write) accesses 885system.cpu.icache.demand_accesses::total 9183902 # number of demand (read+write) accesses 886system.cpu.icache.overall_accesses::cpu.inst 9183902 # number of overall (read+write) accesses 887system.cpu.icache.overall_accesses::total 9183902 # number of overall (read+write) accesses 888system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115222 # miss rate for ReadReq accesses 889system.cpu.icache.ReadReq_miss_rate::total 0.115222 # miss rate for ReadReq accesses 890system.cpu.icache.demand_miss_rate::cpu.inst 0.115222 # miss rate for demand accesses 891system.cpu.icache.demand_miss_rate::total 0.115222 # miss rate for demand accesses 892system.cpu.icache.overall_miss_rate::cpu.inst 0.115222 # miss rate for overall accesses 893system.cpu.icache.overall_miss_rate::total 0.115222 # miss rate for overall accesses 894system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069 # average ReadReq miss latency 895system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069 # average ReadReq miss latency 896system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency 897system.cpu.icache.demand_avg_miss_latency::total 13885.923069 # average overall miss latency 898system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency 899system.cpu.icache.overall_avg_miss_latency::total 13885.923069 # average overall miss latency 900system.cpu.icache.blocked_cycles::no_mshrs 7023 # number of cycles access was blocked 901system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 902system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked 903system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 904system.cpu.icache.avg_blocked_cycles::no_mshrs 23.646465 # average number of cycles each access was blocked 905system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 906system.cpu.icache.fast_writes 0 # number of fast writes performed 907system.cpu.icache.cache_copies 0 # number of cache copies performed 908system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63237 # number of ReadReq MSHR hits 909system.cpu.icache.ReadReq_mshr_hits::total 63237 # number of ReadReq MSHR hits 910system.cpu.icache.demand_mshr_hits::cpu.inst 63237 # number of demand (read+write) MSHR hits 911system.cpu.icache.demand_mshr_hits::total 63237 # number of demand (read+write) MSHR hits 912system.cpu.icache.overall_mshr_hits::cpu.inst 63237 # number of overall MSHR hits 913system.cpu.icache.overall_mshr_hits::total 63237 # number of overall MSHR hits 914system.cpu.icache.ReadReq_mshr_misses::cpu.inst 994948 # number of ReadReq MSHR misses 915system.cpu.icache.ReadReq_mshr_misses::total 994948 # number of ReadReq MSHR misses 916system.cpu.icache.demand_mshr_misses::cpu.inst 994948 # number of demand (read+write) MSHR misses 917system.cpu.icache.demand_mshr_misses::total 994948 # number of demand (read+write) MSHR misses 918system.cpu.icache.overall_mshr_misses::cpu.inst 994948 # number of overall MSHR misses 919system.cpu.icache.overall_mshr_misses::total 994948 # number of overall MSHR misses 920system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12059629101 # number of ReadReq MSHR miss cycles 921system.cpu.icache.ReadReq_mshr_miss_latency::total 12059629101 # number of ReadReq MSHR miss cycles 922system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12059629101 # number of demand (read+write) MSHR miss cycles 923system.cpu.icache.demand_mshr_miss_latency::total 12059629101 # number of demand (read+write) MSHR miss cycles 924system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12059629101 # number of overall MSHR miss cycles 925system.cpu.icache.overall_mshr_miss_latency::total 12059629101 # number of overall MSHR miss cycles 926system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for ReadReq accesses 927system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108336 # mshr miss rate for ReadReq accesses 928system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for demand accesses 929system.cpu.icache.demand_mshr_miss_rate::total 0.108336 # mshr miss rate for demand accesses 930system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for overall accesses 931system.cpu.icache.overall_mshr_miss_rate::total 0.108336 # mshr miss rate for overall accesses 932system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704 # average ReadReq mshr miss latency 933system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704 # average ReadReq mshr miss latency 934system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency 935system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency 936system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency 937system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency 938system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 939system.cpu.itb_walker_cache.tags.replacements 14092 # number of replacements 940system.cpu.itb_walker_cache.tags.tagsinuse 6.014059 # Cycle average of tags in use 941system.cpu.itb_walker_cache.tags.total_refs 26262 # Total number of references to valid blocks. 942system.cpu.itb_walker_cache.tags.sampled_refs 14107 # Sample count of references to valid blocks. 943system.cpu.itb_walker_cache.tags.avg_refs 1.861629 # Average number of references to valid blocks. 944system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000 # Cycle when the warmup percentage was hit. 945system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.014059 # Average occupied blocks per requestor 946system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375879 # Average percentage of cache occupancy 947system.cpu.itb_walker_cache.tags.occ_percent::total 0.375879 # Average percentage of cache occupancy 948system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 949system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 950system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 951system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 952system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 953system.cpu.itb_walker_cache.tags.tag_accesses 97491 # Number of tag accesses 954system.cpu.itb_walker_cache.tags.data_accesses 97491 # Number of data accesses 955system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26263 # number of ReadReq hits 956system.cpu.itb_walker_cache.ReadReq_hits::total 26263 # number of ReadReq hits 957system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 958system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 959system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26265 # number of demand (read+write) hits 960system.cpu.itb_walker_cache.demand_hits::total 26265 # number of demand (read+write) hits 961system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26265 # number of overall hits 962system.cpu.itb_walker_cache.overall_hits::total 26265 # number of overall hits 963system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14987 # number of ReadReq misses 964system.cpu.itb_walker_cache.ReadReq_misses::total 14987 # number of ReadReq misses 965system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14987 # number of demand (read+write) misses 966system.cpu.itb_walker_cache.demand_misses::total 14987 # number of demand (read+write) misses 967system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14987 # number of overall misses 968system.cpu.itb_walker_cache.overall_misses::total 14987 # number of overall misses 969system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 174073497 # number of ReadReq miss cycles 970system.cpu.itb_walker_cache.ReadReq_miss_latency::total 174073497 # number of ReadReq miss cycles 971system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174073497 # number of demand (read+write) miss cycles 972system.cpu.itb_walker_cache.demand_miss_latency::total 174073497 # number of demand (read+write) miss cycles 973system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174073497 # number of overall miss cycles 974system.cpu.itb_walker_cache.overall_miss_latency::total 174073497 # number of overall miss cycles 975system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41250 # number of ReadReq accesses(hits+misses) 976system.cpu.itb_walker_cache.ReadReq_accesses::total 41250 # number of ReadReq accesses(hits+misses) 977system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 978system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 979system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41252 # number of demand (read+write) accesses 980system.cpu.itb_walker_cache.demand_accesses::total 41252 # number of demand (read+write) accesses 981system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41252 # number of overall (read+write) accesses 982system.cpu.itb_walker_cache.overall_accesses::total 41252 # number of overall (read+write) accesses 983system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363321 # miss rate for ReadReq accesses 984system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363321 # miss rate for ReadReq accesses 985system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363304 # miss rate for demand accesses 986system.cpu.itb_walker_cache.demand_miss_rate::total 0.363304 # miss rate for demand accesses 987system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363304 # miss rate for overall accesses 988system.cpu.itb_walker_cache.overall_miss_rate::total 0.363304 # miss rate for overall accesses 989system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104 # average ReadReq miss latency 990system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104 # average ReadReq miss latency 991system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency 992system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104 # average overall miss latency 993system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency 994system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104 # average overall miss latency 995system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 996system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 997system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 998system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 999system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1000system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1001system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1002system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 1003system.cpu.itb_walker_cache.writebacks::writebacks 3303 # number of writebacks 1004system.cpu.itb_walker_cache.writebacks::total 3303 # number of writebacks 1005system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14987 # number of ReadReq MSHR misses 1006system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14987 # number of ReadReq MSHR misses 1007system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14987 # number of demand (read+write) MSHR misses 1008system.cpu.itb_walker_cache.demand_mshr_misses::total 14987 # number of demand (read+write) MSHR misses 1009system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14987 # number of overall MSHR misses 1010system.cpu.itb_walker_cache.overall_mshr_misses::total 14987 # number of overall MSHR misses 1011system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 144083525 # number of ReadReq MSHR miss cycles 1012system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144083525 # number of ReadReq MSHR miss cycles 1013system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144083525 # number of demand (read+write) MSHR miss cycles 1014system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144083525 # number of demand (read+write) MSHR miss cycles 1015system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144083525 # number of overall MSHR miss cycles 1016system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144083525 # number of overall MSHR miss cycles 1017system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363321 # mshr miss rate for ReadReq accesses 1018system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363321 # mshr miss rate for ReadReq accesses 1019system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for demand accesses 1020system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363304 # mshr miss rate for demand accesses 1021system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for overall accesses 1022system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses 1023system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency 1024system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency 1025system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency 1026system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency 1027system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency 1028system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency 1029system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1105system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements 1106system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use 1107system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks. 1108system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks. 1109system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks. 1110system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit. 1111system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor 1112system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy 1113system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy 1114system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 1115system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 1116system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 1117system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 1118system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 1119system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses 1120system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses 1121system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits 1122system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits 1123system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits 1124system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits 1125system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits 1126system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits 1127system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses 1128system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses 1129system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses 1130system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses 1131system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses 1132system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses 1133system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles 1134system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles 1135system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles 1136system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles 1137system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles 1138system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles 1139system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses) 1140system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses) 1141system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses 1142system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses 1143system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses 1144system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses 1145system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses 1146system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses 1147system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses 1148system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses 1149system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses 1150system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses 1151system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency 1152system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency 1153system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency 1154system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency 1155system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency 1156system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency 1157system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1158system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1159system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1160system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1161system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1162system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1163system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1164system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 1165system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks 1166system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks 1167system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses 1168system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses 1169system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses 1170system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses 1171system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses 1172system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses 1173system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles 1174system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles 1175system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles 1176system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles 1177system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles 1178system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles 1179system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses 1180system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses 1181system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses 1182system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses 1183system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses 1184system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses 1185system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency 1186system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency 1187system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency 1188system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency 1189system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency 1190system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency 1191system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1192system.cpu.dcache.tags.replacements 1657683 # number of replacements 1193system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use 1194system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks. 1195system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks. 1196system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks. 1197system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. 1198system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor 1199system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy 1200system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy 1201system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1202system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 1203system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 1204system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 1205system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1206system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses 1207system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses 1208system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits 1209system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits 1210system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits 1211system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits 1212system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits 1213system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits 1214system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits 1215system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits 1216system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits 1217system.cpu.dcache.overall_hits::total 19128334 # number of overall hits 1218system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses 1219system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses 1220system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses 1221system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses 1222system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses 1223system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses 1224system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses 1225system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses 1226system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses 1227system.cpu.dcache.overall_misses::total 2535648 # number of overall misses 1228system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles 1229system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles 1230system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles 1231system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles 1232system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles 1233system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles 1234system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles 1235system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles 1236system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses) 1237system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses) 1238system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses) 1239system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses) 1240system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses) 1241system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses) 1242system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses 1243system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses 1244system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses 1245system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses 1246system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses 1247system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses 1248system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses 1249system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses 1250system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses 1251system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses 1252system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses 1253system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses 1254system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses 1255system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses 1256system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency 1257system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency 1258system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency 1259system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency 1260system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency 1261system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency 1262system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency 1263system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency 1264system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked 1265system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1266system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked 1267system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1268system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked 1269system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1270system.cpu.dcache.fast_writes 0 # number of fast writes performed 1271system.cpu.dcache.cache_copies 0 # number of cache copies performed 1272system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks 1273system.cpu.dcache.writebacks::total 1559289 # number of writebacks 1274system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits 1275system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits 1276system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits 1277system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits 1278system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits 1279system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits 1280system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits 1281system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits 1282system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses 1283system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses 1284system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses 1285system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses 1286system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses 1287system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses 1288system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses 1289system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses 1290system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses 1291system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses 1292system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles 1293system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles 1294system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles 1295system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles 1296system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles 1297system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles 1298system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles 1299system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles 1300system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles 1301system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles 1302system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles 1303system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles 1304system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles 1305system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles 1306system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles 1307system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles 1308system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses 1309system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses 1310system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses 1311system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses 1312system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses 1313system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses 1314system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses 1315system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses 1316system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses 1317system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses 1318system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency 1319system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency 1320system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency 1321system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency 1322system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency 1323system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency 1324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency 1325system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency 1326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency 1327system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency 1328system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1329system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1330system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1331system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1332system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1333system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1334system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1335system.cpu.l2cache.tags.replacements 113085 # number of replacements 1336system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use 1337system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks. 1338system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks. 1339system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks. 1340system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1341system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor 1342system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor 1343system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143343 # Average occupied blocks per requestor 1344system.cpu.l2cache.tags.occ_blocks::cpu.inst 3264.453296 # Average occupied blocks per requestor 1345system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488 # Average occupied blocks per requestor 1346system.cpu.l2cache.tags.occ_percent::writebacks 0.769536 # Average percentage of cache occupancy 1347system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy 1348system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1349system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049812 # Average percentage of cache occupancy 1350system.cpu.l2cache.tags.occ_percent::cpu.data 0.169353 # Average percentage of cache occupancy 1351system.cpu.l2cache.tags.occ_percent::total 0.989050 # Average percentage of cache occupancy 1352system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id 1353system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 1354system.cpu.l2cache.tags.age_task_id_blocks_1024::1 634 # Occupied blocks per task id 1355system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id 1356system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5793 # Occupied blocks per task id 1357system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54091 # Occupied blocks per task id 1358system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id 1359system.cpu.l2cache.tags.tag_accesses 35031209 # Number of tag accesses 1360system.cpu.l2cache.tags.data_accesses 35031209 # Number of data accesses 1361system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68532 # number of ReadReq hits 1362system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12501 # number of ReadReq hits 1363system.cpu.l2cache.ReadReq_hits::cpu.inst 978548 # number of ReadReq hits 1364system.cpu.l2cache.ReadReq_hits::cpu.data 1334624 # number of ReadReq hits 1365system.cpu.l2cache.ReadReq_hits::total 2394205 # number of ReadReq hits 1366system.cpu.l2cache.Writeback_hits::writebacks 1584468 # number of Writeback hits 1367system.cpu.l2cache.Writeback_hits::total 1584468 # number of Writeback hits 1368system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits 1369system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits 1370system.cpu.l2cache.ReadExReq_hits::cpu.data 153669 # number of ReadExReq hits 1371system.cpu.l2cache.ReadExReq_hits::total 153669 # number of ReadExReq hits 1372system.cpu.l2cache.demand_hits::cpu.dtb.walker 68532 # number of demand (read+write) hits 1373system.cpu.l2cache.demand_hits::cpu.itb.walker 12501 # number of demand (read+write) hits 1374system.cpu.l2cache.demand_hits::cpu.inst 978548 # number of demand (read+write) hits 1375system.cpu.l2cache.demand_hits::cpu.data 1488293 # number of demand (read+write) hits 1376system.cpu.l2cache.demand_hits::total 2547874 # number of demand (read+write) hits 1377system.cpu.l2cache.overall_hits::cpu.dtb.walker 68532 # number of overall hits 1378system.cpu.l2cache.overall_hits::cpu.itb.walker 12501 # number of overall hits 1379system.cpu.l2cache.overall_hits::cpu.inst 978548 # number of overall hits 1380system.cpu.l2cache.overall_hits::cpu.data 1488293 # number of overall hits 1381system.cpu.l2cache.overall_hits::total 2547874 # number of overall hits 1382system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 75 # number of ReadReq misses 1383system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 1384system.cpu.l2cache.ReadReq_misses::cpu.inst 16312 # number of ReadReq misses 1385system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses 1386system.cpu.l2cache.ReadReq_misses::total 52269 # number of ReadReq misses 1387system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses 1388system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses 1389system.cpu.l2cache.ReadExReq_misses::cpu.data 133393 # number of ReadExReq misses 1390system.cpu.l2cache.ReadExReq_misses::total 133393 # number of ReadExReq misses 1391system.cpu.l2cache.demand_misses::cpu.dtb.walker 75 # number of demand (read+write) misses 1392system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 1393system.cpu.l2cache.demand_misses::cpu.inst 16312 # number of demand (read+write) misses 1394system.cpu.l2cache.demand_misses::cpu.data 169268 # number of demand (read+write) misses 1395system.cpu.l2cache.demand_misses::total 185662 # number of demand (read+write) misses 1396system.cpu.l2cache.overall_misses::cpu.dtb.walker 75 # number of overall misses 1397system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 1398system.cpu.l2cache.overall_misses::cpu.inst 16312 # number of overall misses 1399system.cpu.l2cache.overall_misses::cpu.data 169268 # number of overall misses 1400system.cpu.l2cache.overall_misses::total 185662 # number of overall misses 1401system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6508500 # number of ReadReq miss cycles 1402system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 560500 # number of ReadReq miss cycles 1403system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1253827000 # number of ReadReq miss cycles 1404system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2884413497 # number of ReadReq miss cycles 1405system.cpu.l2cache.ReadReq_miss_latency::total 4145309497 # number of ReadReq miss cycles 1406system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16150808 # number of UpgradeReq miss cycles 1407system.cpu.l2cache.UpgradeReq_miss_latency::total 16150808 # number of UpgradeReq miss cycles 1408system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9313802457 # number of ReadExReq miss cycles 1409system.cpu.l2cache.ReadExReq_miss_latency::total 9313802457 # number of ReadExReq miss cycles 1410system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6508500 # number of demand (read+write) miss cycles 1411system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 560500 # number of demand (read+write) miss cycles 1412system.cpu.l2cache.demand_miss_latency::cpu.inst 1253827000 # number of demand (read+write) miss cycles 1413system.cpu.l2cache.demand_miss_latency::cpu.data 12198215954 # number of demand (read+write) miss cycles 1414system.cpu.l2cache.demand_miss_latency::total 13459111954 # number of demand (read+write) miss cycles 1415system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6508500 # number of overall miss cycles 1416system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 560500 # number of overall miss cycles 1417system.cpu.l2cache.overall_miss_latency::cpu.inst 1253827000 # number of overall miss cycles 1418system.cpu.l2cache.overall_miss_latency::cpu.data 12198215954 # number of overall miss cycles 1419system.cpu.l2cache.overall_miss_latency::total 13459111954 # number of overall miss cycles 1420system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68607 # number of ReadReq accesses(hits+misses) 1421system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12508 # number of ReadReq accesses(hits+misses) 1422system.cpu.l2cache.ReadReq_accesses::cpu.inst 994860 # number of ReadReq accesses(hits+misses) 1423system.cpu.l2cache.ReadReq_accesses::cpu.data 1370499 # number of ReadReq accesses(hits+misses) 1424system.cpu.l2cache.ReadReq_accesses::total 2446474 # number of ReadReq accesses(hits+misses) 1425system.cpu.l2cache.Writeback_accesses::writebacks 1584468 # number of Writeback accesses(hits+misses) 1426system.cpu.l2cache.Writeback_accesses::total 1584468 # number of Writeback accesses(hits+misses) 1427system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1753 # number of UpgradeReq accesses(hits+misses) 1428system.cpu.l2cache.UpgradeReq_accesses::total 1753 # number of UpgradeReq accesses(hits+misses) 1429system.cpu.l2cache.ReadExReq_accesses::cpu.data 287062 # number of ReadExReq accesses(hits+misses) 1430system.cpu.l2cache.ReadExReq_accesses::total 287062 # number of ReadExReq accesses(hits+misses) 1431system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68607 # number of demand (read+write) accesses 1432system.cpu.l2cache.demand_accesses::cpu.itb.walker 12508 # number of demand (read+write) accesses 1433system.cpu.l2cache.demand_accesses::cpu.inst 994860 # number of demand (read+write) accesses 1434system.cpu.l2cache.demand_accesses::cpu.data 1657561 # number of demand (read+write) accesses 1435system.cpu.l2cache.demand_accesses::total 2733536 # number of demand (read+write) accesses 1436system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68607 # number of overall (read+write) accesses 1437system.cpu.l2cache.overall_accesses::cpu.itb.walker 12508 # number of overall (read+write) accesses 1438system.cpu.l2cache.overall_accesses::cpu.inst 994860 # number of overall (read+write) accesses 1439system.cpu.l2cache.overall_accesses::cpu.data 1657561 # number of overall (read+write) accesses 1440system.cpu.l2cache.overall_accesses::total 2733536 # number of overall (read+write) accesses 1441system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001093 # miss rate for ReadReq accesses 1442system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000560 # miss rate for ReadReq accesses 1443system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016396 # miss rate for ReadReq accesses 1444system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026177 # miss rate for ReadReq accesses 1445system.cpu.l2cache.ReadReq_miss_rate::total 0.021365 # miss rate for ReadReq accesses 1446system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823731 # miss rate for UpgradeReq accesses 1447system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823731 # miss rate for UpgradeReq accesses 1448system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464684 # miss rate for ReadExReq accesses 1449system.cpu.l2cache.ReadExReq_miss_rate::total 0.464684 # miss rate for ReadExReq accesses 1450system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001093 # miss rate for demand accesses 1451system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000560 # miss rate for demand accesses 1452system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016396 # miss rate for demand accesses 1453system.cpu.l2cache.demand_miss_rate::cpu.data 0.102119 # miss rate for demand accesses 1454system.cpu.l2cache.demand_miss_rate::total 0.067920 # miss rate for demand accesses 1455system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001093 # miss rate for overall accesses 1456system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000560 # miss rate for overall accesses 1457system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016396 # miss rate for overall accesses 1458system.cpu.l2cache.overall_miss_rate::cpu.data 0.102119 # miss rate for overall accesses 1459system.cpu.l2cache.overall_miss_rate::total 0.067920 # miss rate for overall accesses 1460system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86780 # average ReadReq miss latency 1461system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571 # average ReadReq miss latency 1462system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879 # average ReadReq miss latency 1463system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80401.769951 # average ReadReq miss latency 1464system.cpu.l2cache.ReadReq_avg_miss_latency::total 79307.227936 # average ReadReq miss latency 1465system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11184.770083 # average UpgradeReq miss latency 1466system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11184.770083 # average UpgradeReq miss latency 1467system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69822.272960 # average ReadExReq miss latency 1468system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69822.272960 # average ReadExReq miss latency 1469system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency 1470system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency 1471system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency 1472system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency 1473system.cpu.l2cache.demand_avg_miss_latency::total 72492.550732 # average overall miss latency 1474system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency 1475system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency 1476system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency 1477system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency 1478system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732 # average overall miss latency 1479system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1480system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1481system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1482system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1483system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1484system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1485system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1486system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1487system.cpu.l2cache.writebacks::writebacks 103196 # number of writebacks 1488system.cpu.l2cache.writebacks::total 103196 # number of writebacks 1489system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1490system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1491system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1492system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1493system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1494system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 1495system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1496system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1497system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits 1498system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 75 # number of ReadReq MSHR misses 1499system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses 1500system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16310 # number of ReadReq MSHR misses 1501system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35874 # number of ReadReq MSHR misses 1502system.cpu.l2cache.ReadReq_mshr_misses::total 52266 # number of ReadReq MSHR misses 1503system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses 1504system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses 1505system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133393 # number of ReadExReq MSHR misses 1506system.cpu.l2cache.ReadExReq_mshr_misses::total 133393 # number of ReadExReq MSHR misses 1507system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 75 # number of demand (read+write) MSHR misses 1508system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 1509system.cpu.l2cache.demand_mshr_misses::cpu.inst 16310 # number of demand (read+write) MSHR misses 1510system.cpu.l2cache.demand_mshr_misses::cpu.data 169267 # number of demand (read+write) MSHR misses 1511system.cpu.l2cache.demand_mshr_misses::total 185659 # number of demand (read+write) MSHR misses 1512system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 75 # number of overall MSHR misses 1513system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1514system.cpu.l2cache.overall_mshr_misses::cpu.inst 16310 # number of overall MSHR misses 1515system.cpu.l2cache.overall_mshr_misses::cpu.data 169267 # number of overall MSHR misses 1516system.cpu.l2cache.overall_mshr_misses::total 185659 # number of overall MSHR misses 1517system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5579000 # number of ReadReq MSHR miss cycles 1518system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 473000 # number of ReadReq MSHR miss cycles 1519system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049198000 # number of ReadReq MSHR miss cycles 1520system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2439336749 # number of ReadReq MSHR miss cycles 1521system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3494586749 # number of ReadReq MSHR miss cycles 1522system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14472940 # number of UpgradeReq MSHR miss cycles 1523system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14472940 # number of UpgradeReq MSHR miss cycles 1524system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7638617543 # number of ReadExReq MSHR miss cycles 1525system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7638617543 # number of ReadExReq MSHR miss cycles 1526system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5579000 # number of demand (read+write) MSHR miss cycles 1527system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 473000 # number of demand (read+write) MSHR miss cycles 1528system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049198000 # number of demand (read+write) MSHR miss cycles 1529system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10077954292 # number of demand (read+write) MSHR miss cycles 1530system.cpu.l2cache.demand_mshr_miss_latency::total 11133204292 # number of demand (read+write) MSHR miss cycles 1531system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5579000 # number of overall MSHR miss cycles 1532system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 473000 # number of overall MSHR miss cycles 1533system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049198000 # number of overall MSHR miss cycles 1534system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10077954292 # number of overall MSHR miss cycles 1535system.cpu.l2cache.overall_mshr_miss_latency::total 11133204292 # number of overall MSHR miss cycles 1536system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275584000 # number of ReadReq MSHR uncacheable cycles 1537system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275584000 # number of ReadReq MSHR uncacheable cycles 1538system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397149000 # number of WriteReq MSHR uncacheable cycles 1539system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397149000 # number of WriteReq MSHR uncacheable cycles 1540system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672733000 # number of overall MSHR uncacheable cycles 1541system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672733000 # number of overall MSHR uncacheable cycles 1542system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for ReadReq accesses 1543system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for ReadReq accesses 1544system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for ReadReq accesses 1545system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026176 # mshr miss rate for ReadReq accesses 1546system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021364 # mshr miss rate for ReadReq accesses 1547system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823731 # mshr miss rate for UpgradeReq accesses 1548system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823731 # mshr miss rate for UpgradeReq accesses 1549system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464684 # mshr miss rate for ReadExReq accesses 1550system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464684 # mshr miss rate for ReadExReq accesses 1551system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for demand accesses 1552system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for demand accesses 1553system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for demand accesses 1554system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for demand accesses 1555system.cpu.l2cache.demand_mshr_miss_rate::total 0.067919 # mshr miss rate for demand accesses 1556system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for overall accesses 1557system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for overall accesses 1558system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for overall accesses 1559system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for overall accesses 1560system.cpu.l2cache.overall_mshr_miss_rate::total 0.067919 # mshr miss rate for overall accesses 1561system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average ReadReq mshr miss latency 1562system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average ReadReq mshr miss latency 1563system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116 # average ReadReq mshr miss latency 1564system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846 # average ReadReq mshr miss latency 1565system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687 # average ReadReq mshr miss latency 1566system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634 # average UpgradeReq mshr miss latency 1567system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634 # average UpgradeReq mshr miss latency 1568system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930 # average ReadExReq mshr miss latency 1569system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930 # average ReadExReq mshr miss latency 1570system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency 1571system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency 1572system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency 1573system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency 1574system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency 1575system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency 1576system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency 1577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency 1578system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency 1579system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency 1580system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1581system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1582system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1583system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1584system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1585system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1586system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate	1030system.cpu.l2cache.tags.replacements 113085 # number of replacements 1031system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use 1032system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks. 1033system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks. 1034system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks. 1035system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1036system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor 1037system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor 1038system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143343 # Average occupied blocks per requestor 1039system.cpu.l2cache.tags.occ_blocks::cpu.inst 3264.453296 # Average occupied blocks per requestor 1040system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488 # Average occupied blocks per requestor 1041system.cpu.l2cache.tags.occ_percent::writebacks 0.769536 # Average percentage of cache occupancy 1042system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy 1043system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1044system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049812 # Average percentage of cache occupancy 1045system.cpu.l2cache.tags.occ_percent::cpu.data 0.169353 # Average percentage of cache occupancy 1046system.cpu.l2cache.tags.occ_percent::total 0.989050 # Average percentage of cache occupancy 1047system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id 1048system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 1049system.cpu.l2cache.tags.age_task_id_blocks_1024::1 634 # Occupied blocks per task id 1050system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id 1051system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5793 # Occupied blocks per task id 1052system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54091 # Occupied blocks per task id 1053system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id 1054system.cpu.l2cache.tags.tag_accesses 35031209 # Number of tag accesses 1055system.cpu.l2cache.tags.data_accesses 35031209 # Number of data accesses 1056system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68532 # number of ReadReq hits 1057system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12501 # number of ReadReq hits 1058system.cpu.l2cache.ReadReq_hits::cpu.inst 978548 # number of ReadReq hits 1059system.cpu.l2cache.ReadReq_hits::cpu.data 1334624 # number of ReadReq hits 1060system.cpu.l2cache.ReadReq_hits::total 2394205 # number of ReadReq hits 1061system.cpu.l2cache.Writeback_hits::writebacks 1584468 # number of Writeback hits 1062system.cpu.l2cache.Writeback_hits::total 1584468 # number of Writeback hits 1063system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits 1064system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits 1065system.cpu.l2cache.ReadExReq_hits::cpu.data 153669 # number of ReadExReq hits 1066system.cpu.l2cache.ReadExReq_hits::total 153669 # number of ReadExReq hits 1067system.cpu.l2cache.demand_hits::cpu.dtb.walker 68532 # number of demand (read+write) hits 1068system.cpu.l2cache.demand_hits::cpu.itb.walker 12501 # number of demand (read+write) hits 1069system.cpu.l2cache.demand_hits::cpu.inst 978548 # number of demand (read+write) hits 1070system.cpu.l2cache.demand_hits::cpu.data 1488293 # number of demand (read+write) hits 1071system.cpu.l2cache.demand_hits::total 2547874 # number of demand (read+write) hits 1072system.cpu.l2cache.overall_hits::cpu.dtb.walker 68532 # number of overall hits 1073system.cpu.l2cache.overall_hits::cpu.itb.walker 12501 # number of overall hits 1074system.cpu.l2cache.overall_hits::cpu.inst 978548 # number of overall hits 1075system.cpu.l2cache.overall_hits::cpu.data 1488293 # number of overall hits 1076system.cpu.l2cache.overall_hits::total 2547874 # number of overall hits 1077system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 75 # number of ReadReq misses 1078system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 1079system.cpu.l2cache.ReadReq_misses::cpu.inst 16312 # number of ReadReq misses 1080system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses 1081system.cpu.l2cache.ReadReq_misses::total 52269 # number of ReadReq misses 1082system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses 1083system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses 1084system.cpu.l2cache.ReadExReq_misses::cpu.data 133393 # number of ReadExReq misses 1085system.cpu.l2cache.ReadExReq_misses::total 133393 # number of ReadExReq misses 1086system.cpu.l2cache.demand_misses::cpu.dtb.walker 75 # number of demand (read+write) misses 1087system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 1088system.cpu.l2cache.demand_misses::cpu.inst 16312 # number of demand (read+write) misses 1089system.cpu.l2cache.demand_misses::cpu.data 169268 # number of demand (read+write) misses 1090system.cpu.l2cache.demand_misses::total 185662 # number of demand (read+write) misses 1091system.cpu.l2cache.overall_misses::cpu.dtb.walker 75 # number of overall misses 1092system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 1093system.cpu.l2cache.overall_misses::cpu.inst 16312 # number of overall misses 1094system.cpu.l2cache.overall_misses::cpu.data 169268 # number of overall misses 1095system.cpu.l2cache.overall_misses::total 185662 # number of overall misses 1096system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6508500 # number of ReadReq miss cycles 1097system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 560500 # number of ReadReq miss cycles 1098system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1253827000 # number of ReadReq miss cycles 1099system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2884413497 # number of ReadReq miss cycles 1100system.cpu.l2cache.ReadReq_miss_latency::total 4145309497 # number of ReadReq miss cycles 1101system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16150808 # number of UpgradeReq miss cycles 1102system.cpu.l2cache.UpgradeReq_miss_latency::total 16150808 # number of UpgradeReq miss cycles 1103system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9313802457 # number of ReadExReq miss cycles 1104system.cpu.l2cache.ReadExReq_miss_latency::total 9313802457 # number of ReadExReq miss cycles 1105system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6508500 # number of demand (read+write) miss cycles 1106system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 560500 # number of demand (read+write) miss cycles 1107system.cpu.l2cache.demand_miss_latency::cpu.inst 1253827000 # number of demand (read+write) miss cycles 1108system.cpu.l2cache.demand_miss_latency::cpu.data 12198215954 # number of demand (read+write) miss cycles 1109system.cpu.l2cache.demand_miss_latency::total 13459111954 # number of demand (read+write) miss cycles 1110system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6508500 # number of overall miss cycles 1111system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 560500 # number of overall miss cycles 1112system.cpu.l2cache.overall_miss_latency::cpu.inst 1253827000 # number of overall miss cycles 1113system.cpu.l2cache.overall_miss_latency::cpu.data 12198215954 # number of overall miss cycles 1114system.cpu.l2cache.overall_miss_latency::total 13459111954 # number of overall miss cycles 1115system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68607 # number of ReadReq accesses(hits+misses) 1116system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12508 # number of ReadReq accesses(hits+misses) 1117system.cpu.l2cache.ReadReq_accesses::cpu.inst 994860 # number of ReadReq accesses(hits+misses) 1118system.cpu.l2cache.ReadReq_accesses::cpu.data 1370499 # number of ReadReq accesses(hits+misses) 1119system.cpu.l2cache.ReadReq_accesses::total 2446474 # number of ReadReq accesses(hits+misses) 1120system.cpu.l2cache.Writeback_accesses::writebacks 1584468 # number of Writeback accesses(hits+misses) 1121system.cpu.l2cache.Writeback_accesses::total 1584468 # number of Writeback accesses(hits+misses) 1122system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1753 # number of UpgradeReq accesses(hits+misses) 1123system.cpu.l2cache.UpgradeReq_accesses::total 1753 # number of UpgradeReq accesses(hits+misses) 1124system.cpu.l2cache.ReadExReq_accesses::cpu.data 287062 # number of ReadExReq accesses(hits+misses) 1125system.cpu.l2cache.ReadExReq_accesses::total 287062 # number of ReadExReq accesses(hits+misses) 1126system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68607 # number of demand (read+write) accesses 1127system.cpu.l2cache.demand_accesses::cpu.itb.walker 12508 # number of demand (read+write) accesses 1128system.cpu.l2cache.demand_accesses::cpu.inst 994860 # number of demand (read+write) accesses 1129system.cpu.l2cache.demand_accesses::cpu.data 1657561 # number of demand (read+write) accesses 1130system.cpu.l2cache.demand_accesses::total 2733536 # number of demand (read+write) accesses 1131system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68607 # number of overall (read+write) accesses 1132system.cpu.l2cache.overall_accesses::cpu.itb.walker 12508 # number of overall (read+write) accesses 1133system.cpu.l2cache.overall_accesses::cpu.inst 994860 # number of overall (read+write) accesses 1134system.cpu.l2cache.overall_accesses::cpu.data 1657561 # number of overall (read+write) accesses 1135system.cpu.l2cache.overall_accesses::total 2733536 # number of overall (read+write) accesses 1136system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001093 # miss rate for ReadReq accesses 1137system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000560 # miss rate for ReadReq accesses 1138system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016396 # miss rate for ReadReq accesses 1139system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026177 # miss rate for ReadReq accesses 1140system.cpu.l2cache.ReadReq_miss_rate::total 0.021365 # miss rate for ReadReq accesses 1141system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823731 # miss rate for UpgradeReq accesses 1142system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823731 # miss rate for UpgradeReq accesses 1143system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464684 # miss rate for ReadExReq accesses 1144system.cpu.l2cache.ReadExReq_miss_rate::total 0.464684 # miss rate for ReadExReq accesses 1145system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001093 # miss rate for demand accesses 1146system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000560 # miss rate for demand accesses 1147system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016396 # miss rate for demand accesses 1148system.cpu.l2cache.demand_miss_rate::cpu.data 0.102119 # miss rate for demand accesses 1149system.cpu.l2cache.demand_miss_rate::total 0.067920 # miss rate for demand accesses 1150system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001093 # miss rate for overall accesses 1151system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000560 # miss rate for overall accesses 1152system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016396 # miss rate for overall accesses 1153system.cpu.l2cache.overall_miss_rate::cpu.data 0.102119 # miss rate for overall accesses 1154system.cpu.l2cache.overall_miss_rate::total 0.067920 # miss rate for overall accesses 1155system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86780 # average ReadReq miss latency 1156system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571 # average ReadReq miss latency 1157system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879 # average ReadReq miss latency 1158system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80401.769951 # average ReadReq miss latency 1159system.cpu.l2cache.ReadReq_avg_miss_latency::total 79307.227936 # average ReadReq miss latency 1160system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11184.770083 # average UpgradeReq miss latency 1161system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11184.770083 # average UpgradeReq miss latency 1162system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69822.272960 # average ReadExReq miss latency 1163system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69822.272960 # average ReadExReq miss latency 1164system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency 1165system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency 1166system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency 1167system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency 1168system.cpu.l2cache.demand_avg_miss_latency::total 72492.550732 # average overall miss latency 1169system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency 1170system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency 1171system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency 1172system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency 1173system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732 # average overall miss latency 1174system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1175system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1176system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1177system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1178system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1179system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1180system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1181system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1182system.cpu.l2cache.writebacks::writebacks 103196 # number of writebacks 1183system.cpu.l2cache.writebacks::total 103196 # number of writebacks 1184system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1185system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1186system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1187system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1188system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1189system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 1190system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1191system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1192system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits 1193system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 75 # number of ReadReq MSHR misses 1194system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses 1195system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16310 # number of ReadReq MSHR misses 1196system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35874 # number of ReadReq MSHR misses 1197system.cpu.l2cache.ReadReq_mshr_misses::total 52266 # number of ReadReq MSHR misses 1198system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses 1199system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses 1200system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133393 # number of ReadExReq MSHR misses 1201system.cpu.l2cache.ReadExReq_mshr_misses::total 133393 # number of ReadExReq MSHR misses 1202system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 75 # number of demand (read+write) MSHR misses 1203system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 1204system.cpu.l2cache.demand_mshr_misses::cpu.inst 16310 # number of demand (read+write) MSHR misses 1205system.cpu.l2cache.demand_mshr_misses::cpu.data 169267 # number of demand (read+write) MSHR misses 1206system.cpu.l2cache.demand_mshr_misses::total 185659 # number of demand (read+write) MSHR misses 1207system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 75 # number of overall MSHR misses 1208system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1209system.cpu.l2cache.overall_mshr_misses::cpu.inst 16310 # number of overall MSHR misses 1210system.cpu.l2cache.overall_mshr_misses::cpu.data 169267 # number of overall MSHR misses 1211system.cpu.l2cache.overall_mshr_misses::total 185659 # number of overall MSHR misses 1212system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5579000 # number of ReadReq MSHR miss cycles 1213system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 473000 # number of ReadReq MSHR miss cycles 1214system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049198000 # number of ReadReq MSHR miss cycles 1215system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2439336749 # number of ReadReq MSHR miss cycles 1216system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3494586749 # number of ReadReq MSHR miss cycles 1217system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14472940 # number of UpgradeReq MSHR miss cycles 1218system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14472940 # number of UpgradeReq MSHR miss cycles 1219system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7638617543 # number of ReadExReq MSHR miss cycles 1220system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7638617543 # number of ReadExReq MSHR miss cycles 1221system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5579000 # number of demand (read+write) MSHR miss cycles 1222system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 473000 # number of demand (read+write) MSHR miss cycles 1223system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049198000 # number of demand (read+write) MSHR miss cycles 1224system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10077954292 # number of demand (read+write) MSHR miss cycles 1225system.cpu.l2cache.demand_mshr_miss_latency::total 11133204292 # number of demand (read+write) MSHR miss cycles 1226system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5579000 # number of overall MSHR miss cycles 1227system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 473000 # number of overall MSHR miss cycles 1228system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049198000 # number of overall MSHR miss cycles 1229system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10077954292 # number of overall MSHR miss cycles 1230system.cpu.l2cache.overall_mshr_miss_latency::total 11133204292 # number of overall MSHR miss cycles 1231system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275584000 # number of ReadReq MSHR uncacheable cycles 1232system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275584000 # number of ReadReq MSHR uncacheable cycles 1233system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397149000 # number of WriteReq MSHR uncacheable cycles 1234system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397149000 # number of WriteReq MSHR uncacheable cycles 1235system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672733000 # number of overall MSHR uncacheable cycles 1236system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672733000 # number of overall MSHR uncacheable cycles 1237system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for ReadReq accesses 1238system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for ReadReq accesses 1239system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for ReadReq accesses 1240system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026176 # mshr miss rate for ReadReq accesses 1241system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021364 # mshr miss rate for ReadReq accesses 1242system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823731 # mshr miss rate for UpgradeReq accesses 1243system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823731 # mshr miss rate for UpgradeReq accesses 1244system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464684 # mshr miss rate for ReadExReq accesses 1245system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464684 # mshr miss rate for ReadExReq accesses 1246system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for demand accesses 1247system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for demand accesses 1248system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for demand accesses 1249system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for demand accesses 1250system.cpu.l2cache.demand_mshr_miss_rate::total 0.067919 # mshr miss rate for demand accesses 1251system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for overall accesses 1252system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for overall accesses 1253system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for overall accesses 1254system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for overall accesses 1255system.cpu.l2cache.overall_mshr_miss_rate::total 0.067919 # mshr miss rate for overall accesses 1256system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average ReadReq mshr miss latency 1257system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average ReadReq mshr miss latency 1258system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116 # average ReadReq mshr miss latency 1259system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846 # average ReadReq mshr miss latency 1260system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687 # average ReadReq mshr miss latency 1261system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634 # average UpgradeReq mshr miss latency 1262system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634 # average UpgradeReq mshr miss latency 1263system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930 # average ReadExReq mshr miss latency 1264system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930 # average ReadExReq mshr miss latency 1265system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency 1266system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency 1267system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency 1268system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency 1269system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency 1270system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency 1271system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency 1272system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency 1273system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency 1274system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency 1275system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1276system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1277system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1278system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1279system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1280system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1281system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
	1282system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution 1283system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution 1284system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution 1285system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution 1286system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution 1287system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution 1288system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution 1289system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution 1290system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution 1291system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution 1292system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution 1293system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes) 1294system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes) 1295system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes) 1296system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes) 1297system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes) 1298system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes) 1299system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes) 1300system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes) 1301system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes) 1302system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes) 1303system.cpu.toL2Bus.snoops 58568 # Total snoops (count) 1304system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram 1305system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram 1306system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram 1307system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1308system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1309system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1310system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1311system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram 1312system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram 1313system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1314system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1315system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1316system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram 1317system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks) 1318system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1319system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) 1320system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1321system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks) 1322system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1323system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks) 1324system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1325system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks) 1326system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1327system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks) 1328system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1329system.iobus.trans_dist::ReadReq 225681 # Transaction distribution 1330system.iobus.trans_dist::ReadResp 225681 # Transaction distribution 1331system.iobus.trans_dist::WriteReq 57721 # Transaction distribution 1332system.iobus.trans_dist::WriteResp 57721 # Transaction distribution 1333system.iobus.trans_dist::MessageReq 1644 # Transaction distribution 1334system.iobus.trans_dist::MessageResp 1644 # Transaction distribution 1335system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1336system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1337system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 1338system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1339system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1340system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 1341system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1342system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1343system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 1344system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1345system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 1346system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1347system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) 1348system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1349system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1350system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1351system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1352system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1353system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) 1354system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) 1355system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) 1356system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) 1357system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) 1358system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes) 1359system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1360system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1361system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 1362system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1363system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1364system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 1365system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1366system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1367system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 1368system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1369system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 1370system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1371system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) 1372system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1373system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1374system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1375system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1376system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1377system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) 1378system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) 1379system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) 1380system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) 1381system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) 1382system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes) 1383system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) 1384system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1385system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1386system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1387system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1388system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1389system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) 1390system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1391system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1392system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1393system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1394system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1395system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 1396system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1397system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1398system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1399system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1400system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1401system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) 1402system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1403system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1404system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1405system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1406system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1407system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 1408system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1409system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) 1410system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1411system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 1412system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1413system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1414system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1415system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1416system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1417system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1418system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1419system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks) 1420system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1421system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 1422system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1423system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) 1424system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1425system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks) 1426system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1427system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) 1428system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1429system.iocache.tags.replacements 47575 # number of replacements 1430system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use 1431system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1432system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. 1433system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1434system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit. 1435system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor 1436system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy 1437system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy 1438system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1439system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1440system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1441system.iocache.tags.tag_accesses 428670 # Number of tag accesses 1442system.iocache.tags.data_accesses 428670 # Number of data accesses 1443system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 1444system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits 1445system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses 1446system.iocache.ReadReq_misses::total 910 # number of ReadReq misses 1447system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses 1448system.iocache.demand_misses::total 910 # number of demand (read+write) misses 1449system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses 1450system.iocache.overall_misses::total 910 # number of overall misses 1451system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles 1452system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles 1453system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles 1454system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles 1455system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles 1456system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles 1457system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) 1458system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) 1459system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1460system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 1461system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses 1462system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses 1463system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses 1464system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses 1465system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1466system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1467system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1468system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1469system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1470system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1471system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency 1472system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency 1473system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency 1474system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency 1475system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency 1476system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency 1477system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 1478system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1479system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked 1480system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1481system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked 1482system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1483system.iocache.fast_writes 46720 # number of fast writes performed 1484system.iocache.cache_copies 0 # number of cache copies performed 1485system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses 1486system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses 1487system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses 1488system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses 1489system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses 1490system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses 1491system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles 1492system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles 1493system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles 1494system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles 1495system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles 1496system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles 1497system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles 1498system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles 1499system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1500system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1501system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1502system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1503system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1504system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1505system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency 1506system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency 1507system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 1508system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1509system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 1510system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 1511system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency 1512system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency 1513system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1514system.membus.trans_dist::ReadReq 662592 # Transaction distribution 1515system.membus.trans_dist::ReadResp 662582 # Transaction distribution 1516system.membus.trans_dist::WriteReq 13889 # Transaction distribution 1517system.membus.trans_dist::WriteResp 13889 # Transaction distribution 1518system.membus.trans_dist::Writeback 103196 # Transaction distribution 1519system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1520system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 1521system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution 1522system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution 1523system.membus.trans_dist::ReadExReq 133104 # Transaction distribution 1524system.membus.trans_dist::ReadExResp 133101 # Transaction distribution 1525system.membus.trans_dist::MessageReq 1644 # Transaction distribution 1526system.membus.trans_dist::MessageResp 1644 # Transaction distribution 1527system.membus.trans_dist::BadAddressError 10 # Transaction distribution 1528system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) 1529system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) 1530system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) 1531system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) 1532system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes) 1533system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes) 1534system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes) 1535system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes) 1536system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes) 1537system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes) 1538system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) 1539system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) 1540system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) 1541system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) 1542system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes) 1543system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes) 1544system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 1545system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 1546system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes) 1547system.membus.snoops 949 # Total snoops (count) 1548system.membus.snoop_fanout::samples 338415 # Request fanout histogram 1549system.membus.snoop_fanout::mean 1 # Request fanout histogram 1550system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1551system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1552system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1553system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram 1554system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1555system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1556system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1557system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1558system.membus.snoop_fanout::total 338415 # Request fanout histogram 1559system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks) 1560system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1561system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks) 1562system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1563system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) 1564system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1565system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks) 1566system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1567system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) 1568system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 1569system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) 1570system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1571system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks) 1572system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1573system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks) 1574system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1575system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1576system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1577system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 1578system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1579system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1580system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1581system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1582system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1583system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1584system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1585system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1586system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1587system.cpu.kern.inst.arm 0 # number of arm instructions executed 1588system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1589 1590---------- End Simulation Statistics ----------	1587system.cpu.kern.inst.arm 0 # number of arm instructions executed 1588system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1589 1590---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.125902 # Number of seconds simulated
4sim_ticks 5125902116500 # Number of ticks simulated
5final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 134346 # Simulator instruction rate (inst/s)
8host_op_rate 265563 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1687822207 # Simulator tick rate (ticks/s)
10host_mem_usage 793660 # Number of bytes of host memory used
11host_seconds 3036.99 # Real time elapsed on the host

7host_inst_rate 182847 # Simulator instruction rate (inst/s)
8host_op_rate 361437 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2297162464 # Simulator tick rate (ticks/s)
10host_mem_usage 805240 # Number of bytes of host memory used
11host_seconds 2231.41 # Real time elapsed on the host

12sim_insts 408006726 # Number of instructions simulated
13sim_ops 806511598 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory

17system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory

16system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory

20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory

21system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory
25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
26system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory

27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory

28system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory

27system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory

31system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory

32system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory
34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory

36system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)

37system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)

36system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)

40system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)

41system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s)

48system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)

48system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)

52system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)

53system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 185800 # Number of read requests accepted
55system.physmem.writeReqs 149916 # Number of write requests accepted
56system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue
60system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 11891200 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 9594624 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 234 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 1736 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 11489 # Per bank write bursts
67system.physmem.perBankRdBursts::1 10946 # Per bank write bursts
68system.physmem.perBankRdBursts::2 11982 # Per bank write bursts
69system.physmem.perBankRdBursts::3 11463 # Per bank write bursts
70system.physmem.perBankRdBursts::4 11671 # Per bank write bursts
71system.physmem.perBankRdBursts::5 11298 # Per bank write bursts
72system.physmem.perBankRdBursts::6 11252 # Per bank write bursts
73system.physmem.perBankRdBursts::7 11687 # Per bank write bursts
74system.physmem.perBankRdBursts::8 11071 # Per bank write bursts
75system.physmem.perBankRdBursts::9 11217 # Per bank write bursts
76system.physmem.perBankRdBursts::10 11355 # Per bank write bursts
77system.physmem.perBankRdBursts::11 12125 # Per bank write bursts
78system.physmem.perBankRdBursts::12 11861 # Per bank write bursts
79system.physmem.perBankRdBursts::13 12651 # Per bank write bursts
80system.physmem.perBankRdBursts::14 12184 # Per bank write bursts
81system.physmem.perBankRdBursts::15 11314 # Per bank write bursts
82system.physmem.perBankWrBursts::0 9710 # Per bank write bursts
83system.physmem.perBankWrBursts::1 9082 # Per bank write bursts
84system.physmem.perBankWrBursts::2 8978 # Per bank write bursts
85system.physmem.perBankWrBursts::3 8996 # Per bank write bursts
86system.physmem.perBankWrBursts::4 9462 # Per bank write bursts
87system.physmem.perBankWrBursts::5 9601 # Per bank write bursts
88system.physmem.perBankWrBursts::6 9097 # Per bank write bursts
89system.physmem.perBankWrBursts::7 8837 # Per bank write bursts
90system.physmem.perBankWrBursts::8 9327 # Per bank write bursts
91system.physmem.perBankWrBursts::9 9159 # Per bank write bursts
92system.physmem.perBankWrBursts::10 9532 # Per bank write bursts
93system.physmem.perBankWrBursts::11 9463 # Per bank write bursts
94system.physmem.perBankWrBursts::12 9618 # Per bank write bursts
95system.physmem.perBankWrBursts::13 9862 # Per bank write bursts
96system.physmem.perBankWrBursts::14 9881 # Per bank write bursts
97system.physmem.perBankWrBursts::15 9285 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
100system.physmem.totGap 5125902065000 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 0 # Read request sizes (log2)
104system.physmem.readPktSize::3 0 # Read request sizes (log2)
105system.physmem.readPktSize::4 0 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 185800 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 0 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 149916 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 170703 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 12067 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 2038 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 421 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 2237 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 2934 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 7172 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 7637 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 7787 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 8527 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 8842 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 9565 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 10246 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 11384 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 10610 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 9929 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 9208 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 9073 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 7958 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 7723 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 7760 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 7617 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 249 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 222 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 205 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 183 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 121 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 72846 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 294.719271 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 174.256286 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 318.919065 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 28471 39.08% 39.08% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 17446 23.95% 63.03% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 7310 10.03% 73.07% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 4243 5.82% 78.89% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2987 4.10% 82.99% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1984 2.72% 85.72% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1403 1.93% 87.64% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1126 1.55% 89.19% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 7876 10.81% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 72846 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 7377 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 25.152094 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 560.212559 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-2047 7376 99.99% 99.99% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::total 7377 # Reads before turning the bus around for writes
231system.physmem.wrPerTurnAround::samples 7377 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::mean 20.318558 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::gmean 18.615023 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::stdev 12.539295 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::16-19 6330 85.81% 85.81% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::20-23 64 0.87% 86.67% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-27 33 0.45% 87.12% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::28-31 268 3.63% 90.76% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-35 287 3.89% 94.65% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::36-39 24 0.33% 94.97% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::40-43 24 0.33% 95.30% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::44-47 16 0.22% 95.51% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::48-51 20 0.27% 95.78% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::52-55 2 0.03% 95.81% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::56-59 6 0.08% 95.89% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::60-63 2 0.03% 95.92% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::64-67 237 3.21% 99.13% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::68-71 3 0.04% 99.17% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::72-75 2 0.03% 99.20% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::80-83 11 0.15% 99.39% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::92-95 1 0.01% 99.40% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::96-99 12 0.16% 99.57% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::104-107 3 0.04% 99.62% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::108-111 2 0.03% 99.65% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::112-115 6 0.08% 99.73% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::116-119 3 0.04% 99.77% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::124-127 1 0.01% 99.78% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::128-131 13 0.18% 99.96% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::136-139 1 0.01% 99.97% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::total 7377 # Writes before turning the bus around for reads
265system.physmem.totQLat 2068154250 # Total ticks spent queuing
266system.physmem.totMemAccLat 5547516750 # Total ticks spent from burst creation until serviced by the DRAM
267system.physmem.totBusLat 927830000 # Total ticks spent in databus transfers
268system.physmem.avgQLat 11145.11 # Average queueing delay per DRAM burst
269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
270system.physmem.avgMemAccLat 29895.11 # Average memory access latency per DRAM burst
271system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
272system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
273system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
274system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s
275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
276system.physmem.busUtil 0.03 # Data bus utilization in percentage
277system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
278system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
279system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
280system.physmem.avgWrQLen 21.36 # Average write queue length when enqueuing
281system.physmem.readRowHits 151753 # Number of row buffer hits during reads
282system.physmem.writeRowHits 110856 # Number of row buffer hits during writes
283system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads
284system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes
285system.physmem.avgGap 15268566.48 # Average gap between requests
286system.physmem.pageHitRate 78.28 # Row buffer hit rate, read and write combined
287system.physmem.memoryStateTime::IDLE 4919748958000 # Time in different power states
288system.physmem.memoryStateTime::REF 171165020000 # Time in different power states
289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
290system.physmem.memoryStateTime::ACT 34988035500 # Time in different power states
291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
292system.physmem.actEnergy::0 267185520 # Energy for activate commands per rank (pJ)
293system.physmem.actEnergy::1 283530240 # Energy for activate commands per rank (pJ)
294system.physmem.preEnergy::0 145785750 # Energy for precharge commands per rank (pJ)
295system.physmem.preEnergy::1 154704000 # Energy for precharge commands per rank (pJ)
296system.physmem.readEnergy::0 715946400 # Energy for read commands per rank (pJ)
297system.physmem.readEnergy::1 731460600 # Energy for read commands per rank (pJ)
298system.physmem.writeEnergy::0 477984240 # Energy for write commands per rank (pJ)
299system.physmem.writeEnergy::1 493302960 # Energy for write commands per rank (pJ)
300system.physmem.refreshEnergy::0 334798779120 # Energy for refresh commands per rank (pJ)
301system.physmem.refreshEnergy::1 334798779120 # Energy for refresh commands per rank (pJ)
302system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ)
303system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ)
304system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ)
305system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ)
306system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ)
307system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ)
308system.physmem.averagePower::0 668.726542 # Core power per rank (mW)
309system.physmem.averagePower::1 668.742609 # Core power per rank (mW)

310system.membus.trans_dist::ReadReq 662592 # Transaction distribution
311system.membus.trans_dist::ReadResp 662582 # Transaction distribution
312system.membus.trans_dist::WriteReq 13889 # Transaction distribution
313system.membus.trans_dist::WriteResp 13889 # Transaction distribution
314system.membus.trans_dist::Writeback 103196 # Transaction distribution
315system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
316system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
317system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution
318system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
319system.membus.trans_dist::ReadExReq 133104 # Transaction distribution
320system.membus.trans_dist::ReadExResp 133101 # Transaction distribution
321system.membus.trans_dist::MessageReq 1644 # Transaction distribution
322system.membus.trans_dist::MessageResp 1644 # Transaction distribution
323system.membus.trans_dist::BadAddressError 10 # Transaction distribution
324system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
325system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
326system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
327system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
328system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes)
329system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes)
330system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes)
331system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes)
332system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes)
333system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes)
334system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
335system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
336system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
337system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
338system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes)
339system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes)
340system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
341system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
342system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes)
343system.membus.snoops 949 # Total snoops (count)
344system.membus.snoop_fanout::samples 338415 # Request fanout histogram
345system.membus.snoop_fanout::mean 1 # Request fanout histogram
346system.membus.snoop_fanout::stdev 0 # Request fanout histogram
347system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
348system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
349system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram
350system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
351system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
352system.membus.snoop_fanout::min_value 1 # Request fanout histogram
353system.membus.snoop_fanout::max_value 1 # Request fanout histogram
354system.membus.snoop_fanout::total 338415 # Request fanout histogram
355system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks)
356system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
357system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks)
358system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
359system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
360system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
361system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks)
362system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
363system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
364system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
365system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
366system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
367system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks)
368system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
369system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks)
370system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
371system.iocache.tags.replacements 47575 # number of replacements
372system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use
373system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
374system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
375system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
376system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit.
377system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor
378system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy
379system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy
380system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
381system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
382system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
383system.iocache.tags.tag_accesses 428670 # Number of tag accesses
384system.iocache.tags.data_accesses 428670 # Number of data accesses
385system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
386system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
387system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
388system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
389system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
390system.iocache.demand_misses::total 910 # number of demand (read+write) misses
391system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
392system.iocache.overall_misses::total 910 # number of overall misses
393system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles
394system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles
395system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles
396system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles
397system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles
398system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles
399system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
400system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
401system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
402system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
403system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
404system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
405system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
406system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
407system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
408system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
409system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
410system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
411system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
412system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
413system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency
414system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency
415system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
416system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency
417system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
418system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency
419system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
420system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
421system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
422system.iocache.blocked::no_targets 0 # number of cycles access was blocked
423system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
424system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
425system.iocache.fast_writes 46720 # number of fast writes performed
426system.iocache.cache_copies 0 # number of cache copies performed
427system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
428system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
429system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
430system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
431system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
432system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
433system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles
434system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles
435system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles
436system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles
437system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles
438system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles
439system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles
440system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
441system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
442system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
443system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
444system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
445system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
446system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
447system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
448system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
449system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
450system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
451system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
452system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
453system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
454system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
455system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
456system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
457system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
458system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
459system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
460system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
461system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
462system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
463system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
464system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
465system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
466system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
467system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
468system.iobus.trans_dist::ReadReq 225681 # Transaction distribution
469system.iobus.trans_dist::ReadResp 225681 # Transaction distribution
470system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
471system.iobus.trans_dist::WriteResp 57721 # Transaction distribution
472system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
473system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
474system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
475system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
476system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
477system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
478system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
479system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
480system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
481system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
482system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
483system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
484system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
485system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
486system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
487system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
488system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
489system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
490system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
491system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
492system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
493system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
494system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
495system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
496system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
497system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes)
498system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
499system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
500system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
501system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
502system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
503system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
504system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
505system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
506system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
507system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
508system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
509system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
510system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
511system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
512system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
513system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
514system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
515system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
516system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
517system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
518system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
519system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
520system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
521system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes)
522system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks)
523system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
524system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
525system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
526system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
527system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
528system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
529system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
530system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
531system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
532system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
533system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
534system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
535system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
536system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
537system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
538system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
539system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
540system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
541system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
542system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
543system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
544system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
545system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
546system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
547system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
548system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
549system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
550system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
551system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
552system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
553system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
554system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
555system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
556system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
557system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
558system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks)
559system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
560system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
561system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
562system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
563system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
564system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks)
565system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
566system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
567system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
568system.cpu_clk_domain.clock 500 # Clock period in ticks

569system.cpu.branchPred.lookups 86911006 # Number of BP lookups
570system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted
571system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect
572system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups
573system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits
574system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
575system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage
576system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target.
577system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.

310system.cpu.branchPred.lookups 86911006 # Number of BP lookups
311system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted
312system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect
313system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups
314system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits
315system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
316system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage
317system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target.
318system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.

319system.cpu_clk_domain.clock 500 # Clock period in ticks

578system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
579system.cpu.numCycles 449563158 # number of cpu cycles simulated
580system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
581system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
582system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss
583system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed
584system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered
585system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken
586system.cpu.fetch.Cycles 417985667 # Number of cycles fetch has run and was not squashing or blocked
587system.cpu.fetch.SquashCycles 1891240 # Number of cycles fetch has spent squashing
588system.cpu.fetch.TlbCycles 143316 # Number of cycles fetch has spent waiting for tlb
589system.cpu.fetch.MiscStallCycles 50930 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
590system.cpu.fetch.PendingTrapStallCycles 210883 # Number of stall cycles due to pending traps
591system.cpu.fetch.PendingQuiesceStallCycles 127962 # Number of stall cycles due to pending quiesce instructions
592system.cpu.fetch.IcacheWaitRetryStallCycles 502 # Number of stall cycles due to full MSHR
593system.cpu.fetch.CacheLines 9183903 # Number of cache lines fetched
594system.cpu.fetch.IcacheSquashes 446388 # Number of outstanding Icache misses that were squashed
595system.cpu.fetch.ItlbSquashes 4881 # Number of outstanding ITLB misses that were squashed
596system.cpu.fetch.rateDist::samples 447018024 # Number of instructions fetched each cycle (Total)
597system.cpu.fetch.rateDist::mean 1.894555 # Number of instructions fetched each cycle (Total)
598system.cpu.fetch.rateDist::stdev 3.051977 # Number of instructions fetched each cycle (Total)
599system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
600system.cpu.fetch.rateDist::0 281457902 62.96% 62.96% # Number of instructions fetched each cycle (Total)
601system.cpu.fetch.rateDist::1 2285728 0.51% 63.47% # Number of instructions fetched each cycle (Total)
602system.cpu.fetch.rateDist::2 72178245 16.15% 79.62% # Number of instructions fetched each cycle (Total)
603system.cpu.fetch.rateDist::3 1597297 0.36% 79.98% # Number of instructions fetched each cycle (Total)
604system.cpu.fetch.rateDist::4 2150673 0.48% 80.46% # Number of instructions fetched each cycle (Total)
605system.cpu.fetch.rateDist::5 2329203 0.52% 80.98% # Number of instructions fetched each cycle (Total)
606system.cpu.fetch.rateDist::6 1531441 0.34% 81.32% # Number of instructions fetched each cycle (Total)
607system.cpu.fetch.rateDist::7 1871505 0.42% 81.74% # Number of instructions fetched each cycle (Total)
608system.cpu.fetch.rateDist::8 81616030 18.26% 100.00% # Number of instructions fetched each cycle (Total)
609system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
610system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
611system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
612system.cpu.fetch.rateDist::total 447018024 # Number of instructions fetched each cycle (Total)
613system.cpu.fetch.branchRate 0.193323 # Number of branch fetches per cycle
614system.cpu.fetch.rate 0.954576 # Number of inst fetches per cycle
615system.cpu.decode.IdleCycles 22975502 # Number of cycles decode is idle
616system.cpu.decode.BlockedCycles 264891753 # Number of cycles decode is blocked
617system.cpu.decode.RunCycles 150781344 # Number of cycles decode is running
618system.cpu.decode.UnblockCycles 7423805 # Number of cycles decode is unblocking
619system.cpu.decode.SquashCycles 945620 # Number of cycles decode is squashing
620system.cpu.decode.DecodedInsts 838588132 # Number of instructions handled by decode
621system.cpu.rename.SquashCycles 945620 # Number of cycles rename is squashing
622system.cpu.rename.IdleCycles 25820685 # Number of cycles rename is idle
623system.cpu.rename.BlockCycles 223318475 # Number of cycles rename is blocking
624system.cpu.rename.serializeStallCycles 13301995 # count of cycles rename stalled for serializing inst
625system.cpu.rename.RunCycles 154670533 # Number of cycles rename is running
626system.cpu.rename.UnblockCycles 28960716 # Number of cycles rename is unblocking
627system.cpu.rename.RenamedInsts 835102889 # Number of instructions processed by rename
628system.cpu.rename.ROBFullEvents 477440 # Number of times rename has blocked due to ROB full
629system.cpu.rename.IQFullEvents 12397064 # Number of times rename has blocked due to IQ full
630system.cpu.rename.LQFullEvents 181319 # Number of times rename has blocked due to LQ full
631system.cpu.rename.SQFullEvents 13705397 # Number of times rename has blocked due to SQ full
632system.cpu.rename.RenamedOperands 997542850 # Number of destination operands rename has renamed
633system.cpu.rename.RenameLookups 1813799502 # Number of register rename lookups that rename has made
634system.cpu.rename.int_rename_lookups 1115056777 # Number of integer rename lookups
635system.cpu.rename.fp_rename_lookups 257 # Number of floating rename lookups
636system.cpu.rename.CommittedMaps 964533940 # Number of HB maps that are committed
637system.cpu.rename.UndoneMaps 33008908 # Number of HB maps that are undone due to squashing
638system.cpu.rename.serializingInsts 469072 # count of serializing insts renamed
639system.cpu.rename.tempSerializingInsts 473209 # count of temporary serializing insts renamed
640system.cpu.rename.skidInsts 39003947 # count of insts added to the skid buffer
641system.cpu.memDep0.insertedLoads 17327064 # Number of loads inserted to the mem dependence unit.
642system.cpu.memDep0.insertedStores 10187947 # Number of stores inserted to the mem dependence unit.
643system.cpu.memDep0.conflictingLoads 1305152 # Number of conflicting loads.
644system.cpu.memDep0.conflictingStores 1075480 # Number of conflicting stores.
645system.cpu.iq.iqInstsAdded 829577990 # Number of instructions added to the IQ (excludes non-spec)
646system.cpu.iq.iqNonSpecInstsAdded 1211603 # Number of non-speculative instructions added to the IQ
647system.cpu.iq.iqInstsIssued 824337264 # Number of instructions issued
648system.cpu.iq.iqSquashedInstsIssued 238496 # Number of squashed instructions issued
649system.cpu.iq.iqSquashedInstsExamined 23343623 # Number of squashed instructions iterated over during squash; mainly for profiling
650system.cpu.iq.iqSquashedOperandsExamined 36066469 # Number of squashed operands that are examined and possibly removed from graph
651system.cpu.iq.iqSquashedNonSpecRemoved 155814 # Number of squashed non-spec instructions that were removed
652system.cpu.iq.issued_per_cycle::samples 447018024 # Number of insts issued each cycle
653system.cpu.iq.issued_per_cycle::mean 1.844081 # Number of insts issued each cycle
654system.cpu.iq.issued_per_cycle::stdev 2.418172 # Number of insts issued each cycle
655system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
656system.cpu.iq.issued_per_cycle::0 262761301 58.78% 58.78% # Number of insts issued each cycle
657system.cpu.iq.issued_per_cycle::1 13855312 3.10% 61.88% # Number of insts issued each cycle
658system.cpu.iq.issued_per_cycle::2 10080747 2.26% 64.14% # Number of insts issued each cycle
659system.cpu.iq.issued_per_cycle::3 6920313 1.55% 65.68% # Number of insts issued each cycle
660system.cpu.iq.issued_per_cycle::4 74355494 16.63% 82.32% # Number of insts issued each cycle
661system.cpu.iq.issued_per_cycle::5 4460811 1.00% 83.32% # Number of insts issued each cycle
662system.cpu.iq.issued_per_cycle::6 72820656 16.29% 99.61% # Number of insts issued each cycle
663system.cpu.iq.issued_per_cycle::7 1197568 0.27% 99.87% # Number of insts issued each cycle
664system.cpu.iq.issued_per_cycle::8 565822 0.13% 100.00% # Number of insts issued each cycle
665system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
666system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
667system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
668system.cpu.iq.issued_per_cycle::total 447018024 # Number of insts issued each cycle
669system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
670system.cpu.iq.fu_full::IntAlu 1976611 71.80% 71.80% # attempts to use FU when none available
671system.cpu.iq.fu_full::IntMult 212 0.01% 71.80% # attempts to use FU when none available
672system.cpu.iq.fu_full::IntDiv 1052 0.04% 71.84% # attempts to use FU when none available
673system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.84% # attempts to use FU when none available
674system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.84% # attempts to use FU when none available
675system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.84% # attempts to use FU when none available
676system.cpu.iq.fu_full::FloatMult 0 0.00% 71.84% # attempts to use FU when none available
677system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.84% # attempts to use FU when none available
678system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
679system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.84% # attempts to use FU when none available
680system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.84% # attempts to use FU when none available
681system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.84% # attempts to use FU when none available
682system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.84% # attempts to use FU when none available
683system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.84% # attempts to use FU when none available
684system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.84% # attempts to use FU when none available
685system.cpu.iq.fu_full::SimdMult 0 0.00% 71.84% # attempts to use FU when none available
686system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.84% # attempts to use FU when none available
687system.cpu.iq.fu_full::SimdShift 0 0.00% 71.84% # attempts to use FU when none available
688system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.84% # attempts to use FU when none available
689system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.84% # attempts to use FU when none available
690system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.84% # attempts to use FU when none available
691system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.84% # attempts to use FU when none available
692system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.84% # attempts to use FU when none available
693system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.84% # attempts to use FU when none available
694system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.84% # attempts to use FU when none available
695system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.84% # attempts to use FU when none available
696system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.84% # attempts to use FU when none available
697system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.84% # attempts to use FU when none available
698system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
699system.cpu.iq.fu_full::MemRead 614146 22.31% 94.15% # attempts to use FU when none available
700system.cpu.iq.fu_full::MemWrite 161054 5.85% 100.00% # attempts to use FU when none available
701system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
702system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
703system.cpu.iq.FU_type_0::No_OpClass 292817 0.04% 0.04% # Type of FU issued
704system.cpu.iq.FU_type_0::IntAlu 795957789 96.56% 96.59% # Type of FU issued
705system.cpu.iq.FU_type_0::IntMult 150640 0.02% 96.61% # Type of FU issued
706system.cpu.iq.FU_type_0::IntDiv 125262 0.02% 96.63% # Type of FU issued
707system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
708system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
709system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued
710system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
711system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
712system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
713system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
714system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
715system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
716system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
717system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
718system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
719system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
720system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
721system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
722system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
723system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
724system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
725system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
726system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
727system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
728system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
729system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
730system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
731system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
732system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
733system.cpu.iq.FU_type_0::MemRead 18413325 2.23% 98.86% # Type of FU issued
734system.cpu.iq.FU_type_0::MemWrite 9397431 1.14% 100.00% # Type of FU issued
735system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
736system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
737system.cpu.iq.FU_type_0::total 824337264 # Type of FU issued
738system.cpu.iq.rate 1.833641 # Inst issue rate
739system.cpu.iq.fu_busy_cnt 2753075 # FU busy when requested
740system.cpu.iq.fu_busy_rate 0.003340 # FU busy rate (busy events/executed inst)
741system.cpu.iq.int_inst_queue_reads 2098683906 # Number of integer instruction queue reads
742system.cpu.iq.int_inst_queue_writes 854145561 # Number of integer instruction queue writes
743system.cpu.iq.int_inst_queue_wakeup_accesses 819784123 # Number of integer instruction queue wakeup accesses
744system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads
745system.cpu.iq.fp_inst_queue_writes 406 # Number of floating instruction queue writes
746system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
747system.cpu.iq.int_alu_accesses 826797420 # Number of integer alu accesses
748system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses
749system.cpu.iew.lsq.thread0.forwLoads 1878905 # Number of loads that had data forwarded from stores
750system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
751system.cpu.iew.lsq.thread0.squashedLoads 3325392 # Number of loads squashed
752system.cpu.iew.lsq.thread0.ignoredResponses 14284 # Number of memory responses ignored because the instruction is squashed
753system.cpu.iew.lsq.thread0.memOrderViolation 14518 # Number of memory ordering violations
754system.cpu.iew.lsq.thread0.squashedStores 1760345 # Number of stores squashed
755system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
756system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
757system.cpu.iew.lsq.thread0.rescheduledLoads 2224613 # Number of loads that were rescheduled
758system.cpu.iew.lsq.thread0.cacheBlocked 71287 # Number of times an access to memory failed due to the cache being blocked
759system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
760system.cpu.iew.iewSquashCycles 945620 # Number of cycles IEW is squashing
761system.cpu.iew.iewBlockCycles 205593402 # Number of cycles IEW is blocking
762system.cpu.iew.iewUnblockCycles 9425350 # Number of cycles IEW is unblocking
763system.cpu.iew.iewDispatchedInsts 830789593 # Number of instructions dispatched to IQ
764system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch
765system.cpu.iew.iewDispLoadInsts 17327064 # Number of dispatched load instructions
766system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions
767system.cpu.iew.iewDispNonSpecInsts 714327 # Number of dispatched non-speculative instructions
768system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall
769system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall
770system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations
771system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly

320system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
321system.cpu.numCycles 449563158 # number of cpu cycles simulated
322system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
323system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
324system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss
325system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed
326system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered
327system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken
328system.cpu.fetch.Cycles 417985667 # Number of cycles fetch has run and was not squashing or blocked
329system.cpu.fetch.SquashCycles 1891240 # Number of cycles fetch has spent squashing
330system.cpu.fetch.TlbCycles 143316 # Number of cycles fetch has spent waiting for tlb
331system.cpu.fetch.MiscStallCycles 50930 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
332system.cpu.fetch.PendingTrapStallCycles 210883 # Number of stall cycles due to pending traps
333system.cpu.fetch.PendingQuiesceStallCycles 127962 # Number of stall cycles due to pending quiesce instructions
334system.cpu.fetch.IcacheWaitRetryStallCycles 502 # Number of stall cycles due to full MSHR
335system.cpu.fetch.CacheLines 9183903 # Number of cache lines fetched
336system.cpu.fetch.IcacheSquashes 446388 # Number of outstanding Icache misses that were squashed
337system.cpu.fetch.ItlbSquashes 4881 # Number of outstanding ITLB misses that were squashed
338system.cpu.fetch.rateDist::samples 447018024 # Number of instructions fetched each cycle (Total)
339system.cpu.fetch.rateDist::mean 1.894555 # Number of instructions fetched each cycle (Total)
340system.cpu.fetch.rateDist::stdev 3.051977 # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.rateDist::0 281457902 62.96% 62.96% # Number of instructions fetched each cycle (Total)
343system.cpu.fetch.rateDist::1 2285728 0.51% 63.47% # Number of instructions fetched each cycle (Total)
344system.cpu.fetch.rateDist::2 72178245 16.15% 79.62% # Number of instructions fetched each cycle (Total)
345system.cpu.fetch.rateDist::3 1597297 0.36% 79.98% # Number of instructions fetched each cycle (Total)
346system.cpu.fetch.rateDist::4 2150673 0.48% 80.46% # Number of instructions fetched each cycle (Total)
347system.cpu.fetch.rateDist::5 2329203 0.52% 80.98% # Number of instructions fetched each cycle (Total)
348system.cpu.fetch.rateDist::6 1531441 0.34% 81.32% # Number of instructions fetched each cycle (Total)
349system.cpu.fetch.rateDist::7 1871505 0.42% 81.74% # Number of instructions fetched each cycle (Total)
350system.cpu.fetch.rateDist::8 81616030 18.26% 100.00% # Number of instructions fetched each cycle (Total)
351system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
352system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
353system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
354system.cpu.fetch.rateDist::total 447018024 # Number of instructions fetched each cycle (Total)
355system.cpu.fetch.branchRate 0.193323 # Number of branch fetches per cycle
356system.cpu.fetch.rate 0.954576 # Number of inst fetches per cycle
357system.cpu.decode.IdleCycles 22975502 # Number of cycles decode is idle
358system.cpu.decode.BlockedCycles 264891753 # Number of cycles decode is blocked
359system.cpu.decode.RunCycles 150781344 # Number of cycles decode is running
360system.cpu.decode.UnblockCycles 7423805 # Number of cycles decode is unblocking
361system.cpu.decode.SquashCycles 945620 # Number of cycles decode is squashing
362system.cpu.decode.DecodedInsts 838588132 # Number of instructions handled by decode
363system.cpu.rename.SquashCycles 945620 # Number of cycles rename is squashing
364system.cpu.rename.IdleCycles 25820685 # Number of cycles rename is idle
365system.cpu.rename.BlockCycles 223318475 # Number of cycles rename is blocking
366system.cpu.rename.serializeStallCycles 13301995 # count of cycles rename stalled for serializing inst
367system.cpu.rename.RunCycles 154670533 # Number of cycles rename is running
368system.cpu.rename.UnblockCycles 28960716 # Number of cycles rename is unblocking
369system.cpu.rename.RenamedInsts 835102889 # Number of instructions processed by rename
370system.cpu.rename.ROBFullEvents 477440 # Number of times rename has blocked due to ROB full
371system.cpu.rename.IQFullEvents 12397064 # Number of times rename has blocked due to IQ full
372system.cpu.rename.LQFullEvents 181319 # Number of times rename has blocked due to LQ full
373system.cpu.rename.SQFullEvents 13705397 # Number of times rename has blocked due to SQ full
374system.cpu.rename.RenamedOperands 997542850 # Number of destination operands rename has renamed
375system.cpu.rename.RenameLookups 1813799502 # Number of register rename lookups that rename has made
376system.cpu.rename.int_rename_lookups 1115056777 # Number of integer rename lookups
377system.cpu.rename.fp_rename_lookups 257 # Number of floating rename lookups
378system.cpu.rename.CommittedMaps 964533940 # Number of HB maps that are committed
379system.cpu.rename.UndoneMaps 33008908 # Number of HB maps that are undone due to squashing
380system.cpu.rename.serializingInsts 469072 # count of serializing insts renamed
381system.cpu.rename.tempSerializingInsts 473209 # count of temporary serializing insts renamed
382system.cpu.rename.skidInsts 39003947 # count of insts added to the skid buffer
383system.cpu.memDep0.insertedLoads 17327064 # Number of loads inserted to the mem dependence unit.
384system.cpu.memDep0.insertedStores 10187947 # Number of stores inserted to the mem dependence unit.
385system.cpu.memDep0.conflictingLoads 1305152 # Number of conflicting loads.
386system.cpu.memDep0.conflictingStores 1075480 # Number of conflicting stores.
387system.cpu.iq.iqInstsAdded 829577990 # Number of instructions added to the IQ (excludes non-spec)
388system.cpu.iq.iqNonSpecInstsAdded 1211603 # Number of non-speculative instructions added to the IQ
389system.cpu.iq.iqInstsIssued 824337264 # Number of instructions issued
390system.cpu.iq.iqSquashedInstsIssued 238496 # Number of squashed instructions issued
391system.cpu.iq.iqSquashedInstsExamined 23343623 # Number of squashed instructions iterated over during squash; mainly for profiling
392system.cpu.iq.iqSquashedOperandsExamined 36066469 # Number of squashed operands that are examined and possibly removed from graph
393system.cpu.iq.iqSquashedNonSpecRemoved 155814 # Number of squashed non-spec instructions that were removed
394system.cpu.iq.issued_per_cycle::samples 447018024 # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::mean 1.844081 # Number of insts issued each cycle
396system.cpu.iq.issued_per_cycle::stdev 2.418172 # Number of insts issued each cycle
397system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::0 262761301 58.78% 58.78% # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::1 13855312 3.10% 61.88% # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::2 10080747 2.26% 64.14% # Number of insts issued each cycle
401system.cpu.iq.issued_per_cycle::3 6920313 1.55% 65.68% # Number of insts issued each cycle
402system.cpu.iq.issued_per_cycle::4 74355494 16.63% 82.32% # Number of insts issued each cycle
403system.cpu.iq.issued_per_cycle::5 4460811 1.00% 83.32% # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::6 72820656 16.29% 99.61% # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::7 1197568 0.27% 99.87% # Number of insts issued each cycle
406system.cpu.iq.issued_per_cycle::8 565822 0.13% 100.00% # Number of insts issued each cycle
407system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
408system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
409system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
410system.cpu.iq.issued_per_cycle::total 447018024 # Number of insts issued each cycle
411system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
412system.cpu.iq.fu_full::IntAlu 1976611 71.80% 71.80% # attempts to use FU when none available
413system.cpu.iq.fu_full::IntMult 212 0.01% 71.80% # attempts to use FU when none available
414system.cpu.iq.fu_full::IntDiv 1052 0.04% 71.84% # attempts to use FU when none available
415system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.84% # attempts to use FU when none available
416system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.84% # attempts to use FU when none available
417system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.84% # attempts to use FU when none available
418system.cpu.iq.fu_full::FloatMult 0 0.00% 71.84% # attempts to use FU when none available
419system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.84% # attempts to use FU when none available
420system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.84% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.84% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.84% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.84% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.84% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.84% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdMult 0 0.00% 71.84% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.84% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdShift 0 0.00% 71.84% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.84% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.84% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.84% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.84% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.84% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.84% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.84% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.84% # attempts to use FU when none available
438system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.84% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.84% # attempts to use FU when none available
440system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
441system.cpu.iq.fu_full::MemRead 614146 22.31% 94.15% # attempts to use FU when none available
442system.cpu.iq.fu_full::MemWrite 161054 5.85% 100.00% # attempts to use FU when none available
443system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
444system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
445system.cpu.iq.FU_type_0::No_OpClass 292817 0.04% 0.04% # Type of FU issued
446system.cpu.iq.FU_type_0::IntAlu 795957789 96.56% 96.59% # Type of FU issued
447system.cpu.iq.FU_type_0::IntMult 150640 0.02% 96.61% # Type of FU issued
448system.cpu.iq.FU_type_0::IntDiv 125262 0.02% 96.63% # Type of FU issued
449system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
450system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
451system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued
452system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
453system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
454system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
455system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
475system.cpu.iq.FU_type_0::MemRead 18413325 2.23% 98.86% # Type of FU issued
476system.cpu.iq.FU_type_0::MemWrite 9397431 1.14% 100.00% # Type of FU issued
477system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
478system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
479system.cpu.iq.FU_type_0::total 824337264 # Type of FU issued
480system.cpu.iq.rate 1.833641 # Inst issue rate
481system.cpu.iq.fu_busy_cnt 2753075 # FU busy when requested
482system.cpu.iq.fu_busy_rate 0.003340 # FU busy rate (busy events/executed inst)
483system.cpu.iq.int_inst_queue_reads 2098683906 # Number of integer instruction queue reads
484system.cpu.iq.int_inst_queue_writes 854145561 # Number of integer instruction queue writes
485system.cpu.iq.int_inst_queue_wakeup_accesses 819784123 # Number of integer instruction queue wakeup accesses
486system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads
487system.cpu.iq.fp_inst_queue_writes 406 # Number of floating instruction queue writes
488system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
489system.cpu.iq.int_alu_accesses 826797420 # Number of integer alu accesses
490system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses
491system.cpu.iew.lsq.thread0.forwLoads 1878905 # Number of loads that had data forwarded from stores
492system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
493system.cpu.iew.lsq.thread0.squashedLoads 3325392 # Number of loads squashed
494system.cpu.iew.lsq.thread0.ignoredResponses 14284 # Number of memory responses ignored because the instruction is squashed
495system.cpu.iew.lsq.thread0.memOrderViolation 14518 # Number of memory ordering violations
496system.cpu.iew.lsq.thread0.squashedStores 1760345 # Number of stores squashed
497system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
498system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
499system.cpu.iew.lsq.thread0.rescheduledLoads 2224613 # Number of loads that were rescheduled
500system.cpu.iew.lsq.thread0.cacheBlocked 71287 # Number of times an access to memory failed due to the cache being blocked
501system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
502system.cpu.iew.iewSquashCycles 945620 # Number of cycles IEW is squashing
503system.cpu.iew.iewBlockCycles 205593402 # Number of cycles IEW is blocking
504system.cpu.iew.iewUnblockCycles 9425350 # Number of cycles IEW is unblocking
505system.cpu.iew.iewDispatchedInsts 830789593 # Number of instructions dispatched to IQ
506system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch
507system.cpu.iew.iewDispLoadInsts 17327064 # Number of dispatched load instructions
508system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions
509system.cpu.iew.iewDispNonSpecInsts 714327 # Number of dispatched non-speculative instructions
510system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall
511system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall
512system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations
513system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly

772system.cpu.iew.predictedNotTakenIncorrect 536897 # Number of branches that were predicted not taken incorrectly
773system.cpu.iew.branchMispredicts 1052437 # Number of branch mispredicts detected at execute

514system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly
515system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute

774system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions
775system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed
776system.cpu.iew.iewExecSquashedInsts 1477348 # Number of squashed instructions skipped in execute
777system.cpu.iew.exec_swp 0 # number of swp insts executed
778system.cpu.iew.exec_nop 0 # number of nop insts executed
779system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed
780system.cpu.iew.exec_branches 83308581 # Number of branches executed
781system.cpu.iew.exec_stores 9169768 # Number of stores executed
782system.cpu.iew.exec_rate 1.830056 # Inst execution rate
783system.cpu.iew.wb_sent 822221777 # cumulative count of insts sent to commit
784system.cpu.iew.wb_count 819784184 # cumulative count of insts written-back
785system.cpu.iew.wb_producers 641108962 # num instructions producing a value
786system.cpu.iew.wb_consumers 1050701242 # num instructions consuming a value
787system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
788system.cpu.iew.wb_rate 1.823513 # insts written-back per cycle
789system.cpu.iew.wb_fanout 0.610172 # average fanout of values written-back
790system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
791system.cpu.commit.commitSquashedInsts 24183935 # The number of squashed insts skipped by commit
792system.cpu.commit.commitNonSpecStalls 1055789 # The number of times commit has been forced to stall to communicate backwards
793system.cpu.commit.branchMispredicts 913678 # The number of times a branch was mispredicted
794system.cpu.commit.committed_per_cycle::samples 443381671 # Number of insts commited each cycle
795system.cpu.commit.committed_per_cycle::mean 1.819001 # Number of insts commited each cycle
796system.cpu.commit.committed_per_cycle::stdev 2.675688 # Number of insts commited each cycle
797system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
798system.cpu.commit.committed_per_cycle::0 272578077 61.48% 61.48% # Number of insts commited each cycle
799system.cpu.commit.committed_per_cycle::1 11201647 2.53% 64.00% # Number of insts commited each cycle
800system.cpu.commit.committed_per_cycle::2 3542666 0.80% 64.80% # Number of insts commited each cycle
801system.cpu.commit.committed_per_cycle::3 74562549 16.82% 81.62% # Number of insts commited each cycle
802system.cpu.commit.committed_per_cycle::4 2432578 0.55% 82.17% # Number of insts commited each cycle
803system.cpu.commit.committed_per_cycle::5 1609465 0.36% 82.53% # Number of insts commited each cycle
804system.cpu.commit.committed_per_cycle::6 914477 0.21% 82.74% # Number of insts commited each cycle
805system.cpu.commit.committed_per_cycle::7 71049223 16.02% 98.76% # Number of insts commited each cycle
806system.cpu.commit.committed_per_cycle::8 5490989 1.24% 100.00% # Number of insts commited each cycle
807system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
808system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
809system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
810system.cpu.commit.committed_per_cycle::total 443381671 # Number of insts commited each cycle
811system.cpu.commit.committedInsts 408006726 # Number of instructions committed
812system.cpu.commit.committedOps 806511598 # Number of ops (including micro ops) committed
813system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
814system.cpu.commit.refs 22429273 # Number of memory references committed
815system.cpu.commit.loads 14001671 # Number of loads committed
816system.cpu.commit.membars 475333 # Number of memory barriers committed
817system.cpu.commit.branches 82207365 # Number of branches committed
818system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
819system.cpu.commit.int_insts 735317995 # Number of committed integer instructions.
820system.cpu.commit.function_calls 1155841 # Number of function calls committed.
821system.cpu.commit.op_class_0::No_OpClass 174216 0.02% 0.02% # Class of committed instruction
822system.cpu.commit.op_class_0::IntAlu 783641693 97.16% 97.19% # Class of committed instruction
823system.cpu.commit.op_class_0::IntMult 144853 0.02% 97.20% # Class of committed instruction
824system.cpu.commit.op_class_0::IntDiv 121563 0.02% 97.22% # Class of committed instruction
825system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
826system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
827system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
828system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
829system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
830system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
831system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
832system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
833system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
834system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
835system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
836system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
837system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
838system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
839system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
840system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
841system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
842system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
843system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
844system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
845system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
846system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
847system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
848system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
849system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
850system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
851system.cpu.commit.op_class_0::MemRead 14001671 1.74% 98.96% # Class of committed instruction
852system.cpu.commit.op_class_0::MemWrite 8427602 1.04% 100.00% # Class of committed instruction
853system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
854system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
855system.cpu.commit.op_class_0::total 806511598 # Class of committed instruction
856system.cpu.commit.bw_lim_events 5490989 # number cycles where commit BW limit reached
857system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
858system.cpu.rob.rob_reads 1268507964 # The number of ROB reads
859system.cpu.rob.rob_writes 1665044622 # The number of ROB writes
860system.cpu.timesIdled 294262 # Number of times that the entire CPU went into an idle state and unscheduled itself
861system.cpu.idleCycles 2545134 # Total number of cycles that the CPU has spent unscheduled due to idling
862system.cpu.quiesceCycles 9802241311 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
863system.cpu.committedInsts 408006726 # Number of Instructions Simulated
864system.cpu.committedOps 806511598 # Number of Ops (including micro ops) Simulated
865system.cpu.cpi 1.101852 # CPI: Cycles Per Instruction
866system.cpu.cpi_total 1.101852 # CPI: Total CPI of All Threads
867system.cpu.ipc 0.907563 # IPC: Instructions Per Cycle
868system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads
869system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads
870system.cpu.int_regfile_writes 656162059 # number of integer regfile writes
871system.cpu.fp_regfile_reads 61 # number of floating regfile reads
872system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads
873system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes
874system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads
875system.cpu.misc_regfile_writes 402647 # number of misc regfile writes

516system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions
517system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed
518system.cpu.iew.iewExecSquashedInsts 1477348 # Number of squashed instructions skipped in execute
519system.cpu.iew.exec_swp 0 # number of swp insts executed
520system.cpu.iew.exec_nop 0 # number of nop insts executed
521system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed
522system.cpu.iew.exec_branches 83308581 # Number of branches executed
523system.cpu.iew.exec_stores 9169768 # Number of stores executed
524system.cpu.iew.exec_rate 1.830056 # Inst execution rate
525system.cpu.iew.wb_sent 822221777 # cumulative count of insts sent to commit
526system.cpu.iew.wb_count 819784184 # cumulative count of insts written-back
527system.cpu.iew.wb_producers 641108962 # num instructions producing a value
528system.cpu.iew.wb_consumers 1050701242 # num instructions consuming a value
529system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
530system.cpu.iew.wb_rate 1.823513 # insts written-back per cycle
531system.cpu.iew.wb_fanout 0.610172 # average fanout of values written-back
532system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
533system.cpu.commit.commitSquashedInsts 24183935 # The number of squashed insts skipped by commit
534system.cpu.commit.commitNonSpecStalls 1055789 # The number of times commit has been forced to stall to communicate backwards
535system.cpu.commit.branchMispredicts 913678 # The number of times a branch was mispredicted
536system.cpu.commit.committed_per_cycle::samples 443381671 # Number of insts commited each cycle
537system.cpu.commit.committed_per_cycle::mean 1.819001 # Number of insts commited each cycle
538system.cpu.commit.committed_per_cycle::stdev 2.675688 # Number of insts commited each cycle
539system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::0 272578077 61.48% 61.48% # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::1 11201647 2.53% 64.00% # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::2 3542666 0.80% 64.80% # Number of insts commited each cycle
543system.cpu.commit.committed_per_cycle::3 74562549 16.82% 81.62% # Number of insts commited each cycle
544system.cpu.commit.committed_per_cycle::4 2432578 0.55% 82.17% # Number of insts commited each cycle
545system.cpu.commit.committed_per_cycle::5 1609465 0.36% 82.53% # Number of insts commited each cycle
546system.cpu.commit.committed_per_cycle::6 914477 0.21% 82.74% # Number of insts commited each cycle
547system.cpu.commit.committed_per_cycle::7 71049223 16.02% 98.76% # Number of insts commited each cycle
548system.cpu.commit.committed_per_cycle::8 5490989 1.24% 100.00% # Number of insts commited each cycle
549system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
550system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
551system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
552system.cpu.commit.committed_per_cycle::total 443381671 # Number of insts commited each cycle
553system.cpu.commit.committedInsts 408006726 # Number of instructions committed
554system.cpu.commit.committedOps 806511598 # Number of ops (including micro ops) committed
555system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
556system.cpu.commit.refs 22429273 # Number of memory references committed
557system.cpu.commit.loads 14001671 # Number of loads committed
558system.cpu.commit.membars 475333 # Number of memory barriers committed
559system.cpu.commit.branches 82207365 # Number of branches committed
560system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
561system.cpu.commit.int_insts 735317995 # Number of committed integer instructions.
562system.cpu.commit.function_calls 1155841 # Number of function calls committed.
563system.cpu.commit.op_class_0::No_OpClass 174216 0.02% 0.02% # Class of committed instruction
564system.cpu.commit.op_class_0::IntAlu 783641693 97.16% 97.19% # Class of committed instruction
565system.cpu.commit.op_class_0::IntMult 144853 0.02% 97.20% # Class of committed instruction
566system.cpu.commit.op_class_0::IntDiv 121563 0.02% 97.22% # Class of committed instruction
567system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
568system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
569system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
570system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
571system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
572system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
573system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
574system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
575system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
576system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
577system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
578system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
579system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
580system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
581system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
582system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
583system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
584system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
585system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
586system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
587system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
588system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
589system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
590system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
591system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
592system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
593system.cpu.commit.op_class_0::MemRead 14001671 1.74% 98.96% # Class of committed instruction
594system.cpu.commit.op_class_0::MemWrite 8427602 1.04% 100.00% # Class of committed instruction
595system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
596system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
597system.cpu.commit.op_class_0::total 806511598 # Class of committed instruction
598system.cpu.commit.bw_lim_events 5490989 # number cycles where commit BW limit reached
599system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
600system.cpu.rob.rob_reads 1268507964 # The number of ROB reads
601system.cpu.rob.rob_writes 1665044622 # The number of ROB writes
602system.cpu.timesIdled 294262 # Number of times that the entire CPU went into an idle state and unscheduled itself
603system.cpu.idleCycles 2545134 # Total number of cycles that the CPU has spent unscheduled due to idling
604system.cpu.quiesceCycles 9802241311 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
605system.cpu.committedInsts 408006726 # Number of Instructions Simulated
606system.cpu.committedOps 806511598 # Number of Ops (including micro ops) Simulated
607system.cpu.cpi 1.101852 # CPI: Cycles Per Instruction
608system.cpu.cpi_total 1.101852 # CPI: Total CPI of All Threads
609system.cpu.ipc 0.907563 # IPC: Instructions Per Cycle
610system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads
611system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads
612system.cpu.int_regfile_writes 656162059 # number of integer regfile writes
613system.cpu.fp_regfile_reads 61 # number of floating regfile reads
614system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads
615system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes
616system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads
617system.cpu.misc_regfile_writes 402647 # number of misc regfile writes

876system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution
877system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution
878system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
879system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
880system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution
881system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
882system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
883system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
884system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution
885system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution
886system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution
887system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes)
888system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes)
889system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes)
890system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes)
891system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes)
892system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes)
893system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes)
894system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes)
895system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes)
896system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes)
897system.cpu.toL2Bus.snoops 58568 # Total snoops (count)
898system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram
899system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram
900system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram
901system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
902system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
903system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
904system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
905system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram
906system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram
907system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
908system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
909system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
910system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram
911system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks)
912system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
913system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks)
914system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
915system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks)
916system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
917system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks)
918system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
919system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks)
920system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
921system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks)
922system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

618system.cpu.dcache.tags.replacements 1657683 # number of replacements
619system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use
620system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks.
621system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks.
622system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks.
623system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
624system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor
625system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
626system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
627system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
628system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
629system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
630system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
631system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
632system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses
633system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses
634system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits
635system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits
636system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits
637system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits
638system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits
639system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits
640system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits
641system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits
642system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits
643system.cpu.dcache.overall_hits::total 19128334 # number of overall hits
644system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses
645system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses
646system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses
647system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses
648system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses
649system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses
650system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses
651system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses
652system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses
653system.cpu.dcache.overall_misses::total 2535648 # number of overall misses
654system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles
655system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles
656system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles
657system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles
658system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles
659system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles
660system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles
661system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles
662system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses)
663system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses)
664system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses)
665system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses)
666system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses)
667system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses)
668system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses
669system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses
670system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses
671system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses
672system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses
673system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses
674system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses
675system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses
676system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses
677system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses
678system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses
679system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses
680system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses
681system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses
682system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency
683system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency
684system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency
685system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency
686system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency
687system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency
688system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency
689system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency
690system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked
691system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
692system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked
693system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
694system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked
695system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
696system.cpu.dcache.fast_writes 0 # number of fast writes performed
697system.cpu.dcache.cache_copies 0 # number of cache copies performed
698system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks
699system.cpu.dcache.writebacks::total 1559289 # number of writebacks
700system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits
701system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits
702system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits
703system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits
704system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits
705system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits
706system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits
707system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits
708system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses
709system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses
710system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses
711system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses
712system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses
713system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses
714system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses
715system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses
716system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses
717system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses
718system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles
719system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles
720system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles
721system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles
722system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles
723system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles
724system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles
725system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles
726system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles
727system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles
728system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles
729system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles
730system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles
731system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles
732system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles
733system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles
734system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses
735system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses
736system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses
737system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses
738system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses
739system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses
740system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses
741system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses
742system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses
743system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses
744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency
745system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency
746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency
747system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency
748system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency
749system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency
750system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency
751system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency
752system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency
753system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency
754system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
755system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
756system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
757system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
758system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
759system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
760system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
761system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements
762system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use
763system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks.
764system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks.
765system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks.
766system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit.
767system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor
768system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy
769system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy
770system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
771system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
772system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
773system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
774system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
775system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses
776system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses
777system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits
778system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits
779system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits
780system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits
781system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits
782system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits
783system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses
784system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses
785system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses
786system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses
787system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses
788system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses
789system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles
790system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles
791system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles
792system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles
793system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles
794system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles
795system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses)
796system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses)
797system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses
798system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses
799system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses
800system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses
801system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses
802system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses
803system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses
804system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses
805system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses
806system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses
807system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency
808system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency
809system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
810system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency
811system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
812system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency
813system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
814system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
815system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
816system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
817system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
818system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
819system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
820system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
821system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks
822system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks
823system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses
824system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses
825system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses
826system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses
827system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses
828system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses
829system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles
830system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles
831system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles
832system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles
833system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles
834system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles
835system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses
836system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses
837system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses
838system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses
839system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses
840system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses
841system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency
842system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency
843system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
844system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
845system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
846system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
847system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate

923system.cpu.icache.tags.replacements 994393 # number of replacements
924system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use
925system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks.
926system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks.
927system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks.
928system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit.
929system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor
930system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy
931system.cpu.icache.tags.occ_percent::total 0.996163 # Average percentage of cache occupancy
932system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
933system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
934system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
935system.cpu.icache.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id
936system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
937system.cpu.icache.tags.tag_accesses 10178850 # Number of tag accesses
938system.cpu.icache.tags.data_accesses 10178850 # Number of data accesses
939system.cpu.icache.ReadReq_hits::cpu.inst 8125717 # number of ReadReq hits
940system.cpu.icache.ReadReq_hits::total 8125717 # number of ReadReq hits
941system.cpu.icache.demand_hits::cpu.inst 8125717 # number of demand (read+write) hits
942system.cpu.icache.demand_hits::total 8125717 # number of demand (read+write) hits
943system.cpu.icache.overall_hits::cpu.inst 8125717 # number of overall hits
944system.cpu.icache.overall_hits::total 8125717 # number of overall hits
945system.cpu.icache.ReadReq_misses::cpu.inst 1058185 # number of ReadReq misses
946system.cpu.icache.ReadReq_misses::total 1058185 # number of ReadReq misses
947system.cpu.icache.demand_misses::cpu.inst 1058185 # number of demand (read+write) misses
948system.cpu.icache.demand_misses::total 1058185 # number of demand (read+write) misses
949system.cpu.icache.overall_misses::cpu.inst 1058185 # number of overall misses
950system.cpu.icache.overall_misses::total 1058185 # number of overall misses
951system.cpu.icache.ReadReq_miss_latency::cpu.inst 14693875503 # number of ReadReq miss cycles
952system.cpu.icache.ReadReq_miss_latency::total 14693875503 # number of ReadReq miss cycles
953system.cpu.icache.demand_miss_latency::cpu.inst 14693875503 # number of demand (read+write) miss cycles
954system.cpu.icache.demand_miss_latency::total 14693875503 # number of demand (read+write) miss cycles
955system.cpu.icache.overall_miss_latency::cpu.inst 14693875503 # number of overall miss cycles
956system.cpu.icache.overall_miss_latency::total 14693875503 # number of overall miss cycles
957system.cpu.icache.ReadReq_accesses::cpu.inst 9183902 # number of ReadReq accesses(hits+misses)
958system.cpu.icache.ReadReq_accesses::total 9183902 # number of ReadReq accesses(hits+misses)
959system.cpu.icache.demand_accesses::cpu.inst 9183902 # number of demand (read+write) accesses
960system.cpu.icache.demand_accesses::total 9183902 # number of demand (read+write) accesses
961system.cpu.icache.overall_accesses::cpu.inst 9183902 # number of overall (read+write) accesses
962system.cpu.icache.overall_accesses::total 9183902 # number of overall (read+write) accesses
963system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115222 # miss rate for ReadReq accesses
964system.cpu.icache.ReadReq_miss_rate::total 0.115222 # miss rate for ReadReq accesses
965system.cpu.icache.demand_miss_rate::cpu.inst 0.115222 # miss rate for demand accesses
966system.cpu.icache.demand_miss_rate::total 0.115222 # miss rate for demand accesses
967system.cpu.icache.overall_miss_rate::cpu.inst 0.115222 # miss rate for overall accesses
968system.cpu.icache.overall_miss_rate::total 0.115222 # miss rate for overall accesses
969system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069 # average ReadReq miss latency
970system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069 # average ReadReq miss latency
971system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
972system.cpu.icache.demand_avg_miss_latency::total 13885.923069 # average overall miss latency
973system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
974system.cpu.icache.overall_avg_miss_latency::total 13885.923069 # average overall miss latency
975system.cpu.icache.blocked_cycles::no_mshrs 7023 # number of cycles access was blocked
976system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
977system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
978system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
979system.cpu.icache.avg_blocked_cycles::no_mshrs 23.646465 # average number of cycles each access was blocked
980system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
981system.cpu.icache.fast_writes 0 # number of fast writes performed
982system.cpu.icache.cache_copies 0 # number of cache copies performed
983system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63237 # number of ReadReq MSHR hits
984system.cpu.icache.ReadReq_mshr_hits::total 63237 # number of ReadReq MSHR hits
985system.cpu.icache.demand_mshr_hits::cpu.inst 63237 # number of demand (read+write) MSHR hits
986system.cpu.icache.demand_mshr_hits::total 63237 # number of demand (read+write) MSHR hits
987system.cpu.icache.overall_mshr_hits::cpu.inst 63237 # number of overall MSHR hits
988system.cpu.icache.overall_mshr_hits::total 63237 # number of overall MSHR hits
989system.cpu.icache.ReadReq_mshr_misses::cpu.inst 994948 # number of ReadReq MSHR misses
990system.cpu.icache.ReadReq_mshr_misses::total 994948 # number of ReadReq MSHR misses
991system.cpu.icache.demand_mshr_misses::cpu.inst 994948 # number of demand (read+write) MSHR misses
992system.cpu.icache.demand_mshr_misses::total 994948 # number of demand (read+write) MSHR misses
993system.cpu.icache.overall_mshr_misses::cpu.inst 994948 # number of overall MSHR misses
994system.cpu.icache.overall_mshr_misses::total 994948 # number of overall MSHR misses
995system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12059629101 # number of ReadReq MSHR miss cycles
996system.cpu.icache.ReadReq_mshr_miss_latency::total 12059629101 # number of ReadReq MSHR miss cycles
997system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12059629101 # number of demand (read+write) MSHR miss cycles
998system.cpu.icache.demand_mshr_miss_latency::total 12059629101 # number of demand (read+write) MSHR miss cycles
999system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12059629101 # number of overall MSHR miss cycles
1000system.cpu.icache.overall_mshr_miss_latency::total 12059629101 # number of overall MSHR miss cycles
1001system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for ReadReq accesses
1002system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108336 # mshr miss rate for ReadReq accesses
1003system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for demand accesses
1004system.cpu.icache.demand_mshr_miss_rate::total 0.108336 # mshr miss rate for demand accesses
1005system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for overall accesses
1006system.cpu.icache.overall_mshr_miss_rate::total 0.108336 # mshr miss rate for overall accesses
1007system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704 # average ReadReq mshr miss latency
1008system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704 # average ReadReq mshr miss latency
1009system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
1010system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
1011system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
1012system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
1013system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1014system.cpu.itb_walker_cache.tags.replacements 14092 # number of replacements
1015system.cpu.itb_walker_cache.tags.tagsinuse 6.014059 # Cycle average of tags in use
1016system.cpu.itb_walker_cache.tags.total_refs 26262 # Total number of references to valid blocks.
1017system.cpu.itb_walker_cache.tags.sampled_refs 14107 # Sample count of references to valid blocks.
1018system.cpu.itb_walker_cache.tags.avg_refs 1.861629 # Average number of references to valid blocks.
1019system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000 # Cycle when the warmup percentage was hit.
1020system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.014059 # Average occupied blocks per requestor
1021system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375879 # Average percentage of cache occupancy
1022system.cpu.itb_walker_cache.tags.occ_percent::total 0.375879 # Average percentage of cache occupancy
1023system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
1024system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1025system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
1026system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
1027system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
1028system.cpu.itb_walker_cache.tags.tag_accesses 97491 # Number of tag accesses
1029system.cpu.itb_walker_cache.tags.data_accesses 97491 # Number of data accesses
1030system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26263 # number of ReadReq hits
1031system.cpu.itb_walker_cache.ReadReq_hits::total 26263 # number of ReadReq hits
1032system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
1033system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
1034system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26265 # number of demand (read+write) hits
1035system.cpu.itb_walker_cache.demand_hits::total 26265 # number of demand (read+write) hits
1036system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26265 # number of overall hits
1037system.cpu.itb_walker_cache.overall_hits::total 26265 # number of overall hits
1038system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14987 # number of ReadReq misses
1039system.cpu.itb_walker_cache.ReadReq_misses::total 14987 # number of ReadReq misses
1040system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14987 # number of demand (read+write) misses
1041system.cpu.itb_walker_cache.demand_misses::total 14987 # number of demand (read+write) misses
1042system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14987 # number of overall misses
1043system.cpu.itb_walker_cache.overall_misses::total 14987 # number of overall misses
1044system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 174073497 # number of ReadReq miss cycles
1045system.cpu.itb_walker_cache.ReadReq_miss_latency::total 174073497 # number of ReadReq miss cycles
1046system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174073497 # number of demand (read+write) miss cycles
1047system.cpu.itb_walker_cache.demand_miss_latency::total 174073497 # number of demand (read+write) miss cycles
1048system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174073497 # number of overall miss cycles
1049system.cpu.itb_walker_cache.overall_miss_latency::total 174073497 # number of overall miss cycles
1050system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41250 # number of ReadReq accesses(hits+misses)
1051system.cpu.itb_walker_cache.ReadReq_accesses::total 41250 # number of ReadReq accesses(hits+misses)
1052system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1053system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1054system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41252 # number of demand (read+write) accesses
1055system.cpu.itb_walker_cache.demand_accesses::total 41252 # number of demand (read+write) accesses
1056system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41252 # number of overall (read+write) accesses
1057system.cpu.itb_walker_cache.overall_accesses::total 41252 # number of overall (read+write) accesses
1058system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363321 # miss rate for ReadReq accesses
1059system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363321 # miss rate for ReadReq accesses
1060system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363304 # miss rate for demand accesses
1061system.cpu.itb_walker_cache.demand_miss_rate::total 0.363304 # miss rate for demand accesses
1062system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363304 # miss rate for overall accesses
1063system.cpu.itb_walker_cache.overall_miss_rate::total 0.363304 # miss rate for overall accesses
1064system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104 # average ReadReq miss latency
1065system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104 # average ReadReq miss latency
1066system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
1067system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104 # average overall miss latency
1068system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
1069system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104 # average overall miss latency
1070system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1071system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1072system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1073system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1074system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1075system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1076system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1077system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1078system.cpu.itb_walker_cache.writebacks::writebacks 3303 # number of writebacks
1079system.cpu.itb_walker_cache.writebacks::total 3303 # number of writebacks
1080system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14987 # number of ReadReq MSHR misses
1081system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14987 # number of ReadReq MSHR misses
1082system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14987 # number of demand (read+write) MSHR misses
1083system.cpu.itb_walker_cache.demand_mshr_misses::total 14987 # number of demand (read+write) MSHR misses
1084system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14987 # number of overall MSHR misses
1085system.cpu.itb_walker_cache.overall_mshr_misses::total 14987 # number of overall MSHR misses
1086system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 144083525 # number of ReadReq MSHR miss cycles
1087system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144083525 # number of ReadReq MSHR miss cycles
1088system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144083525 # number of demand (read+write) MSHR miss cycles
1089system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144083525 # number of demand (read+write) MSHR miss cycles
1090system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144083525 # number of overall MSHR miss cycles
1091system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144083525 # number of overall MSHR miss cycles
1092system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363321 # mshr miss rate for ReadReq accesses
1093system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363321 # mshr miss rate for ReadReq accesses
1094system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for demand accesses
1095system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363304 # mshr miss rate for demand accesses
1096system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for overall accesses
1097system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses
1098system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency
1099system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency
1100system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
1101system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
1102system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
1103system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
1104system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate

848system.cpu.icache.tags.replacements 994393 # number of replacements
849system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use
850system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks.
851system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks.
852system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks.
853system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit.
854system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor
855system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy
856system.cpu.icache.tags.occ_percent::total 0.996163 # Average percentage of cache occupancy
857system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
858system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
859system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
860system.cpu.icache.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id
861system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
862system.cpu.icache.tags.tag_accesses 10178850 # Number of tag accesses
863system.cpu.icache.tags.data_accesses 10178850 # Number of data accesses
864system.cpu.icache.ReadReq_hits::cpu.inst 8125717 # number of ReadReq hits
865system.cpu.icache.ReadReq_hits::total 8125717 # number of ReadReq hits
866system.cpu.icache.demand_hits::cpu.inst 8125717 # number of demand (read+write) hits
867system.cpu.icache.demand_hits::total 8125717 # number of demand (read+write) hits
868system.cpu.icache.overall_hits::cpu.inst 8125717 # number of overall hits
869system.cpu.icache.overall_hits::total 8125717 # number of overall hits
870system.cpu.icache.ReadReq_misses::cpu.inst 1058185 # number of ReadReq misses
871system.cpu.icache.ReadReq_misses::total 1058185 # number of ReadReq misses
872system.cpu.icache.demand_misses::cpu.inst 1058185 # number of demand (read+write) misses
873system.cpu.icache.demand_misses::total 1058185 # number of demand (read+write) misses
874system.cpu.icache.overall_misses::cpu.inst 1058185 # number of overall misses
875system.cpu.icache.overall_misses::total 1058185 # number of overall misses
876system.cpu.icache.ReadReq_miss_latency::cpu.inst 14693875503 # number of ReadReq miss cycles
877system.cpu.icache.ReadReq_miss_latency::total 14693875503 # number of ReadReq miss cycles
878system.cpu.icache.demand_miss_latency::cpu.inst 14693875503 # number of demand (read+write) miss cycles
879system.cpu.icache.demand_miss_latency::total 14693875503 # number of demand (read+write) miss cycles
880system.cpu.icache.overall_miss_latency::cpu.inst 14693875503 # number of overall miss cycles
881system.cpu.icache.overall_miss_latency::total 14693875503 # number of overall miss cycles
882system.cpu.icache.ReadReq_accesses::cpu.inst 9183902 # number of ReadReq accesses(hits+misses)
883system.cpu.icache.ReadReq_accesses::total 9183902 # number of ReadReq accesses(hits+misses)
884system.cpu.icache.demand_accesses::cpu.inst 9183902 # number of demand (read+write) accesses
885system.cpu.icache.demand_accesses::total 9183902 # number of demand (read+write) accesses
886system.cpu.icache.overall_accesses::cpu.inst 9183902 # number of overall (read+write) accesses
887system.cpu.icache.overall_accesses::total 9183902 # number of overall (read+write) accesses
888system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115222 # miss rate for ReadReq accesses
889system.cpu.icache.ReadReq_miss_rate::total 0.115222 # miss rate for ReadReq accesses
890system.cpu.icache.demand_miss_rate::cpu.inst 0.115222 # miss rate for demand accesses
891system.cpu.icache.demand_miss_rate::total 0.115222 # miss rate for demand accesses
892system.cpu.icache.overall_miss_rate::cpu.inst 0.115222 # miss rate for overall accesses
893system.cpu.icache.overall_miss_rate::total 0.115222 # miss rate for overall accesses
894system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069 # average ReadReq miss latency
895system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069 # average ReadReq miss latency
896system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
897system.cpu.icache.demand_avg_miss_latency::total 13885.923069 # average overall miss latency
898system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
899system.cpu.icache.overall_avg_miss_latency::total 13885.923069 # average overall miss latency
900system.cpu.icache.blocked_cycles::no_mshrs 7023 # number of cycles access was blocked
901system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
902system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
903system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
904system.cpu.icache.avg_blocked_cycles::no_mshrs 23.646465 # average number of cycles each access was blocked
905system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
906system.cpu.icache.fast_writes 0 # number of fast writes performed
907system.cpu.icache.cache_copies 0 # number of cache copies performed
908system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63237 # number of ReadReq MSHR hits
909system.cpu.icache.ReadReq_mshr_hits::total 63237 # number of ReadReq MSHR hits
910system.cpu.icache.demand_mshr_hits::cpu.inst 63237 # number of demand (read+write) MSHR hits
911system.cpu.icache.demand_mshr_hits::total 63237 # number of demand (read+write) MSHR hits
912system.cpu.icache.overall_mshr_hits::cpu.inst 63237 # number of overall MSHR hits
913system.cpu.icache.overall_mshr_hits::total 63237 # number of overall MSHR hits
914system.cpu.icache.ReadReq_mshr_misses::cpu.inst 994948 # number of ReadReq MSHR misses
915system.cpu.icache.ReadReq_mshr_misses::total 994948 # number of ReadReq MSHR misses
916system.cpu.icache.demand_mshr_misses::cpu.inst 994948 # number of demand (read+write) MSHR misses
917system.cpu.icache.demand_mshr_misses::total 994948 # number of demand (read+write) MSHR misses
918system.cpu.icache.overall_mshr_misses::cpu.inst 994948 # number of overall MSHR misses
919system.cpu.icache.overall_mshr_misses::total 994948 # number of overall MSHR misses
920system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12059629101 # number of ReadReq MSHR miss cycles
921system.cpu.icache.ReadReq_mshr_miss_latency::total 12059629101 # number of ReadReq MSHR miss cycles
922system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12059629101 # number of demand (read+write) MSHR miss cycles
923system.cpu.icache.demand_mshr_miss_latency::total 12059629101 # number of demand (read+write) MSHR miss cycles
924system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12059629101 # number of overall MSHR miss cycles
925system.cpu.icache.overall_mshr_miss_latency::total 12059629101 # number of overall MSHR miss cycles
926system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for ReadReq accesses
927system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108336 # mshr miss rate for ReadReq accesses
928system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for demand accesses
929system.cpu.icache.demand_mshr_miss_rate::total 0.108336 # mshr miss rate for demand accesses
930system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for overall accesses
931system.cpu.icache.overall_mshr_miss_rate::total 0.108336 # mshr miss rate for overall accesses
932system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704 # average ReadReq mshr miss latency
933system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704 # average ReadReq mshr miss latency
934system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
935system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
936system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
937system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
938system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
939system.cpu.itb_walker_cache.tags.replacements 14092 # number of replacements
940system.cpu.itb_walker_cache.tags.tagsinuse 6.014059 # Cycle average of tags in use
941system.cpu.itb_walker_cache.tags.total_refs 26262 # Total number of references to valid blocks.
942system.cpu.itb_walker_cache.tags.sampled_refs 14107 # Sample count of references to valid blocks.
943system.cpu.itb_walker_cache.tags.avg_refs 1.861629 # Average number of references to valid blocks.
944system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000 # Cycle when the warmup percentage was hit.
945system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.014059 # Average occupied blocks per requestor
946system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375879 # Average percentage of cache occupancy
947system.cpu.itb_walker_cache.tags.occ_percent::total 0.375879 # Average percentage of cache occupancy
948system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
949system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
950system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
951system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
952system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
953system.cpu.itb_walker_cache.tags.tag_accesses 97491 # Number of tag accesses
954system.cpu.itb_walker_cache.tags.data_accesses 97491 # Number of data accesses
955system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26263 # number of ReadReq hits
956system.cpu.itb_walker_cache.ReadReq_hits::total 26263 # number of ReadReq hits
957system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
958system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
959system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26265 # number of demand (read+write) hits
960system.cpu.itb_walker_cache.demand_hits::total 26265 # number of demand (read+write) hits
961system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26265 # number of overall hits
962system.cpu.itb_walker_cache.overall_hits::total 26265 # number of overall hits
963system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14987 # number of ReadReq misses
964system.cpu.itb_walker_cache.ReadReq_misses::total 14987 # number of ReadReq misses
965system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14987 # number of demand (read+write) misses
966system.cpu.itb_walker_cache.demand_misses::total 14987 # number of demand (read+write) misses
967system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14987 # number of overall misses
968system.cpu.itb_walker_cache.overall_misses::total 14987 # number of overall misses
969system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 174073497 # number of ReadReq miss cycles
970system.cpu.itb_walker_cache.ReadReq_miss_latency::total 174073497 # number of ReadReq miss cycles
971system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174073497 # number of demand (read+write) miss cycles
972system.cpu.itb_walker_cache.demand_miss_latency::total 174073497 # number of demand (read+write) miss cycles
973system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174073497 # number of overall miss cycles
974system.cpu.itb_walker_cache.overall_miss_latency::total 174073497 # number of overall miss cycles
975system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41250 # number of ReadReq accesses(hits+misses)
976system.cpu.itb_walker_cache.ReadReq_accesses::total 41250 # number of ReadReq accesses(hits+misses)
977system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
978system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
979system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41252 # number of demand (read+write) accesses
980system.cpu.itb_walker_cache.demand_accesses::total 41252 # number of demand (read+write) accesses
981system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41252 # number of overall (read+write) accesses
982system.cpu.itb_walker_cache.overall_accesses::total 41252 # number of overall (read+write) accesses
983system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363321 # miss rate for ReadReq accesses
984system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363321 # miss rate for ReadReq accesses
985system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363304 # miss rate for demand accesses
986system.cpu.itb_walker_cache.demand_miss_rate::total 0.363304 # miss rate for demand accesses
987system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363304 # miss rate for overall accesses
988system.cpu.itb_walker_cache.overall_miss_rate::total 0.363304 # miss rate for overall accesses
989system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104 # average ReadReq miss latency
990system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104 # average ReadReq miss latency
991system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
992system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104 # average overall miss latency
993system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
994system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104 # average overall miss latency
995system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
996system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
997system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
998system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
999system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1000system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1001system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1002system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1003system.cpu.itb_walker_cache.writebacks::writebacks 3303 # number of writebacks
1004system.cpu.itb_walker_cache.writebacks::total 3303 # number of writebacks
1005system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14987 # number of ReadReq MSHR misses
1006system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14987 # number of ReadReq MSHR misses
1007system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14987 # number of demand (read+write) MSHR misses
1008system.cpu.itb_walker_cache.demand_mshr_misses::total 14987 # number of demand (read+write) MSHR misses
1009system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14987 # number of overall MSHR misses
1010system.cpu.itb_walker_cache.overall_mshr_misses::total 14987 # number of overall MSHR misses
1011system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 144083525 # number of ReadReq MSHR miss cycles
1012system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144083525 # number of ReadReq MSHR miss cycles
1013system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144083525 # number of demand (read+write) MSHR miss cycles
1014system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144083525 # number of demand (read+write) MSHR miss cycles
1015system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144083525 # number of overall MSHR miss cycles
1016system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144083525 # number of overall MSHR miss cycles
1017system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363321 # mshr miss rate for ReadReq accesses
1018system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363321 # mshr miss rate for ReadReq accesses
1019system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for demand accesses
1020system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363304 # mshr miss rate for demand accesses
1021system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for overall accesses
1022system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses
1023system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency
1024system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency
1025system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
1026system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
1027system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
1028system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
1029system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate

1105system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements
1106system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use
1107system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks.
1108system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks.
1109system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks.
1110system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit.
1111system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor
1112system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy
1113system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy
1114system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
1115system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1116system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
1117system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
1118system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
1119system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses
1120system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses
1121system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits
1122system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits
1123system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits
1124system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits
1125system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits
1126system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits
1127system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses
1128system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses
1129system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses
1130system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses
1131system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses
1132system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses
1133system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles
1134system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles
1135system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles
1136system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles
1137system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles
1138system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles
1139system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses)
1140system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses)
1141system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses
1142system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses
1143system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses
1144system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses
1145system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses
1146system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses
1147system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses
1148system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses
1149system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses
1150system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses
1151system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency
1152system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency
1153system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
1154system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency
1155system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
1156system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency
1157system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1158system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1159system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1160system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1161system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1162system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1163system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
1164system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
1165system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks
1166system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks
1167system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses
1168system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses
1169system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses
1170system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses
1171system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses
1172system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses
1173system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles
1174system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles
1175system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles
1176system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles
1177system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles
1178system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles
1179system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses
1180system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses
1181system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses
1182system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses
1183system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses
1184system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses
1185system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency
1186system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency
1187system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
1188system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
1189system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
1190system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
1191system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1192system.cpu.dcache.tags.replacements 1657683 # number of replacements
1193system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use
1194system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks.
1195system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks.
1196system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks.
1197system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
1198system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor
1199system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
1200system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
1201system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1202system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
1203system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
1204system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
1205system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1206system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses
1207system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses
1208system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits
1209system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits
1210system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits
1211system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits
1212system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits
1213system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits
1214system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits
1215system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits
1216system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits
1217system.cpu.dcache.overall_hits::total 19128334 # number of overall hits
1218system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses
1219system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses
1220system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses
1221system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses
1222system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses
1223system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses
1224system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses
1225system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses
1226system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses
1227system.cpu.dcache.overall_misses::total 2535648 # number of overall misses
1228system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles
1229system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles
1230system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles
1231system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles
1232system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles
1233system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles
1234system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles
1235system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles
1236system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses)
1237system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses)
1238system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses)
1239system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses)
1240system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses)
1241system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses)
1242system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses
1243system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses
1244system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses
1245system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses
1246system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses
1247system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses
1248system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses
1249system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses
1250system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses
1251system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses
1252system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses
1253system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses
1254system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses
1255system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses
1256system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency
1257system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency
1258system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency
1259system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency
1260system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency
1261system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency
1262system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency
1263system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency
1264system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked
1265system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1266system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked
1267system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1268system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked
1269system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1270system.cpu.dcache.fast_writes 0 # number of fast writes performed
1271system.cpu.dcache.cache_copies 0 # number of cache copies performed
1272system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks
1273system.cpu.dcache.writebacks::total 1559289 # number of writebacks
1274system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits
1275system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits
1276system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits
1277system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits
1278system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits
1279system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits
1280system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits
1281system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits
1282system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses
1283system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses
1284system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses
1285system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses
1286system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses
1287system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses
1288system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses
1289system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses
1290system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses
1291system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses
1292system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles
1293system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles
1294system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles
1295system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles
1296system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles
1297system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles
1298system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles
1299system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles
1300system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles
1301system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles
1302system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles
1303system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles
1304system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles
1305system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles
1306system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles
1307system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles
1308system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses
1309system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses
1310system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses
1311system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses
1312system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses
1313system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses
1314system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses
1315system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses
1316system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses
1317system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses
1318system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency
1319system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency
1320system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency
1321system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency
1322system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency
1323system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency
1324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency
1325system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency
1326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency
1327system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency
1328system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1329system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1330system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1331system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1332system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1333system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1334system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

1335system.cpu.l2cache.tags.replacements 113085 # number of replacements
1336system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use
1337system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks.
1338system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks.
1339system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks.
1340system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1341system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor
1342system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor
1343system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143343 # Average occupied blocks per requestor
1344system.cpu.l2cache.tags.occ_blocks::cpu.inst 3264.453296 # Average occupied blocks per requestor
1345system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488 # Average occupied blocks per requestor
1346system.cpu.l2cache.tags.occ_percent::writebacks 0.769536 # Average percentage of cache occupancy
1347system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy
1348system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1349system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049812 # Average percentage of cache occupancy
1350system.cpu.l2cache.tags.occ_percent::cpu.data 0.169353 # Average percentage of cache occupancy
1351system.cpu.l2cache.tags.occ_percent::total 0.989050 # Average percentage of cache occupancy
1352system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id
1353system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
1354system.cpu.l2cache.tags.age_task_id_blocks_1024::1 634 # Occupied blocks per task id
1355system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id
1356system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5793 # Occupied blocks per task id
1357system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54091 # Occupied blocks per task id
1358system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id
1359system.cpu.l2cache.tags.tag_accesses 35031209 # Number of tag accesses
1360system.cpu.l2cache.tags.data_accesses 35031209 # Number of data accesses
1361system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68532 # number of ReadReq hits
1362system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12501 # number of ReadReq hits
1363system.cpu.l2cache.ReadReq_hits::cpu.inst 978548 # number of ReadReq hits
1364system.cpu.l2cache.ReadReq_hits::cpu.data 1334624 # number of ReadReq hits
1365system.cpu.l2cache.ReadReq_hits::total 2394205 # number of ReadReq hits
1366system.cpu.l2cache.Writeback_hits::writebacks 1584468 # number of Writeback hits
1367system.cpu.l2cache.Writeback_hits::total 1584468 # number of Writeback hits
1368system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
1369system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits
1370system.cpu.l2cache.ReadExReq_hits::cpu.data 153669 # number of ReadExReq hits
1371system.cpu.l2cache.ReadExReq_hits::total 153669 # number of ReadExReq hits
1372system.cpu.l2cache.demand_hits::cpu.dtb.walker 68532 # number of demand (read+write) hits
1373system.cpu.l2cache.demand_hits::cpu.itb.walker 12501 # number of demand (read+write) hits
1374system.cpu.l2cache.demand_hits::cpu.inst 978548 # number of demand (read+write) hits
1375system.cpu.l2cache.demand_hits::cpu.data 1488293 # number of demand (read+write) hits
1376system.cpu.l2cache.demand_hits::total 2547874 # number of demand (read+write) hits
1377system.cpu.l2cache.overall_hits::cpu.dtb.walker 68532 # number of overall hits
1378system.cpu.l2cache.overall_hits::cpu.itb.walker 12501 # number of overall hits
1379system.cpu.l2cache.overall_hits::cpu.inst 978548 # number of overall hits
1380system.cpu.l2cache.overall_hits::cpu.data 1488293 # number of overall hits
1381system.cpu.l2cache.overall_hits::total 2547874 # number of overall hits
1382system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 75 # number of ReadReq misses
1383system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
1384system.cpu.l2cache.ReadReq_misses::cpu.inst 16312 # number of ReadReq misses
1385system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses
1386system.cpu.l2cache.ReadReq_misses::total 52269 # number of ReadReq misses
1387system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses
1388system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses
1389system.cpu.l2cache.ReadExReq_misses::cpu.data 133393 # number of ReadExReq misses
1390system.cpu.l2cache.ReadExReq_misses::total 133393 # number of ReadExReq misses
1391system.cpu.l2cache.demand_misses::cpu.dtb.walker 75 # number of demand (read+write) misses
1392system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1393system.cpu.l2cache.demand_misses::cpu.inst 16312 # number of demand (read+write) misses
1394system.cpu.l2cache.demand_misses::cpu.data 169268 # number of demand (read+write) misses
1395system.cpu.l2cache.demand_misses::total 185662 # number of demand (read+write) misses
1396system.cpu.l2cache.overall_misses::cpu.dtb.walker 75 # number of overall misses
1397system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1398system.cpu.l2cache.overall_misses::cpu.inst 16312 # number of overall misses
1399system.cpu.l2cache.overall_misses::cpu.data 169268 # number of overall misses
1400system.cpu.l2cache.overall_misses::total 185662 # number of overall misses
1401system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6508500 # number of ReadReq miss cycles
1402system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 560500 # number of ReadReq miss cycles
1403system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1253827000 # number of ReadReq miss cycles
1404system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2884413497 # number of ReadReq miss cycles
1405system.cpu.l2cache.ReadReq_miss_latency::total 4145309497 # number of ReadReq miss cycles
1406system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16150808 # number of UpgradeReq miss cycles
1407system.cpu.l2cache.UpgradeReq_miss_latency::total 16150808 # number of UpgradeReq miss cycles
1408system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9313802457 # number of ReadExReq miss cycles
1409system.cpu.l2cache.ReadExReq_miss_latency::total 9313802457 # number of ReadExReq miss cycles
1410system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6508500 # number of demand (read+write) miss cycles
1411system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 560500 # number of demand (read+write) miss cycles
1412system.cpu.l2cache.demand_miss_latency::cpu.inst 1253827000 # number of demand (read+write) miss cycles
1413system.cpu.l2cache.demand_miss_latency::cpu.data 12198215954 # number of demand (read+write) miss cycles
1414system.cpu.l2cache.demand_miss_latency::total 13459111954 # number of demand (read+write) miss cycles
1415system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6508500 # number of overall miss cycles
1416system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 560500 # number of overall miss cycles
1417system.cpu.l2cache.overall_miss_latency::cpu.inst 1253827000 # number of overall miss cycles
1418system.cpu.l2cache.overall_miss_latency::cpu.data 12198215954 # number of overall miss cycles
1419system.cpu.l2cache.overall_miss_latency::total 13459111954 # number of overall miss cycles
1420system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68607 # number of ReadReq accesses(hits+misses)
1421system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12508 # number of ReadReq accesses(hits+misses)
1422system.cpu.l2cache.ReadReq_accesses::cpu.inst 994860 # number of ReadReq accesses(hits+misses)
1423system.cpu.l2cache.ReadReq_accesses::cpu.data 1370499 # number of ReadReq accesses(hits+misses)
1424system.cpu.l2cache.ReadReq_accesses::total 2446474 # number of ReadReq accesses(hits+misses)
1425system.cpu.l2cache.Writeback_accesses::writebacks 1584468 # number of Writeback accesses(hits+misses)
1426system.cpu.l2cache.Writeback_accesses::total 1584468 # number of Writeback accesses(hits+misses)
1427system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1753 # number of UpgradeReq accesses(hits+misses)
1428system.cpu.l2cache.UpgradeReq_accesses::total 1753 # number of UpgradeReq accesses(hits+misses)
1429system.cpu.l2cache.ReadExReq_accesses::cpu.data 287062 # number of ReadExReq accesses(hits+misses)
1430system.cpu.l2cache.ReadExReq_accesses::total 287062 # number of ReadExReq accesses(hits+misses)
1431system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68607 # number of demand (read+write) accesses
1432system.cpu.l2cache.demand_accesses::cpu.itb.walker 12508 # number of demand (read+write) accesses
1433system.cpu.l2cache.demand_accesses::cpu.inst 994860 # number of demand (read+write) accesses
1434system.cpu.l2cache.demand_accesses::cpu.data 1657561 # number of demand (read+write) accesses
1435system.cpu.l2cache.demand_accesses::total 2733536 # number of demand (read+write) accesses
1436system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68607 # number of overall (read+write) accesses
1437system.cpu.l2cache.overall_accesses::cpu.itb.walker 12508 # number of overall (read+write) accesses
1438system.cpu.l2cache.overall_accesses::cpu.inst 994860 # number of overall (read+write) accesses
1439system.cpu.l2cache.overall_accesses::cpu.data 1657561 # number of overall (read+write) accesses
1440system.cpu.l2cache.overall_accesses::total 2733536 # number of overall (read+write) accesses
1441system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001093 # miss rate for ReadReq accesses
1442system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000560 # miss rate for ReadReq accesses
1443system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016396 # miss rate for ReadReq accesses
1444system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026177 # miss rate for ReadReq accesses
1445system.cpu.l2cache.ReadReq_miss_rate::total 0.021365 # miss rate for ReadReq accesses
1446system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823731 # miss rate for UpgradeReq accesses
1447system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823731 # miss rate for UpgradeReq accesses
1448system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464684 # miss rate for ReadExReq accesses
1449system.cpu.l2cache.ReadExReq_miss_rate::total 0.464684 # miss rate for ReadExReq accesses
1450system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001093 # miss rate for demand accesses
1451system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000560 # miss rate for demand accesses
1452system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016396 # miss rate for demand accesses
1453system.cpu.l2cache.demand_miss_rate::cpu.data 0.102119 # miss rate for demand accesses
1454system.cpu.l2cache.demand_miss_rate::total 0.067920 # miss rate for demand accesses
1455system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001093 # miss rate for overall accesses
1456system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000560 # miss rate for overall accesses
1457system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016396 # miss rate for overall accesses
1458system.cpu.l2cache.overall_miss_rate::cpu.data 0.102119 # miss rate for overall accesses
1459system.cpu.l2cache.overall_miss_rate::total 0.067920 # miss rate for overall accesses
1460system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86780 # average ReadReq miss latency
1461system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571 # average ReadReq miss latency
1462system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879 # average ReadReq miss latency
1463system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80401.769951 # average ReadReq miss latency
1464system.cpu.l2cache.ReadReq_avg_miss_latency::total 79307.227936 # average ReadReq miss latency
1465system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11184.770083 # average UpgradeReq miss latency
1466system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11184.770083 # average UpgradeReq miss latency
1467system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69822.272960 # average ReadExReq miss latency
1468system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69822.272960 # average ReadExReq miss latency
1469system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
1470system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
1471system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency
1472system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
1473system.cpu.l2cache.demand_avg_miss_latency::total 72492.550732 # average overall miss latency
1474system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
1475system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
1476system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency
1477system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
1478system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732 # average overall miss latency
1479system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1480system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1481system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1482system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1483system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1484system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1485system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1486system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1487system.cpu.l2cache.writebacks::writebacks 103196 # number of writebacks
1488system.cpu.l2cache.writebacks::total 103196 # number of writebacks
1489system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
1490system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1491system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1492system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1493system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1494system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1495system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1496system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1497system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1498system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 75 # number of ReadReq MSHR misses
1499system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
1500system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16310 # number of ReadReq MSHR misses
1501system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35874 # number of ReadReq MSHR misses
1502system.cpu.l2cache.ReadReq_mshr_misses::total 52266 # number of ReadReq MSHR misses
1503system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses
1504system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses
1505system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133393 # number of ReadExReq MSHR misses
1506system.cpu.l2cache.ReadExReq_mshr_misses::total 133393 # number of ReadExReq MSHR misses
1507system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 75 # number of demand (read+write) MSHR misses
1508system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1509system.cpu.l2cache.demand_mshr_misses::cpu.inst 16310 # number of demand (read+write) MSHR misses
1510system.cpu.l2cache.demand_mshr_misses::cpu.data 169267 # number of demand (read+write) MSHR misses
1511system.cpu.l2cache.demand_mshr_misses::total 185659 # number of demand (read+write) MSHR misses
1512system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 75 # number of overall MSHR misses
1513system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1514system.cpu.l2cache.overall_mshr_misses::cpu.inst 16310 # number of overall MSHR misses
1515system.cpu.l2cache.overall_mshr_misses::cpu.data 169267 # number of overall MSHR misses
1516system.cpu.l2cache.overall_mshr_misses::total 185659 # number of overall MSHR misses
1517system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5579000 # number of ReadReq MSHR miss cycles
1518system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 473000 # number of ReadReq MSHR miss cycles
1519system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049198000 # number of ReadReq MSHR miss cycles
1520system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2439336749 # number of ReadReq MSHR miss cycles
1521system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3494586749 # number of ReadReq MSHR miss cycles
1522system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14472940 # number of UpgradeReq MSHR miss cycles
1523system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14472940 # number of UpgradeReq MSHR miss cycles
1524system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7638617543 # number of ReadExReq MSHR miss cycles
1525system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7638617543 # number of ReadExReq MSHR miss cycles
1526system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5579000 # number of demand (read+write) MSHR miss cycles
1527system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 473000 # number of demand (read+write) MSHR miss cycles
1528system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049198000 # number of demand (read+write) MSHR miss cycles
1529system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10077954292 # number of demand (read+write) MSHR miss cycles
1530system.cpu.l2cache.demand_mshr_miss_latency::total 11133204292 # number of demand (read+write) MSHR miss cycles
1531system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5579000 # number of overall MSHR miss cycles
1532system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 473000 # number of overall MSHR miss cycles
1533system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049198000 # number of overall MSHR miss cycles
1534system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10077954292 # number of overall MSHR miss cycles
1535system.cpu.l2cache.overall_mshr_miss_latency::total 11133204292 # number of overall MSHR miss cycles
1536system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275584000 # number of ReadReq MSHR uncacheable cycles
1537system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275584000 # number of ReadReq MSHR uncacheable cycles
1538system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397149000 # number of WriteReq MSHR uncacheable cycles
1539system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397149000 # number of WriteReq MSHR uncacheable cycles
1540system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672733000 # number of overall MSHR uncacheable cycles
1541system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672733000 # number of overall MSHR uncacheable cycles
1542system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for ReadReq accesses
1543system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for ReadReq accesses
1544system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for ReadReq accesses
1545system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026176 # mshr miss rate for ReadReq accesses
1546system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021364 # mshr miss rate for ReadReq accesses
1547system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823731 # mshr miss rate for UpgradeReq accesses
1548system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823731 # mshr miss rate for UpgradeReq accesses
1549system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464684 # mshr miss rate for ReadExReq accesses
1550system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464684 # mshr miss rate for ReadExReq accesses
1551system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for demand accesses
1552system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for demand accesses
1553system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for demand accesses
1554system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for demand accesses
1555system.cpu.l2cache.demand_mshr_miss_rate::total 0.067919 # mshr miss rate for demand accesses
1556system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for overall accesses
1557system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for overall accesses
1558system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for overall accesses
1559system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for overall accesses
1560system.cpu.l2cache.overall_mshr_miss_rate::total 0.067919 # mshr miss rate for overall accesses
1561system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average ReadReq mshr miss latency
1562system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average ReadReq mshr miss latency
1563system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116 # average ReadReq mshr miss latency
1564system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846 # average ReadReq mshr miss latency
1565system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687 # average ReadReq mshr miss latency
1566system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634 # average UpgradeReq mshr miss latency
1567system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634 # average UpgradeReq mshr miss latency
1568system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930 # average ReadExReq mshr miss latency
1569system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930 # average ReadExReq mshr miss latency
1570system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
1571system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
1572system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
1573system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
1574system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
1575system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
1576system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
1577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
1578system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
1579system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
1580system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1581system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1582system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1583system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1584system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1585system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1586system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1030system.cpu.l2cache.tags.replacements 113085 # number of replacements
1031system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use
1032system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks.
1033system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks.
1034system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks.
1035system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1036system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor
1037system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor
1038system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143343 # Average occupied blocks per requestor
1039system.cpu.l2cache.tags.occ_blocks::cpu.inst 3264.453296 # Average occupied blocks per requestor
1040system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488 # Average occupied blocks per requestor
1041system.cpu.l2cache.tags.occ_percent::writebacks 0.769536 # Average percentage of cache occupancy
1042system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy
1043system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1044system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049812 # Average percentage of cache occupancy
1045system.cpu.l2cache.tags.occ_percent::cpu.data 0.169353 # Average percentage of cache occupancy
1046system.cpu.l2cache.tags.occ_percent::total 0.989050 # Average percentage of cache occupancy
1047system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id
1048system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
1049system.cpu.l2cache.tags.age_task_id_blocks_1024::1 634 # Occupied blocks per task id
1050system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id
1051system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5793 # Occupied blocks per task id
1052system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54091 # Occupied blocks per task id
1053system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id
1054system.cpu.l2cache.tags.tag_accesses 35031209 # Number of tag accesses
1055system.cpu.l2cache.tags.data_accesses 35031209 # Number of data accesses
1056system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68532 # number of ReadReq hits
1057system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12501 # number of ReadReq hits
1058system.cpu.l2cache.ReadReq_hits::cpu.inst 978548 # number of ReadReq hits
1059system.cpu.l2cache.ReadReq_hits::cpu.data 1334624 # number of ReadReq hits
1060system.cpu.l2cache.ReadReq_hits::total 2394205 # number of ReadReq hits
1061system.cpu.l2cache.Writeback_hits::writebacks 1584468 # number of Writeback hits
1062system.cpu.l2cache.Writeback_hits::total 1584468 # number of Writeback hits
1063system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
1064system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits
1065system.cpu.l2cache.ReadExReq_hits::cpu.data 153669 # number of ReadExReq hits
1066system.cpu.l2cache.ReadExReq_hits::total 153669 # number of ReadExReq hits
1067system.cpu.l2cache.demand_hits::cpu.dtb.walker 68532 # number of demand (read+write) hits
1068system.cpu.l2cache.demand_hits::cpu.itb.walker 12501 # number of demand (read+write) hits
1069system.cpu.l2cache.demand_hits::cpu.inst 978548 # number of demand (read+write) hits
1070system.cpu.l2cache.demand_hits::cpu.data 1488293 # number of demand (read+write) hits
1071system.cpu.l2cache.demand_hits::total 2547874 # number of demand (read+write) hits
1072system.cpu.l2cache.overall_hits::cpu.dtb.walker 68532 # number of overall hits
1073system.cpu.l2cache.overall_hits::cpu.itb.walker 12501 # number of overall hits
1074system.cpu.l2cache.overall_hits::cpu.inst 978548 # number of overall hits
1075system.cpu.l2cache.overall_hits::cpu.data 1488293 # number of overall hits
1076system.cpu.l2cache.overall_hits::total 2547874 # number of overall hits
1077system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 75 # number of ReadReq misses
1078system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
1079system.cpu.l2cache.ReadReq_misses::cpu.inst 16312 # number of ReadReq misses
1080system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses
1081system.cpu.l2cache.ReadReq_misses::total 52269 # number of ReadReq misses
1082system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses
1083system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses
1084system.cpu.l2cache.ReadExReq_misses::cpu.data 133393 # number of ReadExReq misses
1085system.cpu.l2cache.ReadExReq_misses::total 133393 # number of ReadExReq misses
1086system.cpu.l2cache.demand_misses::cpu.dtb.walker 75 # number of demand (read+write) misses
1087system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1088system.cpu.l2cache.demand_misses::cpu.inst 16312 # number of demand (read+write) misses
1089system.cpu.l2cache.demand_misses::cpu.data 169268 # number of demand (read+write) misses
1090system.cpu.l2cache.demand_misses::total 185662 # number of demand (read+write) misses
1091system.cpu.l2cache.overall_misses::cpu.dtb.walker 75 # number of overall misses
1092system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1093system.cpu.l2cache.overall_misses::cpu.inst 16312 # number of overall misses
1094system.cpu.l2cache.overall_misses::cpu.data 169268 # number of overall misses
1095system.cpu.l2cache.overall_misses::total 185662 # number of overall misses
1096system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6508500 # number of ReadReq miss cycles
1097system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 560500 # number of ReadReq miss cycles
1098system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1253827000 # number of ReadReq miss cycles
1099system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2884413497 # number of ReadReq miss cycles
1100system.cpu.l2cache.ReadReq_miss_latency::total 4145309497 # number of ReadReq miss cycles
1101system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16150808 # number of UpgradeReq miss cycles
1102system.cpu.l2cache.UpgradeReq_miss_latency::total 16150808 # number of UpgradeReq miss cycles
1103system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9313802457 # number of ReadExReq miss cycles
1104system.cpu.l2cache.ReadExReq_miss_latency::total 9313802457 # number of ReadExReq miss cycles
1105system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6508500 # number of demand (read+write) miss cycles
1106system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 560500 # number of demand (read+write) miss cycles
1107system.cpu.l2cache.demand_miss_latency::cpu.inst 1253827000 # number of demand (read+write) miss cycles
1108system.cpu.l2cache.demand_miss_latency::cpu.data 12198215954 # number of demand (read+write) miss cycles
1109system.cpu.l2cache.demand_miss_latency::total 13459111954 # number of demand (read+write) miss cycles
1110system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6508500 # number of overall miss cycles
1111system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 560500 # number of overall miss cycles
1112system.cpu.l2cache.overall_miss_latency::cpu.inst 1253827000 # number of overall miss cycles
1113system.cpu.l2cache.overall_miss_latency::cpu.data 12198215954 # number of overall miss cycles
1114system.cpu.l2cache.overall_miss_latency::total 13459111954 # number of overall miss cycles
1115system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68607 # number of ReadReq accesses(hits+misses)
1116system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12508 # number of ReadReq accesses(hits+misses)
1117system.cpu.l2cache.ReadReq_accesses::cpu.inst 994860 # number of ReadReq accesses(hits+misses)
1118system.cpu.l2cache.ReadReq_accesses::cpu.data 1370499 # number of ReadReq accesses(hits+misses)
1119system.cpu.l2cache.ReadReq_accesses::total 2446474 # number of ReadReq accesses(hits+misses)
1120system.cpu.l2cache.Writeback_accesses::writebacks 1584468 # number of Writeback accesses(hits+misses)
1121system.cpu.l2cache.Writeback_accesses::total 1584468 # number of Writeback accesses(hits+misses)
1122system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1753 # number of UpgradeReq accesses(hits+misses)
1123system.cpu.l2cache.UpgradeReq_accesses::total 1753 # number of UpgradeReq accesses(hits+misses)
1124system.cpu.l2cache.ReadExReq_accesses::cpu.data 287062 # number of ReadExReq accesses(hits+misses)
1125system.cpu.l2cache.ReadExReq_accesses::total 287062 # number of ReadExReq accesses(hits+misses)
1126system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68607 # number of demand (read+write) accesses
1127system.cpu.l2cache.demand_accesses::cpu.itb.walker 12508 # number of demand (read+write) accesses
1128system.cpu.l2cache.demand_accesses::cpu.inst 994860 # number of demand (read+write) accesses
1129system.cpu.l2cache.demand_accesses::cpu.data 1657561 # number of demand (read+write) accesses
1130system.cpu.l2cache.demand_accesses::total 2733536 # number of demand (read+write) accesses
1131system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68607 # number of overall (read+write) accesses
1132system.cpu.l2cache.overall_accesses::cpu.itb.walker 12508 # number of overall (read+write) accesses
1133system.cpu.l2cache.overall_accesses::cpu.inst 994860 # number of overall (read+write) accesses
1134system.cpu.l2cache.overall_accesses::cpu.data 1657561 # number of overall (read+write) accesses
1135system.cpu.l2cache.overall_accesses::total 2733536 # number of overall (read+write) accesses
1136system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001093 # miss rate for ReadReq accesses
1137system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000560 # miss rate for ReadReq accesses
1138system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016396 # miss rate for ReadReq accesses
1139system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026177 # miss rate for ReadReq accesses
1140system.cpu.l2cache.ReadReq_miss_rate::total 0.021365 # miss rate for ReadReq accesses
1141system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823731 # miss rate for UpgradeReq accesses
1142system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823731 # miss rate for UpgradeReq accesses
1143system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464684 # miss rate for ReadExReq accesses
1144system.cpu.l2cache.ReadExReq_miss_rate::total 0.464684 # miss rate for ReadExReq accesses
1145system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001093 # miss rate for demand accesses
1146system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000560 # miss rate for demand accesses
1147system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016396 # miss rate for demand accesses
1148system.cpu.l2cache.demand_miss_rate::cpu.data 0.102119 # miss rate for demand accesses
1149system.cpu.l2cache.demand_miss_rate::total 0.067920 # miss rate for demand accesses
1150system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001093 # miss rate for overall accesses
1151system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000560 # miss rate for overall accesses
1152system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016396 # miss rate for overall accesses
1153system.cpu.l2cache.overall_miss_rate::cpu.data 0.102119 # miss rate for overall accesses
1154system.cpu.l2cache.overall_miss_rate::total 0.067920 # miss rate for overall accesses
1155system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86780 # average ReadReq miss latency
1156system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571 # average ReadReq miss latency
1157system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879 # average ReadReq miss latency
1158system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80401.769951 # average ReadReq miss latency
1159system.cpu.l2cache.ReadReq_avg_miss_latency::total 79307.227936 # average ReadReq miss latency
1160system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11184.770083 # average UpgradeReq miss latency
1161system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11184.770083 # average UpgradeReq miss latency
1162system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69822.272960 # average ReadExReq miss latency
1163system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69822.272960 # average ReadExReq miss latency
1164system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
1165system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
1166system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency
1167system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
1168system.cpu.l2cache.demand_avg_miss_latency::total 72492.550732 # average overall miss latency
1169system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
1170system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
1171system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency
1172system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
1173system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732 # average overall miss latency
1174system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1175system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1176system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1177system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1178system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1179system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1180system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1181system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1182system.cpu.l2cache.writebacks::writebacks 103196 # number of writebacks
1183system.cpu.l2cache.writebacks::total 103196 # number of writebacks
1184system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
1185system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1186system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1187system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1188system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1189system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1190system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1191system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1192system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1193system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 75 # number of ReadReq MSHR misses
1194system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
1195system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16310 # number of ReadReq MSHR misses
1196system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35874 # number of ReadReq MSHR misses
1197system.cpu.l2cache.ReadReq_mshr_misses::total 52266 # number of ReadReq MSHR misses
1198system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses
1199system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses
1200system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133393 # number of ReadExReq MSHR misses
1201system.cpu.l2cache.ReadExReq_mshr_misses::total 133393 # number of ReadExReq MSHR misses
1202system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 75 # number of demand (read+write) MSHR misses
1203system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1204system.cpu.l2cache.demand_mshr_misses::cpu.inst 16310 # number of demand (read+write) MSHR misses
1205system.cpu.l2cache.demand_mshr_misses::cpu.data 169267 # number of demand (read+write) MSHR misses
1206system.cpu.l2cache.demand_mshr_misses::total 185659 # number of demand (read+write) MSHR misses
1207system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 75 # number of overall MSHR misses
1208system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1209system.cpu.l2cache.overall_mshr_misses::cpu.inst 16310 # number of overall MSHR misses
1210system.cpu.l2cache.overall_mshr_misses::cpu.data 169267 # number of overall MSHR misses
1211system.cpu.l2cache.overall_mshr_misses::total 185659 # number of overall MSHR misses
1212system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5579000 # number of ReadReq MSHR miss cycles
1213system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 473000 # number of ReadReq MSHR miss cycles
1214system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049198000 # number of ReadReq MSHR miss cycles
1215system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2439336749 # number of ReadReq MSHR miss cycles
1216system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3494586749 # number of ReadReq MSHR miss cycles
1217system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14472940 # number of UpgradeReq MSHR miss cycles
1218system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14472940 # number of UpgradeReq MSHR miss cycles
1219system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7638617543 # number of ReadExReq MSHR miss cycles
1220system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7638617543 # number of ReadExReq MSHR miss cycles
1221system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5579000 # number of demand (read+write) MSHR miss cycles
1222system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 473000 # number of demand (read+write) MSHR miss cycles
1223system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049198000 # number of demand (read+write) MSHR miss cycles
1224system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10077954292 # number of demand (read+write) MSHR miss cycles
1225system.cpu.l2cache.demand_mshr_miss_latency::total 11133204292 # number of demand (read+write) MSHR miss cycles
1226system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5579000 # number of overall MSHR miss cycles
1227system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 473000 # number of overall MSHR miss cycles
1228system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049198000 # number of overall MSHR miss cycles
1229system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10077954292 # number of overall MSHR miss cycles
1230system.cpu.l2cache.overall_mshr_miss_latency::total 11133204292 # number of overall MSHR miss cycles
1231system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275584000 # number of ReadReq MSHR uncacheable cycles
1232system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275584000 # number of ReadReq MSHR uncacheable cycles
1233system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397149000 # number of WriteReq MSHR uncacheable cycles
1234system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397149000 # number of WriteReq MSHR uncacheable cycles
1235system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672733000 # number of overall MSHR uncacheable cycles
1236system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672733000 # number of overall MSHR uncacheable cycles
1237system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for ReadReq accesses
1238system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for ReadReq accesses
1239system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for ReadReq accesses
1240system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026176 # mshr miss rate for ReadReq accesses
1241system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021364 # mshr miss rate for ReadReq accesses
1242system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823731 # mshr miss rate for UpgradeReq accesses
1243system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823731 # mshr miss rate for UpgradeReq accesses
1244system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464684 # mshr miss rate for ReadExReq accesses
1245system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464684 # mshr miss rate for ReadExReq accesses
1246system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for demand accesses
1247system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for demand accesses
1248system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for demand accesses
1249system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for demand accesses
1250system.cpu.l2cache.demand_mshr_miss_rate::total 0.067919 # mshr miss rate for demand accesses
1251system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for overall accesses
1252system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for overall accesses
1253system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for overall accesses
1254system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for overall accesses
1255system.cpu.l2cache.overall_mshr_miss_rate::total 0.067919 # mshr miss rate for overall accesses
1256system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average ReadReq mshr miss latency
1257system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average ReadReq mshr miss latency
1258system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116 # average ReadReq mshr miss latency
1259system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846 # average ReadReq mshr miss latency
1260system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687 # average ReadReq mshr miss latency
1261system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634 # average UpgradeReq mshr miss latency
1262system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634 # average UpgradeReq mshr miss latency
1263system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930 # average ReadExReq mshr miss latency
1264system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930 # average ReadExReq mshr miss latency
1265system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
1266system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
1267system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
1268system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
1269system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
1270system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
1271system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
1272system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
1273system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
1274system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
1275system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1276system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1277system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1278system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1279system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1280system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1281system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1282system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution
1283system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution
1284system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
1285system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
1286system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution
1287system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
1288system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
1289system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
1290system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution
1291system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution
1292system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution
1293system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes)
1294system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes)
1295system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes)
1296system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes)
1297system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes)
1298system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes)
1299system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes)
1300system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes)
1301system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes)
1302system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes)
1303system.cpu.toL2Bus.snoops 58568 # Total snoops (count)
1304system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram
1305system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram
1306system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram
1307system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1308system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1309system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1310system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1311system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram
1312system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram
1313system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1314system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1315system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1316system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram
1317system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks)
1318system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1319system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks)
1320system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1321system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks)
1322system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1323system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks)
1324system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1325system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks)
1326system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1327system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks)
1328system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1329system.iobus.trans_dist::ReadReq 225681 # Transaction distribution
1330system.iobus.trans_dist::ReadResp 225681 # Transaction distribution
1331system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
1332system.iobus.trans_dist::WriteResp 57721 # Transaction distribution
1333system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
1334system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
1335system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1336system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1337system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1338system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1339system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1340system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1341system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1342system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1343system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
1344system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1345system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
1346system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1347system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
1348system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1349system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1350system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1351system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1352system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1353system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
1354system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
1355system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
1356system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
1357system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
1358system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes)
1359system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1360system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1361system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1362system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1363system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1364system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1365system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1366system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1367system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
1368system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1369system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
1370system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1371system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
1372system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1373system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1374system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1375system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1376system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1377system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
1378system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
1379system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
1380system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
1381system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
1382system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes)
1383system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks)
1384system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1385system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1386system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1387system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1388system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1389system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
1390system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1391system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1392system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1393system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1394system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1395system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1396system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1397system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1398system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1399system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1400system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1401system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
1402system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1403system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1404system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1405system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1406system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1407system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
1408system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
1409system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
1410system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1411system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
1412system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1413system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1414system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1415system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1416system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1417system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
1418system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1419system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks)
1420system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1421system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
1422system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1423system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
1424system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1425system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks)
1426system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1427system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
1428system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1429system.iocache.tags.replacements 47575 # number of replacements
1430system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use
1431system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1432system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
1433system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1434system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit.
1435system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor
1436system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy
1437system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy
1438system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1439system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1440system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1441system.iocache.tags.tag_accesses 428670 # Number of tag accesses
1442system.iocache.tags.data_accesses 428670 # Number of data accesses
1443system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
1444system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
1445system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
1446system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
1447system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
1448system.iocache.demand_misses::total 910 # number of demand (read+write) misses
1449system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
1450system.iocache.overall_misses::total 910 # number of overall misses
1451system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles
1452system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles
1453system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles
1454system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles
1455system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles
1456system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles
1457system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
1458system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
1459system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1460system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1461system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
1462system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
1463system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
1464system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
1465system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1466system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1467system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1468system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1469system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1470system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1471system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency
1472system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency
1473system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
1474system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency
1475system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
1476system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency
1477system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
1478system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1479system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
1480system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1481system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
1482system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1483system.iocache.fast_writes 46720 # number of fast writes performed
1484system.iocache.cache_copies 0 # number of cache copies performed
1485system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
1486system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
1487system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
1488system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
1489system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
1490system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
1491system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles
1492system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles
1493system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles
1494system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles
1495system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles
1496system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles
1497system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles
1498system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
1499system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1500system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1501system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1502system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1503system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1504system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1505system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
1506system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
1507system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
1508system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
1509system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
1510system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
1511system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
1512system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
1513system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1514system.membus.trans_dist::ReadReq 662592 # Transaction distribution
1515system.membus.trans_dist::ReadResp 662582 # Transaction distribution
1516system.membus.trans_dist::WriteReq 13889 # Transaction distribution
1517system.membus.trans_dist::WriteResp 13889 # Transaction distribution
1518system.membus.trans_dist::Writeback 103196 # Transaction distribution
1519system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1520system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1521system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution
1522system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
1523system.membus.trans_dist::ReadExReq 133104 # Transaction distribution
1524system.membus.trans_dist::ReadExResp 133101 # Transaction distribution
1525system.membus.trans_dist::MessageReq 1644 # Transaction distribution
1526system.membus.trans_dist::MessageResp 1644 # Transaction distribution
1527system.membus.trans_dist::BadAddressError 10 # Transaction distribution
1528system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
1529system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
1530system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
1531system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
1532system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes)
1533system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes)
1534system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes)
1535system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes)
1536system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes)
1537system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes)
1538system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
1539system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
1540system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
1541system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
1542system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes)
1543system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes)
1544system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
1545system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
1546system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes)
1547system.membus.snoops 949 # Total snoops (count)
1548system.membus.snoop_fanout::samples 338415 # Request fanout histogram
1549system.membus.snoop_fanout::mean 1 # Request fanout histogram
1550system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1551system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1552system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1553system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram
1554system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1555system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1556system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1557system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1558system.membus.snoop_fanout::total 338415 # Request fanout histogram
1559system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks)
1560system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1561system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks)
1562system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1563system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
1564system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1565system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks)
1566system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1567system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
1568system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1569system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
1570system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1571system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks)
1572system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
1573system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks)
1574system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1575system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1576system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1577system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
1578system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1579system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1580system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1581system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1582system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1583system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1584system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1585system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1586system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.