1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.172174 # Number of seconds simulated
4sim_ticks 5172174196500 # Number of ticks simulated
5final_tick 5172174196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 197854 # Simulator instruction rate (inst/s)
8host_op_rate 391125 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2509698416 # Simulator tick rate (ticks/s)
10host_mem_usage 367744 # Number of bytes of host memory used
11host_seconds 2060.87 # Real time elapsed on the host
12sim_insts 407751921 # Number of instructions simulated
13sim_ops 806059216 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2469504 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 1070336 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 10446016 # Number of bytes read from this memory
19system.physmem.bytes_read::total 13989120 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 1070336 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 1070336 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 9206912 # Number of bytes written to this memory
23system.physmem.bytes_written::total 9206912 # Number of bytes written to this memory
24system.physmem.num_reads::pc.south_bridge.ide 38586 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.inst 16724 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.data 163219 # Number of read requests responded to by this memory
29system.physmem.num_reads::total 218580 # Number of read requests responded to by this memory
30system.physmem.num_writes::writebacks 143858 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 143858 # Number of write requests responded to by this memory
32system.physmem.bw_read::pc.south_bridge.ide 477460 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.dtb.walker 544 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.inst 206941 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.data 2019657 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::total 2704688 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_inst_read::cpu.inst 206941 # Instruction read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::total 206941 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_write::writebacks 1780085 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_write::total 1780085 # Write bandwidth from this memory (bytes/s)
42system.physmem.bw_total::writebacks 1780085 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::pc.south_bridge.ide 477460 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 544 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.inst 206941 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.data 2019657 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 4484774 # Total bandwidth to/from this memory (bytes/s)
49system.l2c.replacements 107330 # number of replacements
50system.l2c.tagsinuse 64831.864344 # Cycle average of tags in use
51system.l2c.total_refs 3982185 # Total number of references to valid blocks.
52system.l2c.sampled_refs 171532 # Sample count of references to valid blocks.
53system.l2c.avg_refs 23.215406 # Average number of references to valid blocks.
54system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
55system.l2c.occ_blocks::writebacks 50277.913573 # Average occupied blocks per requestor
56system.l2c.occ_blocks::cpu.dtb.walker 9.980895 # Average occupied blocks per requestor
57system.l2c.occ_blocks::cpu.itb.walker 0.169682 # Average occupied blocks per requestor
58system.l2c.occ_blocks::cpu.inst 3388.636576 # Average occupied blocks per requestor
59system.l2c.occ_blocks::cpu.data 11155.163618 # Average occupied blocks per requestor
60system.l2c.occ_percent::writebacks 0.767180 # Average percentage of cache occupancy
61system.l2c.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy
62system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy
63system.l2c.occ_percent::cpu.inst 0.051706 # Average percentage of cache occupancy
64system.l2c.occ_percent::cpu.data 0.170214 # Average percentage of cache occupancy
65system.l2c.occ_percent::total 0.989256 # Average percentage of cache occupancy
66system.l2c.ReadReq_hits::cpu.dtb.walker 111938 # number of ReadReq hits
67system.l2c.ReadReq_hits::cpu.itb.walker 8555 # number of ReadReq hits
68system.l2c.ReadReq_hits::cpu.inst 1051956 # number of ReadReq hits
69system.l2c.ReadReq_hits::cpu.data 1345107 # number of ReadReq hits
70system.l2c.ReadReq_hits::total 2517556 # number of ReadReq hits
71system.l2c.Writeback_hits::writebacks 1612922 # number of Writeback hits
72system.l2c.Writeback_hits::total 1612922 # number of Writeback hits
73system.l2c.UpgradeReq_hits::cpu.data 325 # number of UpgradeReq hits
74system.l2c.UpgradeReq_hits::total 325 # number of UpgradeReq hits
75system.l2c.ReadExReq_hits::cpu.data 163659 # number of ReadExReq hits
76system.l2c.ReadExReq_hits::total 163659 # number of ReadExReq hits
77system.l2c.demand_hits::cpu.dtb.walker 111938 # number of demand (read+write) hits
78system.l2c.demand_hits::cpu.itb.walker 8555 # number of demand (read+write) hits
79system.l2c.demand_hits::cpu.inst 1051956 # number of demand (read+write) hits
80system.l2c.demand_hits::cpu.data 1508766 # number of demand (read+write) hits
81system.l2c.demand_hits::total 2681215 # number of demand (read+write) hits
82system.l2c.overall_hits::cpu.dtb.walker 111938 # number of overall hits
83system.l2c.overall_hits::cpu.itb.walker 8555 # number of overall hits
84system.l2c.overall_hits::cpu.inst 1051956 # number of overall hits
85system.l2c.overall_hits::cpu.data 1508766 # number of overall hits
86system.l2c.overall_hits::total 2681215 # number of overall hits
87system.l2c.ReadReq_misses::cpu.dtb.walker 44 # number of ReadReq misses
88system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
89system.l2c.ReadReq_misses::cpu.inst 16726 # number of ReadReq misses
90system.l2c.ReadReq_misses::cpu.data 35201 # number of ReadReq misses
91system.l2c.ReadReq_misses::total 51978 # number of ReadReq misses
92system.l2c.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses
93system.l2c.UpgradeReq_misses::total 1498 # number of UpgradeReq misses
94system.l2c.ReadExReq_misses::cpu.data 128962 # number of ReadExReq misses
95system.l2c.ReadExReq_misses::total 128962 # number of ReadExReq misses
96system.l2c.demand_misses::cpu.dtb.walker 44 # number of demand (read+write) misses
97system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
98system.l2c.demand_misses::cpu.inst 16726 # number of demand (read+write) misses
99system.l2c.demand_misses::cpu.data 164163 # number of demand (read+write) misses
100system.l2c.demand_misses::total 180940 # number of demand (read+write) misses
101system.l2c.overall_misses::cpu.dtb.walker 44 # number of overall misses
102system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses
103system.l2c.overall_misses::cpu.inst 16726 # number of overall misses
104system.l2c.overall_misses::cpu.data 164163 # number of overall misses
105system.l2c.overall_misses::total 180940 # number of overall misses
106system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2308000 # number of ReadReq miss cycles
107system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles
108system.l2c.ReadReq_miss_latency::cpu.inst 887926997 # number of ReadReq miss cycles
109system.l2c.ReadReq_miss_latency::cpu.data 1876685493 # number of ReadReq miss cycles
110system.l2c.ReadReq_miss_latency::total 2767284490 # number of ReadReq miss cycles
111system.l2c.UpgradeReq_miss_latency::cpu.data 37648500 # number of UpgradeReq miss cycles
112system.l2c.UpgradeReq_miss_latency::total 37648500 # number of UpgradeReq miss cycles
113system.l2c.ReadExReq_miss_latency::cpu.data 6721908000 # number of ReadExReq miss cycles
114system.l2c.ReadExReq_miss_latency::total 6721908000 # number of ReadExReq miss cycles
115system.l2c.demand_miss_latency::cpu.dtb.walker 2308000 # number of demand (read+write) miss cycles
116system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles
117system.l2c.demand_miss_latency::cpu.inst 887926997 # number of demand (read+write) miss cycles
118system.l2c.demand_miss_latency::cpu.data 8598593493 # number of demand (read+write) miss cycles
119system.l2c.demand_miss_latency::total 9489192490 # number of demand (read+write) miss cycles
120system.l2c.overall_miss_latency::cpu.dtb.walker 2308000 # number of overall miss cycles
121system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles
122system.l2c.overall_miss_latency::cpu.inst 887926997 # number of overall miss cycles
123system.l2c.overall_miss_latency::cpu.data 8598593493 # number of overall miss cycles
124system.l2c.overall_miss_latency::total 9489192490 # number of overall miss cycles
125system.l2c.ReadReq_accesses::cpu.dtb.walker 111982 # number of ReadReq accesses(hits+misses)
126system.l2c.ReadReq_accesses::cpu.itb.walker 8562 # number of ReadReq accesses(hits+misses)
127system.l2c.ReadReq_accesses::cpu.inst 1068682 # number of ReadReq accesses(hits+misses)
128system.l2c.ReadReq_accesses::cpu.data 1380308 # number of ReadReq accesses(hits+misses)
129system.l2c.ReadReq_accesses::total 2569534 # number of ReadReq accesses(hits+misses)
130system.l2c.Writeback_accesses::writebacks 1612922 # number of Writeback accesses(hits+misses)
131system.l2c.Writeback_accesses::total 1612922 # number of Writeback accesses(hits+misses)
132system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
133system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
134system.l2c.ReadExReq_accesses::cpu.data 292621 # number of ReadExReq accesses(hits+misses)
135system.l2c.ReadExReq_accesses::total 292621 # number of ReadExReq accesses(hits+misses)
136system.l2c.demand_accesses::cpu.dtb.walker 111982 # number of demand (read+write) accesses
137system.l2c.demand_accesses::cpu.itb.walker 8562 # number of demand (read+write) accesses
138system.l2c.demand_accesses::cpu.inst 1068682 # number of demand (read+write) accesses
139system.l2c.demand_accesses::cpu.data 1672929 # number of demand (read+write) accesses
140system.l2c.demand_accesses::total 2862155 # number of demand (read+write) accesses
141system.l2c.overall_accesses::cpu.dtb.walker 111982 # number of overall (read+write) accesses
142system.l2c.overall_accesses::cpu.itb.walker 8562 # number of overall (read+write) accesses
143system.l2c.overall_accesses::cpu.inst 1068682 # number of overall (read+write) accesses
144system.l2c.overall_accesses::cpu.data 1672929 # number of overall (read+write) accesses
145system.l2c.overall_accesses::total 2862155 # number of overall (read+write) accesses
146system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000393 # miss rate for ReadReq accesses
147system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000818 # miss rate for ReadReq accesses
148system.l2c.ReadReq_miss_rate::cpu.inst 0.015651 # miss rate for ReadReq accesses
149system.l2c.ReadReq_miss_rate::cpu.data 0.025502 # miss rate for ReadReq accesses
150system.l2c.ReadReq_miss_rate::total 0.020229 # miss rate for ReadReq accesses
151system.l2c.UpgradeReq_miss_rate::cpu.data 0.821722 # miss rate for UpgradeReq accesses
152system.l2c.UpgradeReq_miss_rate::total 0.821722 # miss rate for UpgradeReq accesses
153system.l2c.ReadExReq_miss_rate::cpu.data 0.440713 # miss rate for ReadExReq accesses
154system.l2c.ReadExReq_miss_rate::total 0.440713 # miss rate for ReadExReq accesses
155system.l2c.demand_miss_rate::cpu.dtb.walker 0.000393 # miss rate for demand accesses
156system.l2c.demand_miss_rate::cpu.itb.walker 0.000818 # miss rate for demand accesses
157system.l2c.demand_miss_rate::cpu.inst 0.015651 # miss rate for demand accesses
158system.l2c.demand_miss_rate::cpu.data 0.098129 # miss rate for demand accesses
159system.l2c.demand_miss_rate::total 0.063218 # miss rate for demand accesses
160system.l2c.overall_miss_rate::cpu.dtb.walker 0.000393 # miss rate for overall accesses
161system.l2c.overall_miss_rate::cpu.itb.walker 0.000818 # miss rate for overall accesses
162system.l2c.overall_miss_rate::cpu.inst 0.015651 # miss rate for overall accesses
163system.l2c.overall_miss_rate::cpu.data 0.098129 # miss rate for overall accesses
164system.l2c.overall_miss_rate::total 0.063218 # miss rate for overall accesses
165system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52454.545455 # average ReadReq miss latency
166system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
167system.l2c.ReadReq_avg_miss_latency::cpu.inst 53086.631412 # average ReadReq miss latency
168system.l2c.ReadReq_avg_miss_latency::cpu.data 53313.414193 # average ReadReq miss latency
169system.l2c.ReadReq_avg_miss_latency::total 53239.533841 # average ReadReq miss latency
170system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25132.510013 # average UpgradeReq miss latency
171system.l2c.UpgradeReq_avg_miss_latency::total 25132.510013 # average UpgradeReq miss latency
172system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.168065 # average ReadExReq miss latency
173system.l2c.ReadExReq_avg_miss_latency::total 52123.168065 # average ReadExReq miss latency
174system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52454.545455 # average overall miss latency
175system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
176system.l2c.demand_avg_miss_latency::cpu.inst 53086.631412 # average overall miss latency
177system.l2c.demand_avg_miss_latency::cpu.data 52378.389119 # average overall miss latency
178system.l2c.demand_avg_miss_latency::total 52443.862551 # average overall miss latency
179system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52454.545455 # average overall miss latency
180system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
181system.l2c.overall_avg_miss_latency::cpu.inst 53086.631412 # average overall miss latency
182system.l2c.overall_avg_miss_latency::cpu.data 52378.389119 # average overall miss latency
183system.l2c.overall_avg_miss_latency::total 52443.862551 # average overall miss latency
184system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
185system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
186system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
187system.l2c.blocked::no_targets 0 # number of cycles access was blocked
188system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
189system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
190system.l2c.fast_writes 0 # number of fast writes performed
191system.l2c.cache_copies 0 # number of cache copies performed
192system.l2c.writebacks::writebacks 97191 # number of writebacks
193system.l2c.writebacks::total 97191 # number of writebacks
194system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
195system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
196system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
197system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
198system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
199system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
200system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
201system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
202system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits
203system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 44 # number of ReadReq MSHR misses
204system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
205system.l2c.ReadReq_mshr_misses::cpu.inst 16724 # number of ReadReq MSHR misses
206system.l2c.ReadReq_mshr_misses::cpu.data 35200 # number of ReadReq MSHR misses
207system.l2c.ReadReq_mshr_misses::total 51975 # number of ReadReq MSHR misses
208system.l2c.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses
209system.l2c.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses
210system.l2c.ReadExReq_mshr_misses::cpu.data 128962 # number of ReadExReq MSHR misses
211system.l2c.ReadExReq_mshr_misses::total 128962 # number of ReadExReq MSHR misses
212system.l2c.demand_mshr_misses::cpu.dtb.walker 44 # number of demand (read+write) MSHR misses
213system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
214system.l2c.demand_mshr_misses::cpu.inst 16724 # number of demand (read+write) MSHR misses
215system.l2c.demand_mshr_misses::cpu.data 164162 # number of demand (read+write) MSHR misses
216system.l2c.demand_mshr_misses::total 180937 # number of demand (read+write) MSHR misses
217system.l2c.overall_mshr_misses::cpu.dtb.walker 44 # number of overall MSHR misses
218system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
219system.l2c.overall_mshr_misses::cpu.inst 16724 # number of overall MSHR misses
220system.l2c.overall_mshr_misses::cpu.data 164162 # number of overall MSHR misses
221system.l2c.overall_mshr_misses::total 180937 # number of overall MSHR misses
222system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 1774500 # number of ReadReq MSHR miss cycles
223system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles
224system.l2c.ReadReq_mshr_miss_latency::cpu.inst 683968997 # number of ReadReq MSHR miss cycles
225system.l2c.ReadReq_mshr_miss_latency::cpu.data 1446479000 # number of ReadReq MSHR miss cycles
226system.l2c.ReadReq_mshr_miss_latency::total 2132502497 # number of ReadReq MSHR miss cycles
227system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 60328500 # number of UpgradeReq MSHR miss cycles
228system.l2c.UpgradeReq_mshr_miss_latency::total 60328500 # number of UpgradeReq MSHR miss cycles
229system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5168491500 # number of ReadExReq MSHR miss cycles
230system.l2c.ReadExReq_mshr_miss_latency::total 5168491500 # number of ReadExReq MSHR miss cycles
231system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 1774500 # number of demand (read+write) MSHR miss cycles
232system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles
233system.l2c.demand_mshr_miss_latency::cpu.inst 683968997 # number of demand (read+write) MSHR miss cycles
234system.l2c.demand_mshr_miss_latency::cpu.data 6614970500 # number of demand (read+write) MSHR miss cycles
235system.l2c.demand_mshr_miss_latency::total 7300993997 # number of demand (read+write) MSHR miss cycles
236system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 1774500 # number of overall MSHR miss cycles
237system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles
238system.l2c.overall_mshr_miss_latency::cpu.inst 683968997 # number of overall MSHR miss cycles
239system.l2c.overall_mshr_miss_latency::cpu.data 6614970500 # number of overall MSHR miss cycles
240system.l2c.overall_mshr_miss_latency::total 7300993997 # number of overall MSHR miss cycles
241system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 88673683000 # number of ReadReq MSHR uncacheable cycles
242system.l2c.ReadReq_mshr_uncacheable_latency::total 88673683000 # number of ReadReq MSHR uncacheable cycles
243system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2309054000 # number of WriteReq MSHR uncacheable cycles
244system.l2c.WriteReq_mshr_uncacheable_latency::total 2309054000 # number of WriteReq MSHR uncacheable cycles
245system.l2c.overall_mshr_uncacheable_latency::cpu.data 90982737000 # number of overall MSHR uncacheable cycles
246system.l2c.overall_mshr_uncacheable_latency::total 90982737000 # number of overall MSHR uncacheable cycles
247system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for ReadReq accesses
248system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for ReadReq accesses
249system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for ReadReq accesses
250system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025502 # mshr miss rate for ReadReq accesses
251system.l2c.ReadReq_mshr_miss_rate::total 0.020227 # mshr miss rate for ReadReq accesses
252system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.821722 # mshr miss rate for UpgradeReq accesses
253system.l2c.UpgradeReq_mshr_miss_rate::total 0.821722 # mshr miss rate for UpgradeReq accesses
254system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.440713 # mshr miss rate for ReadExReq accesses
255system.l2c.ReadExReq_mshr_miss_rate::total 0.440713 # mshr miss rate for ReadExReq accesses
256system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for demand accesses
257system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for demand accesses
258system.l2c.demand_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for demand accesses
259system.l2c.demand_mshr_miss_rate::cpu.data 0.098128 # mshr miss rate for demand accesses
260system.l2c.demand_mshr_miss_rate::total 0.063217 # mshr miss rate for demand accesses
261system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for overall accesses
262system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for overall accesses
263system.l2c.overall_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for overall accesses
264system.l2c.overall_mshr_miss_rate::cpu.data 0.098128 # mshr miss rate for overall accesses
265system.l2c.overall_mshr_miss_rate::total 0.063217 # mshr miss rate for overall accesses
266system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average ReadReq mshr miss latency
267system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
268system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40897.452583 # average ReadReq mshr miss latency
269system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41093.153409 # average ReadReq mshr miss latency
270system.l2c.ReadReq_avg_mshr_miss_latency::total 41029.389072 # average ReadReq mshr miss latency
271system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40272.696929 # average UpgradeReq mshr miss latency
272system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40272.696929 # average UpgradeReq mshr miss latency
273system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40077.631395 # average ReadExReq mshr miss latency
274system.l2c.ReadExReq_avg_mshr_miss_latency::total 40077.631395 # average ReadExReq mshr miss latency
275system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average overall mshr miss latency
276system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
277system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40897.452583 # average overall mshr miss latency
278system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.382001 # average overall mshr miss latency
279system.l2c.demand_avg_mshr_miss_latency::total 40351.028242 # average overall mshr miss latency
280system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average overall mshr miss latency
281system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
282system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40897.452583 # average overall mshr miss latency
283system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.382001 # average overall mshr miss latency
284system.l2c.overall_avg_mshr_miss_latency::total 40351.028242 # average overall mshr miss latency
285system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
286system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
287system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
288system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
289system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
290system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
291system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
292system.iocache.replacements 47572 # number of replacements
293system.iocache.tagsinuse 0.197153 # Cycle average of tags in use
294system.iocache.total_refs 0 # Total number of references to valid blocks.
295system.iocache.sampled_refs 47588 # Sample count of references to valid blocks.
296system.iocache.avg_refs 0 # Average number of references to valid blocks.
297system.iocache.warmup_cycle 5000849406000 # Cycle when the warmup percentage was hit.
298system.iocache.occ_blocks::pc.south_bridge.ide 0.197153 # Average occupied blocks per requestor
299system.iocache.occ_percent::pc.south_bridge.ide 0.012322 # Average percentage of cache occupancy
300system.iocache.occ_percent::total 0.012322 # Average percentage of cache occupancy
301system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
302system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
303system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
304system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
305system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
306system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
307system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
308system.iocache.overall_misses::total 47627 # number of overall misses
309system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136172932 # number of ReadReq miss cycles
310system.iocache.ReadReq_miss_latency::total 136172932 # number of ReadReq miss cycles
311system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6920648160 # number of WriteReq miss cycles
312system.iocache.WriteReq_miss_latency::total 6920648160 # number of WriteReq miss cycles
313system.iocache.demand_miss_latency::pc.south_bridge.ide 7056821092 # number of demand (read+write) miss cycles
314system.iocache.demand_miss_latency::total 7056821092 # number of demand (read+write) miss cycles
315system.iocache.overall_miss_latency::pc.south_bridge.ide 7056821092 # number of overall miss cycles
316system.iocache.overall_miss_latency::total 7056821092 # number of overall miss cycles
317system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
318system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
319system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
320system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
321system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
322system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
323system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
324system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
325system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
326system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
327system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
328system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
329system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
330system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
331system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
332system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
333system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150135.536935 # average ReadReq miss latency
334system.iocache.ReadReq_avg_miss_latency::total 150135.536935 # average ReadReq miss latency
335system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148130.311644 # average WriteReq miss latency
336system.iocache.WriteReq_avg_miss_latency::total 148130.311644 # average WriteReq miss latency
337system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency
338system.iocache.demand_avg_miss_latency::total 148168.498793 # average overall miss latency
339system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency
340system.iocache.overall_avg_miss_latency::total 148168.498793 # average overall miss latency
341system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked
342system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
343system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked
344system.iocache.blocked::no_targets 0 # number of cycles access was blocked
345system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked
346system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
347system.iocache.fast_writes 0 # number of fast writes performed
348system.iocache.cache_copies 0 # number of cache copies performed
349system.iocache.writebacks::writebacks 46667 # number of writebacks
350system.iocache.writebacks::total 46667 # number of writebacks
351system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
352system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
353system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
354system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
355system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
356system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
357system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
358system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
359system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88977000 # number of ReadReq MSHR miss cycles
360system.iocache.ReadReq_mshr_miss_latency::total 88977000 # number of ReadReq MSHR miss cycles
361system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4490887946 # number of WriteReq MSHR miss cycles
362system.iocache.WriteReq_mshr_miss_latency::total 4490887946 # number of WriteReq MSHR miss cycles
363system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of demand (read+write) MSHR miss cycles
364system.iocache.demand_mshr_miss_latency::total 4579864946 # number of demand (read+write) MSHR miss cycles
365system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of overall MSHR miss cycles
366system.iocache.overall_mshr_miss_latency::total 4579864946 # number of overall MSHR miss cycles
367system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
368system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
369system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
370system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
371system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
372system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
373system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
374system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
375system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98100.330761 # average ReadReq mshr miss latency
376system.iocache.ReadReq_avg_mshr_miss_latency::total 98100.330761 # average ReadReq mshr miss latency
377system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96123.457748 # average WriteReq mshr miss latency
378system.iocache.WriteReq_avg_mshr_miss_latency::total 96123.457748 # average WriteReq mshr miss latency
379system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency
380system.iocache.demand_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency
381system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency
382system.iocache.overall_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency
383system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
384system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
385system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
386system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
387system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
388system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
389system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
390system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
391system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
392system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
393system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
394system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
395system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
396system.cpu.numCycles 475031565 # number of cpu cycles simulated
397system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
398system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
399system.cpu.BPredUnit.lookups 86684856 # Number of BP lookups
400system.cpu.BPredUnit.condPredicted 86684856 # Number of conditional branches predicted
401system.cpu.BPredUnit.condIncorrect 1176632 # Number of conditional branches incorrect
402system.cpu.BPredUnit.BTBLookups 82122133 # Number of BTB lookups
403system.cpu.BPredUnit.BTBHits 79543196 # Number of BTB hits
404system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
405system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
406system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
407system.cpu.fetch.icacheStallCycles 31269539 # Number of cycles fetch is stalled on an Icache miss
408system.cpu.fetch.Insts 428184771 # Number of instructions fetch has processed
409system.cpu.fetch.Branches 86684856 # Number of branches that fetch encountered
410system.cpu.fetch.predictedBranches 79543196 # Number of branches that fetch has predicted taken
411system.cpu.fetch.Cycles 164289785 # Number of cycles fetch has run and was not squashing or blocked
412system.cpu.fetch.SquashCycles 5325147 # Number of cycles fetch has spent squashing
413system.cpu.fetch.TlbCycles 164614 # Number of cycles fetch has spent waiting for tlb
414system.cpu.fetch.BlockedCycles 76824227 # Number of cycles fetch has spent blocked
415system.cpu.fetch.MiscStallCycles 37234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416system.cpu.fetch.PendingTrapStallCycles 45914 # Number of stall cycles due to pending traps
417system.cpu.fetch.IcacheWaitRetryStallCycles 429 # Number of stall cycles due to full MSHR
418system.cpu.fetch.CacheLines 9378048 # Number of cache lines fetched
419system.cpu.fetch.IcacheSquashes 536886 # Number of outstanding Icache misses that were squashed
420system.cpu.fetch.ItlbSquashes 4957 # Number of outstanding ITLB misses that were squashed
421system.cpu.fetch.rateDist::samples 276741596 # Number of instructions fetched each cycle (Total)
422system.cpu.fetch.rateDist::mean 3.053538 # Number of instructions fetched each cycle (Total)
423system.cpu.fetch.rateDist::stdev 3.401990 # Number of instructions fetched each cycle (Total)
424system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
425system.cpu.fetch.rateDist::0 112886536 40.79% 40.79% # Number of instructions fetched each cycle (Total)
426system.cpu.fetch.rateDist::1 1619655 0.59% 41.38% # Number of instructions fetched each cycle (Total)
427system.cpu.fetch.rateDist::2 71962795 26.00% 67.38% # Number of instructions fetched each cycle (Total)
428system.cpu.fetch.rateDist::3 983886 0.36% 67.74% # Number of instructions fetched each cycle (Total)
429system.cpu.fetch.rateDist::4 1644119 0.59% 68.33% # Number of instructions fetched each cycle (Total)
430system.cpu.fetch.rateDist::5 2486257 0.90% 69.23% # Number of instructions fetched each cycle (Total)
431system.cpu.fetch.rateDist::6 1139995 0.41% 69.64% # Number of instructions fetched each cycle (Total)
432system.cpu.fetch.rateDist::7 1450599 0.52% 70.16% # Number of instructions fetched each cycle (Total)
433system.cpu.fetch.rateDist::8 82567754 29.84% 100.00% # Number of instructions fetched each cycle (Total)
434system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
435system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
436system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
437system.cpu.fetch.rateDist::total 276741596 # Number of instructions fetched each cycle (Total)
438system.cpu.fetch.branchRate 0.182482 # Number of branch fetches per cycle
439system.cpu.fetch.rate 0.901382 # Number of inst fetches per cycle
440system.cpu.decode.IdleCycles 35010017 # Number of cycles decode is idle
441system.cpu.decode.BlockedCycles 74311956 # Number of cycles decode is blocked
442system.cpu.decode.RunCycles 159865423 # Number of cycles decode is running
443system.cpu.decode.UnblockCycles 3444346 # Number of cycles decode is unblocking
444system.cpu.decode.SquashCycles 4109854 # Number of cycles decode is squashing
445system.cpu.decode.DecodedInsts 841785392 # Number of instructions handled by decode
446system.cpu.decode.SquashedInsts 993 # Number of squashed instructions handled by decode
447system.cpu.rename.SquashCycles 4109854 # Number of cycles rename is squashing
448system.cpu.rename.IdleCycles 38173067 # Number of cycles rename is idle
449system.cpu.rename.BlockCycles 41532647 # Number of cycles rename is blocking
450system.cpu.rename.serializeStallCycles 11823127 # count of cycles rename stalled for serializing inst
451system.cpu.rename.RunCycles 159691932 # Number of cycles rename is running
452system.cpu.rename.UnblockCycles 21410969 # Number of cycles rename is unblocking
453system.cpu.rename.RenamedInsts 837988743 # Number of instructions processed by rename
454system.cpu.rename.ROBFullEvents 10561 # Number of times rename has blocked due to ROB full
455system.cpu.rename.IQFullEvents 14331873 # Number of times rename has blocked due to IQ full
456system.cpu.rename.LSQFullEvents 3961467 # Number of times rename has blocked due to LSQ full
457system.cpu.rename.FullRegisterEvents 8380256 # Number of times there has been no free registers
458system.cpu.rename.RenamedOperands 1328629800 # Number of destination operands rename has renamed
459system.cpu.rename.RenameLookups 2380702001 # Number of register rename lookups that rename has made
460system.cpu.rename.int_rename_lookups 2380701417 # Number of integer rename lookups
461system.cpu.rename.fp_rename_lookups 584 # Number of floating rename lookups
462system.cpu.rename.CommittedMaps 1282020322 # Number of HB maps that are committed
463system.cpu.rename.UndoneMaps 46609471 # Number of HB maps that are undone due to squashing
464system.cpu.rename.serializingInsts 469457 # count of serializing insts renamed
465system.cpu.rename.tempSerializingInsts 477289 # count of temporary serializing insts renamed
466system.cpu.rename.skidInsts 33840968 # count of insts added to the skid buffer
467system.cpu.memDep0.insertedLoads 17569417 # Number of loads inserted to the mem dependence unit.
468system.cpu.memDep0.insertedStores 10446486 # Number of stores inserted to the mem dependence unit.
469system.cpu.memDep0.conflictingLoads 1246814 # Number of conflicting loads.
470system.cpu.memDep0.conflictingStores 1007946 # Number of conflicting stores.
471system.cpu.iq.iqInstsAdded 831743249 # Number of instructions added to the IQ (excludes non-spec)
472system.cpu.iq.iqNonSpecInstsAdded 1259421 # Number of non-speculative instructions added to the IQ
473system.cpu.iq.iqInstsIssued 823989117 # Number of instructions issued
474system.cpu.iq.iqSquashedInstsIssued 123035 # Number of squashed instructions issued
475system.cpu.iq.iqSquashedInstsExamined 26027822 # Number of squashed instructions iterated over during squash; mainly for profiling
476system.cpu.iq.iqSquashedOperandsExamined 53490149 # Number of squashed operands that are examined and possibly removed from graph
477system.cpu.iq.iqSquashedNonSpecRemoved 209479 # Number of squashed non-spec instructions that were removed
478system.cpu.iq.issued_per_cycle::samples 276741596 # Number of insts issued each cycle
479system.cpu.iq.issued_per_cycle::mean 2.977468 # Number of insts issued each cycle
480system.cpu.iq.issued_per_cycle::stdev 2.409448 # Number of insts issued each cycle
481system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
482system.cpu.iq.issued_per_cycle::0 86092872 31.11% 31.11% # Number of insts issued each cycle
483system.cpu.iq.issued_per_cycle::1 17946523 6.48% 37.59% # Number of insts issued each cycle
484system.cpu.iq.issued_per_cycle::2 12957239 4.68% 42.28% # Number of insts issued each cycle
485system.cpu.iq.issued_per_cycle::3 7826219 2.83% 45.10% # Number of insts issued each cycle
486system.cpu.iq.issued_per_cycle::4 76249367 27.55% 72.66% # Number of insts issued each cycle
487system.cpu.iq.issued_per_cycle::5 3109383 1.12% 73.78% # Number of insts issued each cycle
488system.cpu.iq.issued_per_cycle::6 71927366 25.99% 99.77% # Number of insts issued each cycle
489system.cpu.iq.issued_per_cycle::7 520136 0.19% 99.96% # Number of insts issued each cycle
490system.cpu.iq.issued_per_cycle::8 112491 0.04% 100.00% # Number of insts issued each cycle
491system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
492system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
493system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
494system.cpu.iq.issued_per_cycle::total 276741596 # Number of insts issued each cycle
495system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
496system.cpu.iq.fu_full::IntAlu 163103 18.01% 18.01% # attempts to use FU when none available
497system.cpu.iq.fu_full::IntMult 0 0.00% 18.01% # attempts to use FU when none available
498system.cpu.iq.fu_full::IntDiv 0 0.00% 18.01% # attempts to use FU when none available
499system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.01% # attempts to use FU when none available
500system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.01% # attempts to use FU when none available
501system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.01% # attempts to use FU when none available
502system.cpu.iq.fu_full::FloatMult 0 0.00% 18.01% # attempts to use FU when none available
503system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.01% # attempts to use FU when none available
504system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.01% # attempts to use FU when none available
505system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.01% # attempts to use FU when none available
506system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.01% # attempts to use FU when none available
507system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.01% # attempts to use FU when none available
508system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.01% # attempts to use FU when none available
509system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.01% # attempts to use FU when none available
510system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.01% # attempts to use FU when none available
511system.cpu.iq.fu_full::SimdMult 0 0.00% 18.01% # attempts to use FU when none available
512system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.01% # attempts to use FU when none available
513system.cpu.iq.fu_full::SimdShift 0 0.00% 18.01% # attempts to use FU when none available
514system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.01% # attempts to use FU when none available
515system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.01% # attempts to use FU when none available
516system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.01% # attempts to use FU when none available
517system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.01% # attempts to use FU when none available
518system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.01% # attempts to use FU when none available
519system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.01% # attempts to use FU when none available
520system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.01% # attempts to use FU when none available
521system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.01% # attempts to use FU when none available
522system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.01% # attempts to use FU when none available
523system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.01% # attempts to use FU when none available
524system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.01% # attempts to use FU when none available
525system.cpu.iq.fu_full::MemRead 583729 64.45% 82.45% # attempts to use FU when none available
526system.cpu.iq.fu_full::MemWrite 158924 17.55% 100.00% # attempts to use FU when none available
527system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
528system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
529system.cpu.iq.FU_type_0::No_OpClass 296041 0.04% 0.04% # Type of FU issued
530system.cpu.iq.FU_type_0::IntAlu 796340985 96.64% 96.68% # Type of FU issued
531system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.68% # Type of FU issued
532system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.68% # Type of FU issued
533system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.68% # Type of FU issued
534system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.68% # Type of FU issued
535system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.68% # Type of FU issued
536system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.68% # Type of FU issued
537system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.68% # Type of FU issued
538system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.68% # Type of FU issued
539system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.68% # Type of FU issued
540system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.68% # Type of FU issued
541system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.68% # Type of FU issued
542system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.68% # Type of FU issued
543system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.68% # Type of FU issued
544system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.68% # Type of FU issued
545system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.68% # Type of FU issued
546system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.68% # Type of FU issued
547system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.68% # Type of FU issued
548system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.68% # Type of FU issued
549system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.68% # Type of FU issued
550system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.68% # Type of FU issued
551system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.68% # Type of FU issued
552system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.68% # Type of FU issued
553system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.68% # Type of FU issued
554system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.68% # Type of FU issued
555system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.68% # Type of FU issued
556system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.68% # Type of FU issued
557system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.68% # Type of FU issued
558system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.68% # Type of FU issued
559system.cpu.iq.FU_type_0::MemRead 17916922 2.17% 98.85% # Type of FU issued
560system.cpu.iq.FU_type_0::MemWrite 9435169 1.15% 100.00% # Type of FU issued
561system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
562system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
563system.cpu.iq.FU_type_0::total 823989117 # Type of FU issued
564system.cpu.iq.rate 1.734599 # Inst issue rate
565system.cpu.iq.fu_busy_cnt 905756 # FU busy when requested
566system.cpu.iq.fu_busy_rate 0.001099 # FU busy rate (busy events/executed inst)
567system.cpu.iq.int_inst_queue_reads 1925886604 # Number of integer instruction queue reads
568system.cpu.iq.int_inst_queue_writes 859041376 # Number of integer instruction queue writes
569system.cpu.iq.int_inst_queue_wakeup_accesses 819484767 # Number of integer instruction queue wakeup accesses
570system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads
571system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes
572system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
573system.cpu.iq.int_alu_accesses 824598744 # Number of integer alu accesses
574system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses
575system.cpu.iew.lsq.thread0.forwLoads 1578458 # Number of loads that had data forwarded from stores
576system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
577system.cpu.iew.lsq.thread0.squashedLoads 3618337 # Number of loads squashed
578system.cpu.iew.lsq.thread0.ignoredResponses 20593 # Number of memory responses ignored because the instruction is squashed
579system.cpu.iew.lsq.thread0.memOrderViolation 12016 # Number of memory ordering violations
580system.cpu.iew.lsq.thread0.squashedStores 2047079 # Number of stores squashed
581system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
582system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
583system.cpu.iew.lsq.thread0.rescheduledLoads 1917340 # Number of loads that were rescheduled
584system.cpu.iew.lsq.thread0.cacheBlocked 4451 # Number of times an access to memory failed due to the cache being blocked
585system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
586system.cpu.iew.iewSquashCycles 4109854 # Number of cycles IEW is squashing
587system.cpu.iew.iewBlockCycles 27168187 # Number of cycles IEW is blocking
588system.cpu.iew.iewUnblockCycles 1772103 # Number of cycles IEW is unblocking
589system.cpu.iew.iewDispatchedInsts 833002670 # Number of instructions dispatched to IQ
590system.cpu.iew.iewDispSquashedInsts 300864 # Number of squashed instructions skipped by dispatch
591system.cpu.iew.iewDispLoadInsts 17569417 # Number of dispatched load instructions
592system.cpu.iew.iewDispStoreInsts 10446486 # Number of dispatched store instructions
593system.cpu.iew.iewDispNonSpecInsts 728436 # Number of dispatched non-speculative instructions
594system.cpu.iew.iewIQFullEvents 974858 # Number of times the IQ has become full, causing a stall
595system.cpu.iew.iewLSQFullEvents 15486 # Number of times the LSQ has become full, causing a stall
596system.cpu.iew.memOrderViolationEvents 12016 # Number of memory order violations
597system.cpu.iew.predictedTakenIncorrect 697910 # Number of branches that were predicted taken incorrectly
598system.cpu.iew.predictedNotTakenIncorrect 625387 # Number of branches that were predicted not taken incorrectly
599system.cpu.iew.branchMispredicts 1323297 # Number of branch mispredicts detected at execute
600system.cpu.iew.iewExecutedInsts 822095189 # Number of executed instructions
601system.cpu.iew.iewExecLoadInsts 17489841 # Number of load instructions executed
602system.cpu.iew.iewExecSquashedInsts 1893927 # Number of squashed instructions skipped in execute
603system.cpu.iew.exec_swp 0 # number of swp insts executed
604system.cpu.iew.exec_nop 0 # number of nop insts executed
605system.cpu.iew.exec_refs 26681633 # number of memory reference insts executed
606system.cpu.iew.exec_branches 83151598 # Number of branches executed
607system.cpu.iew.exec_stores 9191792 # Number of stores executed
608system.cpu.iew.exec_rate 1.730612 # Inst execution rate
609system.cpu.iew.wb_sent 821608460 # cumulative count of insts sent to commit
610system.cpu.iew.wb_count 819484817 # cumulative count of insts written-back
611system.cpu.iew.wb_producers 640296111 # num instructions producing a value
612system.cpu.iew.wb_consumers 1828731330 # num instructions consuming a value
613system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
614system.cpu.iew.wb_rate 1.725117 # insts written-back per cycle
615system.cpu.iew.wb_fanout 0.350131 # average fanout of values written-back
616system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
617system.cpu.commit.commitCommittedInsts 407751921 # The number of committed instructions
618system.cpu.commit.commitCommittedOps 806059216 # The number of committed instructions
619system.cpu.commit.commitSquashedInsts 26839677 # The number of squashed insts skipped by commit
620system.cpu.commit.commitNonSpecStalls 1049940 # The number of times commit has been forced to stall to communicate backwards
621system.cpu.commit.branchMispredicts 1181775 # The number of times a branch was mispredicted
622system.cpu.commit.committed_per_cycle::samples 272647181 # Number of insts commited each cycle
623system.cpu.commit.committed_per_cycle::mean 2.956419 # Number of insts commited each cycle
624system.cpu.commit.committed_per_cycle::stdev 2.843352 # Number of insts commited each cycle
625system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
626system.cpu.commit.committed_per_cycle::0 98573076 36.15% 36.15% # Number of insts commited each cycle
627system.cpu.commit.committed_per_cycle::1 13223290 4.85% 41.00% # Number of insts commited each cycle
628system.cpu.commit.committed_per_cycle::2 4246957 1.56% 42.56% # Number of insts commited each cycle
629system.cpu.commit.committed_per_cycle::3 75817327 27.81% 70.37% # Number of insts commited each cycle
630system.cpu.commit.committed_per_cycle::4 2710299 0.99% 71.36% # Number of insts commited each cycle
631system.cpu.commit.committed_per_cycle::5 1789124 0.66% 72.02% # Number of insts commited each cycle
632system.cpu.commit.committed_per_cycle::6 1087866 0.40% 72.42% # Number of insts commited each cycle
633system.cpu.commit.committed_per_cycle::7 71017917 26.05% 98.47% # Number of insts commited each cycle
634system.cpu.commit.committed_per_cycle::8 4181325 1.53% 100.00% # Number of insts commited each cycle
635system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
636system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
637system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
638system.cpu.commit.committed_per_cycle::total 272647181 # Number of insts commited each cycle
639system.cpu.commit.committedInsts 407751921 # Number of instructions committed
640system.cpu.commit.committedOps 806059216 # Number of ops (including micro ops) committed
641system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
642system.cpu.commit.refs 22350484 # Number of memory references committed
643system.cpu.commit.loads 13951077 # Number of loads committed
644system.cpu.commit.membars 471695 # Number of memory barriers committed
645system.cpu.commit.branches 82163258 # Number of branches committed
646system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
647system.cpu.commit.int_insts 735013406 # Number of committed integer instructions.
648system.cpu.commit.function_calls 0 # Number of function calls committed.
649system.cpu.commit.bw_lim_events 4181325 # number cycles where commit BW limit reached
650system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
651system.cpu.rob.rob_reads 1101286190 # The number of ROB reads
652system.cpu.rob.rob_writes 1669922447 # The number of ROB writes
653system.cpu.timesIdled 1659907 # Number of times that the entire CPU went into an idle state and unscheduled itself
654system.cpu.idleCycles 198289969 # Total number of cycles that the CPU has spent unscheduled due to idling
655system.cpu.quiesceCycles 9869314281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
656system.cpu.committedInsts 407751921 # Number of Instructions Simulated
657system.cpu.committedOps 806059216 # Number of Ops (including micro ops) Simulated
658system.cpu.committedInsts_total 407751921 # Number of Instructions Simulated
659system.cpu.cpi 1.165001 # CPI: Cycles Per Instruction
660system.cpu.cpi_total 1.165001 # CPI: Total CPI of All Threads
661system.cpu.ipc 0.858368 # IPC: Instructions Per Cycle
662system.cpu.ipc_total 0.858368 # IPC: Total IPC of All Threads
663system.cpu.int_regfile_reads 2053713870 # number of integer regfile reads
664system.cpu.int_regfile_writes 1297159076 # number of integer regfile writes
665system.cpu.fp_regfile_reads 50 # number of floating regfile reads
666system.cpu.misc_regfile_reads 265135377 # number of misc regfile reads
667system.cpu.misc_regfile_writes 402339 # number of misc regfile writes
668system.cpu.icache.replacements 1068223 # number of replacements
669system.cpu.icache.tagsinuse 510.418027 # Cycle average of tags in use
670system.cpu.icache.total_refs 8239400 # Total number of references to valid blocks.
671system.cpu.icache.sampled_refs 1068735 # Sample count of references to valid blocks.
672system.cpu.icache.avg_refs 7.709488 # Average number of references to valid blocks.
673system.cpu.icache.warmup_cycle 57281567000 # Cycle when the warmup percentage was hit.
674system.cpu.icache.occ_blocks::cpu.inst 510.418027 # Average occupied blocks per requestor
675system.cpu.icache.occ_percent::cpu.inst 0.996910 # Average percentage of cache occupancy
676system.cpu.icache.occ_percent::total 0.996910 # Average percentage of cache occupancy
677system.cpu.icache.ReadReq_hits::cpu.inst 8239400 # number of ReadReq hits
678system.cpu.icache.ReadReq_hits::total 8239400 # number of ReadReq hits
679system.cpu.icache.demand_hits::cpu.inst 8239400 # number of demand (read+write) hits
680system.cpu.icache.demand_hits::total 8239400 # number of demand (read+write) hits
681system.cpu.icache.overall_hits::cpu.inst 8239400 # number of overall hits
682system.cpu.icache.overall_hits::total 8239400 # number of overall hits
683system.cpu.icache.ReadReq_misses::cpu.inst 1138645 # number of ReadReq misses
684system.cpu.icache.ReadReq_misses::total 1138645 # number of ReadReq misses
685system.cpu.icache.demand_misses::cpu.inst 1138645 # number of demand (read+write) misses
686system.cpu.icache.demand_misses::total 1138645 # number of demand (read+write) misses
687system.cpu.icache.overall_misses::cpu.inst 1138645 # number of overall misses
688system.cpu.icache.overall_misses::total 1138645 # number of overall misses
689system.cpu.icache.ReadReq_miss_latency::cpu.inst 18814976480 # number of ReadReq miss cycles
690system.cpu.icache.ReadReq_miss_latency::total 18814976480 # number of ReadReq miss cycles
691system.cpu.icache.demand_miss_latency::cpu.inst 18814976480 # number of demand (read+write) miss cycles
692system.cpu.icache.demand_miss_latency::total 18814976480 # number of demand (read+write) miss cycles
693system.cpu.icache.overall_miss_latency::cpu.inst 18814976480 # number of overall miss cycles
694system.cpu.icache.overall_miss_latency::total 18814976480 # number of overall miss cycles
695system.cpu.icache.ReadReq_accesses::cpu.inst 9378045 # number of ReadReq accesses(hits+misses)
696system.cpu.icache.ReadReq_accesses::total 9378045 # number of ReadReq accesses(hits+misses)
697system.cpu.icache.demand_accesses::cpu.inst 9378045 # number of demand (read+write) accesses
698system.cpu.icache.demand_accesses::total 9378045 # number of demand (read+write) accesses
699system.cpu.icache.overall_accesses::cpu.inst 9378045 # number of overall (read+write) accesses
700system.cpu.icache.overall_accesses::total 9378045 # number of overall (read+write) accesses
701system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121416 # miss rate for ReadReq accesses
702system.cpu.icache.ReadReq_miss_rate::total 0.121416 # miss rate for ReadReq accesses
703system.cpu.icache.demand_miss_rate::cpu.inst 0.121416 # miss rate for demand accesses
704system.cpu.icache.demand_miss_rate::total 0.121416 # miss rate for demand accesses
705system.cpu.icache.overall_miss_rate::cpu.inst 0.121416 # miss rate for overall accesses
706system.cpu.icache.overall_miss_rate::total 0.121416 # miss rate for overall accesses
707system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16524.005709 # average ReadReq miss latency
708system.cpu.icache.ReadReq_avg_miss_latency::total 16524.005709 # average ReadReq miss latency
709system.cpu.icache.demand_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency
710system.cpu.icache.demand_avg_miss_latency::total 16524.005709 # average overall miss latency
711system.cpu.icache.overall_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency
712system.cpu.icache.overall_avg_miss_latency::total 16524.005709 # average overall miss latency
713system.cpu.icache.blocked_cycles::no_mshrs 3200487 # number of cycles access was blocked
714system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
715system.cpu.icache.blocked::no_mshrs 386 # number of cycles access was blocked
716system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
717system.cpu.icache.avg_blocked_cycles::no_mshrs 8291.417098 # average number of cycles each access was blocked
718system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
719system.cpu.icache.fast_writes 0 # number of fast writes performed
720system.cpu.icache.cache_copies 0 # number of cache copies performed
721system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69787 # number of ReadReq MSHR hits
722system.cpu.icache.ReadReq_mshr_hits::total 69787 # number of ReadReq MSHR hits
723system.cpu.icache.demand_mshr_hits::cpu.inst 69787 # number of demand (read+write) MSHR hits
724system.cpu.icache.demand_mshr_hits::total 69787 # number of demand (read+write) MSHR hits
725system.cpu.icache.overall_mshr_hits::cpu.inst 69787 # number of overall MSHR hits
726system.cpu.icache.overall_mshr_hits::total 69787 # number of overall MSHR hits
727system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1068858 # number of ReadReq MSHR misses
728system.cpu.icache.ReadReq_mshr_misses::total 1068858 # number of ReadReq MSHR misses
729system.cpu.icache.demand_mshr_misses::cpu.inst 1068858 # number of demand (read+write) MSHR misses
730system.cpu.icache.demand_mshr_misses::total 1068858 # number of demand (read+write) MSHR misses
731system.cpu.icache.overall_mshr_misses::cpu.inst 1068858 # number of overall MSHR misses
732system.cpu.icache.overall_mshr_misses::total 1068858 # number of overall MSHR misses
733system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14704003987 # number of ReadReq MSHR miss cycles
734system.cpu.icache.ReadReq_mshr_miss_latency::total 14704003987 # number of ReadReq MSHR miss cycles
735system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14704003987 # number of demand (read+write) MSHR miss cycles
736system.cpu.icache.demand_mshr_miss_latency::total 14704003987 # number of demand (read+write) MSHR miss cycles
737system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14704003987 # number of overall MSHR miss cycles
738system.cpu.icache.overall_mshr_miss_latency::total 14704003987 # number of overall MSHR miss cycles
739system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for ReadReq accesses
740system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113975 # mshr miss rate for ReadReq accesses
741system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for demand accesses
742system.cpu.icache.demand_mshr_miss_rate::total 0.113975 # mshr miss rate for demand accesses
743system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for overall accesses
744system.cpu.icache.overall_mshr_miss_rate::total 0.113975 # mshr miss rate for overall accesses
745system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13756.742230 # average ReadReq mshr miss latency
746system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13756.742230 # average ReadReq mshr miss latency
747system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency
748system.cpu.icache.demand_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency
749system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency
750system.cpu.icache.overall_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency
751system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
752system.cpu.itb_walker_cache.replacements 10021 # number of replacements
753system.cpu.itb_walker_cache.tagsinuse 6.028958 # Cycle average of tags in use
754system.cpu.itb_walker_cache.total_refs 32291 # Total number of references to valid blocks.
755system.cpu.itb_walker_cache.sampled_refs 10034 # Sample count of references to valid blocks.
756system.cpu.itb_walker_cache.avg_refs 3.218158 # Average number of references to valid blocks.
757system.cpu.itb_walker_cache.warmup_cycle 5136098133000 # Cycle when the warmup percentage was hit.
758system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028958 # Average occupied blocks per requestor
759system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376810 # Average percentage of cache occupancy
760system.cpu.itb_walker_cache.occ_percent::total 0.376810 # Average percentage of cache occupancy
761system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 32310 # number of ReadReq hits
762system.cpu.itb_walker_cache.ReadReq_hits::total 32310 # number of ReadReq hits
763system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
764system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
765system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 32313 # number of demand (read+write) hits
766system.cpu.itb_walker_cache.demand_hits::total 32313 # number of demand (read+write) hits
767system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 32313 # number of overall hits
768system.cpu.itb_walker_cache.overall_hits::total 32313 # number of overall hits
769system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10911 # number of ReadReq misses
770system.cpu.itb_walker_cache.ReadReq_misses::total 10911 # number of ReadReq misses
771system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10911 # number of demand (read+write) misses
772system.cpu.itb_walker_cache.demand_misses::total 10911 # number of demand (read+write) misses
773system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10911 # number of overall misses
774system.cpu.itb_walker_cache.overall_misses::total 10911 # number of overall misses
775system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183901500 # number of ReadReq miss cycles
776system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183901500 # number of ReadReq miss cycles
777system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183901500 # number of demand (read+write) miss cycles
778system.cpu.itb_walker_cache.demand_miss_latency::total 183901500 # number of demand (read+write) miss cycles
779system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183901500 # number of overall miss cycles
780system.cpu.itb_walker_cache.overall_miss_latency::total 183901500 # number of overall miss cycles
781system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43221 # number of ReadReq accesses(hits+misses)
782system.cpu.itb_walker_cache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses)
783system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
784system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
785system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43224 # number of demand (read+write) accesses
786system.cpu.itb_walker_cache.demand_accesses::total 43224 # number of demand (read+write) accesses
787system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43224 # number of overall (read+write) accesses
788system.cpu.itb_walker_cache.overall_accesses::total 43224 # number of overall (read+write) accesses
789system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.252447 # miss rate for ReadReq accesses
790system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.252447 # miss rate for ReadReq accesses
791system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.252429 # miss rate for demand accesses
792system.cpu.itb_walker_cache.demand_miss_rate::total 0.252429 # miss rate for demand accesses
793system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.252429 # miss rate for overall accesses
794system.cpu.itb_walker_cache.overall_miss_rate::total 0.252429 # miss rate for overall accesses
795system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16854.687930 # average ReadReq miss latency
796system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16854.687930 # average ReadReq miss latency
797system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency
798system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16854.687930 # average overall miss latency
799system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency
800system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16854.687930 # average overall miss latency
801system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
802system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
803system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
804system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
805system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
806system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
807system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
808system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
809system.cpu.itb_walker_cache.writebacks::writebacks 1563 # number of writebacks
810system.cpu.itb_walker_cache.writebacks::total 1563 # number of writebacks
811system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10911 # number of ReadReq MSHR misses
812system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10911 # number of ReadReq MSHR misses
813system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10911 # number of demand (read+write) MSHR misses
814system.cpu.itb_walker_cache.demand_mshr_misses::total 10911 # number of demand (read+write) MSHR misses
815system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10911 # number of overall MSHR misses
816system.cpu.itb_walker_cache.overall_mshr_misses::total 10911 # number of overall MSHR misses
817system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 150559535 # number of ReadReq MSHR miss cycles
818system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 150559535 # number of ReadReq MSHR miss cycles
819system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 150559535 # number of demand (read+write) MSHR miss cycles
820system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 150559535 # number of demand (read+write) MSHR miss cycles
821system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 150559535 # number of overall MSHR miss cycles
822system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 150559535 # number of overall MSHR miss cycles
823system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.252447 # mshr miss rate for ReadReq accesses
824system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.252447 # mshr miss rate for ReadReq accesses
825system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for demand accesses
826system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.252429 # mshr miss rate for demand accesses
827system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for overall accesses
828system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.252429 # mshr miss rate for overall accesses
829system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average ReadReq mshr miss latency
830system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13798.875905 # average ReadReq mshr miss latency
831system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency
832system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency
833system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency
834system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency
835system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
836system.cpu.dtb_walker_cache.replacements 116564 # number of replacements
837system.cpu.dtb_walker_cache.tagsinuse 12.971477 # Cycle average of tags in use
838system.cpu.dtb_walker_cache.total_refs 137576 # Total number of references to valid blocks.
839system.cpu.dtb_walker_cache.sampled_refs 116580 # Sample count of references to valid blocks.
840system.cpu.dtb_walker_cache.avg_refs 1.180100 # Average number of references to valid blocks.
841system.cpu.dtb_walker_cache.warmup_cycle 5113123336000 # Cycle when the warmup percentage was hit.
842system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.971477 # Average occupied blocks per requestor
843system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810717 # Average percentage of cache occupancy
844system.cpu.dtb_walker_cache.occ_percent::total 0.810717 # Average percentage of cache occupancy
845system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137576 # number of ReadReq hits
846system.cpu.dtb_walker_cache.ReadReq_hits::total 137576 # number of ReadReq hits
847system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137576 # number of demand (read+write) hits
848system.cpu.dtb_walker_cache.demand_hits::total 137576 # number of demand (read+write) hits
849system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137576 # number of overall hits
850system.cpu.dtb_walker_cache.overall_hits::total 137576 # number of overall hits
851system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117614 # number of ReadReq misses
852system.cpu.dtb_walker_cache.ReadReq_misses::total 117614 # number of ReadReq misses
853system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117614 # number of demand (read+write) misses
854system.cpu.dtb_walker_cache.demand_misses::total 117614 # number of demand (read+write) misses
855system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117614 # number of overall misses
856system.cpu.dtb_walker_cache.overall_misses::total 117614 # number of overall misses
857system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2140596500 # number of ReadReq miss cycles
858system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2140596500 # number of ReadReq miss cycles
859system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2140596500 # number of demand (read+write) miss cycles
860system.cpu.dtb_walker_cache.demand_miss_latency::total 2140596500 # number of demand (read+write) miss cycles
861system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2140596500 # number of overall miss cycles
862system.cpu.dtb_walker_cache.overall_miss_latency::total 2140596500 # number of overall miss cycles
863system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255190 # number of ReadReq accesses(hits+misses)
864system.cpu.dtb_walker_cache.ReadReq_accesses::total 255190 # number of ReadReq accesses(hits+misses)
865system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255190 # number of demand (read+write) accesses
866system.cpu.dtb_walker_cache.demand_accesses::total 255190 # number of demand (read+write) accesses
867system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255190 # number of overall (read+write) accesses
868system.cpu.dtb_walker_cache.overall_accesses::total 255190 # number of overall (read+write) accesses
869system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.460888 # miss rate for ReadReq accesses
870system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.460888 # miss rate for ReadReq accesses
871system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.460888 # miss rate for demand accesses
872system.cpu.dtb_walker_cache.demand_miss_rate::total 0.460888 # miss rate for demand accesses
873system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.460888 # miss rate for overall accesses
874system.cpu.dtb_walker_cache.overall_miss_rate::total 0.460888 # miss rate for overall accesses
875system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18200.184502 # average ReadReq miss latency
876system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18200.184502 # average ReadReq miss latency
877system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency
878system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18200.184502 # average overall miss latency
879system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency
880system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18200.184502 # average overall miss latency
881system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
882system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
883system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
884system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
885system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
886system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
887system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
888system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
889system.cpu.dtb_walker_cache.writebacks::writebacks 39184 # number of writebacks
890system.cpu.dtb_walker_cache.writebacks::total 39184 # number of writebacks
891system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117614 # number of ReadReq MSHR misses
892system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117614 # number of ReadReq MSHR misses
893system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117614 # number of demand (read+write) MSHR misses
894system.cpu.dtb_walker_cache.demand_mshr_misses::total 117614 # number of demand (read+write) MSHR misses
895system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117614 # number of overall MSHR misses
896system.cpu.dtb_walker_cache.overall_mshr_misses::total 117614 # number of overall MSHR misses
897system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of ReadReq MSHR miss cycles
898system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1785080011 # number of ReadReq MSHR miss cycles
899system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of demand (read+write) MSHR miss cycles
900system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1785080011 # number of demand (read+write) MSHR miss cycles
901system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of overall MSHR miss cycles
902system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1785080011 # number of overall MSHR miss cycles
903system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for ReadReq accesses
904system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.460888 # mshr miss rate for ReadReq accesses
905system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for demand accesses
906system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.460888 # mshr miss rate for demand accesses
907system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for overall accesses
908system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.460888 # mshr miss rate for overall accesses
909system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average ReadReq mshr miss latency
910system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15177.444956 # average ReadReq mshr miss latency
911system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency
912system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency
913system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency
914system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency
915system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
916system.cpu.dcache.replacements 1673020 # number of replacements
917system.cpu.dcache.tagsinuse 511.997654 # Cycle average of tags in use
918system.cpu.dcache.total_refs 19008279 # Total number of references to valid blocks.
919system.cpu.dcache.sampled_refs 1673532 # Sample count of references to valid blocks.
920system.cpu.dcache.avg_refs 11.358181 # Average number of references to valid blocks.
921system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit.
922system.cpu.dcache.occ_blocks::cpu.data 511.997654 # Average occupied blocks per requestor
923system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
924system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
925system.cpu.dcache.ReadReq_hits::cpu.data 10932679 # number of ReadReq hits
926system.cpu.dcache.ReadReq_hits::total 10932679 # number of ReadReq hits
927system.cpu.dcache.WriteReq_hits::cpu.data 8073031 # number of WriteReq hits
928system.cpu.dcache.WriteReq_hits::total 8073031 # number of WriteReq hits
929system.cpu.dcache.demand_hits::cpu.data 19005710 # number of demand (read+write) hits
930system.cpu.dcache.demand_hits::total 19005710 # number of demand (read+write) hits
931system.cpu.dcache.overall_hits::cpu.data 19005710 # number of overall hits
932system.cpu.dcache.overall_hits::total 19005710 # number of overall hits
933system.cpu.dcache.ReadReq_misses::cpu.data 2430444 # number of ReadReq misses
934system.cpu.dcache.ReadReq_misses::total 2430444 # number of ReadReq misses
935system.cpu.dcache.WriteReq_misses::cpu.data 317095 # number of WriteReq misses
936system.cpu.dcache.WriteReq_misses::total 317095 # number of WriteReq misses
937system.cpu.dcache.demand_misses::cpu.data 2747539 # number of demand (read+write) misses
938system.cpu.dcache.demand_misses::total 2747539 # number of demand (read+write) misses
939system.cpu.dcache.overall_misses::cpu.data 2747539 # number of overall misses
940system.cpu.dcache.overall_misses::total 2747539 # number of overall misses
941system.cpu.dcache.ReadReq_miss_latency::cpu.data 45216991000 # number of ReadReq miss cycles
942system.cpu.dcache.ReadReq_miss_latency::total 45216991000 # number of ReadReq miss cycles
943system.cpu.dcache.WriteReq_miss_latency::cpu.data 10602716492 # number of WriteReq miss cycles
944system.cpu.dcache.WriteReq_miss_latency::total 10602716492 # number of WriteReq miss cycles
945system.cpu.dcache.demand_miss_latency::cpu.data 55819707492 # number of demand (read+write) miss cycles
946system.cpu.dcache.demand_miss_latency::total 55819707492 # number of demand (read+write) miss cycles
947system.cpu.dcache.overall_miss_latency::cpu.data 55819707492 # number of overall miss cycles
948system.cpu.dcache.overall_miss_latency::total 55819707492 # number of overall miss cycles
949system.cpu.dcache.ReadReq_accesses::cpu.data 13363123 # number of ReadReq accesses(hits+misses)
950system.cpu.dcache.ReadReq_accesses::total 13363123 # number of ReadReq accesses(hits+misses)
951system.cpu.dcache.WriteReq_accesses::cpu.data 8390126 # number of WriteReq accesses(hits+misses)
952system.cpu.dcache.WriteReq_accesses::total 8390126 # number of WriteReq accesses(hits+misses)
953system.cpu.dcache.demand_accesses::cpu.data 21753249 # number of demand (read+write) accesses
954system.cpu.dcache.demand_accesses::total 21753249 # number of demand (read+write) accesses
955system.cpu.dcache.overall_accesses::cpu.data 21753249 # number of overall (read+write) accesses
956system.cpu.dcache.overall_accesses::total 21753249 # number of overall (read+write) accesses
957system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181877 # miss rate for ReadReq accesses
958system.cpu.dcache.ReadReq_miss_rate::total 0.181877 # miss rate for ReadReq accesses
959system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037794 # miss rate for WriteReq accesses
960system.cpu.dcache.WriteReq_miss_rate::total 0.037794 # miss rate for WriteReq accesses
961system.cpu.dcache.demand_miss_rate::cpu.data 0.126305 # miss rate for demand accesses
962system.cpu.dcache.demand_miss_rate::total 0.126305 # miss rate for demand accesses
963system.cpu.dcache.overall_miss_rate::cpu.data 0.126305 # miss rate for overall accesses
964system.cpu.dcache.overall_miss_rate::total 0.126305 # miss rate for overall accesses
965system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18604.415901 # average ReadReq miss latency
966system.cpu.dcache.ReadReq_avg_miss_latency::total 18604.415901 # average ReadReq miss latency
967system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33437.034617 # average WriteReq miss latency
968system.cpu.dcache.WriteReq_avg_miss_latency::total 33437.034617 # average WriteReq miss latency
969system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency
970system.cpu.dcache.demand_avg_miss_latency::total 20316.256654 # average overall miss latency
971system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency
972system.cpu.dcache.overall_avg_miss_latency::total 20316.256654 # average overall miss latency
973system.cpu.dcache.blocked_cycles::no_mshrs 27551492 # number of cycles access was blocked
974system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
975system.cpu.dcache.blocked::no_mshrs 4916 # number of cycles access was blocked
976system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
977system.cpu.dcache.avg_blocked_cycles::no_mshrs 5604.453214 # average number of cycles each access was blocked
978system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
979system.cpu.dcache.fast_writes 0 # number of fast writes performed
980system.cpu.dcache.cache_copies 0 # number of cache copies performed
981system.cpu.dcache.writebacks::writebacks 1572175 # number of writebacks
982system.cpu.dcache.writebacks::total 1572175 # number of writebacks
983system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1048961 # number of ReadReq MSHR hits
984system.cpu.dcache.ReadReq_mshr_hits::total 1048961 # number of ReadReq MSHR hits
985system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22710 # number of WriteReq MSHR hits
986system.cpu.dcache.WriteReq_mshr_hits::total 22710 # number of WriteReq MSHR hits
987system.cpu.dcache.demand_mshr_hits::cpu.data 1071671 # number of demand (read+write) MSHR hits
988system.cpu.dcache.demand_mshr_hits::total 1071671 # number of demand (read+write) MSHR hits
989system.cpu.dcache.overall_mshr_hits::cpu.data 1071671 # number of overall MSHR hits
990system.cpu.dcache.overall_mshr_hits::total 1071671 # number of overall MSHR hits
991system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381483 # number of ReadReq MSHR misses
992system.cpu.dcache.ReadReq_mshr_misses::total 1381483 # number of ReadReq MSHR misses
993system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294385 # number of WriteReq MSHR misses
994system.cpu.dcache.WriteReq_mshr_misses::total 294385 # number of WriteReq MSHR misses
995system.cpu.dcache.demand_mshr_misses::cpu.data 1675868 # number of demand (read+write) MSHR misses
996system.cpu.dcache.demand_mshr_misses::total 1675868 # number of demand (read+write) MSHR misses
997system.cpu.dcache.overall_mshr_misses::cpu.data 1675868 # number of overall MSHR misses
998system.cpu.dcache.overall_mshr_misses::total 1675868 # number of overall MSHR misses
999system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23305790513 # number of ReadReq MSHR miss cycles
1000system.cpu.dcache.ReadReq_mshr_miss_latency::total 23305790513 # number of ReadReq MSHR miss cycles
1001system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9339566493 # number of WriteReq MSHR miss cycles
1002system.cpu.dcache.WriteReq_mshr_miss_latency::total 9339566493 # number of WriteReq MSHR miss cycles
1003system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32645357006 # number of demand (read+write) MSHR miss cycles
1004system.cpu.dcache.demand_mshr_miss_latency::total 32645357006 # number of demand (read+write) MSHR miss cycles
1005system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32645357006 # number of overall MSHR miss cycles
1006system.cpu.dcache.overall_mshr_miss_latency::total 32645357006 # number of overall MSHR miss cycles
1007system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96733569500 # number of ReadReq MSHR uncacheable cycles
1008system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96733569500 # number of ReadReq MSHR uncacheable cycles
1009system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2477085000 # number of WriteReq MSHR uncacheable cycles
1010system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2477085000 # number of WriteReq MSHR uncacheable cycles
1011system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99210654500 # number of overall MSHR uncacheable cycles
1012system.cpu.dcache.overall_mshr_uncacheable_latency::total 99210654500 # number of overall MSHR uncacheable cycles
1013system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103380 # mshr miss rate for ReadReq accesses
1014system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103380 # mshr miss rate for ReadReq accesses
1015system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035087 # mshr miss rate for WriteReq accesses
1016system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035087 # mshr miss rate for WriteReq accesses
1017system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for demand accesses
1018system.cpu.dcache.demand_mshr_miss_rate::total 0.077040 # mshr miss rate for demand accesses
1019system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for overall accesses
1020system.cpu.dcache.overall_mshr_miss_rate::total 0.077040 # mshr miss rate for overall accesses
1021system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16870.124723 # average ReadReq mshr miss latency
1022system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16870.124723 # average ReadReq mshr miss latency
1023system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31725.687426 # average WriteReq mshr miss latency
1024system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31725.687426 # average WriteReq mshr miss latency
1025system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency
1026system.cpu.dcache.demand_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency
1027system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency
1028system.cpu.dcache.overall_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency
1029system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1030system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1031system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1032system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1033system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1034system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1035system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1036system.cpu.kern.inst.arm 0 # number of arm instructions executed
1037system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1038
1039---------- End Simulation Statistics ----------