1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.133818 # Number of seconds simulated
4sim_ticks 5133817564000 # Number of ticks simulated
5final_tick 5133817564000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 116267 # Simulator instruction rate (inst/s)
8host_op_rate 229827 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1463849171 # Simulator tick rate (ticks/s)
10host_mem_usage 730944 # Number of bytes of host memory used
11host_seconds 3507.07 # Real time elapsed on the host
12sim_insts 407756178 # Number of instructions simulated
13sim_ops 806017145 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2427456 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 1027392 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 10775296 # Number of bytes read from this memory
19system.physmem.bytes_read::total 14234240 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 1027392 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 1027392 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 9523712 # Number of bytes written to this memory
23system.physmem.bytes_written::total 9523712 # Number of bytes written to this memory
24system.physmem.num_reads::pc.south_bridge.ide 37929 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.inst 16053 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.data 168364 # Number of read requests responded to by this memory
29system.physmem.num_reads::total 222410 # Number of read requests responded to by this memory
30system.physmem.num_writes::writebacks 148808 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 148808 # Number of write requests responded to by this memory
32system.physmem.bw_read::pc.south_bridge.ide 472836 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.dtb.walker 723 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.inst 200122 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.data 2098886 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::total 2772642 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_inst_read::cpu.inst 200122 # Instruction read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::total 200122 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_write::writebacks 1855094 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_write::total 1855094 # Write bandwidth from this memory (bytes/s)
42system.physmem.bw_total::writebacks 1855094 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::pc.south_bridge.ide 472836 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 723 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.inst 200122 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.data 2098886 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 4627736 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.readReqs 222410 # Total number of read requests accepted by DRAM controller
50system.physmem.writeReqs 148808 # Total number of write requests accepted by DRAM controller
51system.physmem.readBursts 222410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
52system.physmem.writeBursts 148808 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
53system.physmem.bytesRead 14234240 # Total number of bytes read from memory
54system.physmem.bytesWritten 9523712 # Total number of bytes written to memory
55system.physmem.bytesConsumedRd 14234240 # bytesRead derated as per pkt->getSize()
56system.physmem.bytesConsumedWr 9523712 # bytesWritten derated as per pkt->getSize()
57system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by write Q
58system.physmem.neitherReadNorWrite 1680 # Reqs where no action is needed
59system.physmem.perBankRdReqs::0 14445 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::1 13880 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::2 14292 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::3 13655 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::4 13870 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::5 13478 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::6 13505 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::7 14003 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::8 13721 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::9 13556 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::10 13489 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::11 13720 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::12 14708 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::13 14278 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::14 14115 # Track reads on a per bank basis
74system.physmem.perBankRdReqs::15 13636 # Track reads on a per bank basis
75system.physmem.perBankWrReqs::0 9830 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::1 9327 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::2 9583 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::3 9096 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::4 9291 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::5 8966 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::6 8927 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::7 9335 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::8 9016 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::9 8977 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::10 8994 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::11 9147 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::12 9992 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::13 9572 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::14 9603 # Track writes on a per bank basis
90system.physmem.perBankWrReqs::15 9152 # Track writes on a per bank basis
91system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
92system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
93system.physmem.totGap 5133817509500 # Total gap between requests
94system.physmem.readPktSize::0 0 # Categorize read packet sizes
95system.physmem.readPktSize::1 0 # Categorize read packet sizes
96system.physmem.readPktSize::2 0 # Categorize read packet sizes
97system.physmem.readPktSize::3 0 # Categorize read packet sizes
98system.physmem.readPktSize::4 0 # Categorize read packet sizes
99system.physmem.readPktSize::5 0 # Categorize read packet sizes
100system.physmem.readPktSize::6 222410 # Categorize read packet sizes
101system.physmem.writePktSize::0 0 # Categorize write packet sizes
102system.physmem.writePktSize::1 0 # Categorize write packet sizes
103system.physmem.writePktSize::2 0 # Categorize write packet sizes
104system.physmem.writePktSize::3 0 # Categorize write packet sizes
105system.physmem.writePktSize::4 0 # Categorize write packet sizes
106system.physmem.writePktSize::5 0 # Categorize write packet sizes
107system.physmem.writePktSize::6 148808 # Categorize write packet sizes
108system.physmem.rdQLenPdf::0 174478 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::1 21469 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::2 7432 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::3 2969 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::4 2498 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::5 2034 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::7 1131 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::8 1042 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::9 990 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::10 926 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::11 916 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::12 874 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::13 901 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::14 960 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::15 914 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::16 731 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::17 470 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::18 209 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::19 134 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::20 26 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
140system.physmem.wrQLenPdf::0 5406 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::1 5728 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::2 6410 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::3 6444 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::4 6447 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::6 6460 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::7 6460 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::8 6462 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::9 6470 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::10 6470 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::11 6470 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::12 6470 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::13 6470 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::14 6470 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::15 6470 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::16 6470 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::17 6470 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::18 6470 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::19 6470 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::20 6470 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::21 6469 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::22 6469 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::23 1064 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::24 742 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::25 60 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
172system.physmem.bytesPerActivate::samples 62679 # Bytes accessed per row activation
173system.physmem.bytesPerActivate::mean 378.930359 # Bytes accessed per row activation
174system.physmem.bytesPerActivate::gmean 154.401970 # Bytes accessed per row activation
175system.physmem.bytesPerActivate::stdev 1268.483208 # Bytes accessed per row activation
176system.physmem.bytesPerActivate::64-67 27823 44.39% 44.39% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::128-131 9775 15.60% 59.99% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::192-195 5839 9.32% 69.30% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::256-259 3939 6.28% 75.59% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::320-323 2540 4.05% 79.64% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::384-387 2068 3.30% 82.94% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::448-451 1534 2.45% 85.38% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::512-515 1237 1.97% 87.36% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::576-579 969 1.55% 88.90% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::640-643 885 1.41% 90.32% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::704-707 570 0.91% 91.23% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::768-771 566 0.90% 92.13% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::832-835 409 0.65% 92.78% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::896-899 368 0.59% 93.37% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::960-963 359 0.57% 93.94% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1024-1027 470 0.75% 94.69% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1088-1091 261 0.42% 95.11% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1152-1155 223 0.36% 95.46% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1216-1219 183 0.29% 95.75% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1280-1283 154 0.25% 96.00% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1344-1347 153 0.24% 96.24% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1408-1411 166 0.26% 96.51% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1472-1475 503 0.80% 97.31% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1536-1539 192 0.31% 97.62% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1600-1603 116 0.19% 97.80% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1664-1667 97 0.15% 97.96% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1728-1731 69 0.11% 98.07% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1792-1795 63 0.10% 98.17% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1856-1859 31 0.05% 98.22% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1920-1923 26 0.04% 98.26% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::1984-1987 27 0.04% 98.30% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2048-2051 24 0.04% 98.34% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2112-2115 21 0.03% 98.37% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2176-2179 14 0.02% 98.40% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::2240-2243 16 0.03% 98.42% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2304-2307 18 0.03% 98.45% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.48% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2432-2435 13 0.02% 98.50% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::2496-2499 7 0.01% 98.51% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.52% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.54% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::2688-2691 6 0.01% 98.54% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::2752-2755 5 0.01% 98.55% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::2816-2819 7 0.01% 98.56% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::2880-2883 8 0.01% 98.58% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.58% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3008-3011 3 0.00% 98.59% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3072-3075 4 0.01% 98.59% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.60% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3200-3203 4 0.01% 98.61% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.62% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.63% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.63% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.65% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::3520-3523 4 0.01% 98.65% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::3584-3587 6 0.01% 98.66% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.67% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::3712-3715 2 0.00% 98.67% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::3776-3779 10 0.02% 98.69% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::3840-3843 4 0.01% 98.69% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::3904-3907 1 0.00% 98.69% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::3968-3971 2 0.00% 98.70% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.70% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4096-4099 25 0.04% 98.74% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4160-4163 7 0.01% 98.76% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4224-4227 2 0.00% 98.76% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.76% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4352-4355 5 0.01% 98.77% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.77% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.78% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::4544-4547 5 0.01% 98.79% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.79% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.79% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::4800-4803 1 0.00% 98.79% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.79% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::4928-4931 5 0.01% 98.80% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.81% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.81% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::5120-5123 6 0.01% 98.82% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.82% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::5248-5251 2 0.00% 98.83% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.83% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.83% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::5440-5443 2 0.00% 98.83% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::5568-5571 2 0.00% 98.84% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.84% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::5696-5699 3 0.00% 98.84% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.85% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.85% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::6016-6019 2 0.00% 98.85% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.85% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::6144-6147 5 0.01% 98.86% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.86% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::6272-6275 2 0.00% 98.87% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.87% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::6464-6467 2 0.00% 98.87% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.88% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::6720-6723 5 0.01% 98.88% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::6848-6851 3 0.00% 98.89% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::6912-6915 8 0.01% 98.90% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::6976-6979 2 0.00% 98.90% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::7040-7043 1 0.00% 98.91% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.91% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.92% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.92% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.92% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.92% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::7616-7619 3 0.00% 98.93% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.93% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::7808-7811 2 0.00% 98.93% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.93% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.94% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::8064-8067 3 0.00% 98.94% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::8128-8131 4 0.01% 98.95% # Bytes accessed per row activation
292system.physmem.bytesPerActivate::8192-8195 340 0.54% 99.49% # Bytes accessed per row activation
293system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.49% # Bytes accessed per row activation
294system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.49% # Bytes accessed per row activation
295system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.50% # Bytes accessed per row activation
296system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.50% # Bytes accessed per row activation
297system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.50% # Bytes accessed per row activation
298system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.50% # Bytes accessed per row activation
299system.physmem.bytesPerActivate::8896-8899 2 0.00% 99.50% # Bytes accessed per row activation
300system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.51% # Bytes accessed per row activation
301system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.51% # Bytes accessed per row activation
302system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation
303system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.52% # Bytes accessed per row activation
304system.physmem.bytesPerActivate::9600-9603 3 0.00% 99.52% # Bytes accessed per row activation
305system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.52% # Bytes accessed per row activation
306system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.53% # Bytes accessed per row activation
307system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.53% # Bytes accessed per row activation
308system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.53% # Bytes accessed per row activation
309system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.54% # Bytes accessed per row activation
310system.physmem.bytesPerActivate::10048-10051 2 0.00% 99.54% # Bytes accessed per row activation
311system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.54% # Bytes accessed per row activation
312system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.55% # Bytes accessed per row activation
313system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.55% # Bytes accessed per row activation
314system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.55% # Bytes accessed per row activation
315system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.55% # Bytes accessed per row activation
316system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation
317system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation
318system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.56% # Bytes accessed per row activation
319system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.56% # Bytes accessed per row activation
320system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.56% # Bytes accessed per row activation
321system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.56% # Bytes accessed per row activation
322system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.56% # Bytes accessed per row activation
323system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.57% # Bytes accessed per row activation
324system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.57% # Bytes accessed per row activation
325system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.57% # Bytes accessed per row activation
326system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.57% # Bytes accessed per row activation
327system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.58% # Bytes accessed per row activation
328system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.58% # Bytes accessed per row activation
329system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.58% # Bytes accessed per row activation
330system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation
331system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation
332system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.59% # Bytes accessed per row activation
333system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.59% # Bytes accessed per row activation
334system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.59% # Bytes accessed per row activation
335system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.59% # Bytes accessed per row activation
336system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.60% # Bytes accessed per row activation
337system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.60% # Bytes accessed per row activation
338system.physmem.bytesPerActivate::14336-14339 4 0.01% 99.60% # Bytes accessed per row activation
339system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.61% # Bytes accessed per row activation
340system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.61% # Bytes accessed per row activation
341system.physmem.bytesPerActivate::14912-14915 32 0.05% 99.66% # Bytes accessed per row activation
342system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.68% # Bytes accessed per row activation
343system.physmem.bytesPerActivate::15040-15043 7 0.01% 99.69% # Bytes accessed per row activation
344system.physmem.bytesPerActivate::15104-15107 11 0.02% 99.71% # Bytes accessed per row activation
345system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.72% # Bytes accessed per row activation
346system.physmem.bytesPerActivate::15232-15235 5 0.01% 99.73% # Bytes accessed per row activation
347system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.74% # Bytes accessed per row activation
348system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.74% # Bytes accessed per row activation
349system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.75% # Bytes accessed per row activation
350system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.76% # Bytes accessed per row activation
351system.physmem.bytesPerActivate::15552-15555 6 0.01% 99.77% # Bytes accessed per row activation
352system.physmem.bytesPerActivate::15616-15619 5 0.01% 99.77% # Bytes accessed per row activation
353system.physmem.bytesPerActivate::15680-15683 9 0.01% 99.79% # Bytes accessed per row activation
354system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.79% # Bytes accessed per row activation
355system.physmem.bytesPerActivate::15808-15811 3 0.00% 99.80% # Bytes accessed per row activation
356system.physmem.bytesPerActivate::15872-15875 8 0.01% 99.81% # Bytes accessed per row activation
357system.physmem.bytesPerActivate::15936-15939 3 0.00% 99.81% # Bytes accessed per row activation
358system.physmem.bytesPerActivate::16000-16003 8 0.01% 99.83% # Bytes accessed per row activation
359system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.83% # Bytes accessed per row activation
360system.physmem.bytesPerActivate::16128-16131 8 0.01% 99.84% # Bytes accessed per row activation
361system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.85% # Bytes accessed per row activation
362system.physmem.bytesPerActivate::16256-16259 15 0.02% 99.88% # Bytes accessed per row activation
363system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.89% # Bytes accessed per row activation
364system.physmem.bytesPerActivate::16384-16387 59 0.09% 99.98% # Bytes accessed per row activation
365system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.99% # Bytes accessed per row activation
366system.physmem.bytesPerActivate::16512-16515 2 0.00% 99.99% # Bytes accessed per row activation
367system.physmem.bytesPerActivate::16576-16579 3 0.00% 100.00% # Bytes accessed per row activation
368system.physmem.bytesPerActivate::16704-16707 1 0.00% 100.00% # Bytes accessed per row activation
369system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation
370system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation
371system.physmem.bytesPerActivate::total 62679 # Bytes accessed per row activation
372system.physmem.totQLat 3976321749 # Total cycles spent in queuing delays
373system.physmem.totMemAccLat 8255787999 # Sum of mem lat for all requests
374system.physmem.totBusLat 1111755000 # Total cycles spent in databus access
375system.physmem.totBankLat 3167711250 # Total cycles spent in bank access
376system.physmem.avgQLat 17883.08 # Average queueing delay per request
377system.physmem.avgBankLat 14246.44 # Average bank access latency per request
378system.physmem.avgBusLat 5000.00 # Average bus latency per request
379system.physmem.avgMemAccLat 37129.53 # Average memory access latency
380system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s
381system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
382system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s
383system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
384system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
385system.physmem.busUtil 0.04 # Data bus utilization in percentage
386system.physmem.avgRdQLen 0.00 # Average read queue length over time
387system.physmem.avgWrQLen 11.10 # Average write queue length over time
388system.physmem.readRowHits 198876 # Number of row buffer hits during reads
389system.physmem.writeRowHits 109583 # Number of row buffer hits during writes
390system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads
391system.physmem.writeRowHitRate 73.64 # Row buffer hit rate for writes
392system.physmem.avgGap 13829656.72 # Average gap between requests
393system.membus.throughput 5107370 # Throughput (bytes/s)
394system.membus.trans_dist::ReadReq 662136 # Transaction distribution
395system.membus.trans_dist::ReadResp 662131 # Transaction distribution
396system.membus.trans_dist::WriteReq 13778 # Transaction distribution
397system.membus.trans_dist::WriteResp 13778 # Transaction distribution
398system.membus.trans_dist::Writeback 148808 # Transaction distribution
399system.membus.trans_dist::UpgradeReq 2204 # Transaction distribution
400system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution
401system.membus.trans_dist::ReadExReq 179955 # Transaction distribution
402system.membus.trans_dist::ReadExResp 179952 # Transaction distribution
403system.membus.trans_dist::MessageReq 1643 # Transaction distribution
404system.membus.trans_dist::MessageResp 1643 # Transaction distribution
405system.membus.trans_dist::BadAddressError 5 # Transaction distribution
406system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
407system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
408system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
409system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes)
410system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475656 # Packet count per connected master and slave (bytes)
411system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes)
412system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721824 # Packet count per connected master and slave (bytes)
413system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132231 # Packet count per connected master and slave (bytes)
414system.membus.pkt_count_system.iocache.mem_side::total 132231 # Packet count per connected master and slave (bytes)
415system.membus.pkt_count::total 1857341 # Packet count per connected master and slave (bytes)
416system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
417system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
418system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
419system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes)
420system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18343808 # Cumulative packet size per connected master and slave (bytes)
421system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20135781 # Cumulative packet size per connected master and slave (bytes)
422system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5414144 # Cumulative packet size per connected master and slave (bytes)
423system.membus.tot_pkt_size_system.iocache.mem_side::total 5414144 # Cumulative packet size per connected master and slave (bytes)
424system.membus.tot_pkt_size::total 25556497 # Cumulative packet size per connected master and slave (bytes)
425system.membus.data_through_bus 25556497 # Total data (bytes)
426system.membus.snoop_data_through_bus 663808 # Total snoop data (bytes)
427system.membus.reqLayer0.occupancy 250614500 # Layer occupancy (ticks)
428system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
429system.membus.reqLayer1.occupancy 583282500 # Layer occupancy (ticks)
430system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
431system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
432system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
433system.membus.reqLayer3.occupancy 1610621247 # Layer occupancy (ticks)
434system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
435system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks)
436system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
437system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
438system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
439system.membus.respLayer2.occupancy 3158121946 # Layer occupancy (ticks)
440system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
441system.membus.respLayer4.occupancy 429462997 # Layer occupancy (ticks)
442system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
443system.iocache.tags.replacements 47580 # number of replacements
444system.iocache.tags.tagsinuse 0.104004 # Cycle average of tags in use
445system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
446system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks.
447system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
448system.iocache.tags.warmup_cycle 4992837152000 # Cycle when the warmup percentage was hit.
449system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.104004 # Average occupied blocks per requestor
450system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006500 # Average percentage of cache occupancy
451system.iocache.tags.occ_percent::total 0.006500 # Average percentage of cache occupancy
452system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses
453system.iocache.ReadReq_misses::total 915 # number of ReadReq misses
454system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
455system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
456system.iocache.demand_misses::pc.south_bridge.ide 47635 # number of demand (read+write) misses
457system.iocache.demand_misses::total 47635 # number of demand (read+write) misses
458system.iocache.overall_misses::pc.south_bridge.ide 47635 # number of overall misses
459system.iocache.overall_misses::total 47635 # number of overall misses
460system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 155029196 # number of ReadReq miss cycles
461system.iocache.ReadReq_miss_latency::total 155029196 # number of ReadReq miss cycles
462system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10272164340 # number of WriteReq miss cycles
463system.iocache.WriteReq_miss_latency::total 10272164340 # number of WriteReq miss cycles
464system.iocache.demand_miss_latency::pc.south_bridge.ide 10427193536 # number of demand (read+write) miss cycles
465system.iocache.demand_miss_latency::total 10427193536 # number of demand (read+write) miss cycles
466system.iocache.overall_miss_latency::pc.south_bridge.ide 10427193536 # number of overall miss cycles
467system.iocache.overall_miss_latency::total 10427193536 # number of overall miss cycles
468system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses)
469system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
470system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
471system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
472system.iocache.demand_accesses::pc.south_bridge.ide 47635 # number of demand (read+write) accesses
473system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses
474system.iocache.overall_accesses::pc.south_bridge.ide 47635 # number of overall (read+write) accesses
475system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses
476system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
477system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
478system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
479system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
480system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
481system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
482system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
483system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
484system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169430.815301 # average ReadReq miss latency
485system.iocache.ReadReq_avg_miss_latency::total 169430.815301 # average ReadReq miss latency
486system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 219866.531250 # average WriteReq miss latency
487system.iocache.WriteReq_avg_miss_latency::total 219866.531250 # average WriteReq miss latency
488system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 218897.733515 # average overall miss latency
489system.iocache.demand_avg_miss_latency::total 218897.733515 # average overall miss latency
490system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 218897.733515 # average overall miss latency
491system.iocache.overall_avg_miss_latency::total 218897.733515 # average overall miss latency
492system.iocache.blocked_cycles::no_mshrs 145846 # number of cycles access was blocked
493system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
494system.iocache.blocked::no_mshrs 13667 # number of cycles access was blocked
495system.iocache.blocked::no_targets 0 # number of cycles access was blocked
496system.iocache.avg_blocked_cycles::no_mshrs 10.671398 # average number of cycles each access was blocked
497system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
498system.iocache.fast_writes 0 # number of fast writes performed
499system.iocache.cache_copies 0 # number of cache copies performed
500system.iocache.writebacks::writebacks 46667 # number of writebacks
501system.iocache.writebacks::total 46667 # number of writebacks
502system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses
503system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses
504system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
505system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
506system.iocache.demand_mshr_misses::pc.south_bridge.ide 47635 # number of demand (read+write) MSHR misses
507system.iocache.demand_mshr_misses::total 47635 # number of demand (read+write) MSHR misses
508system.iocache.overall_mshr_misses::pc.south_bridge.ide 47635 # number of overall MSHR misses
509system.iocache.overall_mshr_misses::total 47635 # number of overall MSHR misses
510system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 107414696 # number of ReadReq MSHR miss cycles
511system.iocache.ReadReq_mshr_miss_latency::total 107414696 # number of ReadReq MSHR miss cycles
512system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7841262846 # number of WriteReq MSHR miss cycles
513system.iocache.WriteReq_mshr_miss_latency::total 7841262846 # number of WriteReq MSHR miss cycles
514system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7948677542 # number of demand (read+write) MSHR miss cycles
515system.iocache.demand_mshr_miss_latency::total 7948677542 # number of demand (read+write) MSHR miss cycles
516system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7948677542 # number of overall MSHR miss cycles
517system.iocache.overall_mshr_miss_latency::total 7948677542 # number of overall MSHR miss cycles
518system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
519system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
520system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
521system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
522system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
523system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
524system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
525system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
526system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117393.110383 # average ReadReq mshr miss latency
527system.iocache.ReadReq_avg_mshr_miss_latency::total 117393.110383 # average ReadReq mshr miss latency
528system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 167835.249272 # average WriteReq mshr miss latency
529system.iocache.WriteReq_avg_mshr_miss_latency::total 167835.249272 # average WriteReq mshr miss latency
530system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 166866.328162 # average overall mshr miss latency
531system.iocache.demand_avg_mshr_miss_latency::total 166866.328162 # average overall mshr miss latency
532system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 166866.328162 # average overall mshr miss latency
533system.iocache.overall_avg_mshr_miss_latency::total 166866.328162 # average overall mshr miss latency
534system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
535system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
536system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
537system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
538system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
539system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
540system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
541system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
542system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
543system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
544system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
545system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
546system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
547system.iobus.throughput 638173 # Throughput (bytes/s)
548system.iobus.trans_dist::ReadReq 225571 # Transaction distribution
549system.iobus.trans_dist::ReadResp 225571 # Transaction distribution
550system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
551system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
552system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
553system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
554system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
555system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
556system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
557system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
558system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
559system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
560system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
561system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
562system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
563system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
564system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
565system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
566system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
567system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
568system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
569system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
570system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
571system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
572system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
573system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes)
574system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes)
575system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
576system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
577system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes)
578system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
579system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
580system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
581system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
582system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
583system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
584system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
585system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
586system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
587system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
588system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
589system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
590system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
591system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
592system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
593system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
594system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
595system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
596system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
597system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes)
598system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes)
599system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
600system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
601system.iobus.tot_pkt_size::total 3276264 # Cumulative packet size per connected master and slave (bytes)
602system.iobus.data_through_bus 3276264 # Total data (bytes)
603system.iobus.reqLayer0.occupancy 3919850 # Layer occupancy (ticks)
604system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
605system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
606system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
607system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
608system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
609system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
610system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
611system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
612system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
613system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
614system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
615system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
616system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
617system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
618system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
619system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
620system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
621system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
622system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
623system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
624system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
625system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
626system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
627system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
628system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
629system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
630system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
631system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
632system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
633system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
634system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
635system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
636system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
637system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
638system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
639system.iobus.reqLayer18.occupancy 424475539 # Layer occupancy (ticks)
640system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
641system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
642system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
643system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
644system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
645system.iobus.respLayer1.occupancy 53455003 # Layer occupancy (ticks)
646system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
647system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
648system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
649system.cpu.branchPred.lookups 85568278 # Number of BP lookups
650system.cpu.branchPred.condPredicted 85568278 # Number of conditional branches predicted
651system.cpu.branchPred.condIncorrect 875805 # Number of conditional branches incorrect
652system.cpu.branchPred.BTBLookups 79194721 # Number of BTB lookups
653system.cpu.branchPred.BTBHits 77515005 # Number of BTB hits
654system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
655system.cpu.branchPred.BTBHitPct 97.879005 # BTB Hit Percentage
656system.cpu.branchPred.usedRAS 1436703 # Number of times the RAS was used to get a target.
657system.cpu.branchPred.RASInCorrect 179530 # Number of incorrect RAS predictions.
658system.cpu.numCycles 453826303 # number of cpu cycles simulated
659system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
660system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
661system.cpu.fetch.icacheStallCycles 25491689 # Number of cycles fetch is stalled on an Icache miss
662system.cpu.fetch.Insts 422571983 # Number of instructions fetch has processed
663system.cpu.fetch.Branches 85568278 # Number of branches that fetch encountered
664system.cpu.fetch.predictedBranches 78951708 # Number of branches that fetch has predicted taken
665system.cpu.fetch.Cycles 162597841 # Number of cycles fetch has run and was not squashing or blocked
666system.cpu.fetch.SquashCycles 3951278 # Number of cycles fetch has spent squashing
667system.cpu.fetch.TlbCycles 103753 # Number of cycles fetch has spent waiting for tlb
668system.cpu.fetch.BlockedCycles 71390541 # Number of cycles fetch has spent blocked
669system.cpu.fetch.MiscStallCycles 42483 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
670system.cpu.fetch.PendingTrapStallCycles 91488 # Number of stall cycles due to pending traps
671system.cpu.fetch.IcacheWaitRetryStallCycles 407 # Number of stall cycles due to full MSHR
672system.cpu.fetch.CacheLines 8456173 # Number of cache lines fetched
673system.cpu.fetch.IcacheSquashes 381386 # Number of outstanding Icache misses that were squashed
674system.cpu.fetch.ItlbSquashes 2285 # Number of outstanding ITLB misses that were squashed
675system.cpu.fetch.rateDist::samples 262749158 # Number of instructions fetched each cycle (Total)
676system.cpu.fetch.rateDist::mean 3.176501 # Number of instructions fetched each cycle (Total)
677system.cpu.fetch.rateDist::stdev 3.411322 # Number of instructions fetched each cycle (Total)
678system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
679system.cpu.fetch.rateDist::0 100566215 38.27% 38.27% # Number of instructions fetched each cycle (Total)
680system.cpu.fetch.rateDist::1 1530086 0.58% 38.86% # Number of instructions fetched each cycle (Total)
681system.cpu.fetch.rateDist::2 71818264 27.33% 66.19% # Number of instructions fetched each cycle (Total)
682system.cpu.fetch.rateDist::3 889095 0.34% 66.53% # Number of instructions fetched each cycle (Total)
683system.cpu.fetch.rateDist::4 1565087 0.60% 67.12% # Number of instructions fetched each cycle (Total)
684system.cpu.fetch.rateDist::5 2386199 0.91% 68.03% # Number of instructions fetched each cycle (Total)
685system.cpu.fetch.rateDist::6 1016423 0.39% 68.42% # Number of instructions fetched each cycle (Total)
686system.cpu.fetch.rateDist::7 1323196 0.50% 68.92% # Number of instructions fetched each cycle (Total)
687system.cpu.fetch.rateDist::8 81654593 31.08% 100.00% # Number of instructions fetched each cycle (Total)
688system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
689system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
690system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
691system.cpu.fetch.rateDist::total 262749158 # Number of instructions fetched each cycle (Total)
692system.cpu.fetch.branchRate 0.188549 # Number of branch fetches per cycle
693system.cpu.fetch.rate 0.931132 # Number of inst fetches per cycle
694system.cpu.decode.IdleCycles 29394099 # Number of cycles decode is idle
695system.cpu.decode.BlockedCycles 68537094 # Number of cycles decode is blocked
696system.cpu.decode.RunCycles 158445926 # Number of cycles decode is running
697system.cpu.decode.UnblockCycles 3341083 # Number of cycles decode is unblocking
698system.cpu.decode.SquashCycles 3030956 # Number of cycles decode is squashing
699system.cpu.decode.DecodedInsts 832311849 # Number of instructions handled by decode
700system.cpu.decode.SquashedInsts 975 # Number of squashed instructions handled by decode
701system.cpu.rename.SquashCycles 3030956 # Number of cycles rename is squashing
702system.cpu.rename.IdleCycles 32089229 # Number of cycles rename is idle
703system.cpu.rename.BlockCycles 43247389 # Number of cycles rename is blocking
704system.cpu.rename.serializeStallCycles 12548061 # count of cycles rename stalled for serializing inst
705system.cpu.rename.RunCycles 158740332 # Number of cycles rename is running
706system.cpu.rename.UnblockCycles 13093191 # Number of cycles rename is unblocking
707system.cpu.rename.RenamedInsts 829412646 # Number of instructions processed by rename
708system.cpu.rename.ROBFullEvents 22400 # Number of times rename has blocked due to ROB full
709system.cpu.rename.IQFullEvents 6072204 # Number of times rename has blocked due to IQ full
710system.cpu.rename.LSQFullEvents 5134846 # Number of times rename has blocked due to LSQ full
711system.cpu.rename.FullRegisterEvents 9895 # Number of times there has been no free registers
712system.cpu.rename.RenamedOperands 991013941 # Number of destination operands rename has renamed
713system.cpu.rename.RenameLookups 1799757815 # Number of register rename lookups that rename has made
714system.cpu.rename.int_rename_lookups 1799757415 # Number of integer rename lookups
715system.cpu.rename.fp_rename_lookups 400 # Number of floating rename lookups
716system.cpu.rename.CommittedMaps 963928798 # Number of HB maps that are committed
717system.cpu.rename.UndoneMaps 27085141 # Number of HB maps that are undone due to squashing
718system.cpu.rename.serializingInsts 453471 # count of serializing insts renamed
719system.cpu.rename.tempSerializingInsts 459839 # count of temporary serializing insts renamed
720system.cpu.rename.skidInsts 29598553 # count of insts added to the skid buffer
721system.cpu.memDep0.insertedLoads 16699186 # Number of loads inserted to the mem dependence unit.
722system.cpu.memDep0.insertedStores 9813003 # Number of stores inserted to the mem dependence unit.
723system.cpu.memDep0.conflictingLoads 1103116 # Number of conflicting loads.
724system.cpu.memDep0.conflictingStores 919400 # Number of conflicting stores.
725system.cpu.iq.iqInstsAdded 824665019 # Number of instructions added to the IQ (excludes non-spec)
726system.cpu.iq.iqNonSpecInstsAdded 1185670 # Number of non-speculative instructions added to the IQ
727system.cpu.iq.iqInstsIssued 820786759 # Number of instructions issued
728system.cpu.iq.iqSquashedInstsIssued 149059 # Number of squashed instructions issued
729system.cpu.iq.iqSquashedInstsExamined 19014850 # Number of squashed instructions iterated over during squash; mainly for profiling
730system.cpu.iq.iqSquashedOperandsExamined 28966021 # Number of squashed operands that are examined and possibly removed from graph
731system.cpu.iq.iqSquashedNonSpecRemoved 131061 # Number of squashed non-spec instructions that were removed
732system.cpu.iq.issued_per_cycle::samples 262749158 # Number of insts issued each cycle
733system.cpu.iq.issued_per_cycle::mean 3.123842 # Number of insts issued each cycle
734system.cpu.iq.issued_per_cycle::stdev 2.400884 # Number of insts issued each cycle
735system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
736system.cpu.iq.issued_per_cycle::0 76415434 29.08% 29.08% # Number of insts issued each cycle
737system.cpu.iq.issued_per_cycle::1 15773446 6.00% 35.09% # Number of insts issued each cycle
738system.cpu.iq.issued_per_cycle::2 10534030 4.01% 39.10% # Number of insts issued each cycle
739system.cpu.iq.issued_per_cycle::3 7363874 2.80% 41.90% # Number of insts issued each cycle
740system.cpu.iq.issued_per_cycle::4 75721487 28.82% 70.72% # Number of insts issued each cycle
741system.cpu.iq.issued_per_cycle::5 3737655 1.42% 72.14% # Number of insts issued each cycle
742system.cpu.iq.issued_per_cycle::6 72289188 27.51% 99.65% # Number of insts issued each cycle
743system.cpu.iq.issued_per_cycle::7 768072 0.29% 99.94% # Number of insts issued each cycle
744system.cpu.iq.issued_per_cycle::8 145972 0.06% 100.00% # Number of insts issued each cycle
745system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
746system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
747system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
748system.cpu.iq.issued_per_cycle::total 262749158 # Number of insts issued each cycle
749system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
750system.cpu.iq.fu_full::IntAlu 347595 33.06% 33.06% # attempts to use FU when none available
751system.cpu.iq.fu_full::IntMult 241 0.02% 33.09% # attempts to use FU when none available
752system.cpu.iq.fu_full::IntDiv 298 0.03% 33.11% # attempts to use FU when none available
753system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.11% # attempts to use FU when none available
754system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.11% # attempts to use FU when none available
755system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.11% # attempts to use FU when none available
756system.cpu.iq.fu_full::FloatMult 0 0.00% 33.11% # attempts to use FU when none available
757system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.11% # attempts to use FU when none available
758system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.11% # attempts to use FU when none available
759system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.11% # attempts to use FU when none available
760system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.11% # attempts to use FU when none available
761system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.11% # attempts to use FU when none available
762system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.11% # attempts to use FU when none available
763system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.11% # attempts to use FU when none available
764system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.11% # attempts to use FU when none available
765system.cpu.iq.fu_full::SimdMult 0 0.00% 33.11% # attempts to use FU when none available
766system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.11% # attempts to use FU when none available
767system.cpu.iq.fu_full::SimdShift 0 0.00% 33.11% # attempts to use FU when none available
768system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.11% # attempts to use FU when none available
769system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.11% # attempts to use FU when none available
770system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.11% # attempts to use FU when none available
771system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.11% # attempts to use FU when none available
772system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.11% # attempts to use FU when none available
773system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.11% # attempts to use FU when none available
774system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.11% # attempts to use FU when none available
775system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.11% # attempts to use FU when none available
776system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.11% # attempts to use FU when none available
777system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.11% # attempts to use FU when none available
778system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.11% # attempts to use FU when none available
779system.cpu.iq.fu_full::MemRead 548989 52.22% 85.34% # attempts to use FU when none available
780system.cpu.iq.fu_full::MemWrite 154170 14.66% 100.00% # attempts to use FU when none available
781system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
782system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
783system.cpu.iq.FU_type_0::No_OpClass 308427 0.04% 0.04% # Type of FU issued
784system.cpu.iq.FU_type_0::IntAlu 793336759 96.66% 96.69% # Type of FU issued
785system.cpu.iq.FU_type_0::IntMult 149572 0.02% 96.71% # Type of FU issued
786system.cpu.iq.FU_type_0::IntDiv 124334 0.02% 96.73% # Type of FU issued
787system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.73% # Type of FU issued
788system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.73% # Type of FU issued
789system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.73% # Type of FU issued
790system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.73% # Type of FU issued
791system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.73% # Type of FU issued
792system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.73% # Type of FU issued
793system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.73% # Type of FU issued
794system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.73% # Type of FU issued
795system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.73% # Type of FU issued
796system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.73% # Type of FU issued
797system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.73% # Type of FU issued
798system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.73% # Type of FU issued
799system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.73% # Type of FU issued
800system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.73% # Type of FU issued
801system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.73% # Type of FU issued
802system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.73% # Type of FU issued
803system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.73% # Type of FU issued
804system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.73% # Type of FU issued
805system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.73% # Type of FU issued
806system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.73% # Type of FU issued
807system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.73% # Type of FU issued
808system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.73% # Type of FU issued
809system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.73% # Type of FU issued
810system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.73% # Type of FU issued
811system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.73% # Type of FU issued
812system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.73% # Type of FU issued
813system.cpu.iq.FU_type_0::MemRead 17650951 2.15% 98.88% # Type of FU issued
814system.cpu.iq.FU_type_0::MemWrite 9216716 1.12% 100.00% # Type of FU issued
815system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
816system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
817system.cpu.iq.FU_type_0::total 820786759 # Type of FU issued
818system.cpu.iq.rate 1.808592 # Inst issue rate
819system.cpu.iq.fu_busy_cnt 1051293 # FU busy when requested
820system.cpu.iq.fu_busy_rate 0.001281 # FU busy rate (busy events/executed inst)
821system.cpu.iq.int_inst_queue_reads 1905631270 # Number of integer instruction queue reads
822system.cpu.iq.int_inst_queue_writes 844875947 # Number of integer instruction queue writes
823system.cpu.iq.int_inst_queue_wakeup_accesses 816895262 # Number of integer instruction queue wakeup accesses
824system.cpu.iq.fp_inst_queue_reads 170 # Number of floating instruction queue reads
825system.cpu.iq.fp_inst_queue_writes 180 # Number of floating instruction queue writes
826system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses
827system.cpu.iq.int_alu_accesses 821529545 # Number of integer alu accesses
828system.cpu.iq.fp_alu_accesses 80 # Number of floating point alu accesses
829system.cpu.iew.lsq.thread0.forwLoads 1693324 # Number of loads that had data forwarded from stores
830system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
831system.cpu.iew.lsq.thread0.squashedLoads 2710358 # Number of loads squashed
832system.cpu.iew.lsq.thread0.ignoredResponses 18596 # Number of memory responses ignored because the instruction is squashed
833system.cpu.iew.lsq.thread0.memOrderViolation 11994 # Number of memory ordering violations
834system.cpu.iew.lsq.thread0.squashedStores 1389490 # Number of stores squashed
835system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
836system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
837system.cpu.iew.lsq.thread0.rescheduledLoads 1931520 # Number of loads that were rescheduled
838system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked
839system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
840system.cpu.iew.iewSquashCycles 3030956 # Number of cycles IEW is squashing
841system.cpu.iew.iewBlockCycles 31365465 # Number of cycles IEW is blocking
842system.cpu.iew.iewUnblockCycles 2153394 # Number of cycles IEW is unblocking
843system.cpu.iew.iewDispatchedInsts 825850689 # Number of instructions dispatched to IQ
844system.cpu.iew.iewDispSquashedInsts 245046 # Number of squashed instructions skipped by dispatch
845system.cpu.iew.iewDispLoadInsts 16699186 # Number of dispatched load instructions
846system.cpu.iew.iewDispStoreInsts 9813003 # Number of dispatched store instructions
847system.cpu.iew.iewDispNonSpecInsts 690244 # Number of dispatched non-speculative instructions
848system.cpu.iew.iewIQFullEvents 1620381 # Number of times the IQ has become full, causing a stall
849system.cpu.iew.iewLSQFullEvents 14551 # Number of times the LSQ has become full, causing a stall
850system.cpu.iew.memOrderViolationEvents 11994 # Number of memory order violations
851system.cpu.iew.predictedTakenIncorrect 492991 # Number of branches that were predicted taken incorrectly
852system.cpu.iew.predictedNotTakenIncorrect 506844 # Number of branches that were predicted not taken incorrectly
853system.cpu.iew.branchMispredicts 999835 # Number of branch mispredicts detected at execute
854system.cpu.iew.iewExecutedInsts 819394540 # Number of executed instructions
855system.cpu.iew.iewExecLoadInsts 17351060 # Number of load instructions executed
856system.cpu.iew.iewExecSquashedInsts 1392218 # Number of squashed instructions skipped in execute
857system.cpu.iew.exec_swp 0 # number of swp insts executed
858system.cpu.iew.exec_nop 0 # number of nop insts executed
859system.cpu.iew.exec_refs 26384270 # number of memory reference insts executed
860system.cpu.iew.exec_branches 83073397 # Number of branches executed
861system.cpu.iew.exec_stores 9033210 # Number of stores executed
862system.cpu.iew.exec_rate 1.805525 # Inst execution rate
863system.cpu.iew.wb_sent 818994723 # cumulative count of insts sent to commit
864system.cpu.iew.wb_count 816895310 # cumulative count of insts written-back
865system.cpu.iew.wb_producers 638461899 # num instructions producing a value
866system.cpu.iew.wb_consumers 1043741013 # num instructions consuming a value
867system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
868system.cpu.iew.wb_rate 1.800018 # insts written-back per cycle
869system.cpu.iew.wb_fanout 0.611705 # average fanout of values written-back
870system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
871system.cpu.commit.commitSquashedInsts 19724455 # The number of squashed insts skipped by commit
872system.cpu.commit.commitNonSpecStalls 1054609 # The number of times commit has been forced to stall to communicate backwards
873system.cpu.commit.branchMispredicts 885977 # The number of times a branch was mispredicted
874system.cpu.commit.committed_per_cycle::samples 259718202 # Number of insts commited each cycle
875system.cpu.commit.committed_per_cycle::mean 3.103430 # Number of insts commited each cycle
876system.cpu.commit.committed_per_cycle::stdev 2.863863 # Number of insts commited each cycle
877system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
878system.cpu.commit.committed_per_cycle::0 88192844 33.96% 33.96% # Number of insts commited each cycle
879system.cpu.commit.committed_per_cycle::1 11850002 4.56% 38.52% # Number of insts commited each cycle
880system.cpu.commit.committed_per_cycle::2 3832476 1.48% 40.00% # Number of insts commited each cycle
881system.cpu.commit.committed_per_cycle::3 74743456 28.78% 68.77% # Number of insts commited each cycle
882system.cpu.commit.committed_per_cycle::4 2382743 0.92% 69.69% # Number of insts commited each cycle
883system.cpu.commit.committed_per_cycle::5 1477125 0.57% 70.26% # Number of insts commited each cycle
884system.cpu.commit.committed_per_cycle::6 857323 0.33% 70.59% # Number of insts commited each cycle
885system.cpu.commit.committed_per_cycle::7 70846576 27.28% 97.87% # Number of insts commited each cycle
886system.cpu.commit.committed_per_cycle::8 5535657 2.13% 100.00% # Number of insts commited each cycle
887system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
888system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
889system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
890system.cpu.commit.committed_per_cycle::total 259718202 # Number of insts commited each cycle
891system.cpu.commit.committedInsts 407756178 # Number of instructions committed
892system.cpu.commit.committedOps 806017145 # Number of ops (including micro ops) committed
893system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
894system.cpu.commit.refs 22412340 # Number of memory references committed
895system.cpu.commit.loads 13988827 # Number of loads committed
896system.cpu.commit.membars 474703 # Number of memory barriers committed
897system.cpu.commit.branches 82157257 # Number of branches committed
898system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
899system.cpu.commit.int_insts 735004802 # Number of committed integer instructions.
900system.cpu.commit.function_calls 1155200 # Number of function calls committed.
901system.cpu.commit.bw_lim_events 5535657 # number cycles where commit BW limit reached
902system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
903system.cpu.rob.rob_reads 1079845864 # The number of ROB reads
904system.cpu.rob.rob_writes 1654528920 # The number of ROB writes
905system.cpu.timesIdled 1259880 # Number of times that the entire CPU went into an idle state and unscheduled itself
906system.cpu.idleCycles 191077145 # Total number of cycles that the CPU has spent unscheduled due to idling
907system.cpu.quiesceCycles 9813814465 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
908system.cpu.committedInsts 407756178 # Number of Instructions Simulated
909system.cpu.committedOps 806017145 # Number of Ops (including micro ops) Simulated
910system.cpu.committedInsts_total 407756178 # Number of Instructions Simulated
911system.cpu.cpi 1.112984 # CPI: Cycles Per Instruction
912system.cpu.cpi_total 1.112984 # CPI: Total CPI of All Threads
913system.cpu.ipc 0.898485 # IPC: Instructions Per Cycle
914system.cpu.ipc_total 0.898485 # IPC: Total IPC of All Threads
915system.cpu.int_regfile_reads 1504160790 # number of integer regfile reads
916system.cpu.int_regfile_writes 975149499 # number of integer regfile writes
917system.cpu.fp_regfile_reads 48 # number of floating regfile reads
918system.cpu.misc_regfile_reads 263996873 # number of misc regfile reads
919system.cpu.misc_regfile_writes 402343 # number of misc regfile writes
920system.cpu.toL2Bus.throughput 53588361 # Throughput (bytes/s)
921system.cpu.toL2Bus.trans_dist::ReadReq 3012770 # Transaction distribution
922system.cpu.toL2Bus.trans_dist::ReadResp 3012220 # Transaction distribution
923system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution
924system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution
925system.cpu.toL2Bus.trans_dist::Writeback 1579976 # Transaction distribution
926system.cpu.toL2Bus.trans_dist::UpgradeReq 2276 # Transaction distribution
927system.cpu.toL2Bus.trans_dist::UpgradeResp 2276 # Transaction distribution
928system.cpu.toL2Bus.trans_dist::ReadExReq 334451 # Transaction distribution
929system.cpu.toL2Bus.trans_dist::ReadExResp 287744 # Transaction distribution
930system.cpu.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution
931system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1911499 # Packet count per connected master and slave (bytes)
932system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6119032 # Packet count per connected master and slave (bytes)
933system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17478 # Packet count per connected master and slave (bytes)
934system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 153515 # Packet count per connected master and slave (bytes)
935system.cpu.toL2Bus.pkt_count::total 8201524 # Packet count per connected master and slave (bytes)
936system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61164352 # Cumulative packet size per connected master and slave (bytes)
937system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207421989 # Cumulative packet size per connected master and slave (bytes)
938system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 548096 # Cumulative packet size per connected master and slave (bytes)
939system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5363392 # Cumulative packet size per connected master and slave (bytes)
940system.cpu.toL2Bus.tot_pkt_size::total 274497829 # Cumulative packet size per connected master and slave (bytes)
941system.cpu.toL2Bus.data_through_bus 274473317 # Total data (bytes)
942system.cpu.toL2Bus.snoop_data_through_bus 639552 # Total snoop data (bytes)
943system.cpu.toL2Bus.reqLayer0.occupancy 4034739870 # Layer occupancy (ticks)
944system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
945system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks)
946system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
947system.cpu.toL2Bus.respLayer0.occupancy 1437663197 # Layer occupancy (ticks)
948system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
949system.cpu.toL2Bus.respLayer1.occupancy 3140492264 # Layer occupancy (ticks)
950system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
951system.cpu.toL2Bus.respLayer2.occupancy 13374496 # Layer occupancy (ticks)
952system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
953system.cpu.toL2Bus.respLayer3.occupancy 104626155 # Layer occupancy (ticks)
954system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
955system.cpu.icache.tags.replacements 955225 # number of replacements
956system.cpu.icache.tags.tagsinuse 509.955368 # Cycle average of tags in use
957system.cpu.icache.tags.total_refs 7446917 # Total number of references to valid blocks.
958system.cpu.icache.tags.sampled_refs 955737 # Sample count of references to valid blocks.
959system.cpu.icache.tags.avg_refs 7.791806 # Average number of references to valid blocks.
960system.cpu.icache.tags.warmup_cycle 147479365250 # Cycle when the warmup percentage was hit.
961system.cpu.icache.tags.occ_blocks::cpu.inst 509.955368 # Average occupied blocks per requestor
962system.cpu.icache.tags.occ_percent::cpu.inst 0.996007 # Average percentage of cache occupancy
963system.cpu.icache.tags.occ_percent::total 0.996007 # Average percentage of cache occupancy
964system.cpu.icache.ReadReq_hits::cpu.inst 7446917 # number of ReadReq hits
965system.cpu.icache.ReadReq_hits::total 7446917 # number of ReadReq hits
966system.cpu.icache.demand_hits::cpu.inst 7446917 # number of demand (read+write) hits
967system.cpu.icache.demand_hits::total 7446917 # number of demand (read+write) hits
968system.cpu.icache.overall_hits::cpu.inst 7446917 # number of overall hits
969system.cpu.icache.overall_hits::total 7446917 # number of overall hits
970system.cpu.icache.ReadReq_misses::cpu.inst 1009251 # number of ReadReq misses
971system.cpu.icache.ReadReq_misses::total 1009251 # number of ReadReq misses
972system.cpu.icache.demand_misses::cpu.inst 1009251 # number of demand (read+write) misses
973system.cpu.icache.demand_misses::total 1009251 # number of demand (read+write) misses
974system.cpu.icache.overall_misses::cpu.inst 1009251 # number of overall misses
975system.cpu.icache.overall_misses::total 1009251 # number of overall misses
976system.cpu.icache.ReadReq_miss_latency::cpu.inst 14258935392 # number of ReadReq miss cycles
977system.cpu.icache.ReadReq_miss_latency::total 14258935392 # number of ReadReq miss cycles
978system.cpu.icache.demand_miss_latency::cpu.inst 14258935392 # number of demand (read+write) miss cycles
979system.cpu.icache.demand_miss_latency::total 14258935392 # number of demand (read+write) miss cycles
980system.cpu.icache.overall_miss_latency::cpu.inst 14258935392 # number of overall miss cycles
981system.cpu.icache.overall_miss_latency::total 14258935392 # number of overall miss cycles
982system.cpu.icache.ReadReq_accesses::cpu.inst 8456168 # number of ReadReq accesses(hits+misses)
983system.cpu.icache.ReadReq_accesses::total 8456168 # number of ReadReq accesses(hits+misses)
984system.cpu.icache.demand_accesses::cpu.inst 8456168 # number of demand (read+write) accesses
985system.cpu.icache.demand_accesses::total 8456168 # number of demand (read+write) accesses
986system.cpu.icache.overall_accesses::cpu.inst 8456168 # number of overall (read+write) accesses
987system.cpu.icache.overall_accesses::total 8456168 # number of overall (read+write) accesses
988system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119351 # miss rate for ReadReq accesses
989system.cpu.icache.ReadReq_miss_rate::total 0.119351 # miss rate for ReadReq accesses
990system.cpu.icache.demand_miss_rate::cpu.inst 0.119351 # miss rate for demand accesses
991system.cpu.icache.demand_miss_rate::total 0.119351 # miss rate for demand accesses
992system.cpu.icache.overall_miss_rate::cpu.inst 0.119351 # miss rate for overall accesses
993system.cpu.icache.overall_miss_rate::total 0.119351 # miss rate for overall accesses
994system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14128.235089 # average ReadReq miss latency
995system.cpu.icache.ReadReq_avg_miss_latency::total 14128.235089 # average ReadReq miss latency
996system.cpu.icache.demand_avg_miss_latency::cpu.inst 14128.235089 # average overall miss latency
997system.cpu.icache.demand_avg_miss_latency::total 14128.235089 # average overall miss latency
998system.cpu.icache.overall_avg_miss_latency::cpu.inst 14128.235089 # average overall miss latency
999system.cpu.icache.overall_avg_miss_latency::total 14128.235089 # average overall miss latency
1000system.cpu.icache.blocked_cycles::no_mshrs 6628 # number of cycles access was blocked
1001system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1002system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked
1003system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1004system.cpu.icache.avg_blocked_cycles::no_mshrs 28.943231 # average number of cycles each access was blocked
1005system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1006system.cpu.icache.fast_writes 0 # number of fast writes performed
1007system.cpu.icache.cache_copies 0 # number of cache copies performed
1008system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53445 # number of ReadReq MSHR hits
1009system.cpu.icache.ReadReq_mshr_hits::total 53445 # number of ReadReq MSHR hits
1010system.cpu.icache.demand_mshr_hits::cpu.inst 53445 # number of demand (read+write) MSHR hits
1011system.cpu.icache.demand_mshr_hits::total 53445 # number of demand (read+write) MSHR hits
1012system.cpu.icache.overall_mshr_hits::cpu.inst 53445 # number of overall MSHR hits
1013system.cpu.icache.overall_mshr_hits::total 53445 # number of overall MSHR hits
1014system.cpu.icache.ReadReq_mshr_misses::cpu.inst 955806 # number of ReadReq MSHR misses
1015system.cpu.icache.ReadReq_mshr_misses::total 955806 # number of ReadReq MSHR misses
1016system.cpu.icache.demand_mshr_misses::cpu.inst 955806 # number of demand (read+write) MSHR misses
1017system.cpu.icache.demand_mshr_misses::total 955806 # number of demand (read+write) MSHR misses
1018system.cpu.icache.overall_mshr_misses::cpu.inst 955806 # number of overall MSHR misses
1019system.cpu.icache.overall_mshr_misses::total 955806 # number of overall MSHR misses
1020system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11762227547 # number of ReadReq MSHR miss cycles
1021system.cpu.icache.ReadReq_mshr_miss_latency::total 11762227547 # number of ReadReq MSHR miss cycles
1022system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11762227547 # number of demand (read+write) MSHR miss cycles
1023system.cpu.icache.demand_mshr_miss_latency::total 11762227547 # number of demand (read+write) MSHR miss cycles
1024system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11762227547 # number of overall MSHR miss cycles
1025system.cpu.icache.overall_mshr_miss_latency::total 11762227547 # number of overall MSHR miss cycles
1026system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for ReadReq accesses
1027system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113031 # mshr miss rate for ReadReq accesses
1028system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for demand accesses
1029system.cpu.icache.demand_mshr_miss_rate::total 0.113031 # mshr miss rate for demand accesses
1030system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for overall accesses
1031system.cpu.icache.overall_mshr_miss_rate::total 0.113031 # mshr miss rate for overall accesses
1032system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12306.082560 # average ReadReq mshr miss latency
1033system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12306.082560 # average ReadReq mshr miss latency
1034system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12306.082560 # average overall mshr miss latency
1035system.cpu.icache.demand_avg_mshr_miss_latency::total 12306.082560 # average overall mshr miss latency
1036system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12306.082560 # average overall mshr miss latency
1037system.cpu.icache.overall_avg_mshr_miss_latency::total 12306.082560 # average overall mshr miss latency
1038system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1039system.cpu.itb_walker_cache.tags.replacements 8028 # number of replacements
1040system.cpu.itb_walker_cache.tags.tagsinuse 6.311146 # Cycle average of tags in use
1041system.cpu.itb_walker_cache.tags.total_refs 21788 # Total number of references to valid blocks.
1042system.cpu.itb_walker_cache.tags.sampled_refs 8039 # Sample count of references to valid blocks.
1043system.cpu.itb_walker_cache.tags.avg_refs 2.710287 # Average number of references to valid blocks.
1044system.cpu.itb_walker_cache.tags.warmup_cycle 5106556199500 # Cycle when the warmup percentage was hit.
1045system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.311146 # Average occupied blocks per requestor
1046system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.394447 # Average percentage of cache occupancy
1047system.cpu.itb_walker_cache.tags.occ_percent::total 0.394447 # Average percentage of cache occupancy
1048system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21802 # number of ReadReq hits
1049system.cpu.itb_walker_cache.ReadReq_hits::total 21802 # number of ReadReq hits
1050system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
1051system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
1052system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21804 # number of demand (read+write) hits
1053system.cpu.itb_walker_cache.demand_hits::total 21804 # number of demand (read+write) hits
1054system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21804 # number of overall hits
1055system.cpu.itb_walker_cache.overall_hits::total 21804 # number of overall hits
1056system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8914 # number of ReadReq misses
1057system.cpu.itb_walker_cache.ReadReq_misses::total 8914 # number of ReadReq misses
1058system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8914 # number of demand (read+write) misses
1059system.cpu.itb_walker_cache.demand_misses::total 8914 # number of demand (read+write) misses
1060system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8914 # number of overall misses
1061system.cpu.itb_walker_cache.overall_misses::total 8914 # number of overall misses
1062system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 98082749 # number of ReadReq miss cycles
1063system.cpu.itb_walker_cache.ReadReq_miss_latency::total 98082749 # number of ReadReq miss cycles
1064system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 98082749 # number of demand (read+write) miss cycles
1065system.cpu.itb_walker_cache.demand_miss_latency::total 98082749 # number of demand (read+write) miss cycles
1066system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 98082749 # number of overall miss cycles
1067system.cpu.itb_walker_cache.overall_miss_latency::total 98082749 # number of overall miss cycles
1068system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30716 # number of ReadReq accesses(hits+misses)
1069system.cpu.itb_walker_cache.ReadReq_accesses::total 30716 # number of ReadReq accesses(hits+misses)
1070system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1071system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1072system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30718 # number of demand (read+write) accesses
1073system.cpu.itb_walker_cache.demand_accesses::total 30718 # number of demand (read+write) accesses
1074system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30718 # number of overall (read+write) accesses
1075system.cpu.itb_walker_cache.overall_accesses::total 30718 # number of overall (read+write) accesses
1076system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.290207 # miss rate for ReadReq accesses
1077system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.290207 # miss rate for ReadReq accesses
1078system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.290188 # miss rate for demand accesses
1079system.cpu.itb_walker_cache.demand_miss_rate::total 0.290188 # miss rate for demand accesses
1080system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.290188 # miss rate for overall accesses
1081system.cpu.itb_walker_cache.overall_miss_rate::total 0.290188 # miss rate for overall accesses
1082system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11003.225151 # average ReadReq miss latency
1083system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11003.225151 # average ReadReq miss latency
1084system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11003.225151 # average overall miss latency
1085system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11003.225151 # average overall miss latency
1086system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11003.225151 # average overall miss latency
1087system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11003.225151 # average overall miss latency
1088system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1089system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1090system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1091system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1092system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1093system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1094system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1095system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1096system.cpu.itb_walker_cache.writebacks::writebacks 1772 # number of writebacks
1097system.cpu.itb_walker_cache.writebacks::total 1772 # number of writebacks
1098system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8914 # number of ReadReq MSHR misses
1099system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses
1100system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8914 # number of demand (read+write) MSHR misses
1101system.cpu.itb_walker_cache.demand_mshr_misses::total 8914 # number of demand (read+write) MSHR misses
1102system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8914 # number of overall MSHR misses
1103system.cpu.itb_walker_cache.overall_mshr_misses::total 8914 # number of overall MSHR misses
1104system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80247757 # number of ReadReq MSHR miss cycles
1105system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 80247757 # number of ReadReq MSHR miss cycles
1106system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 80247757 # number of demand (read+write) MSHR miss cycles
1107system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 80247757 # number of demand (read+write) MSHR miss cycles
1108system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 80247757 # number of overall MSHR miss cycles
1109system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 80247757 # number of overall MSHR miss cycles
1110system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.290207 # mshr miss rate for ReadReq accesses
1111system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.290207 # mshr miss rate for ReadReq accesses
1112system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.290188 # mshr miss rate for demand accesses
1113system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.290188 # mshr miss rate for demand accesses
1114system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.290188 # mshr miss rate for overall accesses
1115system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.290188 # mshr miss rate for overall accesses
1116system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average ReadReq mshr miss latency
1117system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9002.440767 # average ReadReq mshr miss latency
1118system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average overall mshr miss latency
1119system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9002.440767 # average overall mshr miss latency
1120system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average overall mshr miss latency
1121system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9002.440767 # average overall mshr miss latency
1122system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1123system.cpu.dtb_walker_cache.tags.replacements 68638 # number of replacements
1124system.cpu.dtb_walker_cache.tags.tagsinuse 13.809611 # Cycle average of tags in use
1125system.cpu.dtb_walker_cache.tags.total_refs 91506 # Total number of references to valid blocks.
1126system.cpu.dtb_walker_cache.tags.sampled_refs 68653 # Sample count of references to valid blocks.
1127system.cpu.dtb_walker_cache.tags.avg_refs 1.332877 # Average number of references to valid blocks.
1128system.cpu.dtb_walker_cache.tags.warmup_cycle 5104119753500 # Cycle when the warmup percentage was hit.
1129system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.809611 # Average occupied blocks per requestor
1130system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.863101 # Average percentage of cache occupancy
1131system.cpu.dtb_walker_cache.tags.occ_percent::total 0.863101 # Average percentage of cache occupancy
1132system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91510 # number of ReadReq hits
1133system.cpu.dtb_walker_cache.ReadReq_hits::total 91510 # number of ReadReq hits
1134system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91510 # number of demand (read+write) hits
1135system.cpu.dtb_walker_cache.demand_hits::total 91510 # number of demand (read+write) hits
1136system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91510 # number of overall hits
1137system.cpu.dtb_walker_cache.overall_hits::total 91510 # number of overall hits
1138system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69712 # number of ReadReq misses
1139system.cpu.dtb_walker_cache.ReadReq_misses::total 69712 # number of ReadReq misses
1140system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69712 # number of demand (read+write) misses
1141system.cpu.dtb_walker_cache.demand_misses::total 69712 # number of demand (read+write) misses
1142system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69712 # number of overall misses
1143system.cpu.dtb_walker_cache.overall_misses::total 69712 # number of overall misses
1144system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854471475 # number of ReadReq miss cycles
1145system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854471475 # number of ReadReq miss cycles
1146system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854471475 # number of demand (read+write) miss cycles
1147system.cpu.dtb_walker_cache.demand_miss_latency::total 854471475 # number of demand (read+write) miss cycles
1148system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854471475 # number of overall miss cycles
1149system.cpu.dtb_walker_cache.overall_miss_latency::total 854471475 # number of overall miss cycles
1150system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161222 # number of ReadReq accesses(hits+misses)
1151system.cpu.dtb_walker_cache.ReadReq_accesses::total 161222 # number of ReadReq accesses(hits+misses)
1152system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161222 # number of demand (read+write) accesses
1153system.cpu.dtb_walker_cache.demand_accesses::total 161222 # number of demand (read+write) accesses
1154system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161222 # number of overall (read+write) accesses
1155system.cpu.dtb_walker_cache.overall_accesses::total 161222 # number of overall (read+write) accesses
1156system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.432398 # miss rate for ReadReq accesses
1157system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.432398 # miss rate for ReadReq accesses
1158system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.432398 # miss rate for demand accesses
1159system.cpu.dtb_walker_cache.demand_miss_rate::total 0.432398 # miss rate for demand accesses
1160system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.432398 # miss rate for overall accesses
1161system.cpu.dtb_walker_cache.overall_miss_rate::total 0.432398 # miss rate for overall accesses
1162system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12257.164835 # average ReadReq miss latency
1163system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12257.164835 # average ReadReq miss latency
1164system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12257.164835 # average overall miss latency
1165system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12257.164835 # average overall miss latency
1166system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12257.164835 # average overall miss latency
1167system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12257.164835 # average overall miss latency
1168system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1169system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1170system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1171system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1172system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1173system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1174system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
1175system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
1176system.cpu.dtb_walker_cache.writebacks::writebacks 20719 # number of writebacks
1177system.cpu.dtb_walker_cache.writebacks::total 20719 # number of writebacks
1178system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69712 # number of ReadReq MSHR misses
1179system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69712 # number of ReadReq MSHR misses
1180system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69712 # number of demand (read+write) MSHR misses
1181system.cpu.dtb_walker_cache.demand_mshr_misses::total 69712 # number of demand (read+write) MSHR misses
1182system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69712 # number of overall MSHR misses
1183system.cpu.dtb_walker_cache.overall_mshr_misses::total 69712 # number of overall MSHR misses
1184system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 714931165 # number of ReadReq MSHR miss cycles
1185system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 714931165 # number of ReadReq MSHR miss cycles
1186system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 714931165 # number of demand (read+write) MSHR miss cycles
1187system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 714931165 # number of demand (read+write) MSHR miss cycles
1188system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 714931165 # number of overall MSHR miss cycles
1189system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 714931165 # number of overall MSHR miss cycles
1190system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for ReadReq accesses
1191system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.432398 # mshr miss rate for ReadReq accesses
1192system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for demand accesses
1193system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.432398 # mshr miss rate for demand accesses
1194system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for overall accesses
1195system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.432398 # mshr miss rate for overall accesses
1196system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average ReadReq mshr miss latency
1197system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10255.496399 # average ReadReq mshr miss latency
1198system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average overall mshr miss latency
1199system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10255.496399 # average overall mshr miss latency
1200system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average overall mshr miss latency
1201system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10255.496399 # average overall mshr miss latency
1202system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1203system.cpu.dcache.tags.replacements 1655321 # number of replacements
1204system.cpu.dcache.tags.tagsinuse 511.993756 # Cycle average of tags in use
1205system.cpu.dcache.tags.total_refs 18976383 # Total number of references to valid blocks.
1206system.cpu.dcache.tags.sampled_refs 1655833 # Sample count of references to valid blocks.
1207system.cpu.dcache.tags.avg_refs 11.460324 # Average number of references to valid blocks.
1208system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit.
1209system.cpu.dcache.tags.occ_blocks::cpu.data 511.993756 # Average occupied blocks per requestor
1210system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy
1211system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy
1212system.cpu.dcache.ReadReq_hits::cpu.data 10875506 # number of ReadReq hits
1213system.cpu.dcache.ReadReq_hits::total 10875506 # number of ReadReq hits
1214system.cpu.dcache.WriteReq_hits::cpu.data 8098167 # number of WriteReq hits
1215system.cpu.dcache.WriteReq_hits::total 8098167 # number of WriteReq hits
1216system.cpu.dcache.demand_hits::cpu.data 18973673 # number of demand (read+write) hits
1217system.cpu.dcache.demand_hits::total 18973673 # number of demand (read+write) hits
1218system.cpu.dcache.overall_hits::cpu.data 18973673 # number of overall hits
1219system.cpu.dcache.overall_hits::total 18973673 # number of overall hits
1220system.cpu.dcache.ReadReq_misses::cpu.data 2232931 # number of ReadReq misses
1221system.cpu.dcache.ReadReq_misses::total 2232931 # number of ReadReq misses
1222system.cpu.dcache.WriteReq_misses::cpu.data 315791 # number of WriteReq misses
1223system.cpu.dcache.WriteReq_misses::total 315791 # number of WriteReq misses
1224system.cpu.dcache.demand_misses::cpu.data 2548722 # number of demand (read+write) misses
1225system.cpu.dcache.demand_misses::total 2548722 # number of demand (read+write) misses
1226system.cpu.dcache.overall_misses::cpu.data 2548722 # number of overall misses
1227system.cpu.dcache.overall_misses::total 2548722 # number of overall misses
1228system.cpu.dcache.ReadReq_miss_latency::cpu.data 33105603008 # number of ReadReq miss cycles
1229system.cpu.dcache.ReadReq_miss_latency::total 33105603008 # number of ReadReq miss cycles
1230system.cpu.dcache.WriteReq_miss_latency::cpu.data 12178134710 # number of WriteReq miss cycles
1231system.cpu.dcache.WriteReq_miss_latency::total 12178134710 # number of WriteReq miss cycles
1232system.cpu.dcache.demand_miss_latency::cpu.data 45283737718 # number of demand (read+write) miss cycles
1233system.cpu.dcache.demand_miss_latency::total 45283737718 # number of demand (read+write) miss cycles
1234system.cpu.dcache.overall_miss_latency::cpu.data 45283737718 # number of overall miss cycles
1235system.cpu.dcache.overall_miss_latency::total 45283737718 # number of overall miss cycles
1236system.cpu.dcache.ReadReq_accesses::cpu.data 13108437 # number of ReadReq accesses(hits+misses)
1237system.cpu.dcache.ReadReq_accesses::total 13108437 # number of ReadReq accesses(hits+misses)
1238system.cpu.dcache.WriteReq_accesses::cpu.data 8413958 # number of WriteReq accesses(hits+misses)
1239system.cpu.dcache.WriteReq_accesses::total 8413958 # number of WriteReq accesses(hits+misses)
1240system.cpu.dcache.demand_accesses::cpu.data 21522395 # number of demand (read+write) accesses
1241system.cpu.dcache.demand_accesses::total 21522395 # number of demand (read+write) accesses
1242system.cpu.dcache.overall_accesses::cpu.data 21522395 # number of overall (read+write) accesses
1243system.cpu.dcache.overall_accesses::total 21522395 # number of overall (read+write) accesses
1244system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170343 # miss rate for ReadReq accesses
1245system.cpu.dcache.ReadReq_miss_rate::total 0.170343 # miss rate for ReadReq accesses
1246system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037532 # miss rate for WriteReq accesses
1247system.cpu.dcache.WriteReq_miss_rate::total 0.037532 # miss rate for WriteReq accesses
1248system.cpu.dcache.demand_miss_rate::cpu.data 0.118422 # miss rate for demand accesses
1249system.cpu.dcache.demand_miss_rate::total 0.118422 # miss rate for demand accesses
1250system.cpu.dcache.overall_miss_rate::cpu.data 0.118422 # miss rate for overall accesses
1251system.cpu.dcache.overall_miss_rate::total 0.118422 # miss rate for overall accesses
1252system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14826.075238 # average ReadReq miss latency
1253system.cpu.dcache.ReadReq_avg_miss_latency::total 14826.075238 # average ReadReq miss latency
1254system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38563.906856 # average WriteReq miss latency
1255system.cpu.dcache.WriteReq_avg_miss_latency::total 38563.906856 # average WriteReq miss latency
1256system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.233036 # average overall miss latency
1257system.cpu.dcache.demand_avg_miss_latency::total 17767.233036 # average overall miss latency
1258system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.233036 # average overall miss latency
1259system.cpu.dcache.overall_avg_miss_latency::total 17767.233036 # average overall miss latency
1260system.cpu.dcache.blocked_cycles::no_mshrs 397899 # number of cycles access was blocked
1261system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1262system.cpu.dcache.blocked::no_mshrs 42056 # number of cycles access was blocked
1263system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1264system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.461171 # average number of cycles each access was blocked
1265system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1266system.cpu.dcache.fast_writes 0 # number of fast writes performed
1267system.cpu.dcache.cache_copies 0 # number of cache copies performed
1268system.cpu.dcache.writebacks::writebacks 1557485 # number of writebacks
1269system.cpu.dcache.writebacks::total 1557485 # number of writebacks
1270system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864709 # number of ReadReq MSHR hits
1271system.cpu.dcache.ReadReq_mshr_hits::total 864709 # number of ReadReq MSHR hits
1272system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25884 # number of WriteReq MSHR hits
1273system.cpu.dcache.WriteReq_mshr_hits::total 25884 # number of WriteReq MSHR hits
1274system.cpu.dcache.demand_mshr_hits::cpu.data 890593 # number of demand (read+write) MSHR hits
1275system.cpu.dcache.demand_mshr_hits::total 890593 # number of demand (read+write) MSHR hits
1276system.cpu.dcache.overall_mshr_hits::cpu.data 890593 # number of overall MSHR hits
1277system.cpu.dcache.overall_mshr_hits::total 890593 # number of overall MSHR hits
1278system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1368222 # number of ReadReq MSHR misses
1279system.cpu.dcache.ReadReq_mshr_misses::total 1368222 # number of ReadReq MSHR misses
1280system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289907 # number of WriteReq MSHR misses
1281system.cpu.dcache.WriteReq_mshr_misses::total 289907 # number of WriteReq MSHR misses
1282system.cpu.dcache.demand_mshr_misses::cpu.data 1658129 # number of demand (read+write) MSHR misses
1283system.cpu.dcache.demand_mshr_misses::total 1658129 # number of demand (read+write) MSHR misses
1284system.cpu.dcache.overall_mshr_misses::cpu.data 1658129 # number of overall MSHR misses
1285system.cpu.dcache.overall_mshr_misses::total 1658129 # number of overall MSHR misses
1286system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17890826726 # number of ReadReq MSHR miss cycles
1287system.cpu.dcache.ReadReq_mshr_miss_latency::total 17890826726 # number of ReadReq MSHR miss cycles
1288system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11280486479 # number of WriteReq MSHR miss cycles
1289system.cpu.dcache.WriteReq_mshr_miss_latency::total 11280486479 # number of WriteReq MSHR miss cycles
1290system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29171313205 # number of demand (read+write) MSHR miss cycles
1291system.cpu.dcache.demand_mshr_miss_latency::total 29171313205 # number of demand (read+write) MSHR miss cycles
1292system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29171313205 # number of overall MSHR miss cycles
1293system.cpu.dcache.overall_mshr_miss_latency::total 29171313205 # number of overall MSHR miss cycles
1294system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364618000 # number of ReadReq MSHR uncacheable cycles
1295system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364618000 # number of ReadReq MSHR uncacheable cycles
1296system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538596500 # number of WriteReq MSHR uncacheable cycles
1297system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538596500 # number of WriteReq MSHR uncacheable cycles
1298system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903214500 # number of overall MSHR uncacheable cycles
1299system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903214500 # number of overall MSHR uncacheable cycles
1300system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses
1301system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses
1302system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034455 # mshr miss rate for WriteReq accesses
1303system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034455 # mshr miss rate for WriteReq accesses
1304system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077042 # mshr miss rate for demand accesses
1305system.cpu.dcache.demand_mshr_miss_rate::total 0.077042 # mshr miss rate for demand accesses
1306system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077042 # mshr miss rate for overall accesses
1307system.cpu.dcache.overall_mshr_miss_rate::total 0.077042 # mshr miss rate for overall accesses
1308system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13075.967735 # average ReadReq mshr miss latency
1309system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13075.967735 # average ReadReq mshr miss latency
1310system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38910.707499 # average WriteReq mshr miss latency
1311system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38910.707499 # average WriteReq mshr miss latency
1312system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17592.909360 # average overall mshr miss latency
1313system.cpu.dcache.demand_avg_mshr_miss_latency::total 17592.909360 # average overall mshr miss latency
1314system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17592.909360 # average overall mshr miss latency
1315system.cpu.dcache.overall_avg_mshr_miss_latency::total 17592.909360 # average overall mshr miss latency
1316system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1317system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1318system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1319system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1320system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1321system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1322system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1323system.cpu.l2cache.tags.replacements 111515 # number of replacements
1324system.cpu.l2cache.tags.tagsinuse 64833.541766 # Cycle average of tags in use
1325system.cpu.l2cache.tags.total_refs 3779668 # Total number of references to valid blocks.
1326system.cpu.l2cache.tags.sampled_refs 175596 # Sample count of references to valid blocks.
1327system.cpu.l2cache.tags.avg_refs 21.524796 # Average number of references to valid blocks.
1328system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1329system.cpu.l2cache.tags.occ_blocks::writebacks 50736.164769 # Average occupied blocks per requestor
1330system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.333778 # Average occupied blocks per requestor
1331system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.436924 # Average occupied blocks per requestor
1332system.cpu.l2cache.tags.occ_blocks::cpu.inst 3104.326837 # Average occupied blocks per requestor
1333system.cpu.l2cache.tags.occ_blocks::cpu.data 10979.279458 # Average occupied blocks per requestor
1334system.cpu.l2cache.tags.occ_percent::writebacks 0.774172 # Average percentage of cache occupancy
1335system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000203 # Average percentage of cache occupancy
1336system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy
1337system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047368 # Average percentage of cache occupancy
1338system.cpu.l2cache.tags.occ_percent::cpu.data 0.167531 # Average percentage of cache occupancy
1339system.cpu.l2cache.tags.occ_percent::total 0.989281 # Average percentage of cache occupancy
1340system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63026 # number of ReadReq hits
1341system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6786 # number of ReadReq hits
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1344system.cpu.l2cache.ReadReq_hits::total 2341025 # number of ReadReq hits
1345system.cpu.l2cache.Writeback_hits::writebacks 1579976 # number of Writeback hits
1346system.cpu.l2cache.Writeback_hits::total 1579976 # number of Writeback hits
1347system.cpu.l2cache.UpgradeReq_hits::cpu.data 330 # number of UpgradeReq hits
1348system.cpu.l2cache.UpgradeReq_hits::total 330 # number of UpgradeReq hits
1349system.cpu.l2cache.ReadExReq_hits::cpu.data 154233 # number of ReadExReq hits
1350system.cpu.l2cache.ReadExReq_hits::total 154233 # number of ReadExReq hits
1351system.cpu.l2cache.demand_hits::cpu.dtb.walker 63026 # number of demand (read+write) hits
1352system.cpu.l2cache.demand_hits::cpu.itb.walker 6786 # number of demand (read+write) hits
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1361system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 58 # number of ReadReq misses
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1367system.cpu.l2cache.UpgradeReq_misses::total 1441 # number of UpgradeReq misses
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1385system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17718298 # number of UpgradeReq miss cycles
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1394system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6074750 # number of overall miss cycles
1395system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 507000 # number of overall miss cycles
1396system.cpu.l2cache.overall_miss_latency::cpu.inst 1388421484 # number of overall miss cycles
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1403system.cpu.l2cache.ReadReq_accesses::total 2392952 # number of ReadReq accesses(hits+misses)
1404system.cpu.l2cache.Writeback_accesses::writebacks 1579976 # number of Writeback accesses(hits+misses)
1405system.cpu.l2cache.Writeback_accesses::total 1579976 # number of Writeback accesses(hits+misses)
1406system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1771 # number of UpgradeReq accesses(hits+misses)
1407system.cpu.l2cache.UpgradeReq_accesses::total 1771 # number of UpgradeReq accesses(hits+misses)
1408system.cpu.l2cache.ReadExReq_accesses::cpu.data 287723 # number of ReadExReq accesses(hits+misses)
1409system.cpu.l2cache.ReadExReq_accesses::total 287723 # number of ReadExReq accesses(hits+misses)
1410system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63084 # number of demand (read+write) accesses
1411system.cpu.l2cache.demand_accesses::cpu.itb.walker 6792 # number of demand (read+write) accesses
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1414system.cpu.l2cache.demand_accesses::total 2680675 # number of demand (read+write) accesses
1415system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63084 # number of overall (read+write) accesses
1416system.cpu.l2cache.overall_accesses::cpu.itb.walker 6792 # number of overall (read+write) accesses
1417system.cpu.l2cache.overall_accesses::cpu.inst 955693 # number of overall (read+write) accesses
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1419system.cpu.l2cache.overall_accesses::total 2680675 # number of overall (read+write) accesses
1420system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000919 # miss rate for ReadReq accesses
1421system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000883 # miss rate for ReadReq accesses
1422system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016802 # miss rate for ReadReq accesses
1423system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026185 # miss rate for ReadReq accesses
1424system.cpu.l2cache.ReadReq_miss_rate::total 0.021700 # miss rate for ReadReq accesses
1425system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.813665 # miss rate for UpgradeReq accesses
1426system.cpu.l2cache.UpgradeReq_miss_rate::total 0.813665 # miss rate for UpgradeReq accesses
1427system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463953 # miss rate for ReadExReq accesses
1428system.cpu.l2cache.ReadExReq_miss_rate::total 0.463953 # miss rate for ReadExReq accesses
1429system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000919 # miss rate for demand accesses
1430system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000883 # miss rate for demand accesses
1431system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016802 # miss rate for demand accesses
1432system.cpu.l2cache.demand_miss_rate::cpu.data 0.102287 # miss rate for demand accesses
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1434system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000919 # miss rate for overall accesses
1435system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000883 # miss rate for overall accesses
1436system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016802 # miss rate for overall accesses
1437system.cpu.l2cache.overall_miss_rate::cpu.data 0.102287 # miss rate for overall accesses
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1439system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 104737.068966 # average ReadReq miss latency
1440system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84500 # average ReadReq miss latency
1441system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86462.914684 # average ReadReq miss latency
1442system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84121.692920 # average ReadReq miss latency
1443system.cpu.l2cache.ReadReq_avg_miss_latency::total 84868.766711 # average ReadReq miss latency
1444system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12295.834837 # average UpgradeReq miss latency
1445system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12295.834837 # average UpgradeReq miss latency
1446system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70443.935254 # average ReadExReq miss latency
1447system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70443.935254 # average ReadExReq miss latency
1448system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 104737.068966 # average overall miss latency
1449system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84500 # average overall miss latency
1450system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86462.914684 # average overall miss latency
1451system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73336.708893 # average overall miss latency
1452system.cpu.l2cache.demand_avg_miss_latency::total 74483.684700 # average overall miss latency
1453system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 104737.068966 # average overall miss latency
1454system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84500 # average overall miss latency
1455system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86462.914684 # average overall miss latency
1456system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73336.708893 # average overall miss latency
1457system.cpu.l2cache.overall_avg_miss_latency::total 74483.684700 # average overall miss latency
1458system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1459system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1460system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1461system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1462system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1463system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1464system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1465system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1466system.cpu.l2cache.writebacks::writebacks 102141 # number of writebacks
1467system.cpu.l2cache.writebacks::total 102141 # number of writebacks
1468system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
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1471system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
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1474system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
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1511system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles
1512system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1185393516 # number of overall MSHR miss cycles
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1516system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251391500 # number of ReadReq MSHR uncacheable cycles
1517system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372712000 # number of WriteReq MSHR uncacheable cycles
1518system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372712000 # number of WriteReq MSHR uncacheable cycles
1519system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624103500 # number of overall MSHR uncacheable cycles
1520system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624103500 # number of overall MSHR uncacheable cycles
1521system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for ReadReq accesses
1522system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for ReadReq accesses
1523system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for ReadReq accesses
1524system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026184 # mshr miss rate for ReadReq accesses
1525system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021697 # mshr miss rate for ReadReq accesses
1526system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.813665 # mshr miss rate for UpgradeReq accesses
1527system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.813665 # mshr miss rate for UpgradeReq accesses
1528system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463953 # mshr miss rate for ReadExReq accesses
1529system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463953 # mshr miss rate for ReadExReq accesses
1530system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for demand accesses
1531system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for demand accesses
1532system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for demand accesses
1533system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102285 # mshr miss rate for demand accesses
1534system.cpu.l2cache.demand_mshr_miss_rate::total 0.069165 # mshr miss rate for demand accesses
1535system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for overall accesses
1536system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for overall accesses
1537system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for overall accesses
1538system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102285 # mshr miss rate for overall accesses
1539system.cpu.l2cache.overall_mshr_miss_rate::total 0.069165 # mshr miss rate for overall accesses
1540system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average ReadReq mshr miss latency
1541system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency
1542system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73842.491497 # average ReadReq mshr miss latency
1543system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71529.684188 # average ReadReq mshr miss latency
1544system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72267.643471 # average ReadReq mshr miss latency
1545system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10750.465649 # average UpgradeReq mshr miss latency
1546system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10750.465649 # average UpgradeReq mshr miss latency
1547system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.954476 # average ReadExReq mshr miss latency
1548system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.954476 # average ReadExReq mshr miss latency
1549system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average overall mshr miss latency
1550system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency
1551system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73842.491497 # average overall mshr miss latency
1552system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60769.827258 # average overall mshr miss latency
1553system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61911.790799 # average overall mshr miss latency
1554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average overall mshr miss latency
1555system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency
1556system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73842.491497 # average overall mshr miss latency
1557system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60769.827258 # average overall mshr miss latency
1558system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61911.790799 # average overall mshr miss latency
1559system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1560system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1561system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1562system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1563system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1564system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1565system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1566system.cpu.kern.inst.arm 0 # number of arm instructions executed
1567system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1568
1569---------- End Simulation Statistics ----------