1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.125918 # Number of seconds simulated
4sim_ticks 5125917808500 # Number of ticks simulated
5final_tick 5125917808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 163224 # Simulator instruction rate (inst/s)
8host_op_rate 322646 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2051147218 # Simulator tick rate (ticks/s)
10host_mem_usage 753920 # Number of bytes of host memory used
11host_seconds 2499.05 # Real time elapsed on the host
12sim_insts 407905794 # Number of instructions simulated
13sim_ops 806307064 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 4992 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1044736 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 10779456 # Number of bytes read from this memory
20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21system.physmem.bytes_read::total 11857920 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1044736 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1044736 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 9592896 # Number of bytes written to this memory
25system.physmem.bytes_written::total 9592896 # Number of bytes written to this memory
26system.physmem.num_reads::cpu.dtb.walker 78 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 16324 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 168429 # Number of read requests responded to by this memory
30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31system.physmem.num_reads::total 185280 # Number of read requests responded to by this memory
32system.physmem.num_writes::writebacks 149889 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 149889 # Number of write requests responded to by this memory
34system.physmem.bw_read::cpu.dtb.walker 974 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.inst 203814 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.data 2102932 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 2313326 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 203814 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 203814 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1871449 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 1871449 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 1871449 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.dtb.walker 974 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.inst 203814 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.data 2102932 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 4184776 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.readReqs 185280 # Number of read requests accepted
52system.physmem.writeReqs 196609 # Number of write requests accepted
53system.physmem.readBursts 185280 # Number of DRAM read bursts, including those serviced by the write queue
54system.physmem.writeBursts 196609 # Number of DRAM write bursts, including those merged in the write queue
55system.physmem.bytesReadDRAM 11848512 # Total number of bytes read from DRAM
56system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue
57system.physmem.bytesWritten 12427072 # Total number of bytes written to DRAM
58system.physmem.bytesReadSys 11857920 # Total read bytes from the system interface side
59system.physmem.bytesWrittenSys 12582976 # Total written bytes from the system interface side
60system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue
61system.physmem.mergedWrBursts 2411 # Number of DRAM write bursts merged with an existing one
62system.physmem.neitherReadNorWriteReqs 1705 # Number of requests that are neither read nor write
63system.physmem.perBankRdBursts::0 11356 # Per bank write bursts
64system.physmem.perBankRdBursts::1 10792 # Per bank write bursts
65system.physmem.perBankRdBursts::2 11765 # Per bank write bursts
66system.physmem.perBankRdBursts::3 11427 # Per bank write bursts
67system.physmem.perBankRdBursts::4 11775 # Per bank write bursts
68system.physmem.perBankRdBursts::5 11293 # Per bank write bursts
69system.physmem.perBankRdBursts::6 11205 # Per bank write bursts
70system.physmem.perBankRdBursts::7 11692 # Per bank write bursts
71system.physmem.perBankRdBursts::8 11087 # Per bank write bursts
72system.physmem.perBankRdBursts::9 11285 # Per bank write bursts
73system.physmem.perBankRdBursts::10 11605 # Per bank write bursts
74system.physmem.perBankRdBursts::11 12031 # Per bank write bursts
75system.physmem.perBankRdBursts::12 11880 # Per bank write bursts
76system.physmem.perBankRdBursts::13 12674 # Per bank write bursts
77system.physmem.perBankRdBursts::14 11994 # Per bank write bursts
78system.physmem.perBankRdBursts::15 11272 # Per bank write bursts
79system.physmem.perBankWrBursts::0 13000 # Per bank write bursts
80system.physmem.perBankWrBursts::1 12435 # Per bank write bursts
81system.physmem.perBankWrBursts::2 11147 # Per bank write bursts
82system.physmem.perBankWrBursts::3 11517 # Per bank write bursts
83system.physmem.perBankWrBursts::4 12452 # Per bank write bursts
84system.physmem.perBankWrBursts::5 12346 # Per bank write bursts
85system.physmem.perBankWrBursts::6 11719 # Per bank write bursts
86system.physmem.perBankWrBursts::7 11239 # Per bank write bursts
87system.physmem.perBankWrBursts::8 12215 # Per bank write bursts
88system.physmem.perBankWrBursts::9 12097 # Per bank write bursts
89system.physmem.perBankWrBursts::10 12764 # Per bank write bursts
90system.physmem.perBankWrBursts::11 12134 # Per bank write bursts
91system.physmem.perBankWrBursts::12 12379 # Per bank write bursts
92system.physmem.perBankWrBursts::13 12264 # Per bank write bursts
93system.physmem.perBankWrBursts::14 12219 # Per bank write bursts
94system.physmem.perBankWrBursts::15 12246 # Per bank write bursts
95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
97system.physmem.totGap 5125917756500 # Total gap between requests
98system.physmem.readPktSize::0 0 # Read request sizes (log2)
99system.physmem.readPktSize::1 0 # Read request sizes (log2)
100system.physmem.readPktSize::2 0 # Read request sizes (log2)
101system.physmem.readPktSize::3 0 # Read request sizes (log2)
102system.physmem.readPktSize::4 0 # Read request sizes (log2)
103system.physmem.readPktSize::5 0 # Read request sizes (log2)
104system.physmem.readPktSize::6 185280 # Read request sizes (log2)
105system.physmem.writePktSize::0 0 # Write request sizes (log2)
106system.physmem.writePktSize::1 0 # Write request sizes (log2)
107system.physmem.writePktSize::2 0 # Write request sizes (log2)
108system.physmem.writePktSize::3 0 # Write request sizes (log2)
109system.physmem.writePktSize::4 0 # Write request sizes (log2)
110system.physmem.writePktSize::5 0 # Write request sizes (log2)
111system.physmem.writePktSize::6 196609 # Write request sizes (log2)
112system.physmem.rdQLenPdf::0 170576 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::1 11800 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::2 2009 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::5 44 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see

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151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::15 2619 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::16 4983 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::17 9692 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::18 11040 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::19 11520 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::20 12479 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::21 12952 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::22 14075 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::23 13662 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::24 14219 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::25 13150 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::26 12683 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::27 11195 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::28 10547 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::29 8969 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::30 8586 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::31 8463 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::32 8304 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::33 501 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::34 406 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::35 350 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::36 332 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::37 307 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::39 289 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::40 295 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::41 278 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::42 266 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::43 250 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::44 227 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::45 204 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::47 161 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
208system.physmem.bytesPerActivate::samples 74985 # Bytes accessed per row activation
209system.physmem.bytesPerActivate::mean 323.738348 # Bytes accessed per row activation
210system.physmem.bytesPerActivate::gmean 187.730188 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::stdev 342.091209 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::0-127 27875 37.17% 37.17% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::128-255 17344 23.13% 60.30% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::256-383 7346 9.80% 70.10% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::384-511 4205 5.61% 75.71% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::512-639 3044 4.06% 79.77% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::640-767 1991 2.66% 82.42% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::768-895 1466 1.96% 84.38% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::896-1023 1106 1.47% 85.85% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::1024-1151 10608 14.15% 100.00% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::total 74985 # Bytes accessed per row activation
222system.physmem.rdPerTurnAround::samples 7802 # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::mean 23.727634 # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::stdev 544.765031 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::0-2047 7801 99.99% 99.99% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::total 7802 # Reads before turning the bus around for writes
228system.physmem.wrPerTurnAround::samples 7802 # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::mean 24.887593 # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::gmean 20.377135 # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::stdev 24.103132 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::16-19 6364 81.57% 81.57% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::20-23 53 0.68% 82.25% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::24-27 22 0.28% 82.53% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::28-31 275 3.52% 86.05% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::32-35 179 2.29% 88.35% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::36-39 53 0.68% 89.03% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::40-43 27 0.35% 89.37% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::44-47 51 0.65% 90.03% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::48-51 164 2.10% 92.13% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::52-55 17 0.22% 92.35% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::56-59 13 0.17% 92.51% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::60-63 14 0.18% 92.69% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::64-67 32 0.41% 93.10% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::68-71 25 0.32% 93.42% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::72-75 7 0.09% 93.51% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::76-79 50 0.64% 94.16% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::80-83 101 1.29% 95.45% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::84-87 3 0.04% 95.49% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::88-91 9 0.12% 95.60% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::92-95 29 0.37% 95.98% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::96-99 150 1.92% 97.90% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::100-103 8 0.10% 98.00% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::104-107 7 0.09% 98.09% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::108-111 3 0.04% 98.13% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::112-115 28 0.36% 98.49% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::116-119 4 0.05% 98.54% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::120-123 11 0.14% 98.68% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::124-127 4 0.05% 98.73% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::128-131 23 0.29% 99.03% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::132-135 7 0.09% 99.12% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::136-139 3 0.04% 99.15% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::140-143 2 0.03% 99.18% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::144-147 14 0.18% 99.36% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::148-151 10 0.13% 99.49% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::152-155 2 0.03% 99.51% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::156-159 2 0.03% 99.54% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::160-163 9 0.12% 99.65% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::164-167 2 0.03% 99.68% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::168-171 1 0.01% 99.69% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::172-175 4 0.05% 99.74% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::176-179 2 0.03% 99.77% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::180-183 1 0.01% 99.78% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::188-191 2 0.03% 99.81% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::192-195 1 0.01% 99.82% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::200-203 2 0.03% 99.85% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::204-207 1 0.01% 99.86% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::208-211 3 0.04% 99.90% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::212-215 1 0.01% 99.91% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::220-223 2 0.03% 99.94% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::224-227 2 0.03% 99.96% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::total 7802 # Writes before turning the bus around for reads
286system.physmem.totQLat 2011030750 # Total ticks spent queuing
287system.physmem.totMemAccLat 5482274500 # Total ticks spent from burst creation until serviced by the DRAM
288system.physmem.totBusLat 925665000 # Total ticks spent in databus transfers
289system.physmem.avgQLat 10862.63 # Average queueing delay per DRAM burst
290system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
291system.physmem.avgMemAccLat 29612.63 # Average memory access latency per DRAM burst
292system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s
293system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s
294system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s
295system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
296system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
297system.physmem.busUtil 0.04 # Data bus utilization in percentage
298system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
299system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
300system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
301system.physmem.avgWrQLen 21.38 # Average write queue length when enqueuing
302system.physmem.readRowHits 151985 # Number of row buffer hits during reads
303system.physmem.writeRowHits 152335 # Number of row buffer hits during writes
304system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads
305system.physmem.writeRowHitRate 78.44 # Row buffer hit rate for writes
306system.physmem.avgGap 13422533.14 # Average gap between requests
307system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined
308system.physmem.memoryStateTime::IDLE 4919402035500 # Time in different power states
309system.physmem.memoryStateTime::REF 171165540000 # Time in different power states
310system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
311system.physmem.memoryStateTime::ACT 35350129500 # Time in different power states
312system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
313system.physmem.actEnergy::0 274957200 # Energy for activate commands per rank (pJ)
314system.physmem.actEnergy::1 291929400 # Energy for activate commands per rank (pJ)
315system.physmem.preEnergy::0 150026250 # Energy for precharge commands per rank (pJ)
316system.physmem.preEnergy::1 159286875 # Energy for precharge commands per rank (pJ)
317system.physmem.readEnergy::0 712179000 # Energy for read commands per rank (pJ)
318system.physmem.readEnergy::1 731850600 # Energy for read commands per rank (pJ)
319system.physmem.writeEnergy::0 621140400 # Energy for write commands per rank (pJ)
320system.physmem.writeEnergy::1 637100640 # Energy for write commands per rank (pJ)
321system.physmem.refreshEnergy::0 334799796240 # Energy for refresh commands per rank (pJ)
322system.physmem.refreshEnergy::1 334799796240 # Energy for refresh commands per rank (pJ)
323system.physmem.actBackEnergy::0 129444240060 # Energy for active background per rank (pJ)
324system.physmem.actBackEnergy::1 129652397505 # Energy for active background per rank (pJ)
325system.physmem.preBackEnergy::0 2962001074500 # Energy for precharge background per rank (pJ)
326system.physmem.preBackEnergy::1 2961818480250 # Energy for precharge background per rank (pJ)
327system.physmem.totalEnergy::0 3428003413650 # Total energy per rank (pJ)
328system.physmem.totalEnergy::1 3428090841510 # Total energy per rank (pJ)
329system.physmem.averagePower::0 668.759392 # Core power per rank (mW)
330system.physmem.averagePower::1 668.776448 # Core power per rank (mW)
331system.cpu.branchPred.lookups 86891854 # Number of BP lookups
332system.cpu.branchPred.condPredicted 86891854 # Number of conditional branches predicted
333system.cpu.branchPred.condIncorrect 902474 # Number of conditional branches incorrect
334system.cpu.branchPred.BTBLookups 80057154 # Number of BTB lookups
335system.cpu.branchPred.BTBHits 78172464 # Number of BTB hits
336system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
337system.cpu.branchPred.BTBHitPct 97.645819 # BTB Hit Percentage
338system.cpu.branchPred.usedRAS 1556145 # Number of times the RAS was used to get a target.
339system.cpu.branchPred.RASInCorrect 178539 # Number of incorrect RAS predictions.
340system.cpu_clk_domain.clock 500 # Clock period in ticks
341system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
342system.cpu.numCycles 449528542 # number of cpu cycles simulated
343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
345system.cpu.fetch.icacheStallCycles 27579139 # Number of cycles fetch is stalled on an Icache miss
346system.cpu.fetch.Insts 429063602 # Number of instructions fetch has processed
347system.cpu.fetch.Branches 86891854 # Number of branches that fetch encountered
348system.cpu.fetch.predictedBranches 79728609 # Number of branches that fetch has predicted taken
349system.cpu.fetch.Cycles 417924990 # Number of cycles fetch has run and was not squashing or blocked
350system.cpu.fetch.SquashCycles 1892404 # Number of cycles fetch has spent squashing
351system.cpu.fetch.TlbCycles 141641 # Number of cycles fetch has spent waiting for tlb
352system.cpu.fetch.MiscStallCycles 49747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
353system.cpu.fetch.PendingTrapStallCycles 210937 # Number of stall cycles due to pending traps
354system.cpu.fetch.PendingQuiesceStallCycles 127048 # Number of stall cycles due to pending quiesce instructions
355system.cpu.fetch.IcacheWaitRetryStallCycles 749 # Number of stall cycles due to full MSHR
356system.cpu.fetch.CacheLines 9185584 # Number of cache lines fetched
357system.cpu.fetch.IcacheSquashes 447344 # Number of outstanding Icache misses that were squashed
358system.cpu.fetch.ItlbSquashes 4767 # Number of outstanding ITLB misses that were squashed
359system.cpu.fetch.rateDist::samples 446980453 # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::mean 1.894336 # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.rateDist::stdev 3.051866 # Number of instructions fetched each cycle (Total)
362system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
363system.cpu.fetch.rateDist::0 281454432 62.97% 62.97% # Number of instructions fetched each cycle (Total)
364system.cpu.fetch.rateDist::1 2285018 0.51% 63.48% # Number of instructions fetched each cycle (Total)
365system.cpu.fetch.rateDist::2 72162718 16.14% 79.62% # Number of instructions fetched each cycle (Total)
366system.cpu.fetch.rateDist::3 1595292 0.36% 79.98% # Number of instructions fetched each cycle (Total)
367system.cpu.fetch.rateDist::4 2151182 0.48% 80.46% # Number of instructions fetched each cycle (Total)
368system.cpu.fetch.rateDist::5 2328836 0.52% 80.98% # Number of instructions fetched each cycle (Total)
369system.cpu.fetch.rateDist::6 1532887 0.34% 81.33% # Number of instructions fetched each cycle (Total)
370system.cpu.fetch.rateDist::7 1872269 0.42% 81.74% # Number of instructions fetched each cycle (Total)
371system.cpu.fetch.rateDist::8 81597819 18.26% 100.00% # Number of instructions fetched each cycle (Total)
372system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
373system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
374system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
375system.cpu.fetch.rateDist::total 446980453 # Number of instructions fetched each cycle (Total)
376system.cpu.fetch.branchRate 0.193296 # Number of branch fetches per cycle
377system.cpu.fetch.rate 0.954475 # Number of inst fetches per cycle
378system.cpu.decode.IdleCycles 23006879 # Number of cycles decode is idle
379system.cpu.decode.BlockedCycles 264875775 # Number of cycles decode is blocked
380system.cpu.decode.RunCycles 150713064 # Number of cycles decode is running
381system.cpu.decode.UnblockCycles 7438533 # Number of cycles decode is unblocking
382system.cpu.decode.SquashCycles 946202 # Number of cycles decode is squashing
383system.cpu.decode.DecodedInsts 838427175 # Number of instructions handled by decode
384system.cpu.rename.SquashCycles 946202 # Number of cycles rename is squashing
385system.cpu.rename.IdleCycles 25861517 # Number of cycles rename is idle
386system.cpu.rename.BlockCycles 223289477 # Number of cycles rename is blocking
387system.cpu.rename.serializeStallCycles 13277674 # count of cycles rename stalled for serializing inst
388system.cpu.rename.RunCycles 154607234 # Number of cycles rename is running
389system.cpu.rename.UnblockCycles 28998349 # Number of cycles rename is unblocking
390system.cpu.rename.RenamedInsts 834936902 # Number of instructions processed by rename
391system.cpu.rename.ROBFullEvents 476513 # Number of times rename has blocked due to ROB full
392system.cpu.rename.IQFullEvents 12412504 # Number of times rename has blocked due to IQ full
393system.cpu.rename.LQFullEvents 177326 # Number of times rename has blocked due to LQ full
394system.cpu.rename.SQFullEvents 13726812 # Number of times rename has blocked due to SQ full
395system.cpu.rename.RenamedOperands 997336716 # Number of destination operands rename has renamed
396system.cpu.rename.RenameLookups 1813473834 # Number of register rename lookups that rename has made
397system.cpu.rename.int_rename_lookups 1114859292 # Number of integer rename lookups
398system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups
399system.cpu.rename.CommittedMaps 964283425 # Number of HB maps that are committed
400system.cpu.rename.UndoneMaps 33053286 # Number of HB maps that are undone due to squashing
401system.cpu.rename.serializingInsts 468997 # count of serializing insts renamed
402system.cpu.rename.tempSerializingInsts 473016 # count of temporary serializing insts renamed
403system.cpu.rename.skidInsts 39075310 # count of insts added to the skid buffer
404system.cpu.memDep0.insertedLoads 17327574 # Number of loads inserted to the mem dependence unit.
405system.cpu.memDep0.insertedStores 10191135 # Number of stores inserted to the mem dependence unit.
406system.cpu.memDep0.conflictingLoads 1313699 # Number of conflicting loads.
407system.cpu.memDep0.conflictingStores 1076527 # Number of conflicting stores.
408system.cpu.iq.iqInstsAdded 829405798 # Number of instructions added to the IQ (excludes non-spec)
409system.cpu.iq.iqNonSpecInstsAdded 1211413 # Number of non-speculative instructions added to the IQ
410system.cpu.iq.iqInstsIssued 824144334 # Number of instructions issued
411system.cpu.iq.iqSquashedInstsIssued 238741 # Number of squashed instructions issued
412system.cpu.iq.iqSquashedInstsExamined 23374016 # Number of squashed instructions iterated over during squash; mainly for profiling
413system.cpu.iq.iqSquashedOperandsExamined 36157635 # Number of squashed operands that are examined and possibly removed from graph
414system.cpu.iq.iqSquashedNonSpecRemoved 155810 # Number of squashed non-spec instructions that were removed
415system.cpu.iq.issued_per_cycle::samples 446980453 # Number of insts issued each cycle
416system.cpu.iq.issued_per_cycle::mean 1.843804 # Number of insts issued each cycle
417system.cpu.iq.issued_per_cycle::stdev 2.418028 # Number of insts issued each cycle
418system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
419system.cpu.iq.issued_per_cycle::0 262751782 58.78% 58.78% # Number of insts issued each cycle
420system.cpu.iq.issued_per_cycle::1 13860127 3.10% 61.88% # Number of insts issued each cycle
421system.cpu.iq.issued_per_cycle::2 10088289 2.26% 64.14% # Number of insts issued each cycle
422system.cpu.iq.issued_per_cycle::3 6929216 1.55% 65.69% # Number of insts issued each cycle
423system.cpu.iq.issued_per_cycle::4 74323701 16.63% 82.32% # Number of insts issued each cycle
424system.cpu.iq.issued_per_cycle::5 4464363 1.00% 83.32% # Number of insts issued each cycle
425system.cpu.iq.issued_per_cycle::6 72802131 16.29% 99.61% # Number of insts issued each cycle
426system.cpu.iq.issued_per_cycle::7 1196176 0.27% 99.87% # Number of insts issued each cycle
427system.cpu.iq.issued_per_cycle::8 564668 0.13% 100.00% # Number of insts issued each cycle
428system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
429system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
430system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
431system.cpu.iq.issued_per_cycle::total 446980453 # Number of insts issued each cycle
432system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
433system.cpu.iq.fu_full::IntAlu 1984017 71.87% 71.87% # attempts to use FU when none available
434system.cpu.iq.fu_full::IntMult 212 0.01% 71.88% # attempts to use FU when none available
435system.cpu.iq.fu_full::IntDiv 1649 0.06% 71.94% # attempts to use FU when none available
436system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.94% # attempts to use FU when none available
437system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.94% # attempts to use FU when none available
438system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.94% # attempts to use FU when none available
439system.cpu.iq.fu_full::FloatMult 0 0.00% 71.94% # attempts to use FU when none available
440system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.94% # attempts to use FU when none available
441system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.94% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.94% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.94% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.94% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.94% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.94% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.94% # attempts to use FU when none available
448system.cpu.iq.fu_full::SimdMult 0 0.00% 71.94% # attempts to use FU when none available
449system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.94% # attempts to use FU when none available
450system.cpu.iq.fu_full::SimdShift 0 0.00% 71.94% # attempts to use FU when none available
451system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.94% # attempts to use FU when none available
452system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.94% # attempts to use FU when none available
453system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.94% # attempts to use FU when none available
454system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.94% # attempts to use FU when none available
455system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.94% # attempts to use FU when none available
456system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.94% # attempts to use FU when none available
457system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.94% # attempts to use FU when none available
458system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.94% # attempts to use FU when none available
459system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.94% # attempts to use FU when none available
460system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.94% # attempts to use FU when none available
461system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.94% # attempts to use FU when none available
462system.cpu.iq.fu_full::MemRead 613790 22.24% 94.18% # attempts to use FU when none available
463system.cpu.iq.fu_full::MemWrite 160788 5.82% 100.00% # attempts to use FU when none available
464system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
465system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
466system.cpu.iq.FU_type_0::No_OpClass 292283 0.04% 0.04% # Type of FU issued
467system.cpu.iq.FU_type_0::IntAlu 795766200 96.56% 96.59% # Type of FU issued
468system.cpu.iq.FU_type_0::IntMult 150572 0.02% 96.61% # Type of FU issued
469system.cpu.iq.FU_type_0::IntDiv 125282 0.02% 96.63% # Type of FU issued
470system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
471system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
472system.cpu.iq.FU_type_0::FloatCvt 8 0.00% 96.63% # Type of FU issued
473system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
474system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
475system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
476system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
477system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
478system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
479system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
480system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued

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488system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
489system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
490system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
491system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
492system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
493system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
494system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
495system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
496system.cpu.iq.FU_type_0::MemRead 18411850 2.23% 98.86% # Type of FU issued
497system.cpu.iq.FU_type_0::MemWrite 9398139 1.14% 100.00% # Type of FU issued
498system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
499system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
500system.cpu.iq.FU_type_0::total 824144334 # Type of FU issued
501system.cpu.iq.rate 1.833353 # Inst issue rate
502system.cpu.iq.fu_busy_cnt 2760456 # FU busy when requested
503system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst)
504system.cpu.iq.int_inst_queue_reads 2098268090 # Number of integer instruction queue reads
505system.cpu.iq.int_inst_queue_writes 854003641 # Number of integer instruction queue writes
506system.cpu.iq.int_inst_queue_wakeup_accesses 819590055 # Number of integer instruction queue wakeup accesses
507system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads
508system.cpu.iq.fp_inst_queue_writes 270 # Number of floating instruction queue writes
509system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses
510system.cpu.iq.int_alu_accesses 826612402 # Number of integer alu accesses
511system.cpu.iq.fp_alu_accesses 105 # Number of floating point alu accesses
512system.cpu.iew.lsq.thread0.forwLoads 1877597 # Number of loads that had data forwarded from stores
513system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
514system.cpu.iew.lsq.thread0.squashedLoads 3329866 # Number of loads squashed
515system.cpu.iew.lsq.thread0.ignoredResponses 14364 # Number of memory responses ignored because the instruction is squashed
516system.cpu.iew.lsq.thread0.memOrderViolation 14470 # Number of memory ordering violations
517system.cpu.iew.lsq.thread0.squashedStores 1763076 # Number of stores squashed
518system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
519system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
520system.cpu.iew.lsq.thread0.rescheduledLoads 2224552 # Number of loads that were rescheduled
521system.cpu.iew.lsq.thread0.cacheBlocked 71468 # Number of times an access to memory failed due to the cache being blocked
522system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
523system.cpu.iew.iewSquashCycles 946202 # Number of cycles IEW is squashing
524system.cpu.iew.iewBlockCycles 205595274 # Number of cycles IEW is blocking
525system.cpu.iew.iewUnblockCycles 9411486 # Number of cycles IEW is unblocking
526system.cpu.iew.iewDispatchedInsts 830617211 # Number of instructions dispatched to IQ
527system.cpu.iew.iewDispSquashedInsts 184433 # Number of squashed instructions skipped by dispatch
528system.cpu.iew.iewDispLoadInsts 17327584 # Number of dispatched load instructions
529system.cpu.iew.iewDispStoreInsts 10191135 # Number of dispatched store instructions
530system.cpu.iew.iewDispNonSpecInsts 714161 # Number of dispatched non-speculative instructions
531system.cpu.iew.iewIQFullEvents 416193 # Number of times the IQ has become full, causing a stall
532system.cpu.iew.iewLSQFullEvents 8093117 # Number of times the LSQ has become full, causing a stall
533system.cpu.iew.memOrderViolationEvents 14470 # Number of memory order violations
534system.cpu.iew.predictedTakenIncorrect 516905 # Number of branches that were predicted taken incorrectly
535system.cpu.iew.predictedNotTakenIncorrect 536436 # Number of branches that were predicted not taken incorrectly
536system.cpu.iew.branchMispredicts 1053341 # Number of branch mispredicts detected at execute
537system.cpu.iew.iewExecutedInsts 822534076 # Number of executed instructions
538system.cpu.iew.iewExecLoadInsts 18016449 # Number of load instructions executed
539system.cpu.iew.iewExecSquashedInsts 1476395 # Number of squashed instructions skipped in execute
540system.cpu.iew.exec_swp 0 # number of swp insts executed
541system.cpu.iew.exec_nop 0 # number of nop insts executed
542system.cpu.iew.exec_refs 27187129 # number of memory reference insts executed
543system.cpu.iew.exec_branches 83286990 # Number of branches executed
544system.cpu.iew.exec_stores 9170680 # Number of stores executed
545system.cpu.iew.exec_rate 1.829771 # Inst execution rate
546system.cpu.iew.wb_sent 822027813 # cumulative count of insts sent to commit
547system.cpu.iew.wb_count 819590117 # cumulative count of insts written-back
548system.cpu.iew.wb_producers 640953314 # num instructions producing a value
549system.cpu.iew.wb_consumers 1050450596 # num instructions consuming a value
550system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
551system.cpu.iew.wb_rate 1.823222 # insts written-back per cycle
552system.cpu.iew.wb_fanout 0.610170 # average fanout of values written-back
553system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
554system.cpu.commit.commitSquashedInsts 24215626 # The number of squashed insts skipped by commit
555system.cpu.commit.commitNonSpecStalls 1055602 # The number of times commit has been forced to stall to communicate backwards
556system.cpu.commit.branchMispredicts 914308 # The number of times a branch was mispredicted
557system.cpu.commit.committed_per_cycle::samples 443339838 # Number of insts commited each cycle
558system.cpu.commit.committed_per_cycle::mean 1.818711 # Number of insts commited each cycle
559system.cpu.commit.committed_per_cycle::stdev 2.675515 # Number of insts commited each cycle
560system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
561system.cpu.commit.committed_per_cycle::0 272569121 61.48% 61.48% # Number of insts commited each cycle
562system.cpu.commit.committed_per_cycle::1 11207092 2.53% 64.01% # Number of insts commited each cycle
563system.cpu.commit.committed_per_cycle::2 3543073 0.80% 64.81% # Number of insts commited each cycle
564system.cpu.commit.committed_per_cycle::3 74545535 16.81% 81.62% # Number of insts commited each cycle
565system.cpu.commit.committed_per_cycle::4 2433206 0.55% 82.17% # Number of insts commited each cycle
566system.cpu.commit.committed_per_cycle::5 1610406 0.36% 82.53% # Number of insts commited each cycle
567system.cpu.commit.committed_per_cycle::6 913346 0.21% 82.74% # Number of insts commited each cycle
568system.cpu.commit.committed_per_cycle::7 71032181 16.02% 98.76% # Number of insts commited each cycle
569system.cpu.commit.committed_per_cycle::8 5485878 1.24% 100.00% # Number of insts commited each cycle
570system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
571system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
572system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
573system.cpu.commit.committed_per_cycle::total 443339838 # Number of insts commited each cycle
574system.cpu.commit.committedInsts 407905794 # Number of instructions committed
575system.cpu.commit.committedOps 806307064 # Number of ops (including micro ops) committed
576system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
577system.cpu.commit.refs 22425775 # Number of memory references committed
578system.cpu.commit.loads 13997716 # Number of loads committed
579system.cpu.commit.membars 475203 # Number of memory barriers committed
580system.cpu.commit.branches 82185787 # Number of branches committed
581system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
582system.cpu.commit.int_insts 735131032 # Number of committed integer instructions.
583system.cpu.commit.function_calls 1155610 # Number of function calls committed.
584system.cpu.commit.op_class_0::No_OpClass 174231 0.02% 0.02% # Class of committed instruction
585system.cpu.commit.op_class_0::IntAlu 783440615 97.16% 97.19% # Class of committed instruction
586system.cpu.commit.op_class_0::IntMult 144913 0.02% 97.20% # Class of committed instruction
587system.cpu.commit.op_class_0::IntDiv 121530 0.02% 97.22% # Class of committed instruction
588system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
589system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
590system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
591system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
592system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
593system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
594system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
595system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction

--- 10 unchanged lines hidden (view full) ---

606system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
607system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
608system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
609system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
610system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
611system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
612system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
613system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
614system.cpu.commit.op_class_0::MemRead 13997716 1.74% 98.95% # Class of committed instruction
615system.cpu.commit.op_class_0::MemWrite 8428059 1.05% 100.00% # Class of committed instruction
616system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
617system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
618system.cpu.commit.op_class_0::total 806307064 # Class of committed instruction
619system.cpu.commit.bw_lim_events 5485878 # number cycles where commit BW limit reached
620system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
621system.cpu.rob.rob_reads 1268298437 # The number of ROB reads
622system.cpu.rob.rob_writes 1664703185 # The number of ROB writes
623system.cpu.timesIdled 295137 # Number of times that the entire CPU went into an idle state and unscheduled itself
624system.cpu.idleCycles 2548089 # Total number of cycles that the CPU has spent unscheduled due to idling
625system.cpu.quiesceCycles 9802307300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
626system.cpu.committedInsts 407905794 # Number of Instructions Simulated
627system.cpu.committedOps 806307064 # Number of Ops (including micro ops) Simulated
628system.cpu.cpi 1.102040 # CPI: Cycles Per Instruction
629system.cpu.cpi_total 1.102040 # CPI: Total CPI of All Threads
630system.cpu.ipc 0.907408 # IPC: Instructions Per Cycle
631system.cpu.ipc_total 0.907408 # IPC: Total IPC of All Threads
632system.cpu.int_regfile_reads 1092406866 # number of integer regfile reads
633system.cpu.int_regfile_writes 656005719 # number of integer regfile writes
634system.cpu.fp_regfile_reads 62 # number of floating regfile reads
635system.cpu.cc_regfile_reads 416194474 # number of cc regfile reads
636system.cpu.cc_regfile_writes 322040205 # number of cc regfile writes
637system.cpu.misc_regfile_reads 265569258 # number of misc regfile reads
638system.cpu.misc_regfile_writes 402671 # number of misc regfile writes
639system.cpu.dcache.tags.replacements 1659070 # number of replacements
640system.cpu.dcache.tags.tagsinuse 511.990007 # Cycle average of tags in use
641system.cpu.dcache.tags.total_refs 19130419 # Total number of references to valid blocks.
642system.cpu.dcache.tags.sampled_refs 1659582 # Sample count of references to valid blocks.
643system.cpu.dcache.tags.avg_refs 11.527251 # Average number of references to valid blocks.
644system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
645system.cpu.dcache.tags.occ_blocks::cpu.data 511.990007 # Average occupied blocks per requestor
646system.cpu.dcache.tags.occ_percent::cpu.data 0.999980 # Average percentage of cache occupancy
647system.cpu.dcache.tags.occ_percent::total 0.999980 # Average percentage of cache occupancy
648system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
649system.cpu.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id
650system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id
651system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
652system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
653system.cpu.dcache.tags.tag_accesses 88317394 # Number of tag accesses
654system.cpu.dcache.tags.data_accesses 88317394 # Number of data accesses
655system.cpu.dcache.ReadReq_hits::cpu.data 10978879 # number of ReadReq hits
656system.cpu.dcache.ReadReq_hits::total 10978879 # number of ReadReq hits
657system.cpu.dcache.WriteReq_hits::cpu.data 8084521 # number of WriteReq hits
658system.cpu.dcache.WriteReq_hits::total 8084521 # number of WriteReq hits
659system.cpu.dcache.SoftPFReq_hits::cpu.data 64338 # number of SoftPFReq hits
660system.cpu.dcache.SoftPFReq_hits::total 64338 # number of SoftPFReq hits
661system.cpu.dcache.demand_hits::cpu.data 19063400 # number of demand (read+write) hits
662system.cpu.dcache.demand_hits::total 19063400 # number of demand (read+write) hits
663system.cpu.dcache.overall_hits::cpu.data 19127738 # number of overall hits
664system.cpu.dcache.overall_hits::total 19127738 # number of overall hits
665system.cpu.dcache.ReadReq_misses::cpu.data 1796470 # number of ReadReq misses
666system.cpu.dcache.ReadReq_misses::total 1796470 # number of ReadReq misses
667system.cpu.dcache.WriteReq_misses::cpu.data 333911 # number of WriteReq misses
668system.cpu.dcache.WriteReq_misses::total 333911 # number of WriteReq misses
669system.cpu.dcache.SoftPFReq_misses::cpu.data 406328 # number of SoftPFReq misses
670system.cpu.dcache.SoftPFReq_misses::total 406328 # number of SoftPFReq misses
671system.cpu.dcache.demand_misses::cpu.data 2130381 # number of demand (read+write) misses
672system.cpu.dcache.demand_misses::total 2130381 # number of demand (read+write) misses
673system.cpu.dcache.overall_misses::cpu.data 2536709 # number of overall misses
674system.cpu.dcache.overall_misses::total 2536709 # number of overall misses
675system.cpu.dcache.ReadReq_miss_latency::cpu.data 26526077953 # number of ReadReq miss cycles
676system.cpu.dcache.ReadReq_miss_latency::total 26526077953 # number of ReadReq miss cycles
677system.cpu.dcache.WriteReq_miss_latency::cpu.data 12856931699 # number of WriteReq miss cycles
678system.cpu.dcache.WriteReq_miss_latency::total 12856931699 # number of WriteReq miss cycles
679system.cpu.dcache.demand_miss_latency::cpu.data 39383009652 # number of demand (read+write) miss cycles
680system.cpu.dcache.demand_miss_latency::total 39383009652 # number of demand (read+write) miss cycles
681system.cpu.dcache.overall_miss_latency::cpu.data 39383009652 # number of overall miss cycles
682system.cpu.dcache.overall_miss_latency::total 39383009652 # number of overall miss cycles
683system.cpu.dcache.ReadReq_accesses::cpu.data 12775349 # number of ReadReq accesses(hits+misses)
684system.cpu.dcache.ReadReq_accesses::total 12775349 # number of ReadReq accesses(hits+misses)
685system.cpu.dcache.WriteReq_accesses::cpu.data 8418432 # number of WriteReq accesses(hits+misses)
686system.cpu.dcache.WriteReq_accesses::total 8418432 # number of WriteReq accesses(hits+misses)
687system.cpu.dcache.SoftPFReq_accesses::cpu.data 470666 # number of SoftPFReq accesses(hits+misses)
688system.cpu.dcache.SoftPFReq_accesses::total 470666 # number of SoftPFReq accesses(hits+misses)
689system.cpu.dcache.demand_accesses::cpu.data 21193781 # number of demand (read+write) accesses
690system.cpu.dcache.demand_accesses::total 21193781 # number of demand (read+write) accesses
691system.cpu.dcache.overall_accesses::cpu.data 21664447 # number of overall (read+write) accesses
692system.cpu.dcache.overall_accesses::total 21664447 # number of overall (read+write) accesses
693system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140620 # miss rate for ReadReq accesses
694system.cpu.dcache.ReadReq_miss_rate::total 0.140620 # miss rate for ReadReq accesses
695system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039664 # miss rate for WriteReq accesses
696system.cpu.dcache.WriteReq_miss_rate::total 0.039664 # miss rate for WriteReq accesses
697system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863304 # miss rate for SoftPFReq accesses
698system.cpu.dcache.SoftPFReq_miss_rate::total 0.863304 # miss rate for SoftPFReq accesses
699system.cpu.dcache.demand_miss_rate::cpu.data 0.100519 # miss rate for demand accesses
700system.cpu.dcache.demand_miss_rate::total 0.100519 # miss rate for demand accesses
701system.cpu.dcache.overall_miss_rate::cpu.data 0.117091 # miss rate for overall accesses
702system.cpu.dcache.overall_miss_rate::total 0.117091 # miss rate for overall accesses
703system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.667088 # average ReadReq miss latency
704system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.667088 # average ReadReq miss latency
705system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38504.067548 # average WriteReq miss latency
706system.cpu.dcache.WriteReq_avg_miss_latency::total 38504.067548 # average WriteReq miss latency
707system.cpu.dcache.demand_avg_miss_latency::cpu.data 18486.369176 # average overall miss latency
708system.cpu.dcache.demand_avg_miss_latency::total 18486.369176 # average overall miss latency
709system.cpu.dcache.overall_avg_miss_latency::cpu.data 15525.237484 # average overall miss latency
710system.cpu.dcache.overall_avg_miss_latency::total 15525.237484 # average overall miss latency
711system.cpu.dcache.blocked_cycles::no_mshrs 375690 # number of cycles access was blocked
712system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
713system.cpu.dcache.blocked::no_mshrs 39932 # number of cycles access was blocked
714system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
715system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.408244 # average number of cycles each access was blocked
716system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
717system.cpu.dcache.fast_writes 0 # number of fast writes performed
718system.cpu.dcache.cache_copies 0 # number of cache copies performed
719system.cpu.dcache.writebacks::writebacks 1560667 # number of writebacks
720system.cpu.dcache.writebacks::total 1560667 # number of writebacks
721system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827312 # number of ReadReq MSHR hits
722system.cpu.dcache.ReadReq_mshr_hits::total 827312 # number of ReadReq MSHR hits
723system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44114 # number of WriteReq MSHR hits
724system.cpu.dcache.WriteReq_mshr_hits::total 44114 # number of WriteReq MSHR hits
725system.cpu.dcache.demand_mshr_hits::cpu.data 871426 # number of demand (read+write) MSHR hits
726system.cpu.dcache.demand_mshr_hits::total 871426 # number of demand (read+write) MSHR hits
727system.cpu.dcache.overall_mshr_hits::cpu.data 871426 # number of overall MSHR hits
728system.cpu.dcache.overall_mshr_hits::total 871426 # number of overall MSHR hits
729system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969158 # number of ReadReq MSHR misses
730system.cpu.dcache.ReadReq_mshr_misses::total 969158 # number of ReadReq MSHR misses
731system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289797 # number of WriteReq MSHR misses
732system.cpu.dcache.WriteReq_mshr_misses::total 289797 # number of WriteReq MSHR misses
733system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402869 # number of SoftPFReq MSHR misses
734system.cpu.dcache.SoftPFReq_mshr_misses::total 402869 # number of SoftPFReq MSHR misses
735system.cpu.dcache.demand_mshr_misses::cpu.data 1258955 # number of demand (read+write) MSHR misses
736system.cpu.dcache.demand_mshr_misses::total 1258955 # number of demand (read+write) MSHR misses
737system.cpu.dcache.overall_mshr_misses::cpu.data 1661824 # number of overall MSHR misses
738system.cpu.dcache.overall_mshr_misses::total 1661824 # number of overall MSHR misses
739system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12253110515 # number of ReadReq MSHR miss cycles
740system.cpu.dcache.ReadReq_mshr_miss_latency::total 12253110515 # number of ReadReq MSHR miss cycles
741system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11193391556 # number of WriteReq MSHR miss cycles
742system.cpu.dcache.WriteReq_mshr_miss_latency::total 11193391556 # number of WriteReq MSHR miss cycles
743system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5590029250 # number of SoftPFReq MSHR miss cycles
744system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5590029250 # number of SoftPFReq MSHR miss cycles
745system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23446502071 # number of demand (read+write) MSHR miss cycles
746system.cpu.dcache.demand_mshr_miss_latency::total 23446502071 # number of demand (read+write) MSHR miss cycles
747system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29036531321 # number of overall MSHR miss cycles
748system.cpu.dcache.overall_mshr_miss_latency::total 29036531321 # number of overall MSHR miss cycles
749system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97386643000 # number of ReadReq MSHR uncacheable cycles
750system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97386643000 # number of ReadReq MSHR uncacheable cycles
751system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2557063000 # number of WriteReq MSHR uncacheable cycles
752system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2557063000 # number of WriteReq MSHR uncacheable cycles
753system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99943706000 # number of overall MSHR uncacheable cycles
754system.cpu.dcache.overall_mshr_uncacheable_latency::total 99943706000 # number of overall MSHR uncacheable cycles
755system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075862 # mshr miss rate for ReadReq accesses
756system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075862 # mshr miss rate for ReadReq accesses
757system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034424 # mshr miss rate for WriteReq accesses
758system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034424 # mshr miss rate for WriteReq accesses
759system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855955 # mshr miss rate for SoftPFReq accesses
760system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855955 # mshr miss rate for SoftPFReq accesses
761system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059402 # mshr miss rate for demand accesses
762system.cpu.dcache.demand_mshr_miss_rate::total 0.059402 # mshr miss rate for demand accesses
763system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076707 # mshr miss rate for overall accesses
764system.cpu.dcache.overall_mshr_miss_rate::total 0.076707 # mshr miss rate for overall accesses
765system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12643.047382 # average ReadReq mshr miss latency
766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12643.047382 # average ReadReq mshr miss latency
767system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38624.939375 # average WriteReq mshr miss latency
768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38624.939375 # average WriteReq mshr miss latency
769system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13875.550737 # average SoftPFReq mshr miss latency
770system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13875.550737 # average SoftPFReq mshr miss latency
771system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18623.780891 # average overall mshr miss latency
772system.cpu.dcache.demand_avg_mshr_miss_latency::total 18623.780891 # average overall mshr miss latency
773system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.687433 # average overall mshr miss latency
774system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.687433 # average overall mshr miss latency
775system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
776system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
777system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
778system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
779system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
780system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
781system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
782system.cpu.dtb_walker_cache.tags.replacements 73854 # number of replacements
783system.cpu.dtb_walker_cache.tags.tagsinuse 15.812426 # Cycle average of tags in use
784system.cpu.dtb_walker_cache.tags.total_refs 117340 # Total number of references to valid blocks.
785system.cpu.dtb_walker_cache.tags.sampled_refs 73869 # Sample count of references to valid blocks.
786system.cpu.dtb_walker_cache.tags.avg_refs 1.588488 # Average number of references to valid blocks.
787system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit.
788system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812426 # Average occupied blocks per requestor
789system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988277 # Average percentage of cache occupancy
790system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988277 # Average percentage of cache occupancy
791system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
792system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id
793system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
794system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
795system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
796system.cpu.dtb_walker_cache.tags.tag_accesses 459584 # Number of tag accesses
797system.cpu.dtb_walker_cache.tags.data_accesses 459584 # Number of data accesses
798system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117385 # number of ReadReq hits
799system.cpu.dtb_walker_cache.ReadReq_hits::total 117385 # number of ReadReq hits
800system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117385 # number of demand (read+write) hits
801system.cpu.dtb_walker_cache.demand_hits::total 117385 # number of demand (read+write) hits
802system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117385 # number of overall hits
803system.cpu.dtb_walker_cache.overall_hits::total 117385 # number of overall hits
804system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74938 # number of ReadReq misses
805system.cpu.dtb_walker_cache.ReadReq_misses::total 74938 # number of ReadReq misses
806system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74938 # number of demand (read+write) misses
807system.cpu.dtb_walker_cache.demand_misses::total 74938 # number of demand (read+write) misses
808system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74938 # number of overall misses
809system.cpu.dtb_walker_cache.overall_misses::total 74938 # number of overall misses
810system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 912423463 # number of ReadReq miss cycles
811system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 912423463 # number of ReadReq miss cycles
812system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 912423463 # number of demand (read+write) miss cycles
813system.cpu.dtb_walker_cache.demand_miss_latency::total 912423463 # number of demand (read+write) miss cycles
814system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 912423463 # number of overall miss cycles
815system.cpu.dtb_walker_cache.overall_miss_latency::total 912423463 # number of overall miss cycles
816system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192323 # number of ReadReq accesses(hits+misses)
817system.cpu.dtb_walker_cache.ReadReq_accesses::total 192323 # number of ReadReq accesses(hits+misses)
818system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192323 # number of demand (read+write) accesses
819system.cpu.dtb_walker_cache.demand_accesses::total 192323 # number of demand (read+write) accesses
820system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192323 # number of overall (read+write) accesses
821system.cpu.dtb_walker_cache.overall_accesses::total 192323 # number of overall (read+write) accesses
822system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389647 # miss rate for ReadReq accesses
823system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389647 # miss rate for ReadReq accesses
824system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389647 # miss rate for demand accesses
825system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389647 # miss rate for demand accesses
826system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389647 # miss rate for overall accesses
827system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389647 # miss rate for overall accesses
828system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12175.711428 # average ReadReq miss latency
829system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12175.711428 # average ReadReq miss latency
830system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12175.711428 # average overall miss latency
831system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12175.711428 # average overall miss latency
832system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12175.711428 # average overall miss latency
833system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12175.711428 # average overall miss latency
834system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
835system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
836system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
837system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
838system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
839system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
840system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
841system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
842system.cpu.dtb_walker_cache.writebacks::writebacks 19615 # number of writebacks
843system.cpu.dtb_walker_cache.writebacks::total 19615 # number of writebacks
844system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74938 # number of ReadReq MSHR misses
845system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74938 # number of ReadReq MSHR misses
846system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74938 # number of demand (read+write) MSHR misses
847system.cpu.dtb_walker_cache.demand_mshr_misses::total 74938 # number of demand (read+write) MSHR misses
848system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74938 # number of overall MSHR misses
849system.cpu.dtb_walker_cache.overall_mshr_misses::total 74938 # number of overall MSHR misses
850system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 762426693 # number of ReadReq MSHR miss cycles
851system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 762426693 # number of ReadReq MSHR miss cycles
852system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 762426693 # number of demand (read+write) MSHR miss cycles
853system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 762426693 # number of demand (read+write) MSHR miss cycles
854system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 762426693 # number of overall MSHR miss cycles
855system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 762426693 # number of overall MSHR miss cycles
856system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389647 # mshr miss rate for ReadReq accesses
857system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389647 # mshr miss rate for ReadReq accesses
858system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389647 # mshr miss rate for demand accesses
859system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389647 # mshr miss rate for demand accesses
860system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389647 # mshr miss rate for overall accesses
861system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389647 # mshr miss rate for overall accesses
862system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829 # average ReadReq mshr miss latency
863system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10174.099829 # average ReadReq mshr miss latency
864system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829 # average overall mshr miss latency
865system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10174.099829 # average overall mshr miss latency
866system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829 # average overall mshr miss latency
867system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10174.099829 # average overall mshr miss latency
868system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
869system.cpu.icache.tags.replacements 996223 # number of replacements
870system.cpu.icache.tags.tagsinuse 510.034964 # Cycle average of tags in use
871system.cpu.icache.tags.total_refs 8125334 # Total number of references to valid blocks.
872system.cpu.icache.tags.sampled_refs 996735 # Sample count of references to valid blocks.
873system.cpu.icache.tags.avg_refs 8.151950 # Average number of references to valid blocks.
874system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit.
875system.cpu.icache.tags.occ_blocks::cpu.inst 510.034964 # Average occupied blocks per requestor
876system.cpu.icache.tags.occ_percent::cpu.inst 0.996162 # Average percentage of cache occupancy
877system.cpu.icache.tags.occ_percent::total 0.996162 # Average percentage of cache occupancy
878system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
879system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
880system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
881system.cpu.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
882system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
883system.cpu.icache.tags.tag_accesses 10182364 # Number of tag accesses
884system.cpu.icache.tags.data_accesses 10182364 # Number of data accesses
885system.cpu.icache.ReadReq_hits::cpu.inst 8125334 # number of ReadReq hits
886system.cpu.icache.ReadReq_hits::total 8125334 # number of ReadReq hits
887system.cpu.icache.demand_hits::cpu.inst 8125334 # number of demand (read+write) hits
888system.cpu.icache.demand_hits::total 8125334 # number of demand (read+write) hits
889system.cpu.icache.overall_hits::cpu.inst 8125334 # number of overall hits
890system.cpu.icache.overall_hits::total 8125334 # number of overall hits
891system.cpu.icache.ReadReq_misses::cpu.inst 1060246 # number of ReadReq misses
892system.cpu.icache.ReadReq_misses::total 1060246 # number of ReadReq misses
893system.cpu.icache.demand_misses::cpu.inst 1060246 # number of demand (read+write) misses
894system.cpu.icache.demand_misses::total 1060246 # number of demand (read+write) misses
895system.cpu.icache.overall_misses::cpu.inst 1060246 # number of overall misses
896system.cpu.icache.overall_misses::total 1060246 # number of overall misses
897system.cpu.icache.ReadReq_miss_latency::cpu.inst 14710988702 # number of ReadReq miss cycles
898system.cpu.icache.ReadReq_miss_latency::total 14710988702 # number of ReadReq miss cycles
899system.cpu.icache.demand_miss_latency::cpu.inst 14710988702 # number of demand (read+write) miss cycles
900system.cpu.icache.demand_miss_latency::total 14710988702 # number of demand (read+write) miss cycles
901system.cpu.icache.overall_miss_latency::cpu.inst 14710988702 # number of overall miss cycles
902system.cpu.icache.overall_miss_latency::total 14710988702 # number of overall miss cycles
903system.cpu.icache.ReadReq_accesses::cpu.inst 9185580 # number of ReadReq accesses(hits+misses)
904system.cpu.icache.ReadReq_accesses::total 9185580 # number of ReadReq accesses(hits+misses)
905system.cpu.icache.demand_accesses::cpu.inst 9185580 # number of demand (read+write) accesses
906system.cpu.icache.demand_accesses::total 9185580 # number of demand (read+write) accesses
907system.cpu.icache.overall_accesses::cpu.inst 9185580 # number of overall (read+write) accesses
908system.cpu.icache.overall_accesses::total 9185580 # number of overall (read+write) accesses
909system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses
910system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses
911system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses
912system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses
913system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses
914system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses
915system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13875.071165 # average ReadReq miss latency
916system.cpu.icache.ReadReq_avg_miss_latency::total 13875.071165 # average ReadReq miss latency
917system.cpu.icache.demand_avg_miss_latency::cpu.inst 13875.071165 # average overall miss latency
918system.cpu.icache.demand_avg_miss_latency::total 13875.071165 # average overall miss latency
919system.cpu.icache.overall_avg_miss_latency::cpu.inst 13875.071165 # average overall miss latency
920system.cpu.icache.overall_avg_miss_latency::total 13875.071165 # average overall miss latency
921system.cpu.icache.blocked_cycles::no_mshrs 8852 # number of cycles access was blocked
922system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
923system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked
924system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
925system.cpu.icache.avg_blocked_cycles::no_mshrs 29.408638 # average number of cycles each access was blocked
926system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
927system.cpu.icache.fast_writes 0 # number of fast writes performed
928system.cpu.icache.cache_copies 0 # number of cache copies performed
929system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63462 # number of ReadReq MSHR hits
930system.cpu.icache.ReadReq_mshr_hits::total 63462 # number of ReadReq MSHR hits
931system.cpu.icache.demand_mshr_hits::cpu.inst 63462 # number of demand (read+write) MSHR hits
932system.cpu.icache.demand_mshr_hits::total 63462 # number of demand (read+write) MSHR hits
933system.cpu.icache.overall_mshr_hits::cpu.inst 63462 # number of overall MSHR hits
934system.cpu.icache.overall_mshr_hits::total 63462 # number of overall MSHR hits
935system.cpu.icache.ReadReq_mshr_misses::cpu.inst 996784 # number of ReadReq MSHR misses
936system.cpu.icache.ReadReq_mshr_misses::total 996784 # number of ReadReq MSHR misses
937system.cpu.icache.demand_mshr_misses::cpu.inst 996784 # number of demand (read+write) MSHR misses
938system.cpu.icache.demand_mshr_misses::total 996784 # number of demand (read+write) MSHR misses
939system.cpu.icache.overall_mshr_misses::cpu.inst 996784 # number of overall MSHR misses
940system.cpu.icache.overall_mshr_misses::total 996784 # number of overall MSHR misses
941system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12075236643 # number of ReadReq MSHR miss cycles
942system.cpu.icache.ReadReq_mshr_miss_latency::total 12075236643 # number of ReadReq MSHR miss cycles
943system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12075236643 # number of demand (read+write) MSHR miss cycles
944system.cpu.icache.demand_mshr_miss_latency::total 12075236643 # number of demand (read+write) MSHR miss cycles
945system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12075236643 # number of overall MSHR miss cycles
946system.cpu.icache.overall_mshr_miss_latency::total 12075236643 # number of overall MSHR miss cycles
947system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for ReadReq accesses
948system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108516 # mshr miss rate for ReadReq accesses
949system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for demand accesses
950system.cpu.icache.demand_mshr_miss_rate::total 0.108516 # mshr miss rate for demand accesses
951system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for overall accesses
952system.cpu.icache.overall_mshr_miss_rate::total 0.108516 # mshr miss rate for overall accesses
953system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12114.195897 # average ReadReq mshr miss latency
954system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12114.195897 # average ReadReq mshr miss latency
955system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12114.195897 # average overall mshr miss latency
956system.cpu.icache.demand_avg_mshr_miss_latency::total 12114.195897 # average overall mshr miss latency
957system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12114.195897 # average overall mshr miss latency
958system.cpu.icache.overall_avg_mshr_miss_latency::total 12114.195897 # average overall mshr miss latency
959system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
960system.cpu.itb_walker_cache.tags.replacements 13757 # number of replacements
961system.cpu.itb_walker_cache.tags.tagsinuse 6.017843 # Cycle average of tags in use
962system.cpu.itb_walker_cache.tags.total_refs 26179 # Total number of references to valid blocks.
963system.cpu.itb_walker_cache.tags.sampled_refs 13772 # Sample count of references to valid blocks.
964system.cpu.itb_walker_cache.tags.avg_refs 1.900886 # Average number of references to valid blocks.
965system.cpu.itb_walker_cache.tags.warmup_cycle 5104067070500 # Cycle when the warmup percentage was hit.
966system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017843 # Average occupied blocks per requestor
967system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376115 # Average percentage of cache occupancy
968system.cpu.itb_walker_cache.tags.occ_percent::total 0.376115 # Average percentage of cache occupancy
969system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
970system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
971system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
972system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
973system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
974system.cpu.itb_walker_cache.tags.tag_accesses 96280 # Number of tag accesses
975system.cpu.itb_walker_cache.tags.data_accesses 96280 # Number of data accesses
976system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26178 # number of ReadReq hits
977system.cpu.itb_walker_cache.ReadReq_hits::total 26178 # number of ReadReq hits
978system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
979system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
980system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26180 # number of demand (read+write) hits
981system.cpu.itb_walker_cache.demand_hits::total 26180 # number of demand (read+write) hits
982system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26180 # number of overall hits
983system.cpu.itb_walker_cache.overall_hits::total 26180 # number of overall hits
984system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14640 # number of ReadReq misses
985system.cpu.itb_walker_cache.ReadReq_misses::total 14640 # number of ReadReq misses
986system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14640 # number of demand (read+write) misses
987system.cpu.itb_walker_cache.demand_misses::total 14640 # number of demand (read+write) misses
988system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14640 # number of overall misses
989system.cpu.itb_walker_cache.overall_misses::total 14640 # number of overall misses
990system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168910997 # number of ReadReq miss cycles
991system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168910997 # number of ReadReq miss cycles
992system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168910997 # number of demand (read+write) miss cycles
993system.cpu.itb_walker_cache.demand_miss_latency::total 168910997 # number of demand (read+write) miss cycles
994system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168910997 # number of overall miss cycles
995system.cpu.itb_walker_cache.overall_miss_latency::total 168910997 # number of overall miss cycles
996system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40818 # number of ReadReq accesses(hits+misses)
997system.cpu.itb_walker_cache.ReadReq_accesses::total 40818 # number of ReadReq accesses(hits+misses)
998system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
999system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1000system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40820 # number of demand (read+write) accesses
1001system.cpu.itb_walker_cache.demand_accesses::total 40820 # number of demand (read+write) accesses
1002system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40820 # number of overall (read+write) accesses
1003system.cpu.itb_walker_cache.overall_accesses::total 40820 # number of overall (read+write) accesses
1004system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358665 # miss rate for ReadReq accesses
1005system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358665 # miss rate for ReadReq accesses
1006system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358648 # miss rate for demand accesses
1007system.cpu.itb_walker_cache.demand_miss_rate::total 0.358648 # miss rate for demand accesses
1008system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358648 # miss rate for overall accesses
1009system.cpu.itb_walker_cache.overall_miss_rate::total 0.358648 # miss rate for overall accesses
1010system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11537.636407 # average ReadReq miss latency
1011system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11537.636407 # average ReadReq miss latency
1012system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11537.636407 # average overall miss latency
1013system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11537.636407 # average overall miss latency
1014system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11537.636407 # average overall miss latency
1015system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11537.636407 # average overall miss latency
1016system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1017system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1018system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1019system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1020system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1021system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1022system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1023system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1024system.cpu.itb_walker_cache.writebacks::writebacks 3000 # number of writebacks
1025system.cpu.itb_walker_cache.writebacks::total 3000 # number of writebacks
1026system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14640 # number of ReadReq MSHR misses
1027system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14640 # number of ReadReq MSHR misses
1028system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14640 # number of demand (read+write) MSHR misses
1029system.cpu.itb_walker_cache.demand_mshr_misses::total 14640 # number of demand (read+write) MSHR misses
1030system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14640 # number of overall MSHR misses
1031system.cpu.itb_walker_cache.overall_mshr_misses::total 14640 # number of overall MSHR misses
1032system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 139618019 # number of ReadReq MSHR miss cycles
1033system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 139618019 # number of ReadReq MSHR miss cycles
1034system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 139618019 # number of demand (read+write) MSHR miss cycles
1035system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 139618019 # number of demand (read+write) MSHR miss cycles
1036system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 139618019 # number of overall MSHR miss cycles
1037system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 139618019 # number of overall MSHR miss cycles
1038system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358665 # mshr miss rate for ReadReq accesses
1039system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358665 # mshr miss rate for ReadReq accesses
1040system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358648 # mshr miss rate for demand accesses
1041system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358648 # mshr miss rate for demand accesses
1042system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358648 # mshr miss rate for overall accesses
1043system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358648 # mshr miss rate for overall accesses
1044system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9536.749932 # average ReadReq mshr miss latency
1045system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9536.749932 # average ReadReq mshr miss latency
1046system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9536.749932 # average overall mshr miss latency
1047system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9536.749932 # average overall mshr miss latency
1048system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9536.749932 # average overall mshr miss latency
1049system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9536.749932 # average overall mshr miss latency
1050system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1051system.cpu.l2cache.tags.replacements 113048 # number of replacements
1052system.cpu.l2cache.tags.tagsinuse 64817.930454 # Cycle average of tags in use
1053system.cpu.l2cache.tags.total_refs 3838289 # Total number of references to valid blocks.
1054system.cpu.l2cache.tags.sampled_refs 177093 # Sample count of references to valid blocks.
1055system.cpu.l2cache.tags.avg_refs 21.673861 # Average number of references to valid blocks.
1056system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1057system.cpu.l2cache.tags.occ_blocks::writebacks 50426.330308 # Average occupied blocks per requestor
1058system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.730844 # Average occupied blocks per requestor
1059system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.138507 # Average occupied blocks per requestor
1060system.cpu.l2cache.tags.occ_blocks::cpu.inst 3266.844648 # Average occupied blocks per requestor
1061system.cpu.l2cache.tags.occ_blocks::cpu.data 11101.886147 # Average occupied blocks per requestor
1062system.cpu.l2cache.tags.occ_percent::writebacks 0.769445 # Average percentage of cache occupancy
1063system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy
1064system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1065system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049848 # Average percentage of cache occupancy
1066system.cpu.l2cache.tags.occ_percent::cpu.data 0.169401 # Average percentage of cache occupancy
1067system.cpu.l2cache.tags.occ_percent::total 0.989043 # Average percentage of cache occupancy
1068system.cpu.l2cache.tags.occ_task_id_blocks::1024 64045 # Occupied blocks per task id
1069system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
1070system.cpu.l2cache.tags.age_task_id_blocks_1024::1 604 # Occupied blocks per task id
1071system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3317 # Occupied blocks per task id
1072system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5815 # Occupied blocks per task id
1073system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54248 # Occupied blocks per task id
1074system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977249 # Percentage of cache occupancy per task id
1075system.cpu.l2cache.tags.tag_accesses 35033990 # Number of tag accesses
1076system.cpu.l2cache.tags.data_accesses 35033990 # Number of data accesses
1077system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67104 # number of ReadReq hits
1078system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12092 # number of ReadReq hits
1079system.cpu.l2cache.ReadReq_hits::cpu.inst 980368 # number of ReadReq hits
1080system.cpu.l2cache.ReadReq_hits::cpu.data 1335401 # number of ReadReq hits
1081system.cpu.l2cache.ReadReq_hits::total 2394965 # number of ReadReq hits
1082system.cpu.l2cache.Writeback_hits::writebacks 1583282 # number of Writeback hits
1083system.cpu.l2cache.Writeback_hits::total 1583282 # number of Writeback hits
1084system.cpu.l2cache.UpgradeReq_hits::cpu.data 318 # number of UpgradeReq hits
1085system.cpu.l2cache.UpgradeReq_hits::total 318 # number of UpgradeReq hits
1086system.cpu.l2cache.ReadExReq_hits::cpu.data 154206 # number of ReadExReq hits
1087system.cpu.l2cache.ReadExReq_hits::total 154206 # number of ReadExReq hits
1088system.cpu.l2cache.demand_hits::cpu.dtb.walker 67104 # number of demand (read+write) hits
1089system.cpu.l2cache.demand_hits::cpu.itb.walker 12092 # number of demand (read+write) hits
1090system.cpu.l2cache.demand_hits::cpu.inst 980368 # number of demand (read+write) hits
1091system.cpu.l2cache.demand_hits::cpu.data 1489607 # number of demand (read+write) hits
1092system.cpu.l2cache.demand_hits::total 2549171 # number of demand (read+write) hits
1093system.cpu.l2cache.overall_hits::cpu.dtb.walker 67104 # number of overall hits
1094system.cpu.l2cache.overall_hits::cpu.itb.walker 12092 # number of overall hits
1095system.cpu.l2cache.overall_hits::cpu.inst 980368 # number of overall hits
1096system.cpu.l2cache.overall_hits::cpu.data 1489607 # number of overall hits
1097system.cpu.l2cache.overall_hits::total 2549171 # number of overall hits
1098system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 78 # number of ReadReq misses
1099system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
1100system.cpu.l2cache.ReadReq_misses::cpu.inst 16326 # number of ReadReq misses
1101system.cpu.l2cache.ReadReq_misses::cpu.data 35890 # number of ReadReq misses
1102system.cpu.l2cache.ReadReq_misses::total 52300 # number of ReadReq misses
1103system.cpu.l2cache.UpgradeReq_misses::cpu.data 1440 # number of UpgradeReq misses
1104system.cpu.l2cache.UpgradeReq_misses::total 1440 # number of UpgradeReq misses
1105system.cpu.l2cache.ReadExReq_misses::cpu.data 133494 # number of ReadExReq misses
1106system.cpu.l2cache.ReadExReq_misses::total 133494 # number of ReadExReq misses
1107system.cpu.l2cache.demand_misses::cpu.dtb.walker 78 # number of demand (read+write) misses
1108system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
1109system.cpu.l2cache.demand_misses::cpu.inst 16326 # number of demand (read+write) misses
1110system.cpu.l2cache.demand_misses::cpu.data 169384 # number of demand (read+write) misses
1111system.cpu.l2cache.demand_misses::total 185794 # number of demand (read+write) misses
1112system.cpu.l2cache.overall_misses::cpu.dtb.walker 78 # number of overall misses
1113system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
1114system.cpu.l2cache.overall_misses::cpu.inst 16326 # number of overall misses
1115system.cpu.l2cache.overall_misses::cpu.data 169384 # number of overall misses
1116system.cpu.l2cache.overall_misses::total 185794 # number of overall misses
1117system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6504500 # number of ReadReq miss cycles
1118system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 472000 # number of ReadReq miss cycles
1119system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1249428250 # number of ReadReq miss cycles
1120system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2850151495 # number of ReadReq miss cycles
1121system.cpu.l2cache.ReadReq_miss_latency::total 4106556245 # number of ReadReq miss cycles
1122system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17517303 # number of UpgradeReq miss cycles
1123system.cpu.l2cache.UpgradeReq_miss_latency::total 17517303 # number of UpgradeReq miss cycles
1124system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9319163717 # number of ReadExReq miss cycles
1125system.cpu.l2cache.ReadExReq_miss_latency::total 9319163717 # number of ReadExReq miss cycles
1126system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6504500 # number of demand (read+write) miss cycles
1127system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 472000 # number of demand (read+write) miss cycles
1128system.cpu.l2cache.demand_miss_latency::cpu.inst 1249428250 # number of demand (read+write) miss cycles
1129system.cpu.l2cache.demand_miss_latency::cpu.data 12169315212 # number of demand (read+write) miss cycles
1130system.cpu.l2cache.demand_miss_latency::total 13425719962 # number of demand (read+write) miss cycles
1131system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6504500 # number of overall miss cycles
1132system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 472000 # number of overall miss cycles
1133system.cpu.l2cache.overall_miss_latency::cpu.inst 1249428250 # number of overall miss cycles
1134system.cpu.l2cache.overall_miss_latency::cpu.data 12169315212 # number of overall miss cycles
1135system.cpu.l2cache.overall_miss_latency::total 13425719962 # number of overall miss cycles
1136system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67182 # number of ReadReq accesses(hits+misses)
1137system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12098 # number of ReadReq accesses(hits+misses)
1138system.cpu.l2cache.ReadReq_accesses::cpu.inst 996694 # number of ReadReq accesses(hits+misses)
1139system.cpu.l2cache.ReadReq_accesses::cpu.data 1371291 # number of ReadReq accesses(hits+misses)
1140system.cpu.l2cache.ReadReq_accesses::total 2447265 # number of ReadReq accesses(hits+misses)
1141system.cpu.l2cache.Writeback_accesses::writebacks 1583282 # number of Writeback accesses(hits+misses)
1142system.cpu.l2cache.Writeback_accesses::total 1583282 # number of Writeback accesses(hits+misses)
1143system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1758 # number of UpgradeReq accesses(hits+misses)
1144system.cpu.l2cache.UpgradeReq_accesses::total 1758 # number of UpgradeReq accesses(hits+misses)
1145system.cpu.l2cache.ReadExReq_accesses::cpu.data 287700 # number of ReadExReq accesses(hits+misses)
1146system.cpu.l2cache.ReadExReq_accesses::total 287700 # number of ReadExReq accesses(hits+misses)
1147system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67182 # number of demand (read+write) accesses
1148system.cpu.l2cache.demand_accesses::cpu.itb.walker 12098 # number of demand (read+write) accesses
1149system.cpu.l2cache.demand_accesses::cpu.inst 996694 # number of demand (read+write) accesses
1150system.cpu.l2cache.demand_accesses::cpu.data 1658991 # number of demand (read+write) accesses
1151system.cpu.l2cache.demand_accesses::total 2734965 # number of demand (read+write) accesses
1152system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67182 # number of overall (read+write) accesses
1153system.cpu.l2cache.overall_accesses::cpu.itb.walker 12098 # number of overall (read+write) accesses
1154system.cpu.l2cache.overall_accesses::cpu.inst 996694 # number of overall (read+write) accesses
1155system.cpu.l2cache.overall_accesses::cpu.data 1658991 # number of overall (read+write) accesses
1156system.cpu.l2cache.overall_accesses::total 2734965 # number of overall (read+write) accesses
1157system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001161 # miss rate for ReadReq accesses
1158system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000496 # miss rate for ReadReq accesses
1159system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016380 # miss rate for ReadReq accesses
1160system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026172 # miss rate for ReadReq accesses
1161system.cpu.l2cache.ReadReq_miss_rate::total 0.021371 # miss rate for ReadReq accesses
1162system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.819113 # miss rate for UpgradeReq accesses
1163system.cpu.l2cache.UpgradeReq_miss_rate::total 0.819113 # miss rate for UpgradeReq accesses
1164system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464004 # miss rate for ReadExReq accesses
1165system.cpu.l2cache.ReadExReq_miss_rate::total 0.464004 # miss rate for ReadExReq accesses
1166system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001161 # miss rate for demand accesses
1167system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000496 # miss rate for demand accesses
1168system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016380 # miss rate for demand accesses
1169system.cpu.l2cache.demand_miss_rate::cpu.data 0.102101 # miss rate for demand accesses
1170system.cpu.l2cache.demand_miss_rate::total 0.067933 # miss rate for demand accesses
1171system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001161 # miss rate for overall accesses
1172system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000496 # miss rate for overall accesses
1173system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016380 # miss rate for overall accesses
1174system.cpu.l2cache.overall_miss_rate::cpu.data 0.102101 # miss rate for overall accesses
1175system.cpu.l2cache.overall_miss_rate::total 0.067933 # miss rate for overall accesses
1176system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83391.025641 # average ReadReq miss latency
1177system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78666.666667 # average ReadReq miss latency
1178system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76529.967536 # average ReadReq miss latency
1179system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79413.527306 # average ReadReq miss latency
1180system.cpu.l2cache.ReadReq_avg_miss_latency::total 78519.239866 # average ReadReq miss latency
1181system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12164.793750 # average UpgradeReq miss latency
1182system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12164.793750 # average UpgradeReq miss latency
1183system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69809.607301 # average ReadExReq miss latency
1184system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69809.607301 # average ReadExReq miss latency
1185system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83391.025641 # average overall miss latency
1186system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78666.666667 # average overall miss latency
1187system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76529.967536 # average overall miss latency
1188system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71844.537926 # average overall miss latency
1189system.cpu.l2cache.demand_avg_miss_latency::total 72261.321474 # average overall miss latency
1190system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83391.025641 # average overall miss latency
1191system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78666.666667 # average overall miss latency
1192system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76529.967536 # average overall miss latency
1193system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71844.537926 # average overall miss latency
1194system.cpu.l2cache.overall_avg_miss_latency::total 72261.321474 # average overall miss latency
1195system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1196system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1197system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1198system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1199system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1200system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1201system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1202system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1203system.cpu.l2cache.writebacks::writebacks 103222 # number of writebacks
1204system.cpu.l2cache.writebacks::total 103222 # number of writebacks
1205system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
1206system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
1207system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
1208system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1209system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
1210system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
1211system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1212system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
1213system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
1214system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 78 # number of ReadReq MSHR misses
1215system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
1216system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16324 # number of ReadReq MSHR misses
1217system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35888 # number of ReadReq MSHR misses
1218system.cpu.l2cache.ReadReq_mshr_misses::total 52296 # number of ReadReq MSHR misses
1219system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1440 # number of UpgradeReq MSHR misses
1220system.cpu.l2cache.UpgradeReq_mshr_misses::total 1440 # number of UpgradeReq MSHR misses
1221system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133494 # number of ReadExReq MSHR misses
1222system.cpu.l2cache.ReadExReq_mshr_misses::total 133494 # number of ReadExReq MSHR misses
1223system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 78 # number of demand (read+write) MSHR misses
1224system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
1225system.cpu.l2cache.demand_mshr_misses::cpu.inst 16324 # number of demand (read+write) MSHR misses
1226system.cpu.l2cache.demand_mshr_misses::cpu.data 169382 # number of demand (read+write) MSHR misses
1227system.cpu.l2cache.demand_mshr_misses::total 185790 # number of demand (read+write) MSHR misses
1228system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 78 # number of overall MSHR misses
1229system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
1230system.cpu.l2cache.overall_mshr_misses::cpu.inst 16324 # number of overall MSHR misses
1231system.cpu.l2cache.overall_mshr_misses::cpu.data 169382 # number of overall MSHR misses
1232system.cpu.l2cache.overall_mshr_misses::total 185790 # number of overall MSHR misses
1233system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5539000 # number of ReadReq MSHR miss cycles
1234system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 396000 # number of ReadReq MSHR miss cycles
1235system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1044610750 # number of ReadReq MSHR miss cycles
1236system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2405275997 # number of ReadReq MSHR miss cycles
1237system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3455821747 # number of ReadReq MSHR miss cycles
1238system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15368421 # number of UpgradeReq MSHR miss cycles
1239system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15368421 # number of UpgradeReq MSHR miss cycles
1240system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7642927283 # number of ReadExReq MSHR miss cycles
1241system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7642927283 # number of ReadExReq MSHR miss cycles
1242system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5539000 # number of demand (read+write) MSHR miss cycles
1243system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 396000 # number of demand (read+write) MSHR miss cycles
1244system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1044610750 # number of demand (read+write) MSHR miss cycles
1245system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10048203280 # number of demand (read+write) MSHR miss cycles
1246system.cpu.l2cache.demand_mshr_miss_latency::total 11098749030 # number of demand (read+write) MSHR miss cycles
1247system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5539000 # number of overall MSHR miss cycles
1248system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 396000 # number of overall MSHR miss cycles
1249system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1044610750 # number of overall MSHR miss cycles
1250system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10048203280 # number of overall MSHR miss cycles
1251system.cpu.l2cache.overall_mshr_miss_latency::total 11098749030 # number of overall MSHR miss cycles
1252system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89272220000 # number of ReadReq MSHR uncacheable cycles
1253system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89272220000 # number of ReadReq MSHR uncacheable cycles
1254system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2390455500 # number of WriteReq MSHR uncacheable cycles
1255system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2390455500 # number of WriteReq MSHR uncacheable cycles
1256system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91662675500 # number of overall MSHR uncacheable cycles
1257system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91662675500 # number of overall MSHR uncacheable cycles
1258system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001161 # mshr miss rate for ReadReq accesses
1259system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadReq accesses
1260system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016378 # mshr miss rate for ReadReq accesses
1261system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026171 # mshr miss rate for ReadReq accesses
1262system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021369 # mshr miss rate for ReadReq accesses
1263system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.819113 # mshr miss rate for UpgradeReq accesses
1264system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.819113 # mshr miss rate for UpgradeReq accesses
1265system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464004 # mshr miss rate for ReadExReq accesses
1266system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464004 # mshr miss rate for ReadExReq accesses
1267system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001161 # mshr miss rate for demand accesses
1268system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses
1269system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016378 # mshr miss rate for demand accesses
1270system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102099 # mshr miss rate for demand accesses
1271system.cpu.l2cache.demand_mshr_miss_rate::total 0.067931 # mshr miss rate for demand accesses
1272system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001161 # mshr miss rate for overall accesses
1273system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses
1274system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016378 # mshr miss rate for overall accesses
1275system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102099 # mshr miss rate for overall accesses
1276system.cpu.l2cache.overall_mshr_miss_rate::total 0.067931 # mshr miss rate for overall accesses
1277system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513 # average ReadReq mshr miss latency
1278system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66000 # average ReadReq mshr miss latency
1279system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63992.327248 # average ReadReq mshr miss latency
1280system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67021.734201 # average ReadReq mshr miss latency
1281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66081.951717 # average ReadReq mshr miss latency
1282system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10672.514583 # average UpgradeReq mshr miss latency
1283system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10672.514583 # average UpgradeReq mshr miss latency
1284system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57252.964800 # average ReadExReq mshr miss latency
1285system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57252.964800 # average ReadExReq mshr miss latency
1286system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513 # average overall mshr miss latency
1287system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66000 # average overall mshr miss latency
1288system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63992.327248 # average overall mshr miss latency
1289system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59322.733703 # average overall mshr miss latency
1290system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59738.139997 # average overall mshr miss latency
1291system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513 # average overall mshr miss latency
1292system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66000 # average overall mshr miss latency
1293system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63992.327248 # average overall mshr miss latency
1294system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59322.733703 # average overall mshr miss latency
1295system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59738.139997 # average overall mshr miss latency
1296system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1297system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1298system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1299system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1300system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1301system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1302system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1303system.cpu.toL2Bus.trans_dist::ReadReq 3068576 # Transaction distribution
1304system.cpu.toL2Bus.trans_dist::ReadResp 3068035 # Transaction distribution
1305system.cpu.toL2Bus.trans_dist::WriteReq 13841 # Transaction distribution
1306system.cpu.toL2Bus.trans_dist::WriteResp 13841 # Transaction distribution
1307system.cpu.toL2Bus.trans_dist::Writeback 1583282 # Transaction distribution
1308system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1309system.cpu.toL2Bus.trans_dist::UpgradeReq 2219 # Transaction distribution
1310system.cpu.toL2Bus.trans_dist::UpgradeResp 2219 # Transaction distribution
1311system.cpu.toL2Bus.trans_dist::ReadExReq 287706 # Transaction distribution
1312system.cpu.toL2Bus.trans_dist::ReadExResp 287706 # Transaction distribution
1313system.cpu.toL2Bus.trans_dist::BadAddressError 12 # Transaction distribution
1314system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1993478 # Packet count per connected master and slave (bytes)
1315system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130100 # Packet count per connected master and slave (bytes)
1316system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29738 # Packet count per connected master and slave (bytes)
1317system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 161735 # Packet count per connected master and slave (bytes)
1318system.cpu.toL2Bus.pkt_count::total 8315051 # Packet count per connected master and slave (bytes)
1319system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63788416 # Cumulative packet size per connected master and slave (bytes)
1320system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207873825 # Cumulative packet size per connected master and slave (bytes)
1321system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 966272 # Cumulative packet size per connected master and slave (bytes)
1322system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5555008 # Cumulative packet size per connected master and slave (bytes)
1323system.cpu.toL2Bus.pkt_size::total 278183521 # Cumulative packet size per connected master and slave (bytes)
1324system.cpu.toL2Bus.snoops 59487 # Total snoops (count)
1325system.cpu.toL2Bus.snoop_fanout::samples 4379111 # Request fanout histogram
1326system.cpu.toL2Bus.snoop_fanout::mean 3.010877 # Request fanout histogram
1327system.cpu.toL2Bus.snoop_fanout::stdev 0.103722 # Request fanout histogram
1328system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1329system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1330system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1331system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1332system.cpu.toL2Bus.snoop_fanout::3 4331481 98.91% 98.91% # Request fanout histogram
1333system.cpu.toL2Bus.snoop_fanout::4 47630 1.09% 100.00% # Request fanout histogram
1334system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1335system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1336system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1337system.cpu.toL2Bus.snoop_fanout::total 4379111 # Request fanout histogram
1338system.cpu.toL2Bus.reqLayer0.occupancy 4067623882 # Layer occupancy (ticks)
1339system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1340system.cpu.toL2Bus.snoopLayer0.occupancy 571500 # Layer occupancy (ticks)
1341system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1342system.cpu.toL2Bus.respLayer0.occupancy 1499268850 # Layer occupancy (ticks)
1343system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1344system.cpu.toL2Bus.respLayer1.occupancy 3141964932 # Layer occupancy (ticks)
1345system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1346system.cpu.toL2Bus.respLayer2.occupancy 21966489 # Layer occupancy (ticks)
1347system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1348system.cpu.toL2Bus.respLayer3.occupancy 112467385 # Layer occupancy (ticks)
1349system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1350system.iobus.trans_dist::ReadReq 225657 # Transaction distribution
1351system.iobus.trans_dist::ReadResp 225657 # Transaction distribution
1352system.iobus.trans_dist::WriteReq 57676 # Transaction distribution
1353system.iobus.trans_dist::WriteResp 10956 # Transaction distribution
1354system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1355system.iobus.trans_dist::MessageReq 1641 # Transaction distribution
1356system.iobus.trans_dist::MessageResp 1641 # Transaction distribution
1357system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1358system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1359system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
1360system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1361system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1362system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1363system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1364system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1365system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
1366system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1367system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1368system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1369system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
1370system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1371system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1372system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1373system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1374system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1375system.iobus.pkt_count_system.bridge.master::total 471406 # Packet count per connected master and slave (bytes)
1376system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
1377system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
1378system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes)
1379system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes)
1380system.iobus.pkt_count::total 569948 # Packet count per connected master and slave (bytes)
1381system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1382system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1383system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
1384system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1385system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1386system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1387system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1388system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1389system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
1390system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1391system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1392system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1393system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
1394system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1395system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1396system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1397system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1398system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1399system.iobus.pkt_size_system.bridge.master::total 241980 # Cumulative packet size per connected master and slave (bytes)
1400system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
1401system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
1402system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes)
1403system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes)
1404system.iobus.pkt_size::total 3276368 # Cumulative packet size per connected master and slave (bytes)
1405system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks)
1406system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1407system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1408system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1409system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1410system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1411system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks)
1412system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1413system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1414system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1415system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1416system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1417system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1418system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1419system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)

--- 13 unchanged lines hidden (view full) ---

1433system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1434system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1435system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1436system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1437system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1438system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1439system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1440system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1441system.iobus.reqLayer19.occupancy 448438152 # Layer occupancy (ticks)
1442system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1443system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1444system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1445system.iobus.respLayer0.occupancy 460450000 # Layer occupancy (ticks)
1446system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1447system.iobus.respLayer1.occupancy 52358513 # Layer occupancy (ticks)
1448system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1449system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks)
1450system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1451system.iocache.tags.replacements 47575 # number of replacements
1452system.iocache.tags.tagsinuse 0.091509 # Cycle average of tags in use
1453system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1454system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
1455system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1456system.iocache.tags.warmup_cycle 4992976927000 # Cycle when the warmup percentage was hit.
1457system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091509 # Average occupied blocks per requestor
1458system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005719 # Average percentage of cache occupancy
1459system.iocache.tags.occ_percent::total 0.005719 # Average percentage of cache occupancy
1460system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1461system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1462system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1463system.iocache.tags.tag_accesses 428670 # Number of tag accesses
1464system.iocache.tags.data_accesses 428670 # Number of data accesses
1465system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
1466system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
1467system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
1468system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
1469system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
1470system.iocache.demand_misses::total 910 # number of demand (read+write) misses
1471system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
1472system.iocache.overall_misses::total 910 # number of overall misses
1473system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151600663 # number of ReadReq miss cycles
1474system.iocache.ReadReq_miss_latency::total 151600663 # number of ReadReq miss cycles
1475system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12348426976 # number of WriteInvalidateReq miss cycles
1476system.iocache.WriteInvalidateReq_miss_latency::total 12348426976 # number of WriteInvalidateReq miss cycles
1477system.iocache.demand_miss_latency::pc.south_bridge.ide 151600663 # number of demand (read+write) miss cycles
1478system.iocache.demand_miss_latency::total 151600663 # number of demand (read+write) miss cycles
1479system.iocache.overall_miss_latency::pc.south_bridge.ide 151600663 # number of overall miss cycles
1480system.iocache.overall_miss_latency::total 151600663 # number of overall miss cycles
1481system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
1482system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
1483system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1484system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1485system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
1486system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
1487system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
1488system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
1489system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1490system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1491system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
1492system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1493system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1494system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1495system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1496system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1497system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average ReadReq miss latency
1498system.iocache.ReadReq_avg_miss_latency::total 166594.135165 # average ReadReq miss latency
1499system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264307.084247 # average WriteInvalidateReq miss latency
1500system.iocache.WriteInvalidateReq_avg_miss_latency::total 264307.084247 # average WriteInvalidateReq miss latency
1501system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average overall miss latency
1502system.iocache.demand_avg_miss_latency::total 166594.135165 # average overall miss latency
1503system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average overall miss latency
1504system.iocache.overall_avg_miss_latency::total 166594.135165 # average overall miss latency
1505system.iocache.blocked_cycles::no_mshrs 70653 # number of cycles access was blocked
1506system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1507system.iocache.blocked::no_mshrs 9154 # number of cycles access was blocked
1508system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1509system.iocache.avg_blocked_cycles::no_mshrs 7.718265 # average number of cycles each access was blocked
1510system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1511system.iocache.fast_writes 0 # number of fast writes performed
1512system.iocache.cache_copies 0 # number of cache copies performed
1513system.iocache.writebacks::writebacks 46667 # number of writebacks
1514system.iocache.writebacks::total 46667 # number of writebacks
1515system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
1516system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
1517system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
1518system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
1519system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
1520system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
1521system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
1522system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
1523system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of ReadReq MSHR miss cycles
1524system.iocache.ReadReq_mshr_miss_latency::total 104259663 # number of ReadReq MSHR miss cycles
1525system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918961002 # number of WriteInvalidateReq MSHR miss cycles
1526system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918961002 # number of WriteInvalidateReq MSHR miss cycles
1527system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of demand (read+write) MSHR miss cycles
1528system.iocache.demand_mshr_miss_latency::total 104259663 # number of demand (read+write) MSHR miss cycles
1529system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of overall MSHR miss cycles
1530system.iocache.overall_mshr_miss_latency::total 104259663 # number of overall MSHR miss cycles
1531system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1532system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1533system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1534system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1535system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1536system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1537system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1538system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1539system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average ReadReq mshr miss latency
1540system.iocache.ReadReq_avg_mshr_miss_latency::total 114571.058242 # average ReadReq mshr miss latency
1541system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212306.528296 # average WriteInvalidateReq mshr miss latency
1542system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212306.528296 # average WriteInvalidateReq mshr miss latency
1543system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average overall mshr miss latency
1544system.iocache.demand_avg_mshr_miss_latency::total 114571.058242 # average overall mshr miss latency
1545system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average overall mshr miss latency
1546system.iocache.overall_avg_mshr_miss_latency::total 114571.058242 # average overall mshr miss latency
1547system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1548system.membus.trans_dist::ReadReq 662598 # Transaction distribution
1549system.membus.trans_dist::ReadResp 662586 # Transaction distribution
1550system.membus.trans_dist::WriteReq 13841 # Transaction distribution
1551system.membus.trans_dist::WriteResp 13841 # Transaction distribution
1552system.membus.trans_dist::Writeback 149889 # Transaction distribution
1553system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1554system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1555system.membus.trans_dist::UpgradeReq 2184 # Transaction distribution
1556system.membus.trans_dist::UpgradeResp 1723 # Transaction distribution
1557system.membus.trans_dist::ReadExReq 133213 # Transaction distribution
1558system.membus.trans_dist::ReadExResp 133211 # Transaction distribution
1559system.membus.trans_dist::MessageReq 1641 # Transaction distribution
1560system.membus.trans_dist::MessageResp 1641 # Transaction distribution
1561system.membus.trans_dist::BadAddressError 12 # Transaction distribution
1562system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes)
1563system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes)
1564system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471406 # Packet count per connected master and slave (bytes)
1565system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775060 # Packet count per connected master and slave (bytes)
1566system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477445 # Packet count per connected master and slave (bytes)
1567system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 24 # Packet count per connected master and slave (bytes)
1568system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723935 # Packet count per connected master and slave (bytes)
1569system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141460 # Packet count per connected master and slave (bytes)
1570system.membus.pkt_count_system.iocache.mem_side::total 141460 # Packet count per connected master and slave (bytes)
1571system.membus.pkt_count::total 1868677 # Packet count per connected master and slave (bytes)
1572system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes)
1573system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes)
1574system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241980 # Cumulative packet size per connected master and slave (bytes)
1575system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550117 # Cumulative packet size per connected master and slave (bytes)
1576system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435776 # Cumulative packet size per connected master and slave (bytes)
1577system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20227873 # Cumulative packet size per connected master and slave (bytes)
1578system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
1579system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
1580system.membus.pkt_size::total 26239557 # Cumulative packet size per connected master and slave (bytes)
1581system.membus.snoops 1606 # Total snoops (count)
1582system.membus.snoop_fanout::samples 385212 # Request fanout histogram
1583system.membus.snoop_fanout::mean 1 # Request fanout histogram
1584system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1585system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1586system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1587system.membus.snoop_fanout::1 385212 100.00% 100.00% # Request fanout histogram
1588system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1589system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1590system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1591system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1592system.membus.snoop_fanout::total 385212 # Request fanout histogram
1593system.membus.reqLayer0.occupancy 251510000 # Layer occupancy (ticks)
1594system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1595system.membus.reqLayer1.occupancy 583228000 # Layer occupancy (ticks)
1596system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1597system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks)
1598system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1599system.membus.reqLayer3.occupancy 1995467500 # Layer occupancy (ticks)
1600system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1601system.membus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
1602system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1603system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks)
1604system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1605system.membus.respLayer2.occupancy 3158524545 # Layer occupancy (ticks)
1606system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
1607system.membus.respLayer4.occupancy 54933487 # Layer occupancy (ticks)
1608system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1609system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1610system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1611system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
1612system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1613system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1614system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1615system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1616system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1617system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1618system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1619system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1620system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1621system.cpu.kern.inst.arm 0 # number of arm instructions executed
1622system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1623
1624---------- End Simulation Statistics ----------