| config.ini (10791:a80d2d716a53) | config.ini (10901:8cfa8dac39fe) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 197 unchanged lines hidden (view full) --- 206children=tags 207addr_ranges=0:18446744073709551615 208assoc=4 209clk_domain=system.cpu_clk_domain 210demand_mshr_reserve=1 211eventq_index=0 212forward_snoops=true 213hit_latency=2 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 197 unchanged lines hidden (view full) --- 206children=tags 207addr_ranges=0:18446744073709551615 208assoc=4 209clk_domain=system.cpu_clk_domain 210demand_mshr_reserve=1 211eventq_index=0 212forward_snoops=true 213hit_latency=2 |
| 214is_top_level=true | 214is_read_only=false |
| 215max_miss_count=0 216mshrs=4 217prefetch_on_access=false 218prefetcher=Null 219response_latency=2 220sequential_access=false 221size=32768 222system=system 223tags=system.cpu.dcache.tags 224tgts_per_mshr=20 | 215max_miss_count=0 216mshrs=4 217prefetch_on_access=false 218prefetcher=Null 219response_latency=2 220sequential_access=false 221size=32768 222system=system 223tags=system.cpu.dcache.tags 224tgts_per_mshr=20 |
| 225two_queue=false | |
| 226write_buffers=8 227cpu_side=system.cpu.dcache_port 228mem_side=system.cpu.toL2Bus.slave[1] 229 230[system.cpu.dcache.tags] 231type=LRU 232assoc=4 233block_size=64 --- 21 unchanged lines hidden (view full) --- 255[system.cpu.dtb_walker_cache] 256type=BaseCache 257children=tags 258addr_ranges=0:18446744073709551615 259assoc=2 260clk_domain=system.cpu_clk_domain 261demand_mshr_reserve=1 262eventq_index=0 | 225write_buffers=8 226cpu_side=system.cpu.dcache_port 227mem_side=system.cpu.toL2Bus.slave[1] 228 229[system.cpu.dcache.tags] 230type=LRU 231assoc=4 232block_size=64 --- 21 unchanged lines hidden (view full) --- 254[system.cpu.dtb_walker_cache] 255type=BaseCache 256children=tags 257addr_ranges=0:18446744073709551615 258assoc=2 259clk_domain=system.cpu_clk_domain 260demand_mshr_reserve=1 261eventq_index=0 |
| 263forward_snoops=true | 262forward_snoops=false |
| 264hit_latency=2 | 263hit_latency=2 |
| 265is_top_level=true | 264is_read_only=false |
| 266max_miss_count=0 267mshrs=10 268prefetch_on_access=false 269prefetcher=Null 270response_latency=2 271sequential_access=false 272size=1024 273system=system 274tags=system.cpu.dtb_walker_cache.tags 275tgts_per_mshr=12 | 265max_miss_count=0 266mshrs=10 267prefetch_on_access=false 268prefetcher=Null 269response_latency=2 270sequential_access=false 271size=1024 272system=system 273tags=system.cpu.dtb_walker_cache.tags 274tgts_per_mshr=12 |
| 276two_queue=false | |
| 277write_buffers=8 278cpu_side=system.cpu.dtb.walker.port 279mem_side=system.cpu.toL2Bus.slave[3] 280 281[system.cpu.dtb_walker_cache.tags] 282type=LRU 283assoc=2 284block_size=64 --- 14 unchanged lines hidden (view full) --- 299children=opList 300count=6 301eventq_index=0 302opList=system.cpu.fuPool.FUList0.opList 303 304[system.cpu.fuPool.FUList0.opList] 305type=OpDesc 306eventq_index=0 | 275write_buffers=8 276cpu_side=system.cpu.dtb.walker.port 277mem_side=system.cpu.toL2Bus.slave[3] 278 279[system.cpu.dtb_walker_cache.tags] 280type=LRU 281assoc=2 282block_size=64 --- 14 unchanged lines hidden (view full) --- 297children=opList 298count=6 299eventq_index=0 300opList=system.cpu.fuPool.FUList0.opList 301 302[system.cpu.fuPool.FUList0.opList] 303type=OpDesc 304eventq_index=0 |
| 307issueLat=1 | |
| 308opClass=IntAlu 309opLat=1 | 305opClass=IntAlu 306opLat=1 |
| 307pipelined=true |
|
| 310 311[system.cpu.fuPool.FUList1] 312type=FUDesc 313children=opList0 opList1 314count=2 315eventq_index=0 316opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 317 318[system.cpu.fuPool.FUList1.opList0] 319type=OpDesc 320eventq_index=0 | 308 309[system.cpu.fuPool.FUList1] 310type=FUDesc 311children=opList0 opList1 312count=2 313eventq_index=0 314opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 315 316[system.cpu.fuPool.FUList1.opList0] 317type=OpDesc 318eventq_index=0 |
| 321issueLat=1 | |
| 322opClass=IntMult 323opLat=3 | 319opClass=IntMult 320opLat=3 |
| 321pipelined=true |
|
| 324 325[system.cpu.fuPool.FUList1.opList1] 326type=OpDesc 327eventq_index=0 | 322 323[system.cpu.fuPool.FUList1.opList1] 324type=OpDesc 325eventq_index=0 |
| 328issueLat=19 | |
| 329opClass=IntDiv | 326opClass=IntDiv |
| 330opLat=20 | 327opLat=1 328pipelined=false |
| 331 332[system.cpu.fuPool.FUList2] 333type=FUDesc 334children=opList0 opList1 opList2 335count=4 336eventq_index=0 337opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 338 339[system.cpu.fuPool.FUList2.opList0] 340type=OpDesc 341eventq_index=0 | 329 330[system.cpu.fuPool.FUList2] 331type=FUDesc 332children=opList0 opList1 opList2 333count=4 334eventq_index=0 335opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 336 337[system.cpu.fuPool.FUList2.opList0] 338type=OpDesc 339eventq_index=0 |
| 342issueLat=1 | |
| 343opClass=FloatAdd 344opLat=2 | 340opClass=FloatAdd 341opLat=2 |
| 342pipelined=true |
|
| 345 346[system.cpu.fuPool.FUList2.opList1] 347type=OpDesc 348eventq_index=0 | 343 344[system.cpu.fuPool.FUList2.opList1] 345type=OpDesc 346eventq_index=0 |
| 349issueLat=1 | |
| 350opClass=FloatCmp 351opLat=2 | 347opClass=FloatCmp 348opLat=2 |
| 349pipelined=true |
|
| 352 353[system.cpu.fuPool.FUList2.opList2] 354type=OpDesc 355eventq_index=0 | 350 351[system.cpu.fuPool.FUList2.opList2] 352type=OpDesc 353eventq_index=0 |
| 356issueLat=1 | |
| 357opClass=FloatCvt 358opLat=2 | 354opClass=FloatCvt 355opLat=2 |
| 356pipelined=true |
|
| 359 360[system.cpu.fuPool.FUList3] 361type=FUDesc 362children=opList0 opList1 opList2 363count=2 364eventq_index=0 365opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 366 367[system.cpu.fuPool.FUList3.opList0] 368type=OpDesc 369eventq_index=0 | 357 358[system.cpu.fuPool.FUList3] 359type=FUDesc 360children=opList0 opList1 opList2 361count=2 362eventq_index=0 363opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 364 365[system.cpu.fuPool.FUList3.opList0] 366type=OpDesc 367eventq_index=0 |
| 370issueLat=1 | |
| 371opClass=FloatMult 372opLat=4 | 368opClass=FloatMult 369opLat=4 |
| 370pipelined=true |
|
| 373 374[system.cpu.fuPool.FUList3.opList1] 375type=OpDesc 376eventq_index=0 | 371 372[system.cpu.fuPool.FUList3.opList1] 373type=OpDesc 374eventq_index=0 |
| 377issueLat=12 | |
| 378opClass=FloatDiv 379opLat=12 | 375opClass=FloatDiv 376opLat=12 |
| 377pipelined=false |
|
| 380 381[system.cpu.fuPool.FUList3.opList2] 382type=OpDesc 383eventq_index=0 | 378 379[system.cpu.fuPool.FUList3.opList2] 380type=OpDesc 381eventq_index=0 |
| 384issueLat=24 | |
| 385opClass=FloatSqrt 386opLat=24 | 382opClass=FloatSqrt 383opLat=24 |
| 384pipelined=false |
|
| 387 388[system.cpu.fuPool.FUList4] 389type=FUDesc 390children=opList 391count=0 392eventq_index=0 393opList=system.cpu.fuPool.FUList4.opList 394 395[system.cpu.fuPool.FUList4.opList] 396type=OpDesc 397eventq_index=0 | 385 386[system.cpu.fuPool.FUList4] 387type=FUDesc 388children=opList 389count=0 390eventq_index=0 391opList=system.cpu.fuPool.FUList4.opList 392 393[system.cpu.fuPool.FUList4.opList] 394type=OpDesc 395eventq_index=0 |
| 398issueLat=1 | |
| 399opClass=MemRead 400opLat=1 | 396opClass=MemRead 397opLat=1 |
| 398pipelined=true |
|
| 401 402[system.cpu.fuPool.FUList5] 403type=FUDesc 404children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 405count=4 406eventq_index=0 407opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 408 409[system.cpu.fuPool.FUList5.opList00] 410type=OpDesc 411eventq_index=0 | 399 400[system.cpu.fuPool.FUList5] 401type=FUDesc 402children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 403count=4 404eventq_index=0 405opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 406 407[system.cpu.fuPool.FUList5.opList00] 408type=OpDesc 409eventq_index=0 |
| 412issueLat=1 | |
| 413opClass=SimdAdd 414opLat=1 | 410opClass=SimdAdd 411opLat=1 |
| 412pipelined=true |
|
| 415 416[system.cpu.fuPool.FUList5.opList01] 417type=OpDesc 418eventq_index=0 | 413 414[system.cpu.fuPool.FUList5.opList01] 415type=OpDesc 416eventq_index=0 |
| 419issueLat=1 | |
| 420opClass=SimdAddAcc 421opLat=1 | 417opClass=SimdAddAcc 418opLat=1 |
| 419pipelined=true |
|
| 422 423[system.cpu.fuPool.FUList5.opList02] 424type=OpDesc 425eventq_index=0 | 420 421[system.cpu.fuPool.FUList5.opList02] 422type=OpDesc 423eventq_index=0 |
| 426issueLat=1 | |
| 427opClass=SimdAlu 428opLat=1 | 424opClass=SimdAlu 425opLat=1 |
| 426pipelined=true |
|
| 429 430[system.cpu.fuPool.FUList5.opList03] 431type=OpDesc 432eventq_index=0 | 427 428[system.cpu.fuPool.FUList5.opList03] 429type=OpDesc 430eventq_index=0 |
| 433issueLat=1 | |
| 434opClass=SimdCmp 435opLat=1 | 431opClass=SimdCmp 432opLat=1 |
| 433pipelined=true |
|
| 436 437[system.cpu.fuPool.FUList5.opList04] 438type=OpDesc 439eventq_index=0 | 434 435[system.cpu.fuPool.FUList5.opList04] 436type=OpDesc 437eventq_index=0 |
| 440issueLat=1 | |
| 441opClass=SimdCvt 442opLat=1 | 438opClass=SimdCvt 439opLat=1 |
| 440pipelined=true |
|
| 443 444[system.cpu.fuPool.FUList5.opList05] 445type=OpDesc 446eventq_index=0 | 441 442[system.cpu.fuPool.FUList5.opList05] 443type=OpDesc 444eventq_index=0 |
| 447issueLat=1 | |
| 448opClass=SimdMisc 449opLat=1 | 445opClass=SimdMisc 446opLat=1 |
| 447pipelined=true |
|
| 450 451[system.cpu.fuPool.FUList5.opList06] 452type=OpDesc 453eventq_index=0 | 448 449[system.cpu.fuPool.FUList5.opList06] 450type=OpDesc 451eventq_index=0 |
| 454issueLat=1 | |
| 455opClass=SimdMult 456opLat=1 | 452opClass=SimdMult 453opLat=1 |
| 454pipelined=true |
|
| 457 458[system.cpu.fuPool.FUList5.opList07] 459type=OpDesc 460eventq_index=0 | 455 456[system.cpu.fuPool.FUList5.opList07] 457type=OpDesc 458eventq_index=0 |
| 461issueLat=1 | |
| 462opClass=SimdMultAcc 463opLat=1 | 459opClass=SimdMultAcc 460opLat=1 |
| 461pipelined=true |
|
| 464 465[system.cpu.fuPool.FUList5.opList08] 466type=OpDesc 467eventq_index=0 | 462 463[system.cpu.fuPool.FUList5.opList08] 464type=OpDesc 465eventq_index=0 |
| 468issueLat=1 | |
| 469opClass=SimdShift 470opLat=1 | 466opClass=SimdShift 467opLat=1 |
| 468pipelined=true |
|
| 471 472[system.cpu.fuPool.FUList5.opList09] 473type=OpDesc 474eventq_index=0 | 469 470[system.cpu.fuPool.FUList5.opList09] 471type=OpDesc 472eventq_index=0 |
| 475issueLat=1 | |
| 476opClass=SimdShiftAcc 477opLat=1 | 473opClass=SimdShiftAcc 474opLat=1 |
| 475pipelined=true |
|
| 478 479[system.cpu.fuPool.FUList5.opList10] 480type=OpDesc 481eventq_index=0 | 476 477[system.cpu.fuPool.FUList5.opList10] 478type=OpDesc 479eventq_index=0 |
| 482issueLat=1 | |
| 483opClass=SimdSqrt 484opLat=1 | 480opClass=SimdSqrt 481opLat=1 |
| 482pipelined=true |
|
| 485 486[system.cpu.fuPool.FUList5.opList11] 487type=OpDesc 488eventq_index=0 | 483 484[system.cpu.fuPool.FUList5.opList11] 485type=OpDesc 486eventq_index=0 |
| 489issueLat=1 | |
| 490opClass=SimdFloatAdd 491opLat=1 | 487opClass=SimdFloatAdd 488opLat=1 |
| 489pipelined=true |
|
| 492 493[system.cpu.fuPool.FUList5.opList12] 494type=OpDesc 495eventq_index=0 | 490 491[system.cpu.fuPool.FUList5.opList12] 492type=OpDesc 493eventq_index=0 |
| 496issueLat=1 | |
| 497opClass=SimdFloatAlu 498opLat=1 | 494opClass=SimdFloatAlu 495opLat=1 |
| 496pipelined=true |
|
| 499 500[system.cpu.fuPool.FUList5.opList13] 501type=OpDesc 502eventq_index=0 | 497 498[system.cpu.fuPool.FUList5.opList13] 499type=OpDesc 500eventq_index=0 |
| 503issueLat=1 | |
| 504opClass=SimdFloatCmp 505opLat=1 | 501opClass=SimdFloatCmp 502opLat=1 |
| 503pipelined=true |
|
| 506 507[system.cpu.fuPool.FUList5.opList14] 508type=OpDesc 509eventq_index=0 | 504 505[system.cpu.fuPool.FUList5.opList14] 506type=OpDesc 507eventq_index=0 |
| 510issueLat=1 | |
| 511opClass=SimdFloatCvt 512opLat=1 | 508opClass=SimdFloatCvt 509opLat=1 |
| 510pipelined=true |
|
| 513 514[system.cpu.fuPool.FUList5.opList15] 515type=OpDesc 516eventq_index=0 | 511 512[system.cpu.fuPool.FUList5.opList15] 513type=OpDesc 514eventq_index=0 |
| 517issueLat=1 | |
| 518opClass=SimdFloatDiv 519opLat=1 | 515opClass=SimdFloatDiv 516opLat=1 |
| 517pipelined=true |
|
| 520 521[system.cpu.fuPool.FUList5.opList16] 522type=OpDesc 523eventq_index=0 | 518 519[system.cpu.fuPool.FUList5.opList16] 520type=OpDesc 521eventq_index=0 |
| 524issueLat=1 | |
| 525opClass=SimdFloatMisc 526opLat=1 | 522opClass=SimdFloatMisc 523opLat=1 |
| 524pipelined=true |
|
| 527 528[system.cpu.fuPool.FUList5.opList17] 529type=OpDesc 530eventq_index=0 | 525 526[system.cpu.fuPool.FUList5.opList17] 527type=OpDesc 528eventq_index=0 |
| 531issueLat=1 | |
| 532opClass=SimdFloatMult 533opLat=1 | 529opClass=SimdFloatMult 530opLat=1 |
| 531pipelined=true |
|
| 534 535[system.cpu.fuPool.FUList5.opList18] 536type=OpDesc 537eventq_index=0 | 532 533[system.cpu.fuPool.FUList5.opList18] 534type=OpDesc 535eventq_index=0 |
| 538issueLat=1 | |
| 539opClass=SimdFloatMultAcc 540opLat=1 | 536opClass=SimdFloatMultAcc 537opLat=1 |
| 538pipelined=true |
|
| 541 542[system.cpu.fuPool.FUList5.opList19] 543type=OpDesc 544eventq_index=0 | 539 540[system.cpu.fuPool.FUList5.opList19] 541type=OpDesc 542eventq_index=0 |
| 545issueLat=1 | |
| 546opClass=SimdFloatSqrt 547opLat=1 | 543opClass=SimdFloatSqrt 544opLat=1 |
| 545pipelined=true |
|
| 548 549[system.cpu.fuPool.FUList6] 550type=FUDesc 551children=opList 552count=0 553eventq_index=0 554opList=system.cpu.fuPool.FUList6.opList 555 556[system.cpu.fuPool.FUList6.opList] 557type=OpDesc 558eventq_index=0 | 546 547[system.cpu.fuPool.FUList6] 548type=FUDesc 549children=opList 550count=0 551eventq_index=0 552opList=system.cpu.fuPool.FUList6.opList 553 554[system.cpu.fuPool.FUList6.opList] 555type=OpDesc 556eventq_index=0 |
| 559issueLat=1 | |
| 560opClass=MemWrite 561opLat=1 | 557opClass=MemWrite 558opLat=1 |
| 559pipelined=true |
|
| 562 563[system.cpu.fuPool.FUList7] 564type=FUDesc 565children=opList0 opList1 566count=4 567eventq_index=0 568opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 569 570[system.cpu.fuPool.FUList7.opList0] 571type=OpDesc 572eventq_index=0 | 560 561[system.cpu.fuPool.FUList7] 562type=FUDesc 563children=opList0 opList1 564count=4 565eventq_index=0 566opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 567 568[system.cpu.fuPool.FUList7.opList0] 569type=OpDesc 570eventq_index=0 |
| 573issueLat=1 | |
| 574opClass=MemRead 575opLat=1 | 571opClass=MemRead 572opLat=1 |
| 573pipelined=true |
|
| 576 577[system.cpu.fuPool.FUList7.opList1] 578type=OpDesc 579eventq_index=0 | 574 575[system.cpu.fuPool.FUList7.opList1] 576type=OpDesc 577eventq_index=0 |
| 580issueLat=1 | |
| 581opClass=MemWrite 582opLat=1 | 578opClass=MemWrite 579opLat=1 |
| 580pipelined=true |
|
| 583 584[system.cpu.fuPool.FUList8] 585type=FUDesc 586children=opList 587count=1 588eventq_index=0 589opList=system.cpu.fuPool.FUList8.opList 590 591[system.cpu.fuPool.FUList8.opList] 592type=OpDesc 593eventq_index=0 | 581 582[system.cpu.fuPool.FUList8] 583type=FUDesc 584children=opList 585count=1 586eventq_index=0 587opList=system.cpu.fuPool.FUList8.opList 588 589[system.cpu.fuPool.FUList8.opList] 590type=OpDesc 591eventq_index=0 |
| 594issueLat=3 | |
| 595opClass=IprAccess 596opLat=3 | 592opClass=IprAccess 593opLat=3 |
| 594pipelined=false |
|
| 597 598[system.cpu.icache] 599type=BaseCache 600children=tags 601addr_ranges=0:18446744073709551615 602assoc=1 603clk_domain=system.cpu_clk_domain 604demand_mshr_reserve=1 605eventq_index=0 606forward_snoops=true 607hit_latency=2 | 595 596[system.cpu.icache] 597type=BaseCache 598children=tags 599addr_ranges=0:18446744073709551615 600assoc=1 601clk_domain=system.cpu_clk_domain 602demand_mshr_reserve=1 603eventq_index=0 604forward_snoops=true 605hit_latency=2 |
| 608is_top_level=true | 606is_read_only=true |
| 609max_miss_count=0 610mshrs=4 611prefetch_on_access=false 612prefetcher=Null 613response_latency=2 614sequential_access=false 615size=32768 616system=system 617tags=system.cpu.icache.tags 618tgts_per_mshr=20 | 607max_miss_count=0 608mshrs=4 609prefetch_on_access=false 610prefetcher=Null 611response_latency=2 612sequential_access=false 613size=32768 614system=system 615tags=system.cpu.icache.tags 616tgts_per_mshr=20 |
| 619two_queue=false | |
| 620write_buffers=8 621cpu_side=system.cpu.icache_port 622mem_side=system.cpu.toL2Bus.slave[0] 623 624[system.cpu.icache.tags] 625type=LRU 626assoc=1 627block_size=64 --- 37 unchanged lines hidden (view full) --- 665[system.cpu.itb_walker_cache] 666type=BaseCache 667children=tags 668addr_ranges=0:18446744073709551615 669assoc=2 670clk_domain=system.cpu_clk_domain 671demand_mshr_reserve=1 672eventq_index=0 | 617write_buffers=8 618cpu_side=system.cpu.icache_port 619mem_side=system.cpu.toL2Bus.slave[0] 620 621[system.cpu.icache.tags] 622type=LRU 623assoc=1 624block_size=64 --- 37 unchanged lines hidden (view full) --- 662[system.cpu.itb_walker_cache] 663type=BaseCache 664children=tags 665addr_ranges=0:18446744073709551615 666assoc=2 667clk_domain=system.cpu_clk_domain 668demand_mshr_reserve=1 669eventq_index=0 |
| 673forward_snoops=true | 670forward_snoops=false |
| 674hit_latency=2 | 671hit_latency=2 |
| 675is_top_level=true | 672is_read_only=false |
| 676max_miss_count=0 677mshrs=10 678prefetch_on_access=false 679prefetcher=Null 680response_latency=2 681sequential_access=false 682size=1024 683system=system 684tags=system.cpu.itb_walker_cache.tags 685tgts_per_mshr=12 | 673max_miss_count=0 674mshrs=10 675prefetch_on_access=false 676prefetcher=Null 677response_latency=2 678sequential_access=false 679size=1024 680system=system 681tags=system.cpu.itb_walker_cache.tags 682tgts_per_mshr=12 |
| 686two_queue=false | |
| 687write_buffers=8 688cpu_side=system.cpu.itb.walker.port 689mem_side=system.cpu.toL2Bus.slave[2] 690 691[system.cpu.itb_walker_cache.tags] 692type=LRU 693assoc=2 694block_size=64 --- 8 unchanged lines hidden (view full) --- 703children=tags 704addr_ranges=0:18446744073709551615 705assoc=8 706clk_domain=system.cpu_clk_domain 707demand_mshr_reserve=1 708eventq_index=0 709forward_snoops=true 710hit_latency=20 | 683write_buffers=8 684cpu_side=system.cpu.itb.walker.port 685mem_side=system.cpu.toL2Bus.slave[2] 686 687[system.cpu.itb_walker_cache.tags] 688type=LRU 689assoc=2 690block_size=64 --- 8 unchanged lines hidden (view full) --- 699children=tags 700addr_ranges=0:18446744073709551615 701assoc=8 702clk_domain=system.cpu_clk_domain 703demand_mshr_reserve=1 704eventq_index=0 705forward_snoops=true 706hit_latency=20 |
| 711is_top_level=false | 707is_read_only=false |
| 712max_miss_count=0 713mshrs=20 714prefetch_on_access=false 715prefetcher=Null 716response_latency=20 717sequential_access=false 718size=4194304 719system=system 720tags=system.cpu.l2cache.tags 721tgts_per_mshr=12 | 708max_miss_count=0 709mshrs=20 710prefetch_on_access=false 711prefetcher=Null 712response_latency=20 713sequential_access=false 714size=4194304 715system=system 716tags=system.cpu.l2cache.tags 717tgts_per_mshr=12 |
| 722two_queue=false | |
| 723write_buffers=8 724cpu_side=system.cpu.toL2Bus.master[0] 725mem_side=system.membus.slave[2] 726 727[system.cpu.l2cache.tags] 728type=LRU 729assoc=8 730block_size=64 --- 480 unchanged lines hidden (view full) --- 1211children=tags 1212addr_ranges=0:134217727 1213assoc=8 1214clk_domain=system.clk_domain 1215demand_mshr_reserve=1 1216eventq_index=0 1217forward_snoops=false 1218hit_latency=50 | 718write_buffers=8 719cpu_side=system.cpu.toL2Bus.master[0] 720mem_side=system.membus.slave[2] 721 722[system.cpu.l2cache.tags] 723type=LRU 724assoc=8 725block_size=64 --- 480 unchanged lines hidden (view full) --- 1206children=tags 1207addr_ranges=0:134217727 1208assoc=8 1209clk_domain=system.clk_domain 1210demand_mshr_reserve=1 1211eventq_index=0 1212forward_snoops=false 1213hit_latency=50 |
| 1219is_top_level=true | 1214is_read_only=false |
| 1220max_miss_count=0 1221mshrs=20 1222prefetch_on_access=false 1223prefetcher=Null 1224response_latency=50 1225sequential_access=false 1226size=1024 1227system=system 1228tags=system.iocache.tags 1229tgts_per_mshr=12 | 1215max_miss_count=0 1216mshrs=20 1217prefetch_on_access=false 1218prefetcher=Null 1219response_latency=50 1220sequential_access=false 1221size=1024 1222system=system 1223tags=system.iocache.tags 1224tgts_per_mshr=12 |
| 1230two_queue=false | |
| 1231write_buffers=8 1232cpu_side=system.iobus.master[19] 1233mem_side=system.membus.slave[4] 1234 1235[system.iocache.tags] 1236type=LRU 1237assoc=8 1238block_size=64 --- 672 unchanged lines hidden --- | 1225write_buffers=8 1226cpu_side=system.iobus.master[19] 1227mem_side=system.membus.slave[4] 1228 1229[system.iocache.tags] 1230type=LRU 1231assoc=8 1232block_size=64 --- 672 unchanged lines hidden --- |