| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 197 unchanged lines hidden (view full) --- 206children=tags 207addr_ranges=0:18446744073709551615 208assoc=4 209clk_domain=system.cpu_clk_domain 210demand_mshr_reserve=1 211eventq_index=0 212forward_snoops=true 213hit_latency=2 |
| 214is_read_only=false |
| 215max_miss_count=0 216mshrs=4 217prefetch_on_access=false 218prefetcher=Null 219response_latency=2 220sequential_access=false 221size=32768 222system=system 223tags=system.cpu.dcache.tags 224tgts_per_mshr=20 |
| 225write_buffers=8 226cpu_side=system.cpu.dcache_port 227mem_side=system.cpu.toL2Bus.slave[1] 228 229[system.cpu.dcache.tags] 230type=LRU 231assoc=4 232block_size=64 --- 21 unchanged lines hidden (view full) --- 254[system.cpu.dtb_walker_cache] 255type=BaseCache 256children=tags 257addr_ranges=0:18446744073709551615 258assoc=2 259clk_domain=system.cpu_clk_domain 260demand_mshr_reserve=1 261eventq_index=0 |
| 262forward_snoops=false |
| 263hit_latency=2 |
| 264is_read_only=false |
| 265max_miss_count=0 266mshrs=10 267prefetch_on_access=false 268prefetcher=Null 269response_latency=2 270sequential_access=false 271size=1024 272system=system 273tags=system.cpu.dtb_walker_cache.tags 274tgts_per_mshr=12 |
| 275write_buffers=8 276cpu_side=system.cpu.dtb.walker.port 277mem_side=system.cpu.toL2Bus.slave[3] 278 279[system.cpu.dtb_walker_cache.tags] 280type=LRU 281assoc=2 282block_size=64 --- 14 unchanged lines hidden (view full) --- 297children=opList 298count=6 299eventq_index=0 300opList=system.cpu.fuPool.FUList0.opList 301 302[system.cpu.fuPool.FUList0.opList] 303type=OpDesc 304eventq_index=0 |
| 305opClass=IntAlu 306opLat=1 |
| 307pipelined=true |
| 308 309[system.cpu.fuPool.FUList1] 310type=FUDesc 311children=opList0 opList1 312count=2 313eventq_index=0 314opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 315 316[system.cpu.fuPool.FUList1.opList0] 317type=OpDesc 318eventq_index=0 |
| 319opClass=IntMult 320opLat=3 |
| 321pipelined=true |
| 322 323[system.cpu.fuPool.FUList1.opList1] 324type=OpDesc 325eventq_index=0 |
| 326opClass=IntDiv |
| 327opLat=1 328pipelined=false |
| 329 330[system.cpu.fuPool.FUList2] 331type=FUDesc 332children=opList0 opList1 opList2 333count=4 334eventq_index=0 335opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 336 337[system.cpu.fuPool.FUList2.opList0] 338type=OpDesc 339eventq_index=0 |
| 340opClass=FloatAdd 341opLat=2 |
| 342pipelined=true |
| 343 344[system.cpu.fuPool.FUList2.opList1] 345type=OpDesc 346eventq_index=0 |
| 347opClass=FloatCmp 348opLat=2 |
| 349pipelined=true |
| 350 351[system.cpu.fuPool.FUList2.opList2] 352type=OpDesc 353eventq_index=0 |
| 354opClass=FloatCvt 355opLat=2 |
| 356pipelined=true |
| 357 358[system.cpu.fuPool.FUList3] 359type=FUDesc 360children=opList0 opList1 opList2 361count=2 362eventq_index=0 363opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 364 365[system.cpu.fuPool.FUList3.opList0] 366type=OpDesc 367eventq_index=0 |
| 368opClass=FloatMult 369opLat=4 |
| 370pipelined=true |
| 371 372[system.cpu.fuPool.FUList3.opList1] 373type=OpDesc 374eventq_index=0 |
| 375opClass=FloatDiv 376opLat=12 |
| 377pipelined=false |
| 378 379[system.cpu.fuPool.FUList3.opList2] 380type=OpDesc 381eventq_index=0 |
| 382opClass=FloatSqrt 383opLat=24 |
| 384pipelined=false |
| 385 386[system.cpu.fuPool.FUList4] 387type=FUDesc 388children=opList 389count=0 390eventq_index=0 391opList=system.cpu.fuPool.FUList4.opList 392 393[system.cpu.fuPool.FUList4.opList] 394type=OpDesc 395eventq_index=0 |
| 396opClass=MemRead 397opLat=1 |
| 398pipelined=true |
| 399 400[system.cpu.fuPool.FUList5] 401type=FUDesc 402children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 403count=4 404eventq_index=0 405opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 406 407[system.cpu.fuPool.FUList5.opList00] 408type=OpDesc 409eventq_index=0 |
| 410opClass=SimdAdd 411opLat=1 |
| 412pipelined=true |
| 413 414[system.cpu.fuPool.FUList5.opList01] 415type=OpDesc 416eventq_index=0 |
| 417opClass=SimdAddAcc 418opLat=1 |
| 419pipelined=true |
| 420 421[system.cpu.fuPool.FUList5.opList02] 422type=OpDesc 423eventq_index=0 |
| 424opClass=SimdAlu 425opLat=1 |
| 426pipelined=true |
| 427 428[system.cpu.fuPool.FUList5.opList03] 429type=OpDesc 430eventq_index=0 |
| 431opClass=SimdCmp 432opLat=1 |
| 433pipelined=true |
| 434 435[system.cpu.fuPool.FUList5.opList04] 436type=OpDesc 437eventq_index=0 |
| 438opClass=SimdCvt 439opLat=1 |
| 440pipelined=true |
| 441 442[system.cpu.fuPool.FUList5.opList05] 443type=OpDesc 444eventq_index=0 |
| 445opClass=SimdMisc 446opLat=1 |
| 447pipelined=true |
| 448 449[system.cpu.fuPool.FUList5.opList06] 450type=OpDesc 451eventq_index=0 |
| 452opClass=SimdMult 453opLat=1 |
| 454pipelined=true |
| 455 456[system.cpu.fuPool.FUList5.opList07] 457type=OpDesc 458eventq_index=0 |
| 459opClass=SimdMultAcc 460opLat=1 |
| 461pipelined=true |
| 462 463[system.cpu.fuPool.FUList5.opList08] 464type=OpDesc 465eventq_index=0 |
| 466opClass=SimdShift 467opLat=1 |
| 468pipelined=true |
| 469 470[system.cpu.fuPool.FUList5.opList09] 471type=OpDesc 472eventq_index=0 |
| 473opClass=SimdShiftAcc 474opLat=1 |
| 475pipelined=true |
| 476 477[system.cpu.fuPool.FUList5.opList10] 478type=OpDesc 479eventq_index=0 |
| 480opClass=SimdSqrt 481opLat=1 |
| 482pipelined=true |
| 483 484[system.cpu.fuPool.FUList5.opList11] 485type=OpDesc 486eventq_index=0 |
| 487opClass=SimdFloatAdd 488opLat=1 |
| 489pipelined=true |
| 490 491[system.cpu.fuPool.FUList5.opList12] 492type=OpDesc 493eventq_index=0 |
| 494opClass=SimdFloatAlu 495opLat=1 |
| 496pipelined=true |
| 497 498[system.cpu.fuPool.FUList5.opList13] 499type=OpDesc 500eventq_index=0 |
| 501opClass=SimdFloatCmp 502opLat=1 |
| 503pipelined=true |
| 504 505[system.cpu.fuPool.FUList5.opList14] 506type=OpDesc 507eventq_index=0 |
| 508opClass=SimdFloatCvt 509opLat=1 |
| 510pipelined=true |
| 511 512[system.cpu.fuPool.FUList5.opList15] 513type=OpDesc 514eventq_index=0 |
| 515opClass=SimdFloatDiv 516opLat=1 |
| 517pipelined=true |
| 518 519[system.cpu.fuPool.FUList5.opList16] 520type=OpDesc 521eventq_index=0 |
| 522opClass=SimdFloatMisc 523opLat=1 |
| 524pipelined=true |
| 525 526[system.cpu.fuPool.FUList5.opList17] 527type=OpDesc 528eventq_index=0 |
| 529opClass=SimdFloatMult 530opLat=1 |
| 531pipelined=true |
| 532 533[system.cpu.fuPool.FUList5.opList18] 534type=OpDesc 535eventq_index=0 |
| 536opClass=SimdFloatMultAcc 537opLat=1 |
| 538pipelined=true |
| 539 540[system.cpu.fuPool.FUList5.opList19] 541type=OpDesc 542eventq_index=0 |
| 543opClass=SimdFloatSqrt 544opLat=1 |
| 545pipelined=true |
| 546 547[system.cpu.fuPool.FUList6] 548type=FUDesc 549children=opList 550count=0 551eventq_index=0 552opList=system.cpu.fuPool.FUList6.opList 553 554[system.cpu.fuPool.FUList6.opList] 555type=OpDesc 556eventq_index=0 |
| 557opClass=MemWrite 558opLat=1 |
| 559pipelined=true |
| 560 561[system.cpu.fuPool.FUList7] 562type=FUDesc 563children=opList0 opList1 564count=4 565eventq_index=0 566opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 567 568[system.cpu.fuPool.FUList7.opList0] 569type=OpDesc 570eventq_index=0 |
| 571opClass=MemRead 572opLat=1 |
| 573pipelined=true |
| 574 575[system.cpu.fuPool.FUList7.opList1] 576type=OpDesc 577eventq_index=0 |
| 578opClass=MemWrite 579opLat=1 |
| 580pipelined=true |
| 581 582[system.cpu.fuPool.FUList8] 583type=FUDesc 584children=opList 585count=1 586eventq_index=0 587opList=system.cpu.fuPool.FUList8.opList 588 589[system.cpu.fuPool.FUList8.opList] 590type=OpDesc 591eventq_index=0 |
| 592opClass=IprAccess 593opLat=3 |
| 594pipelined=false |
| 595 596[system.cpu.icache] 597type=BaseCache 598children=tags 599addr_ranges=0:18446744073709551615 600assoc=1 601clk_domain=system.cpu_clk_domain 602demand_mshr_reserve=1 603eventq_index=0 604forward_snoops=true 605hit_latency=2 |
| 606is_read_only=true |
| 607max_miss_count=0 608mshrs=4 609prefetch_on_access=false 610prefetcher=Null 611response_latency=2 612sequential_access=false 613size=32768 614system=system 615tags=system.cpu.icache.tags 616tgts_per_mshr=20 |
| 617write_buffers=8 618cpu_side=system.cpu.icache_port 619mem_side=system.cpu.toL2Bus.slave[0] 620 621[system.cpu.icache.tags] 622type=LRU 623assoc=1 624block_size=64 --- 37 unchanged lines hidden (view full) --- 662[system.cpu.itb_walker_cache] 663type=BaseCache 664children=tags 665addr_ranges=0:18446744073709551615 666assoc=2 667clk_domain=system.cpu_clk_domain 668demand_mshr_reserve=1 669eventq_index=0 |
| 670forward_snoops=false |
| 671hit_latency=2 |
| 672is_read_only=false |
| 673max_miss_count=0 674mshrs=10 675prefetch_on_access=false 676prefetcher=Null 677response_latency=2 678sequential_access=false 679size=1024 680system=system 681tags=system.cpu.itb_walker_cache.tags 682tgts_per_mshr=12 |
| 683write_buffers=8 684cpu_side=system.cpu.itb.walker.port 685mem_side=system.cpu.toL2Bus.slave[2] 686 687[system.cpu.itb_walker_cache.tags] 688type=LRU 689assoc=2 690block_size=64 --- 8 unchanged lines hidden (view full) --- 699children=tags 700addr_ranges=0:18446744073709551615 701assoc=8 702clk_domain=system.cpu_clk_domain 703demand_mshr_reserve=1 704eventq_index=0 705forward_snoops=true 706hit_latency=20 |
| 707is_read_only=false |
| 708max_miss_count=0 709mshrs=20 710prefetch_on_access=false 711prefetcher=Null 712response_latency=20 713sequential_access=false 714size=4194304 715system=system 716tags=system.cpu.l2cache.tags 717tgts_per_mshr=12 |
| 718write_buffers=8 719cpu_side=system.cpu.toL2Bus.master[0] 720mem_side=system.membus.slave[2] 721 722[system.cpu.l2cache.tags] 723type=LRU 724assoc=8 725block_size=64 --- 480 unchanged lines hidden (view full) --- 1206children=tags 1207addr_ranges=0:134217727 1208assoc=8 1209clk_domain=system.clk_domain 1210demand_mshr_reserve=1 1211eventq_index=0 1212forward_snoops=false 1213hit_latency=50 |
| 1214is_read_only=false |
| 1215max_miss_count=0 1216mshrs=20 1217prefetch_on_access=false 1218prefetcher=Null 1219response_latency=50 1220sequential_access=false 1221size=1024 1222system=system 1223tags=system.iocache.tags 1224tgts_per_mshr=12 |
| 1225write_buffers=8 1226cpu_side=system.iobus.master[19] 1227mem_side=system.membus.slave[4] 1228 1229[system.iocache.tags] 1230type=LRU 1231assoc=8 1232block_size=64 --- 672 unchanged lines hidden --- |