stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
---|---|
1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 51.820895 # Number of seconds simulated 4sim_ticks 51820894502500 # Number of ticks simulated 5final_tick 51820894502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 51.821889 # Number of seconds simulated 4sim_ticks 51821888787500 # Number of ticks simulated 5final_tick 51821888787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 612269 # Simulator instruction rate (inst/s) 8host_op_rate 719485 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 35448799247 # Simulator tick rate (ticks/s) 10host_mem_usage 680056 # Number of bytes of host memory used 11host_seconds 1461.85 # Real time elapsed on the host 12sim_insts 895045967 # Number of instructions simulated 13sim_ops 1051780871 # Number of ops (including micro ops) simulated | 7host_inst_rate 515124 # Simulator instruction rate (inst/s) 8host_op_rate 605315 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 31054928912 # Simulator tick rate (ticks/s) 10host_mem_usage 676612 # Number of bytes of host memory used 11host_seconds 1668.72 # Real time elapsed on the host 12sim_insts 859596485 # Number of instructions simulated 13sim_ops 1010098639 # Number of ops (including micro ops) simulated |
14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.physmem.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 268032 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 256704 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5200500 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 51306824 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 409600 # Number of bytes read from this memory 22system.physmem.bytes_read::total 57441660 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 5200500 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 5200500 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 78712256 # Number of bytes written to this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 216448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 219200 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5035380 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 42867656 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 394432 # Number of bytes read from this memory 22system.physmem.bytes_read::total 48733116 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 5035380 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 5035380 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 69868992 # Number of bytes written to this memory |
26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory | 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory |
27system.physmem.bytes_written::total 78732836 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 4188 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 4011 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 121665 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 801682 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6400 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 937946 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1229879 # Number of write requests responded to by this memory | 27system.physmem.bytes_written::total 69889572 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 3382 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 3425 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 119085 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 669820 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6163 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 801875 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1091703 # Number of write requests responded to by this memory |
35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory |
36system.physmem.num_writes::total 1232452 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 5172 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 4954 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 100355 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 990080 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7904 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 1108465 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 100355 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 100355 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1518929 # Write bandwidth from this memory (bytes/s) | 36system.physmem.num_writes::total 1094276 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 4177 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 4230 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 97167 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 827211 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7611 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 940396 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 97167 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 97167 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1348253 # Write bandwidth from this memory (bytes/s) |
46system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) | 46system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) |
47system.physmem.bw_write::total 1519326 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1518929 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 5172 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 4954 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 100355 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 990477 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7904 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 2627791 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 937946 # Number of read requests accepted 56system.physmem.writeReqs 1232452 # Number of write requests accepted 57system.physmem.readBursts 937946 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 1232452 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 59993856 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 34688 # Total number of bytes read from write queue 61system.physmem.bytesWritten 78731584 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 57441660 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 78732836 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 542 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one | 47system.physmem.bw_write::total 1348650 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1348253 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 4177 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 4230 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 97167 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 827609 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7611 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 2289046 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 801875 # Number of read requests accepted 56system.physmem.writeReqs 1094276 # Number of write requests accepted 57system.physmem.readBursts 801875 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 1094276 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 51277952 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 42048 # Total number of bytes read from write queue 61system.physmem.bytesWritten 69886912 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 48733116 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 69889572 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 657 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2265 # Number of DRAM write bursts merged with an existing one |
66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
67system.physmem.perBankRdBursts::0 58989 # Per bank write bursts 68system.physmem.perBankRdBursts::1 58919 # Per bank write bursts 69system.physmem.perBankRdBursts::2 58679 # Per bank write bursts 70system.physmem.perBankRdBursts::3 55735 # Per bank write bursts 71system.physmem.perBankRdBursts::4 54249 # Per bank write bursts 72system.physmem.perBankRdBursts::5 59544 # Per bank write bursts 73system.physmem.perBankRdBursts::6 52586 # Per bank write bursts 74system.physmem.perBankRdBursts::7 53926 # Per bank write bursts 75system.physmem.perBankRdBursts::8 52975 # Per bank write bursts 76system.physmem.perBankRdBursts::9 101116 # Per bank write bursts 77system.physmem.perBankRdBursts::10 56481 # Per bank write bursts 78system.physmem.perBankRdBursts::11 59298 # Per bank write bursts 79system.physmem.perBankRdBursts::12 53072 # Per bank write bursts 80system.physmem.perBankRdBursts::13 58564 # Per bank write bursts 81system.physmem.perBankRdBursts::14 50527 # Per bank write bursts 82system.physmem.perBankRdBursts::15 52744 # Per bank write bursts 83system.physmem.perBankWrBursts::0 76908 # Per bank write bursts 84system.physmem.perBankWrBursts::1 78477 # Per bank write bursts 85system.physmem.perBankWrBursts::2 80133 # Per bank write bursts 86system.physmem.perBankWrBursts::3 78953 # Per bank write bursts 87system.physmem.perBankWrBursts::4 75778 # Per bank write bursts 88system.physmem.perBankWrBursts::5 80212 # Per bank write bursts 89system.physmem.perBankWrBursts::6 72590 # Per bank write bursts 90system.physmem.perBankWrBursts::7 74527 # Per bank write bursts 91system.physmem.perBankWrBursts::8 74121 # Per bank write bursts 92system.physmem.perBankWrBursts::9 79665 # Per bank write bursts 93system.physmem.perBankWrBursts::10 76241 # Per bank write bursts 94system.physmem.perBankWrBursts::11 79585 # Per bank write bursts 95system.physmem.perBankWrBursts::12 74881 # Per bank write bursts 96system.physmem.perBankWrBursts::13 79432 # Per bank write bursts 97system.physmem.perBankWrBursts::14 73606 # Per bank write bursts 98system.physmem.perBankWrBursts::15 75072 # Per bank write bursts | 67system.physmem.perBankRdBursts::0 50164 # Per bank write bursts 68system.physmem.perBankRdBursts::1 52640 # Per bank write bursts 69system.physmem.perBankRdBursts::2 46199 # Per bank write bursts 70system.physmem.perBankRdBursts::3 47700 # Per bank write bursts 71system.physmem.perBankRdBursts::4 47678 # Per bank write bursts 72system.physmem.perBankRdBursts::5 54947 # Per bank write bursts 73system.physmem.perBankRdBursts::6 45482 # Per bank write bursts 74system.physmem.perBankRdBursts::7 44174 # Per bank write bursts 75system.physmem.perBankRdBursts::8 47146 # Per bank write bursts 76system.physmem.perBankRdBursts::9 89983 # Per bank write bursts 77system.physmem.perBankRdBursts::10 47048 # Per bank write bursts 78system.physmem.perBankRdBursts::11 49101 # Per bank write bursts 79system.physmem.perBankRdBursts::12 43837 # Per bank write bursts 80system.physmem.perBankRdBursts::13 45399 # Per bank write bursts 81system.physmem.perBankRdBursts::14 43891 # Per bank write bursts 82system.physmem.perBankRdBursts::15 45829 # Per bank write bursts 83system.physmem.perBankWrBursts::0 68109 # Per bank write bursts 84system.physmem.perBankWrBursts::1 72083 # Per bank write bursts 85system.physmem.perBankWrBursts::2 69263 # Per bank write bursts 86system.physmem.perBankWrBursts::3 69948 # Per bank write bursts 87system.physmem.perBankWrBursts::4 67942 # Per bank write bursts 88system.physmem.perBankWrBursts::5 73995 # Per bank write bursts 89system.physmem.perBankWrBursts::6 66206 # Per bank write bursts 90system.physmem.perBankWrBursts::7 65273 # Per bank write bursts 91system.physmem.perBankWrBursts::8 68509 # Per bank write bursts 92system.physmem.perBankWrBursts::9 70672 # Per bank write bursts 93system.physmem.perBankWrBursts::10 68078 # Per bank write bursts 94system.physmem.perBankWrBursts::11 68626 # Per bank write bursts 95system.physmem.perBankWrBursts::12 64922 # Per bank write bursts 96system.physmem.perBankWrBursts::13 66812 # Per bank write bursts 97system.physmem.perBankWrBursts::14 65438 # Per bank write bursts 98system.physmem.perBankWrBursts::15 66107 # Per bank write bursts |
99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
100system.physmem.numWrRetry 41 # Number of times write queue was full causing retry 101system.physmem.totGap 51820891581500 # Total gap between requests | 100system.physmem.numWrRetry 528 # Number of times write queue was full causing retry 101system.physmem.totGap 51821885925500 # Total gap between requests |
102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 43101 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) | 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 43101 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) |
108system.physmem.readPktSize::6 894830 # Read request sizes (log2) | 108system.physmem.readPktSize::6 758759 # Read request sizes (log2) |
109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) | 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) |
115system.physmem.writePktSize::6 1229879 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 903506 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 28089 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 425 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 344 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 490 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 651 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 467 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1235 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 309 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 395 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 169 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 183 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 74 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see | 115system.physmem.writePktSize::6 1091703 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 767795 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 27710 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 516 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 322 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 438 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 573 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 470 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 924 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 568 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 279 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 146 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 101 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see |
137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
163system.physmem.wrQLenPdf::15 33600 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 39104 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 67316 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 70490 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 74148 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 71564 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 70236 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 72767 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 75611 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 72543 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 77682 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 76300 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 72201 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 70498 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 70723 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 68261 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 67880 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 67043 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1360 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 1245 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 1067 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 865 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 685 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 625 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 521 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 296 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 370 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 368 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 334 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 397 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 259 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 230 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 275 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 236 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 236 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 201 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 224 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 255 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 185 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 167 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 563432 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 246.214486 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 148.153142 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 287.290760 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 250076 44.38% 44.38% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 147098 26.11% 70.49% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 49891 8.85% 79.35% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 26994 4.79% 84.14% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 18337 3.25% 87.39% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 11939 2.12% 89.51% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 8931 1.59% 91.10% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 7653 1.36% 92.45% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 42513 7.55% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 563432 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 66023 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 14.197810 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 125.335088 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 66020 100.00% 100.00% # Reads before turning the bus around for writes | 163system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 34869 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 57710 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 61714 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 64549 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 61650 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 60651 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 63213 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 64819 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 63587 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 67440 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 65819 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 62330 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 60766 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 60977 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 60110 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 59233 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 58775 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2370 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 1929 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 1663 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 1421 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 1205 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 1130 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 853 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 815 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 823 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 783 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 742 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 685 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 731 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 732 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 794 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 858 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 921 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 715 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 761 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 715 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 977 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 1097 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 1188 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 1099 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 664 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 1235 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 2021 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 1432 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 593 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 1157 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 494449 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 245.049629 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 147.402723 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 288.016754 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 219085 44.31% 44.31% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 131738 26.64% 70.95% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 43693 8.84% 79.79% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 22796 4.61% 84.40% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 15362 3.11% 87.51% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 9595 1.94% 89.45% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 7428 1.50% 90.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 5929 1.20% 92.15% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 38823 7.85% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 494449 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 57195 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 14.008130 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 134.294281 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 57192 99.99% 99.99% # Reads before turning the bus around for writes |
230system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes | 230system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes |
233system.physmem.rdPerTurnAround::total 66023 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 66023 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 18.632613 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 18.082710 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 6.894597 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-23 62853 95.20% 95.20% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-31 1132 1.71% 96.91% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-39 1165 1.76% 98.68% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-47 145 0.22% 98.90% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::48-55 61 0.09% 98.99% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::56-63 50 0.08% 99.07% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-71 451 0.68% 99.75% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::72-79 71 0.11% 99.86% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::80-87 27 0.04% 99.90% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::88-95 7 0.01% 99.91% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::96-103 4 0.01% 99.91% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::104-111 11 0.02% 99.93% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::112-119 4 0.01% 99.94% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::128-135 20 0.03% 99.97% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::136-143 9 0.01% 99.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::168-175 1 0.00% 99.99% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::184-191 2 0.00% 99.99% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::192-199 4 0.01% 100.00% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::total 66023 # Writes before turning the bus around for reads 260system.physmem.totQLat 12434281516 # Total ticks spent queuing 261system.physmem.totMemAccLat 30010606516 # Total ticks spent from burst creation until serviced by the DRAM 262system.physmem.totBusLat 4687020000 # Total ticks spent in databus transfers 263system.physmem.avgQLat 13264.59 # Average queueing delay per DRAM burst | 233system.physmem.rdPerTurnAround::total 57195 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 57195 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 19.092281 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 18.359425 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 8.356307 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-19 44576 77.94% 77.94% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20-23 9441 16.51% 94.44% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::24-27 730 1.28% 95.72% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::28-31 284 0.50% 96.22% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32-35 871 1.52% 97.74% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::36-39 293 0.51% 98.25% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-43 48 0.08% 98.34% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::44-47 36 0.06% 98.40% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::48-51 15 0.03% 98.42% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::52-55 17 0.03% 98.45% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::56-59 14 0.02% 98.48% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::60-63 33 0.06% 98.54% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::64-67 518 0.91% 99.44% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::68-71 69 0.12% 99.56% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::72-75 50 0.09% 99.65% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::76-79 58 0.10% 99.75% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::80-83 36 0.06% 99.81% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::84-87 1 0.00% 99.82% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 3 0.01% 99.82% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 3 0.01% 99.83% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::96-99 1 0.00% 99.83% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::100-103 5 0.01% 99.84% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::104-107 2 0.00% 99.84% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::108-111 17 0.03% 99.87% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::112-115 4 0.01% 99.88% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::116-119 1 0.00% 99.88% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::124-127 5 0.01% 99.89% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::160-163 2 0.00% 99.97% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::188-191 3 0.01% 99.99% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::192-195 5 0.01% 100.00% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::total 57195 # Writes before turning the bus around for reads 281system.physmem.totQLat 29399013585 # Total ticks spent queuing 282system.physmem.totMemAccLat 44421851085 # Total ticks spent from burst creation until serviced by the DRAM 283system.physmem.totBusLat 4006090000 # Total ticks spent in databus transfers 284system.physmem.avgQLat 36692.90 # Average queueing delay per DRAM burst |
264system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 285system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
265system.physmem.avgMemAccLat 32014.59 # Average memory access latency per DRAM burst 266system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s 267system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s 268system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s 269system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s | 286system.physmem.avgMemAccLat 55442.90 # Average memory access latency per DRAM burst 287system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s 288system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s 289system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s 290system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s |
270system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 271system.physmem.busUtil 0.02 # Data bus utilization in percentage 272system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 273system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 274system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 291system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 292system.physmem.busUtil 0.02 # Data bus utilization in percentage 293system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 294system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 295system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
275system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing 276system.physmem.readRowHits 702833 # Number of row buffer hits during reads 277system.physmem.writeRowHits 901319 # Number of row buffer hits during writes 278system.physmem.readRowHitRate 74.98 # Row buffer hit rate for reads 279system.physmem.writeRowHitRate 73.27 # Row buffer hit rate for writes 280system.physmem.avgGap 23876216.06 # Average gap between requests 281system.physmem.pageHitRate 74.01 # Row buffer hit rate, read and write combined 282system.physmem_0.actEnergy 2165373000 # Energy for activate commands per rank (pJ) 283system.physmem_0.preEnergy 1181503125 # Energy for precharge commands per rank (pJ) 284system.physmem_0.readEnergy 3530451600 # Energy for read commands per rank (pJ) 285system.physmem_0.writeEnergy 4001905440 # Energy for write commands per rank (pJ) 286system.physmem_0.refreshEnergy 3384688532160 # Energy for refresh commands per rank (pJ) 287system.physmem_0.actBackEnergy 1300349435715 # Energy for active background per rank (pJ) 288system.physmem_0.preBackEnergy 29951875881000 # Energy for precharge background per rank (pJ) 289system.physmem_0.totalEnergy 34647793082040 # Total energy per rank (pJ) 290system.physmem_0.averagePower 668.606693 # Core power per rank (mW) 291system.physmem_0.memoryStateTime::IDLE 49827060150280 # Time in different power states 292system.physmem_0.memoryStateTime::REF 1730413360000 # Time in different power states 293system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 294system.physmem_0.memoryStateTime::ACT 263420580720 # Time in different power states 295system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 296system.physmem_1.actEnergy 2094172920 # Energy for activate commands per rank (pJ) 297system.physmem_1.preEnergy 1142653875 # Energy for precharge commands per rank (pJ) 298system.physmem_1.readEnergy 3781260600 # Energy for read commands per rank (pJ) 299system.physmem_1.writeEnergy 3969667440 # Energy for write commands per rank (pJ) 300system.physmem_1.refreshEnergy 3384688532160 # Energy for refresh commands per rank (pJ) 301system.physmem_1.actBackEnergy 1299689474040 # Energy for active background per rank (pJ) 302system.physmem_1.preBackEnergy 29952454794750 # Energy for precharge background per rank (pJ) 303system.physmem_1.totalEnergy 34647820555785 # Total energy per rank (pJ) 304system.physmem_1.averagePower 668.607223 # Core power per rank (mW) 305system.physmem_1.memoryStateTime::IDLE 49827979372630 # Time in different power states 306system.physmem_1.memoryStateTime::REF 1730413360000 # Time in different power states 307system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 308system.physmem_1.memoryStateTime::ACT 262496082370 # Time in different power states 309system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 310system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 296system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing 297system.physmem.readRowHits 600273 # Number of row buffer hits during reads 298system.physmem.writeRowHits 798478 # Number of row buffer hits during writes 299system.physmem.readRowHitRate 74.92 # Row buffer hit rate for reads 300system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes 301system.physmem.avgGap 27330041.71 # Average gap between requests 302system.physmem.pageHitRate 73.88 # Row buffer hit rate, read and write combined 303system.physmem_0.actEnergy 1812881700 # Energy for activate commands per rank (pJ) 304system.physmem_0.preEnergy 963565680 # Energy for precharge commands per rank (pJ) 305system.physmem_0.readEnergy 2777345760 # Energy for read commands per rank (pJ) 306system.physmem_0.writeEnergy 2885715180 # Energy for write commands per rank (pJ) 307system.physmem_0.refreshEnergy 48801801360.000008 # Energy for refresh commands per rank (pJ) 308system.physmem_0.actBackEnergy 38319920670 # Energy for active background per rank (pJ) 309system.physmem_0.preBackEnergy 3025839840 # Energy for precharge background per rank (pJ) 310system.physmem_0.actPowerDownEnergy 94040362440 # Energy for active power-down per rank (pJ) 311system.physmem_0.prePowerDownEnergy 72590911200 # Energy for precharge power-down per rank (pJ) 312system.physmem_0.selfRefreshEnergy 12330316288695 # Energy for self refresh per rank (pJ) 313system.physmem_0.totalEnergy 12595556394525 # Total energy per rank (pJ) 314system.physmem_0.averagePower 243.054753 # Core power per rank (mW) 315system.physmem_0.totalIdleTime 51729925726993 # Total Idle time Per DRAM Rank 316system.physmem_0.memoryStateTime::IDLE 5744734750 # Time in different power states 317system.physmem_0.memoryStateTime::REF 20754236000 # Time in different power states 318system.physmem_0.memoryStateTime::SREF 51334657894500 # Time in different power states 319system.physmem_0.memoryStateTime::PRE_PDN 189038733198 # Time in different power states 320system.physmem_0.memoryStateTime::ACT 65464048007 # Time in different power states 321system.physmem_0.memoryStateTime::ACT_PDN 206229141045 # Time in different power states 322system.physmem_1.actEnergy 1717491300 # Energy for activate commands per rank (pJ) 323system.physmem_1.preEnergy 912868275 # Energy for precharge commands per rank (pJ) 324system.physmem_1.readEnergy 2943350760 # Energy for read commands per rank (pJ) 325system.physmem_1.writeEnergy 2814436080 # Energy for write commands per rank (pJ) 326system.physmem_1.refreshEnergy 46544843280.000008 # Energy for refresh commands per rank (pJ) 327system.physmem_1.actBackEnergy 38176673400 # Energy for active background per rank (pJ) 328system.physmem_1.preBackEnergy 2758502400 # Energy for precharge background per rank (pJ) 329system.physmem_1.actPowerDownEnergy 87988375470 # Energy for active power-down per rank (pJ) 330system.physmem_1.prePowerDownEnergy 69794301120 # Energy for precharge power-down per rank (pJ) 331system.physmem_1.selfRefreshEnergy 12334956932460 # Energy for self refresh per rank (pJ) 332system.physmem_1.totalEnergy 12588629106345 # Total energy per rank (pJ) 333system.physmem_1.averagePower 242.921078 # Core power per rank (mW) 334system.physmem_1.totalIdleTime 51730316233255 # Total Idle time Per DRAM Rank 335system.physmem_1.memoryStateTime::IDLE 5091528742 # Time in different power states 336system.physmem_1.memoryStateTime::REF 19793960000 # Time in different power states 337system.physmem_1.memoryStateTime::SREF 51356223942250 # Time in different power states 338system.physmem_1.memoryStateTime::PRE_PDN 181755962683 # Time in different power states 339system.physmem_1.memoryStateTime::ACT 66066776003 # Time in different power states 340system.physmem_1.memoryStateTime::ACT_PDN 192956617822 # Time in different power states 341system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
311system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 312system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 313system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 314system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 315system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 316system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 317system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 318system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 319system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 325system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 326system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) | 342system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 347system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 349system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 350system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) |
327system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 328system.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 329system.bridge.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 358system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 359system.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 360system.bridge.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
330system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 331system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 332system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 333system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 334system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 335system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 336system.cpu_clk_domain.clock 500 # Clock period in ticks | 361system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 362system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 363system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 364system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 365system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 366system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 367system.cpu_clk_domain.clock 500 # Clock period in ticks |
337system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 368system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
338system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 339system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 340system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 341system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 342system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 359system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 360system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 361system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 362system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 363system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 364system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 365system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 366system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 369system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 390system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 391system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 392system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 393system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 394system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 395system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 396system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 397system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
367system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 368system.cpu.dtb.walker.walks 214264 # Table walker walks requested 369system.cpu.dtb.walker.walksLong 214264 # Table walker walks initiated with long descriptors 370system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17030 # Level at which table walker walks with long descriptors terminate 371system.cpu.dtb.walker.walksLongTerminationLevel::Level3 164948 # Level at which table walker walks with long descriptors terminate 372system.cpu.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting 373system.cpu.dtb.walker.walkWaitTime::samples 214243 # Table walker wait (enqueue to first request) latency 374system.cpu.dtb.walker.walkWaitTime::mean 0.140028 # Table walker wait (enqueue to first request) latency 375system.cpu.dtb.walker.walkWaitTime::stdev 46.737844 # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkWaitTime::0-2047 214241 100.00% 100.00% # Table walker wait (enqueue to first request) latency | 398system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 399system.cpu.dtb.walker.walks 195978 # Table walker walks requested 400system.cpu.dtb.walker.walksLong 195978 # Table walker walks initiated with long descriptors 401system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13491 # Level at which table walker walks with long descriptors terminate 402system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152311 # Level at which table walker walks with long descriptors terminate 403system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting 404system.cpu.dtb.walker.walkWaitTime::samples 195958 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkWaitTime::mean 0.153094 # Table walker wait (enqueue to first request) latency 406system.cpu.dtb.walker.walkWaitTime::stdev 48.869782 # Table walker wait (enqueue to first request) latency 407system.cpu.dtb.walker.walkWaitTime::0-2047 195956 100.00% 100.00% # Table walker wait (enqueue to first request) latency |
377system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency | 408system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 409system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
379system.cpu.dtb.walker.walkWaitTime::total 214243 # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkCompletionTime::samples 181999 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::mean 24181.814186 # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::gmean 20419.578200 # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::stdev 15522.698406 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::0-65535 180089 98.95% 98.95% # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::65536-131071 1633 0.90% 99.85% # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walkCompletionTime::131072-196607 118 0.06% 99.91% # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::196608-262143 77 0.04% 99.95% # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::262144-327679 52 0.03% 99.98% # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 100.00% # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::total 181999 # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walksPending::samples 4819875556 # Table walker pending requests distribution 394system.cpu.dtb.walker.walksPending::mean 1.150179 # Table walker pending requests distribution 395system.cpu.dtb.walker.walksPending::0 -723841796 -15.02% -15.02% # Table walker pending requests distribution 396system.cpu.dtb.walker.walksPending::1 5543717352 115.02% 100.00% # Table walker pending requests distribution 397system.cpu.dtb.walker.walksPending::total 4819875556 # Table walker pending requests distribution 398system.cpu.dtb.walker.walkPageSizes::4K 164949 90.64% 90.64% # Table walker page sizes translated 399system.cpu.dtb.walker.walkPageSizes::2M 17030 9.36% 100.00% # Table walker page sizes translated 400system.cpu.dtb.walker.walkPageSizes::total 181979 # Table walker page sizes translated 401system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 214264 # Table walker requests started/completed, data/inst | 410system.cpu.dtb.walker.walkWaitTime::total 195958 # Table walker wait (enqueue to first request) latency 411system.cpu.dtb.walker.walkCompletionTime::samples 165822 # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::mean 23748.733582 # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::gmean 19720.854851 # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::stdev 19654.042010 # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::0-65535 164137 98.98% 98.98% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::65536-131071 1390 0.84% 99.82% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::131072-196607 75 0.05% 99.87% # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walkCompletionTime::196608-262143 54 0.03% 99.90% # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::262144-327679 79 0.05% 99.95% # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 99.96% # Table walker service (enqueue to completion) latency 421system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.96% # Table walker service (enqueue to completion) latency 422system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.97% # Table walker service (enqueue to completion) latency 423system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency 424system.cpu.dtb.walker.walkCompletionTime::589824-655359 53 0.03% 100.00% # Table walker service (enqueue to completion) latency 425system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 426system.cpu.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 427system.cpu.dtb.walker.walkCompletionTime::total 165822 # Table walker service (enqueue to completion) latency 428system.cpu.dtb.walker.walksPending::samples -2782551036 # Table walker pending requests distribution 429system.cpu.dtb.walker.walksPending::mean 0.846086 # Table walker pending requests distribution 430system.cpu.dtb.walker.walksPending::stdev 0.360866 # Table walker pending requests distribution 431system.cpu.dtb.walker.walksPending::0 -428273296 15.39% 15.39% # Table walker pending requests distribution 432system.cpu.dtb.walker.walksPending::1 -2354277740 84.61% 100.00% # Table walker pending requests distribution 433system.cpu.dtb.walker.walksPending::total -2782551036 # Table walker pending requests distribution 434system.cpu.dtb.walker.walkPageSizes::4K 152312 91.86% 91.86% # Table walker page sizes translated 435system.cpu.dtb.walker.walkPageSizes::2M 13491 8.14% 100.00% # Table walker page sizes translated 436system.cpu.dtb.walker.walkPageSizes::total 165803 # Table walker page sizes translated 437system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 195978 # Table walker requests started/completed, data/inst |
402system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 438system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
403system.cpu.dtb.walker.walkRequestOrigin_Requested::total 214264 # Table walker requests started/completed, data/inst 404system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 181979 # Table walker requests started/completed, data/inst | 439system.cpu.dtb.walker.walkRequestOrigin_Requested::total 195978 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 165803 # Table walker requests started/completed, data/inst |
405system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 441system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
406system.cpu.dtb.walker.walkRequestOrigin_Completed::total 181979 # Table walker requests started/completed, data/inst 407system.cpu.dtb.walker.walkRequestOrigin::total 396243 # Table walker requests started/completed, data/inst | 442system.cpu.dtb.walker.walkRequestOrigin_Completed::total 165803 # Table walker requests started/completed, data/inst 443system.cpu.dtb.walker.walkRequestOrigin::total 361781 # Table walker requests started/completed, data/inst |
408system.cpu.dtb.inst_hits 0 # ITB inst hits 409system.cpu.dtb.inst_misses 0 # ITB inst misses | 444system.cpu.dtb.inst_hits 0 # ITB inst hits 445system.cpu.dtb.inst_misses 0 # ITB inst misses |
410system.cpu.dtb.read_hits 168009449 # DTB read hits 411system.cpu.dtb.read_misses 157878 # DTB read misses 412system.cpu.dtb.write_hits 152852610 # DTB write hits 413system.cpu.dtb.write_misses 56386 # DTB write misses | 446system.cpu.dtb.read_hits 161602593 # DTB read hits 447system.cpu.dtb.read_misses 145506 # DTB read misses 448system.cpu.dtb.write_hits 146806893 # DTB write hits 449system.cpu.dtb.write_misses 50472 # DTB write misses |
414system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 415system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 450system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 451system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
416system.cpu.dtb.flush_tlb_mva_asid 43022 # Number of times TLB was flushed by MVA & ASID 417system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 418system.cpu.dtb.flush_entries 75936 # Number of entries that have been flushed from TLB | 452system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID 453system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID 454system.cpu.dtb.flush_entries 72949 # Number of entries that have been flushed from TLB |
419system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 455system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
420system.cpu.dtb.prefetch_faults 8201 # Number of TLB faults due to prefetch | 456system.cpu.dtb.prefetch_faults 7287 # Number of TLB faults due to prefetch |
421system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 457system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
422system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions 423system.cpu.dtb.read_accesses 168167327 # DTB read accesses 424system.cpu.dtb.write_accesses 152908996 # DTB write accesses | 458system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions 459system.cpu.dtb.read_accesses 161748099 # DTB read accesses 460system.cpu.dtb.write_accesses 146857365 # DTB write accesses |
425system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 461system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
426system.cpu.dtb.hits 320862059 # DTB hits 427system.cpu.dtb.misses 214264 # DTB misses 428system.cpu.dtb.accesses 321076323 # DTB accesses 429system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 462system.cpu.dtb.hits 308409486 # DTB hits 463system.cpu.dtb.misses 195978 # DTB misses 464system.cpu.dtb.accesses 308605464 # DTB accesses 465system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
430system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 433system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 434system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 435system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 436system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 437system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 451system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 452system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 453system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 454system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 455system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 456system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 457system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 458system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 466system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 472system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 473system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 487system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 488system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 489system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 490system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 491system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 492system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 493system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 494system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
459system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 460system.cpu.itb.walker.walks 122945 # Table walker walks requested 461system.cpu.itb.walker.walksLong 122945 # Table walker walks initiated with long descriptors | 495system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 496system.cpu.itb.walker.walks 120718 # Table walker walks requested 497system.cpu.itb.walker.walksLong 120718 # Table walker walks initiated with long descriptors |
462system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate | 498system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate |
463system.cpu.itb.walker.walksLongTerminationLevel::Level3 110624 # Level at which table walker walks with long descriptors terminate 464system.cpu.itb.walker.walkWaitTime::samples 122945 # Table walker wait (enqueue to first request) latency 465system.cpu.itb.walker.walkWaitTime::0 122945 100.00% 100.00% # Table walker wait (enqueue to first request) latency 466system.cpu.itb.walker.walkWaitTime::total 122945 # Table walker wait (enqueue to first request) latency 467system.cpu.itb.walker.walkCompletionTime::samples 111743 # Table walker service (enqueue to completion) latency 468system.cpu.itb.walker.walkCompletionTime::mean 27331.219853 # Table walker service (enqueue to completion) latency 469system.cpu.itb.walker.walkCompletionTime::gmean 23493.082733 # Table walker service (enqueue to completion) latency 470system.cpu.itb.walker.walkCompletionTime::stdev 18310.002732 # Table walker service (enqueue to completion) latency 471system.cpu.itb.walker.walkCompletionTime::0-65535 109587 98.07% 98.07% # Table walker service (enqueue to completion) latency 472system.cpu.itb.walker.walkCompletionTime::65536-131071 1865 1.67% 99.74% # Table walker service (enqueue to completion) latency 473system.cpu.itb.walker.walkCompletionTime::131072-196607 133 0.12% 99.86% # Table walker service (enqueue to completion) latency 474system.cpu.itb.walker.walkCompletionTime::196608-262143 84 0.08% 99.93% # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.04% 99.97% # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::327680-393215 22 0.02% 99.99% # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::total 111743 # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walksPending::samples -850328296 # Table walker pending requests distribution 483system.cpu.itb.walker.walksPending::0 -850328296 100.00% 100.00% # Table walker pending requests distribution 484system.cpu.itb.walker.walksPending::total -850328296 # Table walker pending requests distribution 485system.cpu.itb.walker.walkPageSizes::4K 110624 99.00% 99.00% # Table walker page sizes translated 486system.cpu.itb.walker.walkPageSizes::2M 1119 1.00% 100.00% # Table walker page sizes translated 487system.cpu.itb.walker.walkPageSizes::total 111743 # Table walker page sizes translated | 499system.cpu.itb.walker.walksLongTerminationLevel::Level3 108838 # Level at which table walker walks with long descriptors terminate 500system.cpu.itb.walker.walkWaitTime::samples 120718 # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::0 120718 100.00% 100.00% # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::total 120718 # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkCompletionTime::samples 109957 # Table walker service (enqueue to completion) latency 504system.cpu.itb.walker.walkCompletionTime::mean 27485.576180 # Table walker service (enqueue to completion) latency 505system.cpu.itb.walker.walkCompletionTime::gmean 23297.926209 # Table walker service (enqueue to completion) latency 506system.cpu.itb.walker.walkCompletionTime::stdev 24382.701456 # Table walker service (enqueue to completion) latency 507system.cpu.itb.walker.walkCompletionTime::0-65535 107960 98.18% 98.18% # Table walker service (enqueue to completion) latency 508system.cpu.itb.walker.walkCompletionTime::65536-131071 1664 1.51% 99.70% # Table walker service (enqueue to completion) latency 509system.cpu.itb.walker.walkCompletionTime::131072-196607 68 0.06% 99.76% # Table walker service (enqueue to completion) latency 510system.cpu.itb.walker.walkCompletionTime::196608-262143 86 0.08% 99.84% # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walkCompletionTime::262144-327679 74 0.07% 99.90% # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.93% # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.93% # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::589824-655359 76 0.07% 100.00% # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::total 109957 # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution 518system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution 519system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution 520system.cpu.itb.walker.walkPageSizes::4K 108838 98.98% 98.98% # Table walker page sizes translated 521system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated 522system.cpu.itb.walker.walkPageSizes::total 109957 # Table walker page sizes translated |
488system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 523system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
489system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122945 # Table walker requests started/completed, data/inst 490system.cpu.itb.walker.walkRequestOrigin_Requested::total 122945 # Table walker requests started/completed, data/inst | 524system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120718 # Table walker requests started/completed, data/inst 525system.cpu.itb.walker.walkRequestOrigin_Requested::total 120718 # Table walker requests started/completed, data/inst |
491system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 526system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
492system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111743 # Table walker requests started/completed, data/inst 493system.cpu.itb.walker.walkRequestOrigin_Completed::total 111743 # Table walker requests started/completed, data/inst 494system.cpu.itb.walker.walkRequestOrigin::total 234688 # Table walker requests started/completed, data/inst 495system.cpu.itb.inst_hits 895597591 # ITB inst hits 496system.cpu.itb.inst_misses 122945 # ITB inst misses | 527system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109957 # Table walker requests started/completed, data/inst 528system.cpu.itb.walker.walkRequestOrigin_Completed::total 109957 # Table walker requests started/completed, data/inst 529system.cpu.itb.walker.walkRequestOrigin::total 230675 # Table walker requests started/completed, data/inst 530system.cpu.itb.inst_hits 860126625 # ITB inst hits 531system.cpu.itb.inst_misses 120718 # ITB inst misses |
497system.cpu.itb.read_hits 0 # DTB read hits 498system.cpu.itb.read_misses 0 # DTB read misses 499system.cpu.itb.write_hits 0 # DTB write hits 500system.cpu.itb.write_misses 0 # DTB write misses 501system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 502system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 532system.cpu.itb.read_hits 0 # DTB read hits 533system.cpu.itb.read_misses 0 # DTB read misses 534system.cpu.itb.write_hits 0 # DTB write hits 535system.cpu.itb.write_misses 0 # DTB write misses 536system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 537system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
503system.cpu.itb.flush_tlb_mva_asid 43022 # Number of times TLB was flushed by MVA & ASID 504system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 505system.cpu.itb.flush_entries 53957 # Number of entries that have been flushed from TLB | 538system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID 539system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID 540system.cpu.itb.flush_entries 52157 # Number of entries that have been flushed from TLB |
506system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 507system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 508system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 509system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 510system.cpu.itb.read_accesses 0 # DTB read accesses 511system.cpu.itb.write_accesses 0 # DTB write accesses | 541system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 542system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 543system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 544system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 545system.cpu.itb.read_accesses 0 # DTB read accesses 546system.cpu.itb.write_accesses 0 # DTB write accesses |
512system.cpu.itb.inst_accesses 895720536 # ITB inst accesses 513system.cpu.itb.hits 895597591 # DTB hits 514system.cpu.itb.misses 122945 # DTB misses 515system.cpu.itb.accesses 895720536 # DTB accesses 516system.cpu.numPwrStateTransitions 32698 # Number of power state transitions 517system.cpu.pwrStateClkGateDist::samples 16349 # Distribution of time spent in the clock gated state 518system.cpu.pwrStateClkGateDist::mean 3072754762.549147 # Distribution of time spent in the clock gated state 519system.cpu.pwrStateClkGateDist::stdev 59826711358.002258 # Distribution of time spent in the clock gated state 520system.cpu.pwrStateClkGateDist::underflows 7060 43.18% 43.18% # Distribution of time spent in the clock gated state 521system.cpu.pwrStateClkGateDist::1000-5e+10 9253 56.60% 99.78% # Distribution of time spent in the clock gated state 522system.cpu.pwrStateClkGateDist::5e+10-1e+11 6 0.04% 99.82% # Distribution of time spent in the clock gated state | 547system.cpu.itb.inst_accesses 860247343 # ITB inst accesses 548system.cpu.itb.hits 860126625 # DTB hits 549system.cpu.itb.misses 120718 # DTB misses 550system.cpu.itb.accesses 860247343 # DTB accesses 551system.cpu.numPwrStateTransitions 32322 # Number of power state transitions 552system.cpu.pwrStateClkGateDist::samples 16161 # Distribution of time spent in the clock gated state 553system.cpu.pwrStateClkGateDist::mean 3111677574.020791 # Distribution of time spent in the clock gated state 554system.cpu.pwrStateClkGateDist::stdev 60407510991.245888 # Distribution of time spent in the clock gated state 555system.cpu.pwrStateClkGateDist::underflows 6870 42.51% 42.51% # Distribution of time spent in the clock gated state 556system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state 557system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state |
523system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 524system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 525system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state | 558system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 559system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 560system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state |
526system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 527system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 528system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 529system.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state | 561system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 562system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 563system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 564system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state |
530system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 531system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 532system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 565system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
533system.cpu.pwrStateClkGateDist::max_value 1988775178432 # Distribution of time spent in the clock gated state 534system.cpu.pwrStateClkGateDist::total 16349 # Distribution of time spent in the clock gated state 535system.cpu.pwrStateResidencyTicks::ON 1584426889584 # Cumulative time (in ticks) in various power states 536system.cpu.pwrStateResidencyTicks::CLK_GATED 50236467612916 # Cumulative time (in ticks) in various power states 537system.cpu.numCycles 103641789005 # number of cpu cycles simulated | 568system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state 569system.cpu.pwrStateClkGateDist::total 16161 # Distribution of time spent in the clock gated state 570system.cpu.pwrStateResidencyTicks::ON 1534067513750 # Cumulative time (in ticks) in various power states 571system.cpu.pwrStateResidencyTicks::CLK_GATED 50287821273750 # Cumulative time (in ticks) in various power states 572system.cpu.numCycles 103643777575 # number of cpu cycles simulated |
538system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 539system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 540system.cpu.kern.inst.arm 0 # number of arm instructions executed | 573system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 574system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 575system.cpu.kern.inst.arm 0 # number of arm instructions executed |
541system.cpu.kern.inst.quiesce 16349 # number of quiesce instructions executed 542system.cpu.committedInsts 895045967 # Number of instructions committed 543system.cpu.committedOps 1051780871 # Number of ops (including micro ops) committed 544system.cpu.num_int_alu_accesses 965574423 # Number of integer alu accesses 545system.cpu.num_fp_alu_accesses 894989 # Number of float alu accesses 546system.cpu.num_func_calls 52935800 # number of times a function call or return occured 547system.cpu.num_conditional_control_insts 136802593 # number of instructions that are conditional controls 548system.cpu.num_int_insts 965574423 # number of integer instructions 549system.cpu.num_fp_insts 894989 # number of float instructions 550system.cpu.num_int_register_reads 1409614532 # number of times the integer registers were read 551system.cpu.num_int_register_writes 766141547 # number of times the integer registers were written 552system.cpu.num_fp_register_reads 1442074 # number of times the floating registers were read 553system.cpu.num_fp_register_writes 760100 # number of times the floating registers were written 554system.cpu.num_cc_register_reads 235678872 # number of times the CC registers were read 555system.cpu.num_cc_register_writes 235085086 # number of times the CC registers were written 556system.cpu.num_mem_refs 320845878 # number of memory refs 557system.cpu.num_load_insts 168002679 # Number of load instructions 558system.cpu.num_store_insts 152843199 # Number of store instructions 559system.cpu.num_idle_cycles 100472935225.830063 # Number of idle cycles 560system.cpu.num_busy_cycles 3168853779.169939 # Number of busy cycles 561system.cpu.not_idle_fraction 0.030575 # Percentage of non-idle cycles 562system.cpu.idle_fraction 0.969425 # Percentage of idle cycles 563system.cpu.Branches 199903261 # Number of branches fetched | 576system.cpu.kern.inst.quiesce 16161 # number of quiesce instructions executed 577system.cpu.committedInsts 859596485 # Number of instructions committed 578system.cpu.committedOps 1010098639 # Number of ops (including micro ops) committed 579system.cpu.num_int_alu_accesses 927989339 # Number of integer alu accesses 580system.cpu.num_fp_alu_accesses 896850 # Number of float alu accesses 581system.cpu.num_func_calls 51273640 # number of times a function call or return occured 582system.cpu.num_conditional_control_insts 130821573 # number of instructions that are conditional controls 583system.cpu.num_int_insts 927989339 # number of integer instructions 584system.cpu.num_fp_insts 896850 # number of float instructions 585system.cpu.num_int_register_reads 1348541336 # number of times the integer registers were read 586system.cpu.num_int_register_writes 735865236 # number of times the integer registers were written 587system.cpu.num_fp_register_reads 1446705 # number of times the floating registers were read 588system.cpu.num_fp_register_writes 758956 # number of times the floating registers were written 589system.cpu.num_cc_register_reads 224361660 # number of times the CC registers were read 590system.cpu.num_cc_register_writes 223761478 # number of times the CC registers were written 591system.cpu.num_mem_refs 308390268 # number of memory refs 592system.cpu.num_load_insts 161593947 # Number of load instructions 593system.cpu.num_store_insts 146796321 # Number of store instructions 594system.cpu.num_idle_cycles 100575642547.498062 # Number of idle cycles 595system.cpu.num_busy_cycles 3068135027.501941 # Number of busy cycles 596system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles 597system.cpu.idle_fraction 0.970397 # Percentage of idle cycles 598system.cpu.Branches 191892206 # Number of branches fetched |
564system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction | 599system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction |
565system.cpu.op_class::IntAlu 729096517 69.28% 69.28% # Class of executed instruction 566system.cpu.op_class::IntMult 2224980 0.21% 69.49% # Class of executed instruction 567system.cpu.op_class::IntDiv 97778 0.01% 69.50% # Class of executed instruction 568system.cpu.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 569system.cpu.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 570system.cpu.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 571system.cpu.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 572system.cpu.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 573system.cpu.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction 574system.cpu.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction 575system.cpu.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction 576system.cpu.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction 577system.cpu.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction 578system.cpu.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction 579system.cpu.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction 580system.cpu.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction 581system.cpu.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction 582system.cpu.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction 583system.cpu.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction 584system.cpu.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction 585system.cpu.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction 586system.cpu.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction 587system.cpu.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction 588system.cpu.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction 589system.cpu.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction 590system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.51% # Class of executed instruction 591system.cpu.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 592system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 593system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 594system.cpu.op_class::MemRead 168002679 15.96% 85.48% # Class of executed instruction 595system.cpu.op_class::MemWrite 152843199 14.52% 100.00% # Class of executed instruction | 600system.cpu.op_class::IntAlu 699904687 69.25% 69.25% # Class of executed instruction 601system.cpu.op_class::IntMult 2167959 0.21% 69.47% # Class of executed instruction 602system.cpu.op_class::IntDiv 97409 0.01% 69.48% # Class of executed instruction 603system.cpu.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction 604system.cpu.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction 605system.cpu.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction 606system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction 607system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction 608system.cpu.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction 609system.cpu.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction 610system.cpu.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction 611system.cpu.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction 612system.cpu.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction 613system.cpu.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction 614system.cpu.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction 615system.cpu.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction 616system.cpu.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction 617system.cpu.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction 618system.cpu.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction 619system.cpu.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction 620system.cpu.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction 621system.cpu.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction 622system.cpu.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction 623system.cpu.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction 624system.cpu.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction 625system.cpu.op_class::SimdFloatMisc 111537 0.01% 69.49% # Class of executed instruction 626system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction 627system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction 628system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction 629system.cpu.op_class::MemRead 161593947 15.99% 85.48% # Class of executed instruction 630system.cpu.op_class::MemWrite 146796321 14.52% 100.00% # Class of executed instruction |
596system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 597system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 631system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 632system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
598system.cpu.op_class::total 1052375619 # Class of executed instruction 599system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 600system.cpu.dcache.tags.replacements 10244350 # number of replacements 601system.cpu.dcache.tags.tagsinuse 511.965651 # Cycle average of tags in use 602system.cpu.dcache.tags.total_refs 310416272 # Total number of references to valid blocks. 603system.cpu.dcache.tags.sampled_refs 10244862 # Sample count of references to valid blocks. 604system.cpu.dcache.tags.avg_refs 30.299703 # Average number of references to valid blocks. 605system.cpu.dcache.tags.warmup_cycle 3504161500 # Cycle when the warmup percentage was hit. 606system.cpu.dcache.tags.occ_blocks::cpu.data 511.965651 # Average occupied blocks per requestor 607system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy 608system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy | 633system.cpu.op_class::total 1010671903 # Class of executed instruction 634system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 635system.cpu.dcache.tags.replacements 9712865 # number of replacements 636system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use 637system.cpu.dcache.tags.total_refs 298498000 # Total number of references to valid blocks. 638system.cpu.dcache.tags.sampled_refs 9713377 # Sample count of references to valid blocks. 639system.cpu.dcache.tags.avg_refs 30.730610 # Average number of references to valid blocks. 640system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit. 641system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor 642system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy 643system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy |
609system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 644system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
610system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id 613system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 645system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 646system.cpu.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id 647system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 648system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
614system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 649system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
615system.cpu.dcache.tags.tag_accesses 1293353364 # Number of tag accesses 616system.cpu.dcache.tags.data_accesses 1293353364 # Number of data accesses 617system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 618system.cpu.dcache.ReadReq_hits::cpu.data 156944978 # number of ReadReq hits 619system.cpu.dcache.ReadReq_hits::total 156944978 # number of ReadReq hits 620system.cpu.dcache.WriteReq_hits::cpu.data 145025968 # number of WriteReq hits 621system.cpu.dcache.WriteReq_hits::total 145025968 # number of WriteReq hits 622system.cpu.dcache.SoftPFReq_hits::cpu.data 395817 # number of SoftPFReq hits 623system.cpu.dcache.SoftPFReq_hits::total 395817 # number of SoftPFReq hits 624system.cpu.dcache.WriteLineReq_hits::cpu.data 335163 # number of WriteLineReq hits 625system.cpu.dcache.WriteLineReq_hits::total 335163 # number of WriteLineReq hits 626system.cpu.dcache.LoadLockedReq_hits::cpu.data 3689072 # number of LoadLockedReq hits 627system.cpu.dcache.LoadLockedReq_hits::total 3689072 # number of LoadLockedReq hits 628system.cpu.dcache.StoreCondReq_hits::cpu.data 3994801 # number of StoreCondReq hits 629system.cpu.dcache.StoreCondReq_hits::total 3994801 # number of StoreCondReq hits 630system.cpu.dcache.demand_hits::cpu.data 302306109 # number of demand (read+write) hits 631system.cpu.dcache.demand_hits::total 302306109 # number of demand (read+write) hits 632system.cpu.dcache.overall_hits::cpu.data 302701926 # number of overall hits 633system.cpu.dcache.overall_hits::total 302701926 # number of overall hits 634system.cpu.dcache.ReadReq_misses::cpu.data 5326710 # number of ReadReq misses 635system.cpu.dcache.ReadReq_misses::total 5326710 # number of ReadReq misses 636system.cpu.dcache.WriteReq_misses::cpu.data 2212553 # number of WriteReq misses 637system.cpu.dcache.WriteReq_misses::total 2212553 # number of WriteReq misses 638system.cpu.dcache.SoftPFReq_misses::cpu.data 1311764 # number of SoftPFReq misses 639system.cpu.dcache.SoftPFReq_misses::total 1311764 # number of SoftPFReq misses 640system.cpu.dcache.WriteLineReq_misses::cpu.data 1232866 # number of WriteLineReq misses 641system.cpu.dcache.WriteLineReq_misses::total 1232866 # number of WriteLineReq misses 642system.cpu.dcache.LoadLockedReq_misses::cpu.data 307422 # number of LoadLockedReq misses 643system.cpu.dcache.LoadLockedReq_misses::total 307422 # number of LoadLockedReq misses 644system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses 645system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses 646system.cpu.dcache.demand_misses::cpu.data 8772129 # number of demand (read+write) misses 647system.cpu.dcache.demand_misses::total 8772129 # number of demand (read+write) misses 648system.cpu.dcache.overall_misses::cpu.data 10083893 # number of overall misses 649system.cpu.dcache.overall_misses::total 10083893 # number of overall misses 650system.cpu.dcache.ReadReq_miss_latency::cpu.data 84631439000 # number of ReadReq miss cycles 651system.cpu.dcache.ReadReq_miss_latency::total 84631439000 # number of ReadReq miss cycles 652system.cpu.dcache.WriteReq_miss_latency::cpu.data 66820707500 # number of WriteReq miss cycles 653system.cpu.dcache.WriteReq_miss_latency::total 66820707500 # number of WriteReq miss cycles 654system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 25293878500 # number of WriteLineReq miss cycles 655system.cpu.dcache.WriteLineReq_miss_latency::total 25293878500 # number of WriteLineReq miss cycles 656system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4522600000 # number of LoadLockedReq miss cycles 657system.cpu.dcache.LoadLockedReq_miss_latency::total 4522600000 # number of LoadLockedReq miss cycles 658system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 197000 # number of StoreCondReq miss cycles 659system.cpu.dcache.StoreCondReq_miss_latency::total 197000 # number of StoreCondReq miss cycles 660system.cpu.dcache.demand_miss_latency::cpu.data 176746025000 # number of demand (read+write) miss cycles 661system.cpu.dcache.demand_miss_latency::total 176746025000 # number of demand (read+write) miss cycles 662system.cpu.dcache.overall_miss_latency::cpu.data 176746025000 # number of overall miss cycles 663system.cpu.dcache.overall_miss_latency::total 176746025000 # number of overall miss cycles 664system.cpu.dcache.ReadReq_accesses::cpu.data 162271688 # number of ReadReq accesses(hits+misses) 665system.cpu.dcache.ReadReq_accesses::total 162271688 # number of ReadReq accesses(hits+misses) 666system.cpu.dcache.WriteReq_accesses::cpu.data 147238521 # number of WriteReq accesses(hits+misses) 667system.cpu.dcache.WriteReq_accesses::total 147238521 # number of WriteReq accesses(hits+misses) 668system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707581 # number of SoftPFReq accesses(hits+misses) 669system.cpu.dcache.SoftPFReq_accesses::total 1707581 # number of SoftPFReq accesses(hits+misses) 670system.cpu.dcache.WriteLineReq_accesses::cpu.data 1568029 # number of WriteLineReq accesses(hits+misses) 671system.cpu.dcache.WriteLineReq_accesses::total 1568029 # number of WriteLineReq accesses(hits+misses) 672system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3996494 # number of LoadLockedReq accesses(hits+misses) 673system.cpu.dcache.LoadLockedReq_accesses::total 3996494 # number of LoadLockedReq accesses(hits+misses) 674system.cpu.dcache.StoreCondReq_accesses::cpu.data 3994804 # number of StoreCondReq accesses(hits+misses) 675system.cpu.dcache.StoreCondReq_accesses::total 3994804 # number of StoreCondReq accesses(hits+misses) 676system.cpu.dcache.demand_accesses::cpu.data 311078238 # number of demand (read+write) accesses 677system.cpu.dcache.demand_accesses::total 311078238 # number of demand (read+write) accesses 678system.cpu.dcache.overall_accesses::cpu.data 312785819 # number of overall (read+write) accesses 679system.cpu.dcache.overall_accesses::total 312785819 # number of overall (read+write) accesses 680system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032826 # miss rate for ReadReq accesses 681system.cpu.dcache.ReadReq_miss_rate::total 0.032826 # miss rate for ReadReq accesses 682system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015027 # miss rate for WriteReq accesses 683system.cpu.dcache.WriteReq_miss_rate::total 0.015027 # miss rate for WriteReq accesses 684system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.768200 # miss rate for SoftPFReq accesses 685system.cpu.dcache.SoftPFReq_miss_rate::total 0.768200 # miss rate for SoftPFReq accesses 686system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786252 # miss rate for WriteLineReq accesses 687system.cpu.dcache.WriteLineReq_miss_rate::total 0.786252 # miss rate for WriteLineReq accesses 688system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076923 # miss rate for LoadLockedReq accesses 689system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses | 650system.cpu.dcache.tags.tag_accesses 1243014374 # Number of tag accesses 651system.cpu.dcache.tags.data_accesses 1243014374 # Number of data accesses 652system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 653system.cpu.dcache.ReadReq_hits::cpu.data 151150245 # number of ReadReq hits 654system.cpu.dcache.ReadReq_hits::total 151150245 # number of ReadReq hits 655system.cpu.dcache.WriteReq_hits::cpu.data 139360023 # number of WriteReq hits 656system.cpu.dcache.WriteReq_hits::total 139360023 # number of WriteReq hits 657system.cpu.dcache.SoftPFReq_hits::cpu.data 383359 # number of SoftPFReq hits 658system.cpu.dcache.SoftPFReq_hits::total 383359 # number of SoftPFReq hits 659system.cpu.dcache.WriteLineReq_hits::cpu.data 333234 # number of WriteLineReq hits 660system.cpu.dcache.WriteLineReq_hits::total 333234 # number of WriteLineReq hits 661system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475622 # number of LoadLockedReq hits 662system.cpu.dcache.LoadLockedReq_hits::total 3475622 # number of LoadLockedReq hits 663system.cpu.dcache.StoreCondReq_hits::cpu.data 3766718 # number of StoreCondReq hits 664system.cpu.dcache.StoreCondReq_hits::total 3766718 # number of StoreCondReq hits 665system.cpu.dcache.demand_hits::cpu.data 290843502 # number of demand (read+write) hits 666system.cpu.dcache.demand_hits::total 290843502 # number of demand (read+write) hits 667system.cpu.dcache.overall_hits::cpu.data 291226861 # number of overall hits 668system.cpu.dcache.overall_hits::total 291226861 # number of overall hits 669system.cpu.dcache.ReadReq_misses::cpu.data 5063029 # number of ReadReq misses 670system.cpu.dcache.ReadReq_misses::total 5063029 # number of ReadReq misses 671system.cpu.dcache.WriteReq_misses::cpu.data 2070213 # number of WriteReq misses 672system.cpu.dcache.WriteReq_misses::total 2070213 # number of WriteReq misses 673system.cpu.dcache.SoftPFReq_misses::cpu.data 1203887 # number of SoftPFReq misses 674system.cpu.dcache.SoftPFReq_misses::total 1203887 # number of SoftPFReq misses 675system.cpu.dcache.WriteLineReq_misses::cpu.data 1226147 # number of WriteLineReq misses 676system.cpu.dcache.WriteLineReq_misses::total 1226147 # number of WriteLineReq misses 677system.cpu.dcache.LoadLockedReq_misses::cpu.data 292765 # number of LoadLockedReq misses 678system.cpu.dcache.LoadLockedReq_misses::total 292765 # number of LoadLockedReq misses 679system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 680system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 681system.cpu.dcache.demand_misses::cpu.data 8359389 # number of demand (read+write) misses 682system.cpu.dcache.demand_misses::total 8359389 # number of demand (read+write) misses 683system.cpu.dcache.overall_misses::cpu.data 9563276 # number of overall misses 684system.cpu.dcache.overall_misses::total 9563276 # number of overall misses 685system.cpu.dcache.ReadReq_miss_latency::cpu.data 86479051000 # number of ReadReq miss cycles 686system.cpu.dcache.ReadReq_miss_latency::total 86479051000 # number of ReadReq miss cycles 687system.cpu.dcache.WriteReq_miss_latency::cpu.data 64029512000 # number of WriteReq miss cycles 688system.cpu.dcache.WriteReq_miss_latency::total 64029512000 # number of WriteReq miss cycles 689system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24965286000 # number of WriteLineReq miss cycles 690system.cpu.dcache.WriteLineReq_miss_latency::total 24965286000 # number of WriteLineReq miss cycles 691system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4461300000 # number of LoadLockedReq miss cycles 692system.cpu.dcache.LoadLockedReq_miss_latency::total 4461300000 # number of LoadLockedReq miss cycles 693system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167500 # number of StoreCondReq miss cycles 694system.cpu.dcache.StoreCondReq_miss_latency::total 167500 # number of StoreCondReq miss cycles 695system.cpu.dcache.demand_miss_latency::cpu.data 175473849000 # number of demand (read+write) miss cycles 696system.cpu.dcache.demand_miss_latency::total 175473849000 # number of demand (read+write) miss cycles 697system.cpu.dcache.overall_miss_latency::cpu.data 175473849000 # number of overall miss cycles 698system.cpu.dcache.overall_miss_latency::total 175473849000 # number of overall miss cycles 699system.cpu.dcache.ReadReq_accesses::cpu.data 156213274 # number of ReadReq accesses(hits+misses) 700system.cpu.dcache.ReadReq_accesses::total 156213274 # number of ReadReq accesses(hits+misses) 701system.cpu.dcache.WriteReq_accesses::cpu.data 141430236 # number of WriteReq accesses(hits+misses) 702system.cpu.dcache.WriteReq_accesses::total 141430236 # number of WriteReq accesses(hits+misses) 703system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587246 # number of SoftPFReq accesses(hits+misses) 704system.cpu.dcache.SoftPFReq_accesses::total 1587246 # number of SoftPFReq accesses(hits+misses) 705system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559381 # number of WriteLineReq accesses(hits+misses) 706system.cpu.dcache.WriteLineReq_accesses::total 1559381 # number of WriteLineReq accesses(hits+misses) 707system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768387 # number of LoadLockedReq accesses(hits+misses) 708system.cpu.dcache.LoadLockedReq_accesses::total 3768387 # number of LoadLockedReq accesses(hits+misses) 709system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766720 # number of StoreCondReq accesses(hits+misses) 710system.cpu.dcache.StoreCondReq_accesses::total 3766720 # number of StoreCondReq accesses(hits+misses) 711system.cpu.dcache.demand_accesses::cpu.data 299202891 # number of demand (read+write) accesses 712system.cpu.dcache.demand_accesses::total 299202891 # number of demand (read+write) accesses 713system.cpu.dcache.overall_accesses::cpu.data 300790137 # number of overall (read+write) accesses 714system.cpu.dcache.overall_accesses::total 300790137 # number of overall (read+write) accesses 715system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032411 # miss rate for ReadReq accesses 716system.cpu.dcache.ReadReq_miss_rate::total 0.032411 # miss rate for ReadReq accesses 717system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014638 # miss rate for WriteReq accesses 718system.cpu.dcache.WriteReq_miss_rate::total 0.014638 # miss rate for WriteReq accesses 719system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758475 # miss rate for SoftPFReq accesses 720system.cpu.dcache.SoftPFReq_miss_rate::total 0.758475 # miss rate for SoftPFReq accesses 721system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786304 # miss rate for WriteLineReq accesses 722system.cpu.dcache.WriteLineReq_miss_rate::total 0.786304 # miss rate for WriteLineReq accesses 723system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077690 # miss rate for LoadLockedReq accesses 724system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077690 # miss rate for LoadLockedReq accesses |
690system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 691system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses | 725system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 726system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses |
692system.cpu.dcache.demand_miss_rate::cpu.data 0.028199 # miss rate for demand accesses 693system.cpu.dcache.demand_miss_rate::total 0.028199 # miss rate for demand accesses 694system.cpu.dcache.overall_miss_rate::cpu.data 0.032239 # miss rate for overall accesses 695system.cpu.dcache.overall_miss_rate::total 0.032239 # miss rate for overall accesses 696system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15888.125879 # average ReadReq miss latency 697system.cpu.dcache.ReadReq_avg_miss_latency::total 15888.125879 # average ReadReq miss latency 698system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30200.726265 # average WriteReq miss latency 699system.cpu.dcache.WriteReq_avg_miss_latency::total 30200.726265 # average WriteReq miss latency 700system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20516.324159 # average WriteLineReq miss latency 701system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20516.324159 # average WriteLineReq miss latency 702system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14711.373942 # average LoadLockedReq miss latency 703system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14711.373942 # average LoadLockedReq miss latency 704system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 65666.666667 # average StoreCondReq miss latency 705system.cpu.dcache.StoreCondReq_avg_miss_latency::total 65666.666667 # average StoreCondReq miss latency 706system.cpu.dcache.demand_avg_miss_latency::cpu.data 20148.589356 # average overall miss latency 707system.cpu.dcache.demand_avg_miss_latency::total 20148.589356 # average overall miss latency 708system.cpu.dcache.overall_avg_miss_latency::cpu.data 17527.558553 # average overall miss latency 709system.cpu.dcache.overall_avg_miss_latency::total 17527.558553 # average overall miss latency | 727system.cpu.dcache.demand_miss_rate::cpu.data 0.027939 # miss rate for demand accesses 728system.cpu.dcache.demand_miss_rate::total 0.027939 # miss rate for demand accesses 729system.cpu.dcache.overall_miss_rate::cpu.data 0.031794 # miss rate for overall accesses 730system.cpu.dcache.overall_miss_rate::total 0.031794 # miss rate for overall accesses 731system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17080.496873 # average ReadReq miss latency 732system.cpu.dcache.ReadReq_avg_miss_latency::total 17080.496873 # average ReadReq miss latency 733system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30928.948857 # average WriteReq miss latency 734system.cpu.dcache.WriteReq_avg_miss_latency::total 30928.948857 # average WriteReq miss latency 735system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20360.760985 # average WriteLineReq miss latency 736system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20360.760985 # average WriteLineReq miss latency 737system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15238.501870 # average LoadLockedReq miss latency 738system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15238.501870 # average LoadLockedReq miss latency 739system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency 740system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency 741system.cpu.dcache.demand_avg_miss_latency::cpu.data 20991.229024 # average overall miss latency 742system.cpu.dcache.demand_avg_miss_latency::total 20991.229024 # average overall miss latency 743system.cpu.dcache.overall_avg_miss_latency::cpu.data 18348.717427 # average overall miss latency 744system.cpu.dcache.overall_avg_miss_latency::total 18348.717427 # average overall miss latency |
710system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 711system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 712system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 713system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 714system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 715system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 745system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 746system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 747system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 748system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 749system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 750system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
716system.cpu.dcache.writebacks::writebacks 7906430 # number of writebacks 717system.cpu.dcache.writebacks::total 7906430 # number of writebacks 718system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21920 # number of ReadReq MSHR hits 719system.cpu.dcache.ReadReq_mshr_hits::total 21920 # number of ReadReq MSHR hits 720system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21246 # number of WriteReq MSHR hits 721system.cpu.dcache.WriteReq_mshr_hits::total 21246 # number of WriteReq MSHR hits 722system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70972 # number of LoadLockedReq MSHR hits 723system.cpu.dcache.LoadLockedReq_mshr_hits::total 70972 # number of LoadLockedReq MSHR hits 724system.cpu.dcache.demand_mshr_hits::cpu.data 43166 # number of demand (read+write) MSHR hits 725system.cpu.dcache.demand_mshr_hits::total 43166 # number of demand (read+write) MSHR hits 726system.cpu.dcache.overall_mshr_hits::cpu.data 43166 # number of overall MSHR hits 727system.cpu.dcache.overall_mshr_hits::total 43166 # number of overall MSHR hits 728system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5304790 # number of ReadReq MSHR misses 729system.cpu.dcache.ReadReq_mshr_misses::total 5304790 # number of ReadReq MSHR misses 730system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2191307 # number of WriteReq MSHR misses 731system.cpu.dcache.WriteReq_mshr_misses::total 2191307 # number of WriteReq MSHR misses 732system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1309953 # number of SoftPFReq MSHR misses 733system.cpu.dcache.SoftPFReq_mshr_misses::total 1309953 # number of SoftPFReq MSHR misses 734system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1232866 # number of WriteLineReq MSHR misses 735system.cpu.dcache.WriteLineReq_mshr_misses::total 1232866 # number of WriteLineReq MSHR misses 736system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 236450 # number of LoadLockedReq MSHR misses 737system.cpu.dcache.LoadLockedReq_mshr_misses::total 236450 # number of LoadLockedReq MSHR misses 738system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses 739system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses 740system.cpu.dcache.demand_mshr_misses::cpu.data 8728963 # number of demand (read+write) MSHR misses 741system.cpu.dcache.demand_mshr_misses::total 8728963 # number of demand (read+write) MSHR misses 742system.cpu.dcache.overall_mshr_misses::cpu.data 10038916 # number of overall MSHR misses 743system.cpu.dcache.overall_mshr_misses::total 10038916 # number of overall MSHR misses | 751system.cpu.dcache.writebacks::writebacks 7498102 # number of writebacks 752system.cpu.dcache.writebacks::total 7498102 # number of writebacks 753system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21612 # number of ReadReq MSHR hits 754system.cpu.dcache.ReadReq_mshr_hits::total 21612 # number of ReadReq MSHR hits 755system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21289 # number of WriteReq MSHR hits 756system.cpu.dcache.WriteReq_mshr_hits::total 21289 # number of WriteReq MSHR hits 757system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70591 # number of LoadLockedReq MSHR hits 758system.cpu.dcache.LoadLockedReq_mshr_hits::total 70591 # number of LoadLockedReq MSHR hits 759system.cpu.dcache.demand_mshr_hits::cpu.data 42901 # number of demand (read+write) MSHR hits 760system.cpu.dcache.demand_mshr_hits::total 42901 # number of demand (read+write) MSHR hits 761system.cpu.dcache.overall_mshr_hits::cpu.data 42901 # number of overall MSHR hits 762system.cpu.dcache.overall_mshr_hits::total 42901 # number of overall MSHR hits 763system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5041417 # number of ReadReq MSHR misses 764system.cpu.dcache.ReadReq_mshr_misses::total 5041417 # number of ReadReq MSHR misses 765system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2048924 # number of WriteReq MSHR misses 766system.cpu.dcache.WriteReq_mshr_misses::total 2048924 # number of WriteReq MSHR misses 767system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203533 # number of SoftPFReq MSHR misses 768system.cpu.dcache.SoftPFReq_mshr_misses::total 1203533 # number of SoftPFReq MSHR misses 769system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226147 # number of WriteLineReq MSHR misses 770system.cpu.dcache.WriteLineReq_mshr_misses::total 1226147 # number of WriteLineReq MSHR misses 771system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222174 # number of LoadLockedReq MSHR misses 772system.cpu.dcache.LoadLockedReq_mshr_misses::total 222174 # number of LoadLockedReq MSHR misses 773system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 774system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 775system.cpu.dcache.demand_mshr_misses::cpu.data 8316488 # number of demand (read+write) MSHR misses 776system.cpu.dcache.demand_mshr_misses::total 8316488 # number of demand (read+write) MSHR misses 777system.cpu.dcache.overall_mshr_misses::cpu.data 9520021 # number of overall MSHR misses 778system.cpu.dcache.overall_mshr_misses::total 9520021 # number of overall MSHR misses |
744system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 745system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable 746system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 747system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 748system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 749system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses | 779system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 780system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable 781system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 782system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 783system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 784system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses |
750system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78748278500 # number of ReadReq MSHR miss cycles 751system.cpu.dcache.ReadReq_mshr_miss_latency::total 78748278500 # number of ReadReq MSHR miss cycles 752system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63964841000 # number of WriteReq MSHR miss cycles 753system.cpu.dcache.WriteReq_mshr_miss_latency::total 63964841000 # number of WriteReq MSHR miss cycles 754system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21083631000 # number of SoftPFReq MSHR miss cycles 755system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21083631000 # number of SoftPFReq MSHR miss cycles 756system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 24061012500 # number of WriteLineReq MSHR miss cycles 757system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 24061012500 # number of WriteLineReq MSHR miss cycles 758system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3160913500 # number of LoadLockedReq MSHR miss cycles 759system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3160913500 # number of LoadLockedReq MSHR miss cycles 760system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 194000 # number of StoreCondReq MSHR miss cycles 761system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles 762system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166774132000 # number of demand (read+write) MSHR miss cycles 763system.cpu.dcache.demand_mshr_miss_latency::total 166774132000 # number of demand (read+write) MSHR miss cycles 764system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187857763000 # number of overall MSHR miss cycles 765system.cpu.dcache.overall_mshr_miss_latency::total 187857763000 # number of overall MSHR miss cycles 766system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6233075000 # number of ReadReq MSHR uncacheable cycles 767system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6233075000 # number of ReadReq MSHR uncacheable cycles 768system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6233075000 # number of overall MSHR uncacheable cycles 769system.cpu.dcache.overall_mshr_uncacheable_latency::total 6233075000 # number of overall MSHR uncacheable cycles 770system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032691 # mshr miss rate for ReadReq accesses 771system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032691 # mshr miss rate for ReadReq accesses 772system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014883 # mshr miss rate for WriteReq accesses 773system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014883 # mshr miss rate for WriteReq accesses 774system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.767140 # mshr miss rate for SoftPFReq accesses 775system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.767140 # mshr miss rate for SoftPFReq accesses 776system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786252 # mshr miss rate for WriteLineReq accesses 777system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786252 # mshr miss rate for WriteLineReq accesses 778system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059164 # mshr miss rate for LoadLockedReq accesses 779system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses | 785system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80551413000 # number of ReadReq MSHR miss cycles 786system.cpu.dcache.ReadReq_mshr_miss_latency::total 80551413000 # number of ReadReq MSHR miss cycles 787system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61232027000 # number of WriteReq MSHR miss cycles 788system.cpu.dcache.WriteReq_mshr_miss_latency::total 61232027000 # number of WriteReq MSHR miss cycles 789system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21569596000 # number of SoftPFReq MSHR miss cycles 790system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21569596000 # number of SoftPFReq MSHR miss cycles 791system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23739139000 # number of WriteLineReq MSHR miss cycles 792system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23739139000 # number of WriteLineReq MSHR miss cycles 793system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3061958500 # number of LoadLockedReq MSHR miss cycles 794system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3061958500 # number of LoadLockedReq MSHR miss cycles 795system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles 796system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles 797system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165522579000 # number of demand (read+write) MSHR miss cycles 798system.cpu.dcache.demand_mshr_miss_latency::total 165522579000 # number of demand (read+write) MSHR miss cycles 799system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187092175000 # number of overall MSHR miss cycles 800system.cpu.dcache.overall_mshr_miss_latency::total 187092175000 # number of overall MSHR miss cycles 801system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858000 # number of ReadReq MSHR uncacheable cycles 802system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858000 # number of ReadReq MSHR uncacheable cycles 803system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858000 # number of overall MSHR uncacheable cycles 804system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858000 # number of overall MSHR uncacheable cycles 805system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032273 # mshr miss rate for ReadReq accesses 806system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032273 # mshr miss rate for ReadReq accesses 807system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014487 # mshr miss rate for WriteReq accesses 808system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014487 # mshr miss rate for WriteReq accesses 809system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758252 # mshr miss rate for SoftPFReq accesses 810system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758252 # mshr miss rate for SoftPFReq accesses 811system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786304 # mshr miss rate for WriteLineReq accesses 812system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786304 # mshr miss rate for WriteLineReq accesses 813system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058957 # mshr miss rate for LoadLockedReq accesses 814system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058957 # mshr miss rate for LoadLockedReq accesses |
780system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 781system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses | 815system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 816system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses |
782system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028060 # mshr miss rate for demand accesses 783system.cpu.dcache.demand_mshr_miss_rate::total 0.028060 # mshr miss rate for demand accesses 784system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032095 # mshr miss rate for overall accesses 785system.cpu.dcache.overall_mshr_miss_rate::total 0.032095 # mshr miss rate for overall accesses 786system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14844.749462 # average ReadReq mshr miss latency 787system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14844.749462 # average ReadReq mshr miss latency 788system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29190.269095 # average WriteReq mshr miss latency 789system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29190.269095 # average WriteReq mshr miss latency 790system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16094.952262 # average SoftPFReq mshr miss latency 791system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16094.952262 # average SoftPFReq mshr miss latency 792system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19516.324159 # average WriteLineReq mshr miss latency 793system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19516.324159 # average WriteLineReq mshr miss latency 794system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13368.211038 # average LoadLockedReq mshr miss latency 795system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13368.211038 # average LoadLockedReq mshr miss latency 796system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 64666.666667 # average StoreCondReq mshr miss latency 797system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667 # average StoreCondReq mshr miss latency 798system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19105.835596 # average overall mshr miss latency 799system.cpu.dcache.demand_avg_mshr_miss_latency::total 19105.835596 # average overall mshr miss latency 800system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18712.952972 # average overall mshr miss latency 801system.cpu.dcache.overall_avg_mshr_miss_latency::total 18712.952972 # average overall mshr miss latency 802system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184924.790838 # average ReadReq mshr uncacheable latency 803system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184924.790838 # average ReadReq mshr uncacheable latency 804system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92456.909339 # average overall mshr uncacheable latency 805system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92456.909339 # average overall mshr uncacheable latency 806system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 807system.cpu.icache.tags.replacements 13792548 # number of replacements 808system.cpu.icache.tags.tagsinuse 511.891104 # Cycle average of tags in use 809system.cpu.icache.tags.total_refs 881804526 # Total number of references to valid blocks. 810system.cpu.icache.tags.sampled_refs 13793060 # Sample count of references to valid blocks. 811system.cpu.icache.tags.avg_refs 63.931030 # Average number of references to valid blocks. 812system.cpu.icache.tags.warmup_cycle 31603903500 # Cycle when the warmup percentage was hit. 813system.cpu.icache.tags.occ_blocks::cpu.inst 511.891104 # Average occupied blocks per requestor 814system.cpu.icache.tags.occ_percent::cpu.inst 0.999787 # Average percentage of cache occupancy 815system.cpu.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy | 817system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses 818system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses 819system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031650 # mshr miss rate for overall accesses 820system.cpu.dcache.overall_mshr_miss_rate::total 0.031650 # mshr miss rate for overall accesses 821system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15977.931006 # average ReadReq mshr miss latency 822system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15977.931006 # average ReadReq mshr miss latency 823system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29884.967427 # average WriteReq mshr miss latency 824system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29884.967427 # average WriteReq mshr miss latency 825system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17921.898278 # average SoftPFReq mshr miss latency 826system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17921.898278 # average SoftPFReq mshr miss latency 827system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19360.760985 # average WriteLineReq mshr miss latency 828system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19360.760985 # average WriteLineReq mshr miss latency 829system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13781.803901 # average LoadLockedReq mshr miss latency 830system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13781.803901 # average LoadLockedReq mshr miss latency 831system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency 832system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency 833system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.942083 # average overall mshr miss latency 834system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.942083 # average overall mshr miss latency 835system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.496040 # average overall mshr miss latency 836system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.496040 # average overall mshr miss latency 837system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.352816 # average ReadReq mshr uncacheable latency 838system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.352816 # average ReadReq mshr uncacheable latency 839system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.690519 # average overall mshr uncacheable latency 840system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.690519 # average overall mshr uncacheable latency 841system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 842system.cpu.icache.tags.replacements 13489644 # number of replacements 843system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use 844system.cpu.icache.tags.total_refs 846636464 # Total number of references to valid blocks. 845system.cpu.icache.tags.sampled_refs 13490156 # Sample count of references to valid blocks. 846system.cpu.icache.tags.avg_refs 62.759576 # Average number of references to valid blocks. 847system.cpu.icache.tags.warmup_cycle 32464202500 # Cycle when the warmup percentage was hit. 848system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor 849system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy 850system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy |
816system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 817system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id | 851system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 852system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id |
818system.cpu.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id 819system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id 820system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id | 853system.cpu.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 854system.cpu.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id 855system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id |
821system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 856system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
822system.cpu.icache.tags.tag_accesses 909390656 # Number of tag accesses 823system.cpu.icache.tags.data_accesses 909390656 # Number of data accesses 824system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 825system.cpu.icache.ReadReq_hits::cpu.inst 881804526 # number of ReadReq hits 826system.cpu.icache.ReadReq_hits::total 881804526 # number of ReadReq hits 827system.cpu.icache.demand_hits::cpu.inst 881804526 # number of demand (read+write) hits 828system.cpu.icache.demand_hits::total 881804526 # number of demand (read+write) hits 829system.cpu.icache.overall_hits::cpu.inst 881804526 # number of overall hits 830system.cpu.icache.overall_hits::total 881804526 # number of overall hits 831system.cpu.icache.ReadReq_misses::cpu.inst 13793065 # number of ReadReq misses 832system.cpu.icache.ReadReq_misses::total 13793065 # number of ReadReq misses 833system.cpu.icache.demand_misses::cpu.inst 13793065 # number of demand (read+write) misses 834system.cpu.icache.demand_misses::total 13793065 # number of demand (read+write) misses 835system.cpu.icache.overall_misses::cpu.inst 13793065 # number of overall misses 836system.cpu.icache.overall_misses::total 13793065 # number of overall misses 837system.cpu.icache.ReadReq_miss_latency::cpu.inst 185289814000 # number of ReadReq miss cycles 838system.cpu.icache.ReadReq_miss_latency::total 185289814000 # number of ReadReq miss cycles 839system.cpu.icache.demand_miss_latency::cpu.inst 185289814000 # number of demand (read+write) miss cycles 840system.cpu.icache.demand_miss_latency::total 185289814000 # number of demand (read+write) miss cycles 841system.cpu.icache.overall_miss_latency::cpu.inst 185289814000 # number of overall miss cycles 842system.cpu.icache.overall_miss_latency::total 185289814000 # number of overall miss cycles 843system.cpu.icache.ReadReq_accesses::cpu.inst 895597591 # number of ReadReq accesses(hits+misses) 844system.cpu.icache.ReadReq_accesses::total 895597591 # number of ReadReq accesses(hits+misses) 845system.cpu.icache.demand_accesses::cpu.inst 895597591 # number of demand (read+write) accesses 846system.cpu.icache.demand_accesses::total 895597591 # number of demand (read+write) accesses 847system.cpu.icache.overall_accesses::cpu.inst 895597591 # number of overall (read+write) accesses 848system.cpu.icache.overall_accesses::total 895597591 # number of overall (read+write) accesses 849system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015401 # miss rate for ReadReq accesses 850system.cpu.icache.ReadReq_miss_rate::total 0.015401 # miss rate for ReadReq accesses 851system.cpu.icache.demand_miss_rate::cpu.inst 0.015401 # miss rate for demand accesses 852system.cpu.icache.demand_miss_rate::total 0.015401 # miss rate for demand accesses 853system.cpu.icache.overall_miss_rate::cpu.inst 0.015401 # miss rate for overall accesses 854system.cpu.icache.overall_miss_rate::total 0.015401 # miss rate for overall accesses 855system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13433.548961 # average ReadReq miss latency 856system.cpu.icache.ReadReq_avg_miss_latency::total 13433.548961 # average ReadReq miss latency 857system.cpu.icache.demand_avg_miss_latency::cpu.inst 13433.548961 # average overall miss latency 858system.cpu.icache.demand_avg_miss_latency::total 13433.548961 # average overall miss latency 859system.cpu.icache.overall_avg_miss_latency::cpu.inst 13433.548961 # average overall miss latency 860system.cpu.icache.overall_avg_miss_latency::total 13433.548961 # average overall miss latency | 857system.cpu.icache.tags.tag_accesses 873616786 # Number of tag accesses 858system.cpu.icache.tags.data_accesses 873616786 # Number of data accesses 859system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 860system.cpu.icache.ReadReq_hits::cpu.inst 846636464 # number of ReadReq hits 861system.cpu.icache.ReadReq_hits::total 846636464 # number of ReadReq hits 862system.cpu.icache.demand_hits::cpu.inst 846636464 # number of demand (read+write) hits 863system.cpu.icache.demand_hits::total 846636464 # number of demand (read+write) hits 864system.cpu.icache.overall_hits::cpu.inst 846636464 # number of overall hits 865system.cpu.icache.overall_hits::total 846636464 # number of overall hits 866system.cpu.icache.ReadReq_misses::cpu.inst 13490161 # number of ReadReq misses 867system.cpu.icache.ReadReq_misses::total 13490161 # number of ReadReq misses 868system.cpu.icache.demand_misses::cpu.inst 13490161 # number of demand (read+write) misses 869system.cpu.icache.demand_misses::total 13490161 # number of demand (read+write) misses 870system.cpu.icache.overall_misses::cpu.inst 13490161 # number of overall misses 871system.cpu.icache.overall_misses::total 13490161 # number of overall misses 872system.cpu.icache.ReadReq_miss_latency::cpu.inst 183617881000 # number of ReadReq miss cycles 873system.cpu.icache.ReadReq_miss_latency::total 183617881000 # number of ReadReq miss cycles 874system.cpu.icache.demand_miss_latency::cpu.inst 183617881000 # number of demand (read+write) miss cycles 875system.cpu.icache.demand_miss_latency::total 183617881000 # number of demand (read+write) miss cycles 876system.cpu.icache.overall_miss_latency::cpu.inst 183617881000 # number of overall miss cycles 877system.cpu.icache.overall_miss_latency::total 183617881000 # number of overall miss cycles 878system.cpu.icache.ReadReq_accesses::cpu.inst 860126625 # number of ReadReq accesses(hits+misses) 879system.cpu.icache.ReadReq_accesses::total 860126625 # number of ReadReq accesses(hits+misses) 880system.cpu.icache.demand_accesses::cpu.inst 860126625 # number of demand (read+write) accesses 881system.cpu.icache.demand_accesses::total 860126625 # number of demand (read+write) accesses 882system.cpu.icache.overall_accesses::cpu.inst 860126625 # number of overall (read+write) accesses 883system.cpu.icache.overall_accesses::total 860126625 # number of overall (read+write) accesses 884system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015684 # miss rate for ReadReq accesses 885system.cpu.icache.ReadReq_miss_rate::total 0.015684 # miss rate for ReadReq accesses 886system.cpu.icache.demand_miss_rate::cpu.inst 0.015684 # miss rate for demand accesses 887system.cpu.icache.demand_miss_rate::total 0.015684 # miss rate for demand accesses 888system.cpu.icache.overall_miss_rate::cpu.inst 0.015684 # miss rate for overall accesses 889system.cpu.icache.overall_miss_rate::total 0.015684 # miss rate for overall accesses 890system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13611.244595 # average ReadReq miss latency 891system.cpu.icache.ReadReq_avg_miss_latency::total 13611.244595 # average ReadReq miss latency 892system.cpu.icache.demand_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency 893system.cpu.icache.demand_avg_miss_latency::total 13611.244595 # average overall miss latency 894system.cpu.icache.overall_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency 895system.cpu.icache.overall_avg_miss_latency::total 13611.244595 # average overall miss latency |
861system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 862system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 863system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 864system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 865system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 866system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 896system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 897system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 898system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 899system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 900system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 901system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
867system.cpu.icache.writebacks::writebacks 13792548 # number of writebacks 868system.cpu.icache.writebacks::total 13792548 # number of writebacks 869system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13793065 # number of ReadReq MSHR misses 870system.cpu.icache.ReadReq_mshr_misses::total 13793065 # number of ReadReq MSHR misses 871system.cpu.icache.demand_mshr_misses::cpu.inst 13793065 # number of demand (read+write) MSHR misses 872system.cpu.icache.demand_mshr_misses::total 13793065 # number of demand (read+write) MSHR misses 873system.cpu.icache.overall_mshr_misses::cpu.inst 13793065 # number of overall MSHR misses 874system.cpu.icache.overall_mshr_misses::total 13793065 # number of overall MSHR misses | 902system.cpu.icache.writebacks::writebacks 13489644 # number of writebacks 903system.cpu.icache.writebacks::total 13489644 # number of writebacks 904system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13490161 # number of ReadReq MSHR misses 905system.cpu.icache.ReadReq_mshr_misses::total 13490161 # number of ReadReq MSHR misses 906system.cpu.icache.demand_mshr_misses::cpu.inst 13490161 # number of demand (read+write) MSHR misses 907system.cpu.icache.demand_mshr_misses::total 13490161 # number of demand (read+write) MSHR misses 908system.cpu.icache.overall_mshr_misses::cpu.inst 13490161 # number of overall MSHR misses 909system.cpu.icache.overall_mshr_misses::total 13490161 # number of overall MSHR misses |
875system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 876system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 877system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 878system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses | 910system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 911system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 912system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 913system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses |
879system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171496749000 # number of ReadReq MSHR miss cycles 880system.cpu.icache.ReadReq_mshr_miss_latency::total 171496749000 # number of ReadReq MSHR miss cycles 881system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171496749000 # number of demand (read+write) MSHR miss cycles 882system.cpu.icache.demand_mshr_miss_latency::total 171496749000 # number of demand (read+write) MSHR miss cycles 883system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171496749000 # number of overall MSHR miss cycles 884system.cpu.icache.overall_mshr_miss_latency::total 171496749000 # number of overall MSHR miss cycles 885system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3263374000 # number of ReadReq MSHR uncacheable cycles 886system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3263374000 # number of ReadReq MSHR uncacheable cycles 887system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3263374000 # number of overall MSHR uncacheable cycles 888system.cpu.icache.overall_mshr_uncacheable_latency::total 3263374000 # number of overall MSHR uncacheable cycles 889system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015401 # mshr miss rate for ReadReq accesses 890system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses 891system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015401 # mshr miss rate for demand accesses 892system.cpu.icache.demand_mshr_miss_rate::total 0.015401 # mshr miss rate for demand accesses 893system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015401 # mshr miss rate for overall accesses 894system.cpu.icache.overall_mshr_miss_rate::total 0.015401 # mshr miss rate for overall accesses 895system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12433.548961 # average ReadReq mshr miss latency 896system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12433.548961 # average ReadReq mshr miss latency 897system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12433.548961 # average overall mshr miss latency 898system.cpu.icache.demand_avg_mshr_miss_latency::total 12433.548961 # average overall mshr miss latency 899system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12433.548961 # average overall mshr miss latency 900system.cpu.icache.overall_avg_mshr_miss_latency::total 12433.548961 # average overall mshr miss latency 901system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75672.440580 # average ReadReq mshr uncacheable latency 902system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75672.440580 # average ReadReq mshr uncacheable latency 903system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75672.440580 # average overall mshr uncacheable latency 904system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75672.440580 # average overall mshr uncacheable latency 905system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 906system.cpu.l2cache.tags.replacements 1308215 # number of replacements 907system.cpu.l2cache.tags.tagsinuse 65291.954914 # Cycle average of tags in use 908system.cpu.l2cache.tags.total_refs 46007809 # Total number of references to valid blocks. 909system.cpu.l2cache.tags.sampled_refs 1371583 # Sample count of references to valid blocks. 910system.cpu.l2cache.tags.avg_refs 33.543584 # Average number of references to valid blocks. 911system.cpu.l2cache.tags.warmup_cycle 6631976500 # Cycle when the warmup percentage was hit. 912system.cpu.l2cache.tags.occ_blocks::writebacks 10023.392915 # Average occupied blocks per requestor 913system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 424.218871 # Average occupied blocks per requestor 914system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 466.075042 # Average occupied blocks per requestor 915system.cpu.l2cache.tags.occ_blocks::cpu.inst 6280.682260 # Average occupied blocks per requestor 916system.cpu.l2cache.tags.occ_blocks::cpu.data 48097.585826 # Average occupied blocks per requestor 917system.cpu.l2cache.tags.occ_percent::writebacks 0.152945 # Average percentage of cache occupancy 918system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006473 # Average percentage of cache occupancy 919system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007112 # Average percentage of cache occupancy 920system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095836 # Average percentage of cache occupancy 921system.cpu.l2cache.tags.occ_percent::cpu.data 0.733911 # Average percentage of cache occupancy 922system.cpu.l2cache.tags.occ_percent::total 0.996276 # Average percentage of cache occupancy 923system.cpu.l2cache.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id 924system.cpu.l2cache.tags.occ_task_id_blocks::1024 63097 # Occupied blocks per task id 925system.cpu.l2cache.tags.age_task_id_blocks_1023::4 271 # Occupied blocks per task id 926system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 927system.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 928system.cpu.l2cache.tags.age_task_id_blocks_1024::2 779 # Occupied blocks per task id 929system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5781 # Occupied blocks per task id 930system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56275 # Occupied blocks per task id 931system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004135 # Percentage of cache occupancy per task id 932system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962784 # Percentage of cache occupancy per task id 933system.cpu.l2cache.tags.tag_accesses 391701839 # Number of tag accesses 934system.cpu.l2cache.tags.data_accesses 391701839 # Number of data accesses 935system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 936system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 351291 # number of ReadReq hits 937system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 234298 # number of ReadReq hits 938system.cpu.l2cache.ReadReq_hits::total 585589 # number of ReadReq hits 939system.cpu.l2cache.WritebackDirty_hits::writebacks 7906430 # number of WritebackDirty hits 940system.cpu.l2cache.WritebackDirty_hits::total 7906430 # number of WritebackDirty hits 941system.cpu.l2cache.WritebackClean_hits::writebacks 13790970 # number of WritebackClean hits 942system.cpu.l2cache.WritebackClean_hits::total 13790970 # number of WritebackClean hits 943system.cpu.l2cache.UpgradeReq_hits::cpu.data 26514 # number of UpgradeReq hits 944system.cpu.l2cache.UpgradeReq_hits::total 26514 # number of UpgradeReq hits 945system.cpu.l2cache.ReadExReq_hits::cpu.data 1636834 # number of ReadExReq hits 946system.cpu.l2cache.ReadExReq_hits::total 1636834 # number of ReadExReq hits 947system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13714488 # number of ReadCleanReq hits 948system.cpu.l2cache.ReadCleanReq_hits::total 13714488 # number of ReadCleanReq hits 949system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6572328 # number of ReadSharedReq hits 950system.cpu.l2cache.ReadSharedReq_hits::total 6572328 # number of ReadSharedReq hits 951system.cpu.l2cache.InvalidateReq_hits::cpu.data 722608 # number of InvalidateReq hits 952system.cpu.l2cache.InvalidateReq_hits::total 722608 # number of InvalidateReq hits 953system.cpu.l2cache.demand_hits::cpu.dtb.walker 351291 # number of demand (read+write) hits 954system.cpu.l2cache.demand_hits::cpu.itb.walker 234298 # number of demand (read+write) hits 955system.cpu.l2cache.demand_hits::cpu.inst 13714488 # number of demand (read+write) hits 956system.cpu.l2cache.demand_hits::cpu.data 8209162 # number of demand (read+write) hits 957system.cpu.l2cache.demand_hits::total 22509239 # number of demand (read+write) hits 958system.cpu.l2cache.overall_hits::cpu.dtb.walker 351291 # number of overall hits 959system.cpu.l2cache.overall_hits::cpu.itb.walker 234298 # number of overall hits 960system.cpu.l2cache.overall_hits::cpu.inst 13714488 # number of overall hits 961system.cpu.l2cache.overall_hits::cpu.data 8209162 # number of overall hits 962system.cpu.l2cache.overall_hits::total 22509239 # number of overall hits 963system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4188 # number of ReadReq misses 964system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4011 # number of ReadReq misses 965system.cpu.l2cache.ReadReq_misses::total 8199 # number of ReadReq misses 966system.cpu.l2cache.UpgradeReq_misses::cpu.data 3956 # number of UpgradeReq misses 967system.cpu.l2cache.UpgradeReq_misses::total 3956 # number of UpgradeReq misses 968system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 969system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 970system.cpu.l2cache.ReadExReq_misses::cpu.data 524003 # number of ReadExReq misses 971system.cpu.l2cache.ReadExReq_misses::total 524003 # number of ReadExReq misses 972system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 78577 # number of ReadCleanReq misses 973system.cpu.l2cache.ReadCleanReq_misses::total 78577 # number of ReadCleanReq misses 974system.cpu.l2cache.ReadSharedReq_misses::cpu.data 278865 # number of ReadSharedReq misses 975system.cpu.l2cache.ReadSharedReq_misses::total 278865 # number of ReadSharedReq misses 976system.cpu.l2cache.InvalidateReq_misses::cpu.data 510258 # number of InvalidateReq misses 977system.cpu.l2cache.InvalidateReq_misses::total 510258 # number of InvalidateReq misses 978system.cpu.l2cache.demand_misses::cpu.dtb.walker 4188 # number of demand (read+write) misses 979system.cpu.l2cache.demand_misses::cpu.itb.walker 4011 # number of demand (read+write) misses 980system.cpu.l2cache.demand_misses::cpu.inst 78577 # number of demand (read+write) misses 981system.cpu.l2cache.demand_misses::cpu.data 802868 # number of demand (read+write) misses 982system.cpu.l2cache.demand_misses::total 889644 # number of demand (read+write) misses 983system.cpu.l2cache.overall_misses::cpu.dtb.walker 4188 # number of overall misses 984system.cpu.l2cache.overall_misses::cpu.itb.walker 4011 # number of overall misses 985system.cpu.l2cache.overall_misses::cpu.inst 78577 # number of overall misses 986system.cpu.l2cache.overall_misses::cpu.data 802868 # number of overall misses 987system.cpu.l2cache.overall_misses::total 889644 # number of overall misses 988system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 360029500 # number of ReadReq miss cycles 989system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 354230500 # number of ReadReq miss cycles 990system.cpu.l2cache.ReadReq_miss_latency::total 714260000 # number of ReadReq miss cycles 991system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69357500 # number of UpgradeReq miss cycles 992system.cpu.l2cache.UpgradeReq_miss_latency::total 69357500 # number of UpgradeReq miss cycles 993system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 189500 # number of SCUpgradeReq miss cycles 994system.cpu.l2cache.SCUpgradeReq_miss_latency::total 189500 # number of SCUpgradeReq miss cycles 995system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 43047428500 # number of ReadExReq miss cycles 996system.cpu.l2cache.ReadExReq_miss_latency::total 43047428500 # number of ReadExReq miss cycles 997system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 6529692000 # number of ReadCleanReq miss cycles 998system.cpu.l2cache.ReadCleanReq_miss_latency::total 6529692000 # number of ReadCleanReq miss cycles 999system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 23627731000 # number of ReadSharedReq miss cycles 1000system.cpu.l2cache.ReadSharedReq_miss_latency::total 23627731000 # number of ReadSharedReq miss cycles 1001system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 478000 # number of InvalidateReq miss cycles 1002system.cpu.l2cache.InvalidateReq_miss_latency::total 478000 # number of InvalidateReq miss cycles 1003system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 360029500 # number of demand (read+write) miss cycles 1004system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 354230500 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.demand_miss_latency::cpu.inst 6529692000 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.demand_miss_latency::cpu.data 66675159500 # number of demand (read+write) miss cycles 1007system.cpu.l2cache.demand_miss_latency::total 73919111500 # number of demand (read+write) miss cycles 1008system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 360029500 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 354230500 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::cpu.inst 6529692000 # number of overall miss cycles 1011system.cpu.l2cache.overall_miss_latency::cpu.data 66675159500 # number of overall miss cycles 1012system.cpu.l2cache.overall_miss_latency::total 73919111500 # number of overall miss cycles 1013system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 355479 # number of ReadReq accesses(hits+misses) 1014system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 238309 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::total 593788 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.WritebackDirty_accesses::writebacks 7906430 # number of WritebackDirty accesses(hits+misses) 1017system.cpu.l2cache.WritebackDirty_accesses::total 7906430 # number of WritebackDirty accesses(hits+misses) 1018system.cpu.l2cache.WritebackClean_accesses::writebacks 13790970 # number of WritebackClean accesses(hits+misses) 1019system.cpu.l2cache.WritebackClean_accesses::total 13790970 # number of WritebackClean accesses(hits+misses) 1020system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30470 # number of UpgradeReq accesses(hits+misses) 1021system.cpu.l2cache.UpgradeReq_accesses::total 30470 # number of UpgradeReq accesses(hits+misses) 1022system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) 1023system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) 1024system.cpu.l2cache.ReadExReq_accesses::cpu.data 2160837 # number of ReadExReq accesses(hits+misses) 1025system.cpu.l2cache.ReadExReq_accesses::total 2160837 # number of ReadExReq accesses(hits+misses) 1026system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13793065 # number of ReadCleanReq accesses(hits+misses) 1027system.cpu.l2cache.ReadCleanReq_accesses::total 13793065 # number of ReadCleanReq accesses(hits+misses) 1028system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6851193 # number of ReadSharedReq accesses(hits+misses) 1029system.cpu.l2cache.ReadSharedReq_accesses::total 6851193 # number of ReadSharedReq accesses(hits+misses) 1030system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1232866 # number of InvalidateReq accesses(hits+misses) 1031system.cpu.l2cache.InvalidateReq_accesses::total 1232866 # number of InvalidateReq accesses(hits+misses) 1032system.cpu.l2cache.demand_accesses::cpu.dtb.walker 355479 # number of demand (read+write) accesses 1033system.cpu.l2cache.demand_accesses::cpu.itb.walker 238309 # number of demand (read+write) accesses 1034system.cpu.l2cache.demand_accesses::cpu.inst 13793065 # number of demand (read+write) accesses 1035system.cpu.l2cache.demand_accesses::cpu.data 9012030 # number of demand (read+write) accesses 1036system.cpu.l2cache.demand_accesses::total 23398883 # number of demand (read+write) accesses 1037system.cpu.l2cache.overall_accesses::cpu.dtb.walker 355479 # number of overall (read+write) accesses 1038system.cpu.l2cache.overall_accesses::cpu.itb.walker 238309 # number of overall (read+write) accesses 1039system.cpu.l2cache.overall_accesses::cpu.inst 13793065 # number of overall (read+write) accesses 1040system.cpu.l2cache.overall_accesses::cpu.data 9012030 # number of overall (read+write) accesses 1041system.cpu.l2cache.overall_accesses::total 23398883 # number of overall (read+write) accesses 1042system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011781 # miss rate for ReadReq accesses 1043system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016831 # miss rate for ReadReq accesses 1044system.cpu.l2cache.ReadReq_miss_rate::total 0.013808 # miss rate for ReadReq accesses 1045system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.129833 # miss rate for UpgradeReq accesses 1046system.cpu.l2cache.UpgradeReq_miss_rate::total 0.129833 # miss rate for UpgradeReq accesses | 914system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170127720000 # number of ReadReq MSHR miss cycles 915system.cpu.icache.ReadReq_mshr_miss_latency::total 170127720000 # number of ReadReq MSHR miss cycles 916system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170127720000 # number of demand (read+write) MSHR miss cycles 917system.cpu.icache.demand_mshr_miss_latency::total 170127720000 # number of demand (read+write) MSHR miss cycles 918system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170127720000 # number of overall MSHR miss cycles 919system.cpu.icache.overall_mshr_miss_latency::total 170127720000 # number of overall MSHR miss cycles 920system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3557271000 # number of ReadReq MSHR uncacheable cycles 921system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3557271000 # number of ReadReq MSHR uncacheable cycles 922system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3557271000 # number of overall MSHR uncacheable cycles 923system.cpu.icache.overall_mshr_uncacheable_latency::total 3557271000 # number of overall MSHR uncacheable cycles 924system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for ReadReq accesses 925system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015684 # mshr miss rate for ReadReq accesses 926system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for demand accesses 927system.cpu.icache.demand_mshr_miss_rate::total 0.015684 # mshr miss rate for demand accesses 928system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for overall accesses 929system.cpu.icache.overall_mshr_miss_rate::total 0.015684 # mshr miss rate for overall accesses 930system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12611.244595 # average ReadReq mshr miss latency 931system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12611.244595 # average ReadReq mshr miss latency 932system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12611.244595 # average overall mshr miss latency 933system.cpu.icache.demand_avg_mshr_miss_latency::total 12611.244595 # average overall mshr miss latency 934system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12611.244595 # average overall mshr miss latency 935system.cpu.icache.overall_avg_mshr_miss_latency::total 12611.244595 # average overall mshr miss latency 936system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average ReadReq mshr uncacheable latency 937system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478 # average ReadReq mshr uncacheable latency 938system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency 939system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency 940system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 941system.cpu.l2cache.tags.replacements 1158676 # number of replacements 942system.cpu.l2cache.tags.tagsinuse 65394.159072 # Cycle average of tags in use 943system.cpu.l2cache.tags.total_refs 44435371 # Total number of references to valid blocks. 944system.cpu.l2cache.tags.sampled_refs 1220446 # Sample count of references to valid blocks. 945system.cpu.l2cache.tags.avg_refs 36.409125 # Average number of references to valid blocks. 946system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit. 947system.cpu.l2cache.tags.occ_blocks::writebacks 10890.998401 # Average occupied blocks per requestor 948system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 465.362855 # Average occupied blocks per requestor 949system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 539.855564 # Average occupied blocks per requestor 950system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.163394 # Average occupied blocks per requestor 951system.cpu.l2cache.tags.occ_blocks::cpu.data 46827.778856 # Average occupied blocks per requestor 952system.cpu.l2cache.tags.occ_percent::writebacks 0.166183 # Average percentage of cache occupancy 953system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007101 # Average percentage of cache occupancy 954system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008238 # Average percentage of cache occupancy 955system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101779 # Average percentage of cache occupancy 956system.cpu.l2cache.tags.occ_percent::cpu.data 0.714535 # Average percentage of cache occupancy 957system.cpu.l2cache.tags.occ_percent::total 0.997836 # Average percentage of cache occupancy 958system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id 959system.cpu.l2cache.tags.occ_task_id_blocks::1024 61492 # Occupied blocks per task id 960system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id 961system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id 964system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5790 # Occupied blocks per task id 965system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54645 # Occupied blocks per task id 966system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id 967system.cpu.l2cache.tags.occ_task_id_percent::1024 0.938293 # Percentage of cache occupancy per task id 968system.cpu.l2cache.tags.tag_accesses 377782006 # Number of tag accesses 969system.cpu.l2cache.tags.data_accesses 377782006 # Number of data accesses 970system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 971system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 307317 # number of ReadReq hits 972system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 227975 # number of ReadReq hits 973system.cpu.l2cache.ReadReq_hits::total 535292 # number of ReadReq hits 974system.cpu.l2cache.WritebackDirty_hits::writebacks 7498102 # number of WritebackDirty hits 975system.cpu.l2cache.WritebackDirty_hits::total 7498102 # number of WritebackDirty hits 976system.cpu.l2cache.WritebackClean_hits::writebacks 13488047 # number of WritebackClean hits 977system.cpu.l2cache.WritebackClean_hits::total 13488047 # number of WritebackClean hits 978system.cpu.l2cache.UpgradeReq_hits::cpu.data 24835 # number of UpgradeReq hits 979system.cpu.l2cache.UpgradeReq_hits::total 24835 # number of UpgradeReq hits 980system.cpu.l2cache.ReadExReq_hits::cpu.data 1605264 # number of ReadExReq hits 981system.cpu.l2cache.ReadExReq_hits::total 1605264 # number of ReadExReq hits 982system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13414164 # number of ReadCleanReq hits 983system.cpu.l2cache.ReadCleanReq_hits::total 13414164 # number of ReadCleanReq hits 984system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6210983 # number of ReadSharedReq hits 985system.cpu.l2cache.ReadSharedReq_hits::total 6210983 # number of ReadSharedReq hits 986system.cpu.l2cache.InvalidateReq_hits::cpu.data 729246 # number of InvalidateReq hits 987system.cpu.l2cache.InvalidateReq_hits::total 729246 # number of InvalidateReq hits 988system.cpu.l2cache.demand_hits::cpu.dtb.walker 307317 # number of demand (read+write) hits 989system.cpu.l2cache.demand_hits::cpu.itb.walker 227975 # number of demand (read+write) hits 990system.cpu.l2cache.demand_hits::cpu.inst 13414164 # number of demand (read+write) hits 991system.cpu.l2cache.demand_hits::cpu.data 7816247 # number of demand (read+write) hits 992system.cpu.l2cache.demand_hits::total 21765703 # number of demand (read+write) hits 993system.cpu.l2cache.overall_hits::cpu.dtb.walker 307317 # number of overall hits 994system.cpu.l2cache.overall_hits::cpu.itb.walker 227975 # number of overall hits 995system.cpu.l2cache.overall_hits::cpu.inst 13414164 # number of overall hits 996system.cpu.l2cache.overall_hits::cpu.data 7816247 # number of overall hits 997system.cpu.l2cache.overall_hits::total 21765703 # number of overall hits 998system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3382 # number of ReadReq misses 999system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3425 # number of ReadReq misses 1000system.cpu.l2cache.ReadReq_misses::total 6807 # number of ReadReq misses 1001system.cpu.l2cache.UpgradeReq_misses::cpu.data 3962 # number of UpgradeReq misses 1002system.cpu.l2cache.UpgradeReq_misses::total 3962 # number of UpgradeReq misses 1003system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1004system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 1005system.cpu.l2cache.ReadExReq_misses::cpu.data 414863 # number of ReadExReq misses 1006system.cpu.l2cache.ReadExReq_misses::total 414863 # number of ReadExReq misses 1007system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 75997 # number of ReadCleanReq misses 1008system.cpu.l2cache.ReadCleanReq_misses::total 75997 # number of ReadCleanReq misses 1009system.cpu.l2cache.ReadSharedReq_misses::cpu.data 256141 # number of ReadSharedReq misses 1010system.cpu.l2cache.ReadSharedReq_misses::total 256141 # number of ReadSharedReq misses 1011system.cpu.l2cache.InvalidateReq_misses::cpu.data 496901 # number of InvalidateReq misses 1012system.cpu.l2cache.InvalidateReq_misses::total 496901 # number of InvalidateReq misses 1013system.cpu.l2cache.demand_misses::cpu.dtb.walker 3382 # number of demand (read+write) misses 1014system.cpu.l2cache.demand_misses::cpu.itb.walker 3425 # number of demand (read+write) misses 1015system.cpu.l2cache.demand_misses::cpu.inst 75997 # number of demand (read+write) misses 1016system.cpu.l2cache.demand_misses::cpu.data 671004 # number of demand (read+write) misses 1017system.cpu.l2cache.demand_misses::total 753808 # number of demand (read+write) misses 1018system.cpu.l2cache.overall_misses::cpu.dtb.walker 3382 # number of overall misses 1019system.cpu.l2cache.overall_misses::cpu.itb.walker 3425 # number of overall misses 1020system.cpu.l2cache.overall_misses::cpu.inst 75997 # number of overall misses 1021system.cpu.l2cache.overall_misses::cpu.data 671004 # number of overall misses 1022system.cpu.l2cache.overall_misses::total 753808 # number of overall misses 1023system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 458444500 # number of ReadReq miss cycles 1024system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 422573500 # number of ReadReq miss cycles 1025system.cpu.l2cache.ReadReq_miss_latency::total 881018000 # number of ReadReq miss cycles 1026system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69853000 # number of UpgradeReq miss cycles 1027system.cpu.l2cache.UpgradeReq_miss_latency::total 69853000 # number of UpgradeReq miss cycles 1028system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles 1029system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles 1030system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40877442000 # number of ReadExReq miss cycles 1031system.cpu.l2cache.ReadExReq_miss_latency::total 40877442000 # number of ReadExReq miss cycles 1032system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8773195000 # number of ReadCleanReq miss cycles 1033system.cpu.l2cache.ReadCleanReq_miss_latency::total 8773195000 # number of ReadCleanReq miss cycles 1034system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30189333000 # number of ReadSharedReq miss cycles 1035system.cpu.l2cache.ReadSharedReq_miss_latency::total 30189333000 # number of ReadSharedReq miss cycles 1036system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 454500 # number of InvalidateReq miss cycles 1037system.cpu.l2cache.InvalidateReq_miss_latency::total 454500 # number of InvalidateReq miss cycles 1038system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 458444500 # number of demand (read+write) miss cycles 1039system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 422573500 # number of demand (read+write) miss cycles 1040system.cpu.l2cache.demand_miss_latency::cpu.inst 8773195000 # number of demand (read+write) miss cycles 1041system.cpu.l2cache.demand_miss_latency::cpu.data 71066775000 # number of demand (read+write) miss cycles 1042system.cpu.l2cache.demand_miss_latency::total 80720988000 # number of demand (read+write) miss cycles 1043system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 458444500 # number of overall miss cycles 1044system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 422573500 # number of overall miss cycles 1045system.cpu.l2cache.overall_miss_latency::cpu.inst 8773195000 # number of overall miss cycles 1046system.cpu.l2cache.overall_miss_latency::cpu.data 71066775000 # number of overall miss cycles 1047system.cpu.l2cache.overall_miss_latency::total 80720988000 # number of overall miss cycles 1048system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 310699 # number of ReadReq accesses(hits+misses) 1049system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 231400 # number of ReadReq accesses(hits+misses) 1050system.cpu.l2cache.ReadReq_accesses::total 542099 # number of ReadReq accesses(hits+misses) 1051system.cpu.l2cache.WritebackDirty_accesses::writebacks 7498102 # number of WritebackDirty accesses(hits+misses) 1052system.cpu.l2cache.WritebackDirty_accesses::total 7498102 # number of WritebackDirty accesses(hits+misses) 1053system.cpu.l2cache.WritebackClean_accesses::writebacks 13488047 # number of WritebackClean accesses(hits+misses) 1054system.cpu.l2cache.WritebackClean_accesses::total 13488047 # number of WritebackClean accesses(hits+misses) 1055system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28797 # number of UpgradeReq accesses(hits+misses) 1056system.cpu.l2cache.UpgradeReq_accesses::total 28797 # number of UpgradeReq accesses(hits+misses) 1057system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1058system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1059system.cpu.l2cache.ReadExReq_accesses::cpu.data 2020127 # number of ReadExReq accesses(hits+misses) 1060system.cpu.l2cache.ReadExReq_accesses::total 2020127 # number of ReadExReq accesses(hits+misses) 1061system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13490161 # number of ReadCleanReq accesses(hits+misses) 1062system.cpu.l2cache.ReadCleanReq_accesses::total 13490161 # number of ReadCleanReq accesses(hits+misses) 1063system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6467124 # number of ReadSharedReq accesses(hits+misses) 1064system.cpu.l2cache.ReadSharedReq_accesses::total 6467124 # number of ReadSharedReq accesses(hits+misses) 1065system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226147 # number of InvalidateReq accesses(hits+misses) 1066system.cpu.l2cache.InvalidateReq_accesses::total 1226147 # number of InvalidateReq accesses(hits+misses) 1067system.cpu.l2cache.demand_accesses::cpu.dtb.walker 310699 # number of demand (read+write) accesses 1068system.cpu.l2cache.demand_accesses::cpu.itb.walker 231400 # number of demand (read+write) accesses 1069system.cpu.l2cache.demand_accesses::cpu.inst 13490161 # number of demand (read+write) accesses 1070system.cpu.l2cache.demand_accesses::cpu.data 8487251 # number of demand (read+write) accesses 1071system.cpu.l2cache.demand_accesses::total 22519511 # number of demand (read+write) accesses 1072system.cpu.l2cache.overall_accesses::cpu.dtb.walker 310699 # number of overall (read+write) accesses 1073system.cpu.l2cache.overall_accesses::cpu.itb.walker 231400 # number of overall (read+write) accesses 1074system.cpu.l2cache.overall_accesses::cpu.inst 13490161 # number of overall (read+write) accesses 1075system.cpu.l2cache.overall_accesses::cpu.data 8487251 # number of overall (read+write) accesses 1076system.cpu.l2cache.overall_accesses::total 22519511 # number of overall (read+write) accesses 1077system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010885 # miss rate for ReadReq accesses 1078system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.014801 # miss rate for ReadReq accesses 1079system.cpu.l2cache.ReadReq_miss_rate::total 0.012557 # miss rate for ReadReq accesses 1080system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.137584 # miss rate for UpgradeReq accesses 1081system.cpu.l2cache.UpgradeReq_miss_rate::total 0.137584 # miss rate for UpgradeReq accesses |
1047system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1048system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1082system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1083system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
1049system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.242500 # miss rate for ReadExReq accesses 1050system.cpu.l2cache.ReadExReq_miss_rate::total 0.242500 # miss rate for ReadExReq accesses 1051system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005697 # miss rate for ReadCleanReq accesses 1052system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005697 # miss rate for ReadCleanReq accesses 1053system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040703 # miss rate for ReadSharedReq accesses 1054system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040703 # miss rate for ReadSharedReq accesses 1055system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.413880 # miss rate for InvalidateReq accesses 1056system.cpu.l2cache.InvalidateReq_miss_rate::total 0.413880 # miss rate for InvalidateReq accesses 1057system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011781 # miss rate for demand accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016831 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005697 # miss rate for demand accesses 1060system.cpu.l2cache.demand_miss_rate::cpu.data 0.089088 # miss rate for demand accesses 1061system.cpu.l2cache.demand_miss_rate::total 0.038021 # miss rate for demand accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011781 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016831 # miss rate for overall accesses 1064system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005697 # miss rate for overall accesses 1065system.cpu.l2cache.overall_miss_rate::cpu.data 0.089088 # miss rate for overall accesses 1066system.cpu.l2cache.overall_miss_rate::total 0.038021 # miss rate for overall accesses 1067system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85966.929322 # average ReadReq miss latency 1068system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88314.759412 # average ReadReq miss latency 1069system.cpu.l2cache.ReadReq_avg_miss_latency::total 87115.501890 # average ReadReq miss latency 1070system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17532.229525 # average UpgradeReq miss latency 1071system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17532.229525 # average UpgradeReq miss latency 1072system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 63166.666667 # average SCUpgradeReq miss latency 1073system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 63166.666667 # average SCUpgradeReq miss latency 1074system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82151.110776 # average ReadExReq miss latency 1075system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82151.110776 # average ReadExReq miss latency 1076system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83099.278415 # average ReadCleanReq miss latency 1077system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83099.278415 # average ReadCleanReq miss latency 1078system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84728.205404 # average ReadSharedReq miss latency 1079system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84728.205404 # average ReadSharedReq miss latency 1080system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.936781 # average InvalidateReq miss latency 1081system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.936781 # average InvalidateReq miss latency 1082system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85966.929322 # average overall miss latency 1083system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88314.759412 # average overall miss latency 1084system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83099.278415 # average overall miss latency 1085system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83046.228645 # average overall miss latency 1086system.cpu.l2cache.demand_avg_miss_latency::total 83088.416827 # average overall miss latency 1087system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85966.929322 # average overall miss latency 1088system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88314.759412 # average overall miss latency 1089system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83099.278415 # average overall miss latency 1090system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83046.228645 # average overall miss latency 1091system.cpu.l2cache.overall_avg_miss_latency::total 83088.416827 # average overall miss latency | 1084system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205365 # miss rate for ReadExReq accesses 1085system.cpu.l2cache.ReadExReq_miss_rate::total 0.205365 # miss rate for ReadExReq accesses 1086system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005634 # miss rate for ReadCleanReq accesses 1087system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005634 # miss rate for ReadCleanReq accesses 1088system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039607 # miss rate for ReadSharedReq accesses 1089system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039607 # miss rate for ReadSharedReq accesses 1090system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.405254 # miss rate for InvalidateReq accesses 1091system.cpu.l2cache.InvalidateReq_miss_rate::total 0.405254 # miss rate for InvalidateReq accesses 1092system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010885 # miss rate for demand accesses 1093system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.014801 # miss rate for demand accesses 1094system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005634 # miss rate for demand accesses 1095system.cpu.l2cache.demand_miss_rate::cpu.data 0.079060 # miss rate for demand accesses 1096system.cpu.l2cache.demand_miss_rate::total 0.033474 # miss rate for demand accesses 1097system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010885 # miss rate for overall accesses 1098system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.014801 # miss rate for overall accesses 1099system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005634 # miss rate for overall accesses 1100system.cpu.l2cache.overall_miss_rate::cpu.data 0.079060 # miss rate for overall accesses 1101system.cpu.l2cache.overall_miss_rate::total 0.033474 # miss rate for overall accesses 1102system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135554.257836 # average ReadReq miss latency 1103system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 123379.124088 # average ReadReq miss latency 1104system.cpu.l2cache.ReadReq_avg_miss_latency::total 129428.235640 # average ReadReq miss latency 1105system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17630.742049 # average UpgradeReq miss latency 1106system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17630.742049 # average UpgradeReq miss latency 1107system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81250 # average SCUpgradeReq miss latency 1108system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency 1109system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98532.387800 # average ReadExReq miss latency 1110system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98532.387800 # average ReadExReq miss latency 1111system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 115441.333211 # average ReadCleanReq miss latency 1112system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 115441.333211 # average ReadCleanReq miss latency 1113system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117862.165760 # average ReadSharedReq miss latency 1114system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117862.165760 # average ReadSharedReq miss latency 1115system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.914669 # average InvalidateReq miss latency 1116system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.914669 # average InvalidateReq miss latency 1117system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135554.257836 # average overall miss latency 1118system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 123379.124088 # average overall miss latency 1119system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 115441.333211 # average overall miss latency 1120system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105911.104852 # average overall miss latency 1121system.cpu.l2cache.demand_avg_miss_latency::total 107084.281409 # average overall miss latency 1122system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135554.257836 # average overall miss latency 1123system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 123379.124088 # average overall miss latency 1124system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 115441.333211 # average overall miss latency 1125system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105911.104852 # average overall miss latency 1126system.cpu.l2cache.overall_avg_miss_latency::total 107084.281409 # average overall miss latency |
1092system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1093system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1094system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1095system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1096system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1097system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1127system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1128system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1129system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1130system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1131system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1132system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1098system.cpu.l2cache.writebacks::writebacks 1123249 # number of writebacks 1099system.cpu.l2cache.writebacks::total 1123249 # number of writebacks 1100system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4188 # number of ReadReq MSHR misses 1101system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4011 # number of ReadReq MSHR misses 1102system.cpu.l2cache.ReadReq_mshr_misses::total 8199 # number of ReadReq MSHR misses 1103system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 1104system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 1105system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3956 # number of UpgradeReq MSHR misses 1106system.cpu.l2cache.UpgradeReq_mshr_misses::total 3956 # number of UpgradeReq MSHR misses 1107system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1108system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1109system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 524003 # number of ReadExReq MSHR misses 1110system.cpu.l2cache.ReadExReq_mshr_misses::total 524003 # number of ReadExReq MSHR misses 1111system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 78577 # number of ReadCleanReq MSHR misses 1112system.cpu.l2cache.ReadCleanReq_mshr_misses::total 78577 # number of ReadCleanReq MSHR misses 1113system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 278865 # number of ReadSharedReq MSHR misses 1114system.cpu.l2cache.ReadSharedReq_mshr_misses::total 278865 # number of ReadSharedReq MSHR misses 1115system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 510258 # number of InvalidateReq MSHR misses 1116system.cpu.l2cache.InvalidateReq_mshr_misses::total 510258 # number of InvalidateReq MSHR misses 1117system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4188 # number of demand (read+write) MSHR misses 1118system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4011 # number of demand (read+write) MSHR misses 1119system.cpu.l2cache.demand_mshr_misses::cpu.inst 78577 # number of demand (read+write) MSHR misses 1120system.cpu.l2cache.demand_mshr_misses::cpu.data 802868 # number of demand (read+write) MSHR misses 1121system.cpu.l2cache.demand_mshr_misses::total 889644 # number of demand (read+write) MSHR misses 1122system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4188 # number of overall MSHR misses 1123system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4011 # number of overall MSHR misses 1124system.cpu.l2cache.overall_mshr_misses::cpu.inst 78577 # number of overall MSHR misses 1125system.cpu.l2cache.overall_mshr_misses::cpu.data 802868 # number of overall MSHR misses 1126system.cpu.l2cache.overall_mshr_misses::total 889644 # number of overall MSHR misses | 1133system.cpu.l2cache.writebacks::writebacks 985073 # number of writebacks 1134system.cpu.l2cache.writebacks::total 985073 # number of writebacks 1135system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3382 # number of ReadReq MSHR misses 1136system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3425 # number of ReadReq MSHR misses 1137system.cpu.l2cache.ReadReq_mshr_misses::total 6807 # number of ReadReq MSHR misses 1138system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3962 # number of UpgradeReq MSHR misses 1139system.cpu.l2cache.UpgradeReq_mshr_misses::total 3962 # number of UpgradeReq MSHR misses 1140system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1141system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1142system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 414863 # number of ReadExReq MSHR misses 1143system.cpu.l2cache.ReadExReq_mshr_misses::total 414863 # number of ReadExReq MSHR misses 1144system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 75997 # number of ReadCleanReq MSHR misses 1145system.cpu.l2cache.ReadCleanReq_mshr_misses::total 75997 # number of ReadCleanReq MSHR misses 1146system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256141 # number of ReadSharedReq MSHR misses 1147system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256141 # number of ReadSharedReq MSHR misses 1148system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 496901 # number of InvalidateReq MSHR misses 1149system.cpu.l2cache.InvalidateReq_mshr_misses::total 496901 # number of InvalidateReq MSHR misses 1150system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3382 # number of demand (read+write) MSHR misses 1151system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3425 # number of demand (read+write) MSHR misses 1152system.cpu.l2cache.demand_mshr_misses::cpu.inst 75997 # number of demand (read+write) MSHR misses 1153system.cpu.l2cache.demand_mshr_misses::cpu.data 671004 # number of demand (read+write) MSHR misses 1154system.cpu.l2cache.demand_mshr_misses::total 753808 # number of demand (read+write) MSHR misses 1155system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3382 # number of overall MSHR misses 1156system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3425 # number of overall MSHR misses 1157system.cpu.l2cache.overall_mshr_misses::cpu.inst 75997 # number of overall MSHR misses 1158system.cpu.l2cache.overall_mshr_misses::cpu.data 671004 # number of overall MSHR misses 1159system.cpu.l2cache.overall_mshr_misses::total 753808 # number of overall MSHR misses |
1127system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1128system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 1129system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable 1130system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 1131system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 1132system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1133system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 1134system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses | 1160system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1161system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 1162system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable 1163system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 1164system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 1165system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1166system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 1167system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses |
1135system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 318149500 # number of ReadReq MSHR miss cycles 1136system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314120500 # number of ReadReq MSHR miss cycles 1137system.cpu.l2cache.ReadReq_mshr_miss_latency::total 632270000 # number of ReadReq MSHR miss cycles 1138system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75426500 # number of UpgradeReq MSHR miss cycles 1139system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75426500 # number of UpgradeReq MSHR miss cycles 1140system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 159500 # number of SCUpgradeReq MSHR miss cycles 1141system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 159500 # number of SCUpgradeReq MSHR miss cycles 1142system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 37807398500 # number of ReadExReq MSHR miss cycles 1143system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 37807398500 # number of ReadExReq MSHR miss cycles 1144system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 5743922000 # number of ReadCleanReq MSHR miss cycles 1145system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 5743922000 # number of ReadCleanReq MSHR miss cycles 1146system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20839044573 # number of ReadSharedReq MSHR miss cycles 1147system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20839044573 # number of ReadSharedReq MSHR miss cycles 1148system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9521744500 # number of InvalidateReq MSHR miss cycles 1149system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9521744500 # number of InvalidateReq MSHR miss cycles 1150system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 318149500 # number of demand (read+write) MSHR miss cycles 1151system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314120500 # number of demand (read+write) MSHR miss cycles 1152system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5743922000 # number of demand (read+write) MSHR miss cycles 1153system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58646443073 # number of demand (read+write) MSHR miss cycles 1154system.cpu.l2cache.demand_mshr_miss_latency::total 65022635073 # number of demand (read+write) MSHR miss cycles 1155system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 318149500 # number of overall MSHR miss cycles 1156system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314120500 # number of overall MSHR miss cycles 1157system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5743922000 # number of overall MSHR miss cycles 1158system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58646443073 # number of overall MSHR miss cycles 1159system.cpu.l2cache.overall_mshr_miss_latency::total 65022635073 # number of overall MSHR miss cycles 1160system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2724311500 # number of ReadReq MSHR uncacheable cycles 1161system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810947000 # number of ReadReq MSHR uncacheable cycles 1162system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8535258500 # number of ReadReq MSHR uncacheable cycles 1163system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2724311500 # number of overall MSHR uncacheable cycles 1164system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810947000 # number of overall MSHR uncacheable cycles 1165system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8535258500 # number of overall MSHR uncacheable cycles 1166system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011781 # mshr miss rate for ReadReq accesses 1167system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016831 # mshr miss rate for ReadReq accesses 1168system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013808 # mshr miss rate for ReadReq accesses 1169system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1170system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1171system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.129833 # mshr miss rate for UpgradeReq accesses 1172system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.129833 # mshr miss rate for UpgradeReq accesses | 1168system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 424624500 # number of ReadReq MSHR miss cycles 1169system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 388323500 # number of ReadReq MSHR miss cycles 1170system.cpu.l2cache.ReadReq_mshr_miss_latency::total 812948000 # number of ReadReq MSHR miss cycles 1171system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75436500 # number of UpgradeReq MSHR miss cycles 1172system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75436500 # number of UpgradeReq MSHR miss cycles 1173system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142500 # number of SCUpgradeReq MSHR miss cycles 1174system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles 1175system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36728812000 # number of ReadExReq MSHR miss cycles 1176system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36728812000 # number of ReadExReq MSHR miss cycles 1177system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8013225000 # number of ReadCleanReq MSHR miss cycles 1178system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8013225000 # number of ReadCleanReq MSHR miss cycles 1179system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27627908030 # number of ReadSharedReq MSHR miss cycles 1180system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27627908030 # number of ReadSharedReq MSHR miss cycles 1181system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9273801000 # number of InvalidateReq MSHR miss cycles 1182system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9273801000 # number of InvalidateReq MSHR miss cycles 1183system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 424624500 # number of demand (read+write) MSHR miss cycles 1184system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 388323500 # number of demand (read+write) MSHR miss cycles 1185system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8013225000 # number of demand (read+write) MSHR miss cycles 1186system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64356720030 # number of demand (read+write) MSHR miss cycles 1187system.cpu.l2cache.demand_mshr_miss_latency::total 73182893030 # number of demand (read+write) MSHR miss cycles 1188system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 424624500 # number of overall MSHR miss cycles 1189system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 388323500 # number of overall MSHR miss cycles 1190system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8013225000 # number of overall MSHR miss cycles 1191system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64356720030 # number of overall MSHR miss cycles 1192system.cpu.l2cache.overall_mshr_miss_latency::total 73182893030 # number of overall MSHR miss cycles 1193system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3018208500 # number of ReadReq MSHR uncacheable cycles 1194system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810725000 # number of ReadReq MSHR uncacheable cycles 1195system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8828933500 # number of ReadReq MSHR uncacheable cycles 1196system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3018208500 # number of overall MSHR uncacheable cycles 1197system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810725000 # number of overall MSHR uncacheable cycles 1198system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8828933500 # number of overall MSHR uncacheable cycles 1199system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for ReadReq accesses 1200system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for ReadReq accesses 1201system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012557 # mshr miss rate for ReadReq accesses 1202system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.137584 # mshr miss rate for UpgradeReq accesses 1203system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.137584 # mshr miss rate for UpgradeReq accesses |
1173system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1174system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1204system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1205system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
1175system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.242500 # mshr miss rate for ReadExReq accesses 1176system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.242500 # mshr miss rate for ReadExReq accesses 1177system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for ReadCleanReq accesses 1178system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005697 # mshr miss rate for ReadCleanReq accesses 1179system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040703 # mshr miss rate for ReadSharedReq accesses 1180system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040703 # mshr miss rate for ReadSharedReq accesses 1181system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.413880 # mshr miss rate for InvalidateReq accesses 1182system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.413880 # mshr miss rate for InvalidateReq accesses 1183system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011781 # mshr miss rate for demand accesses 1184system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016831 # mshr miss rate for demand accesses 1185system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for demand accesses 1186system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.089088 # mshr miss rate for demand accesses 1187system.cpu.l2cache.demand_mshr_miss_rate::total 0.038021 # mshr miss rate for demand accesses 1188system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011781 # mshr miss rate for overall accesses 1189system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016831 # mshr miss rate for overall accesses 1190system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for overall accesses 1191system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.089088 # mshr miss rate for overall accesses 1192system.cpu.l2cache.overall_mshr_miss_rate::total 0.038021 # mshr miss rate for overall accesses 1193system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average ReadReq mshr miss latency 1194system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average ReadReq mshr miss latency 1195system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77115.501890 # average ReadReq mshr miss latency 1196system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19066.354904 # average UpgradeReq mshr miss latency 1197system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19066.354904 # average UpgradeReq mshr miss latency 1198system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53166.666667 # average SCUpgradeReq mshr miss latency 1199system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency 1200system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72151.110776 # average ReadExReq mshr miss latency 1201system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72151.110776 # average ReadExReq mshr miss latency 1202system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73099.278415 # average ReadCleanReq mshr miss latency 1203system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73099.278415 # average ReadCleanReq mshr miss latency 1204system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74728.074778 # average ReadSharedReq mshr miss latency 1205system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74728.074778 # average ReadSharedReq mshr miss latency 1206system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18660.647163 # average InvalidateReq mshr miss latency 1207system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18660.647163 # average InvalidateReq mshr miss latency 1208system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average overall mshr miss latency 1209system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average overall mshr miss latency 1210system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73099.278415 # average overall mshr miss latency 1211system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73046.183274 # average overall mshr miss latency 1212system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73088.375882 # average overall mshr miss latency 1213system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average overall mshr miss latency 1214system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average overall mshr miss latency 1215system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73099.278415 # average overall mshr miss latency 1216system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73046.183274 # average overall mshr miss latency 1217system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73088.375882 # average overall mshr miss latency 1218system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63172.440580 # average ReadReq mshr uncacheable latency 1219system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172400.967187 # average ReadReq mshr uncacheable latency 1220system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111091.336830 # average ReadReq mshr uncacheable latency 1221system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63172.440580 # average overall mshr uncacheable latency 1222system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86195.369052 # average overall mshr uncacheable latency 1223system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 77213.509015 # average overall mshr uncacheable latency 1224system.cpu.toL2Bus.snoop_filter.tot_requests 48633709 # Total number of requests made to the snoop filter. 1225system.cpu.toL2Bus.snoop_filter.hit_single_requests 24595755 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1206system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205365 # mshr miss rate for ReadExReq accesses 1207system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205365 # mshr miss rate for ReadExReq accesses 1208system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for ReadCleanReq accesses 1209system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005634 # mshr miss rate for ReadCleanReq accesses 1210system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039607 # mshr miss rate for ReadSharedReq accesses 1211system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039607 # mshr miss rate for ReadSharedReq accesses 1212system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405254 # mshr miss rate for InvalidateReq accesses 1213system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.405254 # mshr miss rate for InvalidateReq accesses 1214system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for demand accesses 1215system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for demand accesses 1216system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for demand accesses 1217system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079060 # mshr miss rate for demand accesses 1218system.cpu.l2cache.demand_mshr_miss_rate::total 0.033474 # mshr miss rate for demand accesses 1219system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for overall accesses 1220system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for overall accesses 1221system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for overall accesses 1222system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079060 # mshr miss rate for overall accesses 1223system.cpu.l2cache.overall_mshr_miss_rate::total 0.033474 # mshr miss rate for overall accesses 1224system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average ReadReq mshr miss latency 1225system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average ReadReq mshr miss latency 1226system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 119428.235640 # average ReadReq mshr miss latency 1227system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19040.005048 # average UpgradeReq mshr miss latency 1228system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19040.005048 # average UpgradeReq mshr miss latency 1229system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71250 # average SCUpgradeReq mshr miss latency 1230system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency 1231system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88532.387800 # average ReadExReq mshr miss latency 1232system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88532.387800 # average ReadExReq mshr miss latency 1233system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105441.333211 # average ReadCleanReq mshr miss latency 1234system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105441.333211 # average ReadCleanReq mshr miss latency 1235system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107862.107316 # average ReadSharedReq mshr miss latency 1236system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107862.107316 # average ReadSharedReq mshr miss latency 1237system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18663.276991 # average InvalidateReq mshr miss latency 1238system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18663.276991 # average InvalidateReq mshr miss latency 1239system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average overall mshr miss latency 1240system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average overall mshr miss latency 1241system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency 1242system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95911.082542 # average overall mshr miss latency 1243system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97084.261549 # average overall mshr miss latency 1244system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average overall mshr miss latency 1245system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average overall mshr miss latency 1246system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency 1247system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95911.082542 # average overall mshr miss latency 1248system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97084.261549 # average overall mshr miss latency 1249system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average ReadReq mshr uncacheable latency 1250system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.380822 # average ReadReq mshr uncacheable latency 1251system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.687184 # average ReadReq mshr uncacheable latency 1252system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency 1253system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.076065 # average overall mshr uncacheable latency 1254system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.215576 # average overall mshr uncacheable latency 1255system.cpu.toL2Bus.snoop_filter.tot_requests 46934872 # Total number of requests made to the snoop filter. 1256system.cpu.toL2Bus.snoop_filter.hit_single_requests 23731321 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
1226system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1257system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
1227system.cpu.toL2Bus.snoop_filter.tot_snoops 2030 # Total number of snoops made to the snoop filter. 1228system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2030 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1258system.cpu.toL2Bus.snoop_filter.tot_snoops 1965 # Total number of snoops made to the snoop filter. 1259system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1965 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
1229system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1260system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
1230system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1231system.cpu.toL2Bus.trans_dist::ReadReq 1068832 # Transaction distribution 1232system.cpu.toL2Bus.trans_dist::ReadResp 21713957 # Transaction distribution | 1261system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1262system.cpu.toL2Bus.trans_dist::ReadReq 1010835 # Transaction distribution 1263system.cpu.toL2Bus.trans_dist::ReadResp 20969000 # Transaction distribution |
1233system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution 1234system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution | 1264system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution 1265system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution |
1235system.cpu.toL2Bus.trans_dist::WritebackDirty 9029679 # Transaction distribution 1236system.cpu.toL2Bus.trans_dist::WritebackClean 13792548 # Transaction distribution 1237system.cpu.toL2Bus.trans_dist::CleanEvict 2522886 # Transaction distribution 1238system.cpu.toL2Bus.trans_dist::UpgradeReq 30473 # Transaction distribution 1239system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1240system.cpu.toL2Bus.trans_dist::UpgradeResp 30476 # Transaction distribution 1241system.cpu.toL2Bus.trans_dist::ReadExReq 2160837 # Transaction distribution 1242system.cpu.toL2Bus.trans_dist::ReadExResp 2160837 # Transaction distribution 1243system.cpu.toL2Bus.trans_dist::ReadCleanReq 13793065 # Transaction distribution 1244system.cpu.toL2Bus.trans_dist::ReadSharedReq 6853863 # Transaction distribution 1245system.cpu.toL2Bus.trans_dist::InvalidateReq 1261524 # Transaction distribution 1246system.cpu.toL2Bus.trans_dist::InvalidateResp 1232866 # Transaction distribution 1247system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41464928 # Packet count per connected master and slave (bytes) 1248system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30930790 # Packet count per connected master and slave (bytes) 1249system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 605749 # Packet count per connected master and slave (bytes) 1250system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 980040 # Packet count per connected master and slave (bytes) 1251system.cpu.toL2Bus.pkt_count::total 73981507 # Packet count per connected master and slave (bytes) 1252system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1765651732 # Cumulative packet size per connected master and slave (bytes) 1253system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1083027398 # Cumulative packet size per connected master and slave (bytes) 1254system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1906472 # Cumulative packet size per connected master and slave (bytes) 1255system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2843832 # Cumulative packet size per connected master and slave (bytes) 1256system.cpu.toL2Bus.pkt_size::total 2853429434 # Cumulative packet size per connected master and slave (bytes) 1257system.cpu.toL2Bus.snoops 1738629 # Total snoops (count) 1258system.cpu.toL2Bus.snoopTraffic 75129128 # Total snoop traffic (bytes) 1259system.cpu.toL2Bus.snoop_fanout::samples 26510522 # Request fanout histogram 1260system.cpu.toL2Bus.snoop_fanout::mean 0.020074 # Request fanout histogram 1261system.cpu.toL2Bus.snoop_fanout::stdev 0.140252 # Request fanout histogram | 1266system.cpu.toL2Bus.trans_dist::WritebackDirty 8483175 # Transaction distribution 1267system.cpu.toL2Bus.trans_dist::WritebackClean 13489644 # Transaction distribution 1268system.cpu.toL2Bus.trans_dist::CleanEvict 2388366 # Transaction distribution 1269system.cpu.toL2Bus.trans_dist::UpgradeReq 28800 # Transaction distribution 1270system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1271system.cpu.toL2Bus.trans_dist::UpgradeResp 28802 # Transaction distribution 1272system.cpu.toL2Bus.trans_dist::ReadExReq 2020127 # Transaction distribution 1273system.cpu.toL2Bus.trans_dist::ReadExResp 2020127 # Transaction distribution 1274system.cpu.toL2Bus.trans_dist::ReadCleanReq 13490161 # Transaction distribution 1275system.cpu.toL2Bus.trans_dist::ReadSharedReq 6470086 # Transaction distribution 1276system.cpu.toL2Bus.trans_dist::InvalidateReq 1256693 # Transaction distribution 1277system.cpu.toL2Bus.trans_dist::InvalidateResp 1226147 # Transaction distribution 1278system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40556216 # Packet count per connected master and slave (bytes) 1279system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332974 # Packet count per connected master and slave (bytes) 1280system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592159 # Packet count per connected master and slave (bytes) 1281system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 883944 # Packet count per connected master and slave (bytes) 1282system.cpu.toL2Bus.pkt_count::total 71365293 # Packet count per connected master and slave (bytes) 1283system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726880020 # Cumulative packet size per connected master and slave (bytes) 1284system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023309382 # Cumulative packet size per connected master and slave (bytes) 1285system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1851200 # Cumulative packet size per connected master and slave (bytes) 1286system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2485592 # Cumulative packet size per connected master and slave (bytes) 1287system.cpu.toL2Bus.pkt_size::total 2754526194 # Cumulative packet size per connected master and slave (bytes) 1288system.cpu.toL2Bus.snoops 1584975 # Total snoops (count) 1289system.cpu.toL2Bus.snoopTraffic 66236232 # Total snoop traffic (bytes) 1290system.cpu.toL2Bus.snoop_fanout::samples 25469090 # Request fanout histogram 1291system.cpu.toL2Bus.snoop_fanout::mean 0.019778 # Request fanout histogram 1292system.cpu.toL2Bus.snoop_fanout::stdev 0.139236 # Request fanout histogram |
1262system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1293system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
1263system.cpu.toL2Bus.snoop_fanout::0 25978363 97.99% 97.99% # Request fanout histogram 1264system.cpu.toL2Bus.snoop_fanout::1 532159 2.01% 100.00% # Request fanout histogram | 1294system.cpu.toL2Bus.snoop_fanout::0 24965367 98.02% 98.02% # Request fanout histogram 1295system.cpu.toL2Bus.snoop_fanout::1 503723 1.98% 100.00% # Request fanout histogram |
1265system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1266system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1267system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1268system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1296system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1297system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1298system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1299system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
1269system.cpu.toL2Bus.snoop_fanout::total 26510522 # Request fanout histogram 1270system.cpu.toL2Bus.reqLayer0.occupancy 46319770000 # Layer occupancy (ticks) | 1300system.cpu.toL2Bus.snoop_fanout::total 25469090 # Request fanout histogram 1301system.cpu.toL2Bus.reqLayer0.occupancy 44744307000 # Layer occupancy (ticks) |
1271system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1302system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
1272system.cpu.toL2Bus.snoopLayer0.occupancy 1608386 # Layer occupancy (ticks) | 1303system.cpu.toL2Bus.snoopLayer0.occupancy 1625890 # Layer occupancy (ticks) |
1273system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1304system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
1274system.cpu.toL2Bus.respLayer0.occupancy 20732722500 # Layer occupancy (ticks) | 1305system.cpu.toL2Bus.respLayer0.occupancy 20278366500 # Layer occupancy (ticks) |
1275system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1306system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
1276system.cpu.toL2Bus.respLayer1.occupancy 14200291468 # Layer occupancy (ticks) | 1307system.cpu.toL2Bus.respLayer1.occupancy 13408934951 # Layer occupancy (ticks) |
1277system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1308system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
1278system.cpu.toL2Bus.respLayer2.occupancy 367440000 # Layer occupancy (ticks) | 1309system.cpu.toL2Bus.respLayer2.occupancy 360759000 # Layer occupancy (ticks) |
1279system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1310system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
1280system.cpu.toL2Bus.respLayer3.occupancy 624561000 # Layer occupancy (ticks) | 1311system.cpu.toL2Bus.respLayer3.occupancy 573245000 # Layer occupancy (ticks) |
1281system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1312system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
1282system.iobus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1283system.iobus.trans_dist::ReadReq 40312 # Transaction distribution 1284system.iobus.trans_dist::ReadResp 40312 # Transaction distribution | 1313system.iobus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1314system.iobus.trans_dist::ReadReq 40346 # Transaction distribution 1315system.iobus.trans_dist::ReadResp 40346 # Transaction distribution |
1285system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1286system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1287system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1288system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1289system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1290system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1291system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1292system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1293system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1294system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1295system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1296system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1297system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1298system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1299system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1300system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) | 1316system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1317system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1318system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1319system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1320system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1321system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1322system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1323system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1324system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1325system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1326system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1327system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1328system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1329system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1330system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1331system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) |
1301system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230982 # Packet count per connected master and slave (bytes) 1302system.iobus.pkt_count_system.realview.ide.dma::total 230982 # Packet count per connected master and slave (bytes) | 1332system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes) 1333system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes) |
1303system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1304system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 1334system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1335system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
1305system.iobus.pkt_count::total 353766 # Packet count per connected master and slave (bytes) | 1336system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) |
1306system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1307system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1308system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1309system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1310system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1311system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1312system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1313system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1314system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1315system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1316system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1317system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1318system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1319system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) | 1337system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1338system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1339system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1340system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1341system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1342system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1343system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1344system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1345system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1346system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1347system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1348system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1349system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1350system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) |
1320system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334360 # Cumulative packet size per connected master and slave (bytes) 1321system.iobus.pkt_size_system.realview.ide.dma::total 7334360 # Cumulative packet size per connected master and slave (bytes) | 1351system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes) 1352system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes) |
1322system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1323system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 1353system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1354system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
1324system.iobus.pkt_size::total 7492280 # Cumulative packet size per connected master and slave (bytes) 1325system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) | 1355system.iobus.pkt_size::total 7492552 # Cumulative packet size per connected master and slave (bytes) 1356system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) |
1326system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1357system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
1327system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) | 1358system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) |
1328system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1359system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
1329system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) | 1360system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) |
1330system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1331system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1332system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1333system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) 1334system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1335system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 1336system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1337system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 1338system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1339system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 1340system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1341system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1342system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1343system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 1344system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1345system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1346system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 1361system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1362system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1363system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1364system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) 1365system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1366system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 1367system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1368system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 1369system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1370system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 1371system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1372system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1373system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1374system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 1375system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1376system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1377system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
1347system.iobus.reqLayer23.occupancy 25722000 # Layer occupancy (ticks) | 1378system.iobus.reqLayer23.occupancy 25714500 # Layer occupancy (ticks) |
1348system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1379system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
1349system.iobus.reqLayer24.occupancy 38610500 # Layer occupancy (ticks) | 1380system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks) |
1350system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1381system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
1351system.iobus.reqLayer25.occupancy 568931558 # Layer occupancy (ticks) | 1382system.iobus.reqLayer25.occupancy 569287162 # Layer occupancy (ticks) |
1352system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1353system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1354system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1383system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1384system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1385system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
1355system.iobus.respLayer3.occupancy 147742000 # Layer occupancy (ticks) | 1386system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks) |
1356system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1357system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1358system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 1387system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1388system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1389system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
1359system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1360system.iocache.tags.replacements 115472 # number of replacements 1361system.iocache.tags.tagsinuse 10.457340 # Cycle average of tags in use | 1390system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1391system.iocache.tags.replacements 115506 # number of replacements 1392system.iocache.tags.tagsinuse 10.457104 # Cycle average of tags in use |
1362system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 1393system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
1363system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks. | 1394system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. |
1364system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 1395system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
1365system.iocache.tags.warmup_cycle 13153794616000 # Cycle when the warmup percentage was hit. 1366system.iocache.tags.occ_blocks::realview.ethernet 3.511175 # Average occupied blocks per requestor 1367system.iocache.tags.occ_blocks::realview.ide 6.946165 # Average occupied blocks per requestor 1368system.iocache.tags.occ_percent::realview.ethernet 0.219448 # Average percentage of cache occupancy 1369system.iocache.tags.occ_percent::realview.ide 0.434135 # Average percentage of cache occupancy 1370system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy | 1396system.iocache.tags.warmup_cycle 13154766855000 # Cycle when the warmup percentage was hit. 1397system.iocache.tags.occ_blocks::realview.ethernet 3.510739 # Average occupied blocks per requestor 1398system.iocache.tags.occ_blocks::realview.ide 6.946366 # Average occupied blocks per requestor 1399system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy 1400system.iocache.tags.occ_percent::realview.ide 0.434148 # Average percentage of cache occupancy 1401system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy |
1371system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1372system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1373system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1402system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1403system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1404system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
1374system.iocache.tags.tag_accesses 1039776 # Number of tag accesses 1375system.iocache.tags.data_accesses 1039776 # Number of data accesses 1376system.iocache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 1405system.iocache.tags.tag_accesses 1040082 # Number of tag accesses 1406system.iocache.tags.data_accesses 1040082 # Number of data accesses 1407system.iocache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
1377system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 1408system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
1378system.iocache.ReadReq_misses::realview.ide 8827 # number of ReadReq misses 1379system.iocache.ReadReq_misses::total 8864 # number of ReadReq misses | 1409system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses 1410system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses |
1380system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1381system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1382system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1383system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1384system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1411system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1412system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1413system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1414system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1415system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
1385system.iocache.demand_misses::realview.ide 115491 # number of demand (read+write) misses 1386system.iocache.demand_misses::total 115531 # number of demand (read+write) misses | 1416system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses 1417system.iocache.demand_misses::total 115565 # number of demand (read+write) misses |
1387system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1418system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
1388system.iocache.overall_misses::realview.ide 115491 # number of overall misses 1389system.iocache.overall_misses::total 115531 # number of overall misses 1390system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles 1391system.iocache.ReadReq_miss_latency::realview.ide 1606262152 # number of ReadReq miss cycles 1392system.iocache.ReadReq_miss_latency::total 1611348152 # number of ReadReq miss cycles | 1419system.iocache.overall_misses::realview.ide 115525 # number of overall misses 1420system.iocache.overall_misses::total 115565 # number of overall misses 1421system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles 1422system.iocache.ReadReq_miss_latency::realview.ide 2019214145 # number of ReadReq miss cycles 1423system.iocache.ReadReq_miss_latency::total 2024300645 # number of ReadReq miss cycles |
1393system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1394system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles | 1424system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1425system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles |
1395system.iocache.WriteLineReq_miss_latency::realview.ide 12771737406 # number of WriteLineReq miss cycles 1396system.iocache.WriteLineReq_miss_latency::total 12771737406 # number of WriteLineReq miss cycles 1397system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles 1398system.iocache.demand_miss_latency::realview.ide 14377999558 # number of demand (read+write) miss cycles 1399system.iocache.demand_miss_latency::total 14383436558 # number of demand (read+write) miss cycles 1400system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles 1401system.iocache.overall_miss_latency::realview.ide 14377999558 # number of overall miss cycles 1402system.iocache.overall_miss_latency::total 14383436558 # number of overall miss cycles | 1426system.iocache.WriteLineReq_miss_latency::realview.ide 13409527517 # number of WriteLineReq miss cycles 1427system.iocache.WriteLineReq_miss_latency::total 13409527517 # number of WriteLineReq miss cycles 1428system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles 1429system.iocache.demand_miss_latency::realview.ide 15428741662 # number of demand (read+write) miss cycles 1430system.iocache.demand_miss_latency::total 15434179162 # number of demand (read+write) miss cycles 1431system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles 1432system.iocache.overall_miss_latency::realview.ide 15428741662 # number of overall miss cycles 1433system.iocache.overall_miss_latency::total 15434179162 # number of overall miss cycles |
1403system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 1434system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
1404system.iocache.ReadReq_accesses::realview.ide 8827 # number of ReadReq accesses(hits+misses) 1405system.iocache.ReadReq_accesses::total 8864 # number of ReadReq accesses(hits+misses) | 1435system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses) 1436system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses) |
1406system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1407system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1408system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1409system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1410system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1437system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1438system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1439system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1440system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1441system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
1411system.iocache.demand_accesses::realview.ide 115491 # number of demand (read+write) accesses 1412system.iocache.demand_accesses::total 115531 # number of demand (read+write) accesses | 1442system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses 1443system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses |
1413system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1444system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
1414system.iocache.overall_accesses::realview.ide 115491 # number of overall (read+write) accesses 1415system.iocache.overall_accesses::total 115531 # number of overall (read+write) accesses | 1445system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses 1446system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses |
1416system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1417system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1418system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1419system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1420system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1421system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1422system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1423system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1424system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1425system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1426system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1427system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1428system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1447system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1448system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1449system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1450system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1451system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1452system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1453system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1454system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1455system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1456system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1457system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1458system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1459system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
1429system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency 1430system.iocache.ReadReq_avg_miss_latency::realview.ide 181971.468449 # average ReadReq miss latency 1431system.iocache.ReadReq_avg_miss_latency::total 181785.666968 # average ReadReq miss latency | 1460system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency 1461system.iocache.ReadReq_avg_miss_latency::realview.ide 227876.554001 # average ReadReq miss latency 1462system.iocache.ReadReq_avg_miss_latency::total 227500.634412 # average ReadReq miss latency |
1432system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1433system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency | 1463system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1464system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency |
1434system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119738.031632 # average WriteLineReq miss latency 1435system.iocache.WriteLineReq_avg_miss_latency::total 119738.031632 # average WriteLineReq miss latency 1436system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 1437system.iocache.demand_avg_miss_latency::realview.ide 124494.545532 # average overall miss latency 1438system.iocache.demand_avg_miss_latency::total 124498.503068 # average overall miss latency 1439system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 1440system.iocache.overall_avg_miss_latency::realview.ide 124494.545532 # average overall miss latency 1441system.iocache.overall_avg_miss_latency::total 124498.503068 # average overall miss latency 1442system.iocache.blocked_cycles::no_mshrs 31144 # number of cycles access was blocked | 1465system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.463408 # average WriteLineReq miss latency 1466system.iocache.WriteLineReq_avg_miss_latency::total 125717.463408 # average WriteLineReq miss latency 1467system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency 1468system.iocache.demand_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency 1469system.iocache.demand_avg_miss_latency::total 133554.096500 # average overall miss latency 1470system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency 1471system.iocache.overall_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency 1472system.iocache.overall_avg_miss_latency::total 133554.096500 # average overall miss latency 1473system.iocache.blocked_cycles::no_mshrs 51750 # number of cycles access was blocked |
1443system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1474system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1444system.iocache.blocked::no_mshrs 3368 # number of cycles access was blocked | 1475system.iocache.blocked::no_mshrs 3356 # number of cycles access was blocked |
1445system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1476system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
1446system.iocache.avg_blocked_cycles::no_mshrs 9.247031 # average number of cycles each access was blocked | 1477system.iocache.avg_blocked_cycles::no_mshrs 15.420143 # average number of cycles each access was blocked |
1447system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1448system.iocache.writebacks::writebacks 106630 # number of writebacks 1449system.iocache.writebacks::total 106630 # number of writebacks 1450system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses | 1478system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1479system.iocache.writebacks::writebacks 106630 # number of writebacks 1480system.iocache.writebacks::total 106630 # number of writebacks 1481system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
1451system.iocache.ReadReq_mshr_misses::realview.ide 8827 # number of ReadReq MSHR misses 1452system.iocache.ReadReq_mshr_misses::total 8864 # number of ReadReq MSHR misses | 1482system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses 1483system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses |
1453system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1454system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1455system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1456system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1457system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 1484system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1485system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1486system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1487system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1488system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
1458system.iocache.demand_mshr_misses::realview.ide 115491 # number of demand (read+write) MSHR misses 1459system.iocache.demand_mshr_misses::total 115531 # number of demand (read+write) MSHR misses | 1489system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses 1490system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses |
1460system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 1491system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
1461system.iocache.overall_mshr_misses::realview.ide 115491 # number of overall MSHR misses 1462system.iocache.overall_mshr_misses::total 115531 # number of overall MSHR misses 1463system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles 1464system.iocache.ReadReq_mshr_miss_latency::realview.ide 1164912152 # number of ReadReq MSHR miss cycles 1465system.iocache.ReadReq_mshr_miss_latency::total 1168148152 # number of ReadReq MSHR miss cycles | 1492system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses 1493system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses 1494system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles 1495system.iocache.ReadReq_mshr_miss_latency::realview.ide 1576164145 # number of ReadReq MSHR miss cycles 1496system.iocache.ReadReq_mshr_miss_latency::total 1579400645 # number of ReadReq MSHR miss cycles |
1466system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1467system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles | 1497system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1498system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles |
1468system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7431704095 # number of WriteLineReq MSHR miss cycles 1469system.iocache.WriteLineReq_mshr_miss_latency::total 7431704095 # number of WriteLineReq MSHR miss cycles 1470system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles 1471system.iocache.demand_mshr_miss_latency::realview.ide 8596616247 # number of demand (read+write) MSHR miss cycles 1472system.iocache.demand_mshr_miss_latency::total 8600053247 # number of demand (read+write) MSHR miss cycles 1473system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles 1474system.iocache.overall_mshr_miss_latency::realview.ide 8596616247 # number of overall MSHR miss cycles 1475system.iocache.overall_mshr_miss_latency::total 8600053247 # number of overall MSHR miss cycles | 1499system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8069228353 # number of WriteLineReq MSHR miss cycles 1500system.iocache.WriteLineReq_mshr_miss_latency::total 8069228353 # number of WriteLineReq MSHR miss cycles 1501system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles 1502system.iocache.demand_mshr_miss_latency::realview.ide 9645392498 # number of demand (read+write) MSHR miss cycles 1503system.iocache.demand_mshr_miss_latency::total 9648829998 # number of demand (read+write) MSHR miss cycles 1504system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles 1505system.iocache.overall_mshr_miss_latency::realview.ide 9645392498 # number of overall MSHR miss cycles 1506system.iocache.overall_mshr_miss_latency::total 9648829998 # number of overall MSHR miss cycles |
1476system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1477system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1478system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1479system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1480system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1481system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1482system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1483system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1484system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1485system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1486system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1487system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1488system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1507system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1508system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1509system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1510system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1511system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1512system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1513system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1514system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1515system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1516system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1517system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1518system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1519system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
1489system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency 1490system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131971.468449 # average ReadReq mshr miss latency 1491system.iocache.ReadReq_avg_mshr_miss_latency::total 131785.666968 # average ReadReq mshr miss latency | 1520system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency 1521system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177876.554001 # average ReadReq mshr miss latency 1522system.iocache.ReadReq_avg_mshr_miss_latency::total 177500.634412 # average ReadReq mshr miss latency |
1492system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1493system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency | 1523system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1524system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency |
1494system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69673.967740 # average WriteLineReq mshr miss latency 1495system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69673.967740 # average WriteLineReq mshr miss latency 1496system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 1497system.iocache.demand_avg_mshr_miss_latency::realview.ide 74435.378055 # average overall mshr miss latency 1498system.iocache.demand_avg_mshr_miss_latency::total 74439.356078 # average overall mshr miss latency 1499system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 1500system.iocache.overall_avg_mshr_miss_latency::realview.ide 74435.378055 # average overall mshr miss latency 1501system.iocache.overall_avg_mshr_miss_latency::total 74439.356078 # average overall mshr miss latency 1502system.membus.snoop_filter.tot_requests 2941993 # Total number of requests made to the snoop filter. 1503system.membus.snoop_filter.hit_single_requests 1455813 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1504system.membus.snoop_filter.hit_multi_requests 3308 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1525system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75650.907082 # average WriteLineReq mshr miss latency 1526system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75650.907082 # average WriteLineReq mshr miss latency 1527system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency 1528system.iocache.demand_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency 1529system.iocache.demand_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency 1530system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency 1531system.iocache.overall_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency 1532system.iocache.overall_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency 1533system.membus.snoop_filter.tot_requests 2643885 # Total number of requests made to the snoop filter. 1534system.membus.snoop_filter.hit_single_requests 1308749 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1535system.membus.snoop_filter.hit_multi_requests 3600 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
1505system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1506system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1507system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1536system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1537system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1538system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
1508system.membus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 1539system.membus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
1509system.membus.trans_dist::ReadReq 76831 # Transaction distribution | 1540system.membus.trans_dist::ReadReq 76831 # Transaction distribution |
1510system.membus.trans_dist::ReadResp 451336 # Transaction distribution | 1541system.membus.trans_dist::ReadResp 424674 # Transaction distribution |
1511system.membus.trans_dist::WriteReq 33710 # Transaction distribution 1512system.membus.trans_dist::WriteResp 33710 # Transaction distribution | 1542system.membus.trans_dist::WriteReq 33710 # Transaction distribution 1543system.membus.trans_dist::WriteResp 33710 # Transaction distribution |
1513system.membus.trans_dist::WritebackDirty 1229879 # Transaction distribution 1514system.membus.trans_dist::CleanEvict 192681 # Transaction distribution 1515system.membus.trans_dist::UpgradeReq 4527 # Transaction distribution 1516system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution | 1544system.membus.trans_dist::WritebackDirty 1091703 # Transaction distribution 1545system.membus.trans_dist::CleanEvict 181416 # Transaction distribution 1546system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution 1547system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
1517system.membus.trans_dist::UpgradeResp 8 # Transaction distribution | 1548system.membus.trans_dist::UpgradeResp 8 # Transaction distribution |
1518system.membus.trans_dist::ReadExReq 523443 # Transaction distribution 1519system.membus.trans_dist::ReadExResp 523443 # Transaction distribution 1520system.membus.trans_dist::ReadSharedReq 374505 # Transaction distribution 1521system.membus.trans_dist::InvalidateReq 616914 # Transaction distribution | 1549system.membus.trans_dist::ReadExReq 414305 # Transaction distribution 1550system.membus.trans_dist::ReadExResp 414305 # Transaction distribution 1551system.membus.trans_dist::ReadSharedReq 347843 # Transaction distribution 1552system.membus.trans_dist::InvalidateReq 603558 # Transaction distribution |
1522system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1523system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1524system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) | 1553system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1554system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1555system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) |
1525system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3690757 # Packet count per connected master and slave (bytes) 1526system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3820461 # Packet count per connected master and slave (bytes) 1527system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237403 # Packet count per connected master and slave (bytes) 1528system.membus.pkt_count_system.iocache.mem_side::total 237403 # Packet count per connected master and slave (bytes) 1529system.membus.pkt_count::total 4057864 # Packet count per connected master and slave (bytes) | 1556system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256260 # Packet count per connected master and slave (bytes) 1557system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385964 # Packet count per connected master and slave (bytes) 1558system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237234 # Packet count per connected master and slave (bytes) 1559system.membus.pkt_count_system.iocache.mem_side::total 237234 # Packet count per connected master and slave (bytes) 1560system.membus.pkt_count::total 3623198 # Packet count per connected master and slave (bytes) |
1530system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1531system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1532system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) | 1561system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1562system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1563system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) |
1533system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 128940576 # Cumulative packet size per connected master and slave (bytes) 1534system.membus.pkt_size_system.cpu.l2cache.mem_side::total 129110426 # Cumulative packet size per connected master and slave (bytes) 1535system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233920 # Cumulative packet size per connected master and slave (bytes) 1536system.membus.pkt_size_system.iocache.mem_side::total 7233920 # Cumulative packet size per connected master and slave (bytes) 1537system.membus.pkt_size::total 136344346 # Cumulative packet size per connected master and slave (bytes) 1538system.membus.snoops 3126 # Total snoops (count) 1539system.membus.snoopTraffic 199552 # Total snoop traffic (bytes) 1540system.membus.snoop_fanout::samples 1629933 # Request fanout histogram 1541system.membus.snoop_fanout::mean 0.019638 # Request fanout histogram 1542system.membus.snoop_fanout::stdev 0.138754 # Request fanout histogram | 1564system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111403936 # Cumulative packet size per connected master and slave (bytes) 1565system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111573786 # Cumulative packet size per connected master and slave (bytes) 1566system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes) 1567system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes) 1568system.membus.pkt_size::total 118792538 # Cumulative packet size per connected master and slave (bytes) 1569system.membus.snoops 3397 # Total snoops (count) 1570system.membus.snoopTraffic 216896 # Total snoop traffic (bytes) 1571system.membus.snoop_fanout::samples 1480779 # Request fanout histogram 1572system.membus.snoop_fanout::mean 0.023089 # Request fanout histogram 1573system.membus.snoop_fanout::stdev 0.150185 # Request fanout histogram |
1543system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1574system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
1544system.membus.snoop_fanout::0 1597924 98.04% 98.04% # Request fanout histogram 1545system.membus.snoop_fanout::1 32009 1.96% 100.00% # Request fanout histogram | 1575system.membus.snoop_fanout::0 1446590 97.69% 97.69% # Request fanout histogram 1576system.membus.snoop_fanout::1 34189 2.31% 100.00% # Request fanout histogram |
1546system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1547system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1548system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1549system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1577system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1578system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1579system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1580system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
1550system.membus.snoop_fanout::total 1629933 # Request fanout histogram 1551system.membus.reqLayer0.occupancy 106906500 # Layer occupancy (ticks) | 1581system.membus.snoop_fanout::total 1480779 # Request fanout histogram 1582system.membus.reqLayer0.occupancy 106893000 # Layer occupancy (ticks) |
1552system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1553system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1554system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1583system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1584system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1585system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
1555system.membus.reqLayer2.occupancy 5804000 # Layer occupancy (ticks) | 1586system.membus.reqLayer2.occupancy 5820500 # Layer occupancy (ticks) |
1556system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1587system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
1557system.membus.reqLayer5.occupancy 8036011189 # Layer occupancy (ticks) | 1588system.membus.reqLayer5.occupancy 7180364209 # Layer occupancy (ticks) |
1558system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1589system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
1559system.membus.respLayer2.occupancy 4923968289 # Layer occupancy (ticks) | 1590system.membus.respLayer2.occupancy 4203282304 # Layer occupancy (ticks) |
1560system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1591system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
1561system.membus.respLayer3.occupancy 44661763 # Layer occupancy (ticks) | 1592system.membus.respLayer3.occupancy 44877398 # Layer occupancy (ticks) |
1562system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1593system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
1563system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1564system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1565system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1566system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1567system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1568system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1569system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 1594system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1595system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1596system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1597system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1598system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1599system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1600system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
1570system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1571system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1572system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1573system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1574system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1575system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1601system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1602system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1603system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1604system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1605system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1606system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
1576system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1577system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 1607system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1608system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
1578system.realview.ethernet.txBytes 966 # Bytes Transmitted 1579system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1580system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1581system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1582system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1583system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1584system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1585system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1612system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1613system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1614system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1615system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1616system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1617system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1618system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1619system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1609system.realview.ethernet.txBytes 966 # Bytes Transmitted 1610system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1611system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1612system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1613system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1614system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1615system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1616system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1643system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1644system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1645system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1646system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1647system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1648system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1649system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1650system.realview.ethernet.droppedPackets 0 # number of packets dropped |
1620system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1621system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1622system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1623system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1624system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1625system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1626system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 1651system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1652system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1653system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1654system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1655system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1656system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1657system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
1627system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1628system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1629system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1630system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1658system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1659system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1660system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1661system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
1631system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1632system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1633system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1634system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1635system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1636system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1637system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1638system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1639system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1640system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1641system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states 1642system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states | 1662system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1663system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1664system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1665system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1666system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1667system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1668system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1669system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1670system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1671system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1672system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states 1673system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states |
1643 1644---------- End Simulation Statistics ---------- | 1674 1675---------- End Simulation Statistics ---------- |