| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.759374 # Number of seconds simulated 4sim_ticks 51759374264500 # Number of ticks simulated 5final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.759374 # Number of seconds simulated 4sim_ticks 51759374264500 # Number of ticks simulated 5final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1051370 # Simulator instruction rate (inst/s) 8host_op_rate 1235514 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 65021013988 # Simulator tick rate (ticks/s) 10host_mem_usage 718040 # Number of bytes of host memory used 11host_seconds 796.04 # Real time elapsed on the host | 7host_inst_rate 622194 # Simulator instruction rate (inst/s) 8host_op_rate 731170 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38479042536 # Simulator tick rate (ticks/s) 10host_mem_usage 677104 # Number of bytes of host memory used 11host_seconds 1345.13 # Real time elapsed on the host |
| 12sim_insts 836933434 # Number of instructions simulated 13sim_ops 983519389 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory --- 407 unchanged lines hidden (view full) --- 427system.cpu.dtb.read_hits 157500215 # DTB read hits 428system.cpu.dtb.read_misses 138721 # DTB read misses 429system.cpu.dtb.write_hits 142992331 # DTB write hits 430system.cpu.dtb.write_misses 48490 # DTB write misses 431system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 432system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 433system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 434system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID | 12sim_insts 836933434 # Number of instructions simulated 13sim_ops 983519389 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory --- 407 unchanged lines hidden (view full) --- 427system.cpu.dtb.read_hits 157500215 # DTB read hits 428system.cpu.dtb.read_misses 138721 # DTB read misses 429system.cpu.dtb.write_hits 142992331 # DTB write hits 430system.cpu.dtb.write_misses 48490 # DTB write misses 431system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 432system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 433system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 434system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID |
| 435system.cpu.dtb.flush_entries 71001 # Number of entries that have been flushed from TLB | 435system.cpu.dtb.flush_entries 70937 # Number of entries that have been flushed from TLB |
| 436system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 437system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch 438system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 439system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions 440system.cpu.dtb.read_accesses 157638936 # DTB read accesses 441system.cpu.dtb.write_accesses 143040821 # DTB write accesses 442system.cpu.dtb.inst_accesses 0 # ITB inst accesses 443system.cpu.dtb.hits 300492546 # DTB hits --- 71 unchanged lines hidden (view full) --- 515system.cpu.itb.read_hits 0 # DTB read hits 516system.cpu.itb.read_misses 0 # DTB read misses 517system.cpu.itb.write_hits 0 # DTB write hits 518system.cpu.itb.write_misses 0 # DTB write misses 519system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 520system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 521system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 522system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID | 436system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 437system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch 438system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 439system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions 440system.cpu.dtb.read_accesses 157638936 # DTB read accesses 441system.cpu.dtb.write_accesses 143040821 # DTB write accesses 442system.cpu.dtb.inst_accesses 0 # ITB inst accesses 443system.cpu.dtb.hits 300492546 # DTB hits --- 71 unchanged lines hidden (view full) --- 515system.cpu.itb.read_hits 0 # DTB read hits 516system.cpu.itb.read_misses 0 # DTB read misses 517system.cpu.itb.write_hits 0 # DTB write hits 518system.cpu.itb.write_misses 0 # DTB write misses 519system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 520system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 521system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 522system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID |
| 523system.cpu.itb.flush_entries 50677 # Number of entries that have been flushed from TLB | 523system.cpu.itb.flush_entries 50613 # Number of entries that have been flushed from TLB |
| 524system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 525system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 526system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 527system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 528system.cpu.itb.read_accesses 0 # DTB read accesses 529system.cpu.itb.write_accesses 0 # DTB write accesses 530system.cpu.itb.inst_accesses 837568735 # ITB inst accesses 531system.cpu.itb.hits 837449249 # DTB hits --- 1119 unchanged lines hidden --- | 524system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 525system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 526system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 527system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 528system.cpu.itb.read_accesses 0 # DTB read accesses 529system.cpu.itb.write_accesses 0 # DTB write accesses 530system.cpu.itb.inst_accesses 837568735 # ITB inst accesses 531system.cpu.itb.hits 837449249 # DTB hits --- 1119 unchanged lines hidden --- |