| stats.txt (11336:b318499f676c) | stats.txt (11353:31c5786945b4) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 51.811400 # Number of seconds simulated 4sim_ticks 51811399994500 # Number of ticks simulated 5final_tick 51811399994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 51.759374 # Number of seconds simulated 4sim_ticks 51759374264500 # Number of ticks simulated 5final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 805770 # Simulator instruction rate (inst/s) 8host_op_rate 946938 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 50389185573 # Simulator tick rate (ticks/s) 10host_mem_usage 678984 # Number of bytes of host memory used 11host_seconds 1028.22 # Real time elapsed on the host 12sim_insts 828512987 # Number of instructions simulated 13sim_ops 973664549 # Number of ops (including micro ops) simulated | 7host_inst_rate 1125548 # Simulator instruction rate (inst/s) 8host_op_rate 1322684 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 69608471837 # Simulator tick rate (ticks/s) 10host_mem_usage 675480 # Number of bytes of host memory used 11host_seconds 743.58 # Real time elapsed on the host 12sim_insts 836933434 # Number of instructions simulated 13sim_ops 983519389 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 141952 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 4623732 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 65034376 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 398080 # Number of bytes read from this memory 21system.physmem.bytes_read::total 70331708 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 4623732 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 4623732 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 61230400 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory 21system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 63133056 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 61250980 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2218 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 112653 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1016175 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6220 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1139353 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 956725 # Number of write requests responded to by this memory | 26system.physmem.bytes_written::total 63153636 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 2426 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2490 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 114528 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 567741 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6242 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 693427 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 986454 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory | 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 959298 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 2740 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 89242 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1255214 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7683 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1357456 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 89242 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 89242 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1181794 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1182191 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1181794 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 2740 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 89242 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1255611 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7683 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 2539647 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1139353 # Number of read requests accepted 55system.physmem.writeReqs 959298 # Number of write requests accepted 56system.physmem.readBursts 1139353 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 959298 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 72868032 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 50560 # Total number of bytes read from write queue 60system.physmem.bytesWritten 61249856 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 70331708 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 61250980 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 790 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one | 35system.physmem.num_writes::total 989027 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 3000 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 91650 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 701991 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7718 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 807437 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 91650 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 91650 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1219741 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1220139 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1219741 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 3000 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 91650 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 702388 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7718 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 2027576 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 693427 # Number of read requests accepted 55system.physmem.writeReqs 989027 # Number of write requests accepted 56system.physmem.readBursts 693427 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 989027 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 44328448 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 50880 # Total number of bytes read from write queue 60system.physmem.bytesWritten 63152448 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 41792444 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 63153636 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 795 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one |
| 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 66system.physmem.perBankRdBursts::0 69574 # Per bank write bursts 67system.physmem.perBankRdBursts::1 73483 # Per bank write bursts 68system.physmem.perBankRdBursts::2 70905 # Per bank write bursts 69system.physmem.perBankRdBursts::3 67568 # Per bank write bursts 70system.physmem.perBankRdBursts::4 64326 # Per bank write bursts 71system.physmem.perBankRdBursts::5 70688 # Per bank write bursts 72system.physmem.perBankRdBursts::6 65575 # Per bank write bursts 73system.physmem.perBankRdBursts::7 64409 # Per bank write bursts 74system.physmem.perBankRdBursts::8 65562 # Per bank write bursts 75system.physmem.perBankRdBursts::9 110058 # Per bank write bursts 76system.physmem.perBankRdBursts::10 69387 # Per bank write bursts 77system.physmem.perBankRdBursts::11 70852 # Per bank write bursts 78system.physmem.perBankRdBursts::12 67727 # Per bank write bursts 79system.physmem.perBankRdBursts::13 71395 # Per bank write bursts 80system.physmem.perBankRdBursts::14 70177 # Per bank write bursts 81system.physmem.perBankRdBursts::15 66877 # Per bank write bursts 82system.physmem.perBankWrBursts::0 57914 # Per bank write bursts 83system.physmem.perBankWrBursts::1 61200 # Per bank write bursts 84system.physmem.perBankWrBursts::2 60974 # Per bank write bursts 85system.physmem.perBankWrBursts::3 59703 # Per bank write bursts 86system.physmem.perBankWrBursts::4 56782 # Per bank write bursts 87system.physmem.perBankWrBursts::5 61096 # Per bank write bursts 88system.physmem.perBankWrBursts::6 57709 # Per bank write bursts 89system.physmem.perBankWrBursts::7 57516 # Per bank write bursts 90system.physmem.perBankWrBursts::8 58389 # Per bank write bursts 91system.physmem.perBankWrBursts::9 61168 # Per bank write bursts 92system.physmem.perBankWrBursts::10 60736 # Per bank write bursts 93system.physmem.perBankWrBursts::11 62143 # Per bank write bursts 94system.physmem.perBankWrBursts::12 59319 # Per bank write bursts 95system.physmem.perBankWrBursts::13 62705 # Per bank write bursts 96system.physmem.perBankWrBursts::14 61087 # Per bank write bursts 97system.physmem.perBankWrBursts::15 58588 # Per bank write bursts | 66system.physmem.perBankRdBursts::0 40853 # Per bank write bursts 67system.physmem.perBankRdBursts::1 42497 # Per bank write bursts 68system.physmem.perBankRdBursts::2 39380 # Per bank write bursts 69system.physmem.perBankRdBursts::3 40815 # Per bank write bursts 70system.physmem.perBankRdBursts::4 36874 # Per bank write bursts 71system.physmem.perBankRdBursts::5 45606 # Per bank write bursts 72system.physmem.perBankRdBursts::6 38207 # Per bank write bursts 73system.physmem.perBankRdBursts::7 36804 # Per bank write bursts 74system.physmem.perBankRdBursts::8 38817 # Per bank write bursts 75system.physmem.perBankRdBursts::9 83381 # Per bank write bursts 76system.physmem.perBankRdBursts::10 47849 # Per bank write bursts 77system.physmem.perBankRdBursts::11 45678 # Per bank write bursts 78system.physmem.perBankRdBursts::12 39735 # Per bank write bursts 79system.physmem.perBankRdBursts::13 40223 # Per bank write bursts 80system.physmem.perBankRdBursts::14 37028 # Per bank write bursts 81system.physmem.perBankRdBursts::15 38885 # Per bank write bursts 82system.physmem.perBankWrBursts::0 61132 # Per bank write bursts 83system.physmem.perBankWrBursts::1 62574 # Per bank write bursts 84system.physmem.perBankWrBursts::2 60681 # Per bank write bursts 85system.physmem.perBankWrBursts::3 62576 # Per bank write bursts 86system.physmem.perBankWrBursts::4 57559 # Per bank write bursts 87system.physmem.perBankWrBursts::5 64093 # Per bank write bursts 88system.physmem.perBankWrBursts::6 59756 # Per bank write bursts 89system.physmem.perBankWrBursts::7 59796 # Per bank write bursts 90system.physmem.perBankWrBursts::8 61252 # Per bank write bursts 91system.physmem.perBankWrBursts::9 63246 # Per bank write bursts 92system.physmem.perBankWrBursts::10 66784 # Per bank write bursts 93system.physmem.perBankWrBursts::11 64593 # Per bank write bursts 94system.physmem.perBankWrBursts::12 60371 # Per bank write bursts 95system.physmem.perBankWrBursts::13 61779 # Per bank write bursts 96system.physmem.perBankWrBursts::14 59591 # Per bank write bursts 97system.physmem.perBankWrBursts::15 60974 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 61 # Number of times write queue was full causing retry 100system.physmem.totGap 51811397057500 # Total gap between requests | 99system.physmem.numWrRetry 25 # Number of times write queue was full causing retry 100system.physmem.totGap 51759371327500 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 43101 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 43101 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 1096237 # Read request sizes (log2) | 107system.physmem.readPktSize::6 650311 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 956725 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1111594 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 21338 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 395 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 330 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 485 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 522 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 535 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1104 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 665 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 328 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 156 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 986454 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 663933 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 23086 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 455 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 539 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 542 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 655 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 269 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 154 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see |
| 130system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see | 130system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see |
| 131system.physmem.rdQLenPdf::16 100 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see | 131system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see |
| 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 13396 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 17710 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 56112 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 55236 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 57047 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 55563 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 55847 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 56596 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 57293 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 56619 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 58037 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 60289 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 57688 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 57977 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 60291 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 57181 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 56145 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 56000 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2355 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 794 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 723 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 518 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 490 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 507 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 456 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 282 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 360 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 324 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 282 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 222 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 283 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 208 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 289 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 270 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 188 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 218 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 220 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 208 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 220 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 450226 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 297.889433 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 171.979745 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 329.177331 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 179632 39.90% 39.90% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 110318 24.50% 64.40% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 39188 8.70% 73.11% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 22734 5.05% 78.15% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 15887 3.53% 81.68% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 11846 2.63% 84.31% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 9963 2.21% 86.53% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 8722 1.94% 88.46% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 51936 11.54% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 450226 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 53627 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 21.230425 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 337.691151 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-4095 53625 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 53627 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 53627 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 17.846029 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 17.135395 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 8.325860 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 51578 96.18% 96.18% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 290 0.54% 96.72% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 64 0.12% 96.84% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 105 0.20% 97.04% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 36 0.07% 97.10% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 101 0.19% 97.29% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 231 0.43% 97.72% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 25 0.05% 97.77% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 324 0.60% 98.37% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 70 0.13% 98.50% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 27 0.05% 98.55% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 55 0.10% 98.66% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 281 0.52% 99.18% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 24 0.04% 99.22% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 27 0.05% 99.27% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 150 0.28% 99.55% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 183 0.34% 99.90% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads | 162system.physmem.wrQLenPdf::15 32057 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 37802 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 55171 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 54666 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 57679 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 55454 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 58825 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 55973 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 56654 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 56029 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 57159 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 59457 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 57206 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 57286 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 59007 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 55988 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 54822 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 54598 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2305 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 830 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 699 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 495 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 443 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 319 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 278 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 238 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 218 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 238 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 213 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 158 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 441826 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 243.264489 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 146.730249 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 285.608942 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 196692 44.52% 44.52% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 117501 26.59% 71.11% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 39119 8.85% 79.97% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 20402 4.62% 84.58% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 13280 3.01% 87.59% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 8813 1.99% 89.58% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 7349 1.66% 91.25% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 5826 1.32% 92.57% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 32844 7.43% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 441826 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 52334 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 13.234628 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 140.708770 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-1023 52332 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 52334 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 52334 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 18.854989 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.140951 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 8.267205 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 48626 92.91% 92.91% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 1874 3.58% 96.50% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 113 0.22% 96.71% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 103 0.20% 96.91% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 52 0.10% 97.01% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 95 0.18% 97.19% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 242 0.46% 97.65% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 26 0.05% 97.70% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 308 0.59% 98.29% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 80 0.15% 98.44% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 37 0.07% 98.51% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 50 0.10% 98.61% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 303 0.58% 99.19% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 32 0.06% 99.25% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 32 0.06% 99.31% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 137 0.26% 99.57% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 171 0.33% 99.90% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads |
| 257system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads | 255system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads |
| 258system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::124-127 3 0.01% 99.93% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::128-131 7 0.01% 99.94% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::144-147 16 0.03% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads | 256system.physmem.wrPerTurnAround::104-107 3 0.01% 99.91% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 2 0.00% 99.92% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 10 0.02% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads |
| 270system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads | 268system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads |
| 271system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::total 53627 # Writes before turning the bus around for reads 273system.physmem.totQLat 14356871098 # Total ticks spent queuing 274system.physmem.totMemAccLat 35704927348 # Total ticks spent from burst creation until serviced by the DRAM 275system.physmem.totBusLat 5692815000 # Total ticks spent in databus transfers 276system.physmem.avgQLat 12609.64 # Average queueing delay per DRAM burst | 269system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::total 52334 # Writes before turning the bus around for reads 272system.physmem.totQLat 9243736951 # Total ticks spent queuing 273system.physmem.totMemAccLat 22230586951 # Total ticks spent from burst creation until serviced by the DRAM 274system.physmem.totBusLat 3463160000 # Total ticks spent in databus transfers 275system.physmem.avgQLat 13345.81 # Average queueing delay per DRAM burst |
| 277system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 278system.physmem.avgMemAccLat 31359.64 # Average memory access latency per DRAM burst 279system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s 280system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s 281system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s 282system.physmem.avgWrBWSys 1.18 # Average system write bandwidth in MiByte/s | 277system.physmem.avgMemAccLat 32095.81 # Average memory access latency per DRAM burst 278system.physmem.avgRdBW 0.86 # Average DRAM read bandwidth in MiByte/s 279system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 0.81 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s |
| 283system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 284system.physmem.busUtil 0.02 # Data bus utilization in percentage 285system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 286system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 287system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.02 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 286system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 288system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing 289system.physmem.readRowHits 917761 # Number of row buffer hits during reads 290system.physmem.writeRowHits 727604 # Number of row buffer hits during writes 291system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads 292system.physmem.writeRowHitRate 76.03 # Row buffer hit rate for writes 293system.physmem.avgGap 24687952.91 # Average gap between requests 294system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined 295system.physmem_0.actEnergy 1698338880 # Energy for activate commands per rank (pJ) 296system.physmem_0.preEnergy 926673000 # Energy for precharge commands per rank (pJ) 297system.physmem_0.readEnergy 4262879400 # Energy for read commands per rank (pJ) 298system.physmem_0.writeEnergy 3064353120 # Energy for write commands per rank (pJ) 299system.physmem_0.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) 300system.physmem_0.actBackEnergy 1294076187855 # Energy for active background per rank (pJ) 301system.physmem_0.preBackEnergy 29951683866750 # Energy for precharge background per rank (pJ) 302system.physmem_0.totalEnergy 34639780896525 # Total energy per rank (pJ) 303system.physmem_0.averagePower 668.574535 # Core power per rank (mW) 304system.physmem_0.memoryStateTime::IDLE 49826749097915 # Time in different power states 305system.physmem_0.memoryStateTime::REF 1730096420000 # Time in different power states | 287system.physmem.avgWrQLen 26.31 # Average write queue length when enqueuing 288system.physmem.readRowHits 510166 # Number of row buffer hits during reads 289system.physmem.writeRowHits 727396 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 73.66 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 73.71 # Row buffer hit rate for writes 292system.physmem.avgGap 30764211.88 # Average gap between requests 293system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined 294system.physmem_0.actEnergy 1653765120 # Energy for activate commands per rank (pJ) 295system.physmem_0.preEnergy 902352000 # Energy for precharge commands per rank (pJ) 296system.physmem_0.readEnergy 2504080800 # Energy for read commands per rank (pJ) 297system.physmem_0.writeEnergy 3163322160 # Energy for write commands per rank (pJ) 298system.physmem_0.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) 299system.physmem_0.actBackEnergy 1281472530255 # Energy for active background per rank (pJ) 300system.physmem_0.preBackEnergy 29931523073250 # Energy for precharge background per rank (pJ) 301system.physmem_0.totalEnergy 34601889523185 # Total energy per rank (pJ) 302system.physmem_0.averagePower 668.514508 # Core power per rank (mW) 303system.physmem_0.memoryStateTime::IDLE 49793449587940 # Time in different power states 304system.physmem_0.memoryStateTime::REF 1728359100000 # Time in different power states |
| 306system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 305system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 307system.physmem_0.memoryStateTime::ACT 254553819585 # Time in different power states | 306system.physmem_0.memoryStateTime::ACT 237560965810 # Time in different power states |
| 308system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 307system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 309system.physmem_1.actEnergy 1705369680 # Energy for activate commands per rank (pJ) 310system.physmem_1.preEnergy 930509250 # Energy for precharge commands per rank (pJ) 311system.physmem_1.readEnergy 4617873000 # Energy for read commands per rank (pJ) 312system.physmem_1.writeEnergy 3137194800 # Energy for write commands per rank (pJ) 313system.physmem_1.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) 314system.physmem_1.actBackEnergy 1296366805530 # Energy for active background per rank (pJ) 315system.physmem_1.preBackEnergy 29949674553000 # Energy for precharge background per rank (pJ) 316system.physmem_1.totalEnergy 34640500902780 # Total energy per rank (pJ) 317system.physmem_1.averagePower 668.588432 # Core power per rank (mW) 318system.physmem_1.memoryStateTime::IDLE 49823352477739 # Time in different power states 319system.physmem_1.memoryStateTime::REF 1730096420000 # Time in different power states | 308system.physmem_1.actEnergy 1686439440 # Energy for activate commands per rank (pJ) 309system.physmem_1.preEnergy 920180250 # Energy for precharge commands per rank (pJ) 310system.physmem_1.readEnergy 2898409800 # Energy for read commands per rank (pJ) 311system.physmem_1.writeEnergy 3230863200 # Energy for write commands per rank (pJ) 312system.physmem_1.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) 313system.physmem_1.actBackEnergy 1285016955840 # Energy for active background per rank (pJ) 314system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ) 315system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ) 316system.physmem_1.averagePower 668.532817 # Core power per rank (mW) 317system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states 318system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states |
| 320system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 321system.physmem_1.memoryStateTime::ACT 257948478511 # Time in different power states | 320system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states |
| 322system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 323system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 326system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 327system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 328system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 329system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory --- 37 unchanged lines hidden (view full) --- 367system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 370system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 371system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 372system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 373system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 374system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 322system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 323system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 325system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 326system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 327system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 328system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory --- 37 unchanged lines hidden (view full) --- 366system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 367system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 368system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 369system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 370system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 371system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 372system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 373system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 375system.cpu.dtb.walker.walks 185086 # Table walker walks requested 376system.cpu.dtb.walker.walksLong 185086 # Table walker walks initiated with long descriptors 377system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12788 # Level at which table walker walks with long descriptors terminate 378system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144037 # Level at which table walker walks with long descriptors terminate 379system.cpu.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting 380system.cpu.dtb.walker.walkWaitTime::samples 185071 # Table walker wait (enqueue to first request) latency 381system.cpu.dtb.walker.walkWaitTime::mean 0.216133 # Table walker wait (enqueue to first request) latency 382system.cpu.dtb.walker.walkWaitTime::stdev 70.811526 # Table walker wait (enqueue to first request) latency 383system.cpu.dtb.walker.walkWaitTime::0-2047 185069 100.00% 100.00% # Table walker wait (enqueue to first request) latency | 374system.cpu.dtb.walker.walks 187211 # Table walker walks requested 375system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors 376system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate 377system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate 378system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting 379system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency 381system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency 382system.cpu.dtb.walker.walkWaitTime::0-2047 187192 100.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 384system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 385system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency | 383system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 384system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 386system.cpu.dtb.walker.walkWaitTime::total 185071 # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkCompletionTime::samples 156840 # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::mean 24753.656593 # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::gmean 20840.255945 # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::stdev 17740.873102 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::0-65535 155696 99.27% 99.27% # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.27% # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::131072-196607 981 0.63% 99.90% # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.96% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.97% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::393216-458751 36 0.02% 100.00% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::total 156840 # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walksPending::samples -374556148 # Table walker pending requests distribution 403system.cpu.dtb.walker.walksPending::mean 5.053125 # Table walker pending requests distribution | 385system.cpu.dtb.walker.walkWaitTime::total 187194 # Table walker wait (enqueue to first request) latency 386system.cpu.dtb.walker.walkCompletionTime::samples 158446 # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::mean 24872.701110 # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::gmean 20850.948689 # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::stdev 18486.762457 # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::0-65535 157188 99.21% 99.21% # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.21% # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::131072-196607 1079 0.68% 99.89% # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::196608-262143 28 0.02% 99.91% # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.95% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::327680-393215 21 0.01% 99.96% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::393216-458751 47 0.03% 99.99% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::total 158446 # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walksPending::samples -5153633892 # Table walker pending requests distribution 403system.cpu.dtb.walker.walksPending::mean 1.304072 # Table walker pending requests distribution |
| 404system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution | 404system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution |
| 405system.cpu.dtb.walker.walksPending::0 1518122704 -405.31% -405.31% # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::1 -1892678852 505.31% 100.00% # Table walker pending requests distribution 407system.cpu.dtb.walker.walksPending::total -374556148 # Table walker pending requests distribution 408system.cpu.dtb.walker.walkPageSizes::4K 144038 91.85% 91.85% # Table walker page sizes translated 409system.cpu.dtb.walker.walkPageSizes::2M 12788 8.15% 100.00% # Table walker page sizes translated 410system.cpu.dtb.walker.walkPageSizes::total 156826 # Table walker page sizes translated 411system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185086 # Table walker requests started/completed, data/inst | 405system.cpu.dtb.walker.walksPending::0 1567075704 -30.41% -30.41% # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::1 -6720709596 130.41% 100.00% # Table walker pending requests distribution 407system.cpu.dtb.walker.walksPending::total -5153633892 # Table walker pending requests distribution 408system.cpu.dtb.walker.walkPageSizes::4K 146093 92.21% 92.21% # Table walker page sizes translated 409system.cpu.dtb.walker.walkPageSizes::2M 12337 7.79% 100.00% # Table walker page sizes translated 410system.cpu.dtb.walker.walkPageSizes::total 158430 # Table walker page sizes translated 411system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 187211 # Table walker requests started/completed, data/inst |
| 412system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 412system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 413system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185086 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156826 # Table walker requests started/completed, data/inst | 413system.cpu.dtb.walker.walkRequestOrigin_Requested::total 187211 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 158430 # Table walker requests started/completed, data/inst |
| 415system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 415system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 416system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156826 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin::total 341912 # Table walker requests started/completed, data/inst | 416system.cpu.dtb.walker.walkRequestOrigin_Completed::total 158430 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin::total 345641 # Table walker requests started/completed, data/inst |
| 418system.cpu.dtb.inst_hits 0 # ITB inst hits 419system.cpu.dtb.inst_misses 0 # ITB inst misses | 418system.cpu.dtb.inst_hits 0 # ITB inst hits 419system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 420system.cpu.dtb.read_hits 156026006 # DTB read hits 421system.cpu.dtb.read_misses 137641 # DTB read misses 422system.cpu.dtb.write_hits 141600690 # DTB write hits 423system.cpu.dtb.write_misses 47445 # DTB write misses | 420system.cpu.dtb.read_hits 157500215 # DTB read hits 421system.cpu.dtb.read_misses 138721 # DTB read misses 422system.cpu.dtb.write_hits 142992331 # DTB write hits 423system.cpu.dtb.write_misses 48490 # DTB write misses |
| 424system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 425system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 424system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 425system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 426system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID 427system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID 428system.cpu.dtb.flush_entries 70612 # Number of entries that have been flushed from TLB | 426system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 427system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID 428system.cpu.dtb.flush_entries 71001 # Number of entries that have been flushed from TLB |
| 429system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 429system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 430system.cpu.dtb.prefetch_faults 6537 # Number of TLB faults due to prefetch | 430system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch |
| 431system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 431system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 432system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions 433system.cpu.dtb.read_accesses 156163647 # DTB read accesses 434system.cpu.dtb.write_accesses 141648135 # DTB write accesses | 432system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions 433system.cpu.dtb.read_accesses 157638936 # DTB read accesses 434system.cpu.dtb.write_accesses 143040821 # DTB write accesses |
| 435system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 435system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 436system.cpu.dtb.hits 297626696 # DTB hits 437system.cpu.dtb.misses 185086 # DTB misses 438system.cpu.dtb.accesses 297811782 # DTB accesses | 436system.cpu.dtb.hits 300492546 # DTB hits 437system.cpu.dtb.misses 187211 # DTB misses 438system.cpu.dtb.accesses 300679757 # DTB accesses |
| 439system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 460system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 461system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 462system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 463system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 464system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 465system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 466system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 467system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 439system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 460system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 461system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 462system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 463system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 464system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 465system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 466system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 467system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 468system.cpu.itb.walker.walks 118473 # Table walker walks requested 469system.cpu.itb.walker.walksLong 118473 # Table walker walks initiated with long descriptors 470system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate 471system.cpu.itb.walker.walksLongTerminationLevel::Level3 107045 # Level at which table walker walks with long descriptors terminate 472system.cpu.itb.walker.walkWaitTime::samples 118473 # Table walker wait (enqueue to first request) latency 473system.cpu.itb.walker.walkWaitTime::0 118473 100.00% 100.00% # Table walker wait (enqueue to first request) latency 474system.cpu.itb.walker.walkWaitTime::total 118473 # Table walker wait (enqueue to first request) latency 475system.cpu.itb.walker.walkCompletionTime::samples 108155 # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::mean 28668.184550 # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::gmean 24838.617630 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::stdev 20892.143337 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::0-65535 106773 98.72% 98.72% # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::131072-196607 1223 1.13% 99.85% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::196608-262143 21 0.02% 99.87% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::262144-327679 63 0.06% 99.93% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::327680-393215 24 0.02% 99.95% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::393216-458751 37 0.03% 99.99% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 100.00% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::total 108155 # Table walker service (enqueue to completion) latency | 468system.cpu.itb.walker.walks 119486 # Table walker walks requested 469system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors 470system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate 471system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate 472system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency 473system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency 474system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency 475system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::mean 28670.651516 # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::gmean 24724.680347 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::stdev 21871.977834 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::0-65535 107545 98.63% 98.63% # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 98.63% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::131072-196607 1290 1.18% 99.82% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::196608-262143 34 0.03% 99.85% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::262144-327679 71 0.07% 99.91% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::327680-393215 41 0.04% 99.95% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::393216-458751 42 0.04% 99.99% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::total 109038 # Table walker service (enqueue to completion) latency |
| 489system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution 490system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution 491system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution | 491system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution 492system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution 493system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution |
| 492system.cpu.itb.walker.walkPageSizes::4K 107045 98.97% 98.97% # Table walker page sizes translated 493system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated 494system.cpu.itb.walker.walkPageSizes::total 108155 # Table walker page sizes translated | 494system.cpu.itb.walker.walkPageSizes::4K 107916 98.97% 98.97% # Table walker page sizes translated 495system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated 496system.cpu.itb.walker.walkPageSizes::total 109038 # Table walker page sizes translated |
| 495system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 497system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 496system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118473 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Requested::total 118473 # Table walker requests started/completed, data/inst | 498system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119486 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Requested::total 119486 # Table walker requests started/completed, data/inst |
| 498system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 500system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 499system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108155 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin_Completed::total 108155 # Table walker requests started/completed, data/inst 501system.cpu.itb.walker.walkRequestOrigin::total 226628 # Table walker requests started/completed, data/inst 502system.cpu.itb.inst_hits 829023400 # ITB inst hits 503system.cpu.itb.inst_misses 118473 # ITB inst misses | 501system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109038 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin_Completed::total 109038 # Table walker requests started/completed, data/inst 503system.cpu.itb.walker.walkRequestOrigin::total 228524 # Table walker requests started/completed, data/inst 504system.cpu.itb.inst_hits 837449249 # ITB inst hits 505system.cpu.itb.inst_misses 119486 # ITB inst misses |
| 504system.cpu.itb.read_hits 0 # DTB read hits 505system.cpu.itb.read_misses 0 # DTB read misses 506system.cpu.itb.write_hits 0 # DTB write hits 507system.cpu.itb.write_misses 0 # DTB write misses 508system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 509system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 506system.cpu.itb.read_hits 0 # DTB read hits 507system.cpu.itb.read_misses 0 # DTB read misses 508system.cpu.itb.write_hits 0 # DTB write hits 509system.cpu.itb.write_misses 0 # DTB write misses 510system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 511system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 510system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID 511system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID 512system.cpu.itb.flush_entries 50418 # Number of entries that have been flushed from TLB | 512system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 513system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID 514system.cpu.itb.flush_entries 50677 # Number of entries that have been flushed from TLB |
| 513system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 514system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 515system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 516system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 517system.cpu.itb.read_accesses 0 # DTB read accesses 518system.cpu.itb.write_accesses 0 # DTB write accesses | 515system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 516system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 517system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 518system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 519system.cpu.itb.read_accesses 0 # DTB read accesses 520system.cpu.itb.write_accesses 0 # DTB write accesses |
| 519system.cpu.itb.inst_accesses 829141873 # ITB inst accesses 520system.cpu.itb.hits 829023400 # DTB hits 521system.cpu.itb.misses 118473 # DTB misses 522system.cpu.itb.accesses 829141873 # DTB accesses 523system.cpu.numCycles 103622799989 # number of cpu cycles simulated | 521system.cpu.itb.inst_accesses 837568735 # ITB inst accesses 522system.cpu.itb.hits 837449249 # DTB hits 523system.cpu.itb.misses 119486 # DTB misses 524system.cpu.itb.accesses 837568735 # DTB accesses 525system.cpu.numCycles 103518748529 # number of cpu cycles simulated |
| 524system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 525system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 526system.cpu.kern.inst.arm 0 # number of arm instructions executed | 526system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 527system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 528system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 527system.cpu.kern.inst.quiesce 15972 # number of quiesce instructions executed 528system.cpu.committedInsts 828512987 # Number of instructions committed 529system.cpu.committedOps 973664549 # Number of ops (including micro ops) committed 530system.cpu.num_int_alu_accesses 895161313 # Number of integer alu accesses 531system.cpu.num_fp_alu_accesses 899443 # Number of float alu accesses 532system.cpu.num_func_calls 49782138 # number of times a function call or return occured 533system.cpu.num_conditional_control_insts 125600972 # number of instructions that are conditional controls 534system.cpu.num_int_insts 895161313 # number of integer instructions 535system.cpu.num_fp_insts 899443 # number of float instructions 536system.cpu.num_int_register_reads 1295047006 # number of times the integer registers were read 537system.cpu.num_int_register_writes 709396185 # number of times the integer registers were written 538system.cpu.num_fp_register_reads 1452745 # number of times the floating registers were read 539system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written 540system.cpu.num_cc_register_reads 214441530 # number of times the CC registers were read 541system.cpu.num_cc_register_writes 213833710 # number of times the CC registers were written 542system.cpu.num_mem_refs 297604519 # number of memory refs 543system.cpu.num_load_insts 156015499 # Number of load instructions 544system.cpu.num_store_insts 141589020 # Number of store instructions 545system.cpu.num_idle_cycles 100541051528.316055 # Number of idle cycles 546system.cpu.num_busy_cycles 3081748460.683940 # Number of busy cycles 547system.cpu.not_idle_fraction 0.029740 # Percentage of non-idle cycles 548system.cpu.idle_fraction 0.970260 # Percentage of idle cycles 549system.cpu.Branches 184855625 # Number of branches fetched | 529system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed 530system.cpu.committedInsts 836933434 # Number of instructions committed 531system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed 532system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses 533system.cpu.num_fp_alu_accesses 901230 # Number of float alu accesses 534system.cpu.num_func_calls 50188688 # number of times a function call or return occured 535system.cpu.num_conditional_control_insts 127012937 # number of instructions that are conditional controls 536system.cpu.num_int_insts 904020212 # number of integer instructions 537system.cpu.num_fp_insts 901230 # number of float instructions 538system.cpu.num_int_register_reads 1309570840 # number of times the integer registers were read 539system.cpu.num_int_register_writes 716549182 # number of times the integer registers were written 540system.cpu.num_fp_register_reads 1454726 # number of times the floating registers were read 541system.cpu.num_fp_register_writes 760848 # number of times the floating registers were written 542system.cpu.num_cc_register_reads 217149735 # number of times the CC registers were read 543system.cpu.num_cc_register_writes 216544825 # number of times the CC registers were written 544system.cpu.num_mem_refs 300471292 # number of memory refs 545system.cpu.num_load_insts 157490392 # Number of load instructions 546system.cpu.num_store_insts 142980900 # Number of store instructions 547system.cpu.num_idle_cycles 100455078038.626068 # Number of idle cycles 548system.cpu.num_busy_cycles 3063670490.373941 # Number of busy cycles 549system.cpu.not_idle_fraction 0.029595 # Percentage of non-idle cycles 550system.cpu.idle_fraction 0.970405 # Percentage of idle cycles 551system.cpu.Branches 186768786 # Number of branches fetched |
| 550system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction | 552system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction |
| 551system.cpu.op_class::IntAlu 674284702 69.21% 69.21% # Class of executed instruction 552system.cpu.op_class::IntMult 2119126 0.22% 69.43% # Class of executed instruction 553system.cpu.op_class::IntDiv 97314 0.01% 69.44% # Class of executed instruction 554system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction 555system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction 556system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction 557system.cpu.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction 558system.cpu.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction 559system.cpu.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction 560system.cpu.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction 561system.cpu.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction 562system.cpu.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction 563system.cpu.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction 564system.cpu.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction 565system.cpu.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction 566system.cpu.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction 567system.cpu.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction 568system.cpu.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction 569system.cpu.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction 570system.cpu.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction 571system.cpu.op_class::SimdFloatAdd 8 0.00% 69.44% # Class of executed instruction 572system.cpu.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction 573system.cpu.op_class::SimdFloatCmp 13 0.00% 69.44% # Class of executed instruction 574system.cpu.op_class::SimdFloatCvt 21 0.00% 69.44% # Class of executed instruction 575system.cpu.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction 576system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Class of executed instruction 577system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction 578system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction 579system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction 580system.cpu.op_class::MemRead 156015499 16.01% 85.47% # Class of executed instruction 581system.cpu.op_class::MemWrite 141589020 14.53% 100.00% # Class of executed instruction | 553system.cpu.op_class::IntAlu 681265861 69.23% 69.23% # Class of executed instruction 554system.cpu.op_class::IntMult 2131844 0.22% 69.45% # Class of executed instruction 555system.cpu.op_class::IntDiv 96991 0.01% 69.46% # Class of executed instruction 556system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction 557system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction 558system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction 559system.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction 560system.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction 561system.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction 562system.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction 563system.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction 564system.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction 565system.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction 566system.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction 567system.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction 568system.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction 569system.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction 570system.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction 571system.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction 572system.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction 573system.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction 574system.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction 575system.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction 576system.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction 577system.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction 578system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction 579system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction 580system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction 581system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction 582system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction 583system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction |
| 582system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 583system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 584system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 585system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 584system.cpu.op_class::total 974218086 # Class of executed instruction 585system.cpu.dcache.tags.replacements 9250712 # number of replacements 586system.cpu.dcache.tags.tagsinuse 511.942785 # Cycle average of tags in use 587system.cpu.dcache.tags.total_refs 288177954 # Total number of references to valid blocks. 588system.cpu.dcache.tags.sampled_refs 9251224 # Sample count of references to valid blocks. 589system.cpu.dcache.tags.avg_refs 31.150251 # Average number of references to valid blocks. | 586system.cpu.op_class::total 984078328 # Class of executed instruction 587system.cpu.dcache.tags.replacements 9381962 # number of replacements 588system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use 589system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks. 590system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks. 591system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks. |
| 590system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. | 592system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. |
| 591system.cpu.dcache.tags.occ_blocks::cpu.data 511.942785 # Average occupied blocks per requestor | 593system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor |
| 592system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy 593system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy 594system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 594system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy 595system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy 596system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 595system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 596system.cpu.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id 597system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 598system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id | 597system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 598system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 599system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id 600system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id |
| 599system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 601system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 600system.cpu.dcache.tags.tag_accesses 1199424100 # Number of tag accesses 601system.cpu.dcache.tags.data_accesses 1199424100 # Number of data accesses 602system.cpu.dcache.ReadReq_hits::cpu.data 146113650 # number of ReadReq hits 603system.cpu.dcache.ReadReq_hits::total 146113650 # number of ReadReq hits 604system.cpu.dcache.WriteReq_hits::cpu.data 134461846 # number of WriteReq hits 605system.cpu.dcache.WriteReq_hits::total 134461846 # number of WriteReq hits 606system.cpu.dcache.SoftPFReq_hits::cpu.data 373199 # number of SoftPFReq hits 607system.cpu.dcache.SoftPFReq_hits::total 373199 # number of SoftPFReq hits 608system.cpu.dcache.WriteLineReq_hits::cpu.data 333438 # number of WriteLineReq hits 609system.cpu.dcache.WriteLineReq_hits::total 333438 # number of WriteLineReq hits 610system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286002 # number of LoadLockedReq hits 611system.cpu.dcache.LoadLockedReq_hits::total 3286002 # number of LoadLockedReq hits 612system.cpu.dcache.StoreCondReq_hits::cpu.data 3568410 # number of StoreCondReq hits 613system.cpu.dcache.StoreCondReq_hits::total 3568410 # number of StoreCondReq hits 614system.cpu.dcache.demand_hits::cpu.data 280575496 # number of demand (read+write) hits 615system.cpu.dcache.demand_hits::total 280575496 # number of demand (read+write) hits 616system.cpu.dcache.overall_hits::cpu.data 280948695 # number of overall hits 617system.cpu.dcache.overall_hits::total 280948695 # number of overall hits 618system.cpu.dcache.ReadReq_misses::cpu.data 4827178 # number of ReadReq misses 619system.cpu.dcache.ReadReq_misses::total 4827178 # number of ReadReq misses 620system.cpu.dcache.WriteReq_misses::cpu.data 1968166 # number of WriteReq misses 621system.cpu.dcache.WriteReq_misses::total 1968166 # number of WriteReq misses 622system.cpu.dcache.SoftPFReq_misses::cpu.data 1108268 # number of SoftPFReq misses 623system.cpu.dcache.SoftPFReq_misses::total 1108268 # number of SoftPFReq misses 624system.cpu.dcache.WriteLineReq_misses::cpu.data 1219027 # number of WriteLineReq misses 625system.cpu.dcache.WriteLineReq_misses::total 1219027 # number of WriteLineReq misses 626system.cpu.dcache.LoadLockedReq_misses::cpu.data 284027 # number of LoadLockedReq misses 627system.cpu.dcache.LoadLockedReq_misses::total 284027 # number of LoadLockedReq misses 628system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 629system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 630system.cpu.dcache.demand_misses::cpu.data 6795344 # number of demand (read+write) misses 631system.cpu.dcache.demand_misses::total 6795344 # number of demand (read+write) misses 632system.cpu.dcache.overall_misses::cpu.data 7903612 # number of overall misses 633system.cpu.dcache.overall_misses::total 7903612 # number of overall misses 634system.cpu.dcache.ReadReq_miss_latency::cpu.data 82868566500 # number of ReadReq miss cycles 635system.cpu.dcache.ReadReq_miss_latency::total 82868566500 # number of ReadReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::cpu.data 66733586000 # number of WriteReq miss cycles 637system.cpu.dcache.WriteReq_miss_latency::total 66733586000 # number of WriteReq miss cycles 638system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73334603500 # number of WriteLineReq miss cycles 639system.cpu.dcache.WriteLineReq_miss_latency::total 73334603500 # number of WriteLineReq miss cycles 640system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4341861000 # number of LoadLockedReq miss cycles 641system.cpu.dcache.LoadLockedReq_miss_latency::total 4341861000 # number of LoadLockedReq miss cycles 642system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles 643system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles 644system.cpu.dcache.demand_miss_latency::cpu.data 149602152500 # number of demand (read+write) miss cycles 645system.cpu.dcache.demand_miss_latency::total 149602152500 # number of demand (read+write) miss cycles 646system.cpu.dcache.overall_miss_latency::cpu.data 149602152500 # number of overall miss cycles 647system.cpu.dcache.overall_miss_latency::total 149602152500 # number of overall miss cycles 648system.cpu.dcache.ReadReq_accesses::cpu.data 150940828 # number of ReadReq accesses(hits+misses) 649system.cpu.dcache.ReadReq_accesses::total 150940828 # number of ReadReq accesses(hits+misses) 650system.cpu.dcache.WriteReq_accesses::cpu.data 136430012 # number of WriteReq accesses(hits+misses) 651system.cpu.dcache.WriteReq_accesses::total 136430012 # number of WriteReq accesses(hits+misses) 652system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481467 # number of SoftPFReq accesses(hits+misses) 653system.cpu.dcache.SoftPFReq_accesses::total 1481467 # number of SoftPFReq accesses(hits+misses) 654system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552465 # number of WriteLineReq accesses(hits+misses) 655system.cpu.dcache.WriteLineReq_accesses::total 1552465 # number of WriteLineReq accesses(hits+misses) 656system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570029 # number of LoadLockedReq accesses(hits+misses) 657system.cpu.dcache.LoadLockedReq_accesses::total 3570029 # number of LoadLockedReq accesses(hits+misses) 658system.cpu.dcache.StoreCondReq_accesses::cpu.data 3568412 # number of StoreCondReq accesses(hits+misses) 659system.cpu.dcache.StoreCondReq_accesses::total 3568412 # number of StoreCondReq accesses(hits+misses) 660system.cpu.dcache.demand_accesses::cpu.data 287370840 # number of demand (read+write) accesses 661system.cpu.dcache.demand_accesses::total 287370840 # number of demand (read+write) accesses 662system.cpu.dcache.overall_accesses::cpu.data 288852307 # number of overall (read+write) accesses 663system.cpu.dcache.overall_accesses::total 288852307 # number of overall (read+write) accesses 664system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031981 # miss rate for ReadReq accesses 665system.cpu.dcache.ReadReq_miss_rate::total 0.031981 # miss rate for ReadReq accesses 666system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014426 # miss rate for WriteReq accesses 667system.cpu.dcache.WriteReq_miss_rate::total 0.014426 # miss rate for WriteReq accesses 668system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748088 # miss rate for SoftPFReq accesses 669system.cpu.dcache.SoftPFReq_miss_rate::total 0.748088 # miss rate for SoftPFReq accesses 670system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785220 # miss rate for WriteLineReq accesses 671system.cpu.dcache.WriteLineReq_miss_rate::total 0.785220 # miss rate for WriteLineReq accesses 672system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079559 # miss rate for LoadLockedReq accesses 673system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079559 # miss rate for LoadLockedReq accesses 674system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 675system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 676system.cpu.dcache.demand_miss_rate::cpu.data 0.023647 # miss rate for demand accesses 677system.cpu.dcache.demand_miss_rate::total 0.023647 # miss rate for demand accesses 678system.cpu.dcache.overall_miss_rate::cpu.data 0.027362 # miss rate for overall accesses 679system.cpu.dcache.overall_miss_rate::total 0.027362 # miss rate for overall accesses 680system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17167.083232 # average ReadReq miss latency 681system.cpu.dcache.ReadReq_avg_miss_latency::total 17167.083232 # average ReadReq miss latency 682system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33906.482482 # average WriteReq miss latency 683system.cpu.dcache.WriteReq_avg_miss_latency::total 33906.482482 # average WriteReq miss latency 684system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60158.309455 # average WriteLineReq miss latency 685system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60158.309455 # average WriteLineReq miss latency 686system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15286.789636 # average LoadLockedReq miss latency 687system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15286.789636 # average LoadLockedReq miss latency 688system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency 689system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency 690system.cpu.dcache.demand_avg_miss_latency::cpu.data 22015.390612 # average overall miss latency 691system.cpu.dcache.demand_avg_miss_latency::total 22015.390612 # average overall miss latency 692system.cpu.dcache.overall_avg_miss_latency::cpu.data 18928.327010 # average overall miss latency 693system.cpu.dcache.overall_avg_miss_latency::total 18928.327010 # average overall miss latency | 602system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses 603system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses 604system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits 605system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits 606system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits 607system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits 608system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits 609system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits 610system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits 611system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits 612system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits 613system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits 614system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits 615system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits 616system.cpu.dcache.demand_hits::cpu.data 283201595 # number of demand (read+write) hits 617system.cpu.dcache.demand_hits::total 283201595 # number of demand (read+write) hits 618system.cpu.dcache.overall_hits::cpu.data 283575709 # number of overall hits 619system.cpu.dcache.overall_hits::total 283575709 # number of overall hits 620system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses 621system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses 622system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses 623system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses 624system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses 625system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses 626system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses 627system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses 628system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses 629system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses 630system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 631system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 632system.cpu.dcache.demand_misses::cpu.data 6893121 # number of demand (read+write) misses 633system.cpu.dcache.demand_misses::total 6893121 # number of demand (read+write) misses 634system.cpu.dcache.overall_misses::cpu.data 8029572 # number of overall misses 635system.cpu.dcache.overall_misses::total 8029572 # number of overall misses 636system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles 637system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles 638system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles 639system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles 640system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles 641system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles 642system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles 643system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles 644system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 645system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles 646system.cpu.dcache.demand_miss_latency::cpu.data 154677984000 # number of demand (read+write) miss cycles 647system.cpu.dcache.demand_miss_latency::total 154677984000 # number of demand (read+write) miss cycles 648system.cpu.dcache.overall_miss_latency::cpu.data 154677984000 # number of overall miss cycles 649system.cpu.dcache.overall_miss_latency::total 154677984000 # number of overall miss cycles 650system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses) 651system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses) 652system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses) 653system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses) 654system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses) 655system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses) 656system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses) 657system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses) 658system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses) 659system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses) 660system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses) 661system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses) 662system.cpu.dcache.demand_accesses::cpu.data 290094716 # number of demand (read+write) accesses 663system.cpu.dcache.demand_accesses::total 290094716 # number of demand (read+write) accesses 664system.cpu.dcache.overall_accesses::cpu.data 291605281 # number of overall (read+write) accesses 665system.cpu.dcache.overall_accesses::total 291605281 # number of overall (read+write) accesses 666system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses 667system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses 668system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses 669system.cpu.dcache.WriteReq_miss_rate::total 0.014504 # miss rate for WriteReq accesses 670system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752335 # miss rate for SoftPFReq accesses 671system.cpu.dcache.SoftPFReq_miss_rate::total 0.752335 # miss rate for SoftPFReq accesses 672system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785976 # miss rate for WriteLineReq accesses 673system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses 674system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses 675system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses 676system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 677system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 678system.cpu.dcache.demand_miss_rate::cpu.data 0.023762 # miss rate for demand accesses 679system.cpu.dcache.demand_miss_rate::total 0.023762 # miss rate for demand accesses 680system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses 681system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency 683system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency 684system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency 685system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency 686system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency 687system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency 688system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency 689system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency 690system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 691system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 692system.cpu.dcache.demand_avg_miss_latency::cpu.data 22439.470307 # average overall miss latency 693system.cpu.dcache.demand_avg_miss_latency::total 22439.470307 # average overall miss latency 694system.cpu.dcache.overall_avg_miss_latency::cpu.data 19263.540323 # average overall miss latency 695system.cpu.dcache.overall_avg_miss_latency::total 19263.540323 # average overall miss latency |
| 694system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 695system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 696system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 697system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 698system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 699system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 700system.cpu.dcache.fast_writes 0 # number of fast writes performed 701system.cpu.dcache.cache_copies 0 # number of cache copies performed | 696system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 697system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 698system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 699system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 700system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 701system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 702system.cpu.dcache.fast_writes 0 # number of fast writes performed 703system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 702system.cpu.dcache.writebacks::writebacks 7246265 # number of writebacks 703system.cpu.dcache.writebacks::total 7246265 # number of writebacks 704system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23319 # number of ReadReq MSHR hits 705system.cpu.dcache.ReadReq_mshr_hits::total 23319 # number of ReadReq MSHR hits 706system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21298 # number of WriteReq MSHR hits 707system.cpu.dcache.WriteReq_mshr_hits::total 21298 # number of WriteReq MSHR hits 708system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67614 # number of LoadLockedReq MSHR hits 709system.cpu.dcache.LoadLockedReq_mshr_hits::total 67614 # number of LoadLockedReq MSHR hits 710system.cpu.dcache.demand_mshr_hits::cpu.data 44617 # number of demand (read+write) MSHR hits 711system.cpu.dcache.demand_mshr_hits::total 44617 # number of demand (read+write) MSHR hits 712system.cpu.dcache.overall_mshr_hits::cpu.data 44617 # number of overall MSHR hits 713system.cpu.dcache.overall_mshr_hits::total 44617 # number of overall MSHR hits 714system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4803859 # number of ReadReq MSHR misses 715system.cpu.dcache.ReadReq_mshr_misses::total 4803859 # number of ReadReq MSHR misses 716system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1946868 # number of WriteReq MSHR misses 717system.cpu.dcache.WriteReq_mshr_misses::total 1946868 # number of WriteReq MSHR misses 718system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1106488 # number of SoftPFReq MSHR misses 719system.cpu.dcache.SoftPFReq_mshr_misses::total 1106488 # number of SoftPFReq MSHR misses 720system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1219027 # number of WriteLineReq MSHR misses 721system.cpu.dcache.WriteLineReq_mshr_misses::total 1219027 # number of WriteLineReq MSHR misses 722system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 216413 # number of LoadLockedReq MSHR misses 723system.cpu.dcache.LoadLockedReq_mshr_misses::total 216413 # number of LoadLockedReq MSHR misses 724system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 725system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 726system.cpu.dcache.demand_mshr_misses::cpu.data 6750727 # number of demand (read+write) MSHR misses 727system.cpu.dcache.demand_mshr_misses::total 6750727 # number of demand (read+write) MSHR misses 728system.cpu.dcache.overall_mshr_misses::cpu.data 7857215 # number of overall MSHR misses 729system.cpu.dcache.overall_mshr_misses::total 7857215 # number of overall MSHR misses | 704system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks 705system.cpu.dcache.writebacks::total 7313678 # number of writebacks 706system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits 707system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits 708system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21254 # number of WriteReq MSHR hits 709system.cpu.dcache.WriteReq_mshr_hits::total 21254 # number of WriteReq MSHR hits 710system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68600 # number of LoadLockedReq MSHR hits 711system.cpu.dcache.LoadLockedReq_mshr_hits::total 68600 # number of LoadLockedReq MSHR hits 712system.cpu.dcache.demand_mshr_hits::cpu.data 43235 # number of demand (read+write) MSHR hits 713system.cpu.dcache.demand_mshr_hits::total 43235 # number of demand (read+write) MSHR hits 714system.cpu.dcache.overall_mshr_hits::cpu.data 43235 # number of overall MSHR hits 715system.cpu.dcache.overall_mshr_hits::total 43235 # number of overall MSHR hits 716system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4873010 # number of ReadReq MSHR misses 717system.cpu.dcache.ReadReq_mshr_misses::total 4873010 # number of ReadReq MSHR misses 718system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1976876 # number of WriteReq MSHR misses 719system.cpu.dcache.WriteReq_mshr_misses::total 1976876 # number of WriteReq MSHR misses 720system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1134686 # number of SoftPFReq MSHR misses 721system.cpu.dcache.SoftPFReq_mshr_misses::total 1134686 # number of SoftPFReq MSHR misses 722system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221510 # number of WriteLineReq MSHR misses 723system.cpu.dcache.WriteLineReq_mshr_misses::total 1221510 # number of WriteLineReq MSHR misses 724system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778 # number of LoadLockedReq MSHR misses 725system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses 726system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 727system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 728system.cpu.dcache.demand_mshr_misses::cpu.data 6849886 # number of demand (read+write) MSHR misses 729system.cpu.dcache.demand_mshr_misses::total 6849886 # number of demand (read+write) MSHR misses 730system.cpu.dcache.overall_mshr_misses::cpu.data 7984572 # number of overall MSHR misses 731system.cpu.dcache.overall_mshr_misses::total 7984572 # number of overall MSHR misses |
| 730system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 731system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable 732system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 733system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 734system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 735system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses | 732system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 733system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable 734system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 735system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 736system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 737system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses |
| 736system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76693371000 # number of ReadReq MSHR miss cycles 737system.cpu.dcache.ReadReq_mshr_miss_latency::total 76693371000 # number of ReadReq MSHR miss cycles 738system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63803384500 # number of WriteReq MSHR miss cycles 739system.cpu.dcache.WriteReq_mshr_miss_latency::total 63803384500 # number of WriteReq MSHR miss cycles 740system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20983567500 # number of SoftPFReq MSHR miss cycles 741system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20983567500 # number of SoftPFReq MSHR miss cycles 742system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72115576500 # number of WriteLineReq MSHR miss cycles 743system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72115576500 # number of WriteLineReq MSHR miss cycles 744system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2970992000 # number of LoadLockedReq MSHR miss cycles 745system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2970992000 # number of LoadLockedReq MSHR miss cycles 746system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles 747system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles 748system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140496755500 # number of demand (read+write) MSHR miss cycles 749system.cpu.dcache.demand_mshr_miss_latency::total 140496755500 # number of demand (read+write) MSHR miss cycles 750system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161480323000 # number of overall MSHR miss cycles 751system.cpu.dcache.overall_mshr_miss_latency::total 161480323000 # number of overall MSHR miss cycles 752system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199653000 # number of ReadReq MSHR uncacheable cycles 753system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199653000 # number of ReadReq MSHR uncacheable cycles 754system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217623500 # number of WriteReq MSHR uncacheable cycles 755system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217623500 # number of WriteReq MSHR uncacheable cycles 756system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417276500 # number of overall MSHR uncacheable cycles 757system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417276500 # number of overall MSHR uncacheable cycles 758system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031826 # mshr miss rate for ReadReq accesses 759system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031826 # mshr miss rate for ReadReq accesses 760system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014270 # mshr miss rate for WriteReq accesses 761system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014270 # mshr miss rate for WriteReq accesses 762system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746887 # mshr miss rate for SoftPFReq accesses 763system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746887 # mshr miss rate for SoftPFReq accesses 764system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785220 # mshr miss rate for WriteLineReq accesses 765system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785220 # mshr miss rate for WriteLineReq accesses 766system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060619 # mshr miss rate for LoadLockedReq accesses 767system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060619 # mshr miss rate for LoadLockedReq accesses 768system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 769system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 770system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023491 # mshr miss rate for demand accesses 771system.cpu.dcache.demand_mshr_miss_rate::total 0.023491 # mshr miss rate for demand accesses 772system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027201 # mshr miss rate for overall accesses 773system.cpu.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses 774system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15964.950470 # average ReadReq mshr miss latency 775system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15964.950470 # average ReadReq mshr miss latency 776system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32772.321750 # average WriteReq mshr miss latency 777system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32772.321750 # average WriteReq mshr miss latency 778system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18964.116647 # average SoftPFReq mshr miss latency 779system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.116647 # average SoftPFReq mshr miss latency 780system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59158.309455 # average WriteLineReq mshr miss latency 781system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59158.309455 # average WriteLineReq mshr miss latency 782system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13728.343491 # average LoadLockedReq mshr miss latency 783system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13728.343491 # average LoadLockedReq mshr miss latency 784system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency 785system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency 786system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20812.092609 # average overall mshr miss latency 787system.cpu.dcache.demand_avg_mshr_miss_latency::total 20812.092609 # average overall mshr miss latency 788system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20551.852406 # average overall mshr miss latency 789system.cpu.dcache.overall_avg_mshr_miss_latency::total 20551.852406 # average overall mshr miss latency 790system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.047178 # average ReadReq mshr uncacheable latency 791system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.047178 # average ReadReq mshr uncacheable latency 792system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.426012 # average WriteReq mshr uncacheable latency 793system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.426012 # average WriteReq mshr uncacheable latency 794system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.258864 # average overall mshr uncacheable latency 795system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.258864 # average overall mshr uncacheable latency | 738system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78281972500 # number of ReadReq MSHR miss cycles 739system.cpu.dcache.ReadReq_mshr_miss_latency::total 78281972500 # number of ReadReq MSHR miss cycles 740system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67251605000 # number of WriteReq MSHR miss cycles 741system.cpu.dcache.WriteReq_mshr_miss_latency::total 67251605000 # number of WriteReq MSHR miss cycles 742system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21441642000 # number of SoftPFReq MSHR miss cycles 743system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21441642000 # number of SoftPFReq MSHR miss cycles 744system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 47007248000 # number of WriteLineReq MSHR miss cycles 745system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles 746system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles 747system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles 748system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 749system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles 750system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145533577500 # number of demand (read+write) MSHR miss cycles 751system.cpu.dcache.demand_mshr_miss_latency::total 145533577500 # number of demand (read+write) MSHR miss cycles 752system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166975219500 # number of overall MSHR miss cycles 753system.cpu.dcache.overall_mshr_miss_latency::total 166975219500 # number of overall MSHR miss cycles 754system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles 755system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles 756system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217603000 # number of WriteReq MSHR uncacheable cycles 757system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217603000 # number of WriteReq MSHR uncacheable cycles 758system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417284500 # number of overall MSHR uncacheable cycles 759system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417284500 # number of overall MSHR uncacheable cycles 760system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses 761system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses 762system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses 763system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses 764system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses 765system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses 766system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses 767system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses 768system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses 769system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses 770system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 771system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 772system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023613 # mshr miss rate for demand accesses 773system.cpu.dcache.demand_mshr_miss_rate::total 0.023613 # mshr miss rate for demand accesses 774system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027381 # mshr miss rate for overall accesses 775system.cpu.dcache.overall_mshr_miss_rate::total 0.027381 # mshr miss rate for overall accesses 776system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency 777system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency 778system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency 779system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency 780system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency 781system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency 782system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency 783system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency 784system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency 785system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency 786system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 787system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 788system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21246.131322 # average overall mshr miss latency 789system.cpu.dcache.demand_avg_mshr_miss_latency::total 21246.131322 # average overall mshr miss latency 790system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20912.231676 # average overall mshr miss latency 791system.cpu.dcache.overall_avg_mshr_miss_latency::total 20912.231676 # average overall mshr miss latency 792system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency 793system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency 794system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.817847 # average WriteReq mshr uncacheable latency 795system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.817847 # average WriteReq mshr uncacheable latency 796system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.377540 # average overall mshr uncacheable latency 797system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.377540 # average overall mshr uncacheable latency |
| 796system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 798system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 797system.cpu.icache.tags.replacements 13387387 # number of replacements 798system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use 799system.cpu.icache.tags.total_refs 815635496 # Total number of references to valid blocks. 800system.cpu.icache.tags.sampled_refs 13387899 # Sample count of references to valid blocks. 801system.cpu.icache.tags.avg_refs 60.923338 # Average number of references to valid blocks. 802system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit. 803system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor 804system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy 805system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy | 799system.cpu.icache.tags.replacements 13331164 # number of replacements 800system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use 801system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. 802system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks. 803system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks. 804system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. 805system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor 806system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy 807system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy |
| 806system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 808system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 807system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 808system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 809system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id 810system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id | 809system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 810system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 811system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id 812system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id |
| 811system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 813system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 812system.cpu.icache.tags.tag_accesses 842411304 # Number of tag accesses 813system.cpu.icache.tags.data_accesses 842411304 # Number of data accesses 814system.cpu.icache.ReadReq_hits::cpu.inst 815635496 # number of ReadReq hits 815system.cpu.icache.ReadReq_hits::total 815635496 # number of ReadReq hits 816system.cpu.icache.demand_hits::cpu.inst 815635496 # number of demand (read+write) hits 817system.cpu.icache.demand_hits::total 815635496 # number of demand (read+write) hits 818system.cpu.icache.overall_hits::cpu.inst 815635496 # number of overall hits 819system.cpu.icache.overall_hits::total 815635496 # number of overall hits 820system.cpu.icache.ReadReq_misses::cpu.inst 13387904 # number of ReadReq misses 821system.cpu.icache.ReadReq_misses::total 13387904 # number of ReadReq misses 822system.cpu.icache.demand_misses::cpu.inst 13387904 # number of demand (read+write) misses 823system.cpu.icache.demand_misses::total 13387904 # number of demand (read+write) misses 824system.cpu.icache.overall_misses::cpu.inst 13387904 # number of overall misses 825system.cpu.icache.overall_misses::total 13387904 # number of overall misses 826system.cpu.icache.ReadReq_miss_latency::cpu.inst 182784455500 # number of ReadReq miss cycles 827system.cpu.icache.ReadReq_miss_latency::total 182784455500 # number of ReadReq miss cycles 828system.cpu.icache.demand_miss_latency::cpu.inst 182784455500 # number of demand (read+write) miss cycles 829system.cpu.icache.demand_miss_latency::total 182784455500 # number of demand (read+write) miss cycles 830system.cpu.icache.overall_miss_latency::cpu.inst 182784455500 # number of overall miss cycles 831system.cpu.icache.overall_miss_latency::total 182784455500 # number of overall miss cycles 832system.cpu.icache.ReadReq_accesses::cpu.inst 829023400 # number of ReadReq accesses(hits+misses) 833system.cpu.icache.ReadReq_accesses::total 829023400 # number of ReadReq accesses(hits+misses) 834system.cpu.icache.demand_accesses::cpu.inst 829023400 # number of demand (read+write) accesses 835system.cpu.icache.demand_accesses::total 829023400 # number of demand (read+write) accesses 836system.cpu.icache.overall_accesses::cpu.inst 829023400 # number of overall (read+write) accesses 837system.cpu.icache.overall_accesses::total 829023400 # number of overall (read+write) accesses 838system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016149 # miss rate for ReadReq accesses 839system.cpu.icache.ReadReq_miss_rate::total 0.016149 # miss rate for ReadReq accesses 840system.cpu.icache.demand_miss_rate::cpu.inst 0.016149 # miss rate for demand accesses 841system.cpu.icache.demand_miss_rate::total 0.016149 # miss rate for demand accesses 842system.cpu.icache.overall_miss_rate::cpu.inst 0.016149 # miss rate for overall accesses 843system.cpu.icache.overall_miss_rate::total 0.016149 # miss rate for overall accesses 844system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13652.955347 # average ReadReq miss latency 845system.cpu.icache.ReadReq_avg_miss_latency::total 13652.955347 # average ReadReq miss latency 846system.cpu.icache.demand_avg_miss_latency::cpu.inst 13652.955347 # average overall miss latency 847system.cpu.icache.demand_avg_miss_latency::total 13652.955347 # average overall miss latency 848system.cpu.icache.overall_avg_miss_latency::cpu.inst 13652.955347 # average overall miss latency 849system.cpu.icache.overall_avg_miss_latency::total 13652.955347 # average overall miss latency | 814system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses 815system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses 816system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits 817system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits 818system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits 819system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits 820system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits 821system.cpu.icache.overall_hits::total 824117568 # number of overall hits 822system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses 823system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses 824system.cpu.icache.demand_misses::cpu.inst 13331681 # number of demand (read+write) misses 825system.cpu.icache.demand_misses::total 13331681 # number of demand (read+write) misses 826system.cpu.icache.overall_misses::cpu.inst 13331681 # number of overall misses 827system.cpu.icache.overall_misses::total 13331681 # number of overall misses 828system.cpu.icache.ReadReq_miss_latency::cpu.inst 182292722500 # number of ReadReq miss cycles 829system.cpu.icache.ReadReq_miss_latency::total 182292722500 # number of ReadReq miss cycles 830system.cpu.icache.demand_miss_latency::cpu.inst 182292722500 # number of demand (read+write) miss cycles 831system.cpu.icache.demand_miss_latency::total 182292722500 # number of demand (read+write) miss cycles 832system.cpu.icache.overall_miss_latency::cpu.inst 182292722500 # number of overall miss cycles 833system.cpu.icache.overall_miss_latency::total 182292722500 # number of overall miss cycles 834system.cpu.icache.ReadReq_accesses::cpu.inst 837449249 # number of ReadReq accesses(hits+misses) 835system.cpu.icache.ReadReq_accesses::total 837449249 # number of ReadReq accesses(hits+misses) 836system.cpu.icache.demand_accesses::cpu.inst 837449249 # number of demand (read+write) accesses 837system.cpu.icache.demand_accesses::total 837449249 # number of demand (read+write) accesses 838system.cpu.icache.overall_accesses::cpu.inst 837449249 # number of overall (read+write) accesses 839system.cpu.icache.overall_accesses::total 837449249 # number of overall (read+write) accesses 840system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015919 # miss rate for ReadReq accesses 841system.cpu.icache.ReadReq_miss_rate::total 0.015919 # miss rate for ReadReq accesses 842system.cpu.icache.demand_miss_rate::cpu.inst 0.015919 # miss rate for demand accesses 843system.cpu.icache.demand_miss_rate::total 0.015919 # miss rate for demand accesses 844system.cpu.icache.overall_miss_rate::cpu.inst 0.015919 # miss rate for overall accesses 845system.cpu.icache.overall_miss_rate::total 0.015919 # miss rate for overall accesses 846system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13673.648694 # average ReadReq miss latency 847system.cpu.icache.ReadReq_avg_miss_latency::total 13673.648694 # average ReadReq miss latency 848system.cpu.icache.demand_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency 849system.cpu.icache.demand_avg_miss_latency::total 13673.648694 # average overall miss latency 850system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency 851system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency |
| 850system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 851system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 852system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 853system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 854system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 855system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 856system.cpu.icache.fast_writes 0 # number of fast writes performed 857system.cpu.icache.cache_copies 0 # number of cache copies performed | 852system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 853system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 854system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 855system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 856system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 857system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 858system.cpu.icache.fast_writes 0 # number of fast writes performed 859system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 858system.cpu.icache.writebacks::writebacks 13387387 # number of writebacks 859system.cpu.icache.writebacks::total 13387387 # number of writebacks 860system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13387904 # number of ReadReq MSHR misses 861system.cpu.icache.ReadReq_mshr_misses::total 13387904 # number of ReadReq MSHR misses 862system.cpu.icache.demand_mshr_misses::cpu.inst 13387904 # number of demand (read+write) MSHR misses 863system.cpu.icache.demand_mshr_misses::total 13387904 # number of demand (read+write) MSHR misses 864system.cpu.icache.overall_mshr_misses::cpu.inst 13387904 # number of overall MSHR misses 865system.cpu.icache.overall_mshr_misses::total 13387904 # number of overall MSHR misses | 860system.cpu.icache.writebacks::writebacks 13331164 # number of writebacks 861system.cpu.icache.writebacks::total 13331164 # number of writebacks 862system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13331681 # number of ReadReq MSHR misses 863system.cpu.icache.ReadReq_mshr_misses::total 13331681 # number of ReadReq MSHR misses 864system.cpu.icache.demand_mshr_misses::cpu.inst 13331681 # number of demand (read+write) MSHR misses 865system.cpu.icache.demand_mshr_misses::total 13331681 # number of demand (read+write) MSHR misses 866system.cpu.icache.overall_mshr_misses::cpu.inst 13331681 # number of overall MSHR misses 867system.cpu.icache.overall_mshr_misses::total 13331681 # number of overall MSHR misses |
| 866system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 867system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 868system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 869system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses | 868system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 869system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 870system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 871system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses |
| 870system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169396551500 # number of ReadReq MSHR miss cycles 871system.cpu.icache.ReadReq_mshr_miss_latency::total 169396551500 # number of ReadReq MSHR miss cycles 872system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169396551500 # number of demand (read+write) MSHR miss cycles 873system.cpu.icache.demand_mshr_miss_latency::total 169396551500 # number of demand (read+write) MSHR miss cycles 874system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169396551500 # number of overall MSHR miss cycles 875system.cpu.icache.overall_mshr_miss_latency::total 169396551500 # number of overall MSHR miss cycles | 872system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168961041500 # number of ReadReq MSHR miss cycles 873system.cpu.icache.ReadReq_mshr_miss_latency::total 168961041500 # number of ReadReq MSHR miss cycles 874system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168961041500 # number of demand (read+write) MSHR miss cycles 875system.cpu.icache.demand_mshr_miss_latency::total 168961041500 # number of demand (read+write) MSHR miss cycles 876system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168961041500 # number of overall MSHR miss cycles 877system.cpu.icache.overall_mshr_miss_latency::total 168961041500 # number of overall MSHR miss cycles |
| 876system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles 877system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles 878system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles 879system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles | 878system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles 879system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles 880system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles 881system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles |
| 880system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for ReadReq accesses 881system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016149 # mshr miss rate for ReadReq accesses 882system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for demand accesses 883system.cpu.icache.demand_mshr_miss_rate::total 0.016149 # mshr miss rate for demand accesses 884system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for overall accesses 885system.cpu.icache.overall_mshr_miss_rate::total 0.016149 # mshr miss rate for overall accesses 886system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12652.955347 # average ReadReq mshr miss latency 887system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12652.955347 # average ReadReq mshr miss latency 888system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency 889system.cpu.icache.demand_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency 890system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency 891system.cpu.icache.overall_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency | 882system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for ReadReq accesses 883system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015919 # mshr miss rate for ReadReq accesses 884system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for demand accesses 885system.cpu.icache.demand_mshr_miss_rate::total 0.015919 # mshr miss rate for demand accesses 886system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for overall accesses 887system.cpu.icache.overall_mshr_miss_rate::total 0.015919 # mshr miss rate for overall accesses 888system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12673.648694 # average ReadReq mshr miss latency 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12673.648694 # average ReadReq mshr miss latency 890system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency 892system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency |
| 892system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency 893system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency 894system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency 895system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency 896system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 894system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency 895system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency 896system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency 897system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency 898system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 897system.cpu.l2cache.tags.replacements 999968 # number of replacements 898system.cpu.l2cache.tags.tagsinuse 65207.127423 # Cycle average of tags in use 899system.cpu.l2cache.tags.total_refs 41555308 # Total number of references to valid blocks. 900system.cpu.l2cache.tags.sampled_refs 1062213 # Sample count of references to valid blocks. 901system.cpu.l2cache.tags.avg_refs 39.121446 # Average number of references to valid blocks. 902system.cpu.l2cache.tags.warmup_cycle 56076472500 # Cycle when the warmup percentage was hit. 903system.cpu.l2cache.tags.occ_blocks::writebacks 37737.548410 # Average occupied blocks per requestor 904system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 210.383401 # Average occupied blocks per requestor 905system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 313.931857 # Average occupied blocks per requestor 906system.cpu.l2cache.tags.occ_blocks::cpu.inst 8489.634618 # Average occupied blocks per requestor 907system.cpu.l2cache.tags.occ_blocks::cpu.data 18455.629136 # Average occupied blocks per requestor 908system.cpu.l2cache.tags.occ_percent::writebacks 0.575829 # Average percentage of cache occupancy 909system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003210 # Average percentage of cache occupancy 910system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004790 # Average percentage of cache occupancy 911system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129542 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::cpu.data 0.281611 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_percent::total 0.994982 # Average percentage of cache occupancy 914system.cpu.l2cache.tags.occ_task_id_blocks::1023 253 # Occupied blocks per task id 915system.cpu.l2cache.tags.occ_task_id_blocks::1024 61992 # Occupied blocks per task id 916system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1023::4 252 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::1 400 # Occupied blocks per task id 920system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id 921system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5510 # Occupied blocks per task id 922system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53605 # Occupied blocks per task id 923system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003860 # Percentage of cache occupancy per task id 924system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945923 # Percentage of cache occupancy per task id 925system.cpu.l2cache.tags.tag_accesses 371220882 # Number of tag accesses 926system.cpu.l2cache.tags.data_accesses 371220882 # Number of data accesses 927system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 309149 # number of ReadReq hits 928system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242072 # number of ReadReq hits 929system.cpu.l2cache.ReadReq_hits::total 551221 # number of ReadReq hits 930system.cpu.l2cache.WritebackDirty_hits::writebacks 7246265 # number of WritebackDirty hits 931system.cpu.l2cache.WritebackDirty_hits::total 7246265 # number of WritebackDirty hits 932system.cpu.l2cache.WritebackClean_hits::writebacks 13385787 # number of WritebackClean hits 933system.cpu.l2cache.WritebackClean_hits::total 13385787 # number of WritebackClean hits 934system.cpu.l2cache.UpgradeReq_hits::cpu.data 8844 # number of UpgradeReq hits 935system.cpu.l2cache.UpgradeReq_hits::total 8844 # number of UpgradeReq hits 936system.cpu.l2cache.ReadExReq_hits::cpu.data 1588762 # number of ReadExReq hits 937system.cpu.l2cache.ReadExReq_hits::total 1588762 # number of ReadExReq hits 938system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13318339 # number of ReadCleanReq hits 939system.cpu.l2cache.ReadCleanReq_hits::total 13318339 # number of ReadCleanReq hits 940system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5906127 # number of ReadSharedReq hits 941system.cpu.l2cache.ReadSharedReq_hits::total 5906127 # number of ReadSharedReq hits 942system.cpu.l2cache.InvalidateReq_hits::cpu.data 738986 # number of InvalidateReq hits 943system.cpu.l2cache.InvalidateReq_hits::total 738986 # number of InvalidateReq hits 944system.cpu.l2cache.demand_hits::cpu.dtb.walker 309149 # number of demand (read+write) hits 945system.cpu.l2cache.demand_hits::cpu.itb.walker 242072 # number of demand (read+write) hits 946system.cpu.l2cache.demand_hits::cpu.inst 13318339 # number of demand (read+write) hits 947system.cpu.l2cache.demand_hits::cpu.data 7494889 # number of demand (read+write) hits 948system.cpu.l2cache.demand_hits::total 21364449 # number of demand (read+write) hits 949system.cpu.l2cache.overall_hits::cpu.dtb.walker 309149 # number of overall hits 950system.cpu.l2cache.overall_hits::cpu.itb.walker 242072 # number of overall hits 951system.cpu.l2cache.overall_hits::cpu.inst 13318339 # number of overall hits 952system.cpu.l2cache.overall_hits::cpu.data 7494889 # number of overall hits 953system.cpu.l2cache.overall_hits::total 21364449 # number of overall hits 954system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2087 # number of ReadReq misses 955system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2218 # number of ReadReq misses 956system.cpu.l2cache.ReadReq_misses::total 4305 # number of ReadReq misses 957system.cpu.l2cache.UpgradeReq_misses::cpu.data 32563 # number of UpgradeReq misses 958system.cpu.l2cache.UpgradeReq_misses::total 32563 # number of UpgradeReq misses 959system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 960system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 961system.cpu.l2cache.ReadExReq_misses::cpu.data 316699 # number of ReadExReq misses 962system.cpu.l2cache.ReadExReq_misses::total 316699 # number of ReadExReq misses 963system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 69565 # number of ReadCleanReq misses 964system.cpu.l2cache.ReadCleanReq_misses::total 69565 # number of ReadCleanReq misses 965system.cpu.l2cache.ReadSharedReq_misses::cpu.data 220633 # number of ReadSharedReq misses 966system.cpu.l2cache.ReadSharedReq_misses::total 220633 # number of ReadSharedReq misses 967system.cpu.l2cache.InvalidateReq_misses::cpu.data 480041 # number of InvalidateReq misses 968system.cpu.l2cache.InvalidateReq_misses::total 480041 # number of InvalidateReq misses 969system.cpu.l2cache.demand_misses::cpu.dtb.walker 2087 # number of demand (read+write) misses 970system.cpu.l2cache.demand_misses::cpu.itb.walker 2218 # number of demand (read+write) misses 971system.cpu.l2cache.demand_misses::cpu.inst 69565 # number of demand (read+write) misses 972system.cpu.l2cache.demand_misses::cpu.data 537332 # number of demand (read+write) misses 973system.cpu.l2cache.demand_misses::total 611202 # number of demand (read+write) misses 974system.cpu.l2cache.overall_misses::cpu.dtb.walker 2087 # number of overall misses 975system.cpu.l2cache.overall_misses::cpu.itb.walker 2218 # number of overall misses 976system.cpu.l2cache.overall_misses::cpu.inst 69565 # number of overall misses 977system.cpu.l2cache.overall_misses::cpu.data 537332 # number of overall misses 978system.cpu.l2cache.overall_misses::total 611202 # number of overall misses 979system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 283625500 # number of ReadReq miss cycles 980system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 302800500 # number of ReadReq miss cycles 981system.cpu.l2cache.ReadReq_miss_latency::total 586426000 # number of ReadReq miss cycles 982system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1304021500 # number of UpgradeReq miss cycles 983system.cpu.l2cache.UpgradeReq_miss_latency::total 1304021500 # number of UpgradeReq miss cycles 984system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 985system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 986system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41520058500 # number of ReadExReq miss cycles 987system.cpu.l2cache.ReadExReq_miss_latency::total 41520058500 # number of ReadExReq miss cycles 988system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9207851000 # number of ReadCleanReq miss cycles 989system.cpu.l2cache.ReadCleanReq_miss_latency::total 9207851000 # number of ReadCleanReq miss cycles 990system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29368319500 # number of ReadSharedReq miss cycles 991system.cpu.l2cache.ReadSharedReq_miss_latency::total 29368319500 # number of ReadSharedReq miss cycles 992system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 62527677000 # number of InvalidateReq miss cycles 993system.cpu.l2cache.InvalidateReq_miss_latency::total 62527677000 # number of InvalidateReq miss cycles 994system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 283625500 # number of demand (read+write) miss cycles 995system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 302800500 # number of demand (read+write) miss cycles 996system.cpu.l2cache.demand_miss_latency::cpu.inst 9207851000 # number of demand (read+write) miss cycles 997system.cpu.l2cache.demand_miss_latency::cpu.data 70888378000 # number of demand (read+write) miss cycles 998system.cpu.l2cache.demand_miss_latency::total 80682655000 # number of demand (read+write) miss cycles 999system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 283625500 # number of overall miss cycles 1000system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 302800500 # number of overall miss cycles 1001system.cpu.l2cache.overall_miss_latency::cpu.inst 9207851000 # number of overall miss cycles 1002system.cpu.l2cache.overall_miss_latency::cpu.data 70888378000 # number of overall miss cycles 1003system.cpu.l2cache.overall_miss_latency::total 80682655000 # number of overall miss cycles 1004system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 311236 # number of ReadReq accesses(hits+misses) 1005system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244290 # number of ReadReq accesses(hits+misses) 1006system.cpu.l2cache.ReadReq_accesses::total 555526 # number of ReadReq accesses(hits+misses) 1007system.cpu.l2cache.WritebackDirty_accesses::writebacks 7246265 # number of WritebackDirty accesses(hits+misses) 1008system.cpu.l2cache.WritebackDirty_accesses::total 7246265 # number of WritebackDirty accesses(hits+misses) 1009system.cpu.l2cache.WritebackClean_accesses::writebacks 13385787 # number of WritebackClean accesses(hits+misses) 1010system.cpu.l2cache.WritebackClean_accesses::total 13385787 # number of WritebackClean accesses(hits+misses) 1011system.cpu.l2cache.UpgradeReq_accesses::cpu.data 41407 # number of UpgradeReq accesses(hits+misses) 1012system.cpu.l2cache.UpgradeReq_accesses::total 41407 # number of UpgradeReq accesses(hits+misses) 1013system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1014system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1015system.cpu.l2cache.ReadExReq_accesses::cpu.data 1905461 # number of ReadExReq accesses(hits+misses) 1016system.cpu.l2cache.ReadExReq_accesses::total 1905461 # number of ReadExReq accesses(hits+misses) 1017system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13387904 # number of ReadCleanReq accesses(hits+misses) 1018system.cpu.l2cache.ReadCleanReq_accesses::total 13387904 # number of ReadCleanReq accesses(hits+misses) 1019system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6126760 # number of ReadSharedReq accesses(hits+misses) 1020system.cpu.l2cache.ReadSharedReq_accesses::total 6126760 # number of ReadSharedReq accesses(hits+misses) 1021system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1219027 # number of InvalidateReq accesses(hits+misses) 1022system.cpu.l2cache.InvalidateReq_accesses::total 1219027 # number of InvalidateReq accesses(hits+misses) 1023system.cpu.l2cache.demand_accesses::cpu.dtb.walker 311236 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.itb.walker 244290 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.inst 13387904 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::cpu.data 8032221 # number of demand (read+write) accesses 1027system.cpu.l2cache.demand_accesses::total 21975651 # number of demand (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.dtb.walker 311236 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.itb.walker 244290 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::cpu.inst 13387904 # number of overall (read+write) accesses 1031system.cpu.l2cache.overall_accesses::cpu.data 8032221 # number of overall (read+write) accesses 1032system.cpu.l2cache.overall_accesses::total 21975651 # number of overall (read+write) accesses 1033system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006706 # miss rate for ReadReq accesses 1034system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009079 # miss rate for ReadReq accesses 1035system.cpu.l2cache.ReadReq_miss_rate::total 0.007749 # miss rate for ReadReq accesses 1036system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.786413 # miss rate for UpgradeReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::total 0.786413 # miss rate for UpgradeReq accesses | 899system.cpu.l2cache.tags.replacements 1036266 # number of replacements 900system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use 901system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks. 902system.cpu.l2cache.tags.sampled_refs 1098550 # Sample count of references to valid blocks. 903system.cpu.l2cache.tags.avg_refs 37.921538 # Average number of references to valid blocks. 904system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit. 905system.cpu.l2cache.tags.occ_blocks::writebacks 38127.362532 # Average occupied blocks per requestor 906system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 231.236011 # Average occupied blocks per requestor 907system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 356.535935 # Average occupied blocks per requestor 908system.cpu.l2cache.tags.occ_blocks::cpu.inst 7851.500133 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_blocks::cpu.data 18688.418163 # Average occupied blocks per requestor 910system.cpu.l2cache.tags.occ_percent::writebacks 0.581777 # Average percentage of cache occupancy 911system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003528 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005440 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119804 # Average percentage of cache occupancy 914system.cpu.l2cache.tags.occ_percent::cpu.data 0.285163 # Average percentage of cache occupancy 915system.cpu.l2cache.tags.occ_percent::total 0.995713 # Average percentage of cache occupancy 916system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id 917system.cpu.l2cache.tags.occ_task_id_blocks::1024 62027 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 920system.cpu.l2cache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id 921system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2434 # Occupied blocks per task id 922system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5507 # Occupied blocks per task id 923system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53647 # Occupied blocks per task id 924system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id 925system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id 926system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses 927system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses 928system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits 929system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits 930system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits 931system.cpu.l2cache.WritebackDirty_hits::writebacks 7313678 # number of WritebackDirty hits 932system.cpu.l2cache.WritebackDirty_hits::total 7313678 # number of WritebackDirty hits 933system.cpu.l2cache.WritebackClean_hits::writebacks 13329610 # number of WritebackClean hits 934system.cpu.l2cache.WritebackClean_hits::total 13329610 # number of WritebackClean hits 935system.cpu.l2cache.UpgradeReq_hits::cpu.data 9057 # number of UpgradeReq hits 936system.cpu.l2cache.UpgradeReq_hits::total 9057 # number of UpgradeReq hits 937system.cpu.l2cache.ReadExReq_hits::cpu.data 1592946 # number of ReadExReq hits 938system.cpu.l2cache.ReadExReq_hits::total 1592946 # number of ReadExReq hits 939system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13260241 # number of ReadCleanReq hits 940system.cpu.l2cache.ReadCleanReq_hits::total 13260241 # number of ReadCleanReq hits 941system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5999138 # number of ReadSharedReq hits 942system.cpu.l2cache.ReadSharedReq_hits::total 5999138 # number of ReadSharedReq hits 943system.cpu.l2cache.InvalidateReq_hits::cpu.data 739812 # number of InvalidateReq hits 944system.cpu.l2cache.InvalidateReq_hits::total 739812 # number of InvalidateReq hits 945system.cpu.l2cache.demand_hits::cpu.dtb.walker 313678 # number of demand (read+write) hits 946system.cpu.l2cache.demand_hits::cpu.itb.walker 242392 # number of demand (read+write) hits 947system.cpu.l2cache.demand_hits::cpu.inst 13260241 # number of demand (read+write) hits 948system.cpu.l2cache.demand_hits::cpu.data 7592084 # number of demand (read+write) hits 949system.cpu.l2cache.demand_hits::total 21408395 # number of demand (read+write) hits 950system.cpu.l2cache.overall_hits::cpu.dtb.walker 313678 # number of overall hits 951system.cpu.l2cache.overall_hits::cpu.itb.walker 242392 # number of overall hits 952system.cpu.l2cache.overall_hits::cpu.inst 13260241 # number of overall hits 953system.cpu.l2cache.overall_hits::cpu.data 7592084 # number of overall hits 954system.cpu.l2cache.overall_hits::total 21408395 # number of overall hits 955system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2426 # number of ReadReq misses 956system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2490 # number of ReadReq misses 957system.cpu.l2cache.ReadReq_misses::total 4916 # number of ReadReq misses 958system.cpu.l2cache.UpgradeReq_misses::cpu.data 33285 # number of UpgradeReq misses 959system.cpu.l2cache.UpgradeReq_misses::total 33285 # number of UpgradeReq misses 960system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 961system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 962system.cpu.l2cache.ReadExReq_misses::cpu.data 341588 # number of ReadExReq misses 963system.cpu.l2cache.ReadExReq_misses::total 341588 # number of ReadExReq misses 964system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 71440 # number of ReadCleanReq misses 965system.cpu.l2cache.ReadCleanReq_misses::total 71440 # number of ReadCleanReq misses 966system.cpu.l2cache.ReadSharedReq_misses::cpu.data 227336 # number of ReadSharedReq misses 967system.cpu.l2cache.ReadSharedReq_misses::total 227336 # number of ReadSharedReq misses 968system.cpu.l2cache.InvalidateReq_misses::cpu.data 481698 # number of InvalidateReq misses 969system.cpu.l2cache.InvalidateReq_misses::total 481698 # number of InvalidateReq misses 970system.cpu.l2cache.demand_misses::cpu.dtb.walker 2426 # number of demand (read+write) misses 971system.cpu.l2cache.demand_misses::cpu.itb.walker 2490 # number of demand (read+write) misses 972system.cpu.l2cache.demand_misses::cpu.inst 71440 # number of demand (read+write) misses 973system.cpu.l2cache.demand_misses::cpu.data 568924 # number of demand (read+write) misses 974system.cpu.l2cache.demand_misses::total 645280 # number of demand (read+write) misses 975system.cpu.l2cache.overall_misses::cpu.dtb.walker 2426 # number of overall misses 976system.cpu.l2cache.overall_misses::cpu.itb.walker 2490 # number of overall misses 977system.cpu.l2cache.overall_misses::cpu.inst 71440 # number of overall misses 978system.cpu.l2cache.overall_misses::cpu.data 568924 # number of overall misses 979system.cpu.l2cache.overall_misses::total 645280 # number of overall misses 980system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 332065500 # number of ReadReq miss cycles 981system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345888500 # number of ReadReq miss cycles 982system.cpu.l2cache.ReadReq_miss_latency::total 677954000 # number of ReadReq miss cycles 983system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1332961000 # number of UpgradeReq miss cycles 984system.cpu.l2cache.UpgradeReq_miss_latency::total 1332961000 # number of UpgradeReq miss cycles 985system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 986system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles 987system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 44822292500 # number of ReadExReq miss cycles 988system.cpu.l2cache.ReadExReq_miss_latency::total 44822292500 # number of ReadExReq miss cycles 989system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9464687500 # number of ReadCleanReq miss cycles 990system.cpu.l2cache.ReadCleanReq_miss_latency::total 9464687500 # number of ReadCleanReq miss cycles 991system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30322723500 # number of ReadSharedReq miss cycles 992system.cpu.l2cache.ReadSharedReq_miss_latency::total 30322723500 # number of ReadSharedReq miss cycles 993system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 542500 # number of InvalidateReq miss cycles 994system.cpu.l2cache.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles 995system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 332065500 # number of demand (read+write) miss cycles 996system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345888500 # number of demand (read+write) miss cycles 997system.cpu.l2cache.demand_miss_latency::cpu.inst 9464687500 # number of demand (read+write) miss cycles 998system.cpu.l2cache.demand_miss_latency::cpu.data 75145016000 # number of demand (read+write) miss cycles 999system.cpu.l2cache.demand_miss_latency::total 85287657500 # number of demand (read+write) miss cycles 1000system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 332065500 # number of overall miss cycles 1001system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345888500 # number of overall miss cycles 1002system.cpu.l2cache.overall_miss_latency::cpu.inst 9464687500 # number of overall miss cycles 1003system.cpu.l2cache.overall_miss_latency::cpu.data 75145016000 # number of overall miss cycles 1004system.cpu.l2cache.overall_miss_latency::total 85287657500 # number of overall miss cycles 1005system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 316104 # number of ReadReq accesses(hits+misses) 1006system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244882 # number of ReadReq accesses(hits+misses) 1007system.cpu.l2cache.ReadReq_accesses::total 560986 # number of ReadReq accesses(hits+misses) 1008system.cpu.l2cache.WritebackDirty_accesses::writebacks 7313678 # number of WritebackDirty accesses(hits+misses) 1009system.cpu.l2cache.WritebackDirty_accesses::total 7313678 # number of WritebackDirty accesses(hits+misses) 1010system.cpu.l2cache.WritebackClean_accesses::writebacks 13329610 # number of WritebackClean accesses(hits+misses) 1011system.cpu.l2cache.WritebackClean_accesses::total 13329610 # number of WritebackClean accesses(hits+misses) 1012system.cpu.l2cache.UpgradeReq_accesses::cpu.data 42342 # number of UpgradeReq accesses(hits+misses) 1013system.cpu.l2cache.UpgradeReq_accesses::total 42342 # number of UpgradeReq accesses(hits+misses) 1014system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 1015system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 1016system.cpu.l2cache.ReadExReq_accesses::cpu.data 1934534 # number of ReadExReq accesses(hits+misses) 1017system.cpu.l2cache.ReadExReq_accesses::total 1934534 # number of ReadExReq accesses(hits+misses) 1018system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13331681 # number of ReadCleanReq accesses(hits+misses) 1019system.cpu.l2cache.ReadCleanReq_accesses::total 13331681 # number of ReadCleanReq accesses(hits+misses) 1020system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6226474 # number of ReadSharedReq accesses(hits+misses) 1021system.cpu.l2cache.ReadSharedReq_accesses::total 6226474 # number of ReadSharedReq accesses(hits+misses) 1022system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1221510 # number of InvalidateReq accesses(hits+misses) 1023system.cpu.l2cache.InvalidateReq_accesses::total 1221510 # number of InvalidateReq accesses(hits+misses) 1024system.cpu.l2cache.demand_accesses::cpu.dtb.walker 316104 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.itb.walker 244882 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::cpu.inst 13331681 # number of demand (read+write) accesses 1027system.cpu.l2cache.demand_accesses::cpu.data 8161008 # number of demand (read+write) accesses 1028system.cpu.l2cache.demand_accesses::total 22053675 # number of demand (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.dtb.walker 316104 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::cpu.itb.walker 244882 # number of overall (read+write) accesses 1031system.cpu.l2cache.overall_accesses::cpu.inst 13331681 # number of overall (read+write) accesses 1032system.cpu.l2cache.overall_accesses::cpu.data 8161008 # number of overall (read+write) accesses 1033system.cpu.l2cache.overall_accesses::total 22053675 # number of overall (read+write) accesses 1034system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007675 # miss rate for ReadReq accesses 1035system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010168 # miss rate for ReadReq accesses 1036system.cpu.l2cache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.786099 # miss rate for UpgradeReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::total 0.786099 # miss rate for UpgradeReq accesses |
| 1038system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1039system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1039system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1040system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1040system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.166206 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.ReadExReq_miss_rate::total 0.166206 # miss rate for ReadExReq accesses 1042system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005196 # miss rate for ReadCleanReq accesses 1043system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005196 # miss rate for ReadCleanReq accesses 1044system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036011 # miss rate for ReadSharedReq accesses 1045system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036011 # miss rate for ReadSharedReq accesses 1046system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.393790 # miss rate for InvalidateReq accesses 1047system.cpu.l2cache.InvalidateReq_miss_rate::total 0.393790 # miss rate for InvalidateReq accesses 1048system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006706 # miss rate for demand accesses 1049system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009079 # miss rate for demand accesses 1050system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005196 # miss rate for demand accesses 1051system.cpu.l2cache.demand_miss_rate::cpu.data 0.066897 # miss rate for demand accesses 1052system.cpu.l2cache.demand_miss_rate::total 0.027813 # miss rate for demand accesses 1053system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006706 # miss rate for overall accesses 1054system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009079 # miss rate for overall accesses 1055system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005196 # miss rate for overall accesses 1056system.cpu.l2cache.overall_miss_rate::cpu.data 0.066897 # miss rate for overall accesses 1057system.cpu.l2cache.overall_miss_rate::total 0.027813 # miss rate for overall accesses 1058system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135901.054145 # average ReadReq miss latency 1059system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136519.612263 # average ReadReq miss latency 1060system.cpu.l2cache.ReadReq_avg_miss_latency::total 136219.744483 # average ReadReq miss latency 1061system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40046.110616 # average UpgradeReq miss latency 1062system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40046.110616 # average UpgradeReq miss latency 1063system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency 1064system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency 1065system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131102.587946 # average ReadExReq miss latency 1066system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131102.587946 # average ReadExReq miss latency 1067system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132363.271760 # average ReadCleanReq miss latency 1068system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132363.271760 # average ReadCleanReq miss latency 1069system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133109.369405 # average ReadSharedReq miss latency 1070system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133109.369405 # average ReadSharedReq miss latency 1071system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130254.867813 # average InvalidateReq miss latency 1072system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130254.867813 # average InvalidateReq miss latency 1073system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135901.054145 # average overall miss latency 1074system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136519.612263 # average overall miss latency 1075system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132363.271760 # average overall miss latency 1076system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131926.589148 # average overall miss latency 1077system.cpu.l2cache.demand_avg_miss_latency::total 132006.529756 # average overall miss latency 1078system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135901.054145 # average overall miss latency 1079system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136519.612263 # average overall miss latency 1080system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132363.271760 # average overall miss latency 1081system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131926.589148 # average overall miss latency 1082system.cpu.l2cache.overall_avg_miss_latency::total 132006.529756 # average overall miss latency | 1041system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.176574 # miss rate for ReadExReq accesses 1042system.cpu.l2cache.ReadExReq_miss_rate::total 0.176574 # miss rate for ReadExReq accesses 1043system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005359 # miss rate for ReadCleanReq accesses 1044system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005359 # miss rate for ReadCleanReq accesses 1045system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036511 # miss rate for ReadSharedReq accesses 1046system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036511 # miss rate for ReadSharedReq accesses 1047system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.394346 # miss rate for InvalidateReq accesses 1048system.cpu.l2cache.InvalidateReq_miss_rate::total 0.394346 # miss rate for InvalidateReq accesses 1049system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007675 # miss rate for demand accesses 1050system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010168 # miss rate for demand accesses 1051system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005359 # miss rate for demand accesses 1052system.cpu.l2cache.demand_miss_rate::cpu.data 0.069712 # miss rate for demand accesses 1053system.cpu.l2cache.demand_miss_rate::total 0.029260 # miss rate for demand accesses 1054system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007675 # miss rate for overall accesses 1055system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010168 # miss rate for overall accesses 1056system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005359 # miss rate for overall accesses 1057system.cpu.l2cache.overall_miss_rate::cpu.data 0.069712 # miss rate for overall accesses 1058system.cpu.l2cache.overall_miss_rate::total 0.029260 # miss rate for overall accesses 1059system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136877.782358 # average ReadReq miss latency 1060system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138911.044177 # average ReadReq miss latency 1061system.cpu.l2cache.ReadReq_avg_miss_latency::total 137907.648495 # average ReadReq miss latency 1062system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40046.898002 # average UpgradeReq miss latency 1063system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40046.898002 # average UpgradeReq miss latency 1064system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1065system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1066system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131217.409569 # average ReadExReq miss latency 1067system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131217.409569 # average ReadExReq miss latency 1068system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132484.427492 # average ReadCleanReq miss latency 1069system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132484.427492 # average ReadCleanReq miss latency 1070system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133382.849615 # average ReadSharedReq miss latency 1071system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133382.849615 # average ReadSharedReq miss latency 1072system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 1.126224 # average InvalidateReq miss latency 1073system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 1.126224 # average InvalidateReq miss latency 1074system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency 1075system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency 1076system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency 1077system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency 1078system.cpu.l2cache.demand_avg_miss_latency::total 132171.549560 # average overall miss latency 1079system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency 1080system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency 1081system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency 1082system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency 1083system.cpu.l2cache.overall_avg_miss_latency::total 132171.549560 # average overall miss latency |
| 1083system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1084system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1085system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1086system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1087system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1088system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1089system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1090system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1084system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1085system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1086system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1087system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1088system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1089system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1090system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1091system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1091system.cpu.l2cache.writebacks::writebacks 850095 # number of writebacks 1092system.cpu.l2cache.writebacks::total 850095 # number of writebacks 1093system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2087 # number of ReadReq MSHR misses 1094system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2218 # number of ReadReq MSHR misses 1095system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses 1096system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 32563 # number of UpgradeReq MSHR misses 1097system.cpu.l2cache.UpgradeReq_mshr_misses::total 32563 # number of UpgradeReq MSHR misses 1098system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1099system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1100system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 316699 # number of ReadExReq MSHR misses 1101system.cpu.l2cache.ReadExReq_mshr_misses::total 316699 # number of ReadExReq MSHR misses 1102system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 69565 # number of ReadCleanReq MSHR misses 1103system.cpu.l2cache.ReadCleanReq_mshr_misses::total 69565 # number of ReadCleanReq MSHR misses 1104system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 220633 # number of ReadSharedReq MSHR misses 1105system.cpu.l2cache.ReadSharedReq_mshr_misses::total 220633 # number of ReadSharedReq MSHR misses 1106system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 480041 # number of InvalidateReq MSHR misses 1107system.cpu.l2cache.InvalidateReq_mshr_misses::total 480041 # number of InvalidateReq MSHR misses 1108system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2087 # number of demand (read+write) MSHR misses 1109system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2218 # number of demand (read+write) MSHR misses 1110system.cpu.l2cache.demand_mshr_misses::cpu.inst 69565 # number of demand (read+write) MSHR misses 1111system.cpu.l2cache.demand_mshr_misses::cpu.data 537332 # number of demand (read+write) MSHR misses 1112system.cpu.l2cache.demand_mshr_misses::total 611202 # number of demand (read+write) MSHR misses 1113system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2087 # number of overall MSHR misses 1114system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2218 # number of overall MSHR misses 1115system.cpu.l2cache.overall_mshr_misses::cpu.inst 69565 # number of overall MSHR misses 1116system.cpu.l2cache.overall_mshr_misses::cpu.data 537332 # number of overall MSHR misses 1117system.cpu.l2cache.overall_mshr_misses::total 611202 # number of overall MSHR misses | 1092system.cpu.l2cache.writebacks::writebacks 879823 # number of writebacks 1093system.cpu.l2cache.writebacks::total 879823 # number of writebacks 1094system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2426 # number of ReadReq MSHR misses 1095system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2490 # number of ReadReq MSHR misses 1096system.cpu.l2cache.ReadReq_mshr_misses::total 4916 # number of ReadReq MSHR misses 1097system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33285 # number of UpgradeReq MSHR misses 1098system.cpu.l2cache.UpgradeReq_mshr_misses::total 33285 # number of UpgradeReq MSHR misses 1099system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1100system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1101system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341588 # number of ReadExReq MSHR misses 1102system.cpu.l2cache.ReadExReq_mshr_misses::total 341588 # number of ReadExReq MSHR misses 1103system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 71440 # number of ReadCleanReq MSHR misses 1104system.cpu.l2cache.ReadCleanReq_mshr_misses::total 71440 # number of ReadCleanReq MSHR misses 1105system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 227336 # number of ReadSharedReq MSHR misses 1106system.cpu.l2cache.ReadSharedReq_mshr_misses::total 227336 # number of ReadSharedReq MSHR misses 1107system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 481698 # number of InvalidateReq MSHR misses 1108system.cpu.l2cache.InvalidateReq_mshr_misses::total 481698 # number of InvalidateReq MSHR misses 1109system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2426 # number of demand (read+write) MSHR misses 1110system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2490 # number of demand (read+write) MSHR misses 1111system.cpu.l2cache.demand_mshr_misses::cpu.inst 71440 # number of demand (read+write) MSHR misses 1112system.cpu.l2cache.demand_mshr_misses::cpu.data 568924 # number of demand (read+write) MSHR misses 1113system.cpu.l2cache.demand_mshr_misses::total 645280 # number of demand (read+write) MSHR misses 1114system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2426 # number of overall MSHR misses 1115system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2490 # number of overall MSHR misses 1116system.cpu.l2cache.overall_mshr_misses::cpu.inst 71440 # number of overall MSHR misses 1117system.cpu.l2cache.overall_mshr_misses::cpu.data 568924 # number of overall MSHR misses 1118system.cpu.l2cache.overall_mshr_misses::total 645280 # number of overall MSHR misses |
| 1118system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1119system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 1120system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable 1121system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 1122system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 1123system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1124system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 1125system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses | 1119system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1120system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 1121system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable 1122system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 1123system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 1124system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1125system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 1126system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses |
| 1126system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 262755500 # number of ReadReq MSHR miss cycles 1127system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280620500 # number of ReadReq MSHR miss cycles 1128system.cpu.l2cache.ReadReq_mshr_miss_latency::total 543376000 # number of ReadReq MSHR miss cycles 1129system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2212537500 # number of UpgradeReq MSHR miss cycles 1130system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2212537500 # number of UpgradeReq MSHR miss cycles 1131system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles 1132system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles 1133system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38353068500 # number of ReadExReq MSHR miss cycles 1134system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38353068500 # number of ReadExReq MSHR miss cycles 1135system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8512201000 # number of ReadCleanReq MSHR miss cycles 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8512201000 # number of ReadCleanReq MSHR miss cycles 1137system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27161989500 # number of ReadSharedReq MSHR miss cycles 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27161989500 # number of ReadSharedReq MSHR miss cycles 1139system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 57727267000 # number of InvalidateReq MSHR miss cycles 1140system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 57727267000 # number of InvalidateReq MSHR miss cycles 1141system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 262755500 # number of demand (read+write) MSHR miss cycles 1142system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280620500 # number of demand (read+write) MSHR miss cycles 1143system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8512201000 # number of demand (read+write) MSHR miss cycles 1144system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65515058000 # 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number of ReadReq MSHR miss cycles 1130system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2261111000 # number of UpgradeReq MSHR miss cycles 1131system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2261111000 # number of UpgradeReq MSHR miss cycles 1132system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles 1133system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles 1134system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41406412500 # number of ReadExReq MSHR miss cycles 1135system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41406412500 # number of ReadExReq MSHR miss cycles 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8750287500 # number of ReadCleanReq MSHR miss cycles 1137system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8750287500 # number of ReadCleanReq MSHR miss cycles 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28049107014 # number of ReadSharedReq MSHR miss cycles 1139system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28049107014 # number of ReadSharedReq MSHR miss cycles 1140system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 32589969500 # number of InvalidateReq MSHR miss cycles 1141system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 32589969500 # number of InvalidateReq MSHR miss cycles 1142system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 307805500 # number of demand (read+write) MSHR miss cycles 1143system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 320988500 # number of demand (read+write) MSHR miss cycles 1144system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8750287500 # number of demand (read+write) MSHR miss cycles 1145system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69455519514 # number of demand (read+write) MSHR miss cycles 1146system.cpu.l2cache.demand_mshr_miss_latency::total 78834601014 # number of demand (read+write) MSHR miss cycles 1147system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 307805500 # number of overall MSHR miss cycles 1148system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 320988500 # number of overall MSHR miss cycles 1149system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8750287500 # number of overall MSHR miss cycles 1150system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69455519514 # number of overall MSHR miss cycles 1151system.cpu.l2cache.overall_mshr_miss_latency::total 78834601014 # number of overall MSHR miss cycles |
| 1151system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles | 1152system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles |
| 1152system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777574500 # number of ReadReq MSHR uncacheable cycles 1153system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675299000 # number of ReadReq MSHR uncacheable cycles 1154system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829970500 # number of WriteReq MSHR uncacheable cycles 1155system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829970500 # number of WriteReq MSHR uncacheable cycles | 1153system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777601500 # number of ReadReq MSHR uncacheable cycles 1154system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675326000 # number of ReadReq MSHR uncacheable cycles 1155system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829950000 # number of WriteReq MSHR uncacheable cycles 1156system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829950000 # number of WriteReq MSHR uncacheable cycles |
| 1156system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles | 1157system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles |
| 1157system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607545000 # number of overall MSHR uncacheable cycles 1158system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505269500 # number of overall MSHR uncacheable cycles 1159system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for ReadReq accesses 1160system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for ReadReq accesses 1161system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007749 # mshr miss rate for ReadReq accesses 1162system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786413 # mshr miss rate for UpgradeReq accesses 1163system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786413 # mshr miss rate for UpgradeReq accesses | 1158system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607551500 # number of overall MSHR uncacheable cycles 1159system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505276000 # number of overall MSHR uncacheable cycles 1160system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses 1161system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses 1162system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses 1163system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses 1164system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses |
| 1164system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1165system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1165system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1166system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1166system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166206 # mshr miss rate for ReadExReq accesses 1167system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166206 # mshr miss rate for ReadExReq accesses 1168system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for ReadCleanReq accesses 1169system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005196 # mshr miss rate for ReadCleanReq accesses 1170system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036011 # mshr miss rate for ReadSharedReq accesses 1171system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036011 # mshr miss rate for ReadSharedReq accesses 1172system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.393790 # mshr miss rate for InvalidateReq accesses 1173system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.393790 # mshr miss rate for InvalidateReq accesses 1174system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for demand accesses 1175system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for demand accesses 1176system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for demand accesses 1177system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for demand accesses 1178system.cpu.l2cache.demand_mshr_miss_rate::total 0.027813 # mshr miss rate for demand accesses 1179system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for overall accesses 1180system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for overall accesses 1181system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for overall accesses 1182system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for overall accesses 1183system.cpu.l2cache.overall_mshr_miss_rate::total 0.027813 # mshr miss rate for overall accesses 1184system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average ReadReq mshr miss latency 1185system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average ReadReq mshr miss latency 1186system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126219.744483 # average ReadReq mshr miss latency 1187system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67946.365507 # average UpgradeReq mshr miss latency 1188system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67946.365507 # average UpgradeReq mshr miss latency 1189system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency 1190system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency 1191system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121102.587946 # average ReadExReq mshr miss latency 1192system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121102.587946 # average ReadExReq mshr miss latency 1193system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122363.271760 # average ReadCleanReq mshr miss latency 1194system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122363.271760 # average ReadCleanReq mshr miss latency 1195system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123109.369405 # average ReadSharedReq mshr miss latency 1196system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123109.369405 # average ReadSharedReq mshr miss latency 1197system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120254.867813 # average InvalidateReq mshr miss latency 1198system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120254.867813 # average InvalidateReq mshr miss latency 1199system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency 1200system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency 1201system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency 1202system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency 1203system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency 1204system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency 1205system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency 1206system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency 1207system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency 1208system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency | 1167system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses 1168system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176574 # mshr miss rate for ReadExReq accesses 1169system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for ReadCleanReq accesses 1170system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005359 # mshr miss rate for ReadCleanReq accesses 1171system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036511 # mshr miss rate for ReadSharedReq accesses 1172system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadSharedReq accesses 1173system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394346 # mshr miss rate for InvalidateReq accesses 1174system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394346 # mshr miss rate for InvalidateReq accesses 1175system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for demand accesses 1176system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for demand accesses 1177system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for demand accesses 1178system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for demand accesses 1179system.cpu.l2cache.demand_mshr_miss_rate::total 0.029260 # mshr miss rate for demand accesses 1180system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for overall accesses 1181system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for overall accesses 1182system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for overall accesses 1183system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for overall accesses 1184system.cpu.l2cache.overall_mshr_miss_rate::total 0.029260 # mshr miss rate for overall accesses 1185system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average ReadReq mshr miss latency 1186system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average ReadReq mshr miss latency 1187system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127907.648495 # average ReadReq mshr miss latency 1188system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67931.831155 # average UpgradeReq mshr miss latency 1189system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67931.831155 # average UpgradeReq mshr miss latency 1190system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1191system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1192system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121217.409569 # average ReadExReq mshr miss latency 1193system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121217.409569 # average ReadExReq mshr miss latency 1194system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122484.427492 # average ReadCleanReq mshr miss latency 1195system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122484.427492 # average ReadCleanReq mshr miss latency 1196system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123381.721390 # average ReadSharedReq mshr miss latency 1197system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123381.721390 # average ReadSharedReq mshr miss latency 1198system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67656.435152 # average InvalidateReq mshr miss latency 1199system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67656.435152 # average InvalidateReq mshr miss latency 1200system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency 1201system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency 1202system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency 1203system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency 1204system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency 1205system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency 1206system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency 1207system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency 1208system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency 1209system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency |
| 1209system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency | 1210system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency |
| 1210system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171431.205863 # average ReadReq mshr uncacheable latency 1211system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.438596 # average ReadReq mshr uncacheable latency 1212system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172955.099680 # average WriteReq mshr uncacheable latency 1213system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172955.099680 # average WriteReq mshr uncacheable latency | 1211system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency 1212system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency 1213system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.491515 # average WriteReq mshr uncacheable latency 1214system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.491515 # average WriteReq mshr uncacheable latency |
| 1214system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency | 1215system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency |
| 1215system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.220590 # average overall mshr uncacheable latency 1216system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.658298 # average overall mshr uncacheable latency | 1216system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.317015 # average overall mshr uncacheable latency 1217system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.717103 # average overall mshr uncacheable latency |
| 1217system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1218system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1218system.cpu.toL2Bus.snoop_filter.tot_requests 45794965 # Total number of requests made to the snoop filter. 1219system.cpu.toL2Bus.snoop_filter.hit_single_requests 23155820 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1220system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1221system.cpu.toL2Bus.snoop_filter.tot_snoops 2699 # Total number of snoops made to the snoop filter. 1222system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2699 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1219system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter. 1220system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1221system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1222system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. 1223system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1223system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1224system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1224system.cpu.toL2Bus.trans_dist::ReadReq 972147 # Transaction distribution 1225system.cpu.toL2Bus.trans_dist::ReadResp 20487667 # Transaction distribution | 1225system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution 1226system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution |
| 1226system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution 1227system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution | 1227system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution 1228system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution |
| 1228system.cpu.toL2Bus.trans_dist::WritebackDirty 8203050 # Transaction distribution 1229system.cpu.toL2Bus.trans_dist::WritebackClean 13387387 # Transaction distribution 1230system.cpu.toL2Bus.trans_dist::CleanEvict 2163174 # Transaction distribution 1231system.cpu.toL2Bus.trans_dist::UpgradeReq 41410 # Transaction distribution 1232system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1233system.cpu.toL2Bus.trans_dist::UpgradeResp 41412 # Transaction distribution 1234system.cpu.toL2Bus.trans_dist::ReadExReq 1905461 # Transaction distribution 1235system.cpu.toL2Bus.trans_dist::ReadExResp 1905461 # Transaction distribution 1236system.cpu.toL2Bus.trans_dist::ReadCleanReq 13387904 # Transaction distribution 1237system.cpu.toL2Bus.trans_dist::ReadSharedReq 6135636 # Transaction distribution 1238system.cpu.toL2Bus.trans_dist::InvalidateReq 1325691 # Transaction distribution 1239system.cpu.toL2Bus.trans_dist::InvalidateResp 1219027 # Transaction distribution 1240system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40249445 # Packet count per connected master and slave (bytes) 1241system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27971705 # Packet count per connected master and slave (bytes) 1242system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598323 # Packet count per connected master and slave (bytes) 1243system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 852523 # Packet count per connected master and slave (bytes) 1244system.cpu.toL2Bus.pkt_count::total 69671996 # Packet count per connected master and slave (bytes) 1245system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1713791124 # Cumulative packet size per connected master and slave (bytes) 1246system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978068334 # Cumulative packet size per connected master and slave (bytes) 1247system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1954320 # Cumulative packet size per connected master and slave (bytes) 1248system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2489888 # Cumulative packet size per connected master and slave (bytes) 1249system.cpu.toL2Bus.pkt_size::total 2696303666 # Cumulative packet size per connected master and slave (bytes) 1250system.cpu.toL2Bus.snoops 1571708 # Total snoops (count) 1251system.cpu.toL2Bus.snoop_fanout::samples 24917471 # Request fanout histogram 1252system.cpu.toL2Bus.snoop_fanout::mean 0.019294 # Request fanout histogram 1253system.cpu.toL2Bus.snoop_fanout::stdev 0.137557 # Request fanout histogram | 1229system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution 1230system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution 1231system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution 1232system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution 1233system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1234system.cpu.toL2Bus.trans_dist::UpgradeResp 42346 # Transaction distribution 1235system.cpu.toL2Bus.trans_dist::ReadExReq 1934534 # Transaction distribution 1236system.cpu.toL2Bus.trans_dist::ReadExResp 1934534 # Transaction distribution 1237system.cpu.toL2Bus.trans_dist::ReadCleanReq 13331681 # Transaction distribution 1238system.cpu.toL2Bus.trans_dist::ReadSharedReq 6235371 # Transaction distribution 1239system.cpu.toL2Bus.trans_dist::InvalidateReq 1328174 # Transaction distribution 1240system.cpu.toL2Bus.trans_dist::InvalidateResp 1221510 # Transaction distribution 1241system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40080776 # Packet count per connected master and slave (bytes) 1242system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28367342 # Packet count per connected master and slave (bytes) 1243system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601942 # Packet count per connected master and slave (bytes) 1244system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 864211 # Packet count per connected master and slave (bytes) 1245system.cpu.toL2Bus.pkt_count::total 69914271 # Packet count per connected master and slave (bytes) 1246system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1706594580 # Cumulative packet size per connected master and slave (bytes) 1247system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 990623790 # Cumulative packet size per connected master and slave (bytes) 1248system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959056 # Cumulative packet size per connected master and slave (bytes) 1249system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2528832 # Cumulative packet size per connected master and slave (bytes) 1250system.cpu.toL2Bus.pkt_size::total 2701706258 # Cumulative packet size per connected master and slave (bytes) 1251system.cpu.toL2Bus.snoops 1612380 # Total snoops (count) 1252system.cpu.toL2Bus.snoop_fanout::samples 25039605 # Request fanout histogram 1253system.cpu.toL2Bus.snoop_fanout::mean 0.019510 # Request fanout histogram 1254system.cpu.toL2Bus.snoop_fanout::stdev 0.138308 # Request fanout histogram |
| 1254system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1255system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1255system.cpu.toL2Bus.snoop_fanout::0 24436707 98.07% 98.07% # Request fanout histogram 1256system.cpu.toL2Bus.snoop_fanout::1 480764 1.93% 100.00% # Request fanout histogram | 1256system.cpu.toL2Bus.snoop_fanout::0 24551092 98.05% 98.05% # Request fanout histogram 1257system.cpu.toL2Bus.snoop_fanout::1 488513 1.95% 100.00% # Request fanout histogram |
| 1257system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1258system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1259system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1260system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1258system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1259system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1260system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1261system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1261system.cpu.toL2Bus.snoop_fanout::total 24917471 # Request fanout histogram 1262system.cpu.toL2Bus.reqLayer0.occupancy 43812763500 # Layer occupancy (ticks) | 1262system.cpu.toL2Bus.snoop_fanout::total 25039605 # Request fanout histogram 1263system.cpu.toL2Bus.reqLayer0.occupancy 43904381000 # Layer occupancy (ticks) |
| 1263system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1264system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1264system.cpu.toL2Bus.snoopLayer0.occupancy 1591387 # Layer occupancy (ticks) | 1265system.cpu.toL2Bus.snoopLayer0.occupancy 1555895 # Layer occupancy (ticks) |
| 1265system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1266system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1266system.cpu.toL2Bus.respLayer0.occupancy 20124981000 # Layer occupancy (ticks) | 1267system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks) |
| 1267system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1268system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1268system.cpu.toL2Bus.respLayer1.occupancy 12729124462 # Layer occupancy (ticks) | 1269system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks) |
| 1269system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1270system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1270system.cpu.toL2Bus.respLayer2.occupancy 354033000 # Layer occupancy (ticks) | 1271system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks) |
| 1271system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1272system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1272system.cpu.toL2Bus.respLayer3.occupancy 541287000 # Layer occupancy (ticks) | 1273system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks) |
| 1273system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1274system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1274system.iobus.trans_dist::ReadReq 40324 # Transaction distribution 1275system.iobus.trans_dist::ReadResp 40324 # Transaction distribution | 1275system.iobus.trans_dist::ReadReq 40345 # Transaction distribution 1276system.iobus.trans_dist::ReadResp 40345 # Transaction distribution |
| 1276system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1277system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1278system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1279system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1280system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1281system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1282system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1283system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1284system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1285system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1286system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1287system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1288system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1289system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1290system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1291system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) | 1277system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1278system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1279system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1280system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1281system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1282system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1283system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1284system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1285system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1286system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1287system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1288system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1289system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1290system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1291system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1292system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) |
| 1292system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) 1293system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) | 1293system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231048 # Packet count per connected master and slave (bytes) 1294system.iobus.pkt_count_system.realview.ide.dma::total 231048 # Packet count per connected master and slave (bytes) |
| 1294system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1295system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 1295system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1296system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 1296system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) | 1297system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) |
| 1297system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1298system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1299system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1300system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1301system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1302system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1303system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1304system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1305system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1306system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1307system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1308system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1309system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1310system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) | 1298system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1299system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1300system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1301system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1302system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1303system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1304system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1305system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1306system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1307system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1308system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1309system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1310system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1311system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) |
| 1311system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) 1312system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) | 1312system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334624 # Cumulative packet size per connected master and slave (bytes) 1313system.iobus.pkt_size_system.realview.ide.dma::total 7334624 # Cumulative packet size per connected master and slave (bytes) |
| 1313system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1314system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 1314system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1315system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 1315system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) 1316system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) | 1316system.iobus.pkt_size::total 7492544 # Cumulative packet size per connected master and slave (bytes) 1317system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) |
| 1317system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1318system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1318system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) | 1319system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) |
| 1319system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1320system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) 1321system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1322system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1323system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1320system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1321system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) 1322system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1323system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1324system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 1324system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks) | 1325system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) |
| 1325system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1326system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 1327system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1328system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1329system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1330system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1331system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1332system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1333system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 1326system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1327system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 1328system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1329system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1330system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1331system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1332system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1333system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1334system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 1334system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) | 1335system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) |
| 1335system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1336system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1337system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 1336system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1337system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1338system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 1338system.iobus.reqLayer23.occupancy 25712000 # Layer occupancy (ticks) | 1339system.iobus.reqLayer23.occupancy 25723500 # Layer occupancy (ticks) |
| 1339system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1340system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1340system.iobus.reqLayer24.occupancy 38603000 # Layer occupancy (ticks) | 1341system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) |
| 1341system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1342system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1342system.iobus.reqLayer25.occupancy 566837671 # Layer occupancy (ticks) | 1343system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks) |
| 1343system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1344system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1345system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1344system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1345system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1346system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1346system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) | 1347system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks) |
| 1347system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1348system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1349system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 1348system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1349system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1350system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 1350system.iocache.tags.replacements 115484 # number of replacements 1351system.iocache.tags.tagsinuse 10.446945 # Cycle average of tags in use | 1351system.iocache.tags.replacements 115506 # number of replacements 1352system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use |
| 1352system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 1353system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 1353system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. | 1354system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. |
| 1354system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 1355system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 1355system.iocache.tags.warmup_cycle 13183709781000 # Cycle when the warmup percentage was hit. 1356system.iocache.tags.occ_blocks::realview.ethernet 3.511462 # Average occupied blocks per requestor 1357system.iocache.tags.occ_blocks::realview.ide 6.935482 # Average occupied blocks per requestor 1358system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy 1359system.iocache.tags.occ_percent::realview.ide 0.433468 # Average percentage of cache occupancy 1360system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy | 1356system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. 1357system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor 1358system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor 1359system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy 1360system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy 1361system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy |
| 1361system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1362system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1363system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1362system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1363system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1364system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1364system.iocache.tags.tag_accesses 1039884 # Number of tag accesses 1365system.iocache.tags.data_accesses 1039884 # Number of data accesses | 1365system.iocache.tags.tag_accesses 1040073 # Number of tag accesses 1366system.iocache.tags.data_accesses 1040073 # Number of data accesses |
| 1366system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 1367system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 1367system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 1368system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses | 1368system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses 1369system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses |
| 1369system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1370system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1371system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1372system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1373system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1370system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1371system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1372system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1373system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1374system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 1374system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses 1375system.iocache.demand_misses::total 8879 # number of demand (read+write) misses | 1375system.iocache.demand_misses::realview.ide 8860 # number of demand (read+write) misses 1376system.iocache.demand_misses::total 8900 # number of demand (read+write) misses |
| 1376system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1377system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 1377system.iocache.overall_misses::realview.ide 8839 # number of overall misses 1378system.iocache.overall_misses::total 8879 # number of overall misses 1379system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles 1380system.iocache.ReadReq_miss_latency::realview.ide 1648554138 # number of ReadReq miss cycles 1381system.iocache.ReadReq_miss_latency::total 1653624638 # number of ReadReq miss cycles | 1378system.iocache.overall_misses::realview.ide 8860 # number of overall misses 1379system.iocache.overall_misses::total 8900 # number of overall misses 1380system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles 1381system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles 1382system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles |
| 1382system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1383system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles | 1383system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1384system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles |
| 1384system.iocache.WriteLineReq_miss_latency::realview.ide 13411902033 # number of WriteLineReq miss cycles 1385system.iocache.WriteLineReq_miss_latency::total 13411902033 # number of WriteLineReq miss cycles 1386system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles 1387system.iocache.demand_miss_latency::realview.ide 1648554138 # number of demand (read+write) miss cycles 1388system.iocache.demand_miss_latency::total 1653975638 # number of demand (read+write) miss cycles 1389system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles 1390system.iocache.overall_miss_latency::realview.ide 1648554138 # number of overall miss cycles 1391system.iocache.overall_miss_latency::total 1653975638 # number of overall miss cycles | 1385system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles 1386system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles 1387system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles 1388system.iocache.demand_miss_latency::realview.ide 1628892126 # number of demand (read+write) miss cycles 1389system.iocache.demand_miss_latency::total 1634313126 # number of demand (read+write) miss cycles 1390system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles 1391system.iocache.overall_miss_latency::realview.ide 1628892126 # number of overall miss cycles 1392system.iocache.overall_miss_latency::total 1634313126 # number of overall miss cycles |
| 1392system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 1393system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 1393system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) 1394system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) | 1394system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses) 1395system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses) |
| 1395system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1396system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1397system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1398system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1399system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1396system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1397system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1398system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1399system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1400system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 1400system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses 1401system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses | 1401system.iocache.demand_accesses::realview.ide 8860 # number of demand (read+write) accesses 1402system.iocache.demand_accesses::total 8900 # number of demand (read+write) accesses |
| 1402system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1403system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 1403system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses 1404system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses | 1404system.iocache.overall_accesses::realview.ide 8860 # number of overall (read+write) accesses 1405system.iocache.overall_accesses::total 8900 # number of overall (read+write) accesses |
| 1405system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1406system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1407system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1408system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1409system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1410system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1411system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1412system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1413system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1414system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1415system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1416system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1417system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1406system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1407system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1408system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1409system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1410system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1411system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1412system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1413system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1414system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1415system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1416system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1417system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1418system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1418system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency 1419system.iocache.ReadReq_avg_miss_latency::realview.ide 186509.122978 # average ReadReq miss latency 1420system.iocache.ReadReq_avg_miss_latency::total 186302.910996 # average ReadReq miss latency | 1419system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency 1420system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency 1421system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency |
| 1421system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1422system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency | 1422system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1423system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency |
| 1423system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.725053 # average WriteLineReq miss latency 1424system.iocache.WriteLineReq_avg_miss_latency::total 125739.725053 # average WriteLineReq miss latency 1425system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency 1426system.iocache.demand_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency 1427system.iocache.demand_avg_miss_latency::total 186279.495213 # average overall miss latency 1428system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency 1429system.iocache.overall_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency 1430system.iocache.overall_avg_miss_latency::total 186279.495213 # average overall miss latency 1431system.iocache.blocked_cycles::no_mshrs 32796 # number of cycles access was blocked | 1424system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency 1425system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency 1426system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1427system.iocache.demand_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency 1428system.iocache.demand_avg_miss_latency::total 183630.688315 # average overall miss latency 1429system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1430system.iocache.overall_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency 1431system.iocache.overall_avg_miss_latency::total 183630.688315 # average overall miss latency 1432system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked |
| 1432system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1433system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1433system.iocache.blocked::no_mshrs 3360 # number of cycles access was blocked | 1434system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked |
| 1434system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1435system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1435system.iocache.avg_blocked_cycles::no_mshrs 9.760714 # average number of cycles each access was blocked | 1436system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked |
| 1436system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1437system.iocache.fast_writes 0 # number of fast writes performed 1438system.iocache.cache_copies 0 # number of cache copies performed | 1437system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1438system.iocache.fast_writes 0 # number of fast writes performed 1439system.iocache.cache_copies 0 # number of cache copies performed |
| 1439system.iocache.writebacks::writebacks 106630 # number of writebacks 1440system.iocache.writebacks::total 106630 # number of writebacks | 1440system.iocache.writebacks::writebacks 106631 # number of writebacks 1441system.iocache.writebacks::total 106631 # number of writebacks |
| 1441system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses | 1442system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
| 1442system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses 1443system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses | 1443system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses 1444system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses |
| 1444system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1445system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1446system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1447system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1448system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 1445system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1446system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1447system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1448system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1449system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 1449system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses 1450system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses | 1450system.iocache.demand_mshr_misses::realview.ide 8860 # number of demand (read+write) MSHR misses 1451system.iocache.demand_mshr_misses::total 8900 # number of demand (read+write) MSHR misses |
| 1451system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 1452system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 1452system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses 1453system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses 1454system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles 1455system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206604138 # number of ReadReq MSHR miss cycles 1456system.iocache.ReadReq_mshr_miss_latency::total 1209824638 # number of ReadReq MSHR miss cycles | 1453system.iocache.overall_mshr_misses::realview.ide 8860 # number of overall MSHR misses 1454system.iocache.overall_mshr_misses::total 8900 # number of overall MSHR misses 1455system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles 1456system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles 1457system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles |
| 1457system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1458system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles | 1458system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1459system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles |
| 1459system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073565122 # number of WriteLineReq MSHR miss cycles 1460system.iocache.WriteLineReq_mshr_miss_latency::total 8073565122 # number of WriteLineReq MSHR miss cycles 1461system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles 1462system.iocache.demand_mshr_miss_latency::realview.ide 1206604138 # number of demand (read+write) MSHR miss cycles 1463system.iocache.demand_mshr_miss_latency::total 1210025638 # number of demand (read+write) MSHR miss cycles 1464system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles 1465system.iocache.overall_mshr_miss_latency::realview.ide 1206604138 # number of overall MSHR miss cycles 1466system.iocache.overall_mshr_miss_latency::total 1210025638 # number of overall MSHR miss cycles | 1460system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles 1461system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles 1462system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles 1463system.iocache.demand_mshr_miss_latency::realview.ide 1185892126 # number of demand (read+write) MSHR miss cycles 1464system.iocache.demand_mshr_miss_latency::total 1189313126 # number of demand (read+write) MSHR miss cycles 1465system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles 1466system.iocache.overall_mshr_miss_latency::realview.ide 1185892126 # number of overall MSHR miss cycles 1467system.iocache.overall_mshr_miss_latency::total 1189313126 # number of overall MSHR miss cycles |
| 1467system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1468system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1469system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1470system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1471system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1472system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1473system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1474system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1475system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1476system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1477system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1478system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1479system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1468system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1469system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1470system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1471system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1472system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1473system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1474system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1475system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1476system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1477system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1478system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1479system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1480system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1480system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency 1481system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136509.122978 # average ReadReq mshr miss latency 1482system.iocache.ReadReq_avg_mshr_miss_latency::total 136302.910996 # average ReadReq mshr miss latency | 1481system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency 1482system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency 1483system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency |
| 1483system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1484system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency | 1484system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1485system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency |
| 1485system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.565308 # average WriteLineReq mshr miss latency 1486system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.565308 # average WriteLineReq mshr miss latency 1487system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency 1488system.iocache.demand_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency 1489system.iocache.demand_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency 1490system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency 1491system.iocache.overall_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency 1492system.iocache.overall_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency | 1486system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency 1487system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency 1488system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1489system.iocache.demand_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency 1490system.iocache.demand_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency 1491system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1492system.iocache.overall_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency 1493system.iocache.overall_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency |
| 1493system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1494system.membus.trans_dist::ReadReq 76827 # Transaction distribution | 1494system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1495system.membus.trans_dist::ReadReq 76827 # Transaction distribution |
| 1495system.membus.trans_dist::ReadResp 380206 # Transaction distribution | 1496system.membus.trans_dist::ReadResp 389416 # Transaction distribution |
| 1496system.membus.trans_dist::WriteReq 33708 # Transaction distribution 1497system.membus.trans_dist::WriteResp 33708 # Transaction distribution | 1497system.membus.trans_dist::WriteReq 33708 # Transaction distribution 1498system.membus.trans_dist::WriteResp 33708 # Transaction distribution |
| 1498system.membus.trans_dist::WritebackDirty 956725 # Transaction distribution 1499system.membus.trans_dist::CleanEvict 157718 # Transaction distribution 1500system.membus.trans_dist::UpgradeReq 33138 # Transaction distribution 1501system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1502system.membus.trans_dist::UpgradeResp 8 # Transaction distribution 1503system.membus.trans_dist::ReadExReq 796168 # Transaction distribution 1504system.membus.trans_dist::ReadExResp 796168 # Transaction distribution 1505system.membus.trans_dist::ReadSharedReq 303379 # Transaction distribution 1506system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution | 1499system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution 1500system.membus.trans_dist::CleanEvict 164302 # Transaction distribution 1501system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution 1502system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1503system.membus.trans_dist::UpgradeResp 7 # Transaction distribution 1504system.membus.trans_dist::ReadExReq 341030 # Transaction distribution 1505system.membus.trans_dist::ReadExResp 341030 # Transaction distribution 1506system.membus.trans_dist::ReadSharedReq 312589 # Transaction distribution 1507system.membus.trans_dist::InvalidateReq 588355 # Transaction distribution |
| 1507system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1508system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1509system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) | 1508system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1509system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1510system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) |
| 1510system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3304162 # Packet count per connected master and slave (bytes) 1511system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3433854 # Packet count per connected master and slave (bytes) 1512system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237247 # Packet count per connected master and slave (bytes) 1513system.membus.pkt_count_system.iocache.mem_side::total 237247 # Packet count per connected master and slave (bytes) 1514system.membus.pkt_count::total 3671101 # Packet count per connected master and slave (bytes) | 1511system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2930961 # Packet count per connected master and slave (bytes) 1512system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3060653 # Packet count per connected master and slave (bytes) 1513system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237312 # Packet count per connected master and slave (bytes) 1514system.membus.pkt_count_system.iocache.mem_side::total 237312 # Packet count per connected master and slave (bytes) 1515system.membus.pkt_count::total 3297965 # Packet count per connected master and slave (bytes) |
| 1515system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1516system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1517system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) | 1516system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1517system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1518system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) |
| 1518system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124360288 # Cumulative packet size per connected master and slave (bytes) 1519system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124530114 # Cumulative packet size per connected master and slave (bytes) 1520system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7222400 # Cumulative packet size per connected master and slave (bytes) 1521system.membus.pkt_size_system.iocache.mem_side::total 7222400 # Cumulative packet size per connected master and slave (bytes) 1522system.membus.pkt_size::total 131752514 # Cumulative packet size per connected master and slave (bytes) 1523system.membus.snoops 3318 # Total snoops (count) 1524system.membus.snoop_fanout::samples 2464390 # Request fanout histogram | 1519system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97722208 # Cumulative packet size per connected master and slave (bytes) 1520system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97892034 # Cumulative packet size per connected master and slave (bytes) 1521system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7223872 # Cumulative packet size per connected master and slave (bytes) 1522system.membus.pkt_size_system.iocache.mem_side::total 7223872 # Cumulative packet size per connected master and slave (bytes) 1523system.membus.pkt_size::total 105115906 # Cumulative packet size per connected master and slave (bytes) 1524system.membus.snoops 3315 # Total snoops (count) 1525system.membus.snoop_fanout::samples 2537144 # Request fanout histogram |
| 1525system.membus.snoop_fanout::mean 1 # Request fanout histogram 1526system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1527system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1528system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1526system.membus.snoop_fanout::mean 1 # Request fanout histogram 1527system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1528system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1529system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1529system.membus.snoop_fanout::1 2464390 100.00% 100.00% # Request fanout histogram | 1530system.membus.snoop_fanout::1 2537144 100.00% 100.00% # Request fanout histogram |
| 1530system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1531system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1532system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1533system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1531system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1532system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1533system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1534system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1534system.membus.snoop_fanout::total 2464390 # Request fanout histogram 1535system.membus.reqLayer0.occupancy 106890000 # Layer occupancy (ticks) | 1535system.membus.snoop_fanout::total 2537144 # Request fanout histogram 1536system.membus.reqLayer0.occupancy 106903500 # Layer occupancy (ticks) |
| 1536system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1537system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1538system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1537system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1538system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1539system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1539system.membus.reqLayer2.occupancy 5800500 # Layer occupancy (ticks) | 1540system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks) |
| 1540system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1541system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1541system.membus.reqLayer5.occupancy 6292280855 # Layer occupancy (ticks) | 1542system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks) |
| 1542system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1543system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1543system.membus.respLayer2.occupancy 5974901047 # Layer occupancy (ticks) | 1544system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks) |
| 1544system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1545system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1545system.membus.respLayer3.occupancy 44724954 # Layer occupancy (ticks) | 1546system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks) |
| 1546system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1547system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1548system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1549system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1550system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1551system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1552system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1553system.realview.ethernet.txBytes 966 # Bytes Transmitted --- 47 unchanged lines hidden --- | 1547system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1548system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1549system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1550system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1551system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1552system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1553system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1554system.realview.ethernet.txBytes 966 # Bytes Transmitted --- 47 unchanged lines hidden --- |