| stats.txt (10752:62b24818c8c6) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.824462 # Number of seconds simulated 4sim_ticks 51824462100500 # Number of ticks simulated 5final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.824462 # Number of seconds simulated 4sim_ticks 51824462100500 # Number of ticks simulated 5final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 723017 # Simulator instruction rate (inst/s) 8host_op_rate 849578 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41937024652 # Simulator tick rate (ticks/s) 10host_mem_usage 712044 # Number of bytes of host memory used 11host_seconds 1235.77 # Real time elapsed on the host | 7host_inst_rate 684695 # Simulator instruction rate (inst/s) 8host_op_rate 804548 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39714246392 # Simulator tick rate (ticks/s) 10host_mem_usage 713112 # Number of bytes of host memory used 11host_seconds 1304.93 # Real time elapsed on the host |
| 12sim_insts 893481288 # Number of instructions simulated 13sim_ops 1049881338 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory --- 706 unchanged lines hidden (view full) --- 726system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses 727system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses 728system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 729system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 730system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses 731system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses 732system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses 733system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses | 12sim_insts 893481288 # Number of instructions simulated 13sim_ops 1049881338 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory --- 706 unchanged lines hidden (view full) --- 726system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses 727system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses 728system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 729system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 730system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses 731system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses 732system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses 733system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses |
| 734system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 735system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable 736system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 737system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 738system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 739system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses |
|
| 734system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles 735system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles 736system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles 737system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles 738system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles 739system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles 740system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles 741system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles --- 38 unchanged lines hidden (view full) --- 780system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency 781system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency 782system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 783system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 784system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency 785system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency 786system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency 787system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency | 740system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles 741system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles 742system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles 743system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles 744system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles 745system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles 746system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles 747system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles --- 38 unchanged lines hidden (view full) --- 786system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency 787system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency 788system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 789system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 790system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency 791system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency 792system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency 793system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency |
| 788system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 789system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 790system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 791system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 792system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 793system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 794system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177 # average ReadReq mshr uncacheable latency 795system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177 # average ReadReq mshr uncacheable latency 796system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056 # average WriteReq mshr uncacheable latency 797system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056 # average WriteReq mshr uncacheable latency 798system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813 # average overall mshr uncacheable latency 799system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813 # average overall mshr uncacheable latency |
| 794system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 795system.cpu.icache.tags.replacements 13753173 # number of replacements 796system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use 797system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks. 798system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks. 799system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks. 800system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit. 801system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor --- 52 unchanged lines hidden (view full) --- 854system.cpu.icache.fast_writes 0 # number of fast writes performed 855system.cpu.icache.cache_copies 0 # number of cache copies performed 856system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13753690 # number of ReadReq MSHR misses 857system.cpu.icache.ReadReq_mshr_misses::total 13753690 # number of ReadReq MSHR misses 858system.cpu.icache.demand_mshr_misses::cpu.inst 13753690 # number of demand (read+write) MSHR misses 859system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses 860system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses 861system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses | 800system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 801system.cpu.icache.tags.replacements 13753173 # number of replacements 802system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use 803system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks. 804system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks. 805system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks. 806system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit. 807system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor --- 52 unchanged lines hidden (view full) --- 860system.cpu.icache.fast_writes 0 # number of fast writes performed 861system.cpu.icache.cache_copies 0 # number of cache copies performed 862system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13753690 # number of ReadReq MSHR misses 863system.cpu.icache.ReadReq_mshr_misses::total 13753690 # number of ReadReq MSHR misses 864system.cpu.icache.demand_mshr_misses::cpu.inst 13753690 # number of demand (read+write) MSHR misses 865system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses 866system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses 867system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses |
| 868system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 869system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 870system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 871system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses |
|
| 862system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles 863system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles 864system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles 865system.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles 866system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles 867system.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles 868system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles 869system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 876system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses 877system.cpu.icache.overall_mshr_miss_rate::total 0.015384 # mshr miss rate for overall accesses 878system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367 # average ReadReq mshr miss latency 879system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367 # average ReadReq mshr miss latency 880system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency 881system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency 882system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency 883system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency | 872system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles 873system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles 874system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles 875system.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles 876system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles 877system.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles 878system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles 879system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 886system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses 887system.cpu.icache.overall_mshr_miss_rate::total 0.015384 # mshr miss rate for overall accesses 888system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367 # average ReadReq mshr miss latency 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367 # average ReadReq mshr miss latency 890system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency 892system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency |
| 884system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 885system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 886system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 887system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 894system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average ReadReq mshr uncacheable latency 895system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74459.988406 # average ReadReq mshr uncacheable latency 896system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average overall mshr uncacheable latency 897system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74459.988406 # average overall mshr uncacheable latency |
| 888system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 889system.cpu.l2cache.tags.replacements 1292250 # number of replacements 890system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use 891system.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks. 892system.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks. 893system.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks. 894system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit. 895system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor --- 188 unchanged lines hidden (view full) --- 1084system.cpu.l2cache.demand_mshr_misses::cpu.inst 79532 # number of demand (read+write) MSHR misses 1085system.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses 1088system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses 1091system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses | 898system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 899system.cpu.l2cache.tags.replacements 1292250 # number of replacements 900system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use 901system.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks. 902system.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks. 903system.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks. 904system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit. 905system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor --- 188 unchanged lines hidden (view full) --- 1094system.cpu.l2cache.demand_mshr_misses::cpu.inst 79532 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses 1096system.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses 1099system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses 1100system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses 1101system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses |
| 1102system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1103system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 1104system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable 1105system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 1106system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 1107system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1108system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 1109system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses |
|
| 1092system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles 1093system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles 1094system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles 1095system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles 1096system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles 1097system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles 1098system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles 1099system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles --- 61 unchanged lines hidden (view full) --- 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency 1163system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency | 1110system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles 1111system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles 1113system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles 1114system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles 1115system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles 1116system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles 1117system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles --- 61 unchanged lines hidden (view full) --- 1179system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency 1180system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency 1181system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency 1184system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency 1185system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency 1186system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency |
| 1169system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1170system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1171system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1172system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1173system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1174system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1175system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1176system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1187system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average ReadReq mshr uncacheable latency 1188system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235 # average ReadReq mshr uncacheable latency 1189system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374 # average ReadReq mshr uncacheable latency 1190system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131 # average WriteReq mshr uncacheable latency 1191system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131 # average WriteReq mshr uncacheable latency 1192system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average overall mshr uncacheable latency 1193system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508 # average overall mshr uncacheable latency 1194system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603 # average overall mshr uncacheable latency |
| 1177system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1178system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution --- 8 unchanged lines hidden (view full) --- 1193system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) 1194system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) 1197system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) 1198system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) 1200system.cpu.toL2Bus.snoops 470306 # Total snoops (count) | 1195system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1196system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution 1198system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution 1200system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution 1201system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution 1202system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution --- 8 unchanged lines hidden (view full) --- 1211system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) 1212system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) 1213system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) 1214system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) 1217system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu.toL2Bus.snoops 470306 # Total snoops (count) |
| 1201system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram 1202system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram 1203system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram | 1219system.cpu.toL2Bus.snoop_fanout::samples 33102923 # Request fanout histogram 1220system.cpu.toL2Bus.snoop_fanout::mean 1.033230 # Request fanout histogram 1221system.cpu.toL2Bus.snoop_fanout::stdev 0.179236 # Request fanout histogram |
| 1204system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1205system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1222system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1223system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1206system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram | 1224system.cpu.toL2Bus.snoop_fanout::1 32002916 96.68% 96.68% # Request fanout histogram 1225system.cpu.toL2Bus.snoop_fanout::2 1100007 3.32% 100.00% # Request fanout histogram |
| 1210system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1226system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1211system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram | 1227system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1228system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1229system.cpu.toL2Bus.snoop_fanout::total 33102923 # Request fanout histogram |
| 1214system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) 1215system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1216system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) 1217system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1218system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) 1219system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1220system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) 1221system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 254 unchanged lines hidden (view full) --- 1476system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1477system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) 1478system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) 1479system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) 1480system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) 1481system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) 1482system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) 1483system.membus.snoops 3324 # Total snoops (count) | 1230system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) 1231system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1232system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) 1233system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1234system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) 1235system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1236system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) 1237system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 254 unchanged lines hidden (view full) --- 1492system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1493system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) 1494system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) 1495system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) 1496system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) 1497system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) 1498system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) 1499system.membus.snoops 3324 # Total snoops (count) |
| 1484system.membus.snoop_fanout::samples 2750930 # Request fanout histogram | 1500system.membus.snoop_fanout::samples 2861471 # Request fanout histogram |
| 1485system.membus.snoop_fanout::mean 1 # Request fanout histogram 1486system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1487system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1488system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1501system.membus.snoop_fanout::mean 1 # Request fanout histogram 1502system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1503system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1504system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1489system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram | 1505system.membus.snoop_fanout::1 2861471 100.00% 100.00% # Request fanout histogram |
| 1490system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1491system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1492system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1493system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1506system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1507system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1508system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1509system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1494system.membus.snoop_fanout::total 2750930 # Request fanout histogram | 1510system.membus.snoop_fanout::total 2861471 # Request fanout histogram |
| 1495system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) 1496system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1497system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1498system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1499system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) 1500system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1501system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) 1502system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) --- 48 unchanged lines hidden --- | 1511system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) 1512system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1513system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1514system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1515system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) 1516system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1517system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) 1518system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) --- 48 unchanged lines hidden --- |