1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.759374 # Number of seconds simulated 4sim_ticks 51759374264500 # Number of ticks simulated 5final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 729832 # Simulator instruction rate (inst/s) 8host_op_rate 857659 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45135767006 # Simulator tick rate (ticks/s) 10host_mem_usage 675484 # Number of bytes of host memory used 11host_seconds 1146.75 # Real time elapsed on the host |
12sim_insts 836933434 # Number of instructions simulated 13sim_ops 983519389 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory --- 588 unchanged lines hidden (view full) --- 608system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits 609system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits 610system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits 611system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits 612system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits 613system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits 614system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits 615system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits |
616system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits 617system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits 618system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits 619system.cpu.dcache.overall_hits::total 283908330 # number of overall hits |
620system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses 621system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses 622system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses 623system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses 624system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses 625system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses 626system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses 627system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses 628system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses 629system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses 630system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 631system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses |
632system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses 633system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses 634system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses 635system.cpu.dcache.overall_misses::total 9251082 # number of overall misses |
636system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles 637system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles 638system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles 639system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles 640system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles 641system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles 642system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles 643system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles 644system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 645system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles |
646system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles 647system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles 648system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles 649system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles |
650system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses) 651system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses) 652system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses) 653system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses) 654system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses) 655system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses) 656system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses) 657system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses) 658system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses) 659system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses) 660system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses) 661system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses) |
662system.cpu.dcache.demand_accesses::cpu.data 291648847 # number of demand (read+write) accesses 663system.cpu.dcache.demand_accesses::total 291648847 # number of demand (read+write) accesses 664system.cpu.dcache.overall_accesses::cpu.data 293159412 # number of overall (read+write) accesses 665system.cpu.dcache.overall_accesses::total 293159412 # number of overall (read+write) accesses |
666system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses 667system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses 668system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses 669system.cpu.dcache.WriteReq_miss_rate::total 0.014504 # miss rate for WriteReq accesses 670system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752335 # miss rate for SoftPFReq accesses 671system.cpu.dcache.SoftPFReq_miss_rate::total 0.752335 # miss rate for SoftPFReq accesses 672system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785976 # miss rate for WriteLineReq accesses 673system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses 674system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses 675system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses 676system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 677system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses |
678system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses 679system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses 680system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses 681system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses |
682system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency 683system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency 684system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency 685system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency 686system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency 687system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency 688system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency 689system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency 690system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 691system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency |
692system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency 693system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # average overall miss latency 694system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397 # average overall miss latency 695system.cpu.dcache.overall_avg_miss_latency::total 21933.298397 # average overall miss latency |
696system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 697system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 698system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 699system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 700system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 701system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
702system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks 703system.cpu.dcache.writebacks::total 7313678 # number of writebacks 704system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits 705system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits 706system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21254 # number of WriteReq MSHR hits 707system.cpu.dcache.WriteReq_mshr_hits::total 21254 # number of WriteReq MSHR hits 708system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68600 # number of LoadLockedReq MSHR hits 709system.cpu.dcache.LoadLockedReq_mshr_hits::total 68600 # number of LoadLockedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 718system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1134686 # number of SoftPFReq MSHR misses 719system.cpu.dcache.SoftPFReq_mshr_misses::total 1134686 # number of SoftPFReq MSHR misses 720system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221510 # number of WriteLineReq MSHR misses 721system.cpu.dcache.WriteLineReq_mshr_misses::total 1221510 # number of WriteLineReq MSHR misses 722system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778 # number of LoadLockedReq MSHR misses 723system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses 724system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 725system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses |
726system.cpu.dcache.demand_mshr_misses::cpu.data 8071396 # number of demand (read+write) MSHR misses 727system.cpu.dcache.demand_mshr_misses::total 8071396 # number of demand (read+write) MSHR misses 728system.cpu.dcache.overall_mshr_misses::cpu.data 9206082 # number of overall MSHR misses 729system.cpu.dcache.overall_mshr_misses::total 9206082 # number of overall MSHR misses |
730system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 731system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable 732system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 733system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 734system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 735system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses 736system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78281972500 # number of ReadReq MSHR miss cycles 737system.cpu.dcache.ReadReq_mshr_miss_latency::total 78281972500 # number of ReadReq MSHR miss cycles 738system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67251605000 # number of WriteReq MSHR miss cycles 739system.cpu.dcache.WriteReq_mshr_miss_latency::total 67251605000 # number of WriteReq MSHR miss cycles 740system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21441642000 # number of SoftPFReq MSHR miss cycles 741system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21441642000 # number of SoftPFReq MSHR miss cycles 742system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 47007248000 # number of WriteLineReq MSHR miss cycles 743system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles 744system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles 745system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles 746system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 747system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles |
748system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles 749system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles 750system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles 751system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles |
752system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles 753system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles |
754system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles 755system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles |
756system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses 757system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses 758system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses 759system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses 760system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses 761system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses 762system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses 763system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses 764system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses 765system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses 766system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 767system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses |
768system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses 769system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses 770system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses 771system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses |
772system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency 773system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency 774system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency 775system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency 776system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency 777system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency 778system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency 779system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency 780system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency 781system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency 782system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 783system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency |
784system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency 785system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency 786system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency 787system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency |
788system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency 789system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency |
790system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency 791system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency |
792system.cpu.icache.tags.replacements 13331164 # number of replacements 793system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use 794system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. 795system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks. 796system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks. 797system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. 798system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor 799system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 843system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency 844system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency 845system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 846system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 847system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 848system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 849system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 850system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
851system.cpu.icache.writebacks::writebacks 13331164 # number of writebacks 852system.cpu.icache.writebacks::total 13331164 # number of writebacks 853system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13331681 # number of ReadReq MSHR misses 854system.cpu.icache.ReadReq_mshr_misses::total 13331681 # number of ReadReq MSHR misses 855system.cpu.icache.demand_mshr_misses::cpu.inst 13331681 # number of demand (read+write) MSHR misses 856system.cpu.icache.demand_mshr_misses::total 13331681 # number of demand (read+write) MSHR misses 857system.cpu.icache.overall_mshr_misses::cpu.inst 13331681 # number of overall MSHR misses 858system.cpu.icache.overall_mshr_misses::total 13331681 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 881system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency 882system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency 883system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency 884system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency 885system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency 886system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency 887system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency 888system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency |
889system.cpu.l2cache.tags.replacements 1036266 # number of replacements 890system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use 891system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks. 892system.cpu.l2cache.tags.sampled_refs 1098550 # Sample count of references to valid blocks. 893system.cpu.l2cache.tags.avg_refs 37.921538 # Average number of references to valid blocks. 894system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit. 895system.cpu.l2cache.tags.occ_blocks::writebacks 38127.362532 # Average occupied blocks per requestor 896system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 231.236011 # Average occupied blocks per requestor --- 175 unchanged lines hidden (view full) --- 1072system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency 1073system.cpu.l2cache.overall_avg_miss_latency::total 132171.549560 # average overall miss latency 1074system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1075system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1076system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1077system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1078system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1079system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1080system.cpu.l2cache.writebacks::writebacks 879823 # number of writebacks 1081system.cpu.l2cache.writebacks::total 879823 # number of writebacks 1082system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2426 # number of ReadReq MSHR misses 1083system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2490 # number of ReadReq MSHR misses 1084system.cpu.l2cache.ReadReq_mshr_misses::total 4916 # number of ReadReq MSHR misses 1085system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33285 # number of UpgradeReq MSHR misses 1086system.cpu.l2cache.UpgradeReq_mshr_misses::total 33285 # number of UpgradeReq MSHR misses 1087system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses --- 47 unchanged lines hidden (view full) --- 1135system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 307805500 # number of overall MSHR miss cycles 1136system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 320988500 # number of overall MSHR miss cycles 1137system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8750287500 # number of overall MSHR miss cycles 1138system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69455519514 # number of overall MSHR miss cycles 1139system.cpu.l2cache.overall_mshr_miss_latency::total 78834601014 # number of overall MSHR miss cycles 1140system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles 1141system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777601500 # number of ReadReq MSHR uncacheable cycles 1142system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675326000 # number of ReadReq MSHR uncacheable cycles |
1143system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles |
1144system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777601500 # number of overall MSHR uncacheable cycles 1145system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675326000 # number of overall MSHR uncacheable cycles |
1146system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses 1147system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses 1148system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses 1149system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses 1150system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses 1151system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1152system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1153system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses --- 37 unchanged lines hidden (view full) --- 1191system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency 1192system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency 1193system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency 1194system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency 1195system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency 1196system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency 1197system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency 1198system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency |
1199system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency |
1200system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency 1201system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency |
1202system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter. 1203system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1204system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1205system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. 1206system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1207system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1208system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution 1209system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution --- 140 unchanged lines hidden (view full) --- 1350system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1351system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses 1352system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses 1353system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1354system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1355system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1356system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1357system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
1358system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses 1359system.iocache.demand_misses::total 115564 # number of demand (read+write) misses |
1360system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
1361system.iocache.overall_misses::realview.ide 115524 # number of overall misses 1362system.iocache.overall_misses::total 115564 # number of overall misses |
1363system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles 1364system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles 1365system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles 1366system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1367system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1368system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles 1369system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles 1370system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles |
1371system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles 1372system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles |
1373system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles |
1374system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles 1375system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles |
1376system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1377system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses) 1378system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses) 1379system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1380system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1381system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1382system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1383system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
1384system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses 1385system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses |
1386system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
1387system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses 1388system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses |
1389system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1390system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1391system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1392system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1393system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1394system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1395system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1396system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1402system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency 1403system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency 1404system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency 1405system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1406system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1407system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency 1408system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency 1409system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency |
1410system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency 1411system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency |
1412system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency |
1413system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency 1414system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency |
1415system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked 1416system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1417system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked 1418system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1419system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked 1420system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1421system.iocache.writebacks::writebacks 106631 # number of writebacks 1422system.iocache.writebacks::total 106631 # number of writebacks 1423system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1424system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses 1425system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses 1426system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1427system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1428system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1429system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1430system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
1431system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses 1432system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses |
1433system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
1434system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses 1435system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses |
1436system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles 1437system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles 1438system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles 1439system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1440system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1441system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles 1442system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles 1443system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles |
1444system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles 1445system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles |
1446system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles |
1447system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles 1448system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles |
1449system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1450system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1451system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1452system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1453system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1454system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1455system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1456system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1462system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency 1463system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency 1464system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency 1465system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1466system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1467system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency 1468system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency 1469system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency |
1470system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency 1471system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency |
1472system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency |
1473system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency 1474system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency |
1475system.membus.trans_dist::ReadReq 76827 # Transaction distribution 1476system.membus.trans_dist::ReadResp 389416 # Transaction distribution 1477system.membus.trans_dist::WriteReq 33708 # Transaction distribution 1478system.membus.trans_dist::WriteResp 33708 # Transaction distribution 1479system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution 1480system.membus.trans_dist::CleanEvict 164302 # Transaction distribution 1481system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution 1482system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution --- 99 unchanged lines hidden --- |