3,5c3,5
< sim_seconds 51.821872 # Number of seconds simulated
< sim_ticks 51821872017500 # Number of ticks simulated
< final_tick 51821872017500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.818011 # Number of seconds simulated
> sim_ticks 51818010617500 # Number of ticks simulated
> final_tick 51818010617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1130306 # Simulator instruction rate (inst/s)
< host_op_rate 1328204 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 68135685678 # Simulator tick rate (ticks/s)
< host_mem_usage 679252 # Number of bytes of host memory used
< host_seconds 760.57 # Real time elapsed on the host
< sim_insts 859675526 # Number of instructions simulated
< sim_ops 1010190283 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1170120 # Simulator instruction rate (inst/s)
> host_op_rate 1392764 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 73119251351 # Simulator tick rate (ticks/s)
> host_mem_usage 679172 # Number of bytes of host memory used
> host_seconds 708.68 # Real time elapsed on the host
> sim_insts 829238196 # Number of instructions simulated
> sim_ops 987021276 # Number of ops (including micro ops) simulated
16,25c16,25
< system.physmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.dtb.walker 215360 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 217216 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 5027508 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 42852104 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 396352 # Number of bytes read from this memory
< system.physmem.bytes_read::total 48708540 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 5027508 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 5027508 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 69916032 # Number of bytes written to this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.dtb.walker 290880 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 276800 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 5155828 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 53423624 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 392768 # Number of bytes read from this memory
> system.physmem.bytes_read::total 59539900 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 5155828 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 5155828 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 81086784 # Number of bytes written to this memory
27,34c27,34
< system.physmem.bytes_written::total 69936612 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 3365 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 3394 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 118962 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 669577 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6193 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 801491 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1092438 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 81107364 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 4545 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 4325 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 84967 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 834757 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6137 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 934731 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1266981 # Number of write requests responded to by this memory
36,45c36,45
< system.physmem.num_writes::total 1095011 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 4156 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 4192 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 97015 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 826912 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 7648 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 939922 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 97015 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 97015 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1349161 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1269554 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 5613 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 5342 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 99499 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1030986 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 7580 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1149019 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 99499 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 99499 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1564838 # Write bandwidth from this memory (bytes/s)
47,65c47,65
< system.physmem.bw_write::total 1349558 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1349161 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 4156 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 4192 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 97015 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 827309 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 7648 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2289480 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 801491 # Number of read requests accepted
< system.physmem.writeReqs 1095011 # Number of write requests accepted
< system.physmem.readBursts 801491 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1095011 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 51258176 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 37248 # Total number of bytes read from write queue
< system.physmem.bytesWritten 69934720 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 48708540 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 69936612 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 582 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 1565235 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1564838 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 5613 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 5342 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 99499 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1031383 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 7580 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2714254 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 934731 # Number of read requests accepted
> system.physmem.writeReqs 1269554 # Number of write requests accepted
> system.physmem.readBursts 934731 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1269554 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 59774080 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 48704 # Total number of bytes read from write queue
> system.physmem.bytesWritten 81104832 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 59539900 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 81107364 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 761 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one
67,98c67,98
< system.physmem.perBankRdBursts::0 50792 # Per bank write bursts
< system.physmem.perBankRdBursts::1 52585 # Per bank write bursts
< system.physmem.perBankRdBursts::2 45494 # Per bank write bursts
< system.physmem.perBankRdBursts::3 47583 # Per bank write bursts
< system.physmem.perBankRdBursts::4 47505 # Per bank write bursts
< system.physmem.perBankRdBursts::5 55338 # Per bank write bursts
< system.physmem.perBankRdBursts::6 45272 # Per bank write bursts
< system.physmem.perBankRdBursts::7 44194 # Per bank write bursts
< system.physmem.perBankRdBursts::8 47329 # Per bank write bursts
< system.physmem.perBankRdBursts::9 89850 # Per bank write bursts
< system.physmem.perBankRdBursts::10 47381 # Per bank write bursts
< system.physmem.perBankRdBursts::11 49509 # Per bank write bursts
< system.physmem.perBankRdBursts::12 42888 # Per bank write bursts
< system.physmem.perBankRdBursts::13 45239 # Per bank write bursts
< system.physmem.perBankRdBursts::14 44185 # Per bank write bursts
< system.physmem.perBankRdBursts::15 45765 # Per bank write bursts
< system.physmem.perBankWrBursts::0 68303 # Per bank write bursts
< system.physmem.perBankWrBursts::1 72266 # Per bank write bursts
< system.physmem.perBankWrBursts::2 69005 # Per bank write bursts
< system.physmem.perBankWrBursts::3 70230 # Per bank write bursts
< system.physmem.perBankWrBursts::4 67390 # Per bank write bursts
< system.physmem.perBankWrBursts::5 74059 # Per bank write bursts
< system.physmem.perBankWrBursts::6 66126 # Per bank write bursts
< system.physmem.perBankWrBursts::7 65521 # Per bank write bursts
< system.physmem.perBankWrBursts::8 69259 # Per bank write bursts
< system.physmem.perBankWrBursts::9 70740 # Per bank write bursts
< system.physmem.perBankWrBursts::10 68902 # Per bank write bursts
< system.physmem.perBankWrBursts::11 68447 # Per bank write bursts
< system.physmem.perBankWrBursts::12 64485 # Per bank write bursts
< system.physmem.perBankWrBursts::13 66687 # Per bank write bursts
< system.physmem.perBankWrBursts::14 65337 # Per bank write bursts
< system.physmem.perBankWrBursts::15 65973 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 59992 # Per bank write bursts
> system.physmem.perBankRdBursts::1 60310 # Per bank write bursts
> system.physmem.perBankRdBursts::2 57698 # Per bank write bursts
> system.physmem.perBankRdBursts::3 58037 # Per bank write bursts
> system.physmem.perBankRdBursts::4 57948 # Per bank write bursts
> system.physmem.perBankRdBursts::5 67620 # Per bank write bursts
> system.physmem.perBankRdBursts::6 56261 # Per bank write bursts
> system.physmem.perBankRdBursts::7 53370 # Per bank write bursts
> system.physmem.perBankRdBursts::8 54837 # Per bank write bursts
> system.physmem.perBankRdBursts::9 66514 # Per bank write bursts
> system.physmem.perBankRdBursts::10 61956 # Per bank write bursts
> system.physmem.perBankRdBursts::11 59662 # Per bank write bursts
> system.physmem.perBankRdBursts::12 55006 # Per bank write bursts
> system.physmem.perBankRdBursts::13 54479 # Per bank write bursts
> system.physmem.perBankRdBursts::14 55622 # Per bank write bursts
> system.physmem.perBankRdBursts::15 54658 # Per bank write bursts
> system.physmem.perBankWrBursts::0 77492 # Per bank write bursts
> system.physmem.perBankWrBursts::1 79625 # Per bank write bursts
> system.physmem.perBankWrBursts::2 80003 # Per bank write bursts
> system.physmem.perBankWrBursts::3 79967 # Per bank write bursts
> system.physmem.perBankWrBursts::4 79681 # Per bank write bursts
> system.physmem.perBankWrBursts::5 86821 # Per bank write bursts
> system.physmem.perBankWrBursts::6 77332 # Per bank write bursts
> system.physmem.perBankWrBursts::7 76109 # Per bank write bursts
> system.physmem.perBankWrBursts::8 76222 # Per bank write bursts
> system.physmem.perBankWrBursts::9 83393 # Per bank write bursts
> system.physmem.perBankWrBursts::10 81152 # Per bank write bursts
> system.physmem.perBankWrBursts::11 79739 # Per bank write bursts
> system.physmem.perBankWrBursts::12 76657 # Per bank write bursts
> system.physmem.perBankWrBursts::13 78391 # Per bank write bursts
> system.physmem.perBankWrBursts::14 77174 # Per bank write bursts
> system.physmem.perBankWrBursts::15 77505 # Per bank write bursts
100,101c100,101
< system.physmem.numWrRetry 520 # Number of times write queue was full causing retry
< system.physmem.totGap 51821869155500 # Total gap between requests
---
> system.physmem.numWrRetry 469 # Number of times write queue was full causing retry
> system.physmem.totGap 51818007690500 # Total gap between requests
104c104
< system.physmem.readPktSize::2 43101 # Read request sizes (log2)
---
> system.physmem.readPktSize::2 4701 # Read request sizes (log2)
108c108
< system.physmem.readPktSize::6 758375 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 930015 # Read request sizes (log2)
115,136c115,136
< system.physmem.writePktSize::6 1092438 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 767476 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 27687 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 318 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 458 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 422 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 585 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 474 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 927 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 560 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 285 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 188 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 99 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1266981 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 899250 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 28995 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 324 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 456 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 433 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 464 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 936 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 574 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 276 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 255 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 182 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 140 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 80 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
163,186c163,186
< system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 57744 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 61921 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 65097 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 62233 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 60629 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 62549 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 64813 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 63194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 67249 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 66047 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 62409 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 60534 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 61342 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 60374 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 59104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 58755 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 2399 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1915 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1349 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 1180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1074 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 32926 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 37724 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 68102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 72474 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 75844 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 72834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 71244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 73203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 75560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 73943 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 77939 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 76725 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 72934 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 71213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 72289 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 71241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 69956 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 69529 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 2492 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1882 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1648 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1372 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1160 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1159 # What write queue length does an incoming req see
188,273c188,276
< system.physmem.wrQLenPdf::40 852 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 821 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 854 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 798 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 796 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 786 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 758 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 811 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 936 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1000 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 837 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 851 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 761 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 822 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 850 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 1161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 1037 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 797 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 1136 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 1468 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 1603 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 687 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 1058 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 494423 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 245.119212 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 147.459226 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 287.994040 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 219027 44.30% 44.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 131709 26.64% 70.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 43564 8.81% 79.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 22937 4.64% 84.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 15466 3.13% 87.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 9602 1.94% 89.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 7396 1.50% 90.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5862 1.19% 92.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 38860 7.86% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 494423 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 57152 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 14.013543 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 134.391751 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 57148 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 57152 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 57152 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.119716 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.362666 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 8.513001 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 44632 78.09% 78.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 9484 16.59% 94.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 590 1.03% 95.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 287 0.50% 96.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 876 1.53% 97.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 130 0.23% 97.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 106 0.19% 98.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 28 0.05% 98.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 52 0.09% 98.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 20 0.03% 98.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 16 0.03% 98.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 48 0.08% 98.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 542 0.95% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 77 0.13% 99.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 52 0.09% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 79 0.14% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 35 0.06% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 2 0.00% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 3 0.01% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 1 0.00% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.00% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 16 0.03% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 9 0.02% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 18 0.03% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 7 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads
---
> system.physmem.wrQLenPdf::40 900 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 849 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 867 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 799 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 917 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 690 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 711 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 685 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 719 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1012 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 811 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 743 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 1158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 949 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 670 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 1096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 1457 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 1424 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 599 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1035 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 576881 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 244.207370 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 147.656879 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 284.643014 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 255111 44.22% 44.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 152646 26.46% 70.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 51224 8.88% 79.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 27873 4.83% 84.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 18823 3.26% 87.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 12144 2.11% 89.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 9162 1.59% 91.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 7710 1.34% 92.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 42188 7.31% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 576881 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 67805 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 13.773807 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 23.890121 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-255 67793 99.98% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::256-511 5 0.01% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-767 3 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 67805 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 67805 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 18.689816 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.049494 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 7.758455 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 55088 81.24% 81.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 9632 14.21% 95.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 629 0.93% 96.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 315 0.46% 96.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 880 1.30% 98.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 141 0.21% 98.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 113 0.17% 98.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 35 0.05% 98.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 64 0.09% 98.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 15 0.02% 98.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 17 0.03% 98.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 38 0.06% 98.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 506 0.75% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 74 0.11% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 50 0.07% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 77 0.11% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 34 0.05% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 3 0.00% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.00% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 7 0.01% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.00% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.00% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 13 0.02% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 3 0.00% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.00% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 4 0.01% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 19 0.03% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 9 0.01% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 2 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 6 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 3 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 3 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads
276,277c279,280
< system.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 6 0.01% 99.99% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::188-191 4 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 3 0.00% 99.99% # Writes before turning the bus around for reads
279,284c282,288
< system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 57152 # Writes before turning the bus around for reads
< system.physmem.totQLat 29342800943 # Total ticks spent queuing
< system.physmem.totMemAccLat 44359844693 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 4004545000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 36636.87 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 67805 # Writes before turning the bus around for reads
> system.physmem.totQLat 32840058772 # Total ticks spent queuing
> system.physmem.totMemAccLat 50351996272 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 4669850000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 35161.79 # Average queueing delay per DRAM burst
286,290c290,294
< system.physmem.avgMemAccLat 55386.87 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 53911.79 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.15 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.15 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
296,341c300,345
< system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing
< system.physmem.readRowHits 600164 # Number of row buffer hits during reads
< system.physmem.writeRowHits 799051 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 74.94 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes
< system.physmem.avgGap 27324974.69 # Average gap between requests
< system.physmem.pageHitRate 73.89 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 1814238300 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 964290525 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2775767820 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 2886138000 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 48823313760.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 38608999590 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 3011693280 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 94024683450 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 72592857120 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 12330153384360 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 12595677850665 # Total energy per rank (pJ)
< system.physmem_0.averagePower 243.057176 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 51728729641480 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 5702683750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 20763204000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 51334071775500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 189043780464 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 66096536270 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 206194037516 # Time in different power states
< system.physmem_1.actEnergy 1715949060 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 912044760 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 2942722440 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 2817912600 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 46334636400.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 38117726280 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2754271680 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 87558235230 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 69416939040 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 12335402832360 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 12587993852010 # Total energy per rank (pJ)
< system.physmem_1.averagePower 242.908898 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 51731061753764 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 5083631742 # Time in different power states
< system.physmem_1.memoryStateTime::REF 19704542000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 51358275119250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 180773350699 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 66022048244 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 192013325565 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
> system.physmem.readRowHits 700734 # Number of row buffer hits during reads
> system.physmem.writeRowHits 923617 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 75.03 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 72.88 # Row buffer hit rate for writes
> system.physmem.avgGap 23507852.97 # Average gap between requests
> system.physmem.pageHitRate 73.79 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 2121758100 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1127741175 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 3364625040 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3325296600 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 53356283760.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 43527513060 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 3305473920 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 105977484840 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 78284868000 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 12316974110865 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 12611384893410 # Total energy per rank (pJ)
> system.physmem_0.averagePower 243.378407 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 51713320513020 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 6156853750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 22684760000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 51277629948750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 203866794298 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 75265891230 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 232406369472 # Time in different power states
> system.physmem_1.actEnergy 1997179380 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1061522220 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 3303920760 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3289816260 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 51035403120.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 42719469090 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3040212960 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 99255699990 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 75177553440 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 12322732679115 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 12603635909925 # Total energy per rank (pJ)
> system.physmem_1.averagePower 243.228865 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 51716360660558 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 5564281492 # Time in different power states
> system.physmem_1.memoryStateTime::REF 21699622000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 51302919507000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 195774926499 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 74386011700 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 217666268809 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
358,360c362,364
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
368c372
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
398,402c402,406
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 196189 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 196189 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13637 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152377 # Level at which table walker walks with long descriptors terminate
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 216211 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 216211 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16346 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 167307 # Level at which table walker walks with long descriptors terminate
404,407c408,411
< system.cpu.dtb.walker.walkWaitTime::samples 196170 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 0.152929 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 48.843369 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-2047 196168 100.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.walkWaitTime::samples 216192 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 0.138766 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 46.526694 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-2047 216190 100.00% 100.00% # Table walker wait (enqueue to first request) latency
410,425c414,429
< system.cpu.dtb.walker.walkWaitTime::total 196170 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 166033 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 23680.132865 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 19678.566540 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 19257.699461 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 164361 98.99% 98.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 1402 0.84% 99.84% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 64 0.04% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 64 0.04% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 59 0.04% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 17 0.01% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::589824-655359 48 0.03% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkWaitTime::total 216192 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 183672 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 24269.346988 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 20148.872722 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 20272.280127 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 181570 98.86% 98.86% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 1738 0.95% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 90 0.05% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 74 0.04% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 86 0.05% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 33 0.02% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 8 0.00% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::589824-655359 59 0.03% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
428,438c432,442
< system.cpu.dtb.walker.walkCompletionTime::total 166033 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples -7075428332 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.933158 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.249747 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0 -472932796 6.68% 6.68% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::1 -6602495536 93.32% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total -7075428332 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 152378 91.79% 91.79% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 13637 8.21% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 166015 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 196189 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkCompletionTime::total 183672 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 2036554556 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.701695 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.457514 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0 607514500 29.83% 29.83% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::1 1429040056 70.17% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 2036554556 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 167308 91.10% 91.10% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 16346 8.90% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 183654 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 216211 # Table walker requests started/completed, data/inst
440,441c444,445
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 196189 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 166015 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 216211 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183654 # Table walker requests started/completed, data/inst
443,444c447,448
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 166015 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 362204 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183654 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 399865 # Table walker requests started/completed, data/inst
447,450c451,454
< system.cpu.dtb.read_hits 161617169 # DTB read hits
< system.cpu.dtb.read_misses 145721 # DTB read misses
< system.cpu.dtb.write_hits 146821389 # DTB write hits
< system.cpu.dtb.write_misses 50468 # DTB write misses
---
> system.cpu.dtb.read_hits 169128390 # DTB read hits
> system.cpu.dtb.read_misses 159496 # DTB read misses
> system.cpu.dtb.write_hits 153929844 # DTB write hits
> system.cpu.dtb.write_misses 56715 # DTB write misses
453,455c457,459
< system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID
< system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID
< system.cpu.dtb.flush_entries 72934 # Number of entries that have been flushed from TLB
---
> system.cpu.dtb.flush_tlb_mva_asid 43399 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dtb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID
> system.cpu.dtb.flush_entries 75955 # Number of entries that have been flushed from TLB
457c461
< system.cpu.dtb.prefetch_faults 7326 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 8791 # Number of TLB faults due to prefetch
459,461c463,465
< system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 161762890 # DTB read accesses
< system.cpu.dtb.write_accesses 146871857 # DTB write accesses
---
> system.cpu.dtb.perms_faults 20041 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 169287886 # DTB read accesses
> system.cpu.dtb.write_accesses 153986559 # DTB write accesses
463,466c467,470
< system.cpu.dtb.hits 308438558 # DTB hits
< system.cpu.dtb.misses 196189 # DTB misses
< system.cpu.dtb.accesses 308634747 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 323058234 # DTB hits
> system.cpu.dtb.misses 216211 # DTB misses
> system.cpu.dtb.accesses 323274445 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
496,517c500,520
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.walks 120716 # Table walker walks requested
< system.cpu.itb.walker.walksLong 120716 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 108836 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 120716 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 120716 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 120716 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 109955 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 27513.978446 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 23291.832317 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 24606.943327 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-65535 107988 98.21% 98.21% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-131071 1629 1.48% 99.69% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-196607 80 0.07% 99.77% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-262143 85 0.08% 99.84% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-327679 60 0.05% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::589824-655359 77 0.07% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.walks 123370 # Table walker walks requested
> system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1116 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 111000 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 112116 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 27477.773021 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 23151.580183 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 24996.246984 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 109776 97.91% 97.91% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 1925 1.72% 99.63% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 106 0.09% 99.72% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 116 0.10% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 77 0.07% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 36 0.03% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::589824-655359 73 0.07% 100.00% # Table walker service (enqueue to completion) latency
519,526c522,528
< system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 109955 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 108836 98.98% 98.98% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 109955 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkCompletionTime::total 112116 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 523074000 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 523074000 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 523074000 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 111000 99.00% 99.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1116 1.00% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 112116 # Table walker page sizes translated
528,529c530,531
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120716 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 120716 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst
531,535c533,537
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109955 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 109955 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 230671 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 860205714 # ITB inst hits
< system.cpu.itb.inst_misses 120716 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112116 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 112116 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 235486 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 829831290 # ITB inst hits
> system.cpu.itb.inst_misses 123370 # ITB inst misses
542,544c544,546
< system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID
< system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID
< system.cpu.itb.flush_entries 52133 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_tlb_mva_asid 43399 # Number of times TLB was flushed by MVA & ASID
> system.cpu.itb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID
> system.cpu.itb.flush_entries 54054 # Number of entries that have been flushed from TLB
551,563c553,565
< system.cpu.itb.inst_accesses 860326430 # ITB inst accesses
< system.cpu.itb.hits 860205714 # DTB hits
< system.cpu.itb.misses 120716 # DTB misses
< system.cpu.itb.accesses 860326430 # DTB accesses
< system.cpu.numPwrStateTransitions 32324 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 16162 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 3111484469.414615 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 60405660268.224297 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::underflows 6871 42.51% 42.51% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
---
> system.cpu.itb.inst_accesses 829954660 # ITB inst accesses
> system.cpu.itb.hits 829831290 # DTB hits
> system.cpu.itb.misses 123370 # DTB misses
> system.cpu.itb.accesses 829954660 # DTB accesses
> system.cpu.numPwrStateTransitions 32736 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 16368 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 3071765118.618646 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 59759289847.266548 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::underflows 7078 43.24% 43.24% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 9254 56.54% 99.78% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::5e+10-1e+11 6 0.04% 99.82% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state
565,567c567,569
< system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
572,576c574,578
< system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::total 16162 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 1534060022821 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 50287811994679 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 103643744035 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::max_value 1988775098960 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::total 16368 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 1539359155950 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 50278651461550 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 103636021235 # number of cpu cycles simulated
580,602c582,604
< system.cpu.kern.inst.quiesce 16162 # number of quiesce instructions executed
< system.cpu.committedInsts 859675526 # Number of instructions committed
< system.cpu.committedOps 1010190283 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 928076114 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 896946 # Number of float alu accesses
< system.cpu.num_func_calls 51280324 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 130830869 # number of instructions that are conditional controls
< system.cpu.num_int_insts 928076114 # number of integer instructions
< system.cpu.num_fp_insts 896946 # number of float instructions
< system.cpu.num_int_register_reads 1348653813 # number of times the integer registers were read
< system.cpu.num_int_register_writes 735932841 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 1446833 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 759084 # number of times the floating registers were written
< system.cpu.num_cc_register_reads 224374440 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 223774216 # number of times the CC registers were written
< system.cpu.num_mem_refs 308419372 # number of memory refs
< system.cpu.num_load_insts 161608555 # Number of load instructions
< system.cpu.num_store_insts 146810817 # Number of store instructions
< system.cpu.num_idle_cycles 100575623989.356064 # Number of idle cycles
< system.cpu.num_busy_cycles 3068120045.643941 # Number of busy cycles
< system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.970397 # Percentage of idle cycles
< system.cpu.Branches 191908708 # Number of branches fetched
---
> system.cpu.kern.inst.quiesce 16368 # number of quiesce instructions executed
> system.cpu.committedInsts 829238196 # Number of instructions committed
> system.cpu.committedOps 987021276 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 918155469 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 894809 # Number of float alu accesses
> system.cpu.num_func_calls 53301366 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 119804511 # number of instructions that are conditional controls
> system.cpu.num_int_insts 918155469 # number of integer instructions
> system.cpu.num_fp_insts 894809 # number of float instructions
> system.cpu.num_int_register_reads 1221916718 # number of times the integer registers were read
> system.cpu.num_int_register_writes 717363924 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 1441242 # number of times the floating registers were read
> system.cpu.num_fp_register_writes 760964 # number of times the floating registers were written
> system.cpu.num_cc_register_reads 183477837 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 182884399 # number of times the CC registers were written
> system.cpu.num_mem_refs 323042928 # number of memory refs
> system.cpu.num_load_insts 169122320 # Number of load instructions
> system.cpu.num_store_insts 153920608 # Number of store instructions
> system.cpu.num_idle_cycles 100557302923.098053 # Number of idle cycles
> system.cpu.num_busy_cycles 3078718311.901940 # Number of busy cycles
> system.cpu.not_idle_fraction 0.029707 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.970293 # Percentage of idle cycles
> system.cpu.Branches 183328759 # Number of branches fetched
604,638c606,640
< system.cpu.op_class::IntAlu 699966855 69.25% 69.25% # Class of executed instruction
< system.cpu.op_class::IntMult 2168337 0.21% 69.47% # Class of executed instruction
< system.cpu.op_class::IntDiv 97451 0.01% 69.48% # Class of executed instruction
< system.cpu.op_class::FloatAdd 8 0.00% 69.48% # Class of executed instruction
< system.cpu.op_class::FloatCmp 13 0.00% 69.48% # Class of executed instruction
< system.cpu.op_class::FloatCvt 21 0.00% 69.48% # Class of executed instruction
< system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
< system.cpu.op_class::FloatMultAcc 0 0.00% 69.48% # Class of executed instruction
< system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
< system.cpu.op_class::FloatMisc 111537 0.01% 69.49% # Class of executed instruction
< system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatMisc 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction
< system.cpu.op_class::MemRead 161496118 15.98% 85.46% # Class of executed instruction
< system.cpu.op_class::MemWrite 146137887 14.46% 99.92% # Class of executed instruction
< system.cpu.op_class::FloatMemRead 112437 0.01% 99.93% # Class of executed instruction
< system.cpu.op_class::FloatMemWrite 672930 0.07% 100.00% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 662135321 67.04% 67.04% # Class of executed instruction
> system.cpu.op_class::IntMult 2232133 0.23% 67.27% # Class of executed instruction
> system.cpu.op_class::IntDiv 98376 0.01% 67.28% # Class of executed instruction
> system.cpu.op_class::FloatAdd 8 0.00% 67.28% # Class of executed instruction
> system.cpu.op_class::FloatCmp 13 0.00% 67.28% # Class of executed instruction
> system.cpu.op_class::FloatCvt 21 0.00% 67.28% # Class of executed instruction
> system.cpu.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction
> system.cpu.op_class::FloatMultAcc 0 0.00% 67.28% # Class of executed instruction
> system.cpu.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction
> system.cpu.op_class::FloatMisc 110293 0.01% 67.29% # Class of executed instruction
> system.cpu.op_class::FloatSqrt 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdAdd 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdAddAcc 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdAlu 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdCmp 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdCvt 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdMisc 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdMult 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdMultAcc 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdShift 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdShiftAcc 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdSqrt 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatAdd 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatAlu 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatCmp 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatCvt 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatDiv 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatMisc 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction
> system.cpu.op_class::MemRead 169008582 17.11% 84.40% # Class of executed instruction
> system.cpu.op_class::MemWrite 153249872 15.52% 99.92% # Class of executed instruction
> system.cpu.op_class::FloatMemRead 113738 0.01% 99.93% # Class of executed instruction
> system.cpu.op_class::FloatMemWrite 670736 0.07% 100.00% # Class of executed instruction
641,651c643,653
< system.cpu.op_class::total 1010763595 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 9712819 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 298526964 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 9713331 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 30.733737 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy
---
> system.cpu.op_class::total 987619094 # Class of executed instruction
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 10318810 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.994503 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 312537175 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 10319322 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 30.286600 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 585910500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.994503 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
653,656c655,658
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
658,752c660,754
< system.cpu.dcache.tags.tag_accesses 1243130616 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1243130616 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 151166129 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 151166129 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 139372457 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 139372457 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 383388 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 383388 # number of SoftPFReq hits
< system.cpu.dcache.WriteLineReq_hits::cpu.data 333792 # number of WriteLineReq hits
< system.cpu.dcache.WriteLineReq_hits::total 333792 # number of WriteLineReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475542 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 3475542 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 3766859 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 3766859 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 290872378 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 290872378 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 291255766 # number of overall hits
< system.cpu.dcache.overall_hits::total 291255766 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 5061632 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 5061632 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2072136 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2072136 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 1203806 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 1203806 # number of SoftPFReq misses
< system.cpu.dcache.WriteLineReq_misses::cpu.data 1225587 # number of WriteLineReq misses
< system.cpu.dcache.WriteLineReq_misses::total 1225587 # number of WriteLineReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 292986 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 292986 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 8359355 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 8359355 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9563161 # number of overall misses
< system.cpu.dcache.overall_misses::total 9563161 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 86410296000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 86410296000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 64078644000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 64078644000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24971401500 # number of WriteLineReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::total 24971401500 # number of WriteLineReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4471115500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 4471115500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 167500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 175460341500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 175460341500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 175460341500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 175460341500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 156227761 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 156227761 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 141444593 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 141444593 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587194 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 1587194 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559379 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::total 1559379 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768528 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 3768528 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766861 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 3766861 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 299231733 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 299231733 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 300818927 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 300818927 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032399 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.032399 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014650 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.014650 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758449 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.758449 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785946 # miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::total 0.785946 # miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077745 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077745 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.027936 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.027936 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.031790 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.031790 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17071.627491 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17071.627491 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30923.956729 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 30923.956729 # average WriteReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20375.054158 # average WriteLineReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20375.054158 # average WriteLineReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15260.509035 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15260.509035 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 20989.698547 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 20989.698547 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 18347.525625 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 18347.525625 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 1302212841 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1302212841 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 157972571 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 157972571 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 146050984 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 146050984 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 397864 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 397864 # number of SoftPFReq hits
> system.cpu.dcache.WriteLineReq_hits::cpu.data 335205 # number of WriteLineReq hits
> system.cpu.dcache.WriteLineReq_hits::total 335205 # number of WriteLineReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 3722931 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 3722931 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 4027066 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 4027066 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 304358760 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 304358760 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 304756624 # number of overall hits
> system.cpu.dcache.overall_hits::total 304756624 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 5371907 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 5371907 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2231014 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2231014 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 1323692 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 1323692 # number of SoftPFReq misses
> system.cpu.dcache.WriteLineReq_misses::cpu.data 1234314 # number of WriteLineReq misses
> system.cpu.dcache.WriteLineReq_misses::total 1234314 # number of WriteLineReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 305825 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 305825 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 8837235 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 8837235 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 10160927 # number of overall misses
> system.cpu.dcache.overall_misses::total 10160927 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 92847463000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 92847463000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 76601172000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 76601172000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 25428557000 # number of WriteLineReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::total 25428557000 # number of WriteLineReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4806019500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 4806019500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 194877192000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 194877192000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 194877192000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 194877192000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 163344478 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 163344478 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 148281998 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 148281998 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 1721556 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 1721556 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::cpu.data 1569519 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::total 1569519 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4028756 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 4028756 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 4027067 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 4027067 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 313195995 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 313195995 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 314917551 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 314917551 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032887 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.032887 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015046 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015046 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.768893 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.768893 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786428 # miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::total 0.786428 # miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.075911 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.075911 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.028216 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.028216 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.032265 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.032265 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17283.892480 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17283.892480 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.689070 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.689070 # average WriteReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20601.368047 # average WriteLineReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20601.368047 # average WriteLineReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15714.933377 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15714.933377 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 22051.828655 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 22051.828655 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 19179.076082 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 19179.076082 # average overall miss latency
759,858c761,860
< system.cpu.dcache.writebacks::writebacks 7496626 # number of writebacks
< system.cpu.dcache.writebacks::total 7496626 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21661 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 21661 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21294 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 21294 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70691 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 70691 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 42955 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 42955 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 42955 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 42955 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5039971 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5039971 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2050842 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2050842 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203452 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 1203452 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1225587 # number of WriteLineReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::total 1225587 # number of WriteLineReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222295 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 222295 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 8316400 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 8316400 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9519852 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9519852 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80495651000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 80495651000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61277537000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 61277537000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21572116000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21572116000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23745814500 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23745814500 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3066936500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3066936500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165519002500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 165519002500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187091118500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 187091118500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032260 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032260 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014499 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014499 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758226 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758226 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785946 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785946 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058987 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058987 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027793 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031646 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.031646 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15971.451225 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15971.451225 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29879.209125 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29879.209125 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17925.198512 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17925.198512 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19375.054158 # average WriteLineReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19375.054158 # average WriteLineReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13796.695832 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13796.695832 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.722632 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.722632 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.733940 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.733940 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.367650 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.367650 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.697935 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.697935 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 13486266 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 846718931 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 13486778 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 62.781409 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 32464203500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy
---
> system.cpu.dcache.writebacks::writebacks 7954497 # number of writebacks
> system.cpu.dcache.writebacks::total 7954497 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22835 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 22835 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21214 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 21214 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 72449 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 72449 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 44049 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 44049 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 44049 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 44049 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5349072 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5349072 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2209800 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2209800 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1323336 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 1323336 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1234314 # number of WriteLineReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::total 1234314 # number of WriteLineReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233376 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 233376 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 8793186 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 8793186 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 10116522 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 10116522 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33620 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 33620 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33624 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 33624 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67244 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 67244 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86573126000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 86573126000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73656101500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 73656101500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23406113500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23406113500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 24194243000 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 24194243000 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3299673500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3299673500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 184423470500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 184423470500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207829584000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 207829584000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6212445000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6212445000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6212445000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6212445000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032747 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032747 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014903 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014903 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.768686 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.768686 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786428 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786428 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057928 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057928 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028076 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.028076 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16184.700075 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16184.700075 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33331.569147 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33331.569147 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17687.203779 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17687.203779 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19601.368047 # average WriteLineReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19601.368047 # average WriteLineReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14138.872463 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14138.872463 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20973.452683 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20973.452683 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20543.580491 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20543.580491 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184784.205830 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184784.205830 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92386.606984 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92386.606984 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 13796932 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.918468 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 816033841 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 13797444 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 59.143841 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 29242894500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.918468 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999841 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999841 # Average percentage of cache occupancy
860,863c862,865
< system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
865,903c867,905
< system.cpu.icache.tags.tag_accesses 873692497 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 873692497 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 846718931 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 846718931 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 846718931 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 846718931 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 846718931 # number of overall hits
< system.cpu.icache.overall_hits::total 846718931 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 13486783 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 13486783 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 13486783 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 13486783 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 13486783 # number of overall misses
< system.cpu.icache.overall_misses::total 13486783 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 183511474500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 183511474500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 183511474500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 183511474500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 183511474500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 183511474500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 860205714 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 860205714 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 860205714 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 860205714 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 860205714 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 860205714 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015679 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.015679 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.015679 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.015679 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.015679 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.015679 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.764082 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13606.764082 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13606.764082 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13606.764082 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 843628739 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 843628739 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 816033841 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 816033841 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 816033841 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 816033841 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 816033841 # number of overall hits
> system.cpu.icache.overall_hits::total 816033841 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 13797449 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 13797449 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 13797449 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 13797449 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 13797449 # number of overall misses
> system.cpu.icache.overall_misses::total 13797449 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 188051577000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 188051577000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 188051577000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 188051577000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 188051577000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 188051577000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 829831290 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 829831290 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 829831290 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 829831290 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 829831290 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 829831290 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016627 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016627 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016627 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016627 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016627 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016627 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13629.445342 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13629.445342 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13629.445342 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13629.445342 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13629.445342 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13629.445342 # average overall miss latency
910,1087c912,1089
< system.cpu.icache.writebacks::writebacks 13486266 # number of writebacks
< system.cpu.icache.writebacks::total 13486266 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13486783 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 13486783 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 13486783 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 13486783 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 13486783 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 13486783 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
< system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
< system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
< system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170024691500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 170024691500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170024691500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 170024691500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170024691500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 170024691500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3557271000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3557271000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3557271000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 3557271000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015679 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.015679 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.015679 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12606.764082 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12606.764082 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average ReadReq mshr uncacheable latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478 # average ReadReq mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 1158711 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65407.211772 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 44429708 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1220523 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 36.402188 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 10958.963563 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 463.658135 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 540.023475 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 6661.801500 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 46782.765099 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.167221 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007075 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008240 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101651 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.713848 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.998035 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 61511 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 301 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 815 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54668 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.938583 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 377726834 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 377726834 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 307081 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 228330 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 535411 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 7496626 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 7496626 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 13484674 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 13484674 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 24887 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 24887 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1607168 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1607168 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13410909 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 13410909 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6209836 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 6209836 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 727975 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 727975 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 307081 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 228330 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 13410909 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 7817004 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 21763324 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 307081 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 228330 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 13410909 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 7817004 # number of overall hits
< system.cpu.l2cache.overall_hits::total 21763324 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3365 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3394 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 6759 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 3908 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 3908 # number of UpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 414879 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 414879 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 75874 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 75874 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 255882 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 255882 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 497612 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 497612 # number of InvalidateReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 3365 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 3394 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 75874 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 670761 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 753394 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 3365 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 3394 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 75874 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 670761 # number of overall misses
< system.cpu.l2cache.overall_misses::total 753394 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 447362000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 421528500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 868890500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69021500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 69021500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40901099500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 40901099500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8709565500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 8709565500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30155420000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 30155420000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 447362000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 421528500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 8709565500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 71056519500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 80634975500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 447362000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 421528500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 8709565500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 71056519500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 80634975500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 310446 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 231724 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 542170 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 7496626 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 7496626 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 13484674 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 13484674 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28795 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 28795 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2022047 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2022047 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13486783 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 13486783 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6465718 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 6465718 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1225587 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::total 1225587 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 310446 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 231724 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 13486783 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 8487765 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 22516718 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 310446 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 231724 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 13486783 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 8487765 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 22516718 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010839 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.014647 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.012467 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.135718 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.135718 # miss rate for UpgradeReq accesses
---
> system.cpu.icache.writebacks::writebacks 13796932 # number of writebacks
> system.cpu.icache.writebacks::total 13796932 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13797449 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 13797449 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 13797449 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 13797449 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 13797449 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 13797449 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 4725 # number of ReadReq MSHR uncacheable
> system.cpu.icache.ReadReq_mshr_uncacheable::total 4725 # number of ReadReq MSHR uncacheable
> system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 4725 # number of overall MSHR uncacheable misses
> system.cpu.icache.overall_mshr_uncacheable_misses::total 4725 # number of overall MSHR uncacheable misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174254128000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 174254128000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174254128000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 174254128000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174254128000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 174254128000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 399607000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 399607000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 399607000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 399607000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016627 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016627 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016627 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016627 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016627 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016627 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12629.445342 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12629.445342 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12629.445342 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12629.445342 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12629.445342 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12629.445342 # average overall mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84572.910053 # average ReadReq mshr uncacheable latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84572.910053 # average ReadReq mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84572.910053 # average overall mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84572.910053 # average overall mshr uncacheable latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 1351080 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65410.698207 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 46116668 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1414341 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 32.606470 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 3738142500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 9967.984706 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 437.366507 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.963757 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 6246.445194 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48262.938042 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.152099 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006674 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007568 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095313 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.736434 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.998088 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 325 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 62936 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 325 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 808 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5758 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56089 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004959 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960327 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 392953982 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 392953982 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 349715 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 229342 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 579057 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 7954497 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 7954497 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 13795341 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 13795341 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 26690 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 26690 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1630864 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1630864 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13717170 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 13717170 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6618229 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 6618229 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 717802 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 717802 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 349715 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 229342 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 13717170 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 8249093 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 22545320 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 349715 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 229342 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 13717170 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 8249093 # number of overall hits
> system.cpu.l2cache.overall_hits::total 22545320 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4545 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4325 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 8870 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 3863 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 3863 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 548383 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 548383 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 80279 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 80279 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 287555 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 287555 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 516512 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 516512 # number of InvalidateReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 4545 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 4325 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 80279 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 835938 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 925087 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 4545 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 4325 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 80279 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 835938 # number of overall misses
> system.cpu.l2cache.overall_misses::total 925087 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 594871500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 523671500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1118543000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 68752000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 68752000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52773795000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 52773795000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9248862500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 9248862500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33350772500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 33350772500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 594871500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 523671500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 9248862500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 86124567500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 96491973000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 594871500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 523671500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 9248862500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 86124567500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 96491973000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 354260 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 233667 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 587927 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 7954497 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 7954497 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 13795341 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 13795341 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30553 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 30553 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2179247 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2179247 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13797449 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 13797449 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6905784 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 6905784 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1234314 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::total 1234314 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 354260 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 233667 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 13797449 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9085031 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 23470407 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 354260 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 233667 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 13797449 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9085031 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 23470407 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012830 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018509 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015087 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.126436 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.126436 # miss rate for UpgradeReq accesses
1090,1130c1092,1132
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205178 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.205178 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005626 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005626 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039575 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039575 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.406019 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.406019 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010839 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.014647 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005626 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.079027 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.033459 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010839 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.014647 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005626 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.079027 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.033459 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 132945.616642 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 124198.143783 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 128553.114366 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17661.591607 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17661.591607 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98585.610503 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98585.610503 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114789.855550 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114789.855550 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117848.930366 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117848.930366 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 132945.616642 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 124198.143783 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114789.855550 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105934.184456 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 107028.958951 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 132945.616642 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 124198.143783 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114789.855550 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105934.184456 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 107028.958951 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.251639 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.251639 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.041640 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.041640 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.418461 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.418461 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012830 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018509 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.092013 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.039415 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012830 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018509 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.092013 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.039415 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 130884.818482 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 121080.115607 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 126104.058625 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17797.566658 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17797.566658 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96235.286287 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96235.286287 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 115208.989898 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 115208.989898 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115980.499383 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115980.499383 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 130884.818482 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 121080.115607 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 115208.989898 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 103027.458376 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 104305.836100 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 130884.818482 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 121080.115607 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 115208.989898 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 103027.458376 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 104305.836100 # average overall miss latency
1137,1207c1139,1209
< system.cpu.l2cache.writebacks::writebacks 985808 # number of writebacks
< system.cpu.l2cache.writebacks::total 985808 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3365 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3394 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 6759 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3908 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 3908 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 414879 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 414879 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 75874 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 75874 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 255882 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 255882 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 497612 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::total 497612 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3365 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3394 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 75874 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 670761 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 753394 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3365 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3394 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 75874 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 670761 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 753394 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413712000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 387588500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 801300500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 74391500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 74391500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36752309500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36752309500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7950825500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7950825500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27596583533 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27596583533 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9287554000 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9287554000 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413712000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 387588500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7950825500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64348893033 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 73101019033 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413712000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 387588500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7950825500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64348893033 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 73101019033 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3018208500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810725500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8828934000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3018208500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810725500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8828934000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012467 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.135718 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.135718 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.writebacks::writebacks 1160350 # number of writebacks
> system.cpu.l2cache.writebacks::total 1160350 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4545 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4325 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 8870 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3863 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 3863 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 548383 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 548383 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 80279 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 80279 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 287555 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 287555 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 516512 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::total 516512 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4545 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4325 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 80279 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 835938 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 925087 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4545 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4325 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 80279 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 835938 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 925087 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 4725 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33620 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 38345 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33624 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33624 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 4725 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67244 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 71969 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 549421500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 480421500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1029843000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 73648000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 73648000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 47289965000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 47289965000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8446072500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8446072500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30475204536 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30475204536 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9640713000 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9640713000 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 549421500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 480421500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8446072500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77765169536 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 87241085036 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 549421500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 480421500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8446072500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77765169536 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 87241085036 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340544500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5791390500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6131935000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340544500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5791390500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6131935000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015087 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126436 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126436 # mshr miss rate for UpgradeReq accesses
1210,1263c1212,1265
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205178 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205178 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005626 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039575 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039575 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.406019 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.406019 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.033459 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.033459 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118553.114366 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19035.696008 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19035.696008 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88585.610503 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88585.610503 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104789.855550 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104789.855550 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107848.866012 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107848.866012 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18664.248451 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18664.248451 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.395657 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.693691 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.083482 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.220099 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 46927036 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 23726903 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1976 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1976 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.251639 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.251639 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005818 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.041640 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.041640 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.418461 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.418461 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.092013 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.039415 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.092013 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.039415 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116104.058625 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19064.975408 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19064.975408 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86235.286287 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86235.286287 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105208.989898 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105208.989898 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105980.436911 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105980.436911 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18665.031984 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18665.031984 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105208.989898 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 93027.436886 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94305.816681 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105208.989898 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 93027.436886 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94305.816681 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 72072.910053 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172260.276621 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159914.852002 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 72072.910053 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86125.014871 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85202.448276 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 48796648 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 24679855 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1750 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2089 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2089 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1265,1296c1267,1298
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 1011319 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 20964705 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 8482434 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 13486266 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 2389096 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 28798 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 28800 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2022047 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2022047 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 13486783 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 6468652 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 1256381 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1225599 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40546082 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332849 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592477 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 884181 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 71355589 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726447636 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023248134 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1853792 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2483568 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 2754033130 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1585660 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 66286896 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 25466403 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.019742 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.139111 # Request fanout histogram
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 1038155 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 21742291 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 33624 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 33624 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 9114847 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 13796932 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 2555043 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 30556 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 30557 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2179247 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2179247 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 13797449 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 6908747 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 1261981 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1234328 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41401280 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31154016 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 602385 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 985352 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 74143033 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1766059284 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1090777710 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1869336 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2834080 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2861540410 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 1794516 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 77615256 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 26600840 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.020202 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.140692 # Request fanout histogram
1298,1299c1300,1301
< system.cpu.toL2Bus.snoop_fanout::0 24963657 98.03% 98.03% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 502746 1.97% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 26063442 97.98% 97.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 537398 2.02% 100.00% # Request fanout histogram
1304,1305c1306,1307
< system.cpu.toL2Bus.snoop_fanout::total 25466403 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 44736270000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 26600840 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 46435675500 # Layer occupancy (ticks)
1307c1309
< system.cpu.toL2Bus.snoopLayer0.occupancy 1643382 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1669386 # Layer occupancy (ticks)
1309c1311
< system.cpu.toL2Bus.respLayer0.occupancy 20273299500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 20700898500 # Layer occupancy (ticks)
1311c1313
< system.cpu.toL2Bus.respLayer1.occupancy 13409418464 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 14310442440 # Layer occupancy (ticks)
1313c1315
< system.cpu.toL2Bus.respLayer2.occupancy 360753000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 368718000 # Layer occupancy (ticks)
1315c1317
< system.cpu.toL2Bus.respLayer3.occupancy 573735000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 631092000 # Layer occupancy (ticks)
1317,1322c1319,1324
< system.iobus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 40342 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40342 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 40260 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40260 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136485 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136485 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes)
1335,1337c1337,1339
< system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231042 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231042 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes)
1340,1341c1342,1343
< system.iobus.pkt_count::total 353826 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353490 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes)
1354,1356c1356,1358
< system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334600 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334600 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes)
1359,1360c1361,1362
< system.iobus.pkt_size::total 7492520 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 42151500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7492208 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 41845500 # Layer occupancy (ticks)
1382c1384
< system.iobus.reqLayer23.occupancy 25717000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks)
1384c1386
< system.iobus.reqLayer24.occupancy 38602500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 38606000 # Layer occupancy (ticks)
1386c1388
< system.iobus.reqLayer25.occupancy 569022926 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 569335764 # Layer occupancy (ticks)
1388c1390
< system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks)
1390c1392
< system.iobus.respLayer3.occupancy 147802000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks)
1394,1396c1396,1398
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 115502 # number of replacements
< system.iocache.tags.tagsinuse 10.457099 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 115507 # number of replacements
> system.iocache.tags.tagsinuse 10.457942 # Cycle average of tags in use
1398c1400
< system.iocache.tags.sampled_refs 115518 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115523 # Sample count of references to valid blocks.
1400,1405c1402,1407
< system.iocache.tags.warmup_cycle 13154766854000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.510741 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 6.946357 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.434147 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 13151557544000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.511326 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.946616 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.219458 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.434164 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.653621 # Average percentage of cache occupancy
1409,1411c1411,1413
< system.iocache.tags.tag_accesses 1040046 # Number of tag accesses
< system.iocache.tags.data_accesses 1040046 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.tag_accesses 1040082 # Number of tag accesses
> system.iocache.tags.data_accesses 1040082 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
1413,1414c1415,1416
< system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses
1420,1421c1422,1423
< system.iocache.demand_misses::realview.ide 115521 # number of demand (read+write) misses
< system.iocache.demand_misses::total 115561 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115565 # number of demand (read+write) misses
1423,1424c1425,1426
< system.iocache.overall_misses::realview.ide 115521 # number of overall misses
< system.iocache.overall_misses::total 115561 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115525 # number of overall misses
> system.iocache.overall_misses::total 115565 # number of overall misses
1426,1427c1428,1429
< system.iocache.ReadReq_miss_latency::realview.ide 2023754150 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 2028840650 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1980781165 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1985867665 # number of ReadReq miss cycles
1430,1431c1432,1433
< system.iocache.WriteLineReq_miss_latency::realview.ide 13483489276 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13483489276 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13389793099 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13389793099 # number of WriteLineReq miss cycles
1433,1434c1435,1436
< system.iocache.demand_miss_latency::realview.ide 15507243426 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 15512680926 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15370574264 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15376011764 # number of demand (read+write) miss cycles
1436,1437c1438,1439
< system.iocache.overall_miss_latency::realview.ide 15507243426 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 15512680926 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15370574264 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15376011764 # number of overall miss cycles
1439,1440c1441,1442
< system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses)
1446,1447c1448,1449
< system.iocache.demand_accesses::realview.ide 115521 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 115561 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses
1449,1450c1451,1452
< system.iocache.overall_accesses::realview.ide 115521 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 115561 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses
1465,1466c1467,1468
< system.iocache.ReadReq_avg_miss_latency::realview.ide 228492.057130 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 228113.407915 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 223539.235414 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 223181.351427 # average ReadReq miss latency
1469,1470c1471,1472
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126410.872234 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 126410.872234 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125532.448614 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 125532.448614 # average WriteLineReq miss latency
1472,1473c1474,1475
< system.iocache.demand_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 134238.029491 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 133049.766406 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 133050.765924 # average overall miss latency
1475,1477c1477,1479
< system.iocache.overall_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 134238.029491 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 52159 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 133049.766406 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 133050.765924 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 49780 # number of cycles access was blocked
1479c1481
< system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3342 # number of cycles access was blocked
1481c1483
< system.iocache.avg_blocked_cycles::no_mshrs 15.574500 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 14.895272 # average number of cycles each access was blocked
1483,1484c1485,1486
< system.iocache.writebacks::writebacks 106630 # number of writebacks
< system.iocache.writebacks::total 106630 # number of writebacks
---
> system.iocache.writebacks::writebacks 106631 # number of writebacks
> system.iocache.writebacks::total 106631 # number of writebacks
1486,1487c1488,1489
< system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses
1493,1494c1495,1496
< system.iocache.demand_mshr_misses::realview.ide 115521 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 115561 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses
1496,1497c1498,1499
< system.iocache.overall_mshr_misses::realview.ide 115521 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 115561 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses
1499,1500c1501,1502
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1580904150 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1584140650 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1537731165 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1540967665 # number of ReadReq MSHR miss cycles
1503,1504c1505,1506
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8144739087 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 8144739087 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8050946475 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8050946475 # number of WriteLineReq MSHR miss cycles
1506,1507c1508,1509
< system.iocache.demand_mshr_miss_latency::realview.ide 9725643237 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 9729080737 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9588677640 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9592115140 # number of demand (read+write) MSHR miss cycles
1509,1510c1511,1512
< system.iocache.overall_mshr_miss_latency::realview.ide 9725643237 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 9729080737 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9588677640 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9592115140 # number of overall MSHR miss cycles
1525,1526c1527,1528
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 178492.057130 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 178113.407915 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173539.235414 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 173181.351427 # average ReadReq mshr miss latency
1529,1530c1531,1532
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76358.837912 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76358.837912 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75479.510191 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75479.510191 # average WriteLineReq mshr miss latency
1532,1533c1534,1535
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 83000.888466 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 83001.904902 # average overall mshr miss latency
1535,1539c1537,1541
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 2644146 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 1308848 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 3757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 83000.888466 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 83001.904902 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 3026927 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 1497963 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 3722 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1543,1558c1545,1560
< system.membus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadReq 76831 # Transaction distribution
< system.membus.trans_dist::ReadResp 424240 # Transaction distribution
< system.membus.trans_dist::WriteReq 33710 # Transaction distribution
< system.membus.trans_dist::WriteResp 33710 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1092438 # Transaction distribution
< system.membus.trans_dist::CleanEvict 180711 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4469 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
< system.membus.trans_dist::ReadExReq 414321 # Transaction distribution
< system.membus.trans_dist::ReadExResp 414321 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 347409 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 604276 # Transaction distribution
< system.membus.trans_dist::InvalidateResp 30630 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadReq 38345 # Transaction distribution
> system.membus.trans_dist::ReadResp 423947 # Transaction distribution
> system.membus.trans_dist::WriteReq 33624 # Transaction distribution
> system.membus.trans_dist::WriteResp 33624 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1266981 # Transaction distribution
> system.membus.trans_dist::CleanEvict 198449 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4422 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
> system.membus.trans_dist::ReadExReq 547827 # Transaction distribution
> system.membus.trans_dist::ReadExResp 547827 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 385602 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 623176 # Transaction distribution
> system.membus.trans_dist::InvalidateResp 27559 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes)
1561,1566c1563,1568
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256123 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385827 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237256 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 237256 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 3623083 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3733842 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3863202 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237209 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 237209 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 4100411 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes)
1569,1578c1571,1580
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111424480 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111594330 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220672 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7220672 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 118815002 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 33993 # Total snoops (count)
< system.membus.snoopTraffic 214720 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 1481018 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.023235 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.150648 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 133430112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 133599618 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7217152 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7217152 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 140816770 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 30980 # Total snoops (count)
> system.membus.snoopTraffic 218496 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 1632997 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.019173 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.137134 # Request fanout histogram
1580,1581c1582,1583
< system.membus.snoop_fanout::0 1446607 97.68% 97.68% # Request fanout histogram
< system.membus.snoop_fanout::1 34411 2.32% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 1601687 98.08% 98.08% # Request fanout histogram
> system.membus.snoop_fanout::1 31310 1.92% 100.00% # Request fanout histogram
1586,1587c1588,1589
< system.membus.snoop_fanout::total 1481018 # Request fanout histogram
< system.membus.reqLayer0.occupancy 106898000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 1632997 # Request fanout histogram
> system.membus.reqLayer0.occupancy 106607500 # Layer occupancy (ticks)
1591c1593
< system.membus.reqLayer2.occupancy 5816000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5784000 # Layer occupancy (ticks)
1593c1595
< system.membus.reqLayer5.occupancy 7183768776 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 8217045206 # Layer occupancy (ticks)
1595c1597
< system.membus.respLayer2.occupancy 4201020680 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 5023572568 # Layer occupancy (ticks)
1597c1599
< system.membus.respLayer3.occupancy 76902808 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 73701370 # Layer occupancy (ticks)
1599,1605c1601,1607
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
1612,1613c1614,1615
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
1656,1662c1658,1664
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
1667,1678c1669,1680
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states