7,11c7,11
< host_inst_rate 1125548 # Simulator instruction rate (inst/s)
< host_op_rate 1322684 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 69608471837 # Simulator tick rate (ticks/s)
< host_mem_usage 675480 # Number of bytes of host memory used
< host_seconds 743.58 # Real time elapsed on the host
---
> host_inst_rate 729832 # Simulator instruction rate (inst/s)
> host_op_rate 857659 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 45135767006 # Simulator tick rate (ticks/s)
> host_mem_usage 675484 # Number of bytes of host memory used
> host_seconds 1146.75 # Real time elapsed on the host
616,619c616,619
< system.cpu.dcache.demand_hits::cpu.data 283201595 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 283201595 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 283575709 # number of overall hits
< system.cpu.dcache.overall_hits::total 283575709 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits
> system.cpu.dcache.overall_hits::total 283908330 # number of overall hits
632,635c632,635
< system.cpu.dcache.demand_misses::cpu.data 6893121 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 6893121 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 8029572 # number of overall misses
< system.cpu.dcache.overall_misses::total 8029572 # number of overall misses
---
> system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses
> system.cpu.dcache.overall_misses::total 9251082 # number of overall misses
646,649c646,649
< system.cpu.dcache.demand_miss_latency::cpu.data 154677984000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 154677984000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 154677984000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 154677984000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles
662,665c662,665
< system.cpu.dcache.demand_accesses::cpu.data 290094716 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 290094716 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 291605281 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 291605281 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 291648847 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 291648847 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 293159412 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 293159412 # number of overall (read+write) accesses
678,681c678,681
< system.cpu.dcache.demand_miss_rate::cpu.data 0.023762 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.023762 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses
692,695c692,695
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22439.470307 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22439.470307 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 19263.540323 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 19263.540323 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21933.298397 # average overall miss latency
702,703d701
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
728,731c726,729
< system.cpu.dcache.demand_mshr_misses::cpu.data 6849886 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 6849886 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 7984572 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 7984572 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 8071396 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 8071396 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9206082 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9206082 # number of overall MSHR misses
750,753c748,751
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145533577500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 145533577500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166975219500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 166975219500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles
756,759c754,755
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217603000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217603000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417284500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417284500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles
772,775c768,771
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023613 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.023613 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027381 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.027381 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses
788,791c784,787
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21246.131322 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21246.131322 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20912.231676 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20912.231676 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency
794,798c790,791
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.817847 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.817847 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.377540 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.377540 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency
858,859d850
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
898d888
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1090,1091d1079
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1155,1156d1142
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829950000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829950000 # number of WriteReq MSHR uncacheable cycles
1158,1159c1144,1145
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607551500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505276000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777601500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675326000 # number of overall MSHR uncacheable cycles
1213,1214d1198
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.491515 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.491515 # average WriteReq mshr uncacheable latency
1216,1218c1200,1201
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.317015 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.717103 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency
1375,1376c1358,1359
< system.iocache.demand_misses::realview.ide 8860 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8900 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115564 # number of demand (read+write) misses
1378,1379c1361,1362
< system.iocache.overall_misses::realview.ide 8860 # number of overall misses
< system.iocache.overall_misses::total 8900 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115524 # number of overall misses
> system.iocache.overall_misses::total 115564 # number of overall misses
1388,1389c1371,1372
< system.iocache.demand_miss_latency::realview.ide 1628892126 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1634313126 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles
1391,1392c1374,1375
< system.iocache.overall_miss_latency::realview.ide 1628892126 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1634313126 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles
1401,1402c1384,1385
< system.iocache.demand_accesses::realview.ide 8860 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8900 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses
1404,1405c1387,1388
< system.iocache.overall_accesses::realview.ide 8860 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8900 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses
1427,1428c1410,1411
< system.iocache.demand_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 183630.688315 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency
1430,1431c1413,1414
< system.iocache.overall_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 183630.688315 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency
1438,1439d1420
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1450,1451c1431,1432
< system.iocache.demand_mshr_misses::realview.ide 8860 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8900 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses
1453,1454c1434,1435
< system.iocache.overall_mshr_misses::realview.ide 8860 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8900 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses
1463,1464c1444,1445
< system.iocache.demand_mshr_miss_latency::realview.ide 1185892126 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1189313126 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles
1466,1467c1447,1448
< system.iocache.overall_mshr_miss_latency::realview.ide 1185892126 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1189313126 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles
1489,1490c1470,1471
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
1492,1494c1473,1474
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
< host_inst_rate 1125548 # Simulator instruction rate (inst/s)
< host_op_rate 1322684 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 69608471837 # Simulator tick rate (ticks/s)
< host_mem_usage 675480 # Number of bytes of host memory used
< host_seconds 743.58 # Real time elapsed on the host
---
> host_inst_rate 729832 # Simulator instruction rate (inst/s)
> host_op_rate 857659 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 45135767006 # Simulator tick rate (ticks/s)
> host_mem_usage 675484 # Number of bytes of host memory used
> host_seconds 1146.75 # Real time elapsed on the host
616,619c616,619
< system.cpu.dcache.demand_hits::cpu.data 283201595 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 283201595 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 283575709 # number of overall hits
< system.cpu.dcache.overall_hits::total 283575709 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits
> system.cpu.dcache.overall_hits::total 283908330 # number of overall hits
632,635c632,635
< system.cpu.dcache.demand_misses::cpu.data 6893121 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 6893121 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 8029572 # number of overall misses
< system.cpu.dcache.overall_misses::total 8029572 # number of overall misses
---
> system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses
> system.cpu.dcache.overall_misses::total 9251082 # number of overall misses
646,649c646,649
< system.cpu.dcache.demand_miss_latency::cpu.data 154677984000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 154677984000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 154677984000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 154677984000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles
662,665c662,665
< system.cpu.dcache.demand_accesses::cpu.data 290094716 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 290094716 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 291605281 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 291605281 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 291648847 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 291648847 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 293159412 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 293159412 # number of overall (read+write) accesses
678,681c678,681
< system.cpu.dcache.demand_miss_rate::cpu.data 0.023762 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.023762 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses
692,695c692,695
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22439.470307 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22439.470307 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 19263.540323 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 19263.540323 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21933.298397 # average overall miss latency
702,703d701
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
728,731c726,729
< system.cpu.dcache.demand_mshr_misses::cpu.data 6849886 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 6849886 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 7984572 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 7984572 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 8071396 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 8071396 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9206082 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9206082 # number of overall MSHR misses
750,753c748,751
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145533577500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 145533577500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166975219500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 166975219500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles
756,759c754,755
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217603000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217603000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417284500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417284500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles
772,775c768,771
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023613 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.023613 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027381 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.027381 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses
788,791c784,787
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21246.131322 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21246.131322 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20912.231676 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20912.231676 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency
794,798c790,791
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.817847 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.817847 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.377540 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.377540 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency
858,859d850
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
898d888
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1090,1091d1079
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1155,1156d1142
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829950000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829950000 # number of WriteReq MSHR uncacheable cycles
1158,1159c1144,1145
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607551500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505276000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777601500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675326000 # number of overall MSHR uncacheable cycles
1213,1214d1198
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.491515 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.491515 # average WriteReq mshr uncacheable latency
1216,1218c1200,1201
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.317015 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.717103 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency
1375,1376c1358,1359
< system.iocache.demand_misses::realview.ide 8860 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8900 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115564 # number of demand (read+write) misses
1378,1379c1361,1362
< system.iocache.overall_misses::realview.ide 8860 # number of overall misses
< system.iocache.overall_misses::total 8900 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115524 # number of overall misses
> system.iocache.overall_misses::total 115564 # number of overall misses
1388,1389c1371,1372
< system.iocache.demand_miss_latency::realview.ide 1628892126 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1634313126 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles
1391,1392c1374,1375
< system.iocache.overall_miss_latency::realview.ide 1628892126 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1634313126 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles
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< system.iocache.demand_accesses::realview.ide 8860 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8900 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses
1404,1405c1387,1388
< system.iocache.overall_accesses::realview.ide 8860 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8900 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses
1427,1428c1410,1411
< system.iocache.demand_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 183630.688315 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency
1430,1431c1413,1414
< system.iocache.overall_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 183630.688315 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency
1438,1439d1420
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1450,1451c1431,1432
< system.iocache.demand_mshr_misses::realview.ide 8860 # number of demand (read+write) MSHR misses
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---
> system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses
1453,1454c1434,1435
< system.iocache.overall_mshr_misses::realview.ide 8860 # number of overall MSHR misses
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---
> system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses
1463,1464c1444,1445
< system.iocache.demand_mshr_miss_latency::realview.ide 1185892126 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1189313126 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles
1466,1467c1447,1448
< system.iocache.overall_mshr_miss_latency::realview.ide 1185892126 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1189313126 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles
1489,1490c1470,1471
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
1492,1494c1473,1474
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency