Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt

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stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.759374 # Number of seconds simulated 4sim_ticks 51759374264500 # Number of ticks simulated 5final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.759374 # Number of seconds simulated 4sim_ticks 51759374264500 # Number of ticks simulated 5final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1051370 # Simulator instruction rate (inst/s) 8host_op_rate 1235514 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 65021013988 # Simulator tick rate (ticks/s) 10host_mem_usage 718040 # Number of bytes of host memory used 11host_seconds 796.04 # Real time elapsed on the host	7host_inst_rate 622194 # Simulator instruction rate (inst/s) 8host_op_rate 731170 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38479042536 # Simulator tick rate (ticks/s) 10host_mem_usage 677104 # Number of bytes of host memory used 11host_seconds 1345.13 # Real time elapsed on the host
12sim_insts 836933434 # Number of instructions simulated 13sim_ops 983519389 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory 22system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 63133056 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 63153636 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 2426 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2490 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 114528 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 567741 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6242 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 693427 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 986454 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 989027 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 3000 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 91650 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 701991 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7718 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 807437 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 91650 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 91650 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1219741 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1220139 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1219741 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 3000 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 91650 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 702388 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7718 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 2027576 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 693427 # Number of read requests accepted 56system.physmem.writeReqs 989027 # Number of write requests accepted 57system.physmem.readBursts 693427 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 989027 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 44328448 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 50880 # Total number of bytes read from write queue 61system.physmem.bytesWritten 63152448 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 41792444 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 63153636 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 795 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 40853 # Per bank write bursts 68system.physmem.perBankRdBursts::1 42497 # Per bank write bursts 69system.physmem.perBankRdBursts::2 39380 # Per bank write bursts 70system.physmem.perBankRdBursts::3 40815 # Per bank write bursts 71system.physmem.perBankRdBursts::4 36874 # Per bank write bursts 72system.physmem.perBankRdBursts::5 45606 # Per bank write bursts 73system.physmem.perBankRdBursts::6 38207 # Per bank write bursts 74system.physmem.perBankRdBursts::7 36804 # Per bank write bursts 75system.physmem.perBankRdBursts::8 38817 # Per bank write bursts 76system.physmem.perBankRdBursts::9 83381 # Per bank write bursts 77system.physmem.perBankRdBursts::10 47849 # Per bank write bursts 78system.physmem.perBankRdBursts::11 45678 # Per bank write bursts 79system.physmem.perBankRdBursts::12 39735 # Per bank write bursts 80system.physmem.perBankRdBursts::13 40223 # Per bank write bursts 81system.physmem.perBankRdBursts::14 37028 # Per bank write bursts 82system.physmem.perBankRdBursts::15 38885 # Per bank write bursts 83system.physmem.perBankWrBursts::0 61132 # Per bank write bursts 84system.physmem.perBankWrBursts::1 62574 # Per bank write bursts 85system.physmem.perBankWrBursts::2 60681 # Per bank write bursts 86system.physmem.perBankWrBursts::3 62576 # Per bank write bursts 87system.physmem.perBankWrBursts::4 57559 # Per bank write bursts 88system.physmem.perBankWrBursts::5 64093 # Per bank write bursts 89system.physmem.perBankWrBursts::6 59756 # Per bank write bursts 90system.physmem.perBankWrBursts::7 59796 # Per bank write bursts 91system.physmem.perBankWrBursts::8 61252 # Per bank write bursts 92system.physmem.perBankWrBursts::9 63246 # Per bank write bursts 93system.physmem.perBankWrBursts::10 66784 # Per bank write bursts 94system.physmem.perBankWrBursts::11 64593 # Per bank write bursts 95system.physmem.perBankWrBursts::12 60371 # Per bank write bursts 96system.physmem.perBankWrBursts::13 61779 # Per bank write bursts 97system.physmem.perBankWrBursts::14 59591 # Per bank write bursts 98system.physmem.perBankWrBursts::15 60974 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 25 # Number of times write queue was full causing retry 101system.physmem.totGap 51759371327500 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 43101 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 650311 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 986454 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 663933 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 23086 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 455 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 539 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 542 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 655 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 269 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 154 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 32057 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 37802 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 55171 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 54666 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 57679 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 55454 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 58825 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 55973 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 56654 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 56029 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 57159 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 59457 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 57206 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 57286 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 59007 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 55988 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 54822 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 54598 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2305 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 830 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 699 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 495 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 443 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 319 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 278 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 238 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 218 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 238 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 213 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 158 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 441826 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 243.264489 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 146.730249 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 285.608942 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 196692 44.52% 44.52% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 117501 26.59% 71.11% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 39119 8.85% 79.97% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 20402 4.62% 84.58% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 13280 3.01% 87.59% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 8813 1.99% 89.58% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 7349 1.66% 91.25% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 5826 1.32% 92.57% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 32844 7.43% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 441826 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 52334 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 13.234628 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 140.708770 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 52332 100.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 52334 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 52334 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 18.854989 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.140951 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 8.267205 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 48626 92.91% 92.91% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 1874 3.58% 96.50% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 113 0.22% 96.71% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 103 0.20% 96.91% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 52 0.10% 97.01% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 95 0.18% 97.19% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 242 0.46% 97.65% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 26 0.05% 97.70% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 308 0.59% 98.29% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 80 0.15% 98.44% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 37 0.07% 98.51% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 50 0.10% 98.61% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 303 0.58% 99.19% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 32 0.06% 99.25% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 32 0.06% 99.31% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 137 0.26% 99.57% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 171 0.33% 99.90% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 3 0.01% 99.91% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::108-111 2 0.00% 99.92% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 10 0.02% 99.98% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::total 52334 # Writes before turning the bus around for reads 273system.physmem.totQLat 9243736951 # Total ticks spent queuing 274system.physmem.totMemAccLat 22230586951 # Total ticks spent from burst creation until serviced by the DRAM 275system.physmem.totBusLat 3463160000 # Total ticks spent in databus transfers 276system.physmem.avgQLat 13345.81 # Average queueing delay per DRAM burst 277system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 278system.physmem.avgMemAccLat 32095.81 # Average memory access latency per DRAM burst 279system.physmem.avgRdBW 0.86 # Average DRAM read bandwidth in MiByte/s 280system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s 281system.physmem.avgRdBWSys 0.81 # Average system read bandwidth in MiByte/s 282system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s 283system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 284system.physmem.busUtil 0.02 # Data bus utilization in percentage 285system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 286system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 287system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 288system.physmem.avgWrQLen 26.31 # Average write queue length when enqueuing 289system.physmem.readRowHits 510166 # Number of row buffer hits during reads 290system.physmem.writeRowHits 727396 # Number of row buffer hits during writes 291system.physmem.readRowHitRate 73.66 # Row buffer hit rate for reads 292system.physmem.writeRowHitRate 73.71 # Row buffer hit rate for writes 293system.physmem.avgGap 30764211.88 # Average gap between requests 294system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined 295system.physmem_0.actEnergy 1653765120 # Energy for activate commands per rank (pJ) 296system.physmem_0.preEnergy 902352000 # Energy for precharge commands per rank (pJ) 297system.physmem_0.readEnergy 2504080800 # Energy for read commands per rank (pJ) 298system.physmem_0.writeEnergy 3163322160 # Energy for write commands per rank (pJ) 299system.physmem_0.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) 300system.physmem_0.actBackEnergy 1281472530255 # Energy for active background per rank (pJ) 301system.physmem_0.preBackEnergy 29931523073250 # Energy for precharge background per rank (pJ) 302system.physmem_0.totalEnergy 34601889523185 # Total energy per rank (pJ) 303system.physmem_0.averagePower 668.514508 # Core power per rank (mW) 304system.physmem_0.memoryStateTime::IDLE 49793449587940 # Time in different power states 305system.physmem_0.memoryStateTime::REF 1728359100000 # Time in different power states 306system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 307system.physmem_0.memoryStateTime::ACT 237560965810 # Time in different power states 308system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 309system.physmem_1.actEnergy 1686439440 # Energy for activate commands per rank (pJ) 310system.physmem_1.preEnergy 920180250 # Energy for precharge commands per rank (pJ) 311system.physmem_1.readEnergy 2898409800 # Energy for read commands per rank (pJ) 312system.physmem_1.writeEnergy 3230863200 # Energy for write commands per rank (pJ) 313system.physmem_1.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) 314system.physmem_1.actBackEnergy 1285016955840 # Energy for active background per rank (pJ) 315system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ) 316system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ) 317system.physmem_1.averagePower 668.532817 # Core power per rank (mW) 318system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states 319system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states 320system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 321system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states 322system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 323system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 324system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 328system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 329system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 330system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 332system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 340system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 341system.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 342system.bridge.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 343system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 344system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 345system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 346system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 347system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 348system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 349system.cpu_clk_domain.clock 500 # Clock period in ticks 350system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 351system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 360system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 361system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 362system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 363system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 364system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 365system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 366system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 367system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 368system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 369system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 370system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 371system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 372system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 373system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 374system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 375system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 376system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 377system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 378system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 379system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 380system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 381system.cpu.dtb.walker.walks 187211 # Table walker walks requested 382system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors 383system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate 384system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate 385system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting 386system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::0-2047 187192 100.00% 100.00% # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::total 187194 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkCompletionTime::samples 158446 # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::mean 24872.701110 # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::gmean 20850.948689 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::stdev 18486.762457 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::0-65535 157188 99.21% 99.21% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.21% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::131072-196607 1079 0.68% 99.89% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::196608-262143 28 0.02% 99.91% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.95% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::327680-393215 21 0.01% 99.96% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::393216-458751 47 0.03% 99.99% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::total 158446 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walksPending::samples -5153633892 # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::mean 1.304072 # Table walker pending requests distribution 411system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution 412system.cpu.dtb.walker.walksPending::0 1567075704 -30.41% -30.41% # Table walker pending requests distribution 413system.cpu.dtb.walker.walksPending::1 -6720709596 130.41% 100.00% # Table walker pending requests distribution 414system.cpu.dtb.walker.walksPending::total -5153633892 # Table walker pending requests distribution 415system.cpu.dtb.walker.walkPageSizes::4K 146093 92.21% 92.21% # Table walker page sizes translated 416system.cpu.dtb.walker.walkPageSizes::2M 12337 7.79% 100.00% # Table walker page sizes translated 417system.cpu.dtb.walker.walkPageSizes::total 158430 # Table walker page sizes translated 418system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 187211 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin_Requested::total 187211 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 158430 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin_Completed::total 158430 # Table walker requests started/completed, data/inst 424system.cpu.dtb.walker.walkRequestOrigin::total 345641 # Table walker requests started/completed, data/inst 425system.cpu.dtb.inst_hits 0 # ITB inst hits 426system.cpu.dtb.inst_misses 0 # ITB inst misses 427system.cpu.dtb.read_hits 157500215 # DTB read hits 428system.cpu.dtb.read_misses 138721 # DTB read misses 429system.cpu.dtb.write_hits 142992331 # DTB write hits 430system.cpu.dtb.write_misses 48490 # DTB write misses 431system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 432system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 433system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 434system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID	12sim_insts 836933434 # Number of instructions simulated 13sim_ops 983519389 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory 22system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 63133056 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 63153636 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 2426 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2490 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 114528 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 567741 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6242 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 693427 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 986454 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 989027 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 3000 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 91650 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 701991 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7718 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 807437 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 91650 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 91650 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1219741 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1220139 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1219741 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 3000 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 91650 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 702388 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7718 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 2027576 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 693427 # Number of read requests accepted 56system.physmem.writeReqs 989027 # Number of write requests accepted 57system.physmem.readBursts 693427 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 989027 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 44328448 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 50880 # Total number of bytes read from write queue 61system.physmem.bytesWritten 63152448 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 41792444 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 63153636 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 795 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 40853 # Per bank write bursts 68system.physmem.perBankRdBursts::1 42497 # Per bank write bursts 69system.physmem.perBankRdBursts::2 39380 # Per bank write bursts 70system.physmem.perBankRdBursts::3 40815 # Per bank write bursts 71system.physmem.perBankRdBursts::4 36874 # Per bank write bursts 72system.physmem.perBankRdBursts::5 45606 # Per bank write bursts 73system.physmem.perBankRdBursts::6 38207 # Per bank write bursts 74system.physmem.perBankRdBursts::7 36804 # Per bank write bursts 75system.physmem.perBankRdBursts::8 38817 # Per bank write bursts 76system.physmem.perBankRdBursts::9 83381 # Per bank write bursts 77system.physmem.perBankRdBursts::10 47849 # Per bank write bursts 78system.physmem.perBankRdBursts::11 45678 # Per bank write bursts 79system.physmem.perBankRdBursts::12 39735 # Per bank write bursts 80system.physmem.perBankRdBursts::13 40223 # Per bank write bursts 81system.physmem.perBankRdBursts::14 37028 # Per bank write bursts 82system.physmem.perBankRdBursts::15 38885 # Per bank write bursts 83system.physmem.perBankWrBursts::0 61132 # Per bank write bursts 84system.physmem.perBankWrBursts::1 62574 # Per bank write bursts 85system.physmem.perBankWrBursts::2 60681 # Per bank write bursts 86system.physmem.perBankWrBursts::3 62576 # Per bank write bursts 87system.physmem.perBankWrBursts::4 57559 # Per bank write bursts 88system.physmem.perBankWrBursts::5 64093 # Per bank write bursts 89system.physmem.perBankWrBursts::6 59756 # Per bank write bursts 90system.physmem.perBankWrBursts::7 59796 # Per bank write bursts 91system.physmem.perBankWrBursts::8 61252 # Per bank write bursts 92system.physmem.perBankWrBursts::9 63246 # Per bank write bursts 93system.physmem.perBankWrBursts::10 66784 # Per bank write bursts 94system.physmem.perBankWrBursts::11 64593 # Per bank write bursts 95system.physmem.perBankWrBursts::12 60371 # Per bank write bursts 96system.physmem.perBankWrBursts::13 61779 # Per bank write bursts 97system.physmem.perBankWrBursts::14 59591 # Per bank write bursts 98system.physmem.perBankWrBursts::15 60974 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 25 # Number of times write queue was full causing retry 101system.physmem.totGap 51759371327500 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 43101 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 650311 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 986454 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 663933 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 23086 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 455 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 539 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 542 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 655 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 269 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 154 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 32057 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 37802 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 55171 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 54666 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 57679 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 55454 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 58825 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 55973 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 56654 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 56029 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 57159 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 59457 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 57206 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 57286 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 59007 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 55988 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 54822 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 54598 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2305 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 830 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 699 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 495 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 443 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 319 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 278 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 238 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 218 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 238 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 213 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 158 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 441826 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 243.264489 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 146.730249 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 285.608942 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 196692 44.52% 44.52% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 117501 26.59% 71.11% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 39119 8.85% 79.97% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 20402 4.62% 84.58% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 13280 3.01% 87.59% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 8813 1.99% 89.58% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 7349 1.66% 91.25% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 5826 1.32% 92.57% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 32844 7.43% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 441826 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 52334 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 13.234628 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 140.708770 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 52332 100.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 52334 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 52334 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 18.854989 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.140951 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 8.267205 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 48626 92.91% 92.91% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 1874 3.58% 96.50% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 113 0.22% 96.71% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 103 0.20% 96.91% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 52 0.10% 97.01% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 95 0.18% 97.19% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 242 0.46% 97.65% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 26 0.05% 97.70% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 308 0.59% 98.29% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 80 0.15% 98.44% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 37 0.07% 98.51% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 50 0.10% 98.61% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 303 0.58% 99.19% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 32 0.06% 99.25% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 32 0.06% 99.31% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 137 0.26% 99.57% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 171 0.33% 99.90% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 3 0.01% 99.91% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::108-111 2 0.00% 99.92% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 10 0.02% 99.98% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::total 52334 # Writes before turning the bus around for reads 273system.physmem.totQLat 9243736951 # Total ticks spent queuing 274system.physmem.totMemAccLat 22230586951 # Total ticks spent from burst creation until serviced by the DRAM 275system.physmem.totBusLat 3463160000 # Total ticks spent in databus transfers 276system.physmem.avgQLat 13345.81 # Average queueing delay per DRAM burst 277system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 278system.physmem.avgMemAccLat 32095.81 # Average memory access latency per DRAM burst 279system.physmem.avgRdBW 0.86 # Average DRAM read bandwidth in MiByte/s 280system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s 281system.physmem.avgRdBWSys 0.81 # Average system read bandwidth in MiByte/s 282system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s 283system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 284system.physmem.busUtil 0.02 # Data bus utilization in percentage 285system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 286system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 287system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 288system.physmem.avgWrQLen 26.31 # Average write queue length when enqueuing 289system.physmem.readRowHits 510166 # Number of row buffer hits during reads 290system.physmem.writeRowHits 727396 # Number of row buffer hits during writes 291system.physmem.readRowHitRate 73.66 # Row buffer hit rate for reads 292system.physmem.writeRowHitRate 73.71 # Row buffer hit rate for writes 293system.physmem.avgGap 30764211.88 # Average gap between requests 294system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined 295system.physmem_0.actEnergy 1653765120 # Energy for activate commands per rank (pJ) 296system.physmem_0.preEnergy 902352000 # Energy for precharge commands per rank (pJ) 297system.physmem_0.readEnergy 2504080800 # Energy for read commands per rank (pJ) 298system.physmem_0.writeEnergy 3163322160 # Energy for write commands per rank (pJ) 299system.physmem_0.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) 300system.physmem_0.actBackEnergy 1281472530255 # Energy for active background per rank (pJ) 301system.physmem_0.preBackEnergy 29931523073250 # Energy for precharge background per rank (pJ) 302system.physmem_0.totalEnergy 34601889523185 # Total energy per rank (pJ) 303system.physmem_0.averagePower 668.514508 # Core power per rank (mW) 304system.physmem_0.memoryStateTime::IDLE 49793449587940 # Time in different power states 305system.physmem_0.memoryStateTime::REF 1728359100000 # Time in different power states 306system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 307system.physmem_0.memoryStateTime::ACT 237560965810 # Time in different power states 308system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 309system.physmem_1.actEnergy 1686439440 # Energy for activate commands per rank (pJ) 310system.physmem_1.preEnergy 920180250 # Energy for precharge commands per rank (pJ) 311system.physmem_1.readEnergy 2898409800 # Energy for read commands per rank (pJ) 312system.physmem_1.writeEnergy 3230863200 # Energy for write commands per rank (pJ) 313system.physmem_1.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) 314system.physmem_1.actBackEnergy 1285016955840 # Energy for active background per rank (pJ) 315system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ) 316system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ) 317system.physmem_1.averagePower 668.532817 # Core power per rank (mW) 318system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states 319system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states 320system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 321system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states 322system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 323system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 324system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 328system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 329system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 330system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 332system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 340system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 341system.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 342system.bridge.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 343system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 344system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 345system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 346system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 347system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 348system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 349system.cpu_clk_domain.clock 500 # Clock period in ticks 350system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 351system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 360system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 361system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 362system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 363system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 364system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 365system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 366system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 367system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 368system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 369system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 370system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 371system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 372system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 373system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 374system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 375system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 376system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 377system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 378system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 379system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 380system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 381system.cpu.dtb.walker.walks 187211 # Table walker walks requested 382system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors 383system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate 384system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate 385system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting 386system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::0-2047 187192 100.00% 100.00% # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::total 187194 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkCompletionTime::samples 158446 # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::mean 24872.701110 # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::gmean 20850.948689 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::stdev 18486.762457 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::0-65535 157188 99.21% 99.21% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.21% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::131072-196607 1079 0.68% 99.89% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::196608-262143 28 0.02% 99.91% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.95% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::327680-393215 21 0.01% 99.96% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::393216-458751 47 0.03% 99.99% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::total 158446 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walksPending::samples -5153633892 # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::mean 1.304072 # Table walker pending requests distribution 411system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution 412system.cpu.dtb.walker.walksPending::0 1567075704 -30.41% -30.41% # Table walker pending requests distribution 413system.cpu.dtb.walker.walksPending::1 -6720709596 130.41% 100.00% # Table walker pending requests distribution 414system.cpu.dtb.walker.walksPending::total -5153633892 # Table walker pending requests distribution 415system.cpu.dtb.walker.walkPageSizes::4K 146093 92.21% 92.21% # Table walker page sizes translated 416system.cpu.dtb.walker.walkPageSizes::2M 12337 7.79% 100.00% # Table walker page sizes translated 417system.cpu.dtb.walker.walkPageSizes::total 158430 # Table walker page sizes translated 418system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 187211 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin_Requested::total 187211 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 158430 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin_Completed::total 158430 # Table walker requests started/completed, data/inst 424system.cpu.dtb.walker.walkRequestOrigin::total 345641 # Table walker requests started/completed, data/inst 425system.cpu.dtb.inst_hits 0 # ITB inst hits 426system.cpu.dtb.inst_misses 0 # ITB inst misses 427system.cpu.dtb.read_hits 157500215 # DTB read hits 428system.cpu.dtb.read_misses 138721 # DTB read misses 429system.cpu.dtb.write_hits 142992331 # DTB write hits 430system.cpu.dtb.write_misses 48490 # DTB write misses 431system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 432system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 433system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 434system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID
435system.cpu.dtb.flush_entries 71001 # Number of entries that have been flushed from TLB	435system.cpu.dtb.flush_entries 70937 # Number of entries that have been flushed from TLB
436system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 437system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch 438system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 439system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions 440system.cpu.dtb.read_accesses 157638936 # DTB read accesses 441system.cpu.dtb.write_accesses 143040821 # DTB write accesses 442system.cpu.dtb.inst_accesses 0 # ITB inst accesses 443system.cpu.dtb.hits 300492546 # DTB hits 444system.cpu.dtb.misses 187211 # DTB misses 445system.cpu.dtb.accesses 300679757 # DTB accesses 446system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 447system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 456system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 457system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 458system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 459system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 460system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 461system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 462system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 463system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 464system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 465system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 466system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 467system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 468system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 469system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 470system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 471system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 472system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 473system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 474system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 475system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 476system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 477system.cpu.itb.walker.walks 119486 # Table walker walks requested 478system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors 479system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate 480system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate 481system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency 482system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency 483system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency 484system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::mean 28670.651516 # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::gmean 24724.680347 # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::stdev 21871.977834 # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::0-65535 107545 98.63% 98.63% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 98.63% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::131072-196607 1290 1.18% 99.82% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::196608-262143 34 0.03% 99.85% # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::262144-327679 71 0.07% 99.91% # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::327680-393215 41 0.04% 99.95% # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::393216-458751 42 0.04% 99.99% # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 496system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 497system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 498system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 499system.cpu.itb.walker.walkCompletionTime::total 109038 # Table walker service (enqueue to completion) latency 500system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution 501system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution 502system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution 503system.cpu.itb.walker.walkPageSizes::4K 107916 98.97% 98.97% # Table walker page sizes translated 504system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated 505system.cpu.itb.walker.walkPageSizes::total 109038 # Table walker page sizes translated 506system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 507system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119486 # Table walker requests started/completed, data/inst 508system.cpu.itb.walker.walkRequestOrigin_Requested::total 119486 # Table walker requests started/completed, data/inst 509system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 510system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109038 # Table walker requests started/completed, data/inst 511system.cpu.itb.walker.walkRequestOrigin_Completed::total 109038 # Table walker requests started/completed, data/inst 512system.cpu.itb.walker.walkRequestOrigin::total 228524 # Table walker requests started/completed, data/inst 513system.cpu.itb.inst_hits 837449249 # ITB inst hits 514system.cpu.itb.inst_misses 119486 # ITB inst misses 515system.cpu.itb.read_hits 0 # DTB read hits 516system.cpu.itb.read_misses 0 # DTB read misses 517system.cpu.itb.write_hits 0 # DTB write hits 518system.cpu.itb.write_misses 0 # DTB write misses 519system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 520system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 521system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 522system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID	436system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 437system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch 438system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 439system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions 440system.cpu.dtb.read_accesses 157638936 # DTB read accesses 441system.cpu.dtb.write_accesses 143040821 # DTB write accesses 442system.cpu.dtb.inst_accesses 0 # ITB inst accesses 443system.cpu.dtb.hits 300492546 # DTB hits 444system.cpu.dtb.misses 187211 # DTB misses 445system.cpu.dtb.accesses 300679757 # DTB accesses 446system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 447system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 456system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 457system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 458system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 459system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 460system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 461system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 462system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 463system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 464system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 465system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 466system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 467system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 468system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 469system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 470system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 471system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 472system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 473system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 474system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 475system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 476system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 477system.cpu.itb.walker.walks 119486 # Table walker walks requested 478system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors 479system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate 480system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate 481system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency 482system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency 483system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency 484system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::mean 28670.651516 # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::gmean 24724.680347 # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::stdev 21871.977834 # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::0-65535 107545 98.63% 98.63% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 98.63% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::131072-196607 1290 1.18% 99.82% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::196608-262143 34 0.03% 99.85% # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::262144-327679 71 0.07% 99.91% # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::327680-393215 41 0.04% 99.95% # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::393216-458751 42 0.04% 99.99% # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 496system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 497system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 498system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 499system.cpu.itb.walker.walkCompletionTime::total 109038 # Table walker service (enqueue to completion) latency 500system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution 501system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution 502system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution 503system.cpu.itb.walker.walkPageSizes::4K 107916 98.97% 98.97% # Table walker page sizes translated 504system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated 505system.cpu.itb.walker.walkPageSizes::total 109038 # Table walker page sizes translated 506system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 507system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119486 # Table walker requests started/completed, data/inst 508system.cpu.itb.walker.walkRequestOrigin_Requested::total 119486 # Table walker requests started/completed, data/inst 509system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 510system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109038 # Table walker requests started/completed, data/inst 511system.cpu.itb.walker.walkRequestOrigin_Completed::total 109038 # Table walker requests started/completed, data/inst 512system.cpu.itb.walker.walkRequestOrigin::total 228524 # Table walker requests started/completed, data/inst 513system.cpu.itb.inst_hits 837449249 # ITB inst hits 514system.cpu.itb.inst_misses 119486 # ITB inst misses 515system.cpu.itb.read_hits 0 # DTB read hits 516system.cpu.itb.read_misses 0 # DTB read misses 517system.cpu.itb.write_hits 0 # DTB write hits 518system.cpu.itb.write_misses 0 # DTB write misses 519system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 520system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 521system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID 522system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID
523system.cpu.itb.flush_entries 50677 # Number of entries that have been flushed from TLB	523system.cpu.itb.flush_entries 50613 # Number of entries that have been flushed from TLB
524system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 525system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 526system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 527system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 528system.cpu.itb.read_accesses 0 # DTB read accesses 529system.cpu.itb.write_accesses 0 # DTB write accesses 530system.cpu.itb.inst_accesses 837568735 # ITB inst accesses 531system.cpu.itb.hits 837449249 # DTB hits 532system.cpu.itb.misses 119486 # DTB misses 533system.cpu.itb.accesses 837568735 # DTB accesses 534system.cpu.numPwrStateTransitions 32056 # Number of power state transitions 535system.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state 536system.cpu.pwrStateClkGateDist::mean 3133737148.696906 # Distribution of time spent in the clock gated state 537system.cpu.pwrStateClkGateDist::stdev 60742072610.602715 # Distribution of time spent in the clock gated state 538system.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state 539system.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state 540system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state 541system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 542system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 543system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 544system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 545system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 546system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 547system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 548system.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 549system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 550system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 551system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state 552system.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state 553system.cpu.pwrStateResidencyTicks::ON 1531835245186 # Cumulative time (in ticks) in various power states 554system.cpu.pwrStateResidencyTicks::CLK_GATED 50227539019314 # Cumulative time (in ticks) in various power states 555system.cpu.numCycles 103518748529 # number of cpu cycles simulated 556system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 557system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 558system.cpu.kern.inst.arm 0 # number of arm instructions executed 559system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed 560system.cpu.committedInsts 836933434 # Number of instructions committed 561system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed 562system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses 563system.cpu.num_fp_alu_accesses 901230 # Number of float alu accesses 564system.cpu.num_func_calls 50188688 # number of times a function call or return occured 565system.cpu.num_conditional_control_insts 127012937 # number of instructions that are conditional controls 566system.cpu.num_int_insts 904020212 # number of integer instructions 567system.cpu.num_fp_insts 901230 # number of float instructions 568system.cpu.num_int_register_reads 1309570840 # number of times the integer registers were read 569system.cpu.num_int_register_writes 716549182 # number of times the integer registers were written 570system.cpu.num_fp_register_reads 1454726 # number of times the floating registers were read 571system.cpu.num_fp_register_writes 760848 # number of times the floating registers were written 572system.cpu.num_cc_register_reads 217149735 # number of times the CC registers were read 573system.cpu.num_cc_register_writes 216544825 # number of times the CC registers were written 574system.cpu.num_mem_refs 300471292 # number of memory refs 575system.cpu.num_load_insts 157490392 # Number of load instructions 576system.cpu.num_store_insts 142980900 # Number of store instructions 577system.cpu.num_idle_cycles 100455078038.626068 # Number of idle cycles 578system.cpu.num_busy_cycles 3063670490.373941 # Number of busy cycles 579system.cpu.not_idle_fraction 0.029595 # Percentage of non-idle cycles 580system.cpu.idle_fraction 0.970405 # Percentage of idle cycles 581system.cpu.Branches 186768786 # Number of branches fetched 582system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 583system.cpu.op_class::IntAlu 681265861 69.23% 69.23% # Class of executed instruction 584system.cpu.op_class::IntMult 2131844 0.22% 69.45% # Class of executed instruction 585system.cpu.op_class::IntDiv 96991 0.01% 69.46% # Class of executed instruction 586system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction 587system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction 588system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction 589system.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction 590system.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction 591system.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction 592system.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction 593system.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction 594system.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction 595system.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction 596system.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction 597system.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction 598system.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction 599system.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction 600system.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction 601system.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction 602system.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction 603system.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction 604system.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction 605system.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction 606system.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction 607system.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction 608system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction 609system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction 610system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction 611system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction 612system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction 613system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction 614system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 615system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 616system.cpu.op_class::total 984078328 # Class of executed instruction 617system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 618system.cpu.dcache.tags.replacements 9381962 # number of replacements 619system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use 620system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks. 621system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks. 622system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks. 623system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. 624system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor 625system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy 626system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy 627system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 629system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 630system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id 631system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 632system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 633system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses 634system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses 635system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 636system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits 637system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits 638system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits 639system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits 640system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits 641system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits 642system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits 643system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits 644system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits 645system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits 646system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits 647system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits 648system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits 649system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits 650system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits 651system.cpu.dcache.overall_hits::total 283908330 # number of overall hits 652system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses 653system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses 654system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses 655system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses 656system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses 657system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses 658system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses 659system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses 660system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses 661system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses 662system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 663system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 664system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses 665system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses 666system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses 667system.cpu.dcache.overall_misses::total 9251082 # number of overall misses 668system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles 669system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles 670system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles 671system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles 672system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles 673system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles 674system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles 675system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles 676system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 677system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles 678system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles 679system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles 680system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles 681system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles 682system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses) 683system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses) 684system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses) 685system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses) 686system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses) 687system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses) 688system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses) 689system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses) 690system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses) 691system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses) 692system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses) 693system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses) 694system.cpu.dcache.demand_accesses::cpu.data 291648847 # number of demand (read+write) accesses 695system.cpu.dcache.demand_accesses::total 291648847 # number of demand (read+write) accesses 696system.cpu.dcache.overall_accesses::cpu.data 293159412 # number of overall (read+write) accesses 697system.cpu.dcache.overall_accesses::total 293159412 # number of overall (read+write) accesses 698system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses 699system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses 700system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses 701system.cpu.dcache.WriteReq_miss_rate::total 0.014504 # miss rate for WriteReq accesses 702system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752335 # miss rate for SoftPFReq accesses 703system.cpu.dcache.SoftPFReq_miss_rate::total 0.752335 # miss rate for SoftPFReq accesses 704system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785976 # miss rate for WriteLineReq accesses 705system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses 706system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses 707system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses 708system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 709system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 710system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses 711system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses 712system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses 713system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses 714system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency 715system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency 716system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency 717system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency 718system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency 719system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency 720system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency 721system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency 722system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 723system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 724system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency 725system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # average overall miss latency 726system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397 # average overall miss latency 727system.cpu.dcache.overall_avg_miss_latency::total 21933.298397 # average overall miss latency 728system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 729system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 730system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 731system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 732system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 733system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 734system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks 735system.cpu.dcache.writebacks::total 7313678 # number of writebacks 736system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits 737system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits 738system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21254 # number of WriteReq MSHR hits 739system.cpu.dcache.WriteReq_mshr_hits::total 21254 # number of WriteReq MSHR hits 740system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68600 # number of LoadLockedReq MSHR hits 741system.cpu.dcache.LoadLockedReq_mshr_hits::total 68600 # number of LoadLockedReq MSHR hits 742system.cpu.dcache.demand_mshr_hits::cpu.data 43235 # number of demand (read+write) MSHR hits 743system.cpu.dcache.demand_mshr_hits::total 43235 # number of demand (read+write) MSHR hits 744system.cpu.dcache.overall_mshr_hits::cpu.data 43235 # number of overall MSHR hits 745system.cpu.dcache.overall_mshr_hits::total 43235 # number of overall MSHR hits 746system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4873010 # number of ReadReq MSHR misses 747system.cpu.dcache.ReadReq_mshr_misses::total 4873010 # number of ReadReq MSHR misses 748system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1976876 # number of WriteReq MSHR misses 749system.cpu.dcache.WriteReq_mshr_misses::total 1976876 # number of WriteReq MSHR misses 750system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1134686 # number of SoftPFReq MSHR misses 751system.cpu.dcache.SoftPFReq_mshr_misses::total 1134686 # number of SoftPFReq MSHR misses 752system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221510 # number of WriteLineReq MSHR misses 753system.cpu.dcache.WriteLineReq_mshr_misses::total 1221510 # number of WriteLineReq MSHR misses 754system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778 # number of LoadLockedReq MSHR misses 755system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses 756system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 757system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 758system.cpu.dcache.demand_mshr_misses::cpu.data 8071396 # number of demand (read+write) MSHR misses 759system.cpu.dcache.demand_mshr_misses::total 8071396 # number of demand (read+write) MSHR misses 760system.cpu.dcache.overall_mshr_misses::cpu.data 9206082 # number of overall MSHR misses 761system.cpu.dcache.overall_mshr_misses::total 9206082 # number of overall MSHR misses 762system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 763system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable 764system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 765system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 766system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 767system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses 768system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78281972500 # number of ReadReq MSHR miss cycles 769system.cpu.dcache.ReadReq_mshr_miss_latency::total 78281972500 # number of ReadReq MSHR miss cycles 770system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67251605000 # number of WriteReq MSHR miss cycles 771system.cpu.dcache.WriteReq_mshr_miss_latency::total 67251605000 # number of WriteReq MSHR miss cycles 772system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21441642000 # number of SoftPFReq MSHR miss cycles 773system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21441642000 # number of SoftPFReq MSHR miss cycles 774system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 47007248000 # number of WriteLineReq MSHR miss cycles 775system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles 776system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles 777system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles 778system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 779system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles 780system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles 781system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles 782system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles 783system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles 784system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles 785system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles 786system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles 787system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles 788system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses 793system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses 794system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses 795system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses 796system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses 797system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses 798system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 799system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 800system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses 801system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses 802system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses 803system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses 804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency 805system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency 807system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency 808system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency 809system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency 810system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency 811system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency 812system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency 813system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency 814system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 815system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 816system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency 817system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency 818system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency 819system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency 820system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency 821system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency 822system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency 823system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency 824system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 825system.cpu.icache.tags.replacements 13331164 # number of replacements 826system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use 827system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. 828system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks. 829system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks. 830system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. 831system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor 832system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy 833system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy 834system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 835system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 836system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 839system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 840system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses 841system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses 842system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 843system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits 844system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits 845system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits 846system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits 847system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits 848system.cpu.icache.overall_hits::total 824117568 # number of overall hits 849system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses 850system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses 851system.cpu.icache.demand_misses::cpu.inst 13331681 # number of demand (read+write) misses 852system.cpu.icache.demand_misses::total 13331681 # number of demand (read+write) misses 853system.cpu.icache.overall_misses::cpu.inst 13331681 # number of overall misses 854system.cpu.icache.overall_misses::total 13331681 # number of overall misses 855system.cpu.icache.ReadReq_miss_latency::cpu.inst 182292722500 # number of ReadReq miss cycles 856system.cpu.icache.ReadReq_miss_latency::total 182292722500 # number of ReadReq miss cycles 857system.cpu.icache.demand_miss_latency::cpu.inst 182292722500 # number of demand (read+write) miss cycles 858system.cpu.icache.demand_miss_latency::total 182292722500 # number of demand (read+write) miss cycles 859system.cpu.icache.overall_miss_latency::cpu.inst 182292722500 # number of overall miss cycles 860system.cpu.icache.overall_miss_latency::total 182292722500 # number of overall miss cycles 861system.cpu.icache.ReadReq_accesses::cpu.inst 837449249 # number of ReadReq accesses(hits+misses) 862system.cpu.icache.ReadReq_accesses::total 837449249 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.demand_accesses::cpu.inst 837449249 # number of demand (read+write) accesses 864system.cpu.icache.demand_accesses::total 837449249 # number of demand (read+write) accesses 865system.cpu.icache.overall_accesses::cpu.inst 837449249 # number of overall (read+write) accesses 866system.cpu.icache.overall_accesses::total 837449249 # number of overall (read+write) accesses 867system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015919 # miss rate for ReadReq accesses 868system.cpu.icache.ReadReq_miss_rate::total 0.015919 # miss rate for ReadReq accesses 869system.cpu.icache.demand_miss_rate::cpu.inst 0.015919 # miss rate for demand accesses 870system.cpu.icache.demand_miss_rate::total 0.015919 # miss rate for demand accesses 871system.cpu.icache.overall_miss_rate::cpu.inst 0.015919 # miss rate for overall accesses 872system.cpu.icache.overall_miss_rate::total 0.015919 # miss rate for overall accesses 873system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13673.648694 # average ReadReq miss latency 874system.cpu.icache.ReadReq_avg_miss_latency::total 13673.648694 # average ReadReq miss latency 875system.cpu.icache.demand_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency 876system.cpu.icache.demand_avg_miss_latency::total 13673.648694 # average overall miss latency 877system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency 879system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.icache.writebacks::writebacks 13331164 # number of writebacks 886system.cpu.icache.writebacks::total 13331164 # number of writebacks 887system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13331681 # number of ReadReq MSHR misses 888system.cpu.icache.ReadReq_mshr_misses::total 13331681 # number of ReadReq MSHR misses 889system.cpu.icache.demand_mshr_misses::cpu.inst 13331681 # number of demand (read+write) MSHR misses 890system.cpu.icache.demand_mshr_misses::total 13331681 # number of demand (read+write) MSHR misses 891system.cpu.icache.overall_mshr_misses::cpu.inst 13331681 # number of overall MSHR misses 892system.cpu.icache.overall_mshr_misses::total 13331681 # number of overall MSHR misses 893system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 894system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 895system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 896system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 897system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168961041500 # number of ReadReq MSHR miss cycles 898system.cpu.icache.ReadReq_mshr_miss_latency::total 168961041500 # number of ReadReq MSHR miss cycles 899system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168961041500 # number of demand (read+write) MSHR miss cycles 900system.cpu.icache.demand_mshr_miss_latency::total 168961041500 # number of demand (read+write) MSHR miss cycles 901system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168961041500 # number of overall MSHR miss cycles 902system.cpu.icache.overall_mshr_miss_latency::total 168961041500 # number of overall MSHR miss cycles 903system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles 904system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles 905system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles 906system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles 907system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for ReadReq accesses 908system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015919 # mshr miss rate for ReadReq accesses 909system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for demand accesses 910system.cpu.icache.demand_mshr_miss_rate::total 0.015919 # mshr miss rate for demand accesses 911system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for overall accesses 912system.cpu.icache.overall_mshr_miss_rate::total 0.015919 # mshr miss rate for overall accesses 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12673.648694 # average ReadReq mshr miss latency 914system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12673.648694 # average ReadReq mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency 916system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency 918system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency 919system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency 920system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency 921system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency 922system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency 923system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 924system.cpu.l2cache.tags.replacements 1036266 # number of replacements 925system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use 926system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks. 927system.cpu.l2cache.tags.sampled_refs 1098550 # Sample count of references to valid blocks. 928system.cpu.l2cache.tags.avg_refs 37.921538 # Average number of references to valid blocks. 929system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit. 930system.cpu.l2cache.tags.occ_blocks::writebacks 38127.362532 # Average occupied blocks per requestor 931system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 231.236011 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 356.535935 # Average occupied blocks per requestor 933system.cpu.l2cache.tags.occ_blocks::cpu.inst 7851.500133 # Average occupied blocks per requestor 934system.cpu.l2cache.tags.occ_blocks::cpu.data 18688.418163 # Average occupied blocks per requestor 935system.cpu.l2cache.tags.occ_percent::writebacks 0.581777 # Average percentage of cache occupancy 936system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003528 # Average percentage of cache occupancy 937system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005440 # Average percentage of cache occupancy 938system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119804 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::cpu.data 0.285163 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_percent::total 0.995713 # Average percentage of cache occupancy 941system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id 942system.cpu.l2cache.tags.occ_task_id_blocks::1024 62027 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2434 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5507 # Occupied blocks per task id 948system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53647 # Occupied blocks per task id 949system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id 950system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id 951system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses 952system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses 953system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 954system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits 957system.cpu.l2cache.WritebackDirty_hits::writebacks 7313678 # number of WritebackDirty hits 958system.cpu.l2cache.WritebackDirty_hits::total 7313678 # number of WritebackDirty hits 959system.cpu.l2cache.WritebackClean_hits::writebacks 13329610 # number of WritebackClean hits 960system.cpu.l2cache.WritebackClean_hits::total 13329610 # number of WritebackClean hits 961system.cpu.l2cache.UpgradeReq_hits::cpu.data 9057 # number of UpgradeReq hits 962system.cpu.l2cache.UpgradeReq_hits::total 9057 # number of UpgradeReq hits 963system.cpu.l2cache.ReadExReq_hits::cpu.data 1592946 # number of ReadExReq hits 964system.cpu.l2cache.ReadExReq_hits::total 1592946 # number of ReadExReq hits 965system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13260241 # number of ReadCleanReq hits 966system.cpu.l2cache.ReadCleanReq_hits::total 13260241 # number of ReadCleanReq hits 967system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5999138 # number of ReadSharedReq hits 968system.cpu.l2cache.ReadSharedReq_hits::total 5999138 # number of ReadSharedReq hits 969system.cpu.l2cache.InvalidateReq_hits::cpu.data 739812 # number of InvalidateReq hits 970system.cpu.l2cache.InvalidateReq_hits::total 739812 # number of InvalidateReq hits 971system.cpu.l2cache.demand_hits::cpu.dtb.walker 313678 # number of demand (read+write) hits 972system.cpu.l2cache.demand_hits::cpu.itb.walker 242392 # number of demand (read+write) hits 973system.cpu.l2cache.demand_hits::cpu.inst 13260241 # number of demand (read+write) hits 974system.cpu.l2cache.demand_hits::cpu.data 7592084 # number of demand (read+write) hits 975system.cpu.l2cache.demand_hits::total 21408395 # number of demand (read+write) hits 976system.cpu.l2cache.overall_hits::cpu.dtb.walker 313678 # number of overall hits 977system.cpu.l2cache.overall_hits::cpu.itb.walker 242392 # number of overall hits 978system.cpu.l2cache.overall_hits::cpu.inst 13260241 # number of overall hits 979system.cpu.l2cache.overall_hits::cpu.data 7592084 # number of overall hits 980system.cpu.l2cache.overall_hits::total 21408395 # number of overall hits 981system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2426 # number of ReadReq misses 982system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2490 # number of ReadReq misses 983system.cpu.l2cache.ReadReq_misses::total 4916 # number of ReadReq misses 984system.cpu.l2cache.UpgradeReq_misses::cpu.data 33285 # number of UpgradeReq misses 985system.cpu.l2cache.UpgradeReq_misses::total 33285 # number of UpgradeReq misses 986system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 987system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 988system.cpu.l2cache.ReadExReq_misses::cpu.data 341588 # number of ReadExReq misses 989system.cpu.l2cache.ReadExReq_misses::total 341588 # number of ReadExReq misses 990system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 71440 # number of ReadCleanReq misses 991system.cpu.l2cache.ReadCleanReq_misses::total 71440 # number of ReadCleanReq misses 992system.cpu.l2cache.ReadSharedReq_misses::cpu.data 227336 # number of ReadSharedReq misses 993system.cpu.l2cache.ReadSharedReq_misses::total 227336 # number of ReadSharedReq misses 994system.cpu.l2cache.InvalidateReq_misses::cpu.data 481698 # number of InvalidateReq misses 995system.cpu.l2cache.InvalidateReq_misses::total 481698 # number of InvalidateReq misses 996system.cpu.l2cache.demand_misses::cpu.dtb.walker 2426 # number of demand (read+write) misses 997system.cpu.l2cache.demand_misses::cpu.itb.walker 2490 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::cpu.inst 71440 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::cpu.data 568924 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::total 645280 # number of demand (read+write) misses 1001system.cpu.l2cache.overall_misses::cpu.dtb.walker 2426 # number of overall misses 1002system.cpu.l2cache.overall_misses::cpu.itb.walker 2490 # number of overall misses 1003system.cpu.l2cache.overall_misses::cpu.inst 71440 # number of overall misses 1004system.cpu.l2cache.overall_misses::cpu.data 568924 # number of overall misses 1005system.cpu.l2cache.overall_misses::total 645280 # number of overall misses 1006system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 332065500 # number of ReadReq miss cycles 1007system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345888500 # number of ReadReq miss cycles 1008system.cpu.l2cache.ReadReq_miss_latency::total 677954000 # number of ReadReq miss cycles 1009system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1332961000 # number of UpgradeReq miss cycles 1010system.cpu.l2cache.UpgradeReq_miss_latency::total 1332961000 # number of UpgradeReq miss cycles 1011system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 1012system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles 1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 44822292500 # number of ReadExReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::total 44822292500 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9464687500 # number of ReadCleanReq miss cycles 1016system.cpu.l2cache.ReadCleanReq_miss_latency::total 9464687500 # number of ReadCleanReq miss cycles 1017system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30322723500 # number of ReadSharedReq miss cycles 1018system.cpu.l2cache.ReadSharedReq_miss_latency::total 30322723500 # number of ReadSharedReq miss cycles 1019system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 542500 # number of InvalidateReq miss cycles 1020system.cpu.l2cache.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles 1021system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 332065500 # number of demand (read+write) miss cycles 1022system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345888500 # number of demand (read+write) miss cycles 1023system.cpu.l2cache.demand_miss_latency::cpu.inst 9464687500 # number of demand (read+write) miss cycles 1024system.cpu.l2cache.demand_miss_latency::cpu.data 75145016000 # number of demand (read+write) miss cycles 1025system.cpu.l2cache.demand_miss_latency::total 85287657500 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 332065500 # number of overall miss cycles 1027system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345888500 # number of overall miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.inst 9464687500 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.data 75145016000 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::total 85287657500 # number of overall miss cycles 1031system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 316104 # number of ReadReq accesses(hits+misses) 1032system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244882 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.ReadReq_accesses::total 560986 # number of ReadReq accesses(hits+misses) 1034system.cpu.l2cache.WritebackDirty_accesses::writebacks 7313678 # number of WritebackDirty accesses(hits+misses) 1035system.cpu.l2cache.WritebackDirty_accesses::total 7313678 # number of WritebackDirty accesses(hits+misses) 1036system.cpu.l2cache.WritebackClean_accesses::writebacks 13329610 # number of WritebackClean accesses(hits+misses) 1037system.cpu.l2cache.WritebackClean_accesses::total 13329610 # number of WritebackClean accesses(hits+misses) 1038system.cpu.l2cache.UpgradeReq_accesses::cpu.data 42342 # number of UpgradeReq accesses(hits+misses) 1039system.cpu.l2cache.UpgradeReq_accesses::total 42342 # number of UpgradeReq accesses(hits+misses) 1040system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 1041system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 1042system.cpu.l2cache.ReadExReq_accesses::cpu.data 1934534 # number of ReadExReq accesses(hits+misses) 1043system.cpu.l2cache.ReadExReq_accesses::total 1934534 # number of ReadExReq accesses(hits+misses) 1044system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13331681 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu.l2cache.ReadCleanReq_accesses::total 13331681 # number of ReadCleanReq accesses(hits+misses) 1046system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6226474 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu.l2cache.ReadSharedReq_accesses::total 6226474 # number of ReadSharedReq accesses(hits+misses) 1048system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1221510 # number of InvalidateReq accesses(hits+misses) 1049system.cpu.l2cache.InvalidateReq_accesses::total 1221510 # number of InvalidateReq accesses(hits+misses) 1050system.cpu.l2cache.demand_accesses::cpu.dtb.walker 316104 # number of demand (read+write) accesses 1051system.cpu.l2cache.demand_accesses::cpu.itb.walker 244882 # number of demand (read+write) accesses 1052system.cpu.l2cache.demand_accesses::cpu.inst 13331681 # number of demand (read+write) accesses 1053system.cpu.l2cache.demand_accesses::cpu.data 8161008 # number of demand (read+write) accesses 1054system.cpu.l2cache.demand_accesses::total 22053675 # number of demand (read+write) accesses 1055system.cpu.l2cache.overall_accesses::cpu.dtb.walker 316104 # number of overall (read+write) accesses 1056system.cpu.l2cache.overall_accesses::cpu.itb.walker 244882 # number of overall (read+write) accesses 1057system.cpu.l2cache.overall_accesses::cpu.inst 13331681 # number of overall (read+write) accesses 1058system.cpu.l2cache.overall_accesses::cpu.data 8161008 # number of overall (read+write) accesses 1059system.cpu.l2cache.overall_accesses::total 22053675 # number of overall (read+write) accesses 1060system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007675 # miss rate for ReadReq accesses 1061system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010168 # miss rate for ReadReq accesses 1062system.cpu.l2cache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses 1063system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.786099 # miss rate for UpgradeReq accesses 1064system.cpu.l2cache.UpgradeReq_miss_rate::total 0.786099 # miss rate for UpgradeReq accesses 1065system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1066system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1067system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.176574 # miss rate for ReadExReq accesses 1068system.cpu.l2cache.ReadExReq_miss_rate::total 0.176574 # miss rate for ReadExReq accesses 1069system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005359 # miss rate for ReadCleanReq accesses 1070system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005359 # miss rate for ReadCleanReq accesses 1071system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036511 # miss rate for ReadSharedReq accesses 1072system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036511 # miss rate for ReadSharedReq accesses 1073system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.394346 # miss rate for InvalidateReq accesses 1074system.cpu.l2cache.InvalidateReq_miss_rate::total 0.394346 # miss rate for InvalidateReq accesses 1075system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007675 # miss rate for demand accesses 1076system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010168 # miss rate for demand accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005359 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::cpu.data 0.069712 # miss rate for demand accesses 1079system.cpu.l2cache.demand_miss_rate::total 0.029260 # miss rate for demand accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007675 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010168 # miss rate for overall accesses 1082system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005359 # miss rate for overall accesses 1083system.cpu.l2cache.overall_miss_rate::cpu.data 0.069712 # miss rate for overall accesses 1084system.cpu.l2cache.overall_miss_rate::total 0.029260 # miss rate for overall accesses 1085system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136877.782358 # average ReadReq miss latency 1086system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138911.044177 # average ReadReq miss latency 1087system.cpu.l2cache.ReadReq_avg_miss_latency::total 137907.648495 # average ReadReq miss latency 1088system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40046.898002 # average UpgradeReq miss latency 1089system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40046.898002 # average UpgradeReq miss latency 1090system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1091system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1092system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131217.409569 # average ReadExReq miss latency 1093system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131217.409569 # average ReadExReq miss latency 1094system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132484.427492 # average ReadCleanReq miss latency 1095system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132484.427492 # average ReadCleanReq miss latency 1096system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133382.849615 # average ReadSharedReq miss latency 1097system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133382.849615 # average ReadSharedReq miss latency 1098system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 1.126224 # average InvalidateReq miss latency 1099system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 1.126224 # average InvalidateReq miss latency 1100system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency 1101system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency 1102system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency 1103system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency 1104system.cpu.l2cache.demand_avg_miss_latency::total 132171.549560 # average overall miss latency 1105system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency 1106system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency 1107system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency 1108system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency 1109system.cpu.l2cache.overall_avg_miss_latency::total 132171.549560 # average overall miss latency 1110system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1111system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1112system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1113system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1114system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1115system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1116system.cpu.l2cache.writebacks::writebacks 879823 # number of writebacks 1117system.cpu.l2cache.writebacks::total 879823 # number of writebacks 1118system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2426 # number of ReadReq MSHR misses 1119system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2490 # number of ReadReq MSHR misses 1120system.cpu.l2cache.ReadReq_mshr_misses::total 4916 # number of ReadReq MSHR misses 1121system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33285 # number of UpgradeReq MSHR misses 1122system.cpu.l2cache.UpgradeReq_mshr_misses::total 33285 # number of UpgradeReq MSHR misses 1123system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1124system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1125system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341588 # number of ReadExReq MSHR misses 1126system.cpu.l2cache.ReadExReq_mshr_misses::total 341588 # number of ReadExReq MSHR misses 1127system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 71440 # number of ReadCleanReq MSHR misses 1128system.cpu.l2cache.ReadCleanReq_mshr_misses::total 71440 # number of ReadCleanReq MSHR misses 1129system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 227336 # number of ReadSharedReq MSHR misses 1130system.cpu.l2cache.ReadSharedReq_mshr_misses::total 227336 # number of ReadSharedReq MSHR misses 1131system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 481698 # number of InvalidateReq MSHR misses 1132system.cpu.l2cache.InvalidateReq_mshr_misses::total 481698 # number of InvalidateReq MSHR misses 1133system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2426 # number of demand (read+write) MSHR misses 1134system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2490 # number of demand (read+write) MSHR misses 1135system.cpu.l2cache.demand_mshr_misses::cpu.inst 71440 # number of demand (read+write) MSHR misses 1136system.cpu.l2cache.demand_mshr_misses::cpu.data 568924 # number of demand (read+write) MSHR misses 1137system.cpu.l2cache.demand_mshr_misses::total 645280 # number of demand (read+write) MSHR misses 1138system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2426 # number of overall MSHR misses 1139system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2490 # number of overall MSHR misses 1140system.cpu.l2cache.overall_mshr_misses::cpu.inst 71440 # number of overall MSHR misses 1141system.cpu.l2cache.overall_mshr_misses::cpu.data 568924 # number of overall MSHR misses 1142system.cpu.l2cache.overall_mshr_misses::total 645280 # number of overall MSHR misses 1143system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1144system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 1145system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable 1146system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 1147system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 1148system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1149system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 1150system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses 1151system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 307805500 # number of ReadReq MSHR miss cycles 1152system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 320988500 # number of ReadReq MSHR miss cycles 1153system.cpu.l2cache.ReadReq_mshr_miss_latency::total 628794000 # number of ReadReq MSHR miss cycles 1154system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2261111000 # number of UpgradeReq MSHR miss cycles 1155system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2261111000 # number of UpgradeReq MSHR miss cycles 1156system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles 1157system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles 1158system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41406412500 # number of ReadExReq MSHR miss cycles 1159system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41406412500 # number of ReadExReq MSHR miss cycles 1160system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8750287500 # number of ReadCleanReq MSHR miss cycles 1161system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8750287500 # number of ReadCleanReq MSHR miss cycles 1162system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28049107014 # number of ReadSharedReq MSHR miss cycles 1163system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28049107014 # number of ReadSharedReq MSHR miss cycles 1164system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 32589969500 # number of InvalidateReq MSHR miss cycles 1165system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 32589969500 # number of InvalidateReq MSHR miss cycles 1166system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 307805500 # number of demand (read+write) MSHR miss cycles 1167system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 320988500 # number of demand (read+write) MSHR miss cycles 1168system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8750287500 # number of demand (read+write) MSHR miss cycles 1169system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69455519514 # number of demand (read+write) MSHR miss cycles 1170system.cpu.l2cache.demand_mshr_miss_latency::total 78834601014 # number of demand (read+write) MSHR miss cycles 1171system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 307805500 # number of overall MSHR miss cycles 1172system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 320988500 # number of overall MSHR miss cycles 1173system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8750287500 # number of overall MSHR miss cycles 1174system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69455519514 # number of overall MSHR miss cycles 1175system.cpu.l2cache.overall_mshr_miss_latency::total 78834601014 # number of overall MSHR miss cycles 1176system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles 1177system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777601500 # number of ReadReq MSHR uncacheable cycles 1178system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675326000 # number of ReadReq MSHR uncacheable cycles 1179system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles 1180system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777601500 # number of overall MSHR uncacheable cycles 1181system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675326000 # number of overall MSHR uncacheable cycles 1182system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses 1183system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses 1184system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses 1185system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses 1186system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses 1187system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1188system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1189system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses 1190system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176574 # mshr miss rate for ReadExReq accesses 1191system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for ReadCleanReq accesses 1192system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005359 # mshr miss rate for ReadCleanReq accesses 1193system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036511 # mshr miss rate for ReadSharedReq accesses 1194system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadSharedReq accesses 1195system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394346 # mshr miss rate for InvalidateReq accesses 1196system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394346 # mshr miss rate for InvalidateReq accesses 1197system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for demand accesses 1198system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for demand accesses 1199system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for demand accesses 1200system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for demand accesses 1201system.cpu.l2cache.demand_mshr_miss_rate::total 0.029260 # mshr miss rate for demand accesses 1202system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for overall accesses 1203system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for overall accesses 1204system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for overall accesses 1205system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for overall accesses 1206system.cpu.l2cache.overall_mshr_miss_rate::total 0.029260 # mshr miss rate for overall accesses 1207system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average ReadReq mshr miss latency 1208system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average ReadReq mshr miss latency 1209system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127907.648495 # average ReadReq mshr miss latency 1210system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67931.831155 # average UpgradeReq mshr miss latency 1211system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67931.831155 # average UpgradeReq mshr miss latency 1212system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1213system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1214system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121217.409569 # average ReadExReq mshr miss latency 1215system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121217.409569 # average ReadExReq mshr miss latency 1216system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122484.427492 # average ReadCleanReq mshr miss latency 1217system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122484.427492 # average ReadCleanReq mshr miss latency 1218system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123381.721390 # average ReadSharedReq mshr miss latency 1219system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123381.721390 # average ReadSharedReq mshr miss latency 1220system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67656.435152 # average InvalidateReq mshr miss latency 1221system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67656.435152 # average InvalidateReq mshr miss latency 1222system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency 1223system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency 1224system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency 1225system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency 1226system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency 1227system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency 1228system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency 1229system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency 1230system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency 1231system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency 1232system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency 1233system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency 1234system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency 1235system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency 1236system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency 1237system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency 1238system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter. 1239system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1240system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1241system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. 1242system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1243system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1244system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1245system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution 1246system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution 1247system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution 1248system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution 1249system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution 1250system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution 1251system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution 1252system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution 1253system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1254system.cpu.toL2Bus.trans_dist::UpgradeResp 42346 # Transaction distribution 1255system.cpu.toL2Bus.trans_dist::ReadExReq 1934534 # Transaction distribution 1256system.cpu.toL2Bus.trans_dist::ReadExResp 1934534 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::ReadCleanReq 13331681 # Transaction distribution 1258system.cpu.toL2Bus.trans_dist::ReadSharedReq 6235371 # Transaction distribution 1259system.cpu.toL2Bus.trans_dist::InvalidateReq 1328174 # Transaction distribution 1260system.cpu.toL2Bus.trans_dist::InvalidateResp 1221510 # Transaction distribution 1261system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40080776 # Packet count per connected master and slave (bytes) 1262system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28367342 # Packet count per connected master and slave (bytes) 1263system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601942 # Packet count per connected master and slave (bytes) 1264system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 864211 # Packet count per connected master and slave (bytes) 1265system.cpu.toL2Bus.pkt_count::total 69914271 # Packet count per connected master and slave (bytes) 1266system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1706594580 # Cumulative packet size per connected master and slave (bytes) 1267system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 990623790 # Cumulative packet size per connected master and slave (bytes) 1268system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959056 # Cumulative packet size per connected master and slave (bytes) 1269system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2528832 # Cumulative packet size per connected master and slave (bytes) 1270system.cpu.toL2Bus.pkt_size::total 2701706258 # Cumulative packet size per connected master and slave (bytes) 1271system.cpu.toL2Bus.snoops 1612380 # Total snoops (count) 1272system.cpu.toL2Bus.snoop_fanout::samples 25039605 # Request fanout histogram 1273system.cpu.toL2Bus.snoop_fanout::mean 0.019510 # Request fanout histogram 1274system.cpu.toL2Bus.snoop_fanout::stdev 0.138308 # Request fanout histogram 1275system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1276system.cpu.toL2Bus.snoop_fanout::0 24551092 98.05% 98.05% # Request fanout histogram 1277system.cpu.toL2Bus.snoop_fanout::1 488513 1.95% 100.00% # Request fanout histogram 1278system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1279system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1280system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1281system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1282system.cpu.toL2Bus.snoop_fanout::total 25039605 # Request fanout histogram 1283system.cpu.toL2Bus.reqLayer0.occupancy 43904381000 # Layer occupancy (ticks) 1284system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1285system.cpu.toL2Bus.snoopLayer0.occupancy 1555895 # Layer occupancy (ticks) 1286system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1287system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks) 1288system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1289system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks) 1290system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1291system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks) 1292system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1293system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks) 1294system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1295system.iobus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1296system.iobus.trans_dist::ReadReq 40345 # Transaction distribution 1297system.iobus.trans_dist::ReadResp 40345 # Transaction distribution 1298system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1299system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1300system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1301system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1302system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1303system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1304system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1305system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1306system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1307system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1308system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1309system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1310system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1311system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1312system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1313system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1314system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231048 # Packet count per connected master and slave (bytes) 1315system.iobus.pkt_count_system.realview.ide.dma::total 231048 # Packet count per connected master and slave (bytes) 1316system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1317system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1318system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) 1319system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1320system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1321system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1322system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1323system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1324system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1325system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1326system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1327system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1328system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1329system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1330system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1331system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1332system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1333system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334624 # Cumulative packet size per connected master and slave (bytes) 1334system.iobus.pkt_size_system.realview.ide.dma::total 7334624 # Cumulative packet size per connected master and slave (bytes) 1335system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1336system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1337system.iobus.pkt_size::total 7492544 # Cumulative packet size per connected master and slave (bytes) 1338system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) 1339system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1340system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1341system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1342system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) 1343system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1344system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1345system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1346system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) 1347system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1348system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 1349system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1350system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1351system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1352system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1353system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1354system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1355system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1356system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 1357system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1358system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1359system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1360system.iobus.reqLayer23.occupancy 25723500 # Layer occupancy (ticks) 1361system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1362system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) 1363system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1364system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks) 1365system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1366system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1367system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1368system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks) 1369system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1370system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1371system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1372system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1373system.iocache.tags.replacements 115506 # number of replacements 1374system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use 1375system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1376system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. 1377system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1378system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. 1379system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor 1380system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor 1381system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy 1382system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy 1383system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy 1384system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1385system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1386system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1387system.iocache.tags.tag_accesses 1040073 # Number of tag accesses 1388system.iocache.tags.data_accesses 1040073 # Number of data accesses 1389system.iocache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1390system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1391system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses 1392system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses 1393system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1394system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1395system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1396system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1397system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1398system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses 1399system.iocache.demand_misses::total 115564 # number of demand (read+write) misses 1400system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1401system.iocache.overall_misses::realview.ide 115524 # number of overall misses 1402system.iocache.overall_misses::total 115564 # number of overall misses 1403system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles 1404system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles 1405system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles 1406system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1407system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1408system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles 1409system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles 1410system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles 1411system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles 1412system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles 1413system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles 1414system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles 1415system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles 1416system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1417system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses) 1418system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses) 1419system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1420system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1421system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1422system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1423system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1424system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses 1425system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses 1426system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1427system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses 1428system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses 1429system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1430system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1431system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1432system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1433system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1434system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1435system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1436system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1437system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1438system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1439system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1440system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1441system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1442system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency 1443system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency 1444system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency 1445system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1446system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1447system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency 1448system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency 1449system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1450system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency 1451system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency 1452system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1453system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency 1454system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency 1455system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked 1456system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1457system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked 1458system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1459system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked 1460system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1461system.iocache.writebacks::writebacks 106631 # number of writebacks 1462system.iocache.writebacks::total 106631 # number of writebacks 1463system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1464system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses 1465system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses 1466system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1467system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1468system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1469system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1470system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1471system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses 1472system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses 1473system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1474system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses 1475system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses 1476system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles 1477system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles 1478system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles 1479system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1480system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1481system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles 1482system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles 1483system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles 1484system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles 1485system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles 1486system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles 1487system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles 1488system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles 1489system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1490system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1491system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1492system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1493system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1494system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1495system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1496system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1497system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1498system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1499system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1500system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1501system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1502system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency 1503system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency 1504system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency 1505system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1506system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1507system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency 1508system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency 1509system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1510system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency 1511system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency 1512system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1513system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency 1514system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency 1515system.membus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1516system.membus.trans_dist::ReadReq 76827 # Transaction distribution 1517system.membus.trans_dist::ReadResp 389416 # Transaction distribution 1518system.membus.trans_dist::WriteReq 33708 # Transaction distribution 1519system.membus.trans_dist::WriteResp 33708 # Transaction distribution 1520system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution 1521system.membus.trans_dist::CleanEvict 164302 # Transaction distribution 1522system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution 1523system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1524system.membus.trans_dist::UpgradeResp 7 # Transaction distribution 1525system.membus.trans_dist::ReadExReq 341030 # Transaction distribution 1526system.membus.trans_dist::ReadExResp 341030 # Transaction distribution 1527system.membus.trans_dist::ReadSharedReq 312589 # Transaction distribution 1528system.membus.trans_dist::InvalidateReq 588355 # Transaction distribution 1529system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1530system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1531system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) 1532system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2930961 # Packet count per connected master and slave (bytes) 1533system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3060653 # Packet count per connected master and slave (bytes) 1534system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237312 # Packet count per connected master and slave (bytes) 1535system.membus.pkt_count_system.iocache.mem_side::total 237312 # Packet count per connected master and slave (bytes) 1536system.membus.pkt_count::total 3297965 # Packet count per connected master and slave (bytes) 1537system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1538system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1539system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) 1540system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97722208 # Cumulative packet size per connected master and slave (bytes) 1541system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97892034 # Cumulative packet size per connected master and slave (bytes) 1542system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7223872 # Cumulative packet size per connected master and slave (bytes) 1543system.membus.pkt_size_system.iocache.mem_side::total 7223872 # Cumulative packet size per connected master and slave (bytes) 1544system.membus.pkt_size::total 105115906 # Cumulative packet size per connected master and slave (bytes) 1545system.membus.snoops 3315 # Total snoops (count) 1546system.membus.snoop_fanout::samples 2537144 # Request fanout histogram 1547system.membus.snoop_fanout::mean 1 # Request fanout histogram 1548system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1549system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1550system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1551system.membus.snoop_fanout::1 2537144 100.00% 100.00% # Request fanout histogram 1552system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1553system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1554system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1555system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1556system.membus.snoop_fanout::total 2537144 # Request fanout histogram 1557system.membus.reqLayer0.occupancy 106903500 # Layer occupancy (ticks) 1558system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1559system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1560system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1561system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks) 1562system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1563system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks) 1564system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1565system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks) 1566system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1567system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks) 1568system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1569system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1570system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1571system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1572system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1573system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1574system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1575system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1576system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1577system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1578system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1579system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1580system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1581system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1582system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1583system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1584system.realview.ethernet.txBytes 966 # Bytes Transmitted 1585system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1586system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1587system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1588system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1589system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1590system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1591system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1592system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1593system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 1594system.realview.ethernet.totPackets 3 # Total Packets 1595system.realview.ethernet.totBytes 966 # Total Bytes 1596system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1597system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 1598system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1599system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1600system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1601system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1602system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1603system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1604system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1605system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1606system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1607system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1608system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1609system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1610system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1611system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1612system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1613system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1614system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1615system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1616system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1617system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1618system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1619system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1620system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1621system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1622system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1623system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1624system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1625system.realview.ethernet.droppedPackets 0 # number of packets dropped 1626system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1627system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1628system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1629system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1630system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1631system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1632system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1633system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1634system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1635system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1636system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1637system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1638system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1639system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1640system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1641system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1642system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1643system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1644system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1645system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1646system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1647system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1648system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1649 1650---------- End Simulation Statistics ----------	524system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 525system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 526system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 527system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 528system.cpu.itb.read_accesses 0 # DTB read accesses 529system.cpu.itb.write_accesses 0 # DTB write accesses 530system.cpu.itb.inst_accesses 837568735 # ITB inst accesses 531system.cpu.itb.hits 837449249 # DTB hits 532system.cpu.itb.misses 119486 # DTB misses 533system.cpu.itb.accesses 837568735 # DTB accesses 534system.cpu.numPwrStateTransitions 32056 # Number of power state transitions 535system.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state 536system.cpu.pwrStateClkGateDist::mean 3133737148.696906 # Distribution of time spent in the clock gated state 537system.cpu.pwrStateClkGateDist::stdev 60742072610.602715 # Distribution of time spent in the clock gated state 538system.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state 539system.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state 540system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state 541system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 542system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 543system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 544system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 545system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 546system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 547system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 548system.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 549system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 550system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 551system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state 552system.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state 553system.cpu.pwrStateResidencyTicks::ON 1531835245186 # Cumulative time (in ticks) in various power states 554system.cpu.pwrStateResidencyTicks::CLK_GATED 50227539019314 # Cumulative time (in ticks) in various power states 555system.cpu.numCycles 103518748529 # number of cpu cycles simulated 556system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 557system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 558system.cpu.kern.inst.arm 0 # number of arm instructions executed 559system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed 560system.cpu.committedInsts 836933434 # Number of instructions committed 561system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed 562system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses 563system.cpu.num_fp_alu_accesses 901230 # Number of float alu accesses 564system.cpu.num_func_calls 50188688 # number of times a function call or return occured 565system.cpu.num_conditional_control_insts 127012937 # number of instructions that are conditional controls 566system.cpu.num_int_insts 904020212 # number of integer instructions 567system.cpu.num_fp_insts 901230 # number of float instructions 568system.cpu.num_int_register_reads 1309570840 # number of times the integer registers were read 569system.cpu.num_int_register_writes 716549182 # number of times the integer registers were written 570system.cpu.num_fp_register_reads 1454726 # number of times the floating registers were read 571system.cpu.num_fp_register_writes 760848 # number of times the floating registers were written 572system.cpu.num_cc_register_reads 217149735 # number of times the CC registers were read 573system.cpu.num_cc_register_writes 216544825 # number of times the CC registers were written 574system.cpu.num_mem_refs 300471292 # number of memory refs 575system.cpu.num_load_insts 157490392 # Number of load instructions 576system.cpu.num_store_insts 142980900 # Number of store instructions 577system.cpu.num_idle_cycles 100455078038.626068 # Number of idle cycles 578system.cpu.num_busy_cycles 3063670490.373941 # Number of busy cycles 579system.cpu.not_idle_fraction 0.029595 # Percentage of non-idle cycles 580system.cpu.idle_fraction 0.970405 # Percentage of idle cycles 581system.cpu.Branches 186768786 # Number of branches fetched 582system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 583system.cpu.op_class::IntAlu 681265861 69.23% 69.23% # Class of executed instruction 584system.cpu.op_class::IntMult 2131844 0.22% 69.45% # Class of executed instruction 585system.cpu.op_class::IntDiv 96991 0.01% 69.46% # Class of executed instruction 586system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction 587system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction 588system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction 589system.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction 590system.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction 591system.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction 592system.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction 593system.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction 594system.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction 595system.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction 596system.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction 597system.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction 598system.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction 599system.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction 600system.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction 601system.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction 602system.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction 603system.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction 604system.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction 605system.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction 606system.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction 607system.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction 608system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction 609system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction 610system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction 611system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction 612system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction 613system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction 614system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 615system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 616system.cpu.op_class::total 984078328 # Class of executed instruction 617system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 618system.cpu.dcache.tags.replacements 9381962 # number of replacements 619system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use 620system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks. 621system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks. 622system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks. 623system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. 624system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor 625system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy 626system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy 627system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 629system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 630system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id 631system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 632system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 633system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses 634system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses 635system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 636system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits 637system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits 638system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits 639system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits 640system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits 641system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits 642system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits 643system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits 644system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits 645system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits 646system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits 647system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits 648system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits 649system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits 650system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits 651system.cpu.dcache.overall_hits::total 283908330 # number of overall hits 652system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses 653system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses 654system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses 655system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses 656system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses 657system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses 658system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses 659system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses 660system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses 661system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses 662system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 663system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 664system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses 665system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses 666system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses 667system.cpu.dcache.overall_misses::total 9251082 # number of overall misses 668system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles 669system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles 670system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles 671system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles 672system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles 673system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles 674system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles 675system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles 676system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 677system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles 678system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles 679system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles 680system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles 681system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles 682system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses) 683system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses) 684system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses) 685system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses) 686system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses) 687system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses) 688system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses) 689system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses) 690system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses) 691system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses) 692system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses) 693system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses) 694system.cpu.dcache.demand_accesses::cpu.data 291648847 # number of demand (read+write) accesses 695system.cpu.dcache.demand_accesses::total 291648847 # number of demand (read+write) accesses 696system.cpu.dcache.overall_accesses::cpu.data 293159412 # number of overall (read+write) accesses 697system.cpu.dcache.overall_accesses::total 293159412 # number of overall (read+write) accesses 698system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses 699system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses 700system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses 701system.cpu.dcache.WriteReq_miss_rate::total 0.014504 # miss rate for WriteReq accesses 702system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752335 # miss rate for SoftPFReq accesses 703system.cpu.dcache.SoftPFReq_miss_rate::total 0.752335 # miss rate for SoftPFReq accesses 704system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785976 # miss rate for WriteLineReq accesses 705system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses 706system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses 707system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses 708system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 709system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 710system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses 711system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses 712system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses 713system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses 714system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency 715system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency 716system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency 717system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency 718system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency 719system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency 720system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency 721system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency 722system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 723system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 724system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency 725system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # average overall miss latency 726system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397 # average overall miss latency 727system.cpu.dcache.overall_avg_miss_latency::total 21933.298397 # average overall miss latency 728system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 729system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 730system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 731system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 732system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 733system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 734system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks 735system.cpu.dcache.writebacks::total 7313678 # number of writebacks 736system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits 737system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits 738system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21254 # number of WriteReq MSHR hits 739system.cpu.dcache.WriteReq_mshr_hits::total 21254 # number of WriteReq MSHR hits 740system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68600 # number of LoadLockedReq MSHR hits 741system.cpu.dcache.LoadLockedReq_mshr_hits::total 68600 # number of LoadLockedReq MSHR hits 742system.cpu.dcache.demand_mshr_hits::cpu.data 43235 # number of demand (read+write) MSHR hits 743system.cpu.dcache.demand_mshr_hits::total 43235 # number of demand (read+write) MSHR hits 744system.cpu.dcache.overall_mshr_hits::cpu.data 43235 # number of overall MSHR hits 745system.cpu.dcache.overall_mshr_hits::total 43235 # number of overall MSHR hits 746system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4873010 # number of ReadReq MSHR misses 747system.cpu.dcache.ReadReq_mshr_misses::total 4873010 # number of ReadReq MSHR misses 748system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1976876 # number of WriteReq MSHR misses 749system.cpu.dcache.WriteReq_mshr_misses::total 1976876 # number of WriteReq MSHR misses 750system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1134686 # number of SoftPFReq MSHR misses 751system.cpu.dcache.SoftPFReq_mshr_misses::total 1134686 # number of SoftPFReq MSHR misses 752system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221510 # number of WriteLineReq MSHR misses 753system.cpu.dcache.WriteLineReq_mshr_misses::total 1221510 # number of WriteLineReq MSHR misses 754system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778 # number of LoadLockedReq MSHR misses 755system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses 756system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 757system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 758system.cpu.dcache.demand_mshr_misses::cpu.data 8071396 # number of demand (read+write) MSHR misses 759system.cpu.dcache.demand_mshr_misses::total 8071396 # number of demand (read+write) MSHR misses 760system.cpu.dcache.overall_mshr_misses::cpu.data 9206082 # number of overall MSHR misses 761system.cpu.dcache.overall_mshr_misses::total 9206082 # number of overall MSHR misses 762system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 763system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable 764system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 765system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 766system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 767system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses 768system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78281972500 # number of ReadReq MSHR miss cycles 769system.cpu.dcache.ReadReq_mshr_miss_latency::total 78281972500 # number of ReadReq MSHR miss cycles 770system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67251605000 # number of WriteReq MSHR miss cycles 771system.cpu.dcache.WriteReq_mshr_miss_latency::total 67251605000 # number of WriteReq MSHR miss cycles 772system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21441642000 # number of SoftPFReq MSHR miss cycles 773system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21441642000 # number of SoftPFReq MSHR miss cycles 774system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 47007248000 # number of WriteLineReq MSHR miss cycles 775system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles 776system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles 777system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles 778system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 779system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles 780system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles 781system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles 782system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles 783system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles 784system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles 785system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles 786system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles 787system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles 788system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses 793system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses 794system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses 795system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses 796system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses 797system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses 798system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 799system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 800system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses 801system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses 802system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses 803system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses 804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency 805system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency 807system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency 808system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency 809system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency 810system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency 811system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency 812system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency 813system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency 814system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 815system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 816system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency 817system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency 818system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency 819system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency 820system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency 821system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency 822system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency 823system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency 824system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 825system.cpu.icache.tags.replacements 13331164 # number of replacements 826system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use 827system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. 828system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks. 829system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks. 830system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. 831system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor 832system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy 833system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy 834system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 835system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 836system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 839system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 840system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses 841system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses 842system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 843system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits 844system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits 845system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits 846system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits 847system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits 848system.cpu.icache.overall_hits::total 824117568 # number of overall hits 849system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses 850system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses 851system.cpu.icache.demand_misses::cpu.inst 13331681 # number of demand (read+write) misses 852system.cpu.icache.demand_misses::total 13331681 # number of demand (read+write) misses 853system.cpu.icache.overall_misses::cpu.inst 13331681 # number of overall misses 854system.cpu.icache.overall_misses::total 13331681 # number of overall misses 855system.cpu.icache.ReadReq_miss_latency::cpu.inst 182292722500 # number of ReadReq miss cycles 856system.cpu.icache.ReadReq_miss_latency::total 182292722500 # number of ReadReq miss cycles 857system.cpu.icache.demand_miss_latency::cpu.inst 182292722500 # number of demand (read+write) miss cycles 858system.cpu.icache.demand_miss_latency::total 182292722500 # number of demand (read+write) miss cycles 859system.cpu.icache.overall_miss_latency::cpu.inst 182292722500 # number of overall miss cycles 860system.cpu.icache.overall_miss_latency::total 182292722500 # number of overall miss cycles 861system.cpu.icache.ReadReq_accesses::cpu.inst 837449249 # number of ReadReq accesses(hits+misses) 862system.cpu.icache.ReadReq_accesses::total 837449249 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.demand_accesses::cpu.inst 837449249 # number of demand (read+write) accesses 864system.cpu.icache.demand_accesses::total 837449249 # number of demand (read+write) accesses 865system.cpu.icache.overall_accesses::cpu.inst 837449249 # number of overall (read+write) accesses 866system.cpu.icache.overall_accesses::total 837449249 # number of overall (read+write) accesses 867system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015919 # miss rate for ReadReq accesses 868system.cpu.icache.ReadReq_miss_rate::total 0.015919 # miss rate for ReadReq accesses 869system.cpu.icache.demand_miss_rate::cpu.inst 0.015919 # miss rate for demand accesses 870system.cpu.icache.demand_miss_rate::total 0.015919 # miss rate for demand accesses 871system.cpu.icache.overall_miss_rate::cpu.inst 0.015919 # miss rate for overall accesses 872system.cpu.icache.overall_miss_rate::total 0.015919 # miss rate for overall accesses 873system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13673.648694 # average ReadReq miss latency 874system.cpu.icache.ReadReq_avg_miss_latency::total 13673.648694 # average ReadReq miss latency 875system.cpu.icache.demand_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency 876system.cpu.icache.demand_avg_miss_latency::total 13673.648694 # average overall miss latency 877system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency 879system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.icache.writebacks::writebacks 13331164 # number of writebacks 886system.cpu.icache.writebacks::total 13331164 # number of writebacks 887system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13331681 # number of ReadReq MSHR misses 888system.cpu.icache.ReadReq_mshr_misses::total 13331681 # number of ReadReq MSHR misses 889system.cpu.icache.demand_mshr_misses::cpu.inst 13331681 # number of demand (read+write) MSHR misses 890system.cpu.icache.demand_mshr_misses::total 13331681 # number of demand (read+write) MSHR misses 891system.cpu.icache.overall_mshr_misses::cpu.inst 13331681 # number of overall MSHR misses 892system.cpu.icache.overall_mshr_misses::total 13331681 # number of overall MSHR misses 893system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 894system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 895system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 896system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 897system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168961041500 # number of ReadReq MSHR miss cycles 898system.cpu.icache.ReadReq_mshr_miss_latency::total 168961041500 # number of ReadReq MSHR miss cycles 899system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168961041500 # number of demand (read+write) MSHR miss cycles 900system.cpu.icache.demand_mshr_miss_latency::total 168961041500 # number of demand (read+write) MSHR miss cycles 901system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168961041500 # number of overall MSHR miss cycles 902system.cpu.icache.overall_mshr_miss_latency::total 168961041500 # number of overall MSHR miss cycles 903system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles 904system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles 905system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles 906system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles 907system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for ReadReq accesses 908system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015919 # mshr miss rate for ReadReq accesses 909system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for demand accesses 910system.cpu.icache.demand_mshr_miss_rate::total 0.015919 # mshr miss rate for demand accesses 911system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for overall accesses 912system.cpu.icache.overall_mshr_miss_rate::total 0.015919 # mshr miss rate for overall accesses 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12673.648694 # average ReadReq mshr miss latency 914system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12673.648694 # average ReadReq mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency 916system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency 918system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency 919system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency 920system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency 921system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency 922system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency 923system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 924system.cpu.l2cache.tags.replacements 1036266 # number of replacements 925system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use 926system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks. 927system.cpu.l2cache.tags.sampled_refs 1098550 # Sample count of references to valid blocks. 928system.cpu.l2cache.tags.avg_refs 37.921538 # Average number of references to valid blocks. 929system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit. 930system.cpu.l2cache.tags.occ_blocks::writebacks 38127.362532 # Average occupied blocks per requestor 931system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 231.236011 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 356.535935 # Average occupied blocks per requestor 933system.cpu.l2cache.tags.occ_blocks::cpu.inst 7851.500133 # Average occupied blocks per requestor 934system.cpu.l2cache.tags.occ_blocks::cpu.data 18688.418163 # Average occupied blocks per requestor 935system.cpu.l2cache.tags.occ_percent::writebacks 0.581777 # Average percentage of cache occupancy 936system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003528 # Average percentage of cache occupancy 937system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005440 # Average percentage of cache occupancy 938system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119804 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::cpu.data 0.285163 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_percent::total 0.995713 # Average percentage of cache occupancy 941system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id 942system.cpu.l2cache.tags.occ_task_id_blocks::1024 62027 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2434 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5507 # Occupied blocks per task id 948system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53647 # Occupied blocks per task id 949system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id 950system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id 951system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses 952system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses 953system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 954system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits 957system.cpu.l2cache.WritebackDirty_hits::writebacks 7313678 # number of WritebackDirty hits 958system.cpu.l2cache.WritebackDirty_hits::total 7313678 # number of WritebackDirty hits 959system.cpu.l2cache.WritebackClean_hits::writebacks 13329610 # number of WritebackClean hits 960system.cpu.l2cache.WritebackClean_hits::total 13329610 # number of WritebackClean hits 961system.cpu.l2cache.UpgradeReq_hits::cpu.data 9057 # number of UpgradeReq hits 962system.cpu.l2cache.UpgradeReq_hits::total 9057 # number of UpgradeReq hits 963system.cpu.l2cache.ReadExReq_hits::cpu.data 1592946 # number of ReadExReq hits 964system.cpu.l2cache.ReadExReq_hits::total 1592946 # number of ReadExReq hits 965system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13260241 # number of ReadCleanReq hits 966system.cpu.l2cache.ReadCleanReq_hits::total 13260241 # number of ReadCleanReq hits 967system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5999138 # number of ReadSharedReq hits 968system.cpu.l2cache.ReadSharedReq_hits::total 5999138 # number of ReadSharedReq hits 969system.cpu.l2cache.InvalidateReq_hits::cpu.data 739812 # number of InvalidateReq hits 970system.cpu.l2cache.InvalidateReq_hits::total 739812 # number of InvalidateReq hits 971system.cpu.l2cache.demand_hits::cpu.dtb.walker 313678 # number of demand (read+write) hits 972system.cpu.l2cache.demand_hits::cpu.itb.walker 242392 # number of demand (read+write) hits 973system.cpu.l2cache.demand_hits::cpu.inst 13260241 # number of demand (read+write) hits 974system.cpu.l2cache.demand_hits::cpu.data 7592084 # number of demand (read+write) hits 975system.cpu.l2cache.demand_hits::total 21408395 # number of demand (read+write) hits 976system.cpu.l2cache.overall_hits::cpu.dtb.walker 313678 # number of overall hits 977system.cpu.l2cache.overall_hits::cpu.itb.walker 242392 # number of overall hits 978system.cpu.l2cache.overall_hits::cpu.inst 13260241 # number of overall hits 979system.cpu.l2cache.overall_hits::cpu.data 7592084 # number of overall hits 980system.cpu.l2cache.overall_hits::total 21408395 # number of overall hits 981system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2426 # number of ReadReq misses 982system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2490 # number of ReadReq misses 983system.cpu.l2cache.ReadReq_misses::total 4916 # number of ReadReq misses 984system.cpu.l2cache.UpgradeReq_misses::cpu.data 33285 # number of UpgradeReq misses 985system.cpu.l2cache.UpgradeReq_misses::total 33285 # number of UpgradeReq misses 986system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 987system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 988system.cpu.l2cache.ReadExReq_misses::cpu.data 341588 # number of ReadExReq misses 989system.cpu.l2cache.ReadExReq_misses::total 341588 # number of ReadExReq misses 990system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 71440 # number of ReadCleanReq misses 991system.cpu.l2cache.ReadCleanReq_misses::total 71440 # number of ReadCleanReq misses 992system.cpu.l2cache.ReadSharedReq_misses::cpu.data 227336 # number of ReadSharedReq misses 993system.cpu.l2cache.ReadSharedReq_misses::total 227336 # number of ReadSharedReq misses 994system.cpu.l2cache.InvalidateReq_misses::cpu.data 481698 # number of InvalidateReq misses 995system.cpu.l2cache.InvalidateReq_misses::total 481698 # number of InvalidateReq misses 996system.cpu.l2cache.demand_misses::cpu.dtb.walker 2426 # number of demand (read+write) misses 997system.cpu.l2cache.demand_misses::cpu.itb.walker 2490 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::cpu.inst 71440 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::cpu.data 568924 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::total 645280 # number of demand (read+write) misses 1001system.cpu.l2cache.overall_misses::cpu.dtb.walker 2426 # number of overall misses 1002system.cpu.l2cache.overall_misses::cpu.itb.walker 2490 # number of overall misses 1003system.cpu.l2cache.overall_misses::cpu.inst 71440 # number of overall misses 1004system.cpu.l2cache.overall_misses::cpu.data 568924 # number of overall misses 1005system.cpu.l2cache.overall_misses::total 645280 # number of overall misses 1006system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 332065500 # number of ReadReq miss cycles 1007system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345888500 # number of ReadReq miss cycles 1008system.cpu.l2cache.ReadReq_miss_latency::total 677954000 # number of ReadReq miss cycles 1009system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1332961000 # number of UpgradeReq miss cycles 1010system.cpu.l2cache.UpgradeReq_miss_latency::total 1332961000 # number of UpgradeReq miss cycles 1011system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 1012system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles 1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 44822292500 # number of ReadExReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::total 44822292500 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9464687500 # number of ReadCleanReq miss cycles 1016system.cpu.l2cache.ReadCleanReq_miss_latency::total 9464687500 # number of ReadCleanReq miss cycles 1017system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30322723500 # number of ReadSharedReq miss cycles 1018system.cpu.l2cache.ReadSharedReq_miss_latency::total 30322723500 # number of ReadSharedReq miss cycles 1019system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 542500 # number of InvalidateReq miss cycles 1020system.cpu.l2cache.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles 1021system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 332065500 # number of demand (read+write) miss cycles 1022system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345888500 # number of demand (read+write) miss cycles 1023system.cpu.l2cache.demand_miss_latency::cpu.inst 9464687500 # number of demand (read+write) miss cycles 1024system.cpu.l2cache.demand_miss_latency::cpu.data 75145016000 # number of demand (read+write) miss cycles 1025system.cpu.l2cache.demand_miss_latency::total 85287657500 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 332065500 # number of overall miss cycles 1027system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345888500 # number of overall miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.inst 9464687500 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.data 75145016000 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::total 85287657500 # number of overall miss cycles 1031system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 316104 # number of ReadReq accesses(hits+misses) 1032system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244882 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.ReadReq_accesses::total 560986 # number of ReadReq accesses(hits+misses) 1034system.cpu.l2cache.WritebackDirty_accesses::writebacks 7313678 # number of WritebackDirty accesses(hits+misses) 1035system.cpu.l2cache.WritebackDirty_accesses::total 7313678 # number of WritebackDirty accesses(hits+misses) 1036system.cpu.l2cache.WritebackClean_accesses::writebacks 13329610 # number of WritebackClean accesses(hits+misses) 1037system.cpu.l2cache.WritebackClean_accesses::total 13329610 # number of WritebackClean accesses(hits+misses) 1038system.cpu.l2cache.UpgradeReq_accesses::cpu.data 42342 # number of UpgradeReq accesses(hits+misses) 1039system.cpu.l2cache.UpgradeReq_accesses::total 42342 # number of UpgradeReq accesses(hits+misses) 1040system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 1041system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 1042system.cpu.l2cache.ReadExReq_accesses::cpu.data 1934534 # number of ReadExReq accesses(hits+misses) 1043system.cpu.l2cache.ReadExReq_accesses::total 1934534 # number of ReadExReq accesses(hits+misses) 1044system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13331681 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu.l2cache.ReadCleanReq_accesses::total 13331681 # number of ReadCleanReq accesses(hits+misses) 1046system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6226474 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu.l2cache.ReadSharedReq_accesses::total 6226474 # number of ReadSharedReq accesses(hits+misses) 1048system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1221510 # number of InvalidateReq accesses(hits+misses) 1049system.cpu.l2cache.InvalidateReq_accesses::total 1221510 # number of InvalidateReq accesses(hits+misses) 1050system.cpu.l2cache.demand_accesses::cpu.dtb.walker 316104 # number of demand (read+write) accesses 1051system.cpu.l2cache.demand_accesses::cpu.itb.walker 244882 # number of demand (read+write) accesses 1052system.cpu.l2cache.demand_accesses::cpu.inst 13331681 # number of demand (read+write) accesses 1053system.cpu.l2cache.demand_accesses::cpu.data 8161008 # number of demand (read+write) accesses 1054system.cpu.l2cache.demand_accesses::total 22053675 # number of demand (read+write) accesses 1055system.cpu.l2cache.overall_accesses::cpu.dtb.walker 316104 # number of overall (read+write) accesses 1056system.cpu.l2cache.overall_accesses::cpu.itb.walker 244882 # number of overall (read+write) accesses 1057system.cpu.l2cache.overall_accesses::cpu.inst 13331681 # number of overall (read+write) accesses 1058system.cpu.l2cache.overall_accesses::cpu.data 8161008 # number of overall (read+write) accesses 1059system.cpu.l2cache.overall_accesses::total 22053675 # number of overall (read+write) accesses 1060system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007675 # miss rate for ReadReq accesses 1061system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010168 # miss rate for ReadReq accesses 1062system.cpu.l2cache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses 1063system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.786099 # miss rate for UpgradeReq accesses 1064system.cpu.l2cache.UpgradeReq_miss_rate::total 0.786099 # miss rate for UpgradeReq accesses 1065system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1066system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1067system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.176574 # miss rate for ReadExReq accesses 1068system.cpu.l2cache.ReadExReq_miss_rate::total 0.176574 # miss rate for ReadExReq accesses 1069system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005359 # miss rate for ReadCleanReq accesses 1070system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005359 # miss rate for ReadCleanReq accesses 1071system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036511 # miss rate for ReadSharedReq accesses 1072system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036511 # miss rate for ReadSharedReq accesses 1073system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.394346 # miss rate for InvalidateReq accesses 1074system.cpu.l2cache.InvalidateReq_miss_rate::total 0.394346 # miss rate for InvalidateReq accesses 1075system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007675 # miss rate for demand accesses 1076system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010168 # miss rate for demand accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005359 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::cpu.data 0.069712 # miss rate for demand accesses 1079system.cpu.l2cache.demand_miss_rate::total 0.029260 # miss rate for demand accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007675 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010168 # miss rate for overall accesses 1082system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005359 # miss rate for overall accesses 1083system.cpu.l2cache.overall_miss_rate::cpu.data 0.069712 # miss rate for overall accesses 1084system.cpu.l2cache.overall_miss_rate::total 0.029260 # miss rate for overall accesses 1085system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136877.782358 # average ReadReq miss latency 1086system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138911.044177 # average ReadReq miss latency 1087system.cpu.l2cache.ReadReq_avg_miss_latency::total 137907.648495 # average ReadReq miss latency 1088system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40046.898002 # average UpgradeReq miss latency 1089system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40046.898002 # average UpgradeReq miss latency 1090system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1091system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1092system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131217.409569 # average ReadExReq miss latency 1093system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131217.409569 # average ReadExReq miss latency 1094system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132484.427492 # average ReadCleanReq miss latency 1095system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132484.427492 # average ReadCleanReq miss latency 1096system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133382.849615 # average ReadSharedReq miss latency 1097system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133382.849615 # average ReadSharedReq miss latency 1098system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 1.126224 # average InvalidateReq miss latency 1099system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 1.126224 # average InvalidateReq miss latency 1100system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency 1101system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency 1102system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency 1103system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency 1104system.cpu.l2cache.demand_avg_miss_latency::total 132171.549560 # average overall miss latency 1105system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency 1106system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency 1107system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency 1108system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency 1109system.cpu.l2cache.overall_avg_miss_latency::total 132171.549560 # average overall miss latency 1110system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1111system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1112system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1113system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1114system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1115system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1116system.cpu.l2cache.writebacks::writebacks 879823 # number of writebacks 1117system.cpu.l2cache.writebacks::total 879823 # number of writebacks 1118system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2426 # number of ReadReq MSHR misses 1119system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2490 # number of ReadReq MSHR misses 1120system.cpu.l2cache.ReadReq_mshr_misses::total 4916 # number of ReadReq MSHR misses 1121system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33285 # number of UpgradeReq MSHR misses 1122system.cpu.l2cache.UpgradeReq_mshr_misses::total 33285 # number of UpgradeReq MSHR misses 1123system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1124system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1125system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341588 # number of ReadExReq MSHR misses 1126system.cpu.l2cache.ReadExReq_mshr_misses::total 341588 # number of ReadExReq MSHR misses 1127system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 71440 # number of ReadCleanReq MSHR misses 1128system.cpu.l2cache.ReadCleanReq_mshr_misses::total 71440 # number of ReadCleanReq MSHR misses 1129system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 227336 # number of ReadSharedReq MSHR misses 1130system.cpu.l2cache.ReadSharedReq_mshr_misses::total 227336 # number of ReadSharedReq MSHR misses 1131system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 481698 # number of InvalidateReq MSHR misses 1132system.cpu.l2cache.InvalidateReq_mshr_misses::total 481698 # number of InvalidateReq MSHR misses 1133system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2426 # number of demand (read+write) MSHR misses 1134system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2490 # number of demand (read+write) MSHR misses 1135system.cpu.l2cache.demand_mshr_misses::cpu.inst 71440 # number of demand (read+write) MSHR misses 1136system.cpu.l2cache.demand_mshr_misses::cpu.data 568924 # number of demand (read+write) MSHR misses 1137system.cpu.l2cache.demand_mshr_misses::total 645280 # number of demand (read+write) MSHR misses 1138system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2426 # number of overall MSHR misses 1139system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2490 # number of overall MSHR misses 1140system.cpu.l2cache.overall_mshr_misses::cpu.inst 71440 # number of overall MSHR misses 1141system.cpu.l2cache.overall_mshr_misses::cpu.data 568924 # number of overall MSHR misses 1142system.cpu.l2cache.overall_mshr_misses::total 645280 # number of overall MSHR misses 1143system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1144system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 1145system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable 1146system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 1147system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 1148system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1149system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 1150system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses 1151system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 307805500 # number of ReadReq MSHR miss cycles 1152system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 320988500 # number of ReadReq MSHR miss cycles 1153system.cpu.l2cache.ReadReq_mshr_miss_latency::total 628794000 # number of ReadReq MSHR miss cycles 1154system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2261111000 # number of UpgradeReq MSHR miss cycles 1155system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2261111000 # number of UpgradeReq MSHR miss cycles 1156system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles 1157system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles 1158system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41406412500 # number of ReadExReq MSHR miss cycles 1159system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41406412500 # number of ReadExReq MSHR miss cycles 1160system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8750287500 # number of ReadCleanReq MSHR miss cycles 1161system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8750287500 # number of ReadCleanReq MSHR miss cycles 1162system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28049107014 # number of ReadSharedReq MSHR miss cycles 1163system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28049107014 # number of ReadSharedReq MSHR miss cycles 1164system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 32589969500 # number of InvalidateReq MSHR miss cycles 1165system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 32589969500 # number of InvalidateReq MSHR miss cycles 1166system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 307805500 # number of demand (read+write) MSHR miss cycles 1167system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 320988500 # number of demand (read+write) MSHR miss cycles 1168system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8750287500 # number of demand (read+write) MSHR miss cycles 1169system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69455519514 # number of demand (read+write) MSHR miss cycles 1170system.cpu.l2cache.demand_mshr_miss_latency::total 78834601014 # number of demand (read+write) MSHR miss cycles 1171system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 307805500 # number of overall MSHR miss cycles 1172system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 320988500 # number of overall MSHR miss cycles 1173system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8750287500 # number of overall MSHR miss cycles 1174system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69455519514 # number of overall MSHR miss cycles 1175system.cpu.l2cache.overall_mshr_miss_latency::total 78834601014 # number of overall MSHR miss cycles 1176system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles 1177system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777601500 # number of ReadReq MSHR uncacheable cycles 1178system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675326000 # number of ReadReq MSHR uncacheable cycles 1179system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles 1180system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777601500 # number of overall MSHR uncacheable cycles 1181system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675326000 # number of overall MSHR uncacheable cycles 1182system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses 1183system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses 1184system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses 1185system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses 1186system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses 1187system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1188system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1189system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses 1190system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176574 # mshr miss rate for ReadExReq accesses 1191system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for ReadCleanReq accesses 1192system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005359 # mshr miss rate for ReadCleanReq accesses 1193system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036511 # mshr miss rate for ReadSharedReq accesses 1194system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadSharedReq accesses 1195system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394346 # mshr miss rate for InvalidateReq accesses 1196system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394346 # mshr miss rate for InvalidateReq accesses 1197system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for demand accesses 1198system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for demand accesses 1199system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for demand accesses 1200system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for demand accesses 1201system.cpu.l2cache.demand_mshr_miss_rate::total 0.029260 # mshr miss rate for demand accesses 1202system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for overall accesses 1203system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for overall accesses 1204system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for overall accesses 1205system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for overall accesses 1206system.cpu.l2cache.overall_mshr_miss_rate::total 0.029260 # mshr miss rate for overall accesses 1207system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average ReadReq mshr miss latency 1208system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average ReadReq mshr miss latency 1209system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127907.648495 # average ReadReq mshr miss latency 1210system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67931.831155 # average UpgradeReq mshr miss latency 1211system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67931.831155 # average UpgradeReq mshr miss latency 1212system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1213system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1214system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121217.409569 # average ReadExReq mshr miss latency 1215system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121217.409569 # average ReadExReq mshr miss latency 1216system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122484.427492 # average ReadCleanReq mshr miss latency 1217system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122484.427492 # average ReadCleanReq mshr miss latency 1218system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123381.721390 # average ReadSharedReq mshr miss latency 1219system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123381.721390 # average ReadSharedReq mshr miss latency 1220system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67656.435152 # average InvalidateReq mshr miss latency 1221system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67656.435152 # average InvalidateReq mshr miss latency 1222system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency 1223system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency 1224system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency 1225system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency 1226system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency 1227system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency 1228system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency 1229system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency 1230system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency 1231system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency 1232system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency 1233system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency 1234system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency 1235system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency 1236system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency 1237system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency 1238system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter. 1239system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1240system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1241system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. 1242system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1243system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1244system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1245system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution 1246system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution 1247system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution 1248system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution 1249system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution 1250system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution 1251system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution 1252system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution 1253system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1254system.cpu.toL2Bus.trans_dist::UpgradeResp 42346 # Transaction distribution 1255system.cpu.toL2Bus.trans_dist::ReadExReq 1934534 # Transaction distribution 1256system.cpu.toL2Bus.trans_dist::ReadExResp 1934534 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::ReadCleanReq 13331681 # Transaction distribution 1258system.cpu.toL2Bus.trans_dist::ReadSharedReq 6235371 # Transaction distribution 1259system.cpu.toL2Bus.trans_dist::InvalidateReq 1328174 # Transaction distribution 1260system.cpu.toL2Bus.trans_dist::InvalidateResp 1221510 # Transaction distribution 1261system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40080776 # Packet count per connected master and slave (bytes) 1262system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28367342 # Packet count per connected master and slave (bytes) 1263system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601942 # Packet count per connected master and slave (bytes) 1264system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 864211 # Packet count per connected master and slave (bytes) 1265system.cpu.toL2Bus.pkt_count::total 69914271 # Packet count per connected master and slave (bytes) 1266system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1706594580 # Cumulative packet size per connected master and slave (bytes) 1267system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 990623790 # Cumulative packet size per connected master and slave (bytes) 1268system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959056 # Cumulative packet size per connected master and slave (bytes) 1269system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2528832 # Cumulative packet size per connected master and slave (bytes) 1270system.cpu.toL2Bus.pkt_size::total 2701706258 # Cumulative packet size per connected master and slave (bytes) 1271system.cpu.toL2Bus.snoops 1612380 # Total snoops (count) 1272system.cpu.toL2Bus.snoop_fanout::samples 25039605 # Request fanout histogram 1273system.cpu.toL2Bus.snoop_fanout::mean 0.019510 # Request fanout histogram 1274system.cpu.toL2Bus.snoop_fanout::stdev 0.138308 # Request fanout histogram 1275system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1276system.cpu.toL2Bus.snoop_fanout::0 24551092 98.05% 98.05% # Request fanout histogram 1277system.cpu.toL2Bus.snoop_fanout::1 488513 1.95% 100.00% # Request fanout histogram 1278system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1279system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1280system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1281system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1282system.cpu.toL2Bus.snoop_fanout::total 25039605 # Request fanout histogram 1283system.cpu.toL2Bus.reqLayer0.occupancy 43904381000 # Layer occupancy (ticks) 1284system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1285system.cpu.toL2Bus.snoopLayer0.occupancy 1555895 # Layer occupancy (ticks) 1286system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1287system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks) 1288system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1289system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks) 1290system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1291system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks) 1292system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1293system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks) 1294system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1295system.iobus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1296system.iobus.trans_dist::ReadReq 40345 # Transaction distribution 1297system.iobus.trans_dist::ReadResp 40345 # Transaction distribution 1298system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1299system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1300system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1301system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1302system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1303system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1304system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1305system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1306system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1307system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1308system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1309system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1310system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1311system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1312system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1313system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1314system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231048 # Packet count per connected master and slave (bytes) 1315system.iobus.pkt_count_system.realview.ide.dma::total 231048 # Packet count per connected master and slave (bytes) 1316system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1317system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1318system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) 1319system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1320system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1321system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1322system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1323system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1324system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1325system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1326system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1327system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1328system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1329system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1330system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1331system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1332system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1333system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334624 # Cumulative packet size per connected master and slave (bytes) 1334system.iobus.pkt_size_system.realview.ide.dma::total 7334624 # Cumulative packet size per connected master and slave (bytes) 1335system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1336system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1337system.iobus.pkt_size::total 7492544 # Cumulative packet size per connected master and slave (bytes) 1338system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) 1339system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1340system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1341system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1342system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) 1343system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1344system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1345system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1346system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) 1347system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1348system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 1349system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1350system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1351system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1352system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1353system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1354system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1355system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1356system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 1357system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1358system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1359system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1360system.iobus.reqLayer23.occupancy 25723500 # Layer occupancy (ticks) 1361system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1362system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) 1363system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1364system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks) 1365system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1366system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1367system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1368system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks) 1369system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1370system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1371system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1372system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1373system.iocache.tags.replacements 115506 # number of replacements 1374system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use 1375system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1376system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. 1377system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1378system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. 1379system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor 1380system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor 1381system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy 1382system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy 1383system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy 1384system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1385system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1386system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1387system.iocache.tags.tag_accesses 1040073 # Number of tag accesses 1388system.iocache.tags.data_accesses 1040073 # Number of data accesses 1389system.iocache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1390system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1391system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses 1392system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses 1393system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1394system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1395system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1396system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1397system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1398system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses 1399system.iocache.demand_misses::total 115564 # number of demand (read+write) misses 1400system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1401system.iocache.overall_misses::realview.ide 115524 # number of overall misses 1402system.iocache.overall_misses::total 115564 # number of overall misses 1403system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles 1404system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles 1405system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles 1406system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1407system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1408system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles 1409system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles 1410system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles 1411system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles 1412system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles 1413system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles 1414system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles 1415system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles 1416system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1417system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses) 1418system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses) 1419system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1420system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1421system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1422system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1423system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1424system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses 1425system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses 1426system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1427system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses 1428system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses 1429system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1430system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1431system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1432system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1433system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1434system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1435system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1436system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1437system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1438system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1439system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1440system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1441system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1442system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency 1443system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency 1444system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency 1445system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1446system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1447system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency 1448system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency 1449system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1450system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency 1451system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency 1452system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency 1453system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency 1454system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency 1455system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked 1456system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1457system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked 1458system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1459system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked 1460system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1461system.iocache.writebacks::writebacks 106631 # number of writebacks 1462system.iocache.writebacks::total 106631 # number of writebacks 1463system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1464system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses 1465system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses 1466system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1467system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1468system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1469system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1470system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1471system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses 1472system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses 1473system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1474system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses 1475system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses 1476system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles 1477system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles 1478system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles 1479system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1480system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1481system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles 1482system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles 1483system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles 1484system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles 1485system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles 1486system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles 1487system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles 1488system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles 1489system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1490system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1491system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1492system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1493system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1494system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1495system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1496system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1497system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1498system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1499system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1500system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1501system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1502system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency 1503system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency 1504system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency 1505system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1506system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1507system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency 1508system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency 1509system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1510system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency 1511system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency 1512system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency 1513system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency 1514system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency 1515system.membus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1516system.membus.trans_dist::ReadReq 76827 # Transaction distribution 1517system.membus.trans_dist::ReadResp 389416 # Transaction distribution 1518system.membus.trans_dist::WriteReq 33708 # Transaction distribution 1519system.membus.trans_dist::WriteResp 33708 # Transaction distribution 1520system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution 1521system.membus.trans_dist::CleanEvict 164302 # Transaction distribution 1522system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution 1523system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1524system.membus.trans_dist::UpgradeResp 7 # Transaction distribution 1525system.membus.trans_dist::ReadExReq 341030 # Transaction distribution 1526system.membus.trans_dist::ReadExResp 341030 # Transaction distribution 1527system.membus.trans_dist::ReadSharedReq 312589 # Transaction distribution 1528system.membus.trans_dist::InvalidateReq 588355 # Transaction distribution 1529system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1530system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1531system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) 1532system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2930961 # Packet count per connected master and slave (bytes) 1533system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3060653 # Packet count per connected master and slave (bytes) 1534system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237312 # Packet count per connected master and slave (bytes) 1535system.membus.pkt_count_system.iocache.mem_side::total 237312 # Packet count per connected master and slave (bytes) 1536system.membus.pkt_count::total 3297965 # Packet count per connected master and slave (bytes) 1537system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1538system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1539system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) 1540system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97722208 # Cumulative packet size per connected master and slave (bytes) 1541system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97892034 # Cumulative packet size per connected master and slave (bytes) 1542system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7223872 # Cumulative packet size per connected master and slave (bytes) 1543system.membus.pkt_size_system.iocache.mem_side::total 7223872 # Cumulative packet size per connected master and slave (bytes) 1544system.membus.pkt_size::total 105115906 # Cumulative packet size per connected master and slave (bytes) 1545system.membus.snoops 3315 # Total snoops (count) 1546system.membus.snoop_fanout::samples 2537144 # Request fanout histogram 1547system.membus.snoop_fanout::mean 1 # Request fanout histogram 1548system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1549system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1550system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1551system.membus.snoop_fanout::1 2537144 100.00% 100.00% # Request fanout histogram 1552system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1553system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1554system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1555system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1556system.membus.snoop_fanout::total 2537144 # Request fanout histogram 1557system.membus.reqLayer0.occupancy 106903500 # Layer occupancy (ticks) 1558system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1559system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1560system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1561system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks) 1562system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1563system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks) 1564system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1565system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks) 1566system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1567system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks) 1568system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1569system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1570system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1571system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1572system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1573system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1574system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1575system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1576system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1577system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1578system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1579system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1580system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1581system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1582system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1583system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1584system.realview.ethernet.txBytes 966 # Bytes Transmitted 1585system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1586system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1587system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1588system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1589system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1590system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1591system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1592system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1593system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 1594system.realview.ethernet.totPackets 3 # Total Packets 1595system.realview.ethernet.totBytes 966 # Total Bytes 1596system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1597system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 1598system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1599system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1600system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1601system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1602system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1603system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1604system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1605system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1606system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1607system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1608system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1609system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1610system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1611system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1612system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1613system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1614system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1615system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1616system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1617system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1618system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1619system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1620system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1621system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1622system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1623system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1624system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1625system.realview.ethernet.droppedPackets 0 # number of packets dropped 1626system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1627system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1628system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1629system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1630system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1631system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1632system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1633system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1634system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1635system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1636system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1637system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1638system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1639system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1640system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1641system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1642system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1643system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1644system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1645system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1646system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1647system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1648system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states 1649 1650---------- End Simulation Statistics ----------