Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.824462 # Number of seconds simulated
4sim_ticks 51824462100500 # Number of ticks simulated
5final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 723017 # Simulator instruction rate (inst/s)
8host_op_rate 849578 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 41937024652 # Simulator tick rate (ticks/s)
10host_mem_usage 712044 # Number of bytes of host memory used
11host_seconds 1235.77 # Real time elapsed on the host

7host_inst_rate 684695 # Simulator instruction rate (inst/s)
8host_op_rate 804548 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 39714246392 # Simulator tick rate (ticks/s)
10host_mem_usage 713112 # Number of bytes of host memory used
11host_seconds 1304.93 # Real time elapsed on the host

12sim_insts 893481288 # Number of instructions simulated
13sim_ops 1049881338 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory
21system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
26system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory
27system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory
31system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 923811 # Number of read requests accepted
55system.physmem.writeReqs 1833124 # Number of write requests accepted
56system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue
60system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 57129 # Per bank write bursts
67system.physmem.perBankRdBursts::1 60965 # Per bank write bursts
68system.physmem.perBankRdBursts::2 52485 # Per bank write bursts
69system.physmem.perBankRdBursts::3 50413 # Per bank write bursts
70system.physmem.perBankRdBursts::4 54002 # Per bank write bursts
71system.physmem.perBankRdBursts::5 59718 # Per bank write bursts
72system.physmem.perBankRdBursts::6 51713 # Per bank write bursts
73system.physmem.perBankRdBursts::7 51669 # Per bank write bursts
74system.physmem.perBankRdBursts::8 50247 # Per bank write bursts
75system.physmem.perBankRdBursts::9 101235 # Per bank write bursts
76system.physmem.perBankRdBursts::10 59848 # Per bank write bursts
77system.physmem.perBankRdBursts::11 58323 # Per bank write bursts
78system.physmem.perBankRdBursts::12 55369 # Per bank write bursts
79system.physmem.perBankRdBursts::13 55988 # Per bank write bursts
80system.physmem.perBankRdBursts::14 51743 # Per bank write bursts
81system.physmem.perBankRdBursts::15 52477 # Per bank write bursts
82system.physmem.perBankWrBursts::0 110630 # Per bank write bursts
83system.physmem.perBankWrBursts::1 112240 # Per bank write bursts
84system.physmem.perBankWrBursts::2 108805 # Per bank write bursts
85system.physmem.perBankWrBursts::3 108103 # Per bank write bursts
86system.physmem.perBankWrBursts::4 111102 # Per bank write bursts
87system.physmem.perBankWrBursts::5 113339 # Per bank write bursts
88system.physmem.perBankWrBursts::6 105567 # Per bank write bursts
89system.physmem.perBankWrBursts::7 107723 # Per bank write bursts
90system.physmem.perBankWrBursts::8 108849 # Per bank write bursts
91system.physmem.perBankWrBursts::9 115780 # Per bank write bursts
92system.physmem.perBankWrBursts::10 115663 # Per bank write bursts
93system.physmem.perBankWrBursts::11 113049 # Per bank write bursts
94system.physmem.perBankWrBursts::12 112494 # Per bank write bursts
95system.physmem.perBankWrBursts::13 116984 # Per bank write bursts
96system.physmem.perBankWrBursts::14 111502 # Per bank write bursts
97system.physmem.perBankWrBursts::15 110389 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 145 # Number of times write queue was full causing retry
100system.physmem.totGap 51824459475500 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 43101 # Read request sizes (log2)
104system.physmem.readPktSize::3 13 # Read request sizes (log2)
105system.physmem.readPktSize::4 2 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 880695 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 1 # Write request sizes (log2)
111system.physmem.writePktSize::3 2572 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 1830551 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 93369 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 92986 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 93402 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 96397 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads
272system.physmem.totQLat 12043609520 # Total ticks spent queuing
273system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM
274system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers
275system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst
276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
277system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst
278system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s
279system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s
280system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
281system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s
282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
283system.physmem.busUtil 0.03 # Data bus utilization in percentage
284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
285system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
286system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
287system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing
288system.physmem.readRowHits 694872 # Number of row buffer hits during reads
289system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes
290system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads
291system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes
292system.physmem.avgGap 18797853.22 # Average gap between requests
293system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined
294system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ)
295system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ)
296system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ)
297system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ)
298system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
299system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ)
300system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ)
301system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ)
302system.physmem_0.averagePower 668.655841 # Core power per rank (mW)
303system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states
304system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states
305system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
306system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states
307system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
308system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ)
309system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ)
310system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ)
311system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ)
312system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
313system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ)
314system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ)
315system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ)
316system.physmem_1.averagePower 668.672178 # Core power per rank (mW)
317system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states
318system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states
319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
320system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states
321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
322system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
323system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
324system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
325system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
326system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
327system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
328system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
329system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
330system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
331system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
332system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
333system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
334system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
335system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
336system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
337system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
338system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
339system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
340system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
341system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
342system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
343system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
344system.cpu_clk_domain.clock 500 # Clock period in ticks
345system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
353system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
354system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
355system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
356system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
357system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
358system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
359system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
360system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
361system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
362system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
363system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
364system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
365system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
366system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
367system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
368system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
369system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
370system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
371system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
372system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
373system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
374system.cpu.dtb.walker.walks 211321 # Table walker walks requested
375system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors
376system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate
377system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate
378system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting
379system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency
380system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency
381system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency
382system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency
383system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
384system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
385system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency
386system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency
387system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency
388system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency
389system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency
390system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency
391system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency
392system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency
393system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency
394system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency
395system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency
396system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
397system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
398system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
399system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency
400system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution
401system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution
402system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution
403system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution
404system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution
405system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated
406system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated
407system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated
408system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst
409system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
410system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst
411system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst
412system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
413system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst
414system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst
415system.cpu.dtb.inst_hits 0 # ITB inst hits
416system.cpu.dtb.inst_misses 0 # ITB inst misses
417system.cpu.dtb.read_hits 167775531 # DTB read hits
418system.cpu.dtb.read_misses 155743 # DTB read misses
419system.cpu.dtb.write_hits 152648275 # DTB write hits
420system.cpu.dtb.write_misses 55578 # DTB write misses
421system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
422system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
423system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
424system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
425system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB
426system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
427system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch
428system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
429system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions
430system.cpu.dtb.read_accesses 167931274 # DTB read accesses
431system.cpu.dtb.write_accesses 152703853 # DTB write accesses
432system.cpu.dtb.inst_accesses 0 # ITB inst accesses
433system.cpu.dtb.hits 320423806 # DTB hits
434system.cpu.dtb.misses 211321 # DTB misses
435system.cpu.dtb.accesses 320635127 # DTB accesses
436system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
437system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
438system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
444system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
445system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
446system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
447system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
448system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
449system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
450system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
451system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
452system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
453system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
454system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
455system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
456system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
457system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
458system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
459system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
460system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
461system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
462system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
463system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
464system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
465system.cpu.itb.walker.walks 122916 # Table walker walks requested
466system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors
467system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
468system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate
469system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency
470system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency
471system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency
472system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency
473system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency
474system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency
475system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency
476system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency
477system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency
478system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency
479system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency
480system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency
481system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency
482system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency
483system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency
484system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency
485system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency
486system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency
487system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency
488system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
489system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
490system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
491system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
492system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency
493system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution
494system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution
495system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution
496system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated
497system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated
498system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated
499system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
500system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst
501system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst
502system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
503system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst
504system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst
505system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst
506system.cpu.itb.inst_hits 894030670 # ITB inst hits
507system.cpu.itb.inst_misses 122916 # ITB inst misses
508system.cpu.itb.read_hits 0 # DTB read hits
509system.cpu.itb.read_misses 0 # DTB read misses
510system.cpu.itb.write_hits 0 # DTB write hits
511system.cpu.itb.write_misses 0 # DTB write misses
512system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
513system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
514system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
515system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
516system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB
517system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
518system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
519system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
520system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
521system.cpu.itb.read_accesses 0 # DTB read accesses
522system.cpu.itb.write_accesses 0 # DTB write accesses
523system.cpu.itb.inst_accesses 894153586 # ITB inst accesses
524system.cpu.itb.hits 894030670 # DTB hits
525system.cpu.itb.misses 122916 # DTB misses
526system.cpu.itb.accesses 894153586 # DTB accesses
527system.cpu.numCycles 103648924201 # number of cpu cycles simulated
528system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
529system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
530system.cpu.committedInsts 893481288 # Number of instructions committed
531system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed
532system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses
533system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses
534system.cpu.num_func_calls 52999943 # number of times a function call or return occured
535system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls
536system.cpu.num_int_insts 963989017 # number of integer instructions
537system.cpu.num_fp_insts 895873 # number of float instructions
538system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read
539system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written
540system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read
541system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written
542system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read
543system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written
544system.cpu.num_mem_refs 320407593 # number of memory refs
545system.cpu.num_load_insts 167768846 # Number of load instructions
546system.cpu.num_store_insts 152638747 # Number of store instructions
547system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles
548system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles
549system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles
550system.cpu.idle_fraction 0.969376 # Percentage of idle cycles
551system.cpu.Branches 199584978 # Number of branches fetched
552system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
553system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction
554system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction
555system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction
556system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction
557system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction
558system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction
559system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction
560system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction
561system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
562system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
563system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
564system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
565system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
566system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
567system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
568system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
569system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
570system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
571system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
572system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
573system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction
574system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
575system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction
576system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction
577system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
578system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction
579system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
580system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
581system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
582system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction
583system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction
584system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
585system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
586system.cpu.op_class::total 1050473844 # Class of executed instruction
587system.cpu.kern.inst.arm 0 # number of arm instructions executed
588system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed
589system.cpu.dcache.tags.replacements 10213653 # number of replacements
590system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use
591system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks.
592system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks.
593system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks.
594system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit.
595system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor
596system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy
597system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy
598system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
599system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
600system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id
601system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
602system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
603system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
604system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses
605system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses
606system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits
607system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits
608system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits
609system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits
610system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits
611system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits
612system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits
613system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits
614system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits
615system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits
616system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits
617system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits
618system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits
619system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits
620system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits
621system.cpu.dcache.overall_hits::total 301988446 # number of overall hits
622system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses
623system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses
624system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses
625system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses
626system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses
627system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses
628system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses
629system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses
630system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses
631system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses
632system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
633system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
634system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses
635system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses
636system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses
637system.cpu.dcache.overall_misses::total 8832117 # number of overall misses
638system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles
639system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles
640system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles
641system.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles
642system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles
643system.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles
644system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles
645system.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles
646system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
647system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
648system.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles
649system.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles
650system.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles
651system.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles
652system.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses)
653system.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses)
654system.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses)
655system.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses)
656system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses)
657system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses)
658system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses)
659system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses)
660system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses)
661system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses)
662system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses)
663system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses)
664system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses
665system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses
666system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses
667system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses
668system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses
669system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses
670system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses
671system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses
672system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses
673system.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses
674system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses
675system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses
676system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses
677system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses
678system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
679system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
680system.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses
681system.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses
682system.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses
683system.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses
684system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency
685system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency
686system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency
687system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency
688system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency
689system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency
690system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency
691system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency
692system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
693system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
694system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency
695system.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency
696system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency
697system.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency
698system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
699system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
700system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
701system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
702system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
703system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
704system.cpu.dcache.fast_writes 0 # number of fast writes performed
705system.cpu.dcache.cache_copies 0 # number of cache copies performed
706system.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks
707system.cpu.dcache.writebacks::total 7878976 # number of writebacks
708system.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits
709system.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits
710system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits
711system.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits
712system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70685 # number of LoadLockedReq MSHR hits
713system.cpu.dcache.LoadLockedReq_mshr_hits::total 70685 # number of LoadLockedReq MSHR hits
714system.cpu.dcache.demand_mshr_hits::cpu.data 37134 # number of demand (read+write) MSHR hits
715system.cpu.dcache.demand_mshr_hits::total 37134 # number of demand (read+write) MSHR hits
716system.cpu.dcache.overall_mshr_hits::cpu.data 37134 # number of overall MSHR hits
717system.cpu.dcache.overall_mshr_hits::total 37134 # number of overall MSHR hits
718system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5299807 # number of ReadReq MSHR misses
719system.cpu.dcache.ReadReq_mshr_misses::total 5299807 # number of ReadReq MSHR misses
720system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2197927 # number of WriteReq MSHR misses
721system.cpu.dcache.WriteReq_mshr_misses::total 2197927 # number of WriteReq MSHR misses
722system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1295520 # number of SoftPFReq MSHR misses
723system.cpu.dcache.SoftPFReq_mshr_misses::total 1295520 # number of SoftPFReq MSHR misses
724system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232796 # number of WriteInvalidateReq MSHR misses
725system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232796 # number of WriteInvalidateReq MSHR misses
726system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses
727system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses
728system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
729system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
730system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses
731system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses
732system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses
733system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses

734system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
735system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable
736system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
737system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
738system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
739system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses

734system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles
735system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles
736system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles
737system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles
738system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles
739system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles
740system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles
741system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles
742system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles
743system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles
744system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles
745system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles
746system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles
747system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles
748system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles
749system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles
750system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles
751system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles
752system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles
753system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles
754system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles
755system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles
756system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses
757system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses
758system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses
759system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses
760system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses
761system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses
762system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses
763system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses
764system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses
765system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses
766system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
767system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
768system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses
769system.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses
770system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses
771system.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses
772system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency
773system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency
774system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency
775system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency
776system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency
777system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency
778system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency
779system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency
780system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency
781system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency
782system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency
783system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
784system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency
785system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency
786system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency
787system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency

740system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles
741system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles
742system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles
743system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles
744system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles
745system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles
746system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles
747system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles
748system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles
749system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles
750system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles
751system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles
752system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles
753system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles
754system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles
755system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles
756system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles
757system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles
758system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles
759system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles
760system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles
761system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles
762system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses
763system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses
764system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses
765system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses
766system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses
767system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses
768system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses
769system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses
770system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses
771system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses
772system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
773system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
774system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses
775system.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses
776system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses
777system.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses
778system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency
779system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency
780system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency
781system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency
782system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency
783system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency
784system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency
785system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency
786system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency
787system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency
788system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency
789system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
790system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency
791system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency
792system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency
793system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency

788system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
789system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
790system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
791system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
792system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
793system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

794system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177 # average ReadReq mshr uncacheable latency
795system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177 # average ReadReq mshr uncacheable latency
796system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056 # average WriteReq mshr uncacheable latency
797system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056 # average WriteReq mshr uncacheable latency
798system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813 # average overall mshr uncacheable latency
799system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813 # average overall mshr uncacheable latency

794system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
795system.cpu.icache.tags.replacements 13753173 # number of replacements
796system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use
797system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks.
798system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks.
799system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks.
800system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit.
801system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor
802system.cpu.icache.tags.occ_percent::cpu.inst 0.999766 # Average percentage of cache occupancy
803system.cpu.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy
804system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
805system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
806system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
807system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
808system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
809system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
810system.cpu.icache.tags.tag_accesses 907784360 # Number of tag accesses
811system.cpu.icache.tags.data_accesses 907784360 # Number of data accesses
812system.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits
813system.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits
814system.cpu.icache.demand_hits::cpu.inst 880276980 # number of demand (read+write) hits
815system.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits
816system.cpu.icache.overall_hits::cpu.inst 880276980 # number of overall hits
817system.cpu.icache.overall_hits::total 880276980 # number of overall hits
818system.cpu.icache.ReadReq_misses::cpu.inst 13753690 # number of ReadReq misses
819system.cpu.icache.ReadReq_misses::total 13753690 # number of ReadReq misses
820system.cpu.icache.demand_misses::cpu.inst 13753690 # number of demand (read+write) misses
821system.cpu.icache.demand_misses::total 13753690 # number of demand (read+write) misses
822system.cpu.icache.overall_misses::cpu.inst 13753690 # number of overall misses
823system.cpu.icache.overall_misses::total 13753690 # number of overall misses
824system.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183 # number of ReadReq miss cycles
825system.cpu.icache.ReadReq_miss_latency::total 184520052183 # number of ReadReq miss cycles
826system.cpu.icache.demand_miss_latency::cpu.inst 184520052183 # number of demand (read+write) miss cycles
827system.cpu.icache.demand_miss_latency::total 184520052183 # number of demand (read+write) miss cycles
828system.cpu.icache.overall_miss_latency::cpu.inst 184520052183 # number of overall miss cycles
829system.cpu.icache.overall_miss_latency::total 184520052183 # number of overall miss cycles
830system.cpu.icache.ReadReq_accesses::cpu.inst 894030670 # number of ReadReq accesses(hits+misses)
831system.cpu.icache.ReadReq_accesses::total 894030670 # number of ReadReq accesses(hits+misses)
832system.cpu.icache.demand_accesses::cpu.inst 894030670 # number of demand (read+write) accesses
833system.cpu.icache.demand_accesses::total 894030670 # number of demand (read+write) accesses
834system.cpu.icache.overall_accesses::cpu.inst 894030670 # number of overall (read+write) accesses
835system.cpu.icache.overall_accesses::total 894030670 # number of overall (read+write) accesses
836system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015384 # miss rate for ReadReq accesses
837system.cpu.icache.ReadReq_miss_rate::total 0.015384 # miss rate for ReadReq accesses
838system.cpu.icache.demand_miss_rate::cpu.inst 0.015384 # miss rate for demand accesses
839system.cpu.icache.demand_miss_rate::total 0.015384 # miss rate for demand accesses
840system.cpu.icache.overall_miss_rate::cpu.inst 0.015384 # miss rate for overall accesses
841system.cpu.icache.overall_miss_rate::total 0.015384 # miss rate for overall accesses
842system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13416.039782 # average ReadReq miss latency
843system.cpu.icache.ReadReq_avg_miss_latency::total 13416.039782 # average ReadReq miss latency
844system.cpu.icache.demand_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency
845system.cpu.icache.demand_avg_miss_latency::total 13416.039782 # average overall miss latency
846system.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency
847system.cpu.icache.overall_avg_miss_latency::total 13416.039782 # average overall miss latency
848system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
849system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
850system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
851system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
852system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
853system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
854system.cpu.icache.fast_writes 0 # number of fast writes performed
855system.cpu.icache.cache_copies 0 # number of cache copies performed
856system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13753690 # number of ReadReq MSHR misses
857system.cpu.icache.ReadReq_mshr_misses::total 13753690 # number of ReadReq MSHR misses
858system.cpu.icache.demand_mshr_misses::cpu.inst 13753690 # number of demand (read+write) MSHR misses
859system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses
860system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses
861system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses

800system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
801system.cpu.icache.tags.replacements 13753173 # number of replacements
802system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use
803system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks.
804system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks.
805system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks.
806system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit.
807system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor
808system.cpu.icache.tags.occ_percent::cpu.inst 0.999766 # Average percentage of cache occupancy
809system.cpu.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy
810system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
811system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
812system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
813system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
814system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
815system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
816system.cpu.icache.tags.tag_accesses 907784360 # Number of tag accesses
817system.cpu.icache.tags.data_accesses 907784360 # Number of data accesses
818system.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits
819system.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits
820system.cpu.icache.demand_hits::cpu.inst 880276980 # number of demand (read+write) hits
821system.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits
822system.cpu.icache.overall_hits::cpu.inst 880276980 # number of overall hits
823system.cpu.icache.overall_hits::total 880276980 # number of overall hits
824system.cpu.icache.ReadReq_misses::cpu.inst 13753690 # number of ReadReq misses
825system.cpu.icache.ReadReq_misses::total 13753690 # number of ReadReq misses
826system.cpu.icache.demand_misses::cpu.inst 13753690 # number of demand (read+write) misses
827system.cpu.icache.demand_misses::total 13753690 # number of demand (read+write) misses
828system.cpu.icache.overall_misses::cpu.inst 13753690 # number of overall misses
829system.cpu.icache.overall_misses::total 13753690 # number of overall misses
830system.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183 # number of ReadReq miss cycles
831system.cpu.icache.ReadReq_miss_latency::total 184520052183 # number of ReadReq miss cycles
832system.cpu.icache.demand_miss_latency::cpu.inst 184520052183 # number of demand (read+write) miss cycles
833system.cpu.icache.demand_miss_latency::total 184520052183 # number of demand (read+write) miss cycles
834system.cpu.icache.overall_miss_latency::cpu.inst 184520052183 # number of overall miss cycles
835system.cpu.icache.overall_miss_latency::total 184520052183 # number of overall miss cycles
836system.cpu.icache.ReadReq_accesses::cpu.inst 894030670 # number of ReadReq accesses(hits+misses)
837system.cpu.icache.ReadReq_accesses::total 894030670 # number of ReadReq accesses(hits+misses)
838system.cpu.icache.demand_accesses::cpu.inst 894030670 # number of demand (read+write) accesses
839system.cpu.icache.demand_accesses::total 894030670 # number of demand (read+write) accesses
840system.cpu.icache.overall_accesses::cpu.inst 894030670 # number of overall (read+write) accesses
841system.cpu.icache.overall_accesses::total 894030670 # number of overall (read+write) accesses
842system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015384 # miss rate for ReadReq accesses
843system.cpu.icache.ReadReq_miss_rate::total 0.015384 # miss rate for ReadReq accesses
844system.cpu.icache.demand_miss_rate::cpu.inst 0.015384 # miss rate for demand accesses
845system.cpu.icache.demand_miss_rate::total 0.015384 # miss rate for demand accesses
846system.cpu.icache.overall_miss_rate::cpu.inst 0.015384 # miss rate for overall accesses
847system.cpu.icache.overall_miss_rate::total 0.015384 # miss rate for overall accesses
848system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13416.039782 # average ReadReq miss latency
849system.cpu.icache.ReadReq_avg_miss_latency::total 13416.039782 # average ReadReq miss latency
850system.cpu.icache.demand_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency
851system.cpu.icache.demand_avg_miss_latency::total 13416.039782 # average overall miss latency
852system.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency
853system.cpu.icache.overall_avg_miss_latency::total 13416.039782 # average overall miss latency
854system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
855system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
856system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
857system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
858system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
859system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
860system.cpu.icache.fast_writes 0 # number of fast writes performed
861system.cpu.icache.cache_copies 0 # number of cache copies performed
862system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13753690 # number of ReadReq MSHR misses
863system.cpu.icache.ReadReq_mshr_misses::total 13753690 # number of ReadReq MSHR misses
864system.cpu.icache.demand_mshr_misses::cpu.inst 13753690 # number of demand (read+write) MSHR misses
865system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses
866system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses
867system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses

868system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
869system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
870system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
871system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses

862system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles
863system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles
864system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles
865system.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles
866system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles
867system.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles
868system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles
869system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles
870system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3211087000 # number of overall MSHR uncacheable cycles
871system.cpu.icache.overall_mshr_uncacheable_latency::total 3211087000 # number of overall MSHR uncacheable cycles
872system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for ReadReq accesses
873system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015384 # mshr miss rate for ReadReq accesses
874system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for demand accesses
875system.cpu.icache.demand_mshr_miss_rate::total 0.015384 # mshr miss rate for demand accesses
876system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses
877system.cpu.icache.overall_mshr_miss_rate::total 0.015384 # mshr miss rate for overall accesses
878system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367 # average ReadReq mshr miss latency
879system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367 # average ReadReq mshr miss latency
880system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency
881system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency
882system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency
883system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency

872system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles
873system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles
874system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles
875system.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles
876system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles
877system.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles
878system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles
879system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles
880system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3211087000 # number of overall MSHR uncacheable cycles
881system.cpu.icache.overall_mshr_uncacheable_latency::total 3211087000 # number of overall MSHR uncacheable cycles
882system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for ReadReq accesses
883system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015384 # mshr miss rate for ReadReq accesses
884system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for demand accesses
885system.cpu.icache.demand_mshr_miss_rate::total 0.015384 # mshr miss rate for demand accesses
886system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses
887system.cpu.icache.overall_mshr_miss_rate::total 0.015384 # mshr miss rate for overall accesses
888system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367 # average ReadReq mshr miss latency
889system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367 # average ReadReq mshr miss latency
890system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency
891system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency
892system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency
893system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency

884system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
885system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
886system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
887system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

894system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average ReadReq mshr uncacheable latency
895system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74459.988406 # average ReadReq mshr uncacheable latency
896system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average overall mshr uncacheable latency
897system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74459.988406 # average overall mshr uncacheable latency

888system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
889system.cpu.l2cache.tags.replacements 1292250 # number of replacements
890system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use
891system.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks.
892system.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks.
893system.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks.
894system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit.
895system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor
896system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 308.197317 # Average occupied blocks per requestor
897system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.773838 # Average occupied blocks per requestor
898system.cpu.l2cache.tags.occ_blocks::cpu.inst 6468.758735 # Average occupied blocks per requestor
899system.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576 # Average occupied blocks per requestor
900system.cpu.l2cache.tags.occ_percent::writebacks 0.585064 # Average percentage of cache occupancy
901system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004703 # Average percentage of cache occupancy
902system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006420 # Average percentage of cache occupancy
903system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098705 # Average percentage of cache occupancy
904system.cpu.l2cache.tags.occ_percent::cpu.data 0.301380 # Average percentage of cache occupancy
905system.cpu.l2cache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy
906system.cpu.l2cache.tags.occ_task_id_blocks::1023 297 # Occupied blocks per task id
907system.cpu.l2cache.tags.occ_task_id_blocks::1024 62733 # Occupied blocks per task id
908system.cpu.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
909system.cpu.l2cache.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id
910system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
911system.cpu.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
912system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2458 # Occupied blocks per task id
913system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id
914system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54401 # Occupied blocks per task id
915system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004532 # Percentage of cache occupancy per task id
916system.cpu.l2cache.tags.occ_task_id_percent::1024 0.957230 # Percentage of cache occupancy per task id
917system.cpu.l2cache.tags.tag_accesses 264471216 # Number of tag accesses
918system.cpu.l2cache.tags.data_accesses 264471216 # Number of data accesses
919system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 371629 # number of ReadReq hits
920system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250715 # number of ReadReq hits
921system.cpu.l2cache.ReadReq_hits::cpu.inst 13674158 # number of ReadReq hits
922system.cpu.l2cache.ReadReq_hits::cpu.data 6553954 # number of ReadReq hits
923system.cpu.l2cache.ReadReq_hits::total 20850456 # number of ReadReq hits
924system.cpu.l2cache.Writeback_hits::writebacks 7878976 # number of Writeback hits
925system.cpu.l2cache.Writeback_hits::total 7878976 # number of Writeback hits
926system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 723057 # number of WriteInvalidateReq hits
927system.cpu.l2cache.WriteInvalidateReq_hits::total 723057 # number of WriteInvalidateReq hits
928system.cpu.l2cache.UpgradeReq_hits::cpu.data 9863 # number of UpgradeReq hits
929system.cpu.l2cache.UpgradeReq_hits::total 9863 # number of UpgradeReq hits
930system.cpu.l2cache.ReadExReq_hits::cpu.data 1639498 # number of ReadExReq hits
931system.cpu.l2cache.ReadExReq_hits::total 1639498 # number of ReadExReq hits
932system.cpu.l2cache.demand_hits::cpu.dtb.walker 371629 # number of demand (read+write) hits
933system.cpu.l2cache.demand_hits::cpu.itb.walker 250715 # number of demand (read+write) hits
934system.cpu.l2cache.demand_hits::cpu.inst 13674158 # number of demand (read+write) hits
935system.cpu.l2cache.demand_hits::cpu.data 8193452 # number of demand (read+write) hits
936system.cpu.l2cache.demand_hits::total 22489954 # number of demand (read+write) hits
937system.cpu.l2cache.overall_hits::cpu.dtb.walker 371629 # number of overall hits
938system.cpu.l2cache.overall_hits::cpu.itb.walker 250715 # number of overall hits
939system.cpu.l2cache.overall_hits::cpu.inst 13674158 # number of overall hits
940system.cpu.l2cache.overall_hits::cpu.data 8193452 # number of overall hits
941system.cpu.l2cache.overall_hits::total 22489954 # number of overall hits
942system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4157 # number of ReadReq misses
943system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4054 # number of ReadReq misses
944system.cpu.l2cache.ReadReq_misses::cpu.inst 79532 # number of ReadReq misses
945system.cpu.l2cache.ReadReq_misses::cpu.data 275030 # number of ReadReq misses
946system.cpu.l2cache.ReadReq_misses::total 362773 # number of ReadReq misses
947system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509738 # number of WriteInvalidateReq misses
948system.cpu.l2cache.WriteInvalidateReq_misses::total 509738 # number of WriteInvalidateReq misses
949system.cpu.l2cache.UpgradeReq_misses::cpu.data 35651 # number of UpgradeReq misses
950system.cpu.l2cache.UpgradeReq_misses::total 35651 # number of UpgradeReq misses
951system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
952system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
953system.cpu.l2cache.ReadExReq_misses::cpu.data 512916 # number of ReadExReq misses
954system.cpu.l2cache.ReadExReq_misses::total 512916 # number of ReadExReq misses
955system.cpu.l2cache.demand_misses::cpu.dtb.walker 4157 # number of demand (read+write) misses
956system.cpu.l2cache.demand_misses::cpu.itb.walker 4054 # number of demand (read+write) misses
957system.cpu.l2cache.demand_misses::cpu.inst 79532 # number of demand (read+write) misses
958system.cpu.l2cache.demand_misses::cpu.data 787946 # number of demand (read+write) misses
959system.cpu.l2cache.demand_misses::total 875689 # number of demand (read+write) misses
960system.cpu.l2cache.overall_misses::cpu.dtb.walker 4157 # number of overall misses
961system.cpu.l2cache.overall_misses::cpu.itb.walker 4054 # number of overall misses
962system.cpu.l2cache.overall_misses::cpu.inst 79532 # number of overall misses
963system.cpu.l2cache.overall_misses::cpu.data 787946 # number of overall misses
964system.cpu.l2cache.overall_misses::total 875689 # number of overall misses
965system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 357827500 # number of ReadReq miss cycles
966system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 356872250 # number of ReadReq miss cycles
967system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6528298780 # number of ReadReq miss cycles
968system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22994549799 # number of ReadReq miss cycles
969system.cpu.l2cache.ReadReq_miss_latency::total 30237548329 # number of ReadReq miss cycles
970system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 123996 # number of WriteInvalidateReq miss cycles
971system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 123996 # number of WriteInvalidateReq miss cycles
972system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 554901623 # number of UpgradeReq miss cycles
973system.cpu.l2cache.UpgradeReq_miss_latency::total 554901623 # number of UpgradeReq miss cycles
974system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
975system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
976system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41601774937 # number of ReadExReq miss cycles
977system.cpu.l2cache.ReadExReq_miss_latency::total 41601774937 # number of ReadExReq miss cycles
978system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 357827500 # number of demand (read+write) miss cycles
979system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 356872250 # number of demand (read+write) miss cycles
980system.cpu.l2cache.demand_miss_latency::cpu.inst 6528298780 # number of demand (read+write) miss cycles
981system.cpu.l2cache.demand_miss_latency::cpu.data 64596324736 # number of demand (read+write) miss cycles
982system.cpu.l2cache.demand_miss_latency::total 71839323266 # number of demand (read+write) miss cycles
983system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 357827500 # number of overall miss cycles
984system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 356872250 # number of overall miss cycles
985system.cpu.l2cache.overall_miss_latency::cpu.inst 6528298780 # number of overall miss cycles
986system.cpu.l2cache.overall_miss_latency::cpu.data 64596324736 # number of overall miss cycles
987system.cpu.l2cache.overall_miss_latency::total 71839323266 # number of overall miss cycles
988system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 375786 # number of ReadReq accesses(hits+misses)
989system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 254769 # number of ReadReq accesses(hits+misses)
990system.cpu.l2cache.ReadReq_accesses::cpu.inst 13753690 # number of ReadReq accesses(hits+misses)
991system.cpu.l2cache.ReadReq_accesses::cpu.data 6828984 # number of ReadReq accesses(hits+misses)
992system.cpu.l2cache.ReadReq_accesses::total 21213229 # number of ReadReq accesses(hits+misses)
993system.cpu.l2cache.Writeback_accesses::writebacks 7878976 # number of Writeback accesses(hits+misses)
994system.cpu.l2cache.Writeback_accesses::total 7878976 # number of Writeback accesses(hits+misses)
995system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1232795 # number of WriteInvalidateReq accesses(hits+misses)
996system.cpu.l2cache.WriteInvalidateReq_accesses::total 1232795 # number of WriteInvalidateReq accesses(hits+misses)
997system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45514 # number of UpgradeReq accesses(hits+misses)
998system.cpu.l2cache.UpgradeReq_accesses::total 45514 # number of UpgradeReq accesses(hits+misses)
999system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
1000system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
1001system.cpu.l2cache.ReadExReq_accesses::cpu.data 2152414 # number of ReadExReq accesses(hits+misses)
1002system.cpu.l2cache.ReadExReq_accesses::total 2152414 # number of ReadExReq accesses(hits+misses)
1003system.cpu.l2cache.demand_accesses::cpu.dtb.walker 375786 # number of demand (read+write) accesses
1004system.cpu.l2cache.demand_accesses::cpu.itb.walker 254769 # number of demand (read+write) accesses
1005system.cpu.l2cache.demand_accesses::cpu.inst 13753690 # number of demand (read+write) accesses
1006system.cpu.l2cache.demand_accesses::cpu.data 8981398 # number of demand (read+write) accesses
1007system.cpu.l2cache.demand_accesses::total 23365643 # number of demand (read+write) accesses
1008system.cpu.l2cache.overall_accesses::cpu.dtb.walker 375786 # number of overall (read+write) accesses
1009system.cpu.l2cache.overall_accesses::cpu.itb.walker 254769 # number of overall (read+write) accesses
1010system.cpu.l2cache.overall_accesses::cpu.inst 13753690 # number of overall (read+write) accesses
1011system.cpu.l2cache.overall_accesses::cpu.data 8981398 # number of overall (read+write) accesses
1012system.cpu.l2cache.overall_accesses::total 23365643 # number of overall (read+write) accesses
1013system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011062 # miss rate for ReadReq accesses
1014system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015912 # miss rate for ReadReq accesses
1015system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005783 # miss rate for ReadReq accesses
1016system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.040274 # miss rate for ReadReq accesses
1017system.cpu.l2cache.ReadReq_miss_rate::total 0.017101 # miss rate for ReadReq accesses
1018system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.413482 # miss rate for WriteInvalidateReq accesses
1019system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.413482 # miss rate for WriteInvalidateReq accesses
1020system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783297 # miss rate for UpgradeReq accesses
1021system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783297 # miss rate for UpgradeReq accesses
1022system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
1023system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1024system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238298 # miss rate for ReadExReq accesses
1025system.cpu.l2cache.ReadExReq_miss_rate::total 0.238298 # miss rate for ReadExReq accesses
1026system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011062 # miss rate for demand accesses
1027system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015912 # miss rate for demand accesses
1028system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005783 # miss rate for demand accesses
1029system.cpu.l2cache.demand_miss_rate::cpu.data 0.087731 # miss rate for demand accesses
1030system.cpu.l2cache.demand_miss_rate::total 0.037478 # miss rate for demand accesses
1031system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011062 # miss rate for overall accesses
1032system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015912 # miss rate for overall accesses
1033system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005783 # miss rate for overall accesses
1034system.cpu.l2cache.overall_miss_rate::cpu.data 0.087731 # miss rate for overall accesses
1035system.cpu.l2cache.overall_miss_rate::total 0.037478 # miss rate for overall accesses
1036system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86078.301660 # average ReadReq miss latency
1037system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88029.662062 # average ReadReq miss latency
1038system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82083.925715 # average ReadReq miss latency
1039system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83607.423914 # average ReadReq miss latency
1040system.cpu.l2cache.ReadReq_avg_miss_latency::total 83351.154383 # average ReadReq miss latency
1041system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.243254 # average WriteInvalidateReq miss latency
1042system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.243254 # average WriteInvalidateReq miss latency
1043system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15564.826316 # average UpgradeReq miss latency
1044system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15564.826316 # average UpgradeReq miss latency
1045system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
1046system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
1047system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81108.358751 # average ReadExReq miss latency
1048system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81108.358751 # average ReadExReq miss latency
1049system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency
1050system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency
1051system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency
1052system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency
1053system.cpu.l2cache.demand_avg_miss_latency::total 82037.485073 # average overall miss latency
1054system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency
1055system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency
1056system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency
1057system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency
1058system.cpu.l2cache.overall_avg_miss_latency::total 82037.485073 # average overall miss latency
1059system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1060system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1061system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1062system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1063system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1064system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1065system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1066system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1067system.cpu.l2cache.writebacks::writebacks 1107523 # number of writebacks
1068system.cpu.l2cache.writebacks::total 1107523 # number of writebacks
1069system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4157 # number of ReadReq MSHR misses
1070system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4054 # number of ReadReq MSHR misses
1071system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 79532 # number of ReadReq MSHR misses
1072system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 275030 # number of ReadReq MSHR misses
1073system.cpu.l2cache.ReadReq_mshr_misses::total 362773 # number of ReadReq MSHR misses
1074system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 509738 # number of WriteInvalidateReq MSHR misses
1075system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 509738 # number of WriteInvalidateReq MSHR misses
1076system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35651 # number of UpgradeReq MSHR misses
1077system.cpu.l2cache.UpgradeReq_mshr_misses::total 35651 # number of UpgradeReq MSHR misses
1078system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1079system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1080system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 512916 # number of ReadExReq MSHR misses
1081system.cpu.l2cache.ReadExReq_mshr_misses::total 512916 # number of ReadExReq MSHR misses
1082system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4157 # number of demand (read+write) MSHR misses
1083system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4054 # number of demand (read+write) MSHR misses
1084system.cpu.l2cache.demand_mshr_misses::cpu.inst 79532 # number of demand (read+write) MSHR misses
1085system.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses
1086system.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses
1087system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses
1088system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses
1089system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses
1090system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses
1091system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses

898system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
899system.cpu.l2cache.tags.replacements 1292250 # number of replacements
900system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use
901system.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks.
902system.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks.
903system.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks.
904system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit.
905system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor
906system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 308.197317 # Average occupied blocks per requestor
907system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.773838 # Average occupied blocks per requestor
908system.cpu.l2cache.tags.occ_blocks::cpu.inst 6468.758735 # Average occupied blocks per requestor
909system.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576 # Average occupied blocks per requestor
910system.cpu.l2cache.tags.occ_percent::writebacks 0.585064 # Average percentage of cache occupancy
911system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004703 # Average percentage of cache occupancy
912system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006420 # Average percentage of cache occupancy
913system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098705 # Average percentage of cache occupancy
914system.cpu.l2cache.tags.occ_percent::cpu.data 0.301380 # Average percentage of cache occupancy
915system.cpu.l2cache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy
916system.cpu.l2cache.tags.occ_task_id_blocks::1023 297 # Occupied blocks per task id
917system.cpu.l2cache.tags.occ_task_id_blocks::1024 62733 # Occupied blocks per task id
918system.cpu.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
919system.cpu.l2cache.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id
920system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
921system.cpu.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
922system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2458 # Occupied blocks per task id
923system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id
924system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54401 # Occupied blocks per task id
925system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004532 # Percentage of cache occupancy per task id
926system.cpu.l2cache.tags.occ_task_id_percent::1024 0.957230 # Percentage of cache occupancy per task id
927system.cpu.l2cache.tags.tag_accesses 264471216 # Number of tag accesses
928system.cpu.l2cache.tags.data_accesses 264471216 # Number of data accesses
929system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 371629 # number of ReadReq hits
930system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250715 # number of ReadReq hits
931system.cpu.l2cache.ReadReq_hits::cpu.inst 13674158 # number of ReadReq hits
932system.cpu.l2cache.ReadReq_hits::cpu.data 6553954 # number of ReadReq hits
933system.cpu.l2cache.ReadReq_hits::total 20850456 # number of ReadReq hits
934system.cpu.l2cache.Writeback_hits::writebacks 7878976 # number of Writeback hits
935system.cpu.l2cache.Writeback_hits::total 7878976 # number of Writeback hits
936system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 723057 # number of WriteInvalidateReq hits
937system.cpu.l2cache.WriteInvalidateReq_hits::total 723057 # number of WriteInvalidateReq hits
938system.cpu.l2cache.UpgradeReq_hits::cpu.data 9863 # number of UpgradeReq hits
939system.cpu.l2cache.UpgradeReq_hits::total 9863 # number of UpgradeReq hits
940system.cpu.l2cache.ReadExReq_hits::cpu.data 1639498 # number of ReadExReq hits
941system.cpu.l2cache.ReadExReq_hits::total 1639498 # number of ReadExReq hits
942system.cpu.l2cache.demand_hits::cpu.dtb.walker 371629 # number of demand (read+write) hits
943system.cpu.l2cache.demand_hits::cpu.itb.walker 250715 # number of demand (read+write) hits
944system.cpu.l2cache.demand_hits::cpu.inst 13674158 # number of demand (read+write) hits
945system.cpu.l2cache.demand_hits::cpu.data 8193452 # number of demand (read+write) hits
946system.cpu.l2cache.demand_hits::total 22489954 # number of demand (read+write) hits
947system.cpu.l2cache.overall_hits::cpu.dtb.walker 371629 # number of overall hits
948system.cpu.l2cache.overall_hits::cpu.itb.walker 250715 # number of overall hits
949system.cpu.l2cache.overall_hits::cpu.inst 13674158 # number of overall hits
950system.cpu.l2cache.overall_hits::cpu.data 8193452 # number of overall hits
951system.cpu.l2cache.overall_hits::total 22489954 # number of overall hits
952system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4157 # number of ReadReq misses
953system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4054 # number of ReadReq misses
954system.cpu.l2cache.ReadReq_misses::cpu.inst 79532 # number of ReadReq misses
955system.cpu.l2cache.ReadReq_misses::cpu.data 275030 # number of ReadReq misses
956system.cpu.l2cache.ReadReq_misses::total 362773 # number of ReadReq misses
957system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509738 # number of WriteInvalidateReq misses
958system.cpu.l2cache.WriteInvalidateReq_misses::total 509738 # number of WriteInvalidateReq misses
959system.cpu.l2cache.UpgradeReq_misses::cpu.data 35651 # number of UpgradeReq misses
960system.cpu.l2cache.UpgradeReq_misses::total 35651 # number of UpgradeReq misses
961system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
962system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
963system.cpu.l2cache.ReadExReq_misses::cpu.data 512916 # number of ReadExReq misses
964system.cpu.l2cache.ReadExReq_misses::total 512916 # number of ReadExReq misses
965system.cpu.l2cache.demand_misses::cpu.dtb.walker 4157 # number of demand (read+write) misses
966system.cpu.l2cache.demand_misses::cpu.itb.walker 4054 # number of demand (read+write) misses
967system.cpu.l2cache.demand_misses::cpu.inst 79532 # number of demand (read+write) misses
968system.cpu.l2cache.demand_misses::cpu.data 787946 # number of demand (read+write) misses
969system.cpu.l2cache.demand_misses::total 875689 # number of demand (read+write) misses
970system.cpu.l2cache.overall_misses::cpu.dtb.walker 4157 # number of overall misses
971system.cpu.l2cache.overall_misses::cpu.itb.walker 4054 # number of overall misses
972system.cpu.l2cache.overall_misses::cpu.inst 79532 # number of overall misses
973system.cpu.l2cache.overall_misses::cpu.data 787946 # number of overall misses
974system.cpu.l2cache.overall_misses::total 875689 # number of overall misses
975system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 357827500 # number of ReadReq miss cycles
976system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 356872250 # number of ReadReq miss cycles
977system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6528298780 # number of ReadReq miss cycles
978system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22994549799 # number of ReadReq miss cycles
979system.cpu.l2cache.ReadReq_miss_latency::total 30237548329 # number of ReadReq miss cycles
980system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 123996 # number of WriteInvalidateReq miss cycles
981system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 123996 # number of WriteInvalidateReq miss cycles
982system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 554901623 # number of UpgradeReq miss cycles
983system.cpu.l2cache.UpgradeReq_miss_latency::total 554901623 # number of UpgradeReq miss cycles
984system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
985system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
986system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41601774937 # number of ReadExReq miss cycles
987system.cpu.l2cache.ReadExReq_miss_latency::total 41601774937 # number of ReadExReq miss cycles
988system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 357827500 # number of demand (read+write) miss cycles
989system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 356872250 # number of demand (read+write) miss cycles
990system.cpu.l2cache.demand_miss_latency::cpu.inst 6528298780 # number of demand (read+write) miss cycles
991system.cpu.l2cache.demand_miss_latency::cpu.data 64596324736 # number of demand (read+write) miss cycles
992system.cpu.l2cache.demand_miss_latency::total 71839323266 # number of demand (read+write) miss cycles
993system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 357827500 # number of overall miss cycles
994system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 356872250 # number of overall miss cycles
995system.cpu.l2cache.overall_miss_latency::cpu.inst 6528298780 # number of overall miss cycles
996system.cpu.l2cache.overall_miss_latency::cpu.data 64596324736 # number of overall miss cycles
997system.cpu.l2cache.overall_miss_latency::total 71839323266 # number of overall miss cycles
998system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 375786 # number of ReadReq accesses(hits+misses)
999system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 254769 # number of ReadReq accesses(hits+misses)
1000system.cpu.l2cache.ReadReq_accesses::cpu.inst 13753690 # number of ReadReq accesses(hits+misses)
1001system.cpu.l2cache.ReadReq_accesses::cpu.data 6828984 # number of ReadReq accesses(hits+misses)
1002system.cpu.l2cache.ReadReq_accesses::total 21213229 # number of ReadReq accesses(hits+misses)
1003system.cpu.l2cache.Writeback_accesses::writebacks 7878976 # number of Writeback accesses(hits+misses)
1004system.cpu.l2cache.Writeback_accesses::total 7878976 # number of Writeback accesses(hits+misses)
1005system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1232795 # number of WriteInvalidateReq accesses(hits+misses)
1006system.cpu.l2cache.WriteInvalidateReq_accesses::total 1232795 # number of WriteInvalidateReq accesses(hits+misses)
1007system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45514 # number of UpgradeReq accesses(hits+misses)
1008system.cpu.l2cache.UpgradeReq_accesses::total 45514 # number of UpgradeReq accesses(hits+misses)
1009system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
1010system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
1011system.cpu.l2cache.ReadExReq_accesses::cpu.data 2152414 # number of ReadExReq accesses(hits+misses)
1012system.cpu.l2cache.ReadExReq_accesses::total 2152414 # number of ReadExReq accesses(hits+misses)
1013system.cpu.l2cache.demand_accesses::cpu.dtb.walker 375786 # number of demand (read+write) accesses
1014system.cpu.l2cache.demand_accesses::cpu.itb.walker 254769 # number of demand (read+write) accesses
1015system.cpu.l2cache.demand_accesses::cpu.inst 13753690 # number of demand (read+write) accesses
1016system.cpu.l2cache.demand_accesses::cpu.data 8981398 # number of demand (read+write) accesses
1017system.cpu.l2cache.demand_accesses::total 23365643 # number of demand (read+write) accesses
1018system.cpu.l2cache.overall_accesses::cpu.dtb.walker 375786 # number of overall (read+write) accesses
1019system.cpu.l2cache.overall_accesses::cpu.itb.walker 254769 # number of overall (read+write) accesses
1020system.cpu.l2cache.overall_accesses::cpu.inst 13753690 # number of overall (read+write) accesses
1021system.cpu.l2cache.overall_accesses::cpu.data 8981398 # number of overall (read+write) accesses
1022system.cpu.l2cache.overall_accesses::total 23365643 # number of overall (read+write) accesses
1023system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011062 # miss rate for ReadReq accesses
1024system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015912 # miss rate for ReadReq accesses
1025system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005783 # miss rate for ReadReq accesses
1026system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.040274 # miss rate for ReadReq accesses
1027system.cpu.l2cache.ReadReq_miss_rate::total 0.017101 # miss rate for ReadReq accesses
1028system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.413482 # miss rate for WriteInvalidateReq accesses
1029system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.413482 # miss rate for WriteInvalidateReq accesses
1030system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783297 # miss rate for UpgradeReq accesses
1031system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783297 # miss rate for UpgradeReq accesses
1032system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
1033system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1034system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238298 # miss rate for ReadExReq accesses
1035system.cpu.l2cache.ReadExReq_miss_rate::total 0.238298 # miss rate for ReadExReq accesses
1036system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011062 # miss rate for demand accesses
1037system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015912 # miss rate for demand accesses
1038system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005783 # miss rate for demand accesses
1039system.cpu.l2cache.demand_miss_rate::cpu.data 0.087731 # miss rate for demand accesses
1040system.cpu.l2cache.demand_miss_rate::total 0.037478 # miss rate for demand accesses
1041system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011062 # miss rate for overall accesses
1042system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015912 # miss rate for overall accesses
1043system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005783 # miss rate for overall accesses
1044system.cpu.l2cache.overall_miss_rate::cpu.data 0.087731 # miss rate for overall accesses
1045system.cpu.l2cache.overall_miss_rate::total 0.037478 # miss rate for overall accesses
1046system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86078.301660 # average ReadReq miss latency
1047system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88029.662062 # average ReadReq miss latency
1048system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82083.925715 # average ReadReq miss latency
1049system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83607.423914 # average ReadReq miss latency
1050system.cpu.l2cache.ReadReq_avg_miss_latency::total 83351.154383 # average ReadReq miss latency
1051system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.243254 # average WriteInvalidateReq miss latency
1052system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.243254 # average WriteInvalidateReq miss latency
1053system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15564.826316 # average UpgradeReq miss latency
1054system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15564.826316 # average UpgradeReq miss latency
1055system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
1056system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
1057system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81108.358751 # average ReadExReq miss latency
1058system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81108.358751 # average ReadExReq miss latency
1059system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency
1060system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency
1061system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency
1062system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency
1063system.cpu.l2cache.demand_avg_miss_latency::total 82037.485073 # average overall miss latency
1064system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency
1065system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency
1066system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency
1067system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency
1068system.cpu.l2cache.overall_avg_miss_latency::total 82037.485073 # average overall miss latency
1069system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1070system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1071system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1072system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1073system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1074system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1075system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1076system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1077system.cpu.l2cache.writebacks::writebacks 1107523 # number of writebacks
1078system.cpu.l2cache.writebacks::total 1107523 # number of writebacks
1079system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4157 # number of ReadReq MSHR misses
1080system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4054 # number of ReadReq MSHR misses
1081system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 79532 # number of ReadReq MSHR misses
1082system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 275030 # number of ReadReq MSHR misses
1083system.cpu.l2cache.ReadReq_mshr_misses::total 362773 # number of ReadReq MSHR misses
1084system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 509738 # number of WriteInvalidateReq MSHR misses
1085system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 509738 # number of WriteInvalidateReq MSHR misses
1086system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35651 # number of UpgradeReq MSHR misses
1087system.cpu.l2cache.UpgradeReq_mshr_misses::total 35651 # number of UpgradeReq MSHR misses
1088system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1089system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1090system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 512916 # number of ReadExReq MSHR misses
1091system.cpu.l2cache.ReadExReq_mshr_misses::total 512916 # number of ReadExReq MSHR misses
1092system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4157 # number of demand (read+write) MSHR misses
1093system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4054 # number of demand (read+write) MSHR misses
1094system.cpu.l2cache.demand_mshr_misses::cpu.inst 79532 # number of demand (read+write) MSHR misses
1095system.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses
1096system.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses
1097system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses
1098system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses
1099system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses
1100system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses
1101system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses

1102system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
1103system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
1104system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable
1105system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
1106system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
1107system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
1108system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
1109system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses

1092system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles
1093system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles
1094system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles
1095system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles
1096system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles
1097system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles
1098system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles
1099system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles
1100system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 625079648 # number of UpgradeReq MSHR miss cycles
1101system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles
1102system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles
1103system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35188398563 # number of ReadExReq MSHR miss cycles
1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35188398563 # number of ReadExReq MSHR miss cycles
1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 305614500 # number of demand (read+write) MSHR miss cycles
1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 305848750 # number of demand (read+write) MSHR miss cycles
1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5531016720 # number of demand (read+write) MSHR miss cycles
1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54736808264 # number of demand (read+write) MSHR miss cycles
1109system.cpu.l2cache.demand_mshr_miss_latency::total 60879288234 # number of demand (read+write) MSHR miss cycles
1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 305614500 # number of overall MSHR miss cycles
1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 305848750 # number of overall MSHR miss cycles
1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5531016720 # number of overall MSHR miss cycles
1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54736808264 # number of overall MSHR miss cycles
1114system.cpu.l2cache.overall_mshr_miss_latency::total 60879288234 # number of overall MSHR miss cycles
1115system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2585776000 # number of ReadReq MSHR uncacheable cycles
1116system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279091500 # number of ReadReq MSHR uncacheable cycles
1117system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7864867500 # number of ReadReq MSHR uncacheable cycles
1118system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles
1119system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles
1120system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles
1121system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles
1122system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles
1123system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses
1124system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses
1125system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses
1126system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses
1127system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses
1128system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses
1129system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses
1130system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses
1131system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses
1132system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1133system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses
1135system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses
1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses
1137system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses
1138system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses
1139system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses
1140system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses
1141system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses
1142system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses
1143system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses
1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses
1145system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses
1146system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency
1147system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency
1148system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency
1149system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency
1150system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency
1151system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency
1152system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency
1153system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency
1154system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency
1155system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency
1156system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
1157system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency
1158system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency
1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency
1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency
1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
1162system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
1163system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency
1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency
1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
1168system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency

1110system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles
1111system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles
1112system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles
1113system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles
1114system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles
1115system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles
1116system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles
1117system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles
1118system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 625079648 # number of UpgradeReq MSHR miss cycles
1119system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles
1120system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles
1121system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35188398563 # number of ReadExReq MSHR miss cycles
1122system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35188398563 # number of ReadExReq MSHR miss cycles
1123system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 305614500 # number of demand (read+write) MSHR miss cycles
1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 305848750 # number of demand (read+write) MSHR miss cycles
1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5531016720 # number of demand (read+write) MSHR miss cycles
1126system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54736808264 # number of demand (read+write) MSHR miss cycles
1127system.cpu.l2cache.demand_mshr_miss_latency::total 60879288234 # number of demand (read+write) MSHR miss cycles
1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 305614500 # number of overall MSHR miss cycles
1129system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 305848750 # number of overall MSHR miss cycles
1130system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5531016720 # number of overall MSHR miss cycles
1131system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54736808264 # number of overall MSHR miss cycles
1132system.cpu.l2cache.overall_mshr_miss_latency::total 60879288234 # number of overall MSHR miss cycles
1133system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2585776000 # number of ReadReq MSHR uncacheable cycles
1134system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279091500 # number of ReadReq MSHR uncacheable cycles
1135system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7864867500 # number of ReadReq MSHR uncacheable cycles
1136system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles
1137system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles
1138system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles
1139system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles
1140system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles
1141system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses
1142system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses
1143system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses
1144system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses
1145system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses
1146system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses
1147system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses
1148system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses
1149system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses
1150system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1151system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1152system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses
1153system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses
1154system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses
1155system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses
1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses
1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses
1158system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses
1159system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses
1160system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses
1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses
1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses
1163system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses
1164system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency
1165system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency
1166system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency
1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency
1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency
1169system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency
1170system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency
1171system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency
1172system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency
1173system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency
1174system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
1175system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency
1176system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency
1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency
1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency
1179system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
1180system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
1181system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency
1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency
1184system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
1185system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
1186system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency

1169system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1170system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1171system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1172system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1173system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1174system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1175system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1176system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

1187system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average ReadReq mshr uncacheable latency
1188system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235 # average ReadReq mshr uncacheable latency
1189system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374 # average ReadReq mshr uncacheable latency
1190system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131 # average WriteReq mshr uncacheable latency
1191system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131 # average WriteReq mshr uncacheable latency
1192system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average overall mshr uncacheable latency
1193system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508 # average overall mshr uncacheable latency
1194system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603 # average overall mshr uncacheable latency

1177system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1178system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
1179system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
1180system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
1181system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
1182system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution
1183system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution
1184system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution
1185system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution
1186system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1187system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution
1188system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution
1189system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution
1190system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes)
1191system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes)
1192system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes)
1193system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes)
1194system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes)
1195system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes)
1196system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes)
1197system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes)
1198system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
1199system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
1200system.cpu.toL2Bus.snoops 470306 # Total snoops (count)

1195system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1196system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
1197system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
1198system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
1199system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
1200system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution
1201system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution
1202system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution
1203system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution
1204system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1205system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution
1206system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution
1207system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution
1208system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes)
1209system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes)
1210system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes)
1211system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes)
1212system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes)
1213system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes)
1214system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes)
1215system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes)
1216system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
1217system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
1218system.cpu.toL2Bus.snoops 470306 # Total snoops (count)

1201system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram
1202system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram
1203system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram

1219system.cpu.toL2Bus.snoop_fanout::samples 33102923 # Request fanout histogram
1220system.cpu.toL2Bus.snoop_fanout::mean 1.033230 # Request fanout histogram
1221system.cpu.toL2Bus.snoop_fanout::stdev 0.179236 # Request fanout histogram

1204system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1205system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1222system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1223system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1206system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1207system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1208system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram
1209system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram

1224system.cpu.toL2Bus.snoop_fanout::1 32002916 96.68% 96.68% # Request fanout histogram
1225system.cpu.toL2Bus.snoop_fanout::2 1100007 3.32% 100.00% # Request fanout histogram

1210system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1226system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1211system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1212system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1213system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram

1227system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1228system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1229system.cpu.toL2Bus.snoop_fanout::total 33102923 # Request fanout histogram

1214system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
1215system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1216system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
1217system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1218system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks)
1219system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1220system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks)
1221system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1222system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks)
1223system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1224system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks)
1225system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1226system.iobus.trans_dist::ReadReq 40333 # Transaction distribution
1227system.iobus.trans_dist::ReadResp 40333 # Transaction distribution
1228system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1229system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
1230system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
1231system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1232system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1233system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1234system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1235system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1236system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1237system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1238system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1239system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1240system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1241system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1242system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1243system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1244system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1245system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1246system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
1247system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes)
1248system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes)
1249system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1250system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1251system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes)
1252system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1253system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1254system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1255system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1256system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1257system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1258system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1259system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1260system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1261system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1262system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1263system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1264system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1265system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1266system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1267system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
1268system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes)
1269system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes)
1270system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1271system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1272system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes)
1273system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
1274system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1275system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
1276system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1277system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
1278system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1279system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
1280system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1281system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1282system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1283system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1284system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1285system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1286system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1287system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1288system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1289system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1290system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1291system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1292system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1293system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
1294system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1295system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
1296system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1297system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
1298system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1299system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
1300system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1301system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks)
1302system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1303system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1304system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1305system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1306system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1307system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks)
1308system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1309system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
1310system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1311system.iocache.tags.replacements 115493 # number of replacements
1312system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use
1313system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1314system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks.
1315system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1316system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit.
1317system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor
1318system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor
1319system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy
1320system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy
1321system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy
1322system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1323system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1324system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1325system.iocache.tags.tag_accesses 1039965 # Number of tag accesses
1326system.iocache.tags.data_accesses 1039965 # Number of data accesses
1327system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1328system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses
1329system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses
1330system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1331system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1332system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
1333system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
1334system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1335system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses
1336system.iocache.demand_misses::total 8888 # number of demand (read+write) misses
1337system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1338system.iocache.overall_misses::realview.ide 8848 # number of overall misses
1339system.iocache.overall_misses::total 8888 # number of overall misses
1340system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
1341system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles
1342system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles
1343system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
1344system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
1345system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles
1346system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles
1347system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
1348system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles
1349system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles
1350system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
1351system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles
1352system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles
1353system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1354system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses)
1355system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses)
1356system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1357system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1358system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
1359system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
1360system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1361system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses
1362system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses
1363system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1364system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses
1365system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses
1366system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1367system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1368system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1369system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1370system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1371system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
1372system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1373system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1374system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1375system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1376system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1377system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1378system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1379system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
1380system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency
1381system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency
1382system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
1383system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
1384system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency
1385system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency
1386system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
1387system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
1388system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency
1389system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
1390system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
1391system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency
1392system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked
1393system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1394system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked
1395system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1396system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked
1397system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1398system.iocache.fast_writes 0 # number of fast writes performed
1399system.iocache.cache_copies 0 # number of cache copies performed
1400system.iocache.writebacks::writebacks 106630 # number of writebacks
1401system.iocache.writebacks::total 106630 # number of writebacks
1402system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1403system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses
1404system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses
1405system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1406system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1407system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
1408system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
1409system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1410system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses
1411system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses
1412system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1413system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses
1414system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses
1415system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
1416system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles
1417system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles
1418system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
1419system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
1420system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles
1421system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles
1422system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
1423system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles
1424system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles
1425system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
1426system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles
1427system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles
1428system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1429system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1430system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1431system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1432system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1433system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1434system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1435system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1436system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1437system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1438system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1439system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1440system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1441system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
1442system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency
1443system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency
1444system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
1445system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
1446system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency
1447system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency
1448system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
1449system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
1450system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
1451system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
1452system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
1453system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
1454system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1455system.membus.trans_dist::ReadReq 448489 # Transaction distribution
1456system.membus.trans_dist::ReadResp 448489 # Transaction distribution
1457system.membus.trans_dist::WriteReq 33710 # Transaction distribution
1458system.membus.trans_dist::WriteResp 33710 # Transaction distribution
1459system.membus.trans_dist::Writeback 1214153 # Transaction distribution
1460system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution
1461system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution
1462system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution
1463system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1464system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution
1465system.membus.trans_dist::ReadExReq 512353 # Transaction distribution
1466system.membus.trans_dist::ReadExResp 512353 # Transaction distribution
1467system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
1468system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
1469system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
1470system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes)
1471system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes)
1472system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes)
1473system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes)
1474system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes)
1475system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
1476system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
1477system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
1478system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes)
1479system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes)
1480system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes)
1481system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
1482system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
1483system.membus.snoops 3324 # Total snoops (count)

1230system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
1231system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1232system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
1233system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1234system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks)
1235system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1236system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks)
1237system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1238system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks)
1239system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1240system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks)
1241system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1242system.iobus.trans_dist::ReadReq 40333 # Transaction distribution
1243system.iobus.trans_dist::ReadResp 40333 # Transaction distribution
1244system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1245system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
1246system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
1247system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1248system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1249system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1250system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1251system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1252system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1253system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1254system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1255system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1256system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1257system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1258system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1259system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1260system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1261system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1262system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
1263system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes)
1264system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes)
1265system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1266system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1267system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes)
1268system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1269system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1270system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1271system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1272system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1273system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1274system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1275system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1276system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1277system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1278system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1279system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1280system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1281system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1282system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1283system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
1284system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes)
1285system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes)
1286system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1287system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1288system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes)
1289system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
1290system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1291system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
1292system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1293system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
1294system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1295system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
1296system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1297system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1298system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1299system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1300system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1301system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1302system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1303system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1304system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1305system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1306system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1307system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1308system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1309system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
1310system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1311system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
1312system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1313system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
1314system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1315system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
1316system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1317system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks)
1318system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1319system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1320system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1321system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1322system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1323system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks)
1324system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1325system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
1326system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1327system.iocache.tags.replacements 115493 # number of replacements
1328system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use
1329system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1330system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks.
1331system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1332system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit.
1333system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor
1334system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor
1335system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy
1336system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy
1337system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy
1338system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1339system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1340system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1341system.iocache.tags.tag_accesses 1039965 # Number of tag accesses
1342system.iocache.tags.data_accesses 1039965 # Number of data accesses
1343system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1344system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses
1345system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses
1346system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1347system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1348system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
1349system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
1350system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1351system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses
1352system.iocache.demand_misses::total 8888 # number of demand (read+write) misses
1353system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1354system.iocache.overall_misses::realview.ide 8848 # number of overall misses
1355system.iocache.overall_misses::total 8888 # number of overall misses
1356system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
1357system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles
1358system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles
1359system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
1360system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
1361system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles
1362system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles
1363system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
1364system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles
1365system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles
1366system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
1367system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles
1368system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles
1369system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1370system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses)
1371system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses)
1372system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1373system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1374system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
1375system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
1376system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1377system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses
1378system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses
1379system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1380system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses
1381system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses
1382system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1383system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1385system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1387system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
1388system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1389system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1390system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1391system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1392system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1393system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1394system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1395system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
1396system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency
1397system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency
1398system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
1399system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
1400system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency
1401system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency
1402system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
1403system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
1404system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency
1405system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
1406system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
1407system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency
1408system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked
1409system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1410system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked
1411system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1412system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked
1413system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1414system.iocache.fast_writes 0 # number of fast writes performed
1415system.iocache.cache_copies 0 # number of cache copies performed
1416system.iocache.writebacks::writebacks 106630 # number of writebacks
1417system.iocache.writebacks::total 106630 # number of writebacks
1418system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1419system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses
1420system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses
1421system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1422system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1423system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
1424system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
1425system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1426system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses
1427system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses
1428system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1429system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses
1430system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses
1431system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
1432system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles
1433system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles
1434system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
1435system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
1436system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles
1437system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles
1438system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
1439system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles
1440system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles
1441system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
1442system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles
1443system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles
1444system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1445system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1446system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1447system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1448system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1449system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1450system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1451system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1452system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1453system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1454system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1455system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1456system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1457system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
1458system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency
1459system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency
1460system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
1461system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
1462system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency
1463system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency
1464system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
1465system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
1466system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
1467system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
1468system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
1469system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
1470system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1471system.membus.trans_dist::ReadReq 448489 # Transaction distribution
1472system.membus.trans_dist::ReadResp 448489 # Transaction distribution
1473system.membus.trans_dist::WriteReq 33710 # Transaction distribution
1474system.membus.trans_dist::WriteResp 33710 # Transaction distribution
1475system.membus.trans_dist::Writeback 1214153 # Transaction distribution
1476system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution
1477system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution
1478system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution
1479system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1480system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution
1481system.membus.trans_dist::ReadExReq 512353 # Transaction distribution
1482system.membus.trans_dist::ReadExResp 512353 # Transaction distribution
1483system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
1484system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
1485system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
1486system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes)
1487system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes)
1488system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes)
1489system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes)
1490system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes)
1491system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
1492system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
1493system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
1494system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes)
1495system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes)
1496system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes)
1497system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
1498system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
1499system.membus.snoops 3324 # Total snoops (count)

1484system.membus.snoop_fanout::samples 2750930 # Request fanout histogram

1500system.membus.snoop_fanout::samples 2861471 # Request fanout histogram

1485system.membus.snoop_fanout::mean 1 # Request fanout histogram
1486system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1487system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1488system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1501system.membus.snoop_fanout::mean 1 # Request fanout histogram
1502system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1503system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1504system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1489system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram

1505system.membus.snoop_fanout::1 2861471 100.00% 100.00% # Request fanout histogram

1490system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1491system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1492system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1493system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1506system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1507system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1508system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1509system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1494system.membus.snoop_fanout::total 2750930 # Request fanout histogram

1510system.membus.snoop_fanout::total 2861471 # Request fanout histogram