1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.759374 # Number of seconds simulated
4sim_ticks 51759374264500 # Number of ticks simulated
5final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 790659 # Simulator instruction rate (inst/s)
8host_op_rate 929140 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 48897567060 # Simulator tick rate (ticks/s)
10host_mem_usage 670860 # Number of bytes of host memory used
11host_seconds 1058.53 # Real time elapsed on the host
12sim_insts 836933434 # Number of instructions simulated
13sim_ops 983519389 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory
21system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory
--- 290 unchanged lines hidden (view full) ---
314system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ)
315system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ)
316system.physmem_1.averagePower 668.532817 # Core power per rank (mW)
317system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states
318system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states
319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
320system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states
321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
322system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
323system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
324system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
325system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
326system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
327system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
328system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
329system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
330system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
331system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
332system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
333system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
334system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
335system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
336system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
337system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
338system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
339system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
340system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
341system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
342system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
343system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
344system.cpu_clk_domain.clock 500 # Clock period in ticks
345system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
366system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
367system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
368system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
369system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
370system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
371system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
372system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
373system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
374system.cpu.dtb.walker.walks 187211 # Table walker walks requested
375system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors
376system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate
377system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate
378system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
379system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency
380system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency
381system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency
--- 49 unchanged lines hidden (view full) ---
431system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
432system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions
433system.cpu.dtb.read_accesses 157638936 # DTB read accesses
434system.cpu.dtb.write_accesses 143040821 # DTB write accesses
435system.cpu.dtb.inst_accesses 0 # ITB inst accesses
436system.cpu.dtb.hits 300492546 # DTB hits
437system.cpu.dtb.misses 187211 # DTB misses
438system.cpu.dtb.accesses 300679757 # DTB accesses
439system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
460system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
461system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
462system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
463system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
464system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
465system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
466system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
467system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
468system.cpu.itb.walker.walks 119486 # Table walker walks requested
469system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors
470system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
471system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate
472system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency
473system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency
474system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency
475system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency
--- 41 unchanged lines hidden (view full) ---
517system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
518system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
519system.cpu.itb.read_accesses 0 # DTB read accesses
520system.cpu.itb.write_accesses 0 # DTB write accesses
521system.cpu.itb.inst_accesses 837568735 # ITB inst accesses
522system.cpu.itb.hits 837449249 # DTB hits
523system.cpu.itb.misses 119486 # DTB misses
524system.cpu.itb.accesses 837568735 # DTB accesses
525system.cpu.numCycles 103518748529 # number of cpu cycles simulated
526system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
527system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
528system.cpu.kern.inst.arm 0 # number of arm instructions executed
529system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed
530system.cpu.committedInsts 836933434 # Number of instructions committed
531system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed
532system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses
--- 46 unchanged lines hidden (view full) ---
579system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction
580system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction
581system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction
582system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction
583system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction
584system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
585system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
586system.cpu.op_class::total 984078328 # Class of executed instruction
587system.cpu.dcache.tags.replacements 9381962 # number of replacements
588system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use
589system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks.
590system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks.
591system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks.
592system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit.
593system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor
594system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy
595system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
596system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
597system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
598system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id
599system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
600system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
601system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
602system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses
603system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses
604system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits
605system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits
606system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits
607system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits
608system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits
609system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits
610system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits
611system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits
--- 172 unchanged lines hidden (view full) ---
784system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency
785system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency
786system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency
787system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency
788system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency
789system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency
790system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency
791system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency
792system.cpu.icache.tags.replacements 13331164 # number of replacements
793system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use
794system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks.
795system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks.
796system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks.
797system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit.
798system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor
799system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy
800system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy
801system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
802system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
803system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
804system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id
805system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
806system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
807system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses
808system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses
809system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits
810system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits
811system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits
812system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits
813system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits
814system.cpu.icache.overall_hits::total 824117568 # number of overall hits
815system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses
816system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses
--- 64 unchanged lines hidden (view full) ---
881system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency
882system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency
883system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency
884system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency
885system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency
886system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency
887system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency
888system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency
889system.cpu.l2cache.tags.replacements 1036266 # number of replacements
890system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use
891system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks.
892system.cpu.l2cache.tags.sampled_refs 1098550 # Sample count of references to valid blocks.
893system.cpu.l2cache.tags.avg_refs 37.921538 # Average number of references to valid blocks.
894system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit.
895system.cpu.l2cache.tags.occ_blocks::writebacks 38127.362532 # Average occupied blocks per requestor
896system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 231.236011 # Average occupied blocks per requestor
--- 13 unchanged lines hidden (view full) ---
910system.cpu.l2cache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id
911system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2434 # Occupied blocks per task id
912system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5507 # Occupied blocks per task id
913system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53647 # Occupied blocks per task id
914system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id
915system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id
916system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses
917system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses
918system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits
919system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits
920system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits
921system.cpu.l2cache.WritebackDirty_hits::writebacks 7313678 # number of WritebackDirty hits
922system.cpu.l2cache.WritebackDirty_hits::total 7313678 # number of WritebackDirty hits
923system.cpu.l2cache.WritebackClean_hits::writebacks 13329610 # number of WritebackClean hits
924system.cpu.l2cache.WritebackClean_hits::total 13329610 # number of WritebackClean hits
925system.cpu.l2cache.UpgradeReq_hits::cpu.data 9057 # number of UpgradeReq hits
--- 274 unchanged lines hidden (view full) ---
1200system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency
1201system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency
1202system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter.
1203system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1204system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1205system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter.
1206system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1207system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1208system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution
1209system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution
1210system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
1211system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
1212system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution
1213system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution
1214system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution
1215system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution
--- 34 unchanged lines hidden (view full) ---
1250system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks)
1251system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1252system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks)
1253system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1254system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks)
1255system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1256system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks)
1257system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1258system.iobus.trans_dist::ReadReq 40345 # Transaction distribution
1259system.iobus.trans_dist::ReadResp 40345 # Transaction distribution
1260system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1261system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
1262system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1263system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1264system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1265system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
--- 60 unchanged lines hidden (view full) ---
1326system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks)
1327system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1328system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1329system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1330system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks)
1331system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1332system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1333system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1334system.iocache.tags.replacements 115506 # number of replacements
1335system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use
1336system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1337system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks.
1338system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1339system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit.
1340system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor
1341system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor
1342system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy
1343system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy
1344system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy
1345system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1346system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1347system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1348system.iocache.tags.tag_accesses 1040073 # Number of tag accesses
1349system.iocache.tags.data_accesses 1040073 # Number of data accesses
1350system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1351system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses
1352system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses
1353system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1354system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1355system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1356system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1357system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
--- 109 unchanged lines hidden (view full) ---
1467system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency
1468system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency
1469system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
1470system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
1471system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
1472system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
1473system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
1474system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
1475system.membus.trans_dist::ReadReq 76827 # Transaction distribution
1476system.membus.trans_dist::ReadResp 389416 # Transaction distribution
1477system.membus.trans_dist::WriteReq 33708 # Transaction distribution
1478system.membus.trans_dist::WriteResp 33708 # Transaction distribution
1479system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution
1480system.membus.trans_dist::CleanEvict 164302 # Transaction distribution
1481system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution
1482system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
--- 37 unchanged lines hidden (view full) ---
1520system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks)
1521system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1522system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks)
1523system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1524system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks)
1525system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1526system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks)
1527system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1528system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1529system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1530system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1531system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1532system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1533system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1534system.realview.ethernet.txBytes 966 # Bytes Transmitted
1535system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1536system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1537system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1538system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1539system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1540system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1541system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
--- 26 unchanged lines hidden (view full) ---
1568system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1569system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1570system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1571system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1572system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1573system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1574system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1575system.realview.ethernet.droppedPackets 0 # number of packets dropped
1576system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1577system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1578system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1579system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1580
1581---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.759374 # Number of seconds simulated
4sim_ticks 51759374264500 # Number of ticks simulated
5final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 790659 # Simulator instruction rate (inst/s)
8host_op_rate 929140 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 48897567060 # Simulator tick rate (ticks/s)
10host_mem_usage 670860 # Number of bytes of host memory used
11host_seconds 1058.53 # Real time elapsed on the host
12sim_insts 836933434 # Number of instructions simulated
13sim_ops 983519389 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory
21system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory
--- 290 unchanged lines hidden (view full) ---
314system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ)
315system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ)
316system.physmem_1.averagePower 668.532817 # Core power per rank (mW)
317system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states
318system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states
319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
320system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states
321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
322system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
323system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
324system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
325system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
326system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
327system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
328system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
329system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
330system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
331system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
332system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
333system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
334system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
335system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
336system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
337system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
338system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
339system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
340system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
341system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
342system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
343system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
344system.cpu_clk_domain.clock 500 # Clock period in ticks
345system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
366system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
367system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
368system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
369system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
370system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
371system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
372system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
373system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
374system.cpu.dtb.walker.walks 187211 # Table walker walks requested
375system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors
376system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate
377system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate
378system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
379system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency
380system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency
381system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency
--- 49 unchanged lines hidden (view full) ---
431system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
432system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions
433system.cpu.dtb.read_accesses 157638936 # DTB read accesses
434system.cpu.dtb.write_accesses 143040821 # DTB write accesses
435system.cpu.dtb.inst_accesses 0 # ITB inst accesses
436system.cpu.dtb.hits 300492546 # DTB hits
437system.cpu.dtb.misses 187211 # DTB misses
438system.cpu.dtb.accesses 300679757 # DTB accesses
439system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
460system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
461system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
462system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
463system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
464system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
465system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
466system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
467system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
468system.cpu.itb.walker.walks 119486 # Table walker walks requested
469system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors
470system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
471system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate
472system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency
473system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency
474system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency
475system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency
--- 41 unchanged lines hidden (view full) ---
517system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
518system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
519system.cpu.itb.read_accesses 0 # DTB read accesses
520system.cpu.itb.write_accesses 0 # DTB write accesses
521system.cpu.itb.inst_accesses 837568735 # ITB inst accesses
522system.cpu.itb.hits 837449249 # DTB hits
523system.cpu.itb.misses 119486 # DTB misses
524system.cpu.itb.accesses 837568735 # DTB accesses
525system.cpu.numCycles 103518748529 # number of cpu cycles simulated
526system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
527system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
528system.cpu.kern.inst.arm 0 # number of arm instructions executed
529system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed
530system.cpu.committedInsts 836933434 # Number of instructions committed
531system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed
532system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses
--- 46 unchanged lines hidden (view full) ---
579system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction
580system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction
581system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction
582system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction
583system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction
584system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
585system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
586system.cpu.op_class::total 984078328 # Class of executed instruction
587system.cpu.dcache.tags.replacements 9381962 # number of replacements
588system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use
589system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks.
590system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks.
591system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks.
592system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit.
593system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor
594system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy
595system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
596system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
597system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
598system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id
599system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
600system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
601system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
602system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses
603system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses
604system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits
605system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits
606system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits
607system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits
608system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits
609system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits
610system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits
611system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits
--- 172 unchanged lines hidden (view full) ---
784system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency
785system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency
786system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency
787system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency
788system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency
789system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency
790system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency
791system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency
792system.cpu.icache.tags.replacements 13331164 # number of replacements
793system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use
794system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks.
795system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks.
796system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks.
797system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit.
798system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor
799system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy
800system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy
801system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
802system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
803system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
804system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id
805system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
806system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
807system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses
808system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses
809system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits
810system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits
811system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits
812system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits
813system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits
814system.cpu.icache.overall_hits::total 824117568 # number of overall hits
815system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses
816system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses
--- 64 unchanged lines hidden (view full) ---
881system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency
882system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency
883system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency
884system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency
885system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency
886system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency
887system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency
888system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency
889system.cpu.l2cache.tags.replacements 1036266 # number of replacements
890system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use
891system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks.
892system.cpu.l2cache.tags.sampled_refs 1098550 # Sample count of references to valid blocks.
893system.cpu.l2cache.tags.avg_refs 37.921538 # Average number of references to valid blocks.
894system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit.
895system.cpu.l2cache.tags.occ_blocks::writebacks 38127.362532 # Average occupied blocks per requestor
896system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 231.236011 # Average occupied blocks per requestor
--- 13 unchanged lines hidden (view full) ---
910system.cpu.l2cache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id
911system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2434 # Occupied blocks per task id
912system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5507 # Occupied blocks per task id
913system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53647 # Occupied blocks per task id
914system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id
915system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id
916system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses
917system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses
918system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits
919system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits
920system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits
921system.cpu.l2cache.WritebackDirty_hits::writebacks 7313678 # number of WritebackDirty hits
922system.cpu.l2cache.WritebackDirty_hits::total 7313678 # number of WritebackDirty hits
923system.cpu.l2cache.WritebackClean_hits::writebacks 13329610 # number of WritebackClean hits
924system.cpu.l2cache.WritebackClean_hits::total 13329610 # number of WritebackClean hits
925system.cpu.l2cache.UpgradeReq_hits::cpu.data 9057 # number of UpgradeReq hits
--- 274 unchanged lines hidden (view full) ---
1200system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency
1201system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency
1202system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter.
1203system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1204system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1205system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter.
1206system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1207system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1208system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution
1209system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution
1210system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
1211system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
1212system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution
1213system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution
1214system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution
1215system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution
--- 34 unchanged lines hidden (view full) ---
1250system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks)
1251system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1252system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks)
1253system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1254system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks)
1255system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1256system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks)
1257system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1258system.iobus.trans_dist::ReadReq 40345 # Transaction distribution
1259system.iobus.trans_dist::ReadResp 40345 # Transaction distribution
1260system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1261system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
1262system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1263system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1264system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1265system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
--- 60 unchanged lines hidden (view full) ---
1326system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks)
1327system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1328system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1329system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1330system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks)
1331system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1332system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1333system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1334system.iocache.tags.replacements 115506 # number of replacements
1335system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use
1336system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1337system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks.
1338system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1339system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit.
1340system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor
1341system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor
1342system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy
1343system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy
1344system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy
1345system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1346system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1347system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1348system.iocache.tags.tag_accesses 1040073 # Number of tag accesses
1349system.iocache.tags.data_accesses 1040073 # Number of data accesses
1350system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1351system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses
1352system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses
1353system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1354system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1355system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1356system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1357system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
--- 109 unchanged lines hidden (view full) ---
1467system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency
1468system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency
1469system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
1470system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
1471system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
1472system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
1473system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
1474system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
1475system.membus.trans_dist::ReadReq 76827 # Transaction distribution
1476system.membus.trans_dist::ReadResp 389416 # Transaction distribution
1477system.membus.trans_dist::WriteReq 33708 # Transaction distribution
1478system.membus.trans_dist::WriteResp 33708 # Transaction distribution
1479system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution
1480system.membus.trans_dist::CleanEvict 164302 # Transaction distribution
1481system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution
1482system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
--- 37 unchanged lines hidden (view full) ---
1520system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks)
1521system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1522system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks)
1523system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1524system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks)
1525system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1526system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks)
1527system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1528system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1529system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1530system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1531system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1532system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1533system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1534system.realview.ethernet.txBytes 966 # Bytes Transmitted
1535system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1536system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1537system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1538system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1539system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1540system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1541system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
--- 26 unchanged lines hidden (view full) ---
1568system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1569system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1570system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1571system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1572system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1573system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1574system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1575system.realview.ethernet.droppedPackets 0 # number of packets dropped
1576system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1577system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1578system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1579system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1580
1581---------- End Simulation Statistics ----------