| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 22 unchanged lines hidden (view full) --- 31highest_el_is_64=false 32init_param=0 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 22 unchanged lines hidden (view full) --- 31highest_el_is_64=false 32init_param=0 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing |
| 39mem_ranges=2147483648:2415919103 | 39mem_ranges=2147483648:2415919103:0:0:0:0 |
| 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 --- 20 unchanged lines hidden (view full) --- 68clk_domain=system.clk_domain 69default_p_state=UNDEFINED 70delay=50000 71eventq_index=0 72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null | 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 --- 20 unchanged lines hidden (view full) --- 68clk_domain=system.clk_domain 69default_p_state=UNDEFINED 70delay=50000 71eventq_index=0 72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null |
| 76ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 | 76ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 |
| 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk 84children=image --- 63 unchanged lines hidden (view full) --- 148tracer=system.cpu.tracer 149workload= 150dcache_port=system.cpu.dcache.cpu_side 151icache_port=system.cpu.icache.cpu_side 152 153[system.cpu.dcache] 154type=Cache 155children=tags | 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk 84children=image --- 63 unchanged lines hidden (view full) --- 148tracer=system.cpu.tracer 149workload= 150dcache_port=system.cpu.dcache.cpu_side 151icache_port=system.cpu.icache.cpu_side 152 153[system.cpu.dcache] 154type=Cache 155children=tags |
| 156addr_ranges=0:18446744073709551615 | 156addr_ranges=0:18446744073709551615:0:0:0:0 |
| 157assoc=4 158clk_domain=system.cpu_clk_domain 159clusivity=mostly_incl 160default_p_state=UNDEFINED 161demand_mshr_reserve=1 162eventq_index=0 163hit_latency=2 164is_read_only=false --- 80 unchanged lines hidden (view full) --- 245p_state_clk_gate_min=1000 246power_model=Null 247sys=system 248port=system.cpu.toL2Bus.slave[3] 249 250[system.cpu.icache] 251type=Cache 252children=tags | 157assoc=4 158clk_domain=system.cpu_clk_domain 159clusivity=mostly_incl 160default_p_state=UNDEFINED 161demand_mshr_reserve=1 162eventq_index=0 163hit_latency=2 164is_read_only=false --- 80 unchanged lines hidden (view full) --- 245p_state_clk_gate_min=1000 246power_model=Null 247sys=system 248port=system.cpu.toL2Bus.slave[3] 249 250[system.cpu.icache] 251type=Cache 252children=tags |
| 253addr_ranges=0:18446744073709551615 | 253addr_ranges=0:18446744073709551615:0:0:0:0 |
| 254assoc=1 255clk_domain=system.cpu_clk_domain 256clusivity=mostly_incl 257default_p_state=UNDEFINED 258demand_mshr_reserve=1 259eventq_index=0 260hit_latency=2 261is_read_only=true --- 43 unchanged lines hidden (view full) --- 305id_aa64afr0_el1=0 306id_aa64afr1_el1=0 307id_aa64dfr0_el1=1052678 308id_aa64dfr1_el1=0 309id_aa64isar0_el1=0 310id_aa64isar1_el1=0 311id_aa64mmfr0_el1=15728642 312id_aa64mmfr1_el1=0 | 254assoc=1 255clk_domain=system.cpu_clk_domain 256clusivity=mostly_incl 257default_p_state=UNDEFINED 258demand_mshr_reserve=1 259eventq_index=0 260hit_latency=2 261is_read_only=true --- 43 unchanged lines hidden (view full) --- 305id_aa64afr0_el1=0 306id_aa64afr1_el1=0 307id_aa64dfr0_el1=1052678 308id_aa64dfr1_el1=0 309id_aa64isar0_el1=0 310id_aa64isar1_el1=0 311id_aa64mmfr0_el1=15728642 312id_aa64mmfr1_el1=0 |
| 313id_aa64pfr0_el1=17 | 313id_aa64pfr0_el1=34 |
| 314id_aa64pfr1_el1=0 315id_isar0=34607377 316id_isar1=34677009 317id_isar2=555950401 318id_isar3=17899825 319id_isar4=268501314 320id_isar5=0 321id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 377p_state_clk_gate_min=1000 378power_model=Null 379sys=system 380port=system.cpu.toL2Bus.slave[2] 381 382[system.cpu.l2cache] 383type=Cache 384children=tags | 314id_aa64pfr1_el1=0 315id_isar0=34607377 316id_isar1=34677009 317id_isar2=555950401 318id_isar3=17899825 319id_isar4=268501314 320id_isar5=0 321id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 377p_state_clk_gate_min=1000 378power_model=Null 379sys=system 380port=system.cpu.toL2Bus.slave[2] 381 382[system.cpu.l2cache] 383type=Cache 384children=tags |
| 385addr_ranges=0:18446744073709551615 | 385addr_ranges=0:18446744073709551615:0:0:0:0 |
| 386assoc=8 387clk_domain=system.cpu_clk_domain 388clusivity=mostly_incl 389default_p_state=UNDEFINED 390demand_mshr_reserve=1 391eventq_index=0 392hit_latency=20 393is_read_only=false --- 100 unchanged lines hidden (view full) --- 494use_default_range=false 495width=16 496master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 497slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 498 499[system.iocache] 500type=Cache 501children=tags | 386assoc=8 387clk_domain=system.cpu_clk_domain 388clusivity=mostly_incl 389default_p_state=UNDEFINED 390demand_mshr_reserve=1 391eventq_index=0 392hit_latency=20 393is_read_only=false --- 100 unchanged lines hidden (view full) --- 494use_default_range=false 495width=16 496master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 497slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 498 499[system.iocache] 500type=Cache 501children=tags |
| 502addr_ranges=2147483648:2415919103 | 502addr_ranges=2147483648:2415919103:0:0:0:0 |
| 503assoc=8 504clk_domain=system.clk_domain 505clusivity=mostly_incl 506default_p_state=UNDEFINED 507demand_mshr_reserve=1 508eventq_index=0 509hit_latency=50 510is_read_only=false --- 28 unchanged lines hidden (view full) --- 539p_state_clk_gate_max=1000000000000 540p_state_clk_gate_min=1000 541power_model=Null 542sequential_access=false 543size=1024 544 545[system.membus] 546type=CoherentXBar | 503assoc=8 504clk_domain=system.clk_domain 505clusivity=mostly_incl 506default_p_state=UNDEFINED 507demand_mshr_reserve=1 508eventq_index=0 509hit_latency=50 510is_read_only=false --- 28 unchanged lines hidden (view full) --- 539p_state_clk_gate_max=1000000000000 540p_state_clk_gate_min=1000 541power_model=Null 542sequential_access=false 543size=1024 544 545[system.membus] 546type=CoherentXBar |
| 547children=badaddr_responder | 547children=badaddr_responder snoop_filter |
| 548clk_domain=system.clk_domain 549default_p_state=UNDEFINED 550eventq_index=0 551forward_latency=4 552frontend_latency=3 553p_state_clk_gate_bins=20 554p_state_clk_gate_max=1000000000000 555p_state_clk_gate_min=1000 556point_of_coherency=true 557power_model=Null 558response_latency=2 | 548clk_domain=system.clk_domain 549default_p_state=UNDEFINED 550eventq_index=0 551forward_latency=4 552frontend_latency=3 553p_state_clk_gate_bins=20 554p_state_clk_gate_max=1000000000000 555p_state_clk_gate_min=1000 556point_of_coherency=true 557power_model=Null 558response_latency=2 |
| 559snoop_filter=Null | 559snoop_filter=system.membus.snoop_filter |
| 560snoop_response_latency=4 561system=system 562use_default_range=false 563width=16 564default=system.membus.badaddr_responder.pio 565master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port 566slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 567 --- 15 unchanged lines hidden (view full) --- 583ret_data32=4294967295 584ret_data64=18446744073709551615 585ret_data8=255 586system=system 587update_data=false 588warn_access=warn 589pio=system.membus.default 590 | 560snoop_response_latency=4 561system=system 562use_default_range=false 563width=16 564default=system.membus.badaddr_responder.pio 565master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port 566slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 567 --- 15 unchanged lines hidden (view full) --- 583ret_data32=4294967295 584ret_data64=18446744073709551615 585ret_data8=255 586system=system 587update_data=false 588warn_access=warn 589pio=system.membus.default 590 |
| 591[system.membus.snoop_filter] 592type=SnoopFilter 593eventq_index=0 594lookup_latency=1 595max_capacity=8388608 596system=system 597 |
|
| 591[system.physmem] 592type=DRAMCtrl | 598[system.physmem] 599type=DRAMCtrl |
| 593IDD0=0.075000 | 600IDD0=0.055000 |
| 594IDD02=0.000000 | 601IDD02=0.000000 |
| 595IDD2N=0.050000 | 602IDD2N=0.032000 |
| 596IDD2N2=0.000000 597IDD2P0=0.000000 598IDD2P02=0.000000 | 603IDD2N2=0.000000 604IDD2P0=0.000000 605IDD2P02=0.000000 |
| 599IDD2P1=0.000000 | 606IDD2P1=0.032000 |
| 600IDD2P12=0.000000 | 607IDD2P12=0.000000 |
| 601IDD3N=0.057000 | 608IDD3N=0.038000 |
| 602IDD3N2=0.000000 603IDD3P0=0.000000 604IDD3P02=0.000000 | 609IDD3N2=0.000000 610IDD3P0=0.000000 611IDD3P02=0.000000 |
| 605IDD3P1=0.000000 | 612IDD3P1=0.038000 |
| 606IDD3P12=0.000000 | 613IDD3P12=0.000000 |
| 607IDD4R=0.187000 | 614IDD4R=0.157000 |
| 608IDD4R2=0.000000 | 615IDD4R2=0.000000 |
| 609IDD4W=0.165000 | 616IDD4W=0.125000 |
| 610IDD4W2=0.000000 | 617IDD4W2=0.000000 |
| 611IDD5=0.220000 | 618IDD5=0.235000 |
| 612IDD52=0.000000 | 619IDD52=0.000000 |
| 613IDD6=0.000000 | 620IDD6=0.020000 |
| 614IDD62=0.000000 615VDD=1.500000 616VDD2=0.000000 617activation_limit=4 618addr_mapping=RoRaBaCoCh 619bank_groups_per_rank=0 620banks_per_rank=8 621burst_length=8 622channels=1 623clk_domain=system.clk_domain 624conf_table_reported=true 625default_p_state=UNDEFINED 626device_bus_width=8 627device_rowbuffer_size=1024 628device_size=536870912 629devices_per_rank=8 630dll=true 631eventq_index=0 632in_addr_map=true | 621IDD62=0.000000 622VDD=1.500000 623VDD2=0.000000 624activation_limit=4 625addr_mapping=RoRaBaCoCh 626bank_groups_per_rank=0 627banks_per_rank=8 628burst_length=8 629channels=1 630clk_domain=system.clk_domain 631conf_table_reported=true 632default_p_state=UNDEFINED 633device_bus_width=8 634device_rowbuffer_size=1024 635device_size=536870912 636devices_per_rank=8 637dll=true 638eventq_index=0 639in_addr_map=true |
| 640kvm_map=true |
|
| 633max_accesses_per_row=16 634mem_sched_policy=frfcfs 635min_writes_per_switch=16 636null=false 637p_state_clk_gate_bins=20 638p_state_clk_gate_max=1000000000000 639p_state_clk_gate_min=1000 640page_policy=open_adaptive 641power_model=Null | 641max_accesses_per_row=16 642mem_sched_policy=frfcfs 643min_writes_per_switch=16 644null=false 645p_state_clk_gate_bins=20 646p_state_clk_gate_max=1000000000000 647p_state_clk_gate_min=1000 648page_policy=open_adaptive 649power_model=Null |
| 642range=2147483648:2415919103 | 650range=2147483648:2415919103:0:0:0:0 |
| 643ranks_per_channel=2 644read_buffer_size=32 645static_backend_latency=10000 646static_frontend_latency=10000 647tBURST=5000 648tCCD_L=0 649tCK=1250 650tCL=13750 --- 5 unchanged lines hidden (view full) --- 656tRP=13750 657tRRD=6000 658tRRD_L=0 659tRTP=7500 660tRTW=2500 661tWR=15000 662tWTR=7500 663tXAW=30000 | 651ranks_per_channel=2 652read_buffer_size=32 653static_backend_latency=10000 654static_frontend_latency=10000 655tBURST=5000 656tCCD_L=0 657tCK=1250 658tCL=13750 --- 5 unchanged lines hidden (view full) --- 664tRP=13750 665tRRD=6000 666tRRD_L=0 667tRTP=7500 668tRTW=2500 669tWR=15000 670tWTR=7500 671tXAW=30000 |
| 664tXP=0 | 672tXP=6000 |
| 665tXPDLL=0 | 673tXPDLL=0 |
| 666tXS=0 | 674tXS=270000 |
| 667tXSDLL=0 668write_buffer_size=64 669write_high_thresh_perc=85 670write_low_thresh_perc=50 671port=system.membus.master[5] 672 673[system.realview] 674type=RealView --- 336 unchanged lines hidden (view full) --- 1011type=Pl390 1012clk_domain=system.clk_domain 1013cpu_addr=738205696 1014cpu_pio_delay=10000 1015default_p_state=UNDEFINED 1016dist_addr=738201600 1017dist_pio_delay=10000 1018eventq_index=0 | 675tXSDLL=0 676write_buffer_size=64 677write_high_thresh_perc=85 678write_low_thresh_perc=50 679port=system.membus.master[5] 680 681[system.realview] 682type=RealView --- 336 unchanged lines hidden (view full) --- 1019type=Pl390 1020clk_domain=system.clk_domain 1021cpu_addr=738205696 1022cpu_pio_delay=10000 1023default_p_state=UNDEFINED 1024dist_addr=738201600 1025dist_pio_delay=10000 1026eventq_index=0 |
| 1019gem5_extensions=true | 1027gem5_extensions=false |
| 1020int_latency=10000 1021it_lines=128 1022p_state_clk_gate_bins=20 1023p_state_clk_gate_max=1000000000000 1024p_state_clk_gate_min=1000 1025platform=system.realview 1026power_model=Null 1027system=system --- 296 unchanged lines hidden (view full) --- 1324power_model=Null 1325system=system 1326pio=system.iobus.master[21] 1327 1328[system.realview.nvmem] 1329type=SimpleMemory 1330bandwidth=73.000000 1331clk_domain=system.clk_domain | 1028int_latency=10000 1029it_lines=128 1030p_state_clk_gate_bins=20 1031p_state_clk_gate_max=1000000000000 1032p_state_clk_gate_min=1000 1033platform=system.realview 1034power_model=Null 1035system=system --- 296 unchanged lines hidden (view full) --- 1332power_model=Null 1333system=system 1334pio=system.iobus.master[21] 1335 1336[system.realview.nvmem] 1337type=SimpleMemory 1338bandwidth=73.000000 1339clk_domain=system.clk_domain |
| 1332conf_table_reported=true | 1340conf_table_reported=false |
| 1333default_p_state=UNDEFINED 1334eventq_index=0 1335in_addr_map=true | 1341default_p_state=UNDEFINED 1342eventq_index=0 1343in_addr_map=true |
| 1344kvm_map=true |
|
| 1336latency=30000 1337latency_var=0 1338null=false 1339p_state_clk_gate_bins=20 1340p_state_clk_gate_max=1000000000000 1341p_state_clk_gate_min=1000 1342power_model=Null | 1345latency=30000 1346latency_var=0 1347null=false 1348p_state_clk_gate_bins=20 1349p_state_clk_gate_max=1000000000000 1350p_state_clk_gate_min=1000 1351power_model=Null |
| 1343range=0:67108863 | 1352range=0:67108863:0:0:0:0 |
| 1344port=system.membus.master[1] 1345 1346[system.realview.pci_host] 1347type=GenericPciHost 1348clk_domain=system.clk_domain 1349conf_base=805306368 1350conf_device_bits=12 1351conf_size=268435456 --- 214 unchanged lines hidden (view full) --- 1566[system.realview.vram] 1567type=SimpleMemory 1568bandwidth=73.000000 1569clk_domain=system.clk_domain 1570conf_table_reported=false 1571default_p_state=UNDEFINED 1572eventq_index=0 1573in_addr_map=true | 1353port=system.membus.master[1] 1354 1355[system.realview.pci_host] 1356type=GenericPciHost 1357clk_domain=system.clk_domain 1358conf_base=805306368 1359conf_device_bits=12 1360conf_size=268435456 --- 214 unchanged lines hidden (view full) --- 1575[system.realview.vram] 1576type=SimpleMemory 1577bandwidth=73.000000 1578clk_domain=system.clk_domain 1579conf_table_reported=false 1580default_p_state=UNDEFINED 1581eventq_index=0 1582in_addr_map=true |
| 1583kvm_map=true |
|
| 1574latency=30000 1575latency_var=0 1576null=false 1577p_state_clk_gate_bins=20 1578p_state_clk_gate_max=1000000000000 1579p_state_clk_gate_min=1000 1580power_model=Null | 1584latency=30000 1585latency_var=0 1586null=false 1587p_state_clk_gate_bins=20 1588p_state_clk_gate_max=1000000000000 1589p_state_clk_gate_min=1000 1590power_model=Null |
| 1581range=402653184:436207615 | 1591range=402653184:436207615:0:0:0:0 |
| 1582port=system.iobus.master[11] 1583 1584[system.realview.watchdog_fake] 1585type=AmbaFake 1586amba_id=0 1587clk_domain=system.clk_domain 1588default_p_state=UNDEFINED 1589eventq_index=0 --- 30 unchanged lines hidden --- | 1592port=system.iobus.master[11] 1593 1594[system.realview.watchdog_fake] 1595type=AmbaFake 1596amba_id=0 1597clk_domain=system.clk_domain 1598default_p_state=UNDEFINED 1599eventq_index=0 --- 30 unchanged lines hidden --- |