| stats.txt (11687:b3d5f0e9e258) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 47.405013 # Number of seconds simulated 4sim_ticks 47405012960500 # Number of ticks simulated 5final_tick 47405012960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 47.405081 # Number of seconds simulated 4sim_ticks 47405080882500 # Number of ticks simulated 5final_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1080699 # Simulator instruction rate (inst/s) 8host_op_rate 1271286 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58247547339 # Simulator tick rate (ticks/s) 10host_mem_usage 759864 # Number of bytes of host memory used 11host_seconds 813.85 # Real time elapsed on the host 12sim_insts 879531552 # Number of instructions simulated 13sim_ops 1034641707 # Number of ops (including micro ops) simulated | 7host_inst_rate 1071981 # Simulator instruction rate (inst/s) 8host_op_rate 1260946 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57861452624 # Simulator tick rate (ticks/s) 10host_mem_usage 765552 # Number of bytes of host memory used 11host_seconds 819.29 # Real time elapsed on the host 12sim_insts 878258906 # Number of instructions simulated 13sim_ops 1033075205 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 107584 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 111616 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3269620 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 13856200 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 15427200 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 122176 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 126272 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2852024 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 9626320 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 10834112 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 432576 # Number of bytes read from this memory 28system.physmem.bytes_read::total 56765700 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 3269620 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2852024 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 6121644 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 74832256 # Number of bytes written to this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory 28system.physmem.bytes_read::total 56765124 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory | 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory |
| 35system.physmem.bytes_written::total 74852840 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 1681 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1744 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 91495 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 216516 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 241050 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 1909 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1973 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 44651 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 150424 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 169283 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6759 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 927485 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1169254 # Number of write requests responded to by this memory | 35system.physmem.bytes_written::total 74764392 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 927476 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory |
| 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory | 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory |
| 51system.physmem.num_writes::total 1171828 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 2269 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 2355 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 68972 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 292294 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 325434 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2577 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2664 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 60163 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 203065 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 228544 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9125 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1197462 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 68972 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 60163 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 129135 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1578573 # Write bandwidth from this memory (bytes/s) | 51system.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 53373 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s) |
| 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) | 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) |
| 70system.physmem.bw_write::total 1579007 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1578573 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 2269 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 2355 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 68972 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 292728 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 325434 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2577 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2664 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 60163 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 203066 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 228544 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9125 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2776469 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 927485 # Number of read requests accepted 85system.physmem.writeReqs 1171828 # Number of write requests accepted 86system.physmem.readBursts 927485 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1171828 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 59337472 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 21568 # Total number of bytes read from write queue 90system.physmem.bytesWritten 74850880 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 56765700 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 74852840 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 337 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one | 70system.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 927476 # Number of read requests accepted 85system.physmem.writeReqs 1170446 # Number of write requests accepted 86system.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue 90system.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one |
| 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 96system.physmem.perBankRdBursts::0 53188 # Per bank write bursts 97system.physmem.perBankRdBursts::1 58555 # Per bank write bursts 98system.physmem.perBankRdBursts::2 49548 # Per bank write bursts 99system.physmem.perBankRdBursts::3 58849 # Per bank write bursts 100system.physmem.perBankRdBursts::4 61060 # Per bank write bursts 101system.physmem.perBankRdBursts::5 64213 # Per bank write bursts 102system.physmem.perBankRdBursts::6 58593 # Per bank write bursts 103system.physmem.perBankRdBursts::7 62574 # Per bank write bursts 104system.physmem.perBankRdBursts::8 53530 # Per bank write bursts 105system.physmem.perBankRdBursts::9 96457 # Per bank write bursts 106system.physmem.perBankRdBursts::10 50033 # Per bank write bursts 107system.physmem.perBankRdBursts::11 57571 # Per bank write bursts 108system.physmem.perBankRdBursts::12 47029 # Per bank write bursts 109system.physmem.perBankRdBursts::13 51615 # Per bank write bursts 110system.physmem.perBankRdBursts::14 49510 # Per bank write bursts 111system.physmem.perBankRdBursts::15 54823 # Per bank write bursts 112system.physmem.perBankWrBursts::0 69378 # Per bank write bursts 113system.physmem.perBankWrBursts::1 74382 # Per bank write bursts 114system.physmem.perBankWrBursts::2 69427 # Per bank write bursts 115system.physmem.perBankWrBursts::3 75087 # Per bank write bursts 116system.physmem.perBankWrBursts::4 76532 # Per bank write bursts 117system.physmem.perBankWrBursts::5 78990 # Per bank write bursts 118system.physmem.perBankWrBursts::6 75385 # Per bank write bursts 119system.physmem.perBankWrBursts::7 77589 # Per bank write bursts 120system.physmem.perBankWrBursts::8 70916 # Per bank write bursts 121system.physmem.perBankWrBursts::9 76207 # Per bank write bursts 122system.physmem.perBankWrBursts::10 70858 # Per bank write bursts 123system.physmem.perBankWrBursts::11 75862 # Per bank write bursts 124system.physmem.perBankWrBursts::12 66596 # Per bank write bursts 125system.physmem.perBankWrBursts::13 70423 # Per bank write bursts 126system.physmem.perBankWrBursts::14 68869 # Per bank write bursts 127system.physmem.perBankWrBursts::15 73044 # Per bank write bursts | 96system.physmem.perBankRdBursts::0 53525 # Per bank write bursts 97system.physmem.perBankRdBursts::1 58700 # Per bank write bursts 98system.physmem.perBankRdBursts::2 53136 # Per bank write bursts 99system.physmem.perBankRdBursts::3 59915 # Per bank write bursts 100system.physmem.perBankRdBursts::4 57558 # Per bank write bursts 101system.physmem.perBankRdBursts::5 67025 # Per bank write bursts 102system.physmem.perBankRdBursts::6 57593 # Per bank write bursts 103system.physmem.perBankRdBursts::7 57551 # Per bank write bursts 104system.physmem.perBankRdBursts::8 45941 # Per bank write bursts 105system.physmem.perBankRdBursts::9 94599 # Per bank write bursts 106system.physmem.perBankRdBursts::10 49635 # Per bank write bursts 107system.physmem.perBankRdBursts::11 57294 # Per bank write bursts 108system.physmem.perBankRdBursts::12 48522 # Per bank write bursts 109system.physmem.perBankRdBursts::13 56965 # Per bank write bursts 110system.physmem.perBankRdBursts::14 52794 # Per bank write bursts 111system.physmem.perBankRdBursts::15 56368 # Per bank write bursts 112system.physmem.perBankWrBursts::0 71875 # Per bank write bursts 113system.physmem.perBankWrBursts::1 75753 # Per bank write bursts 114system.physmem.perBankWrBursts::2 71549 # Per bank write bursts 115system.physmem.perBankWrBursts::3 77042 # Per bank write bursts 116system.physmem.perBankWrBursts::4 73392 # Per bank write bursts 117system.physmem.perBankWrBursts::5 80022 # Per bank write bursts 118system.physmem.perBankWrBursts::6 71461 # Per bank write bursts 119system.physmem.perBankWrBursts::7 73088 # Per bank write bursts 120system.physmem.perBankWrBursts::8 65465 # Per bank write bursts 121system.physmem.perBankWrBursts::9 74249 # Per bank write bursts 122system.physmem.perBankWrBursts::10 70475 # Per bank write bursts 123system.physmem.perBankWrBursts::11 74236 # Per bank write bursts 124system.physmem.perBankWrBursts::12 69250 # Per bank write bursts 125system.physmem.perBankWrBursts::13 75271 # Per bank write bursts 126system.physmem.perBankWrBursts::14 70641 # Per bank write bursts 127system.physmem.perBankWrBursts::15 74378 # Per bank write bursts |
| 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 129system.physmem.numWrRetry 516 # Number of times write queue was full causing retry 130system.physmem.totGap 47405009605000 # Total gap between requests | 129system.physmem.numWrRetry 399 # Number of times write queue was full causing retry 130system.physmem.totGap 47405077592000 # Total gap between requests |
| 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 43195 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) | 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 43195 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 137system.physmem.readPktSize::6 884260 # Read request sizes (log2) | 137system.physmem.readPktSize::6 884251 # Read request sizes (log2) |
| 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) | 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 144system.physmem.writePktSize::6 1169254 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 645919 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 88942 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 42222 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 33520 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 28634 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 25074 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 21962 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 18312 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 15502 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 2962 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1110 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 816 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 608 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 446 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 249 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 195 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see | 144system.physmem.writePktSize::6 1167872 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 648346 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 87693 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 41445 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 33200 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 28689 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 25203 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 22073 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 18329 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 15555 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 2733 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1025 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 772 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 592 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 417 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 272 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 219 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 187 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 159 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 104 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see |
| 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 192system.physmem.wrQLenPdf::15 28620 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 36458 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 48218 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 54653 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 60726 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 63711 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 65994 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 67665 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 70176 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 70363 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 73600 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 75174 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 72029 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 70698 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 71278 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 75021 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 68576 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 65669 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 3787 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 2027 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1477 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 1239 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 975 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 1013 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 865 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 814 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 739 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 756 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 763 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 668 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 705 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 695 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 747 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 666 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 760 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 682 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 648 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 743 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 716 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 785 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 937 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 551 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 928 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 1380 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 1236 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 535 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 1170 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 929017 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 144.440810 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 98.331936 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 191.352121 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 617371 66.45% 66.45% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 189527 20.40% 86.86% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 44674 4.81% 91.66% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 20356 2.19% 93.85% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 14838 1.60% 95.45% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 9142 0.98% 96.44% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6196 0.67% 97.10% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5371 0.58% 97.68% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 21542 2.32% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 929017 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 60832 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 15.240992 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 130.606668 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 60830 100.00% 100.00% # Reads before turning the bus around for writes | 192system.physmem.wrQLenPdf::15 28770 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 36931 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 48299 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 54487 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 61032 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 63693 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 65505 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 67515 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 70215 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 70242 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 73447 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 75382 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 72205 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 70493 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 71352 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 75176 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 68341 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 65445 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 3675 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 2020 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1597 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 1157 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1000 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 958 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 839 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 771 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 710 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 697 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 701 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 747 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 686 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 747 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 673 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 670 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 663 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 668 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 662 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 587 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 676 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 672 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 672 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 955 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 727 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 585 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 1023 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 1347 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 1254 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 573 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 921 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 928498 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 144.423393 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 98.327252 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 191.341879 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 616929 66.44% 66.44% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 189662 20.43% 86.87% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 44616 4.81% 91.68% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 20270 2.18% 93.86% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 14755 1.59% 95.45% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 9179 0.99% 96.44% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6168 0.66% 97.10% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5453 0.59% 97.69% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 21466 2.31% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 928498 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 60682 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 15.278254 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 130.725132 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 60680 100.00% 100.00% # Reads before turning the bus around for writes |
| 259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes | 259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::total 60832 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 60832 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 19.225819 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.418138 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 8.471341 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 49295 81.03% 81.03% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 4521 7.43% 88.47% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 2878 4.73% 93.20% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 1749 2.88% 96.07% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 1023 1.68% 97.75% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 226 0.37% 98.13% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 91 0.15% 98.28% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 113 0.19% 98.46% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 47 0.08% 98.54% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 23 0.04% 98.58% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 10 0.02% 98.59% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 42 0.07% 98.66% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 494 0.81% 99.47% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 82 0.13% 99.61% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 51 0.08% 99.69% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 57 0.09% 99.79% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 26 0.04% 99.83% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 3 0.00% 99.83% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 1 0.00% 99.84% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 4 0.01% 99.84% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 2 0.00% 99.85% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 5 0.01% 99.85% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 4 0.01% 99.86% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 14 0.02% 99.88% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::116-119 2 0.00% 99.89% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::124-127 3 0.00% 99.89% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::128-131 21 0.03% 99.93% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::132-135 3 0.00% 99.93% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::136-139 2 0.00% 99.93% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::140-143 13 0.02% 99.96% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::156-159 2 0.00% 99.97% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::180-183 3 0.00% 99.98% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::192-195 2 0.00% 99.99% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::total 60832 # Writes before turning the bus around for reads 309system.physmem.totQLat 46218732203 # Total ticks spent queuing 310system.physmem.totMemAccLat 63602757203 # Total ticks spent from burst creation until serviced by the DRAM 311system.physmem.totBusLat 4635740000 # Total ticks spent in databus transfers 312system.physmem.avgQLat 49850.44 # Average queueing delay per DRAM burst | 261system.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 60682 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 19.250305 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.439777 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 8.504538 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-23 53685 88.47% 88.47% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-31 4623 7.62% 96.09% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::32-39 1219 2.01% 98.10% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::40-47 192 0.32% 98.41% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::48-55 86 0.14% 98.55% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-63 66 0.11% 98.66% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::64-71 562 0.93% 99.59% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::72-79 118 0.19% 99.78% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::80-87 38 0.06% 99.85% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::88-95 2 0.00% 99.85% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::96-103 5 0.01% 99.86% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::104-111 14 0.02% 99.88% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::112-119 2 0.00% 99.88% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::120-127 2 0.00% 99.89% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::128-135 28 0.05% 99.93% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::136-143 15 0.02% 99.96% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::144-151 2 0.00% 99.96% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::152-159 2 0.00% 99.97% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::160-167 1 0.00% 99.97% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::168-175 2 0.00% 99.97% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::176-183 6 0.01% 99.98% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::184-191 5 0.01% 99.99% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::192-199 5 0.01% 100.00% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads 292system.physmem.totQLat 46391884854 # Total ticks spent queuing 293system.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM 294system.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers 295system.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst |
| 313system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 296system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 314system.physmem.avgMemAccLat 68600.44 # Average memory access latency per DRAM burst | 297system.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst |
| 315system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 316system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 317system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s 318system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 319system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 320system.physmem.busUtil 0.02 # Data bus utilization in percentage 321system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 322system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes | 298system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 299system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 300system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s 301system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 302system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 303system.physmem.busUtil 0.02 # Data bus utilization in percentage 304system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 305system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes |
| 323system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 324system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing 325system.physmem.readRowHits 685692 # Number of row buffer hits during reads 326system.physmem.writeRowHits 481982 # Number of row buffer hits during writes 327system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads 328system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes 329system.physmem.avgGap 22581201.38 # Average gap between requests | 306system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing 307system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing 308system.physmem.readRowHits 687053 # Number of row buffer hits during reads 309system.physmem.writeRowHits 479716 # Number of row buffer hits during writes 310system.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads 311system.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes 312system.physmem.avgGap 22596205.96 # Average gap between requests |
| 330system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined | 313system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined |
| 331system.physmem_0.actEnergy 3446827860 # Energy for activate commands per rank (pJ) 332system.physmem_0.preEnergy 1832028660 # Energy for precharge commands per rank (pJ) 333system.physmem_0.readEnergy 3331381200 # Energy for read commands per rank (pJ) 334system.physmem_0.writeEnergy 3115139400 # Energy for write commands per rank (pJ) 335system.physmem_0.refreshEnergy 41510941680.000008 # Energy for refresh commands per rank (pJ) 336system.physmem_0.actBackEnergy 46501533090 # Energy for active background per rank (pJ) 337system.physmem_0.preBackEnergy 2234866560 # Energy for precharge background per rank (pJ) 338system.physmem_0.actPowerDownEnergy 80625696300 # Energy for active power-down per rank (pJ) 339system.physmem_0.prePowerDownEnergy 57761558880 # Energy for precharge power-down per rank (pJ) 340system.physmem_0.selfRefreshEnergy 11279719224960 # Energy for self refresh per rank (pJ) 341system.physmem_0.totalEnergy 11520096687780 # Total energy per rank (pJ) 342system.physmem_0.averagePower 243.014314 # Core power per rank (mW) 343system.physmem_0.totalIdleTime 47297174723637 # Total Idle time Per DRAM Rank 344system.physmem_0.memoryStateTime::IDLE 3911587994 # Time in different power states 345system.physmem_0.memoryStateTime::REF 17636282000 # Time in different power states 346system.physmem_0.memoryStateTime::SREF 46969945639000 # Time in different power states 347system.physmem_0.memoryStateTime::PRE_PDN 150420602883 # Time in different power states 348system.physmem_0.memoryStateTime::ACT 86288423369 # Time in different power states 349system.physmem_0.memoryStateTime::ACT_PDN 176810425254 # Time in different power states 350system.physmem_1.actEnergy 3186367800 # Energy for activate commands per rank (pJ) 351system.physmem_1.preEnergy 1693590855 # Energy for precharge commands per rank (pJ) 352system.physmem_1.readEnergy 3288455520 # Energy for read commands per rank (pJ) 353system.physmem_1.writeEnergy 2989885500 # Energy for write commands per rank (pJ) 354system.physmem_1.refreshEnergy 39461117280.000008 # Energy for refresh commands per rank (pJ) 355system.physmem_1.actBackEnergy 47361781080 # Energy for active background per rank (pJ) 356system.physmem_1.preBackEnergy 2153404320 # Energy for precharge background per rank (pJ) 357system.physmem_1.actPowerDownEnergy 72224847060 # Energy for active power-down per rank (pJ) 358system.physmem_1.prePowerDownEnergy 55366694400 # Energy for precharge power-down per rank (pJ) 359system.physmem_1.selfRefreshEnergy 11285008491285 # Energy for self refresh per rank (pJ) 360system.physmem_1.totalEnergy 11512750460370 # Total energy per rank (pJ) 361system.physmem_1.averagePower 242.859346 # Core power per rank (mW) 362system.physmem_1.totalIdleTime 47295506898407 # Total Idle time Per DRAM Rank 363system.physmem_1.memoryStateTime::IDLE 3731843770 # Time in different power states 364system.physmem_1.memoryStateTime::REF 16766470000 # Time in different power states 365system.physmem_1.memoryStateTime::SREF 46992934432500 # Time in different power states 366system.physmem_1.memoryStateTime::PRE_PDN 144184093324 # Time in different power states 367system.physmem_1.memoryStateTime::ACT 89007700573 # Time in different power states 368system.physmem_1.memoryStateTime::ACT_PDN 158388420333 # Time in different power states 369system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 314system.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ) 315system.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ) 316system.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ) 317system.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ) 318system.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ) 319system.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ) 320system.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ) 321system.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ) 322system.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ) 323system.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ) 324system.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ) 325system.physmem_0.averagePower 243.004907 # Core power per rank (mW) 326system.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank 327system.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states 328system.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states 329system.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states 330system.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states 331system.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states 332system.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states 333system.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ) 334system.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ) 335system.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ) 336system.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ) 337system.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ) 338system.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ) 339system.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ) 340system.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ) 341system.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ) 342system.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ) 343system.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ) 344system.physmem_1.averagePower 242.918480 # Core power per rank (mW) 345system.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank 346system.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states 347system.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states 348system.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states 349system.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states 350system.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states 351system.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states 352system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 370system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 371system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 372system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 373system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 374system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 375system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 376system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 377system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 388system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 389system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 390system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 391system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 392system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 393system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 394system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 395system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) | 353system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 355system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 358system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 359system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 360system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 371system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 378system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) |
| 396system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 397system.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 398system.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 379system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 380system.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 381system.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 399system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 400system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 401system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 402system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 403system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 404system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 405system.cpu_clk_domain.clock 500 # Clock period in ticks | 382system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 383system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 384system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 385system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 386system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 387system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 388system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 406system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 389system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 428system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 429system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 430system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 431system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 432system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 433system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 434system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 435system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 411system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 414system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 415system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 416system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 417system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 418system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 436system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 437system.cpu0.dtb.walker.walks 110745 # Table walker walks requested 438system.cpu0.dtb.walker.walksLong 110745 # Table walker walks initiated with long descriptors 439system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10295 # Level at which table walker walks with long descriptors terminate 440system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84545 # Level at which table walker walks with long descriptors terminate 441system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting 442system.cpu0.dtb.walker.walkWaitTime::samples 110723 # Table walker wait (enqueue to first request) latency 443system.cpu0.dtb.walker.walkWaitTime::mean 0.234820 # Table walker wait (enqueue to first request) latency 444system.cpu0.dtb.walker.walkWaitTime::stdev 78.136585 # Table walker wait (enqueue to first request) latency 445system.cpu0.dtb.walker.walkWaitTime::0-2047 110722 100.00% 100.00% # Table walker wait (enqueue to first request) latency | 419system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 420system.cpu0.dtb.walker.walks 105104 # Table walker walks requested 421system.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors 422system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate 423system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate 424system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting 425system.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 446system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency | 429system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 447system.cpu0.dtb.walker.walkWaitTime::total 110723 # Table walker wait (enqueue to first request) latency 448system.cpu0.dtb.walker.walkCompletionTime::samples 94862 # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162 # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361 # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694 # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::0-65535 93763 98.84% 98.84% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::65536-131071 840 0.89% 99.73% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::131072-196607 113 0.12% 99.85% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.96% # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.98% # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency | 430system.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency |
| 459system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency | 441system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency |
| 460system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 461system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.01% 100.00% # Table walker service (enqueue to completion) latency 462system.cpu0.dtb.walker.walkCompletionTime::total 94862 # Table walker service (enqueue to completion) latency 463system.cpu0.dtb.walker.walksPending::samples -2682325288 # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::mean 2.121047 # Table walker pending requests distribution | 442system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution |
| 465system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution | 449system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution |
| 466system.cpu0.dtb.walker.walksPending::0 3007013124 -112.10% -112.10% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::1 -5689338412 212.10% 100.00% # Table walker pending requests distribution 468system.cpu0.dtb.walker.walksPending::total -2682325288 # Table walker pending requests distribution 469system.cpu0.dtb.walker.walkPageSizes::4K 84546 89.14% 89.14% # Table walker page sizes translated 470system.cpu0.dtb.walker.walkPageSizes::2M 10295 10.86% 100.00% # Table walker page sizes translated 471system.cpu0.dtb.walker.walkPageSizes::total 94841 # Table walker page sizes translated 472system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 110745 # Table walker requests started/completed, data/inst | 450system.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution 453system.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated 454system.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated 455system.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated 456system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst |
| 473system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 474system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 110745 # Table walker requests started/completed, data/inst 475system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94841 # Table walker requests started/completed, data/inst | 458system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst |
| 476system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 477system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94841 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.walker.walkRequestOrigin::total 205586 # Table walker requests started/completed, data/inst | 461system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst |
| 479system.cpu0.dtb.inst_hits 0 # ITB inst hits 480system.cpu0.dtb.inst_misses 0 # ITB inst misses | 463system.cpu0.dtb.inst_hits 0 # ITB inst hits 464system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 481system.cpu0.dtb.read_hits 86849149 # DTB read hits 482system.cpu0.dtb.read_misses 83538 # DTB read misses 483system.cpu0.dtb.write_hits 78785461 # DTB write hits 484system.cpu0.dtb.write_misses 27207 # DTB write misses | 465system.cpu0.dtb.read_hits 85250979 # DTB read hits 466system.cpu0.dtb.read_misses 79026 # DTB read misses 467system.cpu0.dtb.write_hits 77401552 # DTB write hits 468system.cpu0.dtb.write_misses 26078 # DTB write misses |
| 485system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 486system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 469system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 470system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 487system.cpu0.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID | 471system.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID |
| 488system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 472system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 489system.cpu0.dtb.flush_entries 37555 # Number of entries that have been flushed from TLB | 473system.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB |
| 490system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 474system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 491system.cpu0.dtb.prefetch_faults 4746 # Number of TLB faults due to prefetch | 475system.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch |
| 492system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 476system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 493system.cpu0.dtb.perms_faults 9443 # Number of TLB faults due to permissions restrictions 494system.cpu0.dtb.read_accesses 86932687 # DTB read accesses 495system.cpu0.dtb.write_accesses 78812668 # DTB write accesses | 477system.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions 478system.cpu0.dtb.read_accesses 85330005 # DTB read accesses 479system.cpu0.dtb.write_accesses 77427630 # DTB write accesses |
| 496system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 480system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 497system.cpu0.dtb.hits 165634610 # DTB hits 498system.cpu0.dtb.misses 110745 # DTB misses 499system.cpu0.dtb.accesses 165745355 # DTB accesses 500system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 481system.cpu0.dtb.hits 162652531 # DTB hits 482system.cpu0.dtb.misses 105104 # DTB misses 483system.cpu0.dtb.accesses 162757635 # DTB accesses 484system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 501system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 522system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 523system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 524system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 525system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 526system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 527system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 528system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 529system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 485system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 506system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 507system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 508system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 509system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 510system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 511system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 512system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 513system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 530system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 531system.cpu0.itb.walker.walks 57780 # Table walker walks requested 532system.cpu0.itb.walker.walksLong 57780 # Table walker walks initiated with long descriptors 533system.cpu0.itb.walker.walksLongTerminationLevel::Level2 572 # Level at which table walker walks with long descriptors terminate 534system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51544 # Level at which table walker walks with long descriptors terminate 535system.cpu0.itb.walker.walkWaitTime::samples 57780 # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::0 57780 100.00% 100.00% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::total 57780 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkCompletionTime::samples 52116 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::mean 25803.102694 # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726 # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518 # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::0-65535 51056 97.97% 97.97% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::65536-131071 692 1.33% 99.29% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::131072-196607 219 0.42% 99.71% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::196608-262143 60 0.12% 99.83% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.10% 99.93% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.95% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.96% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.96% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::589824-655359 14 0.03% 99.99% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::total 52116 # Table walker service (enqueue to completion) latency | 514system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 515system.cpu0.itb.walker.walks 55600 # Table walker walks requested 516system.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors 517system.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate 518system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate 519system.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency |
| 554system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution 555system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution | 537system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution 538system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution 539system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution |
| 557system.cpu0.itb.walker.walkPageSizes::4K 51544 98.90% 98.90% # Table walker page sizes translated 558system.cpu0.itb.walker.walkPageSizes::2M 572 1.10% 100.00% # Table walker page sizes translated 559system.cpu0.itb.walker.walkPageSizes::total 52116 # Table walker page sizes translated | 540system.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated 541system.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated 542system.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated |
| 560system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 543system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 561system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57780 # Table walker requests started/completed, data/inst 562system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57780 # Table walker requests started/completed, data/inst | 544system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst 545system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst |
| 563system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 546system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 564system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52116 # Table walker requests started/completed, data/inst 565system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52116 # Table walker requests started/completed, data/inst 566system.cpu0.itb.walker.walkRequestOrigin::total 109896 # Table walker requests started/completed, data/inst 567system.cpu0.itb.inst_hits 463942995 # ITB inst hits 568system.cpu0.itb.inst_misses 57780 # ITB inst misses | 547system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst 548system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst 549system.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst 550system.cpu0.itb.inst_hits 455710659 # ITB inst hits 551system.cpu0.itb.inst_misses 55600 # ITB inst misses |
| 569system.cpu0.itb.read_hits 0 # DTB read hits 570system.cpu0.itb.read_misses 0 # DTB read misses 571system.cpu0.itb.write_hits 0 # DTB write hits 572system.cpu0.itb.write_misses 0 # DTB write misses 573system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 574system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 552system.cpu0.itb.read_hits 0 # DTB read hits 553system.cpu0.itb.read_misses 0 # DTB read misses 554system.cpu0.itb.write_hits 0 # DTB write hits 555system.cpu0.itb.write_misses 0 # DTB write misses 556system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 575system.cpu0.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID | 558system.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID |
| 576system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 559system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 577system.cpu0.itb.flush_entries 26477 # Number of entries that have been flushed from TLB | 560system.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB |
| 578system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 579system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 580system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 582system.cpu0.itb.read_accesses 0 # DTB read accesses 583system.cpu0.itb.write_accesses 0 # DTB write accesses | 561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 564system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 565system.cpu0.itb.read_accesses 0 # DTB read accesses 566system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 584system.cpu0.itb.inst_accesses 464000775 # ITB inst accesses 585system.cpu0.itb.hits 463942995 # DTB hits 586system.cpu0.itb.misses 57780 # DTB misses 587system.cpu0.itb.accesses 464000775 # DTB accesses 588system.cpu0.numPwrStateTransitions 8984 # Number of power state transitions 589system.cpu0.pwrStateClkGateDist::samples 4492 # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::mean 10426010818.709705 # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::stdev 169261679723.888153 # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::underflows 3260 72.57% 72.57% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::1000-5e+10 1205 26.83% 99.40% # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::5e+10-1e+11 8 0.18% 99.58% # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.60% # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state 597system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::overflows 12 0.27% 100.00% # Distribution of time spent in the clock gated state | 567system.cpu0.itb.inst_accesses 455766259 # ITB inst accesses 568system.cpu0.itb.hits 455710659 # DTB hits 569system.cpu0.itb.misses 55600 # DTB misses 570system.cpu0.itb.accesses 455766259 # DTB accesses 571system.cpu0.numPwrStateTransitions 25961 # Number of power state transitions 572system.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state 573system.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state 574system.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state 575system.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state 576system.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state 577system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state 578system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state 579system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state 580system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 581system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 582system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 583system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 584system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state |
| 601system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 585system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 602system.cpu0.pwrStateClkGateDist::max_value 7033293863000 # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::total 4492 # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateResidencyTicks::ON 571372362856 # Cumulative time (in ticks) in various power states 605system.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644 # Cumulative time (in ticks) in various power states 606system.cpu0.numCycles 94810025915 # number of cpu cycles simulated | 586system.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state 587system.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state 588system.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states 589system.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states 590system.cpu0.numCycles 94809604801 # number of cpu cycles simulated |
| 607system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 608system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 609system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 591system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 592system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 593system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 610system.cpu0.kern.inst.quiesce 4492 # number of quiesce instructions executed 611system.cpu0.committedInsts 463690677 # Number of instructions committed 612system.cpu0.committedOps 544305781 # Number of ops (including micro ops) committed 613system.cpu0.num_int_alu_accesses 499985272 # Number of integer alu accesses 614system.cpu0.num_fp_alu_accesses 430429 # Number of float alu accesses 615system.cpu0.num_func_calls 27825312 # number of times a function call or return occured 616system.cpu0.num_conditional_control_insts 70353837 # number of instructions that are conditional controls 617system.cpu0.num_int_insts 499985272 # number of integer instructions 618system.cpu0.num_fp_insts 430429 # number of float instructions 619system.cpu0.num_int_register_reads 725660016 # number of times the integer registers were read 620system.cpu0.num_int_register_writes 396645033 # number of times the integer registers were written 621system.cpu0.num_fp_register_reads 713342 # number of times the floating registers were read 622system.cpu0.num_fp_register_writes 322808 # number of times the floating registers were written 623system.cpu0.num_cc_register_reads 121489824 # number of times the CC registers were read 624system.cpu0.num_cc_register_writes 121106505 # number of times the CC registers were written 625system.cpu0.num_mem_refs 165624912 # number of memory refs 626system.cpu0.num_load_insts 86844124 # Number of load instructions 627system.cpu0.num_store_insts 78780788 # Number of store instructions 628system.cpu0.num_idle_cycles 93667281189.358337 # Number of idle cycles 629system.cpu0.num_busy_cycles 1142744725.641658 # Number of busy cycles 630system.cpu0.not_idle_fraction 0.012053 # Percentage of non-idle cycles 631system.cpu0.idle_fraction 0.987947 # Percentage of idle cycles 632system.cpu0.Branches 103560532 # Number of branches fetched | 594system.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed 595system.cpu0.committedInsts 455440444 # Number of instructions committed 596system.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed 597system.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses 598system.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses 599system.cpu0.num_func_calls 27345084 # number of times a function call or return occured 600system.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls 601system.cpu0.num_int_insts 490602455 # number of integer instructions 602system.cpu0.num_fp_insts 409464 # number of float instructions 603system.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read 604system.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written 605system.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read 606system.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written 607system.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read 608system.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written 609system.cpu0.num_mem_refs 162644052 # number of memory refs 610system.cpu0.num_load_insts 85246888 # Number of load instructions 611system.cpu0.num_store_insts 77397164 # Number of store instructions 612system.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles 613system.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles 614system.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles 615system.cpu0.idle_fraction 0.988028 # Percentage of idle cycles 616system.cpu0.Branches 101837898 # Number of branches fetched |
| 633system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction | 617system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction |
| 634system.cpu0.op_class::IntAlu 377679680 69.35% 69.35% # Class of executed instruction 635system.cpu0.op_class::IntMult 1190205 0.22% 69.57% # Class of executed instruction 636system.cpu0.op_class::IntDiv 61578 0.01% 69.58% # Class of executed instruction 637system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction 638system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction 639system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction 640system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction 641system.cpu0.op_class::FloatMultAcc 0 0.00% 69.58% # Class of executed instruction 642system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction 643system.cpu0.op_class::FloatMisc 44848 0.01% 69.59% # Class of executed instruction 644system.cpu0.op_class::FloatSqrt 0 0.00% 69.59% # Class of executed instruction 645system.cpu0.op_class::SimdAdd 0 0.00% 69.59% # Class of executed instruction 646system.cpu0.op_class::SimdAddAcc 0 0.00% 69.59% # Class of executed instruction 647system.cpu0.op_class::SimdAlu 0 0.00% 69.59% # Class of executed instruction 648system.cpu0.op_class::SimdCmp 0 0.00% 69.59% # Class of executed instruction 649system.cpu0.op_class::SimdCvt 0 0.00% 69.59% # Class of executed instruction 650system.cpu0.op_class::SimdMisc 0 0.00% 69.59% # Class of executed instruction 651system.cpu0.op_class::SimdMult 0 0.00% 69.59% # Class of executed instruction 652system.cpu0.op_class::SimdMultAcc 0 0.00% 69.59% # Class of executed instruction 653system.cpu0.op_class::SimdShift 0 0.00% 69.59% # Class of executed instruction 654system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.59% # Class of executed instruction 655system.cpu0.op_class::SimdSqrt 0 0.00% 69.59% # Class of executed instruction 656system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.59% # Class of executed instruction 657system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.59% # Class of executed instruction 658system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.59% # Class of executed instruction 659system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.59% # Class of executed instruction 660system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.59% # Class of executed instruction 661system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.59% # Class of executed instruction 662system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction 663system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction 664system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction 665system.cpu0.op_class::MemRead 86795135 15.94% 85.53% # Class of executed instruction 666system.cpu0.op_class::MemWrite 78444196 14.40% 99.93% # Class of executed instruction 667system.cpu0.op_class::FloatMemRead 48989 0.01% 99.94% # Class of executed instruction 668system.cpu0.op_class::FloatMemWrite 336592 0.06% 100.00% # Class of executed instruction | 618system.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction 619system.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction 620system.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction 621system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction 622system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction 623system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction 624system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction 625system.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction 626system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction 627system.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction 628system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction 629system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction 630system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction 631system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction 632system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction 633system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction 634system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction 635system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction 636system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction 637system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction 638system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction 639system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction 640system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction 641system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction 642system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction 643system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction 644system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction 645system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction 646system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction 647system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction 648system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction 649system.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction 650system.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction 651system.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction 652system.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction |
| 669system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 670system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 653system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 654system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 671system.cpu0.op_class::total 544601223 # Class of executed instruction 672system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 673system.cpu0.dcache.tags.replacements 5731745 # number of replacements 674system.cpu0.dcache.tags.tagsinuse 479.859189 # Cycle average of tags in use 675system.cpu0.dcache.tags.total_refs 159669170 # Total number of references to valid blocks. 676system.cpu0.dcache.tags.sampled_refs 5732255 # Sample count of references to valid blocks. 677system.cpu0.dcache.tags.avg_refs 27.854513 # Average number of references to valid blocks. | 655system.cpu0.op_class::total 534571495 # Class of executed instruction 656system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 657system.cpu0.dcache.tags.replacements 5548235 # number of replacements 658system.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use 659system.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks. 660system.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks. 661system.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks. |
| 678system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. | 662system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. |
| 679system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.859189 # Average occupied blocks per requestor 680system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937225 # Average percentage of cache occupancy 681system.cpu0.dcache.tags.occ_percent::total 0.937225 # Average percentage of cache occupancy 682system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 683system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 684system.cpu0.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 685system.cpu0.dcache.tags.age_task_id_blocks_1024::2 452 # Occupied blocks per task id 686system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 687system.cpu0.dcache.tags.tag_accesses 337018109 # Number of tag accesses 688system.cpu0.dcache.tags.data_accesses 337018109 # Number of data accesses 689system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 690system.cpu0.dcache.ReadReq_hits::cpu0.data 80850678 # number of ReadReq hits 691system.cpu0.dcache.ReadReq_hits::total 80850678 # number of ReadReq hits 692system.cpu0.dcache.WriteReq_hits::cpu0.data 74290365 # number of WriteReq hits 693system.cpu0.dcache.WriteReq_hits::total 74290365 # number of WriteReq hits 694system.cpu0.dcache.SoftPFReq_hits::cpu0.data 206988 # number of SoftPFReq hits 695system.cpu0.dcache.SoftPFReq_hits::total 206988 # number of SoftPFReq hits 696system.cpu0.dcache.WriteLineReq_hits::cpu0.data 237888 # number of WriteLineReq hits 697system.cpu0.dcache.WriteLineReq_hits::total 237888 # number of WriteLineReq hits 698system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1848102 # number of LoadLockedReq hits 699system.cpu0.dcache.LoadLockedReq_hits::total 1848102 # number of LoadLockedReq hits 700system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1813975 # number of StoreCondReq hits 701system.cpu0.dcache.StoreCondReq_hits::total 1813975 # number of StoreCondReq hits 702system.cpu0.dcache.demand_hits::cpu0.data 155378931 # number of demand (read+write) hits 703system.cpu0.dcache.demand_hits::total 155378931 # number of demand (read+write) hits 704system.cpu0.dcache.overall_hits::cpu0.data 155585919 # number of overall hits 705system.cpu0.dcache.overall_hits::total 155585919 # number of overall hits 706system.cpu0.dcache.ReadReq_misses::cpu0.data 3109712 # number of ReadReq misses 707system.cpu0.dcache.ReadReq_misses::total 3109712 # number of ReadReq misses 708system.cpu0.dcache.WriteReq_misses::cpu0.data 1421405 # number of WriteReq misses 709system.cpu0.dcache.WriteReq_misses::total 1421405 # number of WriteReq misses 710system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649654 # number of SoftPFReq misses 711system.cpu0.dcache.SoftPFReq_misses::total 649654 # number of SoftPFReq misses 712system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796576 # number of WriteLineReq misses 713system.cpu0.dcache.WriteLineReq_misses::total 796576 # number of WriteLineReq misses 714system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167654 # number of LoadLockedReq misses 715system.cpu0.dcache.LoadLockedReq_misses::total 167654 # number of LoadLockedReq misses 716system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200528 # number of StoreCondReq misses 717system.cpu0.dcache.StoreCondReq_misses::total 200528 # number of StoreCondReq misses 718system.cpu0.dcache.demand_misses::cpu0.data 5327693 # number of demand (read+write) misses 719system.cpu0.dcache.demand_misses::total 5327693 # number of demand (read+write) misses 720system.cpu0.dcache.overall_misses::cpu0.data 5977347 # number of overall misses 721system.cpu0.dcache.overall_misses::total 5977347 # number of overall misses 722system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 48841831500 # number of ReadReq miss cycles 723system.cpu0.dcache.ReadReq_miss_latency::total 48841831500 # number of ReadReq miss cycles 724system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 30112535000 # number of WriteReq miss cycles 725system.cpu0.dcache.WriteReq_miss_latency::total 30112535000 # number of WriteReq miss cycles 726system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25700725500 # number of WriteLineReq miss cycles 727system.cpu0.dcache.WriteLineReq_miss_latency::total 25700725500 # number of WriteLineReq miss cycles 728system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2575322000 # number of LoadLockedReq miss cycles 729system.cpu0.dcache.LoadLockedReq_miss_latency::total 2575322000 # number of LoadLockedReq miss cycles 730system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4758884500 # number of StoreCondReq miss cycles 731system.cpu0.dcache.StoreCondReq_miss_latency::total 4758884500 # number of StoreCondReq miss cycles 732system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2246000 # number of StoreCondFailReq miss cycles 733system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles 734system.cpu0.dcache.demand_miss_latency::cpu0.data 104655092000 # number of demand (read+write) miss cycles 735system.cpu0.dcache.demand_miss_latency::total 104655092000 # number of demand (read+write) miss cycles 736system.cpu0.dcache.overall_miss_latency::cpu0.data 104655092000 # number of overall miss cycles 737system.cpu0.dcache.overall_miss_latency::total 104655092000 # number of overall miss cycles 738system.cpu0.dcache.ReadReq_accesses::cpu0.data 83960390 # number of ReadReq accesses(hits+misses) 739system.cpu0.dcache.ReadReq_accesses::total 83960390 # number of ReadReq accesses(hits+misses) 740system.cpu0.dcache.WriteReq_accesses::cpu0.data 75711770 # number of WriteReq accesses(hits+misses) 741system.cpu0.dcache.WriteReq_accesses::total 75711770 # number of WriteReq accesses(hits+misses) 742system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 856642 # number of SoftPFReq accesses(hits+misses) 743system.cpu0.dcache.SoftPFReq_accesses::total 856642 # number of SoftPFReq accesses(hits+misses) 744system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1034464 # number of WriteLineReq accesses(hits+misses) 745system.cpu0.dcache.WriteLineReq_accesses::total 1034464 # number of WriteLineReq accesses(hits+misses) 746system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015756 # number of LoadLockedReq accesses(hits+misses) 747system.cpu0.dcache.LoadLockedReq_accesses::total 2015756 # number of LoadLockedReq accesses(hits+misses) 748system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014503 # number of StoreCondReq accesses(hits+misses) 749system.cpu0.dcache.StoreCondReq_accesses::total 2014503 # number of StoreCondReq accesses(hits+misses) 750system.cpu0.dcache.demand_accesses::cpu0.data 160706624 # number of demand (read+write) accesses 751system.cpu0.dcache.demand_accesses::total 160706624 # number of demand (read+write) accesses 752system.cpu0.dcache.overall_accesses::cpu0.data 161563266 # number of overall (read+write) accesses 753system.cpu0.dcache.overall_accesses::total 161563266 # number of overall (read+write) accesses 754system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037038 # miss rate for ReadReq accesses 755system.cpu0.dcache.ReadReq_miss_rate::total 0.037038 # miss rate for ReadReq accesses 756system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018774 # miss rate for WriteReq accesses 757system.cpu0.dcache.WriteReq_miss_rate::total 0.018774 # miss rate for WriteReq accesses 758system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758373 # miss rate for SoftPFReq accesses 759system.cpu0.dcache.SoftPFReq_miss_rate::total 0.758373 # miss rate for SoftPFReq accesses 760system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.770037 # miss rate for WriteLineReq accesses 761system.cpu0.dcache.WriteLineReq_miss_rate::total 0.770037 # miss rate for WriteLineReq accesses 762system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083172 # miss rate for LoadLockedReq accesses 763system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083172 # miss rate for LoadLockedReq accesses 764system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses 765system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses 766system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033152 # miss rate for demand accesses 767system.cpu0.dcache.demand_miss_rate::total 0.033152 # miss rate for demand accesses 768system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036997 # miss rate for overall accesses 769system.cpu0.dcache.overall_miss_rate::total 0.036997 # miss rate for overall accesses 770system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15706.223438 # average ReadReq miss latency 771system.cpu0.dcache.ReadReq_avg_miss_latency::total 15706.223438 # average ReadReq miss latency 772system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21185.049300 # average WriteReq miss latency 773system.cpu0.dcache.WriteReq_avg_miss_latency::total 21185.049300 # average WriteReq miss latency 774system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32263.996781 # average WriteLineReq miss latency 775system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32263.996781 # average WriteLineReq miss latency 776system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.933828 # average LoadLockedReq miss latency 777system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.933828 # average LoadLockedReq miss latency 778system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23731.770626 # average StoreCondReq miss latency 779system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23731.770626 # average StoreCondReq miss latency | 663system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.308001 # Average occupied blocks per requestor 664system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992789 # Average percentage of cache occupancy 665system.cpu0.dcache.tags.occ_percent::total 0.992789 # Average percentage of cache occupancy 666system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 667system.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id 668system.cpu0.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 669system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id 670system.cpu0.dcache.tags.tag_accesses 330814481 # Number of tag accesses 671system.cpu0.dcache.tags.data_accesses 330814481 # Number of data accesses 672system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 673system.cpu0.dcache.ReadReq_hits::cpu0.data 79405965 # number of ReadReq hits 674system.cpu0.dcache.ReadReq_hits::total 79405965 # number of ReadReq hits 675system.cpu0.dcache.WriteReq_hits::cpu0.data 72971377 # number of WriteReq hits 676system.cpu0.dcache.WriteReq_hits::total 72971377 # number of WriteReq hits 677system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204972 # number of SoftPFReq hits 678system.cpu0.dcache.SoftPFReq_hits::total 204972 # number of SoftPFReq hits 679system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263219 # number of WriteLineReq hits 680system.cpu0.dcache.WriteLineReq_hits::total 263219 # number of WriteLineReq hits 681system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813440 # number of LoadLockedReq hits 682system.cpu0.dcache.LoadLockedReq_hits::total 1813440 # number of LoadLockedReq hits 683system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787735 # number of StoreCondReq hits 684system.cpu0.dcache.StoreCondReq_hits::total 1787735 # number of StoreCondReq hits 685system.cpu0.dcache.demand_hits::cpu0.data 152640561 # number of demand (read+write) hits 686system.cpu0.dcache.demand_hits::total 152640561 # number of demand (read+write) hits 687system.cpu0.dcache.overall_hits::cpu0.data 152845533 # number of overall hits 688system.cpu0.dcache.overall_hits::total 152845533 # number of overall hits 689system.cpu0.dcache.ReadReq_misses::cpu0.data 3006341 # number of ReadReq misses 690system.cpu0.dcache.ReadReq_misses::total 3006341 # number of ReadReq misses 691system.cpu0.dcache.WriteReq_misses::cpu0.data 1360477 # number of WriteReq misses 692system.cpu0.dcache.WriteReq_misses::total 1360477 # number of WriteReq misses 693system.cpu0.dcache.SoftPFReq_misses::cpu0.data 626311 # number of SoftPFReq misses 694system.cpu0.dcache.SoftPFReq_misses::total 626311 # number of SoftPFReq misses 695system.cpu0.dcache.WriteLineReq_misses::cpu0.data 794287 # number of WriteLineReq misses 696system.cpu0.dcache.WriteLineReq_misses::total 794287 # number of WriteLineReq misses 697system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164142 # number of LoadLockedReq misses 698system.cpu0.dcache.LoadLockedReq_misses::total 164142 # number of LoadLockedReq misses 699system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188530 # number of StoreCondReq misses 700system.cpu0.dcache.StoreCondReq_misses::total 188530 # number of StoreCondReq misses 701system.cpu0.dcache.demand_misses::cpu0.data 5161105 # number of demand (read+write) misses 702system.cpu0.dcache.demand_misses::total 5161105 # number of demand (read+write) misses 703system.cpu0.dcache.overall_misses::cpu0.data 5787416 # number of overall misses 704system.cpu0.dcache.overall_misses::total 5787416 # number of overall misses 705system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47850868000 # number of ReadReq miss cycles 706system.cpu0.dcache.ReadReq_miss_latency::total 47850868000 # number of ReadReq miss cycles 707system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29377875000 # number of WriteReq miss cycles 708system.cpu0.dcache.WriteReq_miss_latency::total 29377875000 # number of WriteReq miss cycles 709system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25259415500 # number of WriteLineReq miss cycles 710system.cpu0.dcache.WriteLineReq_miss_latency::total 25259415500 # number of WriteLineReq miss cycles 711system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2486803500 # number of LoadLockedReq miss cycles 712system.cpu0.dcache.LoadLockedReq_miss_latency::total 2486803500 # number of LoadLockedReq miss cycles 713system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4498365000 # number of StoreCondReq miss cycles 714system.cpu0.dcache.StoreCondReq_miss_latency::total 4498365000 # number of StoreCondReq miss cycles 715system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2057500 # number of StoreCondFailReq miss cycles 716system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2057500 # number of StoreCondFailReq miss cycles 717system.cpu0.dcache.demand_miss_latency::cpu0.data 102488158500 # number of demand (read+write) miss cycles 718system.cpu0.dcache.demand_miss_latency::total 102488158500 # number of demand (read+write) miss cycles 719system.cpu0.dcache.overall_miss_latency::cpu0.data 102488158500 # number of overall miss cycles 720system.cpu0.dcache.overall_miss_latency::total 102488158500 # number of overall miss cycles 721system.cpu0.dcache.ReadReq_accesses::cpu0.data 82412306 # number of ReadReq accesses(hits+misses) 722system.cpu0.dcache.ReadReq_accesses::total 82412306 # number of ReadReq accesses(hits+misses) 723system.cpu0.dcache.WriteReq_accesses::cpu0.data 74331854 # number of WriteReq accesses(hits+misses) 724system.cpu0.dcache.WriteReq_accesses::total 74331854 # number of WriteReq accesses(hits+misses) 725system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 831283 # number of SoftPFReq accesses(hits+misses) 726system.cpu0.dcache.SoftPFReq_accesses::total 831283 # number of SoftPFReq accesses(hits+misses) 727system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1057506 # number of WriteLineReq accesses(hits+misses) 728system.cpu0.dcache.WriteLineReq_accesses::total 1057506 # number of WriteLineReq accesses(hits+misses) 729system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1977582 # number of LoadLockedReq accesses(hits+misses) 730system.cpu0.dcache.LoadLockedReq_accesses::total 1977582 # number of LoadLockedReq accesses(hits+misses) 731system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1976265 # number of StoreCondReq accesses(hits+misses) 732system.cpu0.dcache.StoreCondReq_accesses::total 1976265 # number of StoreCondReq accesses(hits+misses) 733system.cpu0.dcache.demand_accesses::cpu0.data 157801666 # number of demand (read+write) accesses 734system.cpu0.dcache.demand_accesses::total 157801666 # number of demand (read+write) accesses 735system.cpu0.dcache.overall_accesses::cpu0.data 158632949 # number of overall (read+write) accesses 736system.cpu0.dcache.overall_accesses::total 158632949 # number of overall (read+write) accesses 737system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036479 # miss rate for ReadReq accesses 738system.cpu0.dcache.ReadReq_miss_rate::total 0.036479 # miss rate for ReadReq accesses 739system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018303 # miss rate for WriteReq accesses 740system.cpu0.dcache.WriteReq_miss_rate::total 0.018303 # miss rate for WriteReq accesses 741system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.753427 # miss rate for SoftPFReq accesses 742system.cpu0.dcache.SoftPFReq_miss_rate::total 0.753427 # miss rate for SoftPFReq accesses 743system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.751095 # miss rate for WriteLineReq accesses 744system.cpu0.dcache.WriteLineReq_miss_rate::total 0.751095 # miss rate for WriteLineReq accesses 745system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083001 # miss rate for LoadLockedReq accesses 746system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083001 # miss rate for LoadLockedReq accesses 747system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095397 # miss rate for StoreCondReq accesses 748system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095397 # miss rate for StoreCondReq accesses 749system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032706 # miss rate for demand accesses 750system.cpu0.dcache.demand_miss_rate::total 0.032706 # miss rate for demand accesses 751system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036483 # miss rate for overall accesses 752system.cpu0.dcache.overall_miss_rate::total 0.036483 # miss rate for overall accesses 753system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency 754system.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency 755system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21593.804967 # average WriteReq miss latency 756system.cpu0.dcache.WriteReq_avg_miss_latency::total 21593.804967 # average WriteReq miss latency 757system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31801.370915 # average WriteLineReq miss latency 758system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31801.370915 # average WriteLineReq miss latency 759system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15150.318017 # average LoadLockedReq miss latency 760system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15150.318017 # average LoadLockedReq miss latency 761system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23860.207924 # average StoreCondReq miss latency 762system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency |
| 780system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 781system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 763system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 764system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 782system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19643.604089 # average overall miss latency 783system.cpu0.dcache.demand_avg_miss_latency::total 19643.604089 # average overall miss latency 784system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17508.619125 # average overall miss latency 785system.cpu0.dcache.overall_avg_miss_latency::total 17508.619125 # average overall miss latency | 765system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19857.793728 # average overall miss latency 766system.cpu0.dcache.demand_avg_miss_latency::total 19857.793728 # average overall miss latency 767system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17708.794132 # average overall miss latency 768system.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency |
| 786system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 787system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 788system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 789system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 790system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 791system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 769system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 792system.cpu0.dcache.writebacks::writebacks 5731745 # number of writebacks 793system.cpu0.dcache.writebacks::total 5731745 # number of writebacks 794system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26385 # number of ReadReq MSHR hits 795system.cpu0.dcache.ReadReq_mshr_hits::total 26385 # number of ReadReq MSHR hits 796system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21245 # number of WriteReq MSHR hits 797system.cpu0.dcache.WriteReq_mshr_hits::total 21245 # number of WriteReq MSHR hits 798system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44162 # number of LoadLockedReq MSHR hits 799system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44162 # number of LoadLockedReq MSHR hits 800system.cpu0.dcache.demand_mshr_hits::cpu0.data 47630 # number of demand (read+write) MSHR hits 801system.cpu0.dcache.demand_mshr_hits::total 47630 # number of demand (read+write) MSHR hits 802system.cpu0.dcache.overall_mshr_hits::cpu0.data 47630 # number of overall MSHR hits 803system.cpu0.dcache.overall_mshr_hits::total 47630 # number of overall MSHR hits 804system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3083327 # number of ReadReq MSHR misses 805system.cpu0.dcache.ReadReq_mshr_misses::total 3083327 # number of ReadReq MSHR misses 806system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1400160 # number of WriteReq MSHR misses 807system.cpu0.dcache.WriteReq_mshr_misses::total 1400160 # number of WriteReq MSHR misses 808system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648080 # number of SoftPFReq MSHR misses 809system.cpu0.dcache.SoftPFReq_mshr_misses::total 648080 # number of SoftPFReq MSHR misses 810system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796576 # number of WriteLineReq MSHR misses 811system.cpu0.dcache.WriteLineReq_mshr_misses::total 796576 # number of WriteLineReq MSHR misses 812system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123492 # number of LoadLockedReq MSHR misses 813system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123492 # number of LoadLockedReq MSHR misses 814system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200528 # number of StoreCondReq MSHR misses 815system.cpu0.dcache.StoreCondReq_mshr_misses::total 200528 # number of StoreCondReq MSHR misses 816system.cpu0.dcache.demand_mshr_misses::cpu0.data 5280063 # number of demand (read+write) MSHR misses 817system.cpu0.dcache.demand_mshr_misses::total 5280063 # number of demand (read+write) MSHR misses 818system.cpu0.dcache.overall_mshr_misses::cpu0.data 5928143 # number of overall MSHR misses 819system.cpu0.dcache.overall_mshr_misses::total 5928143 # number of overall MSHR misses 820system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable 821system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16381 # number of ReadReq MSHR uncacheable 822system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 823system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable 824system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses 825system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34075 # number of overall MSHR uncacheable misses 826system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44323294000 # number of ReadReq MSHR miss cycles 827system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44323294000 # number of ReadReq MSHR miss cycles 828system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28148510000 # number of WriteReq MSHR miss cycles 829system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28148510000 # number of WriteReq MSHR miss cycles 830system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14944693500 # number of SoftPFReq MSHR miss cycles 831system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14944693500 # number of SoftPFReq MSHR miss cycles 832system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24904149500 # number of WriteLineReq MSHR miss cycles 833system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24904149500 # number of WriteLineReq MSHR miss cycles 834system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1681387500 # number of LoadLockedReq MSHR miss cycles 835system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1681387500 # number of LoadLockedReq MSHR miss cycles 836system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4558410500 # number of StoreCondReq MSHR miss cycles 837system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4558410500 # number of StoreCondReq MSHR miss cycles 838system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2192000 # number of StoreCondFailReq MSHR miss cycles 839system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2192000 # number of StoreCondFailReq MSHR miss cycles 840system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 97375953500 # number of demand (read+write) MSHR miss cycles 841system.cpu0.dcache.demand_mshr_miss_latency::total 97375953500 # number of demand (read+write) MSHR miss cycles 842system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000 # number of overall MSHR miss cycles 843system.cpu0.dcache.overall_mshr_miss_latency::total 112320647000 # number of overall MSHR miss cycles 844system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3040589500 # number of ReadReq MSHR uncacheable cycles 845system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3040589500 # number of ReadReq MSHR uncacheable cycles 846system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3040589500 # number of overall MSHR uncacheable cycles 847system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3040589500 # number of overall MSHR uncacheable cycles 848system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036724 # mshr miss rate for ReadReq accesses 849system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036724 # mshr miss rate for ReadReq accesses 850system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018493 # mshr miss rate for WriteReq accesses 851system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018493 # mshr miss rate for WriteReq accesses 852system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756535 # mshr miss rate for SoftPFReq accesses 853system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756535 # mshr miss rate for SoftPFReq accesses 854system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.770037 # mshr miss rate for WriteLineReq accesses 855system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.770037 # mshr miss rate for WriteLineReq accesses 856system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061263 # mshr miss rate for LoadLockedReq accesses 857system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061263 # mshr miss rate for LoadLockedReq accesses 858system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099542 # mshr miss rate for StoreCondReq accesses 859system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099542 # mshr miss rate for StoreCondReq accesses 860system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032855 # mshr miss rate for demand accesses 861system.cpu0.dcache.demand_mshr_miss_rate::total 0.032855 # mshr miss rate for demand accesses 862system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for overall accesses 863system.cpu0.dcache.overall_mshr_miss_rate::total 0.036692 # mshr miss rate for overall accesses 864system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906 # average ReadReq mshr miss latency 865system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906 # average ReadReq mshr miss latency 866system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996 # average WriteReq mshr miss latency 867system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996 # average WriteReq mshr miss latency 868system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703 # average SoftPFReq mshr miss latency 869system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703 # average SoftPFReq mshr miss latency 870system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781 # average WriteLineReq mshr miss latency 871system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781 # average WriteLineReq mshr miss latency 872system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651 # average LoadLockedReq mshr miss latency 873system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651 # average LoadLockedReq mshr miss latency 874system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915 # average StoreCondReq mshr miss latency 875system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915 # average StoreCondReq mshr miss latency | 775system.cpu0.dcache.writebacks::writebacks 5548235 # number of writebacks 776system.cpu0.dcache.writebacks::total 5548235 # number of writebacks 777system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26826 # number of ReadReq MSHR hits 778system.cpu0.dcache.ReadReq_mshr_hits::total 26826 # number of ReadReq MSHR hits 779system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21220 # number of WriteReq MSHR hits 780system.cpu0.dcache.WriteReq_mshr_hits::total 21220 # number of WriteReq MSHR hits 781system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43038 # number of LoadLockedReq MSHR hits 782system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43038 # number of LoadLockedReq MSHR hits 783system.cpu0.dcache.demand_mshr_hits::cpu0.data 48046 # number of demand (read+write) MSHR hits 784system.cpu0.dcache.demand_mshr_hits::total 48046 # number of demand (read+write) MSHR hits 785system.cpu0.dcache.overall_mshr_hits::cpu0.data 48046 # number of overall MSHR hits 786system.cpu0.dcache.overall_mshr_hits::total 48046 # number of overall MSHR hits 787system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2979515 # number of ReadReq MSHR misses 788system.cpu0.dcache.ReadReq_mshr_misses::total 2979515 # number of ReadReq MSHR misses 789system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1339257 # number of WriteReq MSHR misses 790system.cpu0.dcache.WriteReq_mshr_misses::total 1339257 # number of WriteReq MSHR misses 791system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 624730 # number of SoftPFReq MSHR misses 792system.cpu0.dcache.SoftPFReq_mshr_misses::total 624730 # number of SoftPFReq MSHR misses 793system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 794287 # number of WriteLineReq MSHR misses 794system.cpu0.dcache.WriteLineReq_mshr_misses::total 794287 # number of WriteLineReq MSHR misses 795system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121104 # number of LoadLockedReq MSHR misses 796system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses 797system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188530 # number of StoreCondReq MSHR misses 798system.cpu0.dcache.StoreCondReq_mshr_misses::total 188530 # number of StoreCondReq MSHR misses 799system.cpu0.dcache.demand_mshr_misses::cpu0.data 5113059 # number of demand (read+write) MSHR misses 800system.cpu0.dcache.demand_mshr_misses::total 5113059 # number of demand (read+write) MSHR misses 801system.cpu0.dcache.overall_mshr_misses::cpu0.data 5737789 # number of overall MSHR misses 802system.cpu0.dcache.overall_mshr_misses::total 5737789 # number of overall MSHR misses 803system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable 804system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable 805system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable 806system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable 807system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses 808system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59187 # number of overall MSHR uncacheable misses 809system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43367868500 # number of ReadReq MSHR miss cycles 810system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43367868500 # number of ReadReq MSHR miss cycles 811system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27478579500 # number of WriteReq MSHR miss cycles 812system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27478579500 # number of WriteReq MSHR miss cycles 813system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14655261000 # number of SoftPFReq MSHR miss cycles 814system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14655261000 # number of SoftPFReq MSHR miss cycles 815system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24465128500 # number of WriteLineReq MSHR miss cycles 816system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24465128500 # number of WriteLineReq MSHR miss cycles 817system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1605767000 # number of LoadLockedReq MSHR miss cycles 818system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles 819system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4309885000 # number of StoreCondReq MSHR miss cycles 820system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4309885000 # number of StoreCondReq MSHR miss cycles 821system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2007500 # number of StoreCondFailReq MSHR miss cycles 822system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2007500 # number of StoreCondFailReq MSHR miss cycles 823system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95311576500 # number of demand (read+write) MSHR miss cycles 824system.cpu0.dcache.demand_mshr_miss_latency::total 95311576500 # number of demand (read+write) MSHR miss cycles 825system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109966837500 # number of overall MSHR miss cycles 826system.cpu0.dcache.overall_mshr_miss_latency::total 109966837500 # number of overall MSHR miss cycles 827system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5687970000 # number of ReadReq MSHR uncacheable cycles 828system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles 829system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles 830system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles 831system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses 832system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses 833system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018017 # mshr miss rate for WriteReq accesses 834system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018017 # mshr miss rate for WriteReq accesses 835system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.751525 # mshr miss rate for SoftPFReq accesses 836system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751525 # mshr miss rate for SoftPFReq accesses 837system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.751095 # mshr miss rate for WriteLineReq accesses 838system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.751095 # mshr miss rate for WriteLineReq accesses 839system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061238 # mshr miss rate for LoadLockedReq accesses 840system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061238 # mshr miss rate for LoadLockedReq accesses 841system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095397 # mshr miss rate for StoreCondReq accesses 842system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095397 # mshr miss rate for StoreCondReq accesses 843system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032402 # mshr miss rate for demand accesses 844system.cpu0.dcache.demand_mshr_miss_rate::total 0.032402 # mshr miss rate for demand accesses 845system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036170 # mshr miss rate for overall accesses 846system.cpu0.dcache.overall_mshr_miss_rate::total 0.036170 # mshr miss rate for overall accesses 847system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14555.344914 # average ReadReq mshr miss latency 848system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14555.344914 # average ReadReq mshr miss latency 849system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20517.779261 # average WriteReq mshr miss latency 850system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20517.779261 # average WriteReq mshr miss latency 851system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23458.551694 # average SoftPFReq mshr miss latency 852system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency 853system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30801.370915 # average WriteLineReq mshr miss latency 854system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30801.370915 # average WriteLineReq mshr miss latency 855system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13259.405139 # average LoadLockedReq mshr miss latency 856system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency 857system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22860.473134 # average StoreCondReq mshr miss latency 858system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22860.473134 # average StoreCondReq mshr miss latency |
| 876system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 877system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 859system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 860system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 878system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387 # average overall mshr miss latency 879system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387 # average overall mshr miss latency 880system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509 # average overall mshr miss latency 881system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509 # average overall mshr miss latency 882system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684 # average ReadReq mshr uncacheable latency 883system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684 # average ReadReq mshr uncacheable latency 884system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058 # average overall mshr uncacheable latency 885system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058 # average overall mshr uncacheable latency 886system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 887system.cpu0.icache.tags.replacements 4959559 # number of replacements 888system.cpu0.icache.tags.tagsinuse 511.903947 # Cycle average of tags in use 889system.cpu0.icache.tags.total_refs 458982923 # Total number of references to valid blocks. 890system.cpu0.icache.tags.sampled_refs 4960071 # Sample count of references to valid blocks. 891system.cpu0.icache.tags.avg_refs 92.535555 # Average number of references to valid blocks. 892system.cpu0.icache.tags.warmup_cycle 30768955000 # Cycle when the warmup percentage was hit. 893system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903947 # Average occupied blocks per requestor | 861system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18640.812965 # average overall mshr miss latency 862system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18640.812965 # average overall mshr miss latency 863system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19165.367967 # average overall mshr miss latency 864system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19165.367967 # average overall mshr miss latency 865system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190692.302535 # average ReadReq mshr uncacheable latency 866system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190692.302535 # average ReadReq mshr uncacheable latency 867system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96101.677733 # average overall mshr uncacheable latency 868system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96101.677733 # average overall mshr uncacheable latency 869system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 870system.cpu0.icache.tags.replacements 4928137 # number of replacements 871system.cpu0.icache.tags.tagsinuse 511.903899 # Cycle average of tags in use 872system.cpu0.icache.tags.total_refs 450782010 # Total number of references to valid blocks. 873system.cpu0.icache.tags.sampled_refs 4928649 # Sample count of references to valid blocks. 874system.cpu0.icache.tags.avg_refs 91.461577 # Average number of references to valid blocks. 875system.cpu0.icache.tags.warmup_cycle 30794452000 # Cycle when the warmup percentage was hit. 876system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903899 # Average occupied blocks per requestor |
| 894system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy 895system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy 896system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 877system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy 878system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy 879system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 897system.cpu0.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 898system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 899system.cpu0.icache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id 900system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id | 880system.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id 881system.cpu0.icache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id |
| 901system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 882system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 902system.cpu0.icache.tags.tag_accesses 932846061 # Number of tag accesses 903system.cpu0.icache.tags.data_accesses 932846061 # Number of data accesses 904system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 905system.cpu0.icache.ReadReq_hits::cpu0.inst 458982923 # number of ReadReq hits 906system.cpu0.icache.ReadReq_hits::total 458982923 # number of ReadReq hits 907system.cpu0.icache.demand_hits::cpu0.inst 458982923 # number of demand (read+write) hits 908system.cpu0.icache.demand_hits::total 458982923 # number of demand (read+write) hits 909system.cpu0.icache.overall_hits::cpu0.inst 458982923 # number of overall hits 910system.cpu0.icache.overall_hits::total 458982923 # number of overall hits 911system.cpu0.icache.ReadReq_misses::cpu0.inst 4960072 # number of ReadReq misses 912system.cpu0.icache.ReadReq_misses::total 4960072 # number of ReadReq misses 913system.cpu0.icache.demand_misses::cpu0.inst 4960072 # number of demand (read+write) misses 914system.cpu0.icache.demand_misses::total 4960072 # number of demand (read+write) misses 915system.cpu0.icache.overall_misses::cpu0.inst 4960072 # number of overall misses 916system.cpu0.icache.overall_misses::total 4960072 # number of overall misses 917system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54306348500 # number of ReadReq miss cycles 918system.cpu0.icache.ReadReq_miss_latency::total 54306348500 # number of ReadReq miss cycles 919system.cpu0.icache.demand_miss_latency::cpu0.inst 54306348500 # number of demand (read+write) miss cycles 920system.cpu0.icache.demand_miss_latency::total 54306348500 # number of demand (read+write) miss cycles 921system.cpu0.icache.overall_miss_latency::cpu0.inst 54306348500 # number of overall miss cycles 922system.cpu0.icache.overall_miss_latency::total 54306348500 # number of overall miss cycles 923system.cpu0.icache.ReadReq_accesses::cpu0.inst 463942995 # number of ReadReq accesses(hits+misses) 924system.cpu0.icache.ReadReq_accesses::total 463942995 # number of ReadReq accesses(hits+misses) 925system.cpu0.icache.demand_accesses::cpu0.inst 463942995 # number of demand (read+write) accesses 926system.cpu0.icache.demand_accesses::total 463942995 # number of demand (read+write) accesses 927system.cpu0.icache.overall_accesses::cpu0.inst 463942995 # number of overall (read+write) accesses 928system.cpu0.icache.overall_accesses::total 463942995 # number of overall (read+write) accesses 929system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010691 # miss rate for ReadReq accesses 930system.cpu0.icache.ReadReq_miss_rate::total 0.010691 # miss rate for ReadReq accesses 931system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010691 # miss rate for demand accesses 932system.cpu0.icache.demand_miss_rate::total 0.010691 # miss rate for demand accesses 933system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010691 # miss rate for overall accesses 934system.cpu0.icache.overall_miss_rate::total 0.010691 # miss rate for overall accesses 935system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.701652 # average ReadReq miss latency 936system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.701652 # average ReadReq miss latency 937system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency 938system.cpu0.icache.demand_avg_miss_latency::total 10948.701652 # average overall miss latency 939system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency 940system.cpu0.icache.overall_avg_miss_latency::total 10948.701652 # average overall miss latency | 883system.cpu0.icache.tags.tag_accesses 916349967 # Number of tag accesses 884system.cpu0.icache.tags.data_accesses 916349967 # Number of data accesses 885system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 886system.cpu0.icache.ReadReq_hits::cpu0.inst 450782010 # number of ReadReq hits 887system.cpu0.icache.ReadReq_hits::total 450782010 # number of ReadReq hits 888system.cpu0.icache.demand_hits::cpu0.inst 450782010 # number of demand (read+write) hits 889system.cpu0.icache.demand_hits::total 450782010 # number of demand (read+write) hits 890system.cpu0.icache.overall_hits::cpu0.inst 450782010 # number of overall hits 891system.cpu0.icache.overall_hits::total 450782010 # number of overall hits 892system.cpu0.icache.ReadReq_misses::cpu0.inst 4928649 # number of ReadReq misses 893system.cpu0.icache.ReadReq_misses::total 4928649 # number of ReadReq misses 894system.cpu0.icache.demand_misses::cpu0.inst 4928649 # number of demand (read+write) misses 895system.cpu0.icache.demand_misses::total 4928649 # number of demand (read+write) misses 896system.cpu0.icache.overall_misses::cpu0.inst 4928649 # number of overall misses 897system.cpu0.icache.overall_misses::total 4928649 # number of overall misses 898system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54016215500 # number of ReadReq miss cycles 899system.cpu0.icache.ReadReq_miss_latency::total 54016215500 # number of ReadReq miss cycles 900system.cpu0.icache.demand_miss_latency::cpu0.inst 54016215500 # number of demand (read+write) miss cycles 901system.cpu0.icache.demand_miss_latency::total 54016215500 # number of demand (read+write) miss cycles 902system.cpu0.icache.overall_miss_latency::cpu0.inst 54016215500 # number of overall miss cycles 903system.cpu0.icache.overall_miss_latency::total 54016215500 # number of overall miss cycles 904system.cpu0.icache.ReadReq_accesses::cpu0.inst 455710659 # number of ReadReq accesses(hits+misses) 905system.cpu0.icache.ReadReq_accesses::total 455710659 # number of ReadReq accesses(hits+misses) 906system.cpu0.icache.demand_accesses::cpu0.inst 455710659 # number of demand (read+write) accesses 907system.cpu0.icache.demand_accesses::total 455710659 # number of demand (read+write) accesses 908system.cpu0.icache.overall_accesses::cpu0.inst 455710659 # number of overall (read+write) accesses 909system.cpu0.icache.overall_accesses::total 455710659 # number of overall (read+write) accesses 910system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010815 # miss rate for ReadReq accesses 911system.cpu0.icache.ReadReq_miss_rate::total 0.010815 # miss rate for ReadReq accesses 912system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010815 # miss rate for demand accesses 913system.cpu0.icache.demand_miss_rate::total 0.010815 # miss rate for demand accesses 914system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010815 # miss rate for overall accesses 915system.cpu0.icache.overall_miss_rate::total 0.010815 # miss rate for overall accesses 916system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10959.639345 # average ReadReq miss latency 917system.cpu0.icache.ReadReq_avg_miss_latency::total 10959.639345 # average ReadReq miss latency 918system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency 919system.cpu0.icache.demand_avg_miss_latency::total 10959.639345 # average overall miss latency 920system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency 921system.cpu0.icache.overall_avg_miss_latency::total 10959.639345 # average overall miss latency |
| 941system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 942system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 943system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 944system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 945system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 946system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 922system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 923system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 924system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 925system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 926system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 927system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 947system.cpu0.icache.writebacks::writebacks 4959559 # number of writebacks 948system.cpu0.icache.writebacks::total 4959559 # number of writebacks 949system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4960072 # number of ReadReq MSHR misses 950system.cpu0.icache.ReadReq_mshr_misses::total 4960072 # number of ReadReq MSHR misses 951system.cpu0.icache.demand_mshr_misses::cpu0.inst 4960072 # number of demand (read+write) MSHR misses 952system.cpu0.icache.demand_mshr_misses::total 4960072 # number of demand (read+write) MSHR misses 953system.cpu0.icache.overall_mshr_misses::cpu0.inst 4960072 # number of overall MSHR misses 954system.cpu0.icache.overall_mshr_misses::total 4960072 # number of overall MSHR misses | 928system.cpu0.icache.writebacks::writebacks 4928137 # number of writebacks 929system.cpu0.icache.writebacks::total 4928137 # number of writebacks 930system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4928649 # number of ReadReq MSHR misses 931system.cpu0.icache.ReadReq_mshr_misses::total 4928649 # number of ReadReq MSHR misses 932system.cpu0.icache.demand_mshr_misses::cpu0.inst 4928649 # number of demand (read+write) MSHR misses 933system.cpu0.icache.demand_mshr_misses::total 4928649 # number of demand (read+write) MSHR misses 934system.cpu0.icache.overall_mshr_misses::cpu0.inst 4928649 # number of overall MSHR misses 935system.cpu0.icache.overall_mshr_misses::total 4928649 # number of overall MSHR misses |
| 955system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 956system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 957system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 958system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses | 936system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 937system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 938system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 939system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses |
| 959system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51826313000 # number of ReadReq MSHR miss cycles 960system.cpu0.icache.ReadReq_mshr_miss_latency::total 51826313000 # number of ReadReq MSHR miss cycles 961system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51826313000 # number of demand (read+write) MSHR miss cycles 962system.cpu0.icache.demand_mshr_miss_latency::total 51826313000 # number of demand (read+write) MSHR miss cycles 963system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51826313000 # number of overall MSHR miss cycles 964system.cpu0.icache.overall_mshr_miss_latency::total 51826313000 # number of overall MSHR miss cycles | 940system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51551891000 # number of ReadReq MSHR miss cycles 941system.cpu0.icache.ReadReq_mshr_miss_latency::total 51551891000 # number of ReadReq MSHR miss cycles 942system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51551891000 # number of demand (read+write) MSHR miss cycles 943system.cpu0.icache.demand_mshr_miss_latency::total 51551891000 # number of demand (read+write) MSHR miss cycles 944system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51551891000 # number of overall MSHR miss cycles 945system.cpu0.icache.overall_mshr_miss_latency::total 51551891000 # number of overall MSHR miss cycles |
| 965system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles 966system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles 967system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles 968system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles | 946system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles 947system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles 948system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles 949system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles |
| 969system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for ReadReq accesses 970system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010691 # mshr miss rate for ReadReq accesses 971system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for demand accesses 972system.cpu0.icache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses 973system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for overall accesses 974system.cpu0.icache.overall_mshr_miss_rate::total 0.010691 # mshr miss rate for overall accesses 975system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average ReadReq mshr miss latency 976system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753 # average ReadReq mshr miss latency 977system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency 978system.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency 979system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency 980system.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency | 950system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for ReadReq accesses 951system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010815 # mshr miss rate for ReadReq accesses 952system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for demand accesses 953system.cpu0.icache.demand_mshr_miss_rate::total 0.010815 # mshr miss rate for demand accesses 954system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for overall accesses 955system.cpu0.icache.overall_mshr_miss_rate::total 0.010815 # mshr miss rate for overall accesses 956system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average ReadReq mshr miss latency 957system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10459.639345 # average ReadReq mshr miss latency 958system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency 959system.cpu0.icache.demand_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency 960system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency 961system.cpu0.icache.overall_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency |
| 981system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency 982system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency 983system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency 984system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency | 962system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency 963system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency 964system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency 965system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency |
| 985system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 986system.cpu0.l2cache.prefetcher.num_hwpf_issued 7732053 # number of hwpf issued 987system.cpu0.l2cache.prefetcher.pfIdentified 7732077 # number of prefetch candidates identified 988system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue | 966system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 967system.cpu0.l2cache.prefetcher.num_hwpf_issued 7424522 # number of hwpf issued 968system.cpu0.l2cache.prefetcher.pfIdentified 7424525 # number of prefetch candidates identified 969system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue |
| 989system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 990system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 970system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 971system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 991system.cpu0.l2cache.prefetcher.pfSpanPage 1019171 # number of prefetches not generated due to page crossing 992system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 993system.cpu0.l2cache.tags.replacements 2286879 # number of replacements 994system.cpu0.l2cache.tags.tagsinuse 15893.622807 # Cycle average of tags in use 995system.cpu0.l2cache.tags.total_refs 9162734 # Total number of references to valid blocks. 996system.cpu0.l2cache.tags.sampled_refs 2302009 # Sample count of references to valid blocks. 997system.cpu0.l2cache.tags.avg_refs 3.980321 # Average number of references to valid blocks. 998system.cpu0.l2cache.tags.warmup_cycle 5406430500 # Cycle when the warmup percentage was hit. 999system.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064 # Average occupied blocks per requestor 1000system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 29.949034 # Average occupied blocks per requestor 1001system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 16.856945 # Average occupied blocks per requestor 1002system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 242.920764 # Average occupied blocks per requestor 1003system.cpu0.l2cache.tags.occ_percent::writebacks 0.952386 # Average percentage of cache occupancy 1004system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001828 # Average percentage of cache occupancy 1005system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001029 # Average percentage of cache occupancy 1006system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014827 # Average percentage of cache occupancy 1007system.cpu0.l2cache.tags.occ_percent::total 0.970070 # Average percentage of cache occupancy 1008system.cpu0.l2cache.tags.occ_task_id_blocks::1022 306 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14757 # Occupied blocks per task id 1011system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id 1012system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 139 # Occupied blocks per task id 1013system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 67 # Occupied blocks per task id 1014system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1015system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 1016system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id 1017system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1018system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 1019system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 1020system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4608 # Occupied blocks per task id 1021system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8403 # Occupied blocks per task id 1022system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1616 # Occupied blocks per task id 1023system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018677 # Percentage of cache occupancy per task id 1024system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id 1025system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900696 # Percentage of cache occupancy per task id 1026system.cpu0.l2cache.tags.tag_accesses 368793343 # Number of tag accesses 1027system.cpu0.l2cache.tags.data_accesses 368793343 # Number of data accesses 1028system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1029system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 252482 # number of ReadReq hits 1030system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 146217 # number of ReadReq hits 1031system.cpu0.l2cache.ReadReq_hits::total 398699 # number of ReadReq hits 1032system.cpu0.l2cache.WritebackDirty_hits::writebacks 3794669 # number of WritebackDirty hits 1033system.cpu0.l2cache.WritebackDirty_hits::total 3794669 # number of WritebackDirty hits 1034system.cpu0.l2cache.WritebackClean_hits::writebacks 6895627 # number of WritebackClean hits 1035system.cpu0.l2cache.WritebackClean_hits::total 6895627 # number of WritebackClean hits 1036system.cpu0.l2cache.ReadExReq_hits::cpu0.data 932984 # number of ReadExReq hits 1037system.cpu0.l2cache.ReadExReq_hits::total 932984 # number of ReadExReq hits 1038system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4503327 # number of ReadCleanReq hits 1039system.cpu0.l2cache.ReadCleanReq_hits::total 4503327 # number of ReadCleanReq hits 1040system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2919116 # number of ReadSharedReq hits 1041system.cpu0.l2cache.ReadSharedReq_hits::total 2919116 # number of ReadSharedReq hits 1042system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 217183 # number of InvalidateReq hits 1043system.cpu0.l2cache.InvalidateReq_hits::total 217183 # number of InvalidateReq hits 1044system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 252482 # number of demand (read+write) hits 1045system.cpu0.l2cache.demand_hits::cpu0.itb.walker 146217 # number of demand (read+write) hits 1046system.cpu0.l2cache.demand_hits::cpu0.inst 4503327 # number of demand (read+write) hits 1047system.cpu0.l2cache.demand_hits::cpu0.data 3852100 # number of demand (read+write) hits 1048system.cpu0.l2cache.demand_hits::total 8754126 # number of demand (read+write) hits 1049system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 252482 # number of overall hits 1050system.cpu0.l2cache.overall_hits::cpu0.itb.walker 146217 # number of overall hits 1051system.cpu0.l2cache.overall_hits::cpu0.inst 4503327 # number of overall hits 1052system.cpu0.l2cache.overall_hits::cpu0.data 3852100 # number of overall hits 1053system.cpu0.l2cache.overall_hits::total 8754126 # number of overall hits 1054system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 17757 # number of ReadReq misses 1055system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8990 # number of ReadReq misses 1056system.cpu0.l2cache.ReadReq_misses::total 26747 # number of ReadReq misses 1057system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 236502 # number of UpgradeReq misses 1058system.cpu0.l2cache.UpgradeReq_misses::total 236502 # number of UpgradeReq misses 1059system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200518 # number of SCUpgradeReq misses 1060system.cpu0.l2cache.SCUpgradeReq_misses::total 200518 # number of SCUpgradeReq misses 1061system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses 1062system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 1063system.cpu0.l2cache.ReadExReq_misses::cpu0.data 248602 # number of ReadExReq misses 1064system.cpu0.l2cache.ReadExReq_misses::total 248602 # number of ReadExReq misses 1065system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 456745 # number of ReadCleanReq misses 1066system.cpu0.l2cache.ReadCleanReq_misses::total 456745 # number of ReadCleanReq misses 1067system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 935783 # number of ReadSharedReq misses 1068system.cpu0.l2cache.ReadSharedReq_misses::total 935783 # number of ReadSharedReq misses 1069system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 577322 # number of InvalidateReq misses 1070system.cpu0.l2cache.InvalidateReq_misses::total 577322 # number of InvalidateReq misses 1071system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 17757 # number of demand (read+write) misses 1072system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8990 # number of demand (read+write) misses 1073system.cpu0.l2cache.demand_misses::cpu0.inst 456745 # number of demand (read+write) misses 1074system.cpu0.l2cache.demand_misses::cpu0.data 1184385 # number of demand (read+write) misses 1075system.cpu0.l2cache.demand_misses::total 1667877 # number of demand (read+write) misses 1076system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 17757 # number of overall misses 1077system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8990 # number of overall misses 1078system.cpu0.l2cache.overall_misses::cpu0.inst 456745 # number of overall misses 1079system.cpu0.l2cache.overall_misses::cpu0.data 1184385 # number of overall misses 1080system.cpu0.l2cache.overall_misses::total 1667877 # number of overall misses 1081system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 557104000 # number of ReadReq miss cycles 1082system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 362043000 # number of ReadReq miss cycles 1083system.cpu0.l2cache.ReadReq_miss_latency::total 919147000 # number of ReadReq miss cycles 1084system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 930109500 # number of UpgradeReq miss cycles 1085system.cpu0.l2cache.UpgradeReq_miss_latency::total 930109500 # number of UpgradeReq miss cycles 1086system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 320714500 # number of SCUpgradeReq miss cycles 1087system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 320714500 # number of SCUpgradeReq miss cycles 1088system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2109497 # number of SCUpgradeFailReq miss cycles 1089system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2109497 # number of SCUpgradeFailReq miss cycles 1090system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13818048499 # number of ReadExReq miss cycles 1091system.cpu0.l2cache.ReadExReq_miss_latency::total 13818048499 # number of ReadExReq miss cycles 1092system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17338170000 # number of ReadCleanReq miss cycles 1093system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17338170000 # number of ReadCleanReq miss cycles 1094system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 36151090000 # number of ReadSharedReq miss cycles 1095system.cpu0.l2cache.ReadSharedReq_miss_latency::total 36151090000 # number of ReadSharedReq miss cycles 1096system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 305279500 # number of InvalidateReq miss cycles 1097system.cpu0.l2cache.InvalidateReq_miss_latency::total 305279500 # number of InvalidateReq miss cycles 1098system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 557104000 # number of demand (read+write) miss cycles 1099system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 362043000 # number of demand (read+write) miss cycles 1100system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17338170000 # number of demand (read+write) miss cycles 1101system.cpu0.l2cache.demand_miss_latency::cpu0.data 49969138499 # number of demand (read+write) miss cycles 1102system.cpu0.l2cache.demand_miss_latency::total 68226455499 # number of demand (read+write) miss cycles 1103system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 557104000 # number of overall miss cycles 1104system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 362043000 # number of overall miss cycles 1105system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17338170000 # number of overall miss cycles 1106system.cpu0.l2cache.overall_miss_latency::cpu0.data 49969138499 # number of overall miss cycles 1107system.cpu0.l2cache.overall_miss_latency::total 68226455499 # number of overall miss cycles 1108system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 270239 # number of ReadReq accesses(hits+misses) 1109system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155207 # number of ReadReq accesses(hits+misses) 1110system.cpu0.l2cache.ReadReq_accesses::total 425446 # number of ReadReq accesses(hits+misses) 1111system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3794669 # number of WritebackDirty accesses(hits+misses) 1112system.cpu0.l2cache.WritebackDirty_accesses::total 3794669 # number of WritebackDirty accesses(hits+misses) 1113system.cpu0.l2cache.WritebackClean_accesses::writebacks 6895627 # number of WritebackClean accesses(hits+misses) 1114system.cpu0.l2cache.WritebackClean_accesses::total 6895627 # number of WritebackClean accesses(hits+misses) 1115system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 236502 # number of UpgradeReq accesses(hits+misses) 1116system.cpu0.l2cache.UpgradeReq_accesses::total 236502 # number of UpgradeReq accesses(hits+misses) 1117system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200518 # number of SCUpgradeReq accesses(hits+misses) 1118system.cpu0.l2cache.SCUpgradeReq_accesses::total 200518 # number of SCUpgradeReq accesses(hits+misses) 1119system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) 1120system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 1121system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1181586 # number of ReadExReq accesses(hits+misses) 1122system.cpu0.l2cache.ReadExReq_accesses::total 1181586 # number of ReadExReq accesses(hits+misses) 1123system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4960072 # number of ReadCleanReq accesses(hits+misses) 1124system.cpu0.l2cache.ReadCleanReq_accesses::total 4960072 # number of ReadCleanReq accesses(hits+misses) 1125system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3854899 # number of ReadSharedReq accesses(hits+misses) 1126system.cpu0.l2cache.ReadSharedReq_accesses::total 3854899 # number of ReadSharedReq accesses(hits+misses) 1127system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794505 # number of InvalidateReq accesses(hits+misses) 1128system.cpu0.l2cache.InvalidateReq_accesses::total 794505 # number of InvalidateReq accesses(hits+misses) 1129system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 270239 # number of demand (read+write) accesses 1130system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155207 # number of demand (read+write) accesses 1131system.cpu0.l2cache.demand_accesses::cpu0.inst 4960072 # number of demand (read+write) accesses 1132system.cpu0.l2cache.demand_accesses::cpu0.data 5036485 # number of demand (read+write) accesses 1133system.cpu0.l2cache.demand_accesses::total 10422003 # number of demand (read+write) accesses 1134system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 270239 # number of overall (read+write) accesses 1135system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155207 # number of overall (read+write) accesses 1136system.cpu0.l2cache.overall_accesses::cpu0.inst 4960072 # number of overall (read+write) accesses 1137system.cpu0.l2cache.overall_accesses::cpu0.data 5036485 # number of overall (read+write) accesses 1138system.cpu0.l2cache.overall_accesses::total 10422003 # number of overall (read+write) accesses 1139system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for ReadReq accesses 1140system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057923 # miss rate for ReadReq accesses 1141system.cpu0.l2cache.ReadReq_miss_rate::total 0.062868 # miss rate for ReadReq accesses | 972system.cpu0.l2cache.prefetcher.pfSpanPage 998915 # number of prefetches not generated due to page crossing 973system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 974system.cpu0.l2cache.tags.replacements 2238289 # number of replacements 975system.cpu0.l2cache.tags.tagsinuse 15477.322343 # Cycle average of tags in use 976system.cpu0.l2cache.tags.total_refs 8961437 # Total number of references to valid blocks. 977system.cpu0.l2cache.tags.sampled_refs 2253120 # Sample count of references to valid blocks. 978system.cpu0.l2cache.tags.avg_refs 3.977346 # Average number of references to valid blocks. 979system.cpu0.l2cache.tags.warmup_cycle 5406108500 # Cycle when the warmup percentage was hit. 980system.cpu0.l2cache.tags.occ_blocks::writebacks 15186.002225 # Average occupied blocks per requestor 981system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.160912 # Average occupied blocks per requestor 982system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.574333 # Average occupied blocks per requestor 983system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.584873 # Average occupied blocks per requestor 984system.cpu0.l2cache.tags.occ_percent::writebacks 0.926880 # Average percentage of cache occupancy 985system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001963 # Average percentage of cache occupancy 986system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001622 # Average percentage of cache occupancy 987system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014196 # Average percentage of cache occupancy 988system.cpu0.l2cache.tags.occ_percent::total 0.944661 # Average percentage of cache occupancy 989system.cpu0.l2cache.tags.occ_task_id_blocks::1022 343 # Occupied blocks per task id 990system.cpu0.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id 991system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14429 # Occupied blocks per task id 992system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id 993system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id 994system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id 995system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 996system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id 997system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id 998system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id 999system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8440 # Occupied blocks per task id 1000system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4747 # Occupied blocks per task id 1001system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020935 # Percentage of cache occupancy per task id 1002system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id 1003system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880676 # Percentage of cache occupancy per task id 1004system.cpu0.l2cache.tags.tag_accesses 361005368 # Number of tag accesses 1005system.cpu0.l2cache.tags.data_accesses 361005368 # Number of data accesses 1006system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1007system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 239188 # number of ReadReq hits 1008system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140105 # number of ReadReq hits 1009system.cpu0.l2cache.ReadReq_hits::total 379293 # number of ReadReq hits 1010system.cpu0.l2cache.WritebackDirty_hits::writebacks 3693855 # number of WritebackDirty hits 1011system.cpu0.l2cache.WritebackDirty_hits::total 3693855 # number of WritebackDirty hits 1012system.cpu0.l2cache.WritebackClean_hits::writebacks 6781361 # number of WritebackClean hits 1013system.cpu0.l2cache.WritebackClean_hits::total 6781361 # number of WritebackClean hits 1014system.cpu0.l2cache.ReadExReq_hits::cpu0.data 879738 # number of ReadExReq hits 1015system.cpu0.l2cache.ReadExReq_hits::total 879738 # number of ReadExReq hits 1016system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4485760 # number of ReadCleanReq hits 1017system.cpu0.l2cache.ReadCleanReq_hits::total 4485760 # number of ReadCleanReq hits 1018system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2821736 # number of ReadSharedReq hits 1019system.cpu0.l2cache.ReadSharedReq_hits::total 2821736 # number of ReadSharedReq hits 1020system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211609 # number of InvalidateReq hits 1021system.cpu0.l2cache.InvalidateReq_hits::total 211609 # number of InvalidateReq hits 1022system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 239188 # number of demand (read+write) hits 1023system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140105 # number of demand (read+write) hits 1024system.cpu0.l2cache.demand_hits::cpu0.inst 4485760 # number of demand (read+write) hits 1025system.cpu0.l2cache.demand_hits::cpu0.data 3701474 # number of demand (read+write) hits 1026system.cpu0.l2cache.demand_hits::total 8566527 # number of demand (read+write) hits 1027system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 239188 # number of overall hits 1028system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140105 # number of overall hits 1029system.cpu0.l2cache.overall_hits::cpu0.inst 4485760 # number of overall hits 1030system.cpu0.l2cache.overall_hits::cpu0.data 3701474 # number of overall hits 1031system.cpu0.l2cache.overall_hits::total 8566527 # number of overall hits 1032system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16649 # number of ReadReq misses 1033system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8661 # number of ReadReq misses 1034system.cpu0.l2cache.ReadReq_misses::total 25310 # number of ReadReq misses 1035system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 231687 # number of UpgradeReq misses 1036system.cpu0.l2cache.UpgradeReq_misses::total 231687 # number of UpgradeReq misses 1037system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 188526 # number of SCUpgradeReq misses 1038system.cpu0.l2cache.SCUpgradeReq_misses::total 188526 # number of SCUpgradeReq misses 1039system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 1040system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1041system.cpu0.l2cache.ReadExReq_misses::cpu0.data 243594 # number of ReadExReq misses 1042system.cpu0.l2cache.ReadExReq_misses::total 243594 # number of ReadExReq misses 1043system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 442889 # number of ReadCleanReq misses 1044system.cpu0.l2cache.ReadCleanReq_misses::total 442889 # number of ReadCleanReq misses 1045system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 903613 # number of ReadSharedReq misses 1046system.cpu0.l2cache.ReadSharedReq_misses::total 903613 # number of ReadSharedReq misses 1047system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582678 # number of InvalidateReq misses 1048system.cpu0.l2cache.InvalidateReq_misses::total 582678 # number of InvalidateReq misses 1049system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 16649 # number of demand (read+write) misses 1050system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8661 # number of demand (read+write) misses 1051system.cpu0.l2cache.demand_misses::cpu0.inst 442889 # number of demand (read+write) misses 1052system.cpu0.l2cache.demand_misses::cpu0.data 1147207 # number of demand (read+write) misses 1053system.cpu0.l2cache.demand_misses::total 1615406 # number of demand (read+write) misses 1054system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 16649 # number of overall misses 1055system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8661 # number of overall misses 1056system.cpu0.l2cache.overall_misses::cpu0.inst 442889 # number of overall misses 1057system.cpu0.l2cache.overall_misses::cpu0.data 1147207 # number of overall misses 1058system.cpu0.l2cache.overall_misses::total 1615406 # number of overall misses 1059system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 524453500 # number of ReadReq miss cycles 1060system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 332493500 # number of ReadReq miss cycles 1061system.cpu0.l2cache.ReadReq_miss_latency::total 856947000 # number of ReadReq miss cycles 1062system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 896560000 # number of UpgradeReq miss cycles 1063system.cpu0.l2cache.UpgradeReq_miss_latency::total 896560000 # number of UpgradeReq miss cycles 1064system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 330254000 # number of SCUpgradeReq miss cycles 1065system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 330254000 # number of SCUpgradeReq miss cycles 1066system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1931999 # number of SCUpgradeFailReq miss cycles 1067system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1931999 # number of SCUpgradeFailReq miss cycles 1068system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13649420499 # number of ReadExReq miss cycles 1069system.cpu0.l2cache.ReadExReq_miss_latency::total 13649420499 # number of ReadExReq miss cycles 1070system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17214501500 # number of ReadCleanReq miss cycles 1071system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17214501500 # number of ReadCleanReq miss cycles 1072system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35658673000 # number of ReadSharedReq miss cycles 1073system.cpu0.l2cache.ReadSharedReq_miss_latency::total 35658673000 # number of ReadSharedReq miss cycles 1074system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 429500 # number of InvalidateReq miss cycles 1075system.cpu0.l2cache.InvalidateReq_miss_latency::total 429500 # number of InvalidateReq miss cycles 1076system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 524453500 # number of demand (read+write) miss cycles 1077system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 332493500 # number of demand (read+write) miss cycles 1078system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17214501500 # number of demand (read+write) miss cycles 1079system.cpu0.l2cache.demand_miss_latency::cpu0.data 49308093499 # number of demand (read+write) miss cycles 1080system.cpu0.l2cache.demand_miss_latency::total 67379541999 # number of demand (read+write) miss cycles 1081system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 524453500 # number of overall miss cycles 1082system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 332493500 # number of overall miss cycles 1083system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17214501500 # number of overall miss cycles 1084system.cpu0.l2cache.overall_miss_latency::cpu0.data 49308093499 # number of overall miss cycles 1085system.cpu0.l2cache.overall_miss_latency::total 67379541999 # number of overall miss cycles 1086system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 255837 # number of ReadReq accesses(hits+misses) 1087system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148766 # number of ReadReq accesses(hits+misses) 1088system.cpu0.l2cache.ReadReq_accesses::total 404603 # number of ReadReq accesses(hits+misses) 1089system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3693855 # number of WritebackDirty accesses(hits+misses) 1090system.cpu0.l2cache.WritebackDirty_accesses::total 3693855 # number of WritebackDirty accesses(hits+misses) 1091system.cpu0.l2cache.WritebackClean_accesses::writebacks 6781361 # number of WritebackClean accesses(hits+misses) 1092system.cpu0.l2cache.WritebackClean_accesses::total 6781361 # number of WritebackClean accesses(hits+misses) 1093system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231687 # number of UpgradeReq accesses(hits+misses) 1094system.cpu0.l2cache.UpgradeReq_accesses::total 231687 # number of UpgradeReq accesses(hits+misses) 1095system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188526 # number of SCUpgradeReq accesses(hits+misses) 1096system.cpu0.l2cache.SCUpgradeReq_accesses::total 188526 # number of SCUpgradeReq accesses(hits+misses) 1097system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1098system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1099system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1123332 # number of ReadExReq accesses(hits+misses) 1100system.cpu0.l2cache.ReadExReq_accesses::total 1123332 # number of ReadExReq accesses(hits+misses) 1101system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4928649 # number of ReadCleanReq accesses(hits+misses) 1102system.cpu0.l2cache.ReadCleanReq_accesses::total 4928649 # number of ReadCleanReq accesses(hits+misses) 1103system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3725349 # number of ReadSharedReq accesses(hits+misses) 1104system.cpu0.l2cache.ReadSharedReq_accesses::total 3725349 # number of ReadSharedReq accesses(hits+misses) 1105system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794287 # number of InvalidateReq accesses(hits+misses) 1106system.cpu0.l2cache.InvalidateReq_accesses::total 794287 # number of InvalidateReq accesses(hits+misses) 1107system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 255837 # number of demand (read+write) accesses 1108system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148766 # number of demand (read+write) accesses 1109system.cpu0.l2cache.demand_accesses::cpu0.inst 4928649 # number of demand (read+write) accesses 1110system.cpu0.l2cache.demand_accesses::cpu0.data 4848681 # number of demand (read+write) accesses 1111system.cpu0.l2cache.demand_accesses::total 10181933 # number of demand (read+write) accesses 1112system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 255837 # number of overall (read+write) accesses 1113system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148766 # number of overall (read+write) accesses 1114system.cpu0.l2cache.overall_accesses::cpu0.inst 4928649 # number of overall (read+write) accesses 1115system.cpu0.l2cache.overall_accesses::cpu0.data 4848681 # number of overall (read+write) accesses 1116system.cpu0.l2cache.overall_accesses::total 10181933 # number of overall (read+write) accesses 1117system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for ReadReq accesses 1118system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058219 # miss rate for ReadReq accesses 1119system.cpu0.l2cache.ReadReq_miss_rate::total 0.062555 # miss rate for ReadReq accesses |
| 1142system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1143system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1144system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1145system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1146system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1147system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1120system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1121system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1122system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1123system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1124system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1125system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1148system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.210397 # miss rate for ReadExReq accesses 1149system.cpu0.l2cache.ReadExReq_miss_rate::total 0.210397 # miss rate for ReadExReq accesses 1150system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092084 # miss rate for ReadCleanReq accesses 1151system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092084 # miss rate for ReadCleanReq accesses 1152system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242752 # miss rate for ReadSharedReq accesses 1153system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242752 # miss rate for ReadSharedReq accesses 1154system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.726644 # miss rate for InvalidateReq accesses 1155system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.726644 # miss rate for InvalidateReq accesses 1156system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for demand accesses 1157system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057923 # miss rate for demand accesses 1158system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092084 # miss rate for demand accesses 1159system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.235161 # miss rate for demand accesses 1160system.cpu0.l2cache.demand_miss_rate::total 0.160034 # miss rate for demand accesses 1161system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for overall accesses 1162system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057923 # miss rate for overall accesses 1163system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092084 # miss rate for overall accesses 1164system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.235161 # miss rate for overall accesses 1165system.cpu0.l2cache.overall_miss_rate::total 0.160034 # miss rate for overall accesses 1166system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average ReadReq miss latency 1167system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40271.746385 # average ReadReq miss latency 1168system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34364.489475 # average ReadReq miss latency 1169system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3932.776467 # average UpgradeReq miss latency 1170system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3932.776467 # average UpgradeReq miss latency 1171system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1599.429976 # average SCUpgradeReq miss latency 1172system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1599.429976 # average SCUpgradeReq miss latency 1173system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 210949.700000 # average SCUpgradeFailReq miss latency 1174system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 210949.700000 # average SCUpgradeFailReq miss latency 1175system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55583.014211 # average ReadExReq miss latency 1176system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55583.014211 # average ReadExReq miss latency 1177system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37960.284185 # average ReadCleanReq miss latency 1178system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37960.284185 # average ReadCleanReq miss latency 1179system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38631.915733 # average ReadSharedReq miss latency 1180system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38631.915733 # average ReadSharedReq miss latency 1181system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 528.785496 # average InvalidateReq miss latency 1182system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 528.785496 # average InvalidateReq miss latency 1183system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average overall miss latency 1184system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40271.746385 # average overall miss latency 1185system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37960.284185 # average overall miss latency 1186system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42189.945414 # average overall miss latency 1187system.cpu0.l2cache.demand_avg_miss_latency::total 40906.167241 # average overall miss latency 1188system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average overall miss latency 1189system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40271.746385 # average overall miss latency 1190system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37960.284185 # average overall miss latency 1191system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42189.945414 # average overall miss latency 1192system.cpu0.l2cache.overall_avg_miss_latency::total 40906.167241 # average overall miss latency | 1126system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.216850 # miss rate for ReadExReq accesses 1127system.cpu0.l2cache.ReadExReq_miss_rate::total 0.216850 # miss rate for ReadExReq accesses 1128system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089860 # miss rate for ReadCleanReq accesses 1129system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089860 # miss rate for ReadCleanReq accesses 1130system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242558 # miss rate for ReadSharedReq accesses 1131system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242558 # miss rate for ReadSharedReq accesses 1132system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733586 # miss rate for InvalidateReq accesses 1133system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733586 # miss rate for InvalidateReq accesses 1134system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for demand accesses 1135system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058219 # miss rate for demand accesses 1136system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089860 # miss rate for demand accesses 1137system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.236602 # miss rate for demand accesses 1138system.cpu0.l2cache.demand_miss_rate::total 0.158654 # miss rate for demand accesses 1139system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for overall accesses 1140system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058219 # miss rate for overall accesses 1141system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089860 # miss rate for overall accesses 1142system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.236602 # miss rate for overall accesses 1143system.cpu0.l2cache.overall_miss_rate::total 0.158654 # miss rate for overall accesses 1144system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average ReadReq miss latency 1145system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38389.735596 # average ReadReq miss latency 1146system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33858.040300 # average ReadReq miss latency 1147system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3869.703522 # average UpgradeReq miss latency 1148system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3869.703522 # average UpgradeReq miss latency 1149system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1751.768987 # average SCUpgradeReq miss latency 1150system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1751.768987 # average SCUpgradeReq miss latency 1151system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 482999.750000 # average SCUpgradeFailReq miss latency 1152system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 482999.750000 # average SCUpgradeFailReq miss latency 1153system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56033.483990 # average ReadExReq miss latency 1154system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56033.483990 # average ReadExReq miss latency 1155system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38868.658964 # average ReadCleanReq miss latency 1156system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38868.658964 # average ReadCleanReq miss latency 1157system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39462.328453 # average ReadSharedReq miss latency 1158system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39462.328453 # average ReadSharedReq miss latency 1159system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.737114 # average InvalidateReq miss latency 1160system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.737114 # average InvalidateReq miss latency 1161system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency 1162system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency 1163system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency 1164system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency 1165system.cpu0.l2cache.demand_avg_miss_latency::total 41710.592878 # average overall miss latency 1166system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency 1167system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency 1168system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency 1169system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency 1170system.cpu0.l2cache.overall_avg_miss_latency::total 41710.592878 # average overall miss latency |
| 1193system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1194system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1195system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1196system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1197system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1198system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1171system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1172system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1173system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1174system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1175system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1176system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1199system.cpu0.l2cache.unused_prefetches 38115 # number of HardPF blocks evicted w/o reference 1200system.cpu0.l2cache.writebacks::writebacks 1518116 # number of writebacks 1201system.cpu0.l2cache.writebacks::total 1518116 # number of writebacks 1202system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6419 # number of ReadExReq MSHR hits 1203system.cpu0.l2cache.ReadExReq_mshr_hits::total 6419 # number of ReadExReq MSHR hits 1204system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 459 # number of ReadSharedReq MSHR hits 1205system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 459 # number of ReadSharedReq MSHR hits 1206system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6878 # number of demand (read+write) MSHR hits 1207system.cpu0.l2cache.demand_mshr_hits::total 6878 # number of demand (read+write) MSHR hits 1208system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6878 # number of overall MSHR hits 1209system.cpu0.l2cache.overall_mshr_hits::total 6878 # number of overall MSHR hits 1210system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 17757 # number of ReadReq MSHR misses 1211system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8990 # number of ReadReq MSHR misses 1212system.cpu0.l2cache.ReadReq_mshr_misses::total 26747 # number of ReadReq MSHR misses 1213system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 749864 # number of HardPFReq MSHR misses 1214system.cpu0.l2cache.HardPFReq_mshr_misses::total 749864 # number of HardPFReq MSHR misses 1215system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 236502 # number of UpgradeReq MSHR misses 1216system.cpu0.l2cache.UpgradeReq_mshr_misses::total 236502 # number of UpgradeReq MSHR misses 1217system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200518 # number of SCUpgradeReq MSHR misses 1218system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200518 # number of SCUpgradeReq MSHR misses 1219system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses 1220system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 1221system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 242183 # number of ReadExReq MSHR misses 1222system.cpu0.l2cache.ReadExReq_mshr_misses::total 242183 # number of ReadExReq MSHR misses 1223system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 456745 # number of ReadCleanReq MSHR misses 1224system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 456745 # number of ReadCleanReq MSHR misses 1225system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 935324 # number of ReadSharedReq MSHR misses 1226system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 935324 # number of ReadSharedReq MSHR misses 1227system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 577322 # number of InvalidateReq MSHR misses 1228system.cpu0.l2cache.InvalidateReq_mshr_misses::total 577322 # number of InvalidateReq MSHR misses 1229system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 17757 # number of demand (read+write) MSHR misses 1230system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8990 # number of demand (read+write) MSHR misses 1231system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 456745 # number of demand (read+write) MSHR misses 1232system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1177507 # number of demand (read+write) MSHR misses 1233system.cpu0.l2cache.demand_mshr_misses::total 1660999 # number of demand (read+write) MSHR misses 1234system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 17757 # number of overall MSHR misses 1235system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8990 # number of overall MSHR misses 1236system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 456745 # number of overall MSHR misses 1237system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1177507 # number of overall MSHR misses 1238system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 749864 # number of overall MSHR misses 1239system.cpu0.l2cache.overall_mshr_misses::total 2410863 # number of overall MSHR misses | 1177system.cpu0.l2cache.unused_prefetches 36707 # number of HardPF blocks evicted w/o reference 1178system.cpu0.l2cache.writebacks::writebacks 1501692 # number of writebacks 1179system.cpu0.l2cache.writebacks::total 1501692 # number of writebacks 1180system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6241 # number of ReadExReq MSHR hits 1181system.cpu0.l2cache.ReadExReq_mshr_hits::total 6241 # number of ReadExReq MSHR hits 1182system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 600 # number of ReadSharedReq MSHR hits 1183system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 600 # number of ReadSharedReq MSHR hits 1184system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 1 # number of InvalidateReq MSHR hits 1185system.cpu0.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 1186system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6841 # number of demand (read+write) MSHR hits 1187system.cpu0.l2cache.demand_mshr_hits::total 6841 # number of demand (read+write) MSHR hits 1188system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6841 # number of overall MSHR hits 1189system.cpu0.l2cache.overall_mshr_hits::total 6841 # number of overall MSHR hits 1190system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 16649 # number of ReadReq MSHR misses 1191system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8661 # number of ReadReq MSHR misses 1192system.cpu0.l2cache.ReadReq_mshr_misses::total 25310 # number of ReadReq MSHR misses 1193system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of HardPFReq MSHR misses 1194system.cpu0.l2cache.HardPFReq_mshr_misses::total 726594 # number of HardPFReq MSHR misses 1195system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 231687 # number of UpgradeReq MSHR misses 1196system.cpu0.l2cache.UpgradeReq_mshr_misses::total 231687 # number of UpgradeReq MSHR misses 1197system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 188526 # number of SCUpgradeReq MSHR misses 1198system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 188526 # number of SCUpgradeReq MSHR misses 1199system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 1200system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1201system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 237353 # number of ReadExReq MSHR misses 1202system.cpu0.l2cache.ReadExReq_mshr_misses::total 237353 # number of ReadExReq MSHR misses 1203system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 442889 # number of ReadCleanReq MSHR misses 1204system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 442889 # number of ReadCleanReq MSHR misses 1205system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 903013 # number of ReadSharedReq MSHR misses 1206system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 903013 # number of ReadSharedReq MSHR misses 1207system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 582677 # number of InvalidateReq MSHR misses 1208system.cpu0.l2cache.InvalidateReq_mshr_misses::total 582677 # number of InvalidateReq MSHR misses 1209system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 16649 # number of demand (read+write) MSHR misses 1210system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8661 # number of demand (read+write) MSHR misses 1211system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 442889 # number of demand (read+write) MSHR misses 1212system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1140366 # number of demand (read+write) MSHR misses 1213system.cpu0.l2cache.demand_mshr_misses::total 1608565 # number of demand (read+write) MSHR misses 1214system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 16649 # number of overall MSHR misses 1215system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8661 # number of overall MSHR misses 1216system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 442889 # number of overall MSHR misses 1217system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1140366 # number of overall MSHR misses 1218system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of overall MSHR misses 1219system.cpu0.l2cache.overall_mshr_misses::total 2335159 # number of overall MSHR misses |
| 1240system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable | 1220system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable |
| 1241system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable 1242system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59506 # number of ReadReq MSHR uncacheable 1243system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 1244system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable | 1221system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable 1222system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72953 # number of ReadReq MSHR uncacheable 1223system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable 1224system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable |
| 1245system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses | 1225system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses |
| 1246system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses 1247system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77200 # number of overall MSHR uncacheable misses 1248system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of ReadReq MSHR miss cycles 1249system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 308103000 # number of ReadReq MSHR miss cycles 1250system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 758665000 # number of ReadReq MSHR miss cycles 1251system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37032584946 # number of HardPFReq MSHR miss cycles 1252system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37032584946 # number of HardPFReq MSHR miss cycles 1253system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4392780000 # number of UpgradeReq MSHR miss cycles 1254system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4392780000 # number of UpgradeReq MSHR miss cycles 1255system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3053423000 # number of SCUpgradeReq MSHR miss cycles 1256system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3053423000 # number of SCUpgradeReq MSHR miss cycles 1257system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1785497 # number of SCUpgradeFailReq MSHR miss cycles 1258system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1785497 # number of SCUpgradeFailReq MSHR miss cycles 1259system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11646133999 # number of ReadExReq MSHR miss cycles 1260system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11646133999 # number of ReadExReq MSHR miss cycles 1261system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14597700000 # number of ReadCleanReq MSHR miss cycles 1262system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14597700000 # number of ReadCleanReq MSHR miss cycles 1263system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30480683500 # number of ReadSharedReq MSHR miss cycles 1264system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30480683500 # number of ReadSharedReq MSHR miss cycles 1265system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18786696000 # number of InvalidateReq MSHR miss cycles 1266system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18786696000 # number of InvalidateReq MSHR miss cycles 1267system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of demand (read+write) MSHR miss cycles 1268system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 308103000 # number of demand (read+write) MSHR miss cycles 1269system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14597700000 # number of demand (read+write) MSHR miss cycles 1270system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 42126817499 # number of demand (read+write) MSHR miss cycles 1271system.cpu0.l2cache.demand_mshr_miss_latency::total 57483182499 # number of demand (read+write) MSHR miss cycles 1272system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of overall MSHR miss cycles 1273system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 308103000 # number of overall MSHR miss cycles 1274system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14597700000 # number of overall MSHR miss cycles 1275system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42126817499 # number of overall MSHR miss cycles 1276system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37032584946 # number of overall MSHR miss cycles 1277system.cpu0.l2cache.overall_mshr_miss_latency::total 94515767445 # number of overall MSHR miss cycles | 1226system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses 1227system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 102312 # number of overall MSHR uncacheable misses 1228system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of ReadReq MSHR miss cycles 1229system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 280527500 # number of ReadReq MSHR miss cycles 1230system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 705087000 # number of ReadReq MSHR miss cycles 1231system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of HardPFReq MSHR miss cycles 1232system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37258472903 # number of HardPFReq MSHR miss cycles 1233system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4314197500 # number of UpgradeReq MSHR miss cycles 1234system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4314197500 # number of UpgradeReq MSHR miss cycles 1235system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2894861999 # number of SCUpgradeReq MSHR miss cycles 1236system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2894861999 # number of SCUpgradeReq MSHR miss cycles 1237system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1631999 # number of SCUpgradeFailReq MSHR miss cycles 1238system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1631999 # number of SCUpgradeFailReq MSHR miss cycles 1239system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11516279999 # number of ReadExReq MSHR miss cycles 1240system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11516279999 # number of ReadExReq MSHR miss cycles 1241system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14557167500 # number of ReadCleanReq MSHR miss cycles 1242system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14557167500 # number of ReadCleanReq MSHR miss cycles 1243system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30162372000 # number of ReadSharedReq MSHR miss cycles 1244system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30162372000 # number of ReadSharedReq MSHR miss cycles 1245system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18401745500 # number of InvalidateReq MSHR miss cycles 1246system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18401745500 # number of InvalidateReq MSHR miss cycles 1247system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of demand (read+write) MSHR miss cycles 1248system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 280527500 # number of demand (read+write) MSHR miss cycles 1249system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14557167500 # number of demand (read+write) MSHR miss cycles 1250system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 41678651999 # number of demand (read+write) MSHR miss cycles 1251system.cpu0.l2cache.demand_mshr_miss_latency::total 56940906499 # number of demand (read+write) MSHR miss cycles 1252system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of overall MSHR miss cycles 1253system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 280527500 # number of overall MSHR miss cycles 1254system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14557167500 # number of overall MSHR miss cycles 1255system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 41678651999 # number of overall MSHR miss cycles 1256system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of overall MSHR miss cycles 1257system.cpu0.l2cache.overall_mshr_miss_latency::total 94199379402 # number of overall MSHR miss cycles |
| 1278system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles | 1258system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles |
| 1279system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2909184500 # number of ReadReq MSHR uncacheable cycles 1280system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6702281000 # number of ReadReq MSHR uncacheable cycles | 1259system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5448952500 # number of ReadReq MSHR uncacheable cycles 1260system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9242049000 # number of ReadReq MSHR uncacheable cycles |
| 1281system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles | 1261system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles |
| 1282system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2909184500 # number of overall MSHR uncacheable cycles 1283system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6702281000 # number of overall MSHR uncacheable cycles 1284system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for ReadReq accesses 1285system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for ReadReq accesses 1286system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062868 # mshr miss rate for ReadReq accesses | 1262system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5448952500 # number of overall MSHR uncacheable cycles 1263system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9242049000 # number of overall MSHR uncacheable cycles 1264system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for ReadReq accesses 1265system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for ReadReq accesses 1266system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062555 # mshr miss rate for ReadReq accesses |
| 1287system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1288system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1289system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1290system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1291system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1292system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1293system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1294system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1267system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1268system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1269system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1270system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1271system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1272system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1273system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1274system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1295system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.204964 # mshr miss rate for ReadExReq accesses 1296system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.204964 # mshr miss rate for ReadExReq accesses 1297system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for ReadCleanReq accesses 1298system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092084 # mshr miss rate for ReadCleanReq accesses 1299system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242633 # mshr miss rate for ReadSharedReq accesses 1300system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242633 # mshr miss rate for ReadSharedReq accesses 1301system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.726644 # mshr miss rate for InvalidateReq accesses 1302system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.726644 # mshr miss rate for InvalidateReq accesses 1303system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for demand accesses 1304system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for demand accesses 1305system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for demand accesses 1306system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for demand accesses 1307system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159374 # mshr miss rate for demand accesses 1308system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for overall accesses 1309system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for overall accesses 1310system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for overall accesses 1311system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for overall accesses | 1275system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.211294 # mshr miss rate for ReadExReq accesses 1276system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.211294 # mshr miss rate for ReadExReq accesses 1277system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for ReadCleanReq accesses 1278system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089860 # mshr miss rate for ReadCleanReq accesses 1279system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242397 # mshr miss rate for ReadSharedReq accesses 1280system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242397 # mshr miss rate for ReadSharedReq accesses 1281system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.733585 # mshr miss rate for InvalidateReq accesses 1282system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.733585 # mshr miss rate for InvalidateReq accesses 1283system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for demand accesses 1284system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for demand accesses 1285system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for demand accesses 1286system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for demand accesses 1287system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157982 # mshr miss rate for demand accesses 1288system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for overall accesses 1289system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for overall accesses 1290system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for overall accesses 1291system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for overall accesses |
| 1312system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1292system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1313system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231324 # mshr miss rate for overall accesses 1314system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average ReadReq mshr miss latency 1315system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average ReadReq mshr miss latency 1316system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28364.489475 # average ReadReq mshr miss latency 1317system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average HardPFReq mshr miss latency 1318system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49385.735208 # average HardPFReq mshr miss latency 1319system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18573.965548 # average UpgradeReq mshr miss latency 1320system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18573.965548 # average UpgradeReq mshr miss latency 1321system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15227.675321 # average SCUpgradeReq mshr miss latency 1322system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15227.675321 # average SCUpgradeReq mshr miss latency 1323system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178549.700000 # average SCUpgradeFailReq mshr miss latency 1324system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178549.700000 # average SCUpgradeFailReq mshr miss latency 1325system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48088.156473 # average ReadExReq mshr miss latency 1326system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48088.156473 # average ReadExReq mshr miss latency 1327system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average ReadCleanReq mshr miss latency 1328system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31960.284185 # average ReadCleanReq mshr miss latency 1329system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32588.368843 # average ReadSharedReq mshr miss latency 1330system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32588.368843 # average ReadSharedReq mshr miss latency 1331system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32541.105310 # average InvalidateReq mshr miss latency 1332system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32541.105310 # average InvalidateReq mshr miss latency 1333system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency 1334system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency 1335system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency 1336system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency 1337system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34607.596091 # average overall mshr miss latency 1338system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency 1339system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency 1340system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency 1341system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency 1342system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average overall mshr miss latency 1343system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39204.122111 # average overall mshr miss latency | 1293system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229343 # mshr miss rate for overall accesses 1294system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average ReadReq mshr miss latency 1295system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average ReadReq mshr miss latency 1296system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27858.040300 # average ReadReq mshr miss latency 1297system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average HardPFReq mshr miss latency 1298system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51278.255674 # average HardPFReq mshr miss latency 1299system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18620.800908 # average UpgradeReq mshr miss latency 1300system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18620.800908 # average UpgradeReq mshr miss latency 1301system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15355.240121 # average SCUpgradeReq mshr miss latency 1302system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15355.240121 # average SCUpgradeReq mshr miss latency 1303system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 407999.750000 # average SCUpgradeFailReq mshr miss latency 1304system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 407999.750000 # average SCUpgradeFailReq mshr miss latency 1305system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48519.631094 # average ReadExReq mshr miss latency 1306system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48519.631094 # average ReadExReq mshr miss latency 1307system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average ReadCleanReq mshr miss latency 1308system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32868.658964 # average ReadCleanReq mshr miss latency 1309system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33401.924446 # average ReadSharedReq mshr miss latency 1310system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33401.924446 # average ReadSharedReq mshr miss latency 1311system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31581.382996 # average InvalidateReq mshr miss latency 1312system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency 1313system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency 1314system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency 1315system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency 1316system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency 1317system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency 1318system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency 1319system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency 1320system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency 1321system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency 1322system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency 1323system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency |
| 1344system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency | 1324system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency |
| 1345system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142 # average ReadReq mshr uncacheable latency 1346system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300 # average ReadReq mshr uncacheable latency | 1325system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency 1326system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency |
| 1347system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency | 1327system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency |
| 1348system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763 # average overall mshr uncacheable latency 1349system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399 # average overall mshr uncacheable latency 1350system.cpu0.toL2Bus.snoop_filter.tot_requests 22159208 # Total number of requests made to the snoop filter. 1351system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11368269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1352system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1353system.cpu0.toL2Bus.snoop_filter.tot_snoops 619514 # Total number of snoops made to the snoop filter. 1354system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 619512 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1355system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1356system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1357system.cpu0.toL2Bus.trans_dist::ReadReq 553426 # Transaction distribution 1358system.cpu0.toL2Bus.trans_dist::ReadResp 9465318 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::WriteReq 17695 # Transaction distribution 1361system.cpu0.toL2Bus.trans_dist::WriteResp 17694 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::WritebackDirty 5316723 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::WritebackClean 6896635 # Transaction distribution 1364system.cpu0.toL2Bus.trans_dist::CleanEvict 1098455 # Transaction distribution 1365system.cpu0.toL2Bus.trans_dist::HardPFReq 916448 # Transaction distribution 1366system.cpu0.toL2Bus.trans_dist::UpgradeReq 433150 # Transaction distribution 1367system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 369627 # Transaction distribution 1368system.cpu0.toL2Bus.trans_dist::UpgradeResp 506111 # Transaction distribution 1369system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution 1370system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 1371system.cpu0.toL2Bus.trans_dist::ReadExReq 1214944 # Transaction distribution 1372system.cpu0.toL2Bus.trans_dist::ReadExResp 1192020 # Transaction distribution 1373system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4960072 # Transaction distribution 1374system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4756139 # Transaction distribution 1375system.cpu0.toL2Bus.trans_dist::InvalidateReq 842201 # Transaction distribution 1376system.cpu0.toL2Bus.trans_dist::InvalidateResp 794505 # Transaction distribution 1377system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14965952 # Packet count per connected master and slave (bytes) 1378system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18512478 # Packet count per connected master and slave (bytes) 1379system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327835 # Packet count per connected master and slave (bytes) 1380system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 591529 # Packet count per connected master and slave (bytes) 1381system.cpu0.toL2Bus.pkt_count::total 34397794 # Packet count per connected master and slave (bytes) 1382system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 635028820 # Cumulative packet size per connected master and slave (bytes) 1383system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696134983 # Cumulative packet size per connected master and slave (bytes) 1384system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241656 # Cumulative packet size per connected master and slave (bytes) 1385system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2161912 # Cumulative packet size per connected master and slave (bytes) 1386system.cpu0.toL2Bus.pkt_size::total 1334567371 # Cumulative packet size per connected master and slave (bytes) 1387system.cpu0.toL2Bus.snoops 5130075 # Total snoops (count) 1388system.cpu0.toL2Bus.snoopTraffic 104832276 # Total snoop traffic (bytes) 1389system.cpu0.toL2Bus.snoop_fanout::samples 16684270 # Request fanout histogram 1390system.cpu0.toL2Bus.snoop_fanout::mean 0.051566 # Request fanout histogram 1391system.cpu0.toL2Bus.snoop_fanout::stdev 0.221149 # Request fanout histogram | 1328system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency 1329system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency 1330system.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter. 1331system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1332system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1333system.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter. 1334system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1335system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1336system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1337system.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution 1338system.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution 1339system.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution 1340system.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution 1341system.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution 1342system.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution 1343system.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution 1344system.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution 1345system.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution 1346system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution 1347system.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution 1348system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution 1349system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 1350system.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution 1351system.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution 1352system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution 1353system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution 1354system.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution 1355system.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution 1356system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes) 1357system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes) 1358system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes) 1359system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes) 1360system.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes) 1361system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes) 1362system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes) 1363system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes) 1364system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes) 1365system.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes) 1366system.cpu0.toL2Bus.snoops 5091046 # Total snoops (count) 1367system.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes) 1368system.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram 1369system.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram 1370system.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram |
| 1392system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1371system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1393system.cpu0.toL2Bus.snoop_fanout::0 15823936 94.84% 94.84% # Request fanout histogram 1394system.cpu0.toL2Bus.snoop_fanout::1 860332 5.16% 100.00% # Request fanout histogram 1395system.cpu0.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram | 1372system.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram 1373system.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram 1374system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| 1396system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1397system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram | 1375system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1376system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1398system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1399system.cpu0.toL2Bus.snoop_fanout::total 16684270 # Request fanout histogram 1400system.cpu0.toL2Bus.reqLayer0.occupancy 21945410994 # Layer occupancy (ticks) | 1377system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1378system.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram 1379system.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks) |
| 1401system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1380system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1402system.cpu0.toL2Bus.snoopLayer0.occupancy 195855793 # Layer occupancy (ticks) | 1381system.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks) |
| 1403system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1382system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1404system.cpu0.toL2Bus.respLayer0.occupancy 7483231500 # Layer occupancy (ticks) | 1383system.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks) |
| 1405system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1384system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1406system.cpu0.toL2Bus.respLayer1.occupancy 8196031021 # Layer occupancy (ticks) | 1385system.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks) |
| 1407system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1386system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1408system.cpu0.toL2Bus.respLayer2.occupancy 172628000 # Layer occupancy (ticks) | 1387system.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks) |
| 1409system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1388system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1410system.cpu0.toL2Bus.respLayer3.occupancy 321290000 # Layer occupancy (ticks) | 1389system.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks) |
| 1411system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1390system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1412system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 1391system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 1413system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1414system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1415system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1416system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1417system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1418system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1419system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1420system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1434system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1435system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1436system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1437system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1438system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1439system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1440system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1441system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1392system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1393system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1394system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1395system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1396system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1397system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1398system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1399system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1413system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1414system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1415system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1416system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1417system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1418system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1419system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1420system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1442system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1443system.cpu1.dtb.walker.walks 99152 # Table walker walks requested 1444system.cpu1.dtb.walker.walksLong 99152 # Table walker walks initiated with long descriptors 1445system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8586 # Level at which table walker walks with long descriptors terminate 1446system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75770 # Level at which table walker walks with long descriptors terminate 1447system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting 1448system.cpu1.dtb.walker.walkWaitTime::samples 99148 # Table walker wait (enqueue to first request) latency 1449system.cpu1.dtb.walker.walkWaitTime::mean 0.080687 # Table walker wait (enqueue to first request) latency 1450system.cpu1.dtb.walker.walkWaitTime::stdev 25.406685 # Table walker wait (enqueue to first request) latency 1451system.cpu1.dtb.walker.walkWaitTime::0-511 99147 100.00% 100.00% # Table walker wait (enqueue to first request) latency | 1421system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1422system.cpu1.dtb.walker.walks 105151 # Table walker walks requested 1423system.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors 1424system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate 1425system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate 1426system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting 1427system.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency 1428system.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency 1429system.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency 1430system.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 1452system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency | 1431system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 1453system.cpu1.dtb.walker.walkWaitTime::total 99148 # Table walker wait (enqueue to first request) latency 1454system.cpu1.dtb.walker.walkCompletionTime::samples 84360 # Table walker service (enqueue to completion) latency 1455system.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574 # Table walker service (enqueue to completion) latency 1456system.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597 # Table walker service (enqueue to completion) latency 1457system.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703 # Table walker service (enqueue to completion) latency 1458system.cpu1.dtb.walker.walkCompletionTime::0-65535 83116 98.53% 98.53% # Table walker service (enqueue to completion) latency 1459system.cpu1.dtb.walker.walkCompletionTime::65536-131071 940 1.11% 99.64% # Table walker service (enqueue to completion) latency 1460system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.19% 99.83% # Table walker service (enqueue to completion) latency 1461system.cpu1.dtb.walker.walkCompletionTime::196608-262143 58 0.07% 99.90% # Table walker service (enqueue to completion) latency 1462system.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.94% # Table walker service (enqueue to completion) latency 1463system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.97% # Table walker service (enqueue to completion) latency 1464system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 1465system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 1466system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.02% 100.00% # Table walker service (enqueue to completion) latency 1467system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1468system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1469system.cpu1.dtb.walker.walkCompletionTime::total 84360 # Table walker service (enqueue to completion) latency 1470system.cpu1.dtb.walker.walksPending::samples 407519048 # Table walker pending requests distribution 1471system.cpu1.dtb.walker.walksPending::mean 2.490877 # Table walker pending requests distribution 1472system.cpu1.dtb.walker.walksPending::0 -607560648 -149.09% -149.09% # Table walker pending requests distribution 1473system.cpu1.dtb.walker.walksPending::1 1015079696 249.09% 100.00% # Table walker pending requests distribution 1474system.cpu1.dtb.walker.walksPending::total 407519048 # Table walker pending requests distribution 1475system.cpu1.dtb.walker.walkPageSizes::4K 75770 89.82% 89.82% # Table walker page sizes translated 1476system.cpu1.dtb.walker.walkPageSizes::2M 8586 10.18% 100.00% # Table walker page sizes translated 1477system.cpu1.dtb.walker.walkPageSizes::total 84356 # Table walker page sizes translated 1478system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99152 # Table walker requests started/completed, data/inst | 1432system.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency 1433system.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency 1434system.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency 1435system.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency 1436system.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency 1437system.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency 1438system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency 1439system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency 1440system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency 1441system.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency 1442system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency 1443system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency 1444system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency 1445system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency 1446system.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency 1447system.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1448system.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency 1449system.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution 1450system.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution 1451system.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution 1452system.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution 1453system.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution 1454system.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution 1455system.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated 1456system.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated 1457system.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated 1458system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst |
| 1479system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1459system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1480system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99152 # Table walker requests started/completed, data/inst 1481system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84356 # Table walker requests started/completed, data/inst | 1460system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst 1461system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst |
| 1482system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1462system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1483system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84356 # Table walker requests started/completed, data/inst 1484system.cpu1.dtb.walker.walkRequestOrigin::total 183508 # Table walker requests started/completed, data/inst | 1463system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst 1464system.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst |
| 1485system.cpu1.dtb.inst_hits 0 # ITB inst hits 1486system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1465system.cpu1.dtb.inst_hits 0 # ITB inst hits 1466system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1487system.cpu1.dtb.read_hits 78885011 # DTB read hits 1488system.cpu1.dtb.read_misses 72039 # DTB read misses 1489system.cpu1.dtb.write_hits 71761800 # DTB write hits 1490system.cpu1.dtb.write_misses 27113 # DTB write misses | 1467system.cpu1.dtb.read_hits 80227147 # DTB read hits 1468system.cpu1.dtb.read_misses 76874 # DTB read misses 1469system.cpu1.dtb.write_hits 72873093 # DTB write hits 1470system.cpu1.dtb.write_misses 28277 # DTB write misses |
| 1491system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1492system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1471system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1472system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1493system.cpu1.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID | 1473system.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID |
| 1494system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 1474system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 1495system.cpu1.dtb.flush_entries 36637 # Number of entries that have been flushed from TLB | 1475system.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB |
| 1496system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1476system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1497system.cpu1.dtb.prefetch_faults 3802 # Number of TLB faults due to prefetch | 1477system.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch |
| 1498system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1478system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1499system.cpu1.dtb.perms_faults 10123 # Number of TLB faults due to permissions restrictions 1500system.cpu1.dtb.read_accesses 78957050 # DTB read accesses 1501system.cpu1.dtb.write_accesses 71788913 # DTB write accesses | 1479system.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions 1480system.cpu1.dtb.read_accesses 80304021 # DTB read accesses 1481system.cpu1.dtb.write_accesses 72901370 # DTB write accesses |
| 1502system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1482system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1503system.cpu1.dtb.hits 150646811 # DTB hits 1504system.cpu1.dtb.misses 99152 # DTB misses 1505system.cpu1.dtb.accesses 150745963 # DTB accesses 1506system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 1483system.cpu1.dtb.hits 153100240 # DTB hits 1484system.cpu1.dtb.misses 105151 # DTB misses 1485system.cpu1.dtb.accesses 153205391 # DTB accesses 1486system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 1507system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1508system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1509system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1510system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1511system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1512system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1513system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1514system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1528system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1529system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1530system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1531system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1532system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1533system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1534system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1535system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1487system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1488system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1489system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1490system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1491system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1492system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1493system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1494system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1508system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1509system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1510system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1511system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1512system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1513system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1514system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1515system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1536system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1537system.cpu1.itb.walker.walks 58316 # Table walker walks requested 1538system.cpu1.itb.walker.walksLong 58316 # Table walker walks initiated with long descriptors 1539system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate 1540system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52495 # Level at which table walker walks with long descriptors terminate 1541system.cpu1.itb.walker.walkWaitTime::samples 58316 # Table walker wait (enqueue to first request) latency 1542system.cpu1.itb.walker.walkWaitTime::0 58316 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1543system.cpu1.itb.walker.walkWaitTime::total 58316 # Table walker wait (enqueue to first request) latency 1544system.cpu1.itb.walker.walkCompletionTime::samples 53121 # Table walker service (enqueue to completion) latency 1545system.cpu1.itb.walker.walkCompletionTime::mean 27183.693831 # Table walker service (enqueue to completion) latency 1546system.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403 # Table walker service (enqueue to completion) latency 1547system.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195 # Table walker service (enqueue to completion) latency 1548system.cpu1.itb.walker.walkCompletionTime::0-65535 51734 97.39% 97.39% # Table walker service (enqueue to completion) latency 1549system.cpu1.itb.walker.walkCompletionTime::65536-131071 949 1.79% 99.18% # Table walker service (enqueue to completion) latency 1550system.cpu1.itb.walker.walkCompletionTime::131072-196607 242 0.46% 99.63% # Table walker service (enqueue to completion) latency 1551system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.15% 99.78% # Table walker service (enqueue to completion) latency 1552system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.88% # Table walker service (enqueue to completion) latency 1553system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.91% # Table walker service (enqueue to completion) latency 1554system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.92% # Table walker service (enqueue to completion) latency 1555system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.93% # Table walker service (enqueue to completion) latency 1556system.cpu1.itb.walker.walkCompletionTime::589824-655359 33 0.06% 99.99% # Table walker service (enqueue to completion) latency 1557system.cpu1.itb.walker.walkCompletionTime::655360-720895 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1558system.cpu1.itb.walker.walkCompletionTime::total 53121 # Table walker service (enqueue to completion) latency 1559system.cpu1.itb.walker.walksPending::samples -615394148 # Table walker pending requests distribution 1560system.cpu1.itb.walker.walksPending::0 -615394148 100.00% 100.00% # Table walker pending requests distribution 1561system.cpu1.itb.walker.walksPending::total -615394148 # Table walker pending requests distribution 1562system.cpu1.itb.walker.walkPageSizes::4K 52495 98.82% 98.82% # Table walker page sizes translated 1563system.cpu1.itb.walker.walkPageSizes::2M 626 1.18% 100.00% # Table walker page sizes translated 1564system.cpu1.itb.walker.walkPageSizes::total 53121 # Table walker page sizes translated | 1516system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1517system.cpu1.itb.walker.walks 60537 # Table walker walks requested 1518system.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors 1519system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate 1520system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate 1521system.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency 1522system.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1523system.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency 1524system.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency 1525system.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency 1526system.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency 1527system.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency 1528system.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency 1529system.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency 1530system.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency 1531system.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency 1532system.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency 1533system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency 1534system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency 1535system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency 1536system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency 1537system.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency 1538system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1539system.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency 1540system.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution 1541system.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution 1542system.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution 1543system.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated 1544system.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated 1545system.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated |
| 1565system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1546system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1566system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58316 # Table walker requests started/completed, data/inst 1567system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58316 # Table walker requests started/completed, data/inst | 1547system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst 1548system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst |
| 1568system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1549system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1569system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53121 # Table walker requests started/completed, data/inst 1570system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53121 # Table walker requests started/completed, data/inst 1571system.cpu1.itb.walker.walkRequestOrigin::total 111437 # Table walker requests started/completed, data/inst 1572system.cpu1.itb.inst_hits 416140593 # ITB inst hits 1573system.cpu1.itb.inst_misses 58316 # ITB inst misses | 1550system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst 1551system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst 1552system.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst 1553system.cpu1.itb.inst_hits 423099313 # ITB inst hits 1554system.cpu1.itb.inst_misses 60537 # ITB inst misses |
| 1574system.cpu1.itb.read_hits 0 # DTB read hits 1575system.cpu1.itb.read_misses 0 # DTB read misses 1576system.cpu1.itb.write_hits 0 # DTB write hits 1577system.cpu1.itb.write_misses 0 # DTB write misses 1578system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1579system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1555system.cpu1.itb.read_hits 0 # DTB read hits 1556system.cpu1.itb.read_misses 0 # DTB read misses 1557system.cpu1.itb.write_hits 0 # DTB write hits 1558system.cpu1.itb.write_misses 0 # DTB write misses 1559system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1560system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1580system.cpu1.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID | 1561system.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID |
| 1581system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 1562system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 1582system.cpu1.itb.flush_entries 25699 # Number of entries that have been flushed from TLB | 1563system.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB |
| 1583system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1584system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1585system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1586system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1587system.cpu1.itb.read_accesses 0 # DTB read accesses 1588system.cpu1.itb.write_accesses 0 # DTB write accesses | 1564system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1565system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1566system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1567system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1568system.cpu1.itb.read_accesses 0 # DTB read accesses 1569system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1589system.cpu1.itb.inst_accesses 416198909 # ITB inst accesses 1590system.cpu1.itb.hits 416140593 # DTB hits 1591system.cpu1.itb.misses 58316 # DTB misses 1592system.cpu1.itb.accesses 416198909 # DTB accesses 1593system.cpu1.numPwrStateTransitions 28692 # Number of power state transitions 1594system.cpu1.pwrStateClkGateDist::samples 14346 # Distribution of time spent in the clock gated state 1595system.cpu1.pwrStateClkGateDist::mean 3269284130.341071 # Distribution of time spent in the clock gated state 1596system.cpu1.pwrStateClkGateDist::stdev 86001867955.202789 # Distribution of time spent in the clock gated state 1597system.cpu1.pwrStateClkGateDist::underflows 3953 27.55% 27.55% # Distribution of time spent in the clock gated state 1598system.cpu1.pwrStateClkGateDist::1000-5e+10 10364 72.24% 99.80% # Distribution of time spent in the clock gated state 1599system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.83% # Distribution of time spent in the clock gated state 1600system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 1601system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state 1602system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 1603system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 1604system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 1605system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 1606system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 1607system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state | 1570system.cpu1.itb.inst_accesses 423159850 # ITB inst accesses 1571system.cpu1.itb.hits 423099313 # DTB hits 1572system.cpu1.itb.misses 60537 # DTB misses 1573system.cpu1.itb.accesses 423159850 # DTB accesses 1574system.cpu1.numPwrStateTransitions 11486 # Number of power state transitions 1575system.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state 1576system.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state 1577system.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state 1578system.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state 1579system.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state 1580system.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state 1581system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state 1582system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state 1583system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state 1584system.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state |
| 1608system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 1585system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 1609system.cpu1.pwrStateClkGateDist::max_value 7510077904252 # Distribution of time spent in the clock gated state 1610system.cpu1.pwrStateClkGateDist::total 14346 # Distribution of time spent in the clock gated state 1611system.cpu1.pwrStateResidencyTicks::ON 503862826627 # Cumulative time (in ticks) in various power states 1612system.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873 # Cumulative time (in ticks) in various power states 1613system.cpu1.numCycles 94810025921 # number of cpu cycles simulated | 1586system.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state 1587system.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state 1588system.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states 1589system.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states 1590system.cpu1.numCycles 94810161765 # number of cpu cycles simulated |
| 1614system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1615system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1616system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1591system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1592system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1593system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1617system.cpu1.kern.inst.quiesce 14346 # number of quiesce instructions executed 1618system.cpu1.committedInsts 415840875 # Number of instructions committed 1619system.cpu1.committedOps 490335926 # Number of ops (including micro ops) committed 1620system.cpu1.num_int_alu_accesses 450775425 # Number of integer alu accesses 1621system.cpu1.num_fp_alu_accesses 467875 # Number of float alu accesses 1622system.cpu1.num_func_calls 24835210 # number of times a function call or return occured 1623system.cpu1.num_conditional_control_insts 63203882 # number of instructions that are conditional controls 1624system.cpu1.num_int_insts 450775425 # number of integer instructions 1625system.cpu1.num_fp_insts 467875 # number of float instructions 1626system.cpu1.num_int_register_reads 655878523 # number of times the integer registers were read 1627system.cpu1.num_int_register_writes 357644258 # number of times the integer registers were written 1628system.cpu1.num_fp_register_reads 746575 # number of times the floating registers were read 1629system.cpu1.num_fp_register_writes 415812 # number of times the floating registers were written 1630system.cpu1.num_cc_register_reads 107608929 # number of times the CC registers were read 1631system.cpu1.num_cc_register_writes 107374492 # number of times the CC registers were written 1632system.cpu1.num_mem_refs 150638767 # number of memory refs 1633system.cpu1.num_load_insts 78882725 # Number of load instructions 1634system.cpu1.num_store_insts 71756042 # Number of store instructions 1635system.cpu1.num_idle_cycles 93802300267.744019 # Number of idle cycles 1636system.cpu1.num_busy_cycles 1007725653.255979 # Number of busy cycles 1637system.cpu1.not_idle_fraction 0.010629 # Percentage of non-idle cycles 1638system.cpu1.idle_fraction 0.989371 # Percentage of idle cycles 1639system.cpu1.Branches 92635099 # Number of branches fetched | 1594system.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed 1595system.cpu1.committedInsts 422818462 # Number of instructions committed 1596system.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed 1597system.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses 1598system.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses 1599system.cpu1.num_func_calls 25225246 # number of times a function call or return occured 1600system.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls 1601system.cpu1.num_int_insts 458669371 # number of integer instructions 1602system.cpu1.num_fp_insts 488965 # number of float instructions 1603system.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read 1604system.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written 1605system.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read 1606system.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written 1607system.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read 1608system.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written 1609system.cpu1.num_mem_refs 153090665 # number of memory refs 1610system.cpu1.num_load_insts 80223644 # Number of load instructions 1611system.cpu1.num_store_insts 72867021 # Number of store instructions 1612system.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles 1613system.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles 1614system.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles 1615system.cpu1.idle_fraction 0.989313 # Percentage of idle cycles 1616system.cpu1.Branches 94103649 # Number of branches fetched |
| 1640system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction | 1617system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction |
| 1641system.cpu1.op_class::IntAlu 338840052 69.06% 69.06% # Class of executed instruction 1642system.cpu1.op_class::IntMult 1031473 0.21% 69.27% # Class of executed instruction 1643system.cpu1.op_class::IntDiv 58381 0.01% 69.28% # Class of executed instruction 1644system.cpu1.op_class::FloatAdd 8 0.00% 69.28% # Class of executed instruction 1645system.cpu1.op_class::FloatCmp 13 0.00% 69.28% # Class of executed instruction 1646system.cpu1.op_class::FloatCvt 21 0.00% 69.28% # Class of executed instruction 1647system.cpu1.op_class::FloatMult 0 0.00% 69.28% # Class of executed instruction 1648system.cpu1.op_class::FloatMultAcc 0 0.00% 69.28% # Class of executed instruction 1649system.cpu1.op_class::FloatDiv 0 0.00% 69.28% # Class of executed instruction 1650system.cpu1.op_class::FloatMisc 67037 0.01% 69.30% # Class of executed instruction 1651system.cpu1.op_class::FloatSqrt 0 0.00% 69.30% # Class of executed instruction 1652system.cpu1.op_class::SimdAdd 0 0.00% 69.30% # Class of executed instruction 1653system.cpu1.op_class::SimdAddAcc 0 0.00% 69.30% # Class of executed instruction 1654system.cpu1.op_class::SimdAlu 0 0.00% 69.30% # Class of executed instruction 1655system.cpu1.op_class::SimdCmp 0 0.00% 69.30% # Class of executed instruction 1656system.cpu1.op_class::SimdCvt 0 0.00% 69.30% # Class of executed instruction 1657system.cpu1.op_class::SimdMisc 0 0.00% 69.30% # Class of executed instruction 1658system.cpu1.op_class::SimdMult 0 0.00% 69.30% # Class of executed instruction 1659system.cpu1.op_class::SimdMultAcc 0 0.00% 69.30% # Class of executed instruction 1660system.cpu1.op_class::SimdShift 0 0.00% 69.30% # Class of executed instruction 1661system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.30% # Class of executed instruction 1662system.cpu1.op_class::SimdSqrt 0 0.00% 69.30% # Class of executed instruction 1663system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.30% # Class of executed instruction 1664system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.30% # Class of executed instruction 1665system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.30% # Class of executed instruction 1666system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.30% # Class of executed instruction 1667system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.30% # Class of executed instruction 1668system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.30% # Class of executed instruction 1669system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction 1670system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction 1671system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction 1672system.cpu1.op_class::MemRead 78824615 16.07% 85.36% # Class of executed instruction 1673system.cpu1.op_class::MemWrite 71413356 14.56% 99.92% # Class of executed instruction 1674system.cpu1.op_class::FloatMemRead 58110 0.01% 99.93% # Class of executed instruction 1675system.cpu1.op_class::FloatMemWrite 342686 0.07% 100.00% # Class of executed instruction | 1618system.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction 1619system.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction 1620system.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction 1621system.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction 1622system.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction 1623system.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction 1624system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction 1625system.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction 1626system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction 1627system.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction 1628system.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction 1629system.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction 1630system.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction 1631system.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction 1632system.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction 1633system.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction 1634system.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction 1635system.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction 1636system.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction 1637system.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction 1638system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction 1639system.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction 1640system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction 1641system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction 1642system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction 1643system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction 1644system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction 1645system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction 1646system.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction 1647system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction 1648system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction 1649system.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction 1650system.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction 1651system.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction 1652system.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction |
| 1676system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1677system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1653system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1654system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1678system.cpu1.op_class::total 490635753 # Class of executed instruction 1679system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1680system.cpu1.dcache.tags.replacements 4949273 # number of replacements 1681system.cpu1.dcache.tags.tagsinuse 456.328608 # Cycle average of tags in use 1682system.cpu1.dcache.tags.total_refs 145491110 # Total number of references to valid blocks. 1683system.cpu1.dcache.tags.sampled_refs 4949785 # Sample count of references to valid blocks. 1684system.cpu1.dcache.tags.avg_refs 29.393420 # Average number of references to valid blocks. 1685system.cpu1.dcache.tags.warmup_cycle 8379669141000 # Cycle when the warmup percentage was hit. 1686system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.328608 # Average occupied blocks per requestor 1687system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891267 # Average percentage of cache occupancy 1688system.cpu1.dcache.tags.occ_percent::total 0.891267 # Average percentage of cache occupancy | 1655system.cpu1.op_class::total 499098010 # Class of executed instruction 1656system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1657system.cpu1.dcache.tags.replacements 5131141 # number of replacements 1658system.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use 1659system.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks. 1660system.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks. 1661system.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks. 1662system.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit. 1663system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor 1664system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy 1665system.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy |
| 1689system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1666system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1690system.cpu1.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 1691system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id 1692system.cpu1.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id | 1667system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 1668system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id 1669system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id |
| 1693system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1670system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1694system.cpu1.dcache.tags.tag_accesses 306227498 # Number of tag accesses 1695system.cpu1.dcache.tags.data_accesses 306227498 # Number of data accesses 1696system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1697system.cpu1.dcache.ReadReq_hits::cpu1.data 73475131 # number of ReadReq hits 1698system.cpu1.dcache.ReadReq_hits::total 73475131 # number of ReadReq hits 1699system.cpu1.dcache.WriteReq_hits::cpu1.data 68103188 # number of WriteReq hits 1700system.cpu1.dcache.WriteReq_hits::total 68103188 # number of WriteReq hits 1701system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168046 # number of SoftPFReq hits 1702system.cpu1.dcache.SoftPFReq_hits::total 168046 # number of SoftPFReq hits 1703system.cpu1.dcache.WriteLineReq_hits::cpu1.data 87192 # number of WriteLineReq hits 1704system.cpu1.dcache.WriteLineReq_hits::total 87192 # number of WriteLineReq hits 1705system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1644934 # number of LoadLockedReq hits 1706system.cpu1.dcache.LoadLockedReq_hits::total 1644934 # number of LoadLockedReq hits 1707system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602204 # number of StoreCondReq hits 1708system.cpu1.dcache.StoreCondReq_hits::total 1602204 # number of StoreCondReq hits 1709system.cpu1.dcache.demand_hits::cpu1.data 141665511 # number of demand (read+write) hits 1710system.cpu1.dcache.demand_hits::total 141665511 # number of demand (read+write) hits 1711system.cpu1.dcache.overall_hits::cpu1.data 141833557 # number of overall hits 1712system.cpu1.dcache.overall_hits::total 141833557 # number of overall hits 1713system.cpu1.dcache.ReadReq_misses::cpu1.data 2804863 # number of ReadReq misses 1714system.cpu1.dcache.ReadReq_misses::total 2804863 # number of ReadReq misses 1715system.cpu1.dcache.WriteReq_misses::cpu1.data 1292961 # number of WriteReq misses 1716system.cpu1.dcache.WriteReq_misses::total 1292961 # number of WriteReq misses 1717system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609189 # number of SoftPFReq misses 1718system.cpu1.dcache.SoftPFReq_misses::total 609189 # number of SoftPFReq misses 1719system.cpu1.dcache.WriteLineReq_misses::cpu1.data 443031 # number of WriteLineReq misses 1720system.cpu1.dcache.WriteLineReq_misses::total 443031 # number of WriteLineReq misses 1721system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160663 # number of LoadLockedReq misses 1722system.cpu1.dcache.LoadLockedReq_misses::total 160663 # number of LoadLockedReq misses 1723system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202242 # number of StoreCondReq misses 1724system.cpu1.dcache.StoreCondReq_misses::total 202242 # number of StoreCondReq misses 1725system.cpu1.dcache.demand_misses::cpu1.data 4540855 # number of demand (read+write) misses 1726system.cpu1.dcache.demand_misses::total 4540855 # number of demand (read+write) misses 1727system.cpu1.dcache.overall_misses::cpu1.data 5150044 # number of overall misses 1728system.cpu1.dcache.overall_misses::total 5150044 # number of overall misses 1729system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42649111500 # number of ReadReq miss cycles 1730system.cpu1.dcache.ReadReq_miss_latency::total 42649111500 # number of ReadReq miss cycles 1731system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25017964000 # number of WriteReq miss cycles 1732system.cpu1.dcache.WriteReq_miss_latency::total 25017964000 # number of WriteReq miss cycles 1733system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10518897000 # number of WriteLineReq miss cycles 1734system.cpu1.dcache.WriteLineReq_miss_latency::total 10518897000 # number of WriteLineReq miss cycles 1735system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2505987000 # number of LoadLockedReq miss cycles 1736system.cpu1.dcache.LoadLockedReq_miss_latency::total 2505987000 # number of LoadLockedReq miss cycles 1737system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4791659000 # number of StoreCondReq miss cycles 1738system.cpu1.dcache.StoreCondReq_miss_latency::total 4791659000 # number of StoreCondReq miss cycles 1739system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2159000 # number of StoreCondFailReq miss cycles 1740system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2159000 # number of StoreCondFailReq miss cycles 1741system.cpu1.dcache.demand_miss_latency::cpu1.data 78185972500 # number of demand (read+write) miss cycles 1742system.cpu1.dcache.demand_miss_latency::total 78185972500 # number of demand (read+write) miss cycles 1743system.cpu1.dcache.overall_miss_latency::cpu1.data 78185972500 # number of overall miss cycles 1744system.cpu1.dcache.overall_miss_latency::total 78185972500 # number of overall miss cycles 1745system.cpu1.dcache.ReadReq_accesses::cpu1.data 76279994 # number of ReadReq accesses(hits+misses) 1746system.cpu1.dcache.ReadReq_accesses::total 76279994 # number of ReadReq accesses(hits+misses) 1747system.cpu1.dcache.WriteReq_accesses::cpu1.data 69396149 # number of WriteReq accesses(hits+misses) 1748system.cpu1.dcache.WriteReq_accesses::total 69396149 # number of WriteReq accesses(hits+misses) 1749system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 777235 # number of SoftPFReq accesses(hits+misses) 1750system.cpu1.dcache.SoftPFReq_accesses::total 777235 # number of SoftPFReq accesses(hits+misses) 1751system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 530223 # number of WriteLineReq accesses(hits+misses) 1752system.cpu1.dcache.WriteLineReq_accesses::total 530223 # number of WriteLineReq accesses(hits+misses) 1753system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1805597 # number of LoadLockedReq accesses(hits+misses) 1754system.cpu1.dcache.LoadLockedReq_accesses::total 1805597 # number of LoadLockedReq accesses(hits+misses) 1755system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1804446 # number of StoreCondReq accesses(hits+misses) 1756system.cpu1.dcache.StoreCondReq_accesses::total 1804446 # number of StoreCondReq accesses(hits+misses) 1757system.cpu1.dcache.demand_accesses::cpu1.data 146206366 # number of demand (read+write) accesses 1758system.cpu1.dcache.demand_accesses::total 146206366 # number of demand (read+write) accesses 1759system.cpu1.dcache.overall_accesses::cpu1.data 146983601 # number of overall (read+write) accesses 1760system.cpu1.dcache.overall_accesses::total 146983601 # number of overall (read+write) accesses 1761system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036771 # miss rate for ReadReq accesses 1762system.cpu1.dcache.ReadReq_miss_rate::total 0.036771 # miss rate for ReadReq accesses 1763system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018632 # miss rate for WriteReq accesses 1764system.cpu1.dcache.WriteReq_miss_rate::total 0.018632 # miss rate for WriteReq accesses 1765system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783790 # miss rate for SoftPFReq accesses 1766system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783790 # miss rate for SoftPFReq accesses 1767system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.835556 # miss rate for WriteLineReq accesses 1768system.cpu1.dcache.WriteLineReq_miss_rate::total 0.835556 # miss rate for WriteLineReq accesses 1769system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088981 # miss rate for LoadLockedReq accesses 1770system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088981 # miss rate for LoadLockedReq accesses 1771system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112080 # miss rate for StoreCondReq accesses 1772system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112080 # miss rate for StoreCondReq accesses 1773system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031058 # miss rate for demand accesses 1774system.cpu1.dcache.demand_miss_rate::total 0.031058 # miss rate for demand accesses 1775system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035038 # miss rate for overall accesses 1776system.cpu1.dcache.overall_miss_rate::total 0.035038 # miss rate for overall accesses 1777system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985 # average ReadReq miss latency 1778system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985 # average ReadReq miss latency 1779system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019 # average WriteReq miss latency 1780system.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019 # average WriteReq miss latency 1781system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012 # average WriteLineReq miss latency 1782system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012 # average WriteLineReq miss latency 1783system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427 # average LoadLockedReq miss latency 1784system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427 # average LoadLockedReq miss latency 1785system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835 # average StoreCondReq miss latency 1786system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835 # average StoreCondReq miss latency | 1671system.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses 1672system.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses 1673system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1674system.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits 1675system.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits 1676system.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits 1677system.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits 1678system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits 1679system.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits 1680system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60851 # number of WriteLineReq hits 1681system.cpu1.dcache.WriteLineReq_hits::total 60851 # number of WriteLineReq hits 1682system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1670690 # number of LoadLockedReq hits 1683system.cpu1.dcache.LoadLockedReq_hits::total 1670690 # number of LoadLockedReq hits 1684system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1646008 # number of StoreCondReq hits 1685system.cpu1.dcache.StoreCondReq_hits::total 1646008 # number of StoreCondReq hits 1686system.cpu1.dcache.demand_hits::cpu1.data 143907086 # number of demand (read+write) hits 1687system.cpu1.dcache.demand_hits::total 143907086 # number of demand (read+write) hits 1688system.cpu1.dcache.overall_hits::cpu1.data 144074861 # number of overall hits 1689system.cpu1.dcache.overall_hits::total 144074861 # number of overall hits 1690system.cpu1.dcache.ReadReq_misses::cpu1.data 2897407 # number of ReadReq misses 1691system.cpu1.dcache.ReadReq_misses::total 2897407 # number of ReadReq misses 1692system.cpu1.dcache.WriteReq_misses::cpu1.data 1336766 # number of WriteReq misses 1693system.cpu1.dcache.WriteReq_misses::total 1336766 # number of WriteReq misses 1694system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634591 # number of SoftPFReq misses 1695system.cpu1.dcache.SoftPFReq_misses::total 634591 # number of SoftPFReq misses 1696system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446061 # number of WriteLineReq misses 1697system.cpu1.dcache.WriteLineReq_misses::total 446061 # number of WriteLineReq misses 1698system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170887 # number of LoadLockedReq misses 1699system.cpu1.dcache.LoadLockedReq_misses::total 170887 # number of LoadLockedReq misses 1700system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194464 # number of StoreCondReq misses 1701system.cpu1.dcache.StoreCondReq_misses::total 194464 # number of StoreCondReq misses 1702system.cpu1.dcache.demand_misses::cpu1.data 4680234 # number of demand (read+write) misses 1703system.cpu1.dcache.demand_misses::total 4680234 # number of demand (read+write) misses 1704system.cpu1.dcache.overall_misses::cpu1.data 5314825 # number of overall misses 1705system.cpu1.dcache.overall_misses::total 5314825 # number of overall misses 1706system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43647010000 # number of ReadReq miss cycles 1707system.cpu1.dcache.ReadReq_miss_latency::total 43647010000 # number of ReadReq miss cycles 1708system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25591315500 # number of WriteReq miss cycles 1709system.cpu1.dcache.WriteReq_miss_latency::total 25591315500 # number of WriteReq miss cycles 1710system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9621405000 # number of WriteLineReq miss cycles 1711system.cpu1.dcache.WriteLineReq_miss_latency::total 9621405000 # number of WriteLineReq miss cycles 1712system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2591957500 # number of LoadLockedReq miss cycles 1713system.cpu1.dcache.LoadLockedReq_miss_latency::total 2591957500 # number of LoadLockedReq miss cycles 1714system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4654513500 # number of StoreCondReq miss cycles 1715system.cpu1.dcache.StoreCondReq_miss_latency::total 4654513500 # number of StoreCondReq miss cycles 1716system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles 1717system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles 1718system.cpu1.dcache.demand_miss_latency::cpu1.data 78859730500 # number of demand (read+write) miss cycles 1719system.cpu1.dcache.demand_miss_latency::total 78859730500 # number of demand (read+write) miss cycles 1720system.cpu1.dcache.overall_miss_latency::cpu1.data 78859730500 # number of overall miss cycles 1721system.cpu1.dcache.overall_miss_latency::total 78859730500 # number of overall miss cycles 1722system.cpu1.dcache.ReadReq_accesses::cpu1.data 77574498 # number of ReadReq accesses(hits+misses) 1723system.cpu1.dcache.ReadReq_accesses::total 77574498 # number of ReadReq accesses(hits+misses) 1724system.cpu1.dcache.WriteReq_accesses::cpu1.data 70505910 # number of WriteReq accesses(hits+misses) 1725system.cpu1.dcache.WriteReq_accesses::total 70505910 # number of WriteReq accesses(hits+misses) 1726system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 802366 # number of SoftPFReq accesses(hits+misses) 1727system.cpu1.dcache.SoftPFReq_accesses::total 802366 # number of SoftPFReq accesses(hits+misses) 1728system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 506912 # number of WriteLineReq accesses(hits+misses) 1729system.cpu1.dcache.WriteLineReq_accesses::total 506912 # number of WriteLineReq accesses(hits+misses) 1730system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1841577 # number of LoadLockedReq accesses(hits+misses) 1731system.cpu1.dcache.LoadLockedReq_accesses::total 1841577 # number of LoadLockedReq accesses(hits+misses) 1732system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1840472 # number of StoreCondReq accesses(hits+misses) 1733system.cpu1.dcache.StoreCondReq_accesses::total 1840472 # number of StoreCondReq accesses(hits+misses) 1734system.cpu1.dcache.demand_accesses::cpu1.data 148587320 # number of demand (read+write) accesses 1735system.cpu1.dcache.demand_accesses::total 148587320 # number of demand (read+write) accesses 1736system.cpu1.dcache.overall_accesses::cpu1.data 149389686 # number of overall (read+write) accesses 1737system.cpu1.dcache.overall_accesses::total 149389686 # number of overall (read+write) accesses 1738system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037350 # miss rate for ReadReq accesses 1739system.cpu1.dcache.ReadReq_miss_rate::total 0.037350 # miss rate for ReadReq accesses 1740system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018960 # miss rate for WriteReq accesses 1741system.cpu1.dcache.WriteReq_miss_rate::total 0.018960 # miss rate for WriteReq accesses 1742system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790900 # miss rate for SoftPFReq accesses 1743system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790900 # miss rate for SoftPFReq accesses 1744system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.879957 # miss rate for WriteLineReq accesses 1745system.cpu1.dcache.WriteLineReq_miss_rate::total 0.879957 # miss rate for WriteLineReq accesses 1746system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092794 # miss rate for LoadLockedReq accesses 1747system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092794 # miss rate for LoadLockedReq accesses 1748system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105660 # miss rate for StoreCondReq accesses 1749system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105660 # miss rate for StoreCondReq accesses 1750system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031498 # miss rate for demand accesses 1751system.cpu1.dcache.demand_miss_rate::total 0.031498 # miss rate for demand accesses 1752system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035577 # miss rate for overall accesses 1753system.cpu1.dcache.overall_miss_rate::total 0.035577 # miss rate for overall accesses 1754system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15064.162543 # average ReadReq miss latency 1755system.cpu1.dcache.ReadReq_avg_miss_latency::total 15064.162543 # average ReadReq miss latency 1756system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19144.199882 # average WriteReq miss latency 1757system.cpu1.dcache.WriteReq_avg_miss_latency::total 19144.199882 # average WriteReq miss latency 1758system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 21569.706834 # average WriteLineReq miss latency 1759system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 21569.706834 # average WriteLineReq miss latency 1760system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15167.669279 # average LoadLockedReq miss latency 1761system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15167.669279 # average LoadLockedReq miss latency 1762system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23935.090814 # average StoreCondReq miss latency 1763system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23935.090814 # average StoreCondReq miss latency |
| 1787system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1788system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1764system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1765system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1789system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185 # average overall miss latency 1790system.cpu1.dcache.demand_avg_miss_latency::total 17218.337185 # average overall miss latency 1791system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526 # average overall miss latency 1792system.cpu1.dcache.overall_avg_miss_latency::total 15181.612526 # average overall miss latency | 1766system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16849.527289 # average overall miss latency 1767system.cpu1.dcache.demand_avg_miss_latency::total 16849.527289 # average overall miss latency 1768system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14837.690893 # average overall miss latency 1769system.cpu1.dcache.overall_avg_miss_latency::total 14837.690893 # average overall miss latency |
| 1793system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1794system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1795system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1796system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1797system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1798system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1770system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1771system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1772system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1773system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1774system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1775system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1799system.cpu1.dcache.writebacks::writebacks 4949273 # number of writebacks 1800system.cpu1.dcache.writebacks::total 4949273 # number of writebacks 1801system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18154 # number of ReadReq MSHR hits 1802system.cpu1.dcache.ReadReq_mshr_hits::total 18154 # number of ReadReq MSHR hits 1803system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 423 # number of WriteReq MSHR hits 1804system.cpu1.dcache.WriteReq_mshr_hits::total 423 # number of WriteReq MSHR hits 1805system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43805 # number of LoadLockedReq MSHR hits 1806system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43805 # number of LoadLockedReq MSHR hits 1807system.cpu1.dcache.demand_mshr_hits::cpu1.data 18577 # number of demand (read+write) MSHR hits 1808system.cpu1.dcache.demand_mshr_hits::total 18577 # number of demand (read+write) MSHR hits 1809system.cpu1.dcache.overall_mshr_hits::cpu1.data 18577 # number of overall MSHR hits 1810system.cpu1.dcache.overall_mshr_hits::total 18577 # number of overall MSHR hits 1811system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2786709 # number of ReadReq MSHR misses 1812system.cpu1.dcache.ReadReq_mshr_misses::total 2786709 # number of ReadReq MSHR misses 1813system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1292538 # number of WriteReq MSHR misses 1814system.cpu1.dcache.WriteReq_mshr_misses::total 1292538 # number of WriteReq MSHR misses 1815system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 609189 # number of SoftPFReq MSHR misses 1816system.cpu1.dcache.SoftPFReq_mshr_misses::total 609189 # number of SoftPFReq MSHR misses 1817system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 443031 # number of WriteLineReq MSHR misses 1818system.cpu1.dcache.WriteLineReq_mshr_misses::total 443031 # number of WriteLineReq MSHR misses 1819system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116858 # number of LoadLockedReq MSHR misses 1820system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116858 # number of LoadLockedReq MSHR misses 1821system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202242 # number of StoreCondReq MSHR misses 1822system.cpu1.dcache.StoreCondReq_mshr_misses::total 202242 # number of StoreCondReq MSHR misses 1823system.cpu1.dcache.demand_mshr_misses::cpu1.data 4522278 # number of demand (read+write) MSHR misses 1824system.cpu1.dcache.demand_mshr_misses::total 4522278 # number of demand (read+write) MSHR misses 1825system.cpu1.dcache.overall_mshr_misses::cpu1.data 5131467 # number of overall MSHR misses 1826system.cpu1.dcache.overall_mshr_misses::total 5131467 # number of overall MSHR misses 1827system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable 1828system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22203 # number of ReadReq MSHR uncacheable 1829system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 1830system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable 1831system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses 1832system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42958 # number of overall MSHR uncacheable misses 1833system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38628648000 # number of ReadReq MSHR miss cycles 1834system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38628648000 # number of ReadReq MSHR miss cycles 1835system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23695979500 # number of WriteReq MSHR miss cycles 1836system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23695979500 # number of WriteReq MSHR miss cycles 1837system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13886318000 # number of SoftPFReq MSHR miss cycles 1838system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13886318000 # number of SoftPFReq MSHR miss cycles 1839system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10075866000 # number of WriteLineReq MSHR miss cycles 1840system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10075866000 # number of WriteLineReq MSHR miss cycles 1841system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623112500 # number of LoadLockedReq MSHR miss cycles 1842system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1623112500 # number of LoadLockedReq MSHR miss cycles 1843system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4589466000 # number of StoreCondReq MSHR miss cycles 1844system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4589466000 # number of StoreCondReq MSHR miss cycles 1845system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2110000 # number of StoreCondFailReq MSHR miss cycles 1846system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2110000 # number of StoreCondFailReq MSHR miss cycles 1847system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72400493500 # number of demand (read+write) MSHR miss cycles 1848system.cpu1.dcache.demand_mshr_miss_latency::total 72400493500 # number of demand (read+write) MSHR miss cycles 1849system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 86286811500 # number of overall MSHR miss cycles 1850system.cpu1.dcache.overall_mshr_miss_latency::total 86286811500 # number of overall MSHR miss cycles 1851system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3923399500 # number of ReadReq MSHR uncacheable cycles 1852system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3923399500 # number of ReadReq MSHR uncacheable cycles 1853system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3923399500 # number of overall MSHR uncacheable cycles 1854system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3923399500 # number of overall MSHR uncacheable cycles 1855system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036533 # mshr miss rate for ReadReq accesses 1856system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036533 # mshr miss rate for ReadReq accesses 1857system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018626 # mshr miss rate for WriteReq accesses 1858system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018626 # mshr miss rate for WriteReq accesses 1859system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783790 # mshr miss rate for SoftPFReq accesses 1860system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783790 # mshr miss rate for SoftPFReq accesses 1861system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.835556 # mshr miss rate for WriteLineReq accesses 1862system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.835556 # mshr miss rate for WriteLineReq accesses 1863system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064720 # mshr miss rate for LoadLockedReq accesses 1864system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064720 # mshr miss rate for LoadLockedReq accesses 1865system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112080 # mshr miss rate for StoreCondReq accesses 1866system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112080 # mshr miss rate for StoreCondReq accesses 1867system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030931 # mshr miss rate for demand accesses 1868system.cpu1.dcache.demand_mshr_miss_rate::total 0.030931 # mshr miss rate for demand accesses 1869system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034912 # mshr miss rate for overall accesses 1870system.cpu1.dcache.overall_mshr_miss_rate::total 0.034912 # mshr miss rate for overall accesses 1871system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445 # average ReadReq mshr miss latency 1872system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445 # average ReadReq mshr miss latency 1873system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427 # average WriteReq mshr miss latency 1874system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427 # average WriteReq mshr miss latency 1875system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560 # average SoftPFReq mshr miss latency 1876system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560 # average SoftPFReq mshr miss latency 1877system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012 # average WriteLineReq mshr miss latency 1878system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012 # average WriteLineReq mshr miss latency 1879system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890 # average LoadLockedReq mshr miss latency 1880system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890 # average LoadLockedReq mshr miss latency 1881system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119 # average StoreCondReq mshr miss latency 1882system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119 # average StoreCondReq mshr miss latency | 1776system.cpu1.dcache.writebacks::writebacks 5131141 # number of writebacks 1777system.cpu1.dcache.writebacks::total 5131141 # number of writebacks 1778system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17932 # number of ReadReq MSHR hits 1779system.cpu1.dcache.ReadReq_mshr_hits::total 17932 # number of ReadReq MSHR hits 1780system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 468 # number of WriteReq MSHR hits 1781system.cpu1.dcache.WriteReq_mshr_hits::total 468 # number of WriteReq MSHR hits 1782system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44381 # number of LoadLockedReq MSHR hits 1783system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44381 # number of LoadLockedReq MSHR hits 1784system.cpu1.dcache.demand_mshr_hits::cpu1.data 18400 # number of demand (read+write) MSHR hits 1785system.cpu1.dcache.demand_mshr_hits::total 18400 # number of demand (read+write) MSHR hits 1786system.cpu1.dcache.overall_mshr_hits::cpu1.data 18400 # number of overall MSHR hits 1787system.cpu1.dcache.overall_mshr_hits::total 18400 # number of overall MSHR hits 1788system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879475 # number of ReadReq MSHR misses 1789system.cpu1.dcache.ReadReq_mshr_misses::total 2879475 # number of ReadReq MSHR misses 1790system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1336298 # number of WriteReq MSHR misses 1791system.cpu1.dcache.WriteReq_mshr_misses::total 1336298 # number of WriteReq MSHR misses 1792system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634591 # number of SoftPFReq MSHR misses 1793system.cpu1.dcache.SoftPFReq_mshr_misses::total 634591 # number of SoftPFReq MSHR misses 1794system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446061 # number of WriteLineReq MSHR misses 1795system.cpu1.dcache.WriteLineReq_mshr_misses::total 446061 # number of WriteLineReq MSHR misses 1796system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126506 # number of LoadLockedReq MSHR misses 1797system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126506 # number of LoadLockedReq MSHR misses 1798system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194464 # number of StoreCondReq MSHR misses 1799system.cpu1.dcache.StoreCondReq_mshr_misses::total 194464 # number of StoreCondReq MSHR misses 1800system.cpu1.dcache.demand_mshr_misses::cpu1.data 4661834 # number of demand (read+write) MSHR misses 1801system.cpu1.dcache.demand_mshr_misses::total 4661834 # number of demand (read+write) MSHR misses 1802system.cpu1.dcache.overall_mshr_misses::cpu1.data 5296425 # number of overall MSHR misses 1803system.cpu1.dcache.overall_mshr_misses::total 5296425 # number of overall MSHR misses 1804system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable 1805system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8724 # number of ReadReq MSHR uncacheable 1806system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable 1807system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable 1808system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses 1809system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17779 # number of overall MSHR uncacheable misses 1810system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39613799000 # number of ReadReq MSHR miss cycles 1811system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39613799000 # number of ReadReq MSHR miss cycles 1812system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24222435000 # number of WriteReq MSHR miss cycles 1813system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24222435000 # number of WriteReq MSHR miss cycles 1814system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14015397000 # number of SoftPFReq MSHR miss cycles 1815system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14015397000 # number of SoftPFReq MSHR miss cycles 1816system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9175344000 # number of WriteLineReq MSHR miss cycles 1817system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9175344000 # number of WriteLineReq MSHR miss cycles 1818system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1695802000 # number of LoadLockedReq MSHR miss cycles 1819system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1695802000 # number of LoadLockedReq MSHR miss cycles 1820system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4460100500 # number of StoreCondReq MSHR miss cycles 1821system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4460100500 # number of StoreCondReq MSHR miss cycles 1822system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2195000 # number of StoreCondFailReq MSHR miss cycles 1823system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2195000 # number of StoreCondFailReq MSHR miss cycles 1824system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73011578000 # number of demand (read+write) MSHR miss cycles 1825system.cpu1.dcache.demand_mshr_miss_latency::total 73011578000 # number of demand (read+write) MSHR miss cycles 1826system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87026975000 # number of overall MSHR miss cycles 1827system.cpu1.dcache.overall_mshr_miss_latency::total 87026975000 # number of overall MSHR miss cycles 1828system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1272776000 # number of ReadReq MSHR uncacheable cycles 1829system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles 1830system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles 1831system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1272776000 # number of overall MSHR uncacheable cycles 1832system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037119 # mshr miss rate for ReadReq accesses 1833system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037119 # mshr miss rate for ReadReq accesses 1834system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018953 # mshr miss rate for WriteReq accesses 1835system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018953 # mshr miss rate for WriteReq accesses 1836system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790900 # mshr miss rate for SoftPFReq accesses 1837system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790900 # mshr miss rate for SoftPFReq accesses 1838system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879957 # mshr miss rate for WriteLineReq accesses 1839system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879957 # mshr miss rate for WriteLineReq accesses 1840system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068694 # mshr miss rate for LoadLockedReq accesses 1841system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068694 # mshr miss rate for LoadLockedReq accesses 1842system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105660 # mshr miss rate for StoreCondReq accesses 1843system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105660 # mshr miss rate for StoreCondReq accesses 1844system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031374 # mshr miss rate for demand accesses 1845system.cpu1.dcache.demand_mshr_miss_rate::total 0.031374 # mshr miss rate for demand accesses 1846system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035454 # mshr miss rate for overall accesses 1847system.cpu1.dcache.overall_mshr_miss_rate::total 0.035454 # mshr miss rate for overall accesses 1848system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13757.299160 # average ReadReq mshr miss latency 1849system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13757.299160 # average ReadReq mshr miss latency 1850system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18126.521928 # average WriteReq mshr miss latency 1851system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18126.521928 # average WriteReq mshr miss latency 1852system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22085.716627 # average SoftPFReq mshr miss latency 1853system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency 1854system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 20569.706834 # average WriteLineReq mshr miss latency 1855system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 20569.706834 # average WriteLineReq mshr miss latency 1856system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13404.913601 # average LoadLockedReq mshr miss latency 1857system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency 1858system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22935.353073 # average StoreCondReq mshr miss latency 1859system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22935.353073 # average StoreCondReq mshr miss latency |
| 1883system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1884system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1860system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1861system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1885system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671 # average overall mshr miss latency 1886system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671 # average overall mshr miss latency 1887system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662 # average overall mshr miss latency 1888system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662 # average overall mshr miss latency 1889system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041 # average ReadReq mshr uncacheable latency 1890system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041 # average ReadReq mshr uncacheable latency 1891system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915 # average overall mshr uncacheable latency 1892system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915 # average overall mshr uncacheable latency 1893system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1894system.cpu1.icache.tags.replacements 4981311 # number of replacements 1895system.cpu1.icache.tags.tagsinuse 496.212019 # Cycle average of tags in use 1896system.cpu1.icache.tags.total_refs 411158765 # Total number of references to valid blocks. 1897system.cpu1.icache.tags.sampled_refs 4981823 # Sample count of references to valid blocks. 1898system.cpu1.icache.tags.avg_refs 82.531789 # Average number of references to valid blocks. 1899system.cpu1.icache.tags.warmup_cycle 8379594860000 # Cycle when the warmup percentage was hit. 1900system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.212019 # Average occupied blocks per requestor | 1862system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15661.556804 # average overall mshr miss latency 1863system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15661.556804 # average overall mshr miss latency 1864system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16431.267317 # average overall mshr miss latency 1865system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16431.267317 # average overall mshr miss latency 1866system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145893.626777 # average ReadReq mshr uncacheable latency 1867system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 145893.626777 # average ReadReq mshr uncacheable latency 1868system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 71588.728275 # average overall mshr uncacheable latency 1869system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 71588.728275 # average overall mshr uncacheable latency 1870system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1871system.cpu1.icache.tags.replacements 5003710 # number of replacements 1872system.cpu1.icache.tags.tagsinuse 496.211749 # Cycle average of tags in use 1873system.cpu1.icache.tags.total_refs 418095086 # Total number of references to valid blocks. 1874system.cpu1.icache.tags.sampled_refs 5004222 # Sample count of references to valid blocks. 1875system.cpu1.icache.tags.avg_refs 83.548469 # Average number of references to valid blocks. 1876system.cpu1.icache.tags.warmup_cycle 8379626352000 # Cycle when the warmup percentage was hit. 1877system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.211749 # Average occupied blocks per requestor |
| 1901system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy 1902system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy 1903system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1904system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id | 1878system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy 1879system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy 1880system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1881system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id |
| 1905system.cpu1.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 1906system.cpu1.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id | 1882system.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id 1883system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id |
| 1907system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1884system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1908system.cpu1.icache.tags.tag_accesses 837263014 # Number of tag accesses 1909system.cpu1.icache.tags.data_accesses 837263014 # Number of data accesses 1910system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1911system.cpu1.icache.ReadReq_hits::cpu1.inst 411158765 # number of ReadReq hits 1912system.cpu1.icache.ReadReq_hits::total 411158765 # number of ReadReq hits 1913system.cpu1.icache.demand_hits::cpu1.inst 411158765 # number of demand (read+write) hits 1914system.cpu1.icache.demand_hits::total 411158765 # number of demand (read+write) hits 1915system.cpu1.icache.overall_hits::cpu1.inst 411158765 # number of overall hits 1916system.cpu1.icache.overall_hits::total 411158765 # number of overall hits 1917system.cpu1.icache.ReadReq_misses::cpu1.inst 4981828 # number of ReadReq misses 1918system.cpu1.icache.ReadReq_misses::total 4981828 # number of ReadReq misses 1919system.cpu1.icache.demand_misses::cpu1.inst 4981828 # number of demand (read+write) misses 1920system.cpu1.icache.demand_misses::total 4981828 # number of demand (read+write) misses 1921system.cpu1.icache.overall_misses::cpu1.inst 4981828 # number of overall misses 1922system.cpu1.icache.overall_misses::total 4981828 # number of overall misses 1923system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54111358000 # number of ReadReq miss cycles 1924system.cpu1.icache.ReadReq_miss_latency::total 54111358000 # number of ReadReq miss cycles 1925system.cpu1.icache.demand_miss_latency::cpu1.inst 54111358000 # number of demand (read+write) miss cycles 1926system.cpu1.icache.demand_miss_latency::total 54111358000 # number of demand (read+write) miss cycles 1927system.cpu1.icache.overall_miss_latency::cpu1.inst 54111358000 # number of overall miss cycles 1928system.cpu1.icache.overall_miss_latency::total 54111358000 # number of overall miss cycles 1929system.cpu1.icache.ReadReq_accesses::cpu1.inst 416140593 # number of ReadReq accesses(hits+misses) 1930system.cpu1.icache.ReadReq_accesses::total 416140593 # number of ReadReq accesses(hits+misses) 1931system.cpu1.icache.demand_accesses::cpu1.inst 416140593 # number of demand (read+write) accesses 1932system.cpu1.icache.demand_accesses::total 416140593 # number of demand (read+write) accesses 1933system.cpu1.icache.overall_accesses::cpu1.inst 416140593 # number of overall (read+write) accesses 1934system.cpu1.icache.overall_accesses::total 416140593 # number of overall (read+write) accesses 1935system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011972 # miss rate for ReadReq accesses 1936system.cpu1.icache.ReadReq_miss_rate::total 0.011972 # miss rate for ReadReq accesses 1937system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011972 # miss rate for demand accesses 1938system.cpu1.icache.demand_miss_rate::total 0.011972 # miss rate for demand accesses 1939system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011972 # miss rate for overall accesses 1940system.cpu1.icache.overall_miss_rate::total 0.011972 # miss rate for overall accesses 1941system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10861.747535 # average ReadReq miss latency 1942system.cpu1.icache.ReadReq_avg_miss_latency::total 10861.747535 # average ReadReq miss latency 1943system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency 1944system.cpu1.icache.demand_avg_miss_latency::total 10861.747535 # average overall miss latency 1945system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency 1946system.cpu1.icache.overall_avg_miss_latency::total 10861.747535 # average overall miss latency | 1885system.cpu1.icache.tags.tag_accesses 851202853 # Number of tag accesses 1886system.cpu1.icache.tags.data_accesses 851202853 # Number of data accesses 1887system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1888system.cpu1.icache.ReadReq_hits::cpu1.inst 418095086 # number of ReadReq hits 1889system.cpu1.icache.ReadReq_hits::total 418095086 # number of ReadReq hits 1890system.cpu1.icache.demand_hits::cpu1.inst 418095086 # number of demand (read+write) hits 1891system.cpu1.icache.demand_hits::total 418095086 # number of demand (read+write) hits 1892system.cpu1.icache.overall_hits::cpu1.inst 418095086 # number of overall hits 1893system.cpu1.icache.overall_hits::total 418095086 # number of overall hits 1894system.cpu1.icache.ReadReq_misses::cpu1.inst 5004227 # number of ReadReq misses 1895system.cpu1.icache.ReadReq_misses::total 5004227 # number of ReadReq misses 1896system.cpu1.icache.demand_misses::cpu1.inst 5004227 # number of demand (read+write) misses 1897system.cpu1.icache.demand_misses::total 5004227 # number of demand (read+write) misses 1898system.cpu1.icache.overall_misses::cpu1.inst 5004227 # number of overall misses 1899system.cpu1.icache.overall_misses::total 5004227 # number of overall misses 1900system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54129933000 # number of ReadReq miss cycles 1901system.cpu1.icache.ReadReq_miss_latency::total 54129933000 # number of ReadReq miss cycles 1902system.cpu1.icache.demand_miss_latency::cpu1.inst 54129933000 # number of demand (read+write) miss cycles 1903system.cpu1.icache.demand_miss_latency::total 54129933000 # number of demand (read+write) miss cycles 1904system.cpu1.icache.overall_miss_latency::cpu1.inst 54129933000 # number of overall miss cycles 1905system.cpu1.icache.overall_miss_latency::total 54129933000 # number of overall miss cycles 1906system.cpu1.icache.ReadReq_accesses::cpu1.inst 423099313 # number of ReadReq accesses(hits+misses) 1907system.cpu1.icache.ReadReq_accesses::total 423099313 # number of ReadReq accesses(hits+misses) 1908system.cpu1.icache.demand_accesses::cpu1.inst 423099313 # number of demand (read+write) accesses 1909system.cpu1.icache.demand_accesses::total 423099313 # number of demand (read+write) accesses 1910system.cpu1.icache.overall_accesses::cpu1.inst 423099313 # number of overall (read+write) accesses 1911system.cpu1.icache.overall_accesses::total 423099313 # number of overall (read+write) accesses 1912system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011828 # miss rate for ReadReq accesses 1913system.cpu1.icache.ReadReq_miss_rate::total 0.011828 # miss rate for ReadReq accesses 1914system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011828 # miss rate for demand accesses 1915system.cpu1.icache.demand_miss_rate::total 0.011828 # miss rate for demand accesses 1916system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011828 # miss rate for overall accesses 1917system.cpu1.icache.overall_miss_rate::total 0.011828 # miss rate for overall accesses 1918system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10816.842042 # average ReadReq miss latency 1919system.cpu1.icache.ReadReq_avg_miss_latency::total 10816.842042 # average ReadReq miss latency 1920system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency 1921system.cpu1.icache.demand_avg_miss_latency::total 10816.842042 # average overall miss latency 1922system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency 1923system.cpu1.icache.overall_avg_miss_latency::total 10816.842042 # average overall miss latency |
| 1947system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1948system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1949system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1950system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1951system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1952system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1924system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1925system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1926system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1927system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1928system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1929system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1953system.cpu1.icache.writebacks::writebacks 4981311 # number of writebacks 1954system.cpu1.icache.writebacks::total 4981311 # number of writebacks 1955system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4981828 # number of ReadReq MSHR misses 1956system.cpu1.icache.ReadReq_mshr_misses::total 4981828 # number of ReadReq MSHR misses 1957system.cpu1.icache.demand_mshr_misses::cpu1.inst 4981828 # number of demand (read+write) MSHR misses 1958system.cpu1.icache.demand_mshr_misses::total 4981828 # number of demand (read+write) MSHR misses 1959system.cpu1.icache.overall_mshr_misses::cpu1.inst 4981828 # number of overall MSHR misses 1960system.cpu1.icache.overall_mshr_misses::total 4981828 # number of overall MSHR misses | 1930system.cpu1.icache.writebacks::writebacks 5003710 # number of writebacks 1931system.cpu1.icache.writebacks::total 5003710 # number of writebacks 1932system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5004227 # number of ReadReq MSHR misses 1933system.cpu1.icache.ReadReq_mshr_misses::total 5004227 # number of ReadReq MSHR misses 1934system.cpu1.icache.demand_mshr_misses::cpu1.inst 5004227 # number of demand (read+write) MSHR misses 1935system.cpu1.icache.demand_mshr_misses::total 5004227 # number of demand (read+write) MSHR misses 1936system.cpu1.icache.overall_mshr_misses::cpu1.inst 5004227 # number of overall MSHR misses 1937system.cpu1.icache.overall_mshr_misses::total 5004227 # number of overall MSHR misses |
| 1961system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1962system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1963system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1964system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses | 1938system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1939system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1940system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1941system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses |
| 1965system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51620444000 # number of ReadReq MSHR miss cycles 1966system.cpu1.icache.ReadReq_mshr_miss_latency::total 51620444000 # number of ReadReq MSHR miss cycles 1967system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51620444000 # number of demand (read+write) MSHR miss cycles 1968system.cpu1.icache.demand_mshr_miss_latency::total 51620444000 # number of demand (read+write) MSHR miss cycles 1969system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51620444000 # number of overall MSHR miss cycles 1970system.cpu1.icache.overall_mshr_miss_latency::total 51620444000 # number of overall MSHR miss cycles 1971system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10472000 # number of ReadReq MSHR uncacheable cycles 1972system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10472000 # number of ReadReq MSHR uncacheable cycles 1973system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10472000 # number of overall MSHR uncacheable cycles 1974system.cpu1.icache.overall_mshr_uncacheable_latency::total 10472000 # number of overall MSHR uncacheable cycles 1975system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for ReadReq accesses 1976system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011972 # mshr miss rate for ReadReq accesses 1977system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for demand accesses 1978system.cpu1.icache.demand_mshr_miss_rate::total 0.011972 # mshr miss rate for demand accesses 1979system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for overall accesses 1980system.cpu1.icache.overall_mshr_miss_rate::total 0.011972 # mshr miss rate for overall accesses 1981system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average ReadReq mshr miss latency 1982system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10361.747535 # average ReadReq mshr miss latency 1983system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency 1984system.cpu1.icache.demand_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency 1985system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency 1986system.cpu1.icache.overall_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency 1987system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average ReadReq mshr uncacheable latency 1988system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95200 # average ReadReq mshr uncacheable latency 1989system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average overall mshr uncacheable latency 1990system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95200 # average overall mshr uncacheable latency 1991system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1992system.cpu1.l2cache.prefetcher.num_hwpf_issued 6872416 # number of hwpf issued 1993system.cpu1.l2cache.prefetcher.pfIdentified 6872436 # number of prefetch candidates identified 1994system.cpu1.l2cache.prefetcher.pfBufferHit 18 # number of redundant prefetches already in prefetch queue | 1942system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51627819500 # number of ReadReq MSHR miss cycles 1943system.cpu1.icache.ReadReq_mshr_miss_latency::total 51627819500 # number of ReadReq MSHR miss cycles 1944system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51627819500 # number of demand (read+write) MSHR miss cycles 1945system.cpu1.icache.demand_mshr_miss_latency::total 51627819500 # number of demand (read+write) MSHR miss cycles 1946system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51627819500 # number of overall MSHR miss cycles 1947system.cpu1.icache.overall_mshr_miss_latency::total 51627819500 # number of overall MSHR miss cycles 1948system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917500 # number of ReadReq MSHR uncacheable cycles 1949system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10917500 # number of ReadReq MSHR uncacheable cycles 1950system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10917500 # number of overall MSHR uncacheable cycles 1951system.cpu1.icache.overall_mshr_uncacheable_latency::total 10917500 # number of overall MSHR uncacheable cycles 1952system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for ReadReq accesses 1953system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011828 # mshr miss rate for ReadReq accesses 1954system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for demand accesses 1955system.cpu1.icache.demand_mshr_miss_rate::total 0.011828 # mshr miss rate for demand accesses 1956system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for overall accesses 1957system.cpu1.icache.overall_mshr_miss_rate::total 0.011828 # mshr miss rate for overall accesses 1958system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average ReadReq mshr miss latency 1959system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10316.842042 # average ReadReq mshr miss latency 1960system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency 1961system.cpu1.icache.demand_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency 1962system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency 1963system.cpu1.icache.overall_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency 1964system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average ReadReq mshr uncacheable latency 1965system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99250 # average ReadReq mshr uncacheable latency 1966system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average overall mshr uncacheable latency 1967system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99250 # average overall mshr uncacheable latency 1968system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1969system.cpu1.l2cache.prefetcher.num_hwpf_issued 7173608 # number of hwpf issued 1970system.cpu1.l2cache.prefetcher.pfIdentified 7173625 # number of prefetch candidates identified 1971system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue |
| 1995system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1996system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1972system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1973system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1997system.cpu1.l2cache.prefetcher.pfSpanPage 852028 # number of prefetches not generated due to page crossing 1998system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1999system.cpu1.l2cache.tags.replacements 1861043 # number of replacements 2000system.cpu1.l2cache.tags.tagsinuse 12976.163549 # Cycle average of tags in use 2001system.cpu1.l2cache.tags.total_refs 8767962 # Total number of references to valid blocks. 2002system.cpu1.l2cache.tags.sampled_refs 1876890 # Sample count of references to valid blocks. 2003system.cpu1.l2cache.tags.avg_refs 4.671537 # Average number of references to valid blocks. | 1974system.cpu1.l2cache.prefetcher.pfSpanPage 895743 # number of prefetches not generated due to page crossing 1975system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 1976system.cpu1.l2cache.tags.replacements 1888854 # number of replacements 1977system.cpu1.l2cache.tags.tagsinuse 13151.739114 # Cycle average of tags in use 1978system.cpu1.l2cache.tags.total_refs 8987368 # Total number of references to valid blocks. 1979system.cpu1.l2cache.tags.sampled_refs 1904692 # Sample count of references to valid blocks. 1980system.cpu1.l2cache.tags.avg_refs 4.718541 # Average number of references to valid blocks. |
| 2004system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1981system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2005system.cpu1.l2cache.tags.occ_blocks::writebacks 12709.863020 # Average occupied blocks per requestor 2006system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.854479 # Average occupied blocks per requestor 2007system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 23.050365 # Average occupied blocks per requestor 2008system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 215.395684 # Average occupied blocks per requestor 2009system.cpu1.l2cache.tags.occ_percent::writebacks 0.775748 # Average percentage of cache occupancy 2010system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001700 # Average percentage of cache occupancy 2011system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001407 # Average percentage of cache occupancy 2012system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013147 # Average percentage of cache occupancy 2013system.cpu1.l2cache.tags.occ_percent::total 0.792002 # Average percentage of cache occupancy 2014system.cpu1.l2cache.tags.occ_task_id_blocks::1022 377 # Occupied blocks per task id 2015system.cpu1.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id 2016system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15415 # Occupied blocks per task id 2017system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 2018system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id 2019system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 69 # Occupied blocks per task id 2020system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 165 # Occupied blocks per task id 2021system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id 2022system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 2023system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 2024system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 2025system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1400 # Occupied blocks per task id 2026system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5858 # Occupied blocks per task id 2027system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4122 # Occupied blocks per task id 2028system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3918 # Occupied blocks per task id 2029system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.023010 # Percentage of cache occupancy per task id 2030system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id 2031system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940857 # Percentage of cache occupancy per task id 2032system.cpu1.l2cache.tags.tag_accesses 342605185 # Number of tag accesses 2033system.cpu1.l2cache.tags.data_accesses 342605185 # Number of data accesses 2034system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2035system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 220532 # number of ReadReq hits 2036system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 147847 # number of ReadReq hits 2037system.cpu1.l2cache.ReadReq_hits::total 368379 # number of ReadReq hits 2038system.cpu1.l2cache.WritebackDirty_hits::writebacks 3122709 # number of WritebackDirty hits 2039system.cpu1.l2cache.WritebackDirty_hits::total 3122709 # number of WritebackDirty hits 2040system.cpu1.l2cache.WritebackClean_hits::writebacks 6807120 # number of WritebackClean hits 2041system.cpu1.l2cache.WritebackClean_hits::total 6807120 # number of WritebackClean hits 2042system.cpu1.l2cache.ReadExReq_hits::cpu1.data 835381 # number of ReadExReq hits 2043system.cpu1.l2cache.ReadExReq_hits::total 835381 # number of ReadExReq hits 2044system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4529100 # number of ReadCleanReq hits 2045system.cpu1.l2cache.ReadCleanReq_hits::total 4529100 # number of ReadCleanReq hits 2046system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2623579 # number of ReadSharedReq hits 2047system.cpu1.l2cache.ReadSharedReq_hits::total 2623579 # number of ReadSharedReq hits 2048system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191618 # number of InvalidateReq hits 2049system.cpu1.l2cache.InvalidateReq_hits::total 191618 # number of InvalidateReq hits 2050system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 220532 # number of demand (read+write) hits 2051system.cpu1.l2cache.demand_hits::cpu1.itb.walker 147847 # number of demand (read+write) hits 2052system.cpu1.l2cache.demand_hits::cpu1.inst 4529100 # number of demand (read+write) hits 2053system.cpu1.l2cache.demand_hits::cpu1.data 3458960 # number of demand (read+write) hits 2054system.cpu1.l2cache.demand_hits::total 8356439 # number of demand (read+write) hits 2055system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 220532 # number of overall hits 2056system.cpu1.l2cache.overall_hits::cpu1.itb.walker 147847 # number of overall hits 2057system.cpu1.l2cache.overall_hits::cpu1.inst 4529100 # number of overall hits 2058system.cpu1.l2cache.overall_hits::cpu1.data 3458960 # number of overall hits 2059system.cpu1.l2cache.overall_hits::total 8356439 # number of overall hits 2060system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 17957 # number of ReadReq misses 2061system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10279 # number of ReadReq misses 2062system.cpu1.l2cache.ReadReq_misses::total 28236 # number of ReadReq misses 2063system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208369 # number of UpgradeReq misses 2064system.cpu1.l2cache.UpgradeReq_misses::total 208369 # number of UpgradeReq misses 2065system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202239 # number of SCUpgradeReq misses 2066system.cpu1.l2cache.SCUpgradeReq_misses::total 202239 # number of SCUpgradeReq misses 2067system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 2068system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2069system.cpu1.l2cache.ReadExReq_misses::cpu1.data 250965 # number of ReadExReq misses 2070system.cpu1.l2cache.ReadExReq_misses::total 250965 # number of ReadExReq misses 2071system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 452728 # number of ReadCleanReq misses 2072system.cpu1.l2cache.ReadCleanReq_misses::total 452728 # number of ReadCleanReq misses 2073system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 889177 # number of ReadSharedReq misses 2074system.cpu1.l2cache.ReadSharedReq_misses::total 889177 # number of ReadSharedReq misses 2075system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 249433 # number of InvalidateReq misses 2076system.cpu1.l2cache.InvalidateReq_misses::total 249433 # number of InvalidateReq misses 2077system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 17957 # number of demand (read+write) misses 2078system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10279 # number of demand (read+write) misses 2079system.cpu1.l2cache.demand_misses::cpu1.inst 452728 # number of demand (read+write) misses 2080system.cpu1.l2cache.demand_misses::cpu1.data 1140142 # number of demand (read+write) misses 2081system.cpu1.l2cache.demand_misses::total 1621106 # number of demand (read+write) misses 2082system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 17957 # number of overall misses 2083system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10279 # number of overall misses 2084system.cpu1.l2cache.overall_misses::cpu1.inst 452728 # number of overall misses 2085system.cpu1.l2cache.overall_misses::cpu1.data 1140142 # number of overall misses 2086system.cpu1.l2cache.overall_misses::total 1621106 # number of overall misses 2087system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 590137500 # number of ReadReq miss cycles 2088system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 422641500 # number of ReadReq miss cycles 2089system.cpu1.l2cache.ReadReq_miss_latency::total 1012779000 # number of ReadReq miss cycles 2090system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 875652500 # number of UpgradeReq miss cycles 2091system.cpu1.l2cache.UpgradeReq_miss_latency::total 875652500 # number of UpgradeReq miss cycles 2092system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 333590500 # number of SCUpgradeReq miss cycles 2093system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 333590500 # number of SCUpgradeReq miss cycles 2094system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2035999 # number of SCUpgradeFailReq miss cycles 2095system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2035999 # number of SCUpgradeFailReq miss cycles 2096system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11238175000 # number of ReadExReq miss cycles 2097system.cpu1.l2cache.ReadExReq_miss_latency::total 11238175000 # number of ReadExReq miss cycles 2098system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16933068500 # number of ReadCleanReq miss cycles 2099system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16933068500 # number of ReadCleanReq miss cycles 2100system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31773824000 # number of ReadSharedReq miss cycles 2101system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31773824000 # number of ReadSharedReq miss cycles 2102system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 403814500 # number of InvalidateReq miss cycles 2103system.cpu1.l2cache.InvalidateReq_miss_latency::total 403814500 # number of InvalidateReq miss cycles 2104system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 590137500 # number of demand (read+write) miss cycles 2105system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 422641500 # number of demand (read+write) miss cycles 2106system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16933068500 # number of demand (read+write) miss cycles 2107system.cpu1.l2cache.demand_miss_latency::cpu1.data 43011999000 # number of demand (read+write) miss cycles 2108system.cpu1.l2cache.demand_miss_latency::total 60957846500 # number of demand (read+write) miss cycles 2109system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 590137500 # number of overall miss cycles 2110system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 422641500 # number of overall miss cycles 2111system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16933068500 # number of overall miss cycles 2112system.cpu1.l2cache.overall_miss_latency::cpu1.data 43011999000 # number of overall miss cycles 2113system.cpu1.l2cache.overall_miss_latency::total 60957846500 # number of overall miss cycles 2114system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 238489 # number of ReadReq accesses(hits+misses) 2115system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 158126 # number of ReadReq accesses(hits+misses) 2116system.cpu1.l2cache.ReadReq_accesses::total 396615 # number of ReadReq accesses(hits+misses) 2117system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3122709 # number of WritebackDirty accesses(hits+misses) 2118system.cpu1.l2cache.WritebackDirty_accesses::total 3122709 # number of WritebackDirty accesses(hits+misses) 2119system.cpu1.l2cache.WritebackClean_accesses::writebacks 6807120 # number of WritebackClean accesses(hits+misses) 2120system.cpu1.l2cache.WritebackClean_accesses::total 6807120 # number of WritebackClean accesses(hits+misses) 2121system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208369 # number of UpgradeReq accesses(hits+misses) 2122system.cpu1.l2cache.UpgradeReq_accesses::total 208369 # number of UpgradeReq accesses(hits+misses) 2123system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202239 # number of SCUpgradeReq accesses(hits+misses) 2124system.cpu1.l2cache.SCUpgradeReq_accesses::total 202239 # number of SCUpgradeReq accesses(hits+misses) 2125system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 2126system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2127system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1086346 # number of ReadExReq accesses(hits+misses) 2128system.cpu1.l2cache.ReadExReq_accesses::total 1086346 # number of ReadExReq accesses(hits+misses) 2129system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4981828 # number of ReadCleanReq accesses(hits+misses) 2130system.cpu1.l2cache.ReadCleanReq_accesses::total 4981828 # number of ReadCleanReq accesses(hits+misses) 2131system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3512756 # number of ReadSharedReq accesses(hits+misses) 2132system.cpu1.l2cache.ReadSharedReq_accesses::total 3512756 # number of ReadSharedReq accesses(hits+misses) 2133system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 441051 # number of InvalidateReq accesses(hits+misses) 2134system.cpu1.l2cache.InvalidateReq_accesses::total 441051 # number of InvalidateReq accesses(hits+misses) 2135system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 238489 # number of demand (read+write) accesses 2136system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 158126 # number of demand (read+write) accesses 2137system.cpu1.l2cache.demand_accesses::cpu1.inst 4981828 # number of demand (read+write) accesses 2138system.cpu1.l2cache.demand_accesses::cpu1.data 4599102 # number of demand (read+write) accesses 2139system.cpu1.l2cache.demand_accesses::total 9977545 # number of demand (read+write) accesses 2140system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 238489 # number of overall (read+write) accesses 2141system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 158126 # number of overall (read+write) accesses 2142system.cpu1.l2cache.overall_accesses::cpu1.inst 4981828 # number of overall (read+write) accesses 2143system.cpu1.l2cache.overall_accesses::cpu1.data 4599102 # number of overall (read+write) accesses 2144system.cpu1.l2cache.overall_accesses::total 9977545 # number of overall (read+write) accesses 2145system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for ReadReq accesses 2146system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065005 # miss rate for ReadReq accesses 2147system.cpu1.l2cache.ReadReq_miss_rate::total 0.071192 # miss rate for ReadReq accesses | 1982system.cpu1.l2cache.tags.occ_blocks::writebacks 12880.289345 # Average occupied blocks per requestor 1983system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.911148 # Average occupied blocks per requestor 1984system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 9.232940 # Average occupied blocks per requestor 1985system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 244.305681 # Average occupied blocks per requestor 1986system.cpu1.l2cache.tags.occ_percent::writebacks 0.786150 # Average percentage of cache occupancy 1987system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001093 # Average percentage of cache occupancy 1988system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000564 # Average percentage of cache occupancy 1989system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014911 # Average percentage of cache occupancy 1990system.cpu1.l2cache.tags.occ_percent::total 0.802718 # Average percentage of cache occupancy 1991system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id 1992system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id 1993system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id 1994system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 1995system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id 1996system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id 1997system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 70 # Occupied blocks per task id 1998system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1999system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 46 # Occupied blocks per task id 2000system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 2001system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 2002system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 2003system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1447 # Occupied blocks per task id 2004system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5487 # Occupied blocks per task id 2005system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7313 # Occupied blocks per task id 2006system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1113 # Occupied blocks per task id 2007system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id 2008system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id 2009system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id 2010system.cpu1.l2cache.tags.tag_accesses 349452832 # Number of tag accesses 2011system.cpu1.l2cache.tags.data_accesses 349452832 # Number of data accesses 2012system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 2013system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 234483 # number of ReadReq hits 2014system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153773 # number of ReadReq hits 2015system.cpu1.l2cache.ReadReq_hits::total 388256 # number of ReadReq hits 2016system.cpu1.l2cache.WritebackDirty_hits::writebacks 3241183 # number of WritebackDirty hits 2017system.cpu1.l2cache.WritebackDirty_hits::total 3241183 # number of WritebackDirty hits 2018system.cpu1.l2cache.WritebackClean_hits::writebacks 6893065 # number of WritebackClean hits 2019system.cpu1.l2cache.WritebackClean_hits::total 6893065 # number of WritebackClean hits 2020system.cpu1.l2cache.ReadExReq_hits::cpu1.data 876408 # number of ReadExReq hits 2021system.cpu1.l2cache.ReadExReq_hits::total 876408 # number of ReadExReq hits 2022system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4540376 # number of ReadCleanReq hits 2023system.cpu1.l2cache.ReadCleanReq_hits::total 4540376 # number of ReadCleanReq hits 2024system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2756982 # number of ReadSharedReq hits 2025system.cpu1.l2cache.ReadSharedReq_hits::total 2756982 # number of ReadSharedReq hits 2026system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 197607 # number of InvalidateReq hits 2027system.cpu1.l2cache.InvalidateReq_hits::total 197607 # number of InvalidateReq hits 2028system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 234483 # number of demand (read+write) hits 2029system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153773 # number of demand (read+write) hits 2030system.cpu1.l2cache.demand_hits::cpu1.inst 4540376 # number of demand (read+write) hits 2031system.cpu1.l2cache.demand_hits::cpu1.data 3633390 # number of demand (read+write) hits 2032system.cpu1.l2cache.demand_hits::total 8562022 # number of demand (read+write) hits 2033system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 234483 # number of overall hits 2034system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153773 # number of overall hits 2035system.cpu1.l2cache.overall_hits::cpu1.inst 4540376 # number of overall hits 2036system.cpu1.l2cache.overall_hits::cpu1.data 3633390 # number of overall hits 2037system.cpu1.l2cache.overall_hits::total 8562022 # number of overall hits 2038system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18869 # number of ReadReq misses 2039system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10447 # number of ReadReq misses 2040system.cpu1.l2cache.ReadReq_misses::total 29316 # number of ReadReq misses 2041system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206667 # number of UpgradeReq misses 2042system.cpu1.l2cache.UpgradeReq_misses::total 206667 # number of UpgradeReq misses 2043system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194457 # number of SCUpgradeReq misses 2044system.cpu1.l2cache.SCUpgradeReq_misses::total 194457 # number of SCUpgradeReq misses 2045system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses 2046system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 2047system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253441 # number of ReadExReq misses 2048system.cpu1.l2cache.ReadExReq_misses::total 253441 # number of ReadExReq misses 2049system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463851 # number of ReadCleanReq misses 2050system.cpu1.l2cache.ReadCleanReq_misses::total 463851 # number of ReadCleanReq misses 2051system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 883590 # number of ReadSharedReq misses 2052system.cpu1.l2cache.ReadSharedReq_misses::total 883590 # number of ReadSharedReq misses 2053system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 248454 # number of InvalidateReq misses 2054system.cpu1.l2cache.InvalidateReq_misses::total 248454 # number of InvalidateReq misses 2055system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18869 # number of demand (read+write) misses 2056system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10447 # number of demand (read+write) misses 2057system.cpu1.l2cache.demand_misses::cpu1.inst 463851 # number of demand (read+write) misses 2058system.cpu1.l2cache.demand_misses::cpu1.data 1137031 # number of demand (read+write) misses 2059system.cpu1.l2cache.demand_misses::total 1630198 # number of demand (read+write) misses 2060system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18869 # number of overall misses 2061system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10447 # number of overall misses 2062system.cpu1.l2cache.overall_misses::cpu1.inst 463851 # number of overall misses 2063system.cpu1.l2cache.overall_misses::cpu1.data 1137031 # number of overall misses 2064system.cpu1.l2cache.overall_misses::total 1630198 # number of overall misses 2065system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 633582000 # number of ReadReq miss cycles 2066system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 432596500 # number of ReadReq miss cycles 2067system.cpu1.l2cache.ReadReq_miss_latency::total 1066178500 # number of ReadReq miss cycles 2068system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 941410000 # number of UpgradeReq miss cycles 2069system.cpu1.l2cache.UpgradeReq_miss_latency::total 941410000 # number of UpgradeReq miss cycles 2070system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 356938000 # number of SCUpgradeReq miss cycles 2071system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 356938000 # number of SCUpgradeReq miss cycles 2072system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2118500 # number of SCUpgradeFailReq miss cycles 2073system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2118500 # number of SCUpgradeFailReq miss cycles 2074system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11335810999 # number of ReadExReq miss cycles 2075system.cpu1.l2cache.ReadExReq_miss_latency::total 11335810999 # number of ReadExReq miss cycles 2076system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16839909000 # number of ReadCleanReq miss cycles 2077system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16839909000 # number of ReadCleanReq miss cycles 2078system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31901147000 # number of ReadSharedReq miss cycles 2079system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31901147000 # number of ReadSharedReq miss cycles 2080system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 63500 # number of InvalidateReq miss cycles 2081system.cpu1.l2cache.InvalidateReq_miss_latency::total 63500 # number of InvalidateReq miss cycles 2082system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 633582000 # number of demand (read+write) miss cycles 2083system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 432596500 # number of demand (read+write) miss cycles 2084system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16839909000 # number of demand (read+write) miss cycles 2085system.cpu1.l2cache.demand_miss_latency::cpu1.data 43236957999 # number of demand (read+write) miss cycles 2086system.cpu1.l2cache.demand_miss_latency::total 61143045499 # number of demand (read+write) miss cycles 2087system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 633582000 # number of overall miss cycles 2088system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 432596500 # number of overall miss cycles 2089system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16839909000 # number of overall miss cycles 2090system.cpu1.l2cache.overall_miss_latency::cpu1.data 43236957999 # number of overall miss cycles 2091system.cpu1.l2cache.overall_miss_latency::total 61143045499 # number of overall miss cycles 2092system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 253352 # number of ReadReq accesses(hits+misses) 2093system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164220 # number of ReadReq accesses(hits+misses) 2094system.cpu1.l2cache.ReadReq_accesses::total 417572 # number of ReadReq accesses(hits+misses) 2095system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3241183 # number of WritebackDirty accesses(hits+misses) 2096system.cpu1.l2cache.WritebackDirty_accesses::total 3241183 # number of WritebackDirty accesses(hits+misses) 2097system.cpu1.l2cache.WritebackClean_accesses::writebacks 6893065 # number of WritebackClean accesses(hits+misses) 2098system.cpu1.l2cache.WritebackClean_accesses::total 6893065 # number of WritebackClean accesses(hits+misses) 2099system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206667 # number of UpgradeReq accesses(hits+misses) 2100system.cpu1.l2cache.UpgradeReq_accesses::total 206667 # number of UpgradeReq accesses(hits+misses) 2101system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194457 # number of SCUpgradeReq accesses(hits+misses) 2102system.cpu1.l2cache.SCUpgradeReq_accesses::total 194457 # number of SCUpgradeReq accesses(hits+misses) 2103system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 2104system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 2105system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1129849 # number of ReadExReq accesses(hits+misses) 2106system.cpu1.l2cache.ReadExReq_accesses::total 1129849 # number of ReadExReq accesses(hits+misses) 2107system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5004227 # number of ReadCleanReq accesses(hits+misses) 2108system.cpu1.l2cache.ReadCleanReq_accesses::total 5004227 # number of ReadCleanReq accesses(hits+misses) 2109system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3640572 # number of ReadSharedReq accesses(hits+misses) 2110system.cpu1.l2cache.ReadSharedReq_accesses::total 3640572 # number of ReadSharedReq accesses(hits+misses) 2111system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 446061 # number of InvalidateReq accesses(hits+misses) 2112system.cpu1.l2cache.InvalidateReq_accesses::total 446061 # number of InvalidateReq accesses(hits+misses) 2113system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 253352 # number of demand (read+write) accesses 2114system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164220 # number of demand (read+write) accesses 2115system.cpu1.l2cache.demand_accesses::cpu1.inst 5004227 # number of demand (read+write) accesses 2116system.cpu1.l2cache.demand_accesses::cpu1.data 4770421 # number of demand (read+write) accesses 2117system.cpu1.l2cache.demand_accesses::total 10192220 # number of demand (read+write) accesses 2118system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 253352 # number of overall (read+write) accesses 2119system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164220 # number of overall (read+write) accesses 2120system.cpu1.l2cache.overall_accesses::cpu1.inst 5004227 # number of overall (read+write) accesses 2121system.cpu1.l2cache.overall_accesses::cpu1.data 4770421 # number of overall (read+write) accesses 2122system.cpu1.l2cache.overall_accesses::total 10192220 # number of overall (read+write) accesses 2123system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for ReadReq accesses 2124system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063616 # miss rate for ReadReq accesses 2125system.cpu1.l2cache.ReadReq_miss_rate::total 0.070206 # miss rate for ReadReq accesses |
| 2148system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2149system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2150system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2151system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2152system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2153system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2126system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2127system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2128system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2129system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2130system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2131system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2154system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231018 # miss rate for ReadExReq accesses 2155system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231018 # miss rate for ReadExReq accesses 2156system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.090876 # miss rate for ReadCleanReq accesses 2157system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.090876 # miss rate for ReadCleanReq accesses 2158system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253128 # miss rate for ReadSharedReq accesses 2159system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253128 # miss rate for ReadSharedReq accesses 2160system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.565542 # miss rate for InvalidateReq accesses 2161system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.565542 # miss rate for InvalidateReq accesses 2162system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for demand accesses 2163system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065005 # miss rate for demand accesses 2164system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.090876 # miss rate for demand accesses 2165system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.247905 # miss rate for demand accesses 2166system.cpu1.l2cache.demand_miss_rate::total 0.162475 # miss rate for demand accesses 2167system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for overall accesses 2168system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065005 # miss rate for overall accesses 2169system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.090876 # miss rate for overall accesses 2170system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.247905 # miss rate for overall accesses 2171system.cpu1.l2cache.overall_miss_rate::total 0.162475 # miss rate for overall accesses 2172system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average ReadReq miss latency 2173system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41116.986088 # average ReadReq miss latency 2174system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35868.359541 # average ReadReq miss latency 2175system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4202.412547 # average UpgradeReq miss latency 2176system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4202.412547 # average UpgradeReq miss latency 2177system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1649.486499 # average SCUpgradeReq miss latency 2178system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1649.486499 # average SCUpgradeReq miss latency 2179system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678666.333333 # average SCUpgradeFailReq miss latency 2180system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678666.333333 # average SCUpgradeFailReq miss latency 2181system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44779.849780 # average ReadExReq miss latency 2182system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44779.849780 # average ReadExReq miss latency 2183system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37402.300057 # average ReadCleanReq miss latency 2184system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37402.300057 # average ReadCleanReq miss latency 2185system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35733.969727 # average ReadSharedReq miss latency 2186system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35733.969727 # average ReadSharedReq miss latency 2187system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1618.929733 # average InvalidateReq miss latency 2188system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1618.929733 # average InvalidateReq miss latency 2189system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average overall miss latency 2190system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41116.986088 # average overall miss latency 2191system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37402.300057 # average overall miss latency 2192system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37725.124590 # average overall miss latency 2193system.cpu1.l2cache.demand_avg_miss_latency::total 37602.628391 # average overall miss latency 2194system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average overall miss latency 2195system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41116.986088 # average overall miss latency 2196system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37402.300057 # average overall miss latency 2197system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37725.124590 # average overall miss latency 2198system.cpu1.l2cache.overall_avg_miss_latency::total 37602.628391 # average overall miss latency | 2132system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224314 # miss rate for ReadExReq accesses 2133system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224314 # miss rate for ReadExReq accesses 2134system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092692 # miss rate for ReadCleanReq accesses 2135system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092692 # miss rate for ReadCleanReq accesses 2136system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242706 # miss rate for ReadSharedReq accesses 2137system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242706 # miss rate for ReadSharedReq accesses 2138system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.556996 # miss rate for InvalidateReq accesses 2139system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.556996 # miss rate for InvalidateReq accesses 2140system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for demand accesses 2141system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063616 # miss rate for demand accesses 2142system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092692 # miss rate for demand accesses 2143system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238350 # miss rate for demand accesses 2144system.cpu1.l2cache.demand_miss_rate::total 0.159945 # miss rate for demand accesses 2145system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for overall accesses 2146system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063616 # miss rate for overall accesses 2147system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092692 # miss rate for overall accesses 2148system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238350 # miss rate for overall accesses 2149system.cpu1.l2cache.overall_miss_rate::total 0.159945 # miss rate for overall accesses 2150system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average ReadReq miss latency 2151system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41408.681918 # average ReadReq miss latency 2152system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36368.484786 # average ReadReq miss latency 2153system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4555.202330 # average UpgradeReq miss latency 2154system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4555.202330 # average UpgradeReq miss latency 2155system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1835.562618 # average SCUpgradeReq miss latency 2156system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1835.562618 # average SCUpgradeReq miss latency 2157system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 302642.857143 # average SCUpgradeFailReq miss latency 2158system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 302642.857143 # average SCUpgradeFailReq miss latency 2159system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44727.613129 # average ReadExReq miss latency 2160system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44727.613129 # average ReadExReq miss latency 2161system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36304.565475 # average ReadCleanReq miss latency 2162system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36304.565475 # average ReadCleanReq miss latency 2163system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36104.015437 # average ReadSharedReq miss latency 2164system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36104.015437 # average ReadSharedReq miss latency 2165system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.255581 # average InvalidateReq miss latency 2166system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.255581 # average InvalidateReq miss latency 2167system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency 2168system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency 2169system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency 2170system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency 2171system.cpu1.l2cache.demand_avg_miss_latency::total 37506.514852 # average overall miss latency 2172system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency 2173system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency 2174system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency 2175system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency 2176system.cpu1.l2cache.overall_avg_miss_latency::total 37506.514852 # average overall miss latency |
| 2199system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2200system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2201system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2202system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2203system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2204system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2177system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2178system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2179system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2180system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2181system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2182system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2205system.cpu1.l2cache.unused_prefetches 38928 # number of HardPF blocks evicted w/o reference 2206system.cpu1.l2cache.writebacks::writebacks 1071108 # number of writebacks 2207system.cpu1.l2cache.writebacks::total 1071108 # number of writebacks 2208system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4423 # number of ReadExReq MSHR hits 2209system.cpu1.l2cache.ReadExReq_mshr_hits::total 4423 # number of ReadExReq MSHR hits 2210system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 417 # number of ReadSharedReq MSHR hits 2211system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 417 # number of ReadSharedReq MSHR hits 2212system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4840 # number of demand (read+write) MSHR hits 2213system.cpu1.l2cache.demand_mshr_hits::total 4840 # number of demand (read+write) MSHR hits 2214system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4840 # number of overall MSHR hits 2215system.cpu1.l2cache.overall_mshr_hits::total 4840 # number of overall MSHR hits 2216system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 17957 # number of ReadReq MSHR misses 2217system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10279 # number of ReadReq MSHR misses 2218system.cpu1.l2cache.ReadReq_mshr_misses::total 28236 # number of ReadReq MSHR misses 2219system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 666851 # number of HardPFReq MSHR misses 2220system.cpu1.l2cache.HardPFReq_mshr_misses::total 666851 # number of HardPFReq MSHR misses 2221system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208369 # number of UpgradeReq MSHR misses 2222system.cpu1.l2cache.UpgradeReq_mshr_misses::total 208369 # number of UpgradeReq MSHR misses 2223system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202239 # number of SCUpgradeReq MSHR misses 2224system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202239 # number of SCUpgradeReq MSHR misses 2225system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2226system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2227system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 246542 # number of ReadExReq MSHR misses 2228system.cpu1.l2cache.ReadExReq_mshr_misses::total 246542 # number of ReadExReq MSHR misses 2229system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 452728 # number of ReadCleanReq MSHR misses 2230system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 452728 # number of ReadCleanReq MSHR misses 2231system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 888760 # number of ReadSharedReq MSHR misses 2232system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 888760 # number of ReadSharedReq MSHR misses 2233system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 249433 # number of InvalidateReq MSHR misses 2234system.cpu1.l2cache.InvalidateReq_mshr_misses::total 249433 # number of InvalidateReq MSHR misses 2235system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 17957 # number of demand (read+write) MSHR misses 2236system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10279 # number of demand (read+write) MSHR misses 2237system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 452728 # number of demand (read+write) MSHR misses 2238system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1135302 # number of demand (read+write) MSHR misses 2239system.cpu1.l2cache.demand_mshr_misses::total 1616266 # number of demand (read+write) MSHR misses 2240system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 17957 # number of overall MSHR misses 2241system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10279 # number of overall MSHR misses 2242system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 452728 # number of overall MSHR misses 2243system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1135302 # number of overall MSHR misses 2244system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 666851 # number of overall MSHR misses 2245system.cpu1.l2cache.overall_mshr_misses::total 2283117 # number of overall MSHR misses | 2183system.cpu1.l2cache.unused_prefetches 39938 # number of HardPF blocks evicted w/o reference 2184system.cpu1.l2cache.writebacks::writebacks 1086447 # number of writebacks 2185system.cpu1.l2cache.writebacks::total 1086447 # number of writebacks 2186system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4568 # number of ReadExReq MSHR hits 2187system.cpu1.l2cache.ReadExReq_mshr_hits::total 4568 # number of ReadExReq MSHR hits 2188system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 305 # number of ReadSharedReq MSHR hits 2189system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 305 # number of ReadSharedReq MSHR hits 2190system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 2191system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 2192system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4873 # number of demand (read+write) MSHR hits 2193system.cpu1.l2cache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits 2194system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4873 # number of overall MSHR hits 2195system.cpu1.l2cache.overall_mshr_hits::total 4873 # number of overall MSHR hits 2196system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18869 # number of ReadReq MSHR misses 2197system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10447 # number of ReadReq MSHR misses 2198system.cpu1.l2cache.ReadReq_mshr_misses::total 29316 # number of ReadReq MSHR misses 2199system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of HardPFReq MSHR misses 2200system.cpu1.l2cache.HardPFReq_mshr_misses::total 688963 # number of HardPFReq MSHR misses 2201system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206667 # number of UpgradeReq MSHR misses 2202system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206667 # number of UpgradeReq MSHR misses 2203system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194457 # number of SCUpgradeReq MSHR misses 2204system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194457 # number of SCUpgradeReq MSHR misses 2205system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses 2206system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 2207system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248873 # number of ReadExReq MSHR misses 2208system.cpu1.l2cache.ReadExReq_mshr_misses::total 248873 # number of ReadExReq MSHR misses 2209system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463851 # number of ReadCleanReq MSHR misses 2210system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463851 # number of ReadCleanReq MSHR misses 2211system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 883285 # number of ReadSharedReq MSHR misses 2212system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 883285 # number of ReadSharedReq MSHR misses 2213system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 248453 # number of InvalidateReq MSHR misses 2214system.cpu1.l2cache.InvalidateReq_mshr_misses::total 248453 # number of InvalidateReq MSHR misses 2215system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18869 # number of demand (read+write) MSHR misses 2216system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10447 # number of demand (read+write) MSHR misses 2217system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463851 # number of demand (read+write) MSHR misses 2218system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1132158 # number of demand (read+write) MSHR misses 2219system.cpu1.l2cache.demand_mshr_misses::total 1625325 # number of demand (read+write) MSHR misses 2220system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18869 # number of overall MSHR misses 2221system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10447 # number of overall MSHR misses 2222system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463851 # number of overall MSHR misses 2223system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1132158 # number of overall MSHR misses 2224system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of overall MSHR misses 2225system.cpu1.l2cache.overall_mshr_misses::total 2314288 # number of overall MSHR misses |
| 2246system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable | 2226system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable |
| 2247system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable 2248system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22313 # number of ReadReq MSHR uncacheable 2249system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 2250system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable | 2227system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable 2228system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8834 # number of ReadReq MSHR uncacheable 2229system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable 2230system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable |
| 2251system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses | 2231system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses |
| 2252system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses 2253system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43068 # number of overall MSHR uncacheable misses 2254system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of ReadReq MSHR miss cycles 2255system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 360967500 # number of ReadReq MSHR miss cycles 2256system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 843363000 # number of ReadReq MSHR miss cycles 2257system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of HardPFReq MSHR miss cycles 2258system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27800562984 # number of HardPFReq MSHR miss cycles 2259system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3852073000 # number of UpgradeReq MSHR miss cycles 2260system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3852073000 # number of UpgradeReq MSHR miss cycles 2261system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3071337500 # number of SCUpgradeReq MSHR miss cycles 2262system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3071337500 # number of SCUpgradeReq MSHR miss cycles 2263system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1741999 # number of SCUpgradeFailReq MSHR miss cycles 2264system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1741999 # number of SCUpgradeFailReq MSHR miss cycles 2265system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9224946500 # number of ReadExReq MSHR miss cycles 2266system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9224946500 # number of ReadExReq MSHR miss cycles 2267system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14216700500 # number of ReadCleanReq MSHR miss cycles 2268system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14216700500 # number of ReadCleanReq MSHR miss cycles 2269system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26383538000 # number of ReadSharedReq MSHR miss cycles 2270system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26383538000 # number of ReadSharedReq MSHR miss cycles 2271system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6621907000 # number of InvalidateReq MSHR miss cycles 2272system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6621907000 # number of InvalidateReq MSHR miss cycles 2273system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of demand (read+write) MSHR miss cycles 2274system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 360967500 # number of demand (read+write) MSHR miss cycles 2275system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14216700500 # number of demand (read+write) MSHR miss cycles 2276system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35608484500 # number of demand (read+write) MSHR miss cycles 2277system.cpu1.l2cache.demand_mshr_miss_latency::total 50668548000 # number of demand (read+write) MSHR miss cycles 2278system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of overall MSHR miss cycles 2279system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 360967500 # number of overall MSHR miss cycles 2280system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14216700500 # number of overall MSHR miss cycles 2281system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35608484500 # number of overall MSHR miss cycles 2282system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of overall MSHR miss cycles 2283system.cpu1.l2cache.overall_mshr_miss_latency::total 78469110984 # number of overall MSHR miss cycles 2284system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9647000 # number of ReadReq MSHR uncacheable cycles 2285system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3745274000 # number of ReadReq MSHR uncacheable cycles 2286system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3754921000 # number of ReadReq MSHR uncacheable cycles 2287system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9647000 # number of overall MSHR uncacheable cycles 2288system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3745274000 # number of overall MSHR uncacheable cycles 2289system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3754921000 # number of overall MSHR uncacheable cycles 2290system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for ReadReq accesses 2291system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for ReadReq accesses 2292system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.071192 # mshr miss rate for ReadReq accesses | 2232system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses 2233system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17889 # number of overall MSHR uncacheable misses 2234system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of ReadReq MSHR miss cycles 2235system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369914500 # number of ReadReq MSHR miss cycles 2236system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 890282500 # number of ReadReq MSHR miss cycles 2237system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of HardPFReq MSHR miss cycles 2238system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27673006691 # number of HardPFReq MSHR miss cycles 2239system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3909692000 # number of UpgradeReq MSHR miss cycles 2240system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3909692000 # number of UpgradeReq MSHR miss cycles 2241system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3000401499 # number of SCUpgradeReq MSHR miss cycles 2242system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3000401499 # number of SCUpgradeReq MSHR miss cycles 2243system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1812500 # number of SCUpgradeFailReq MSHR miss cycles 2244system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1812500 # number of SCUpgradeFailReq MSHR miss cycles 2245system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9302871999 # number of ReadExReq MSHR miss cycles 2246system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9302871999 # number of ReadExReq MSHR miss cycles 2247system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14056803000 # number of ReadCleanReq MSHR miss cycles 2248system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14056803000 # number of ReadCleanReq MSHR miss cycles 2249system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26558969500 # number of ReadSharedReq MSHR miss cycles 2250system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26558969500 # number of ReadSharedReq MSHR miss cycles 2251system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5731021500 # number of InvalidateReq MSHR miss cycles 2252system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5731021500 # number of InvalidateReq MSHR miss cycles 2253system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of demand (read+write) MSHR miss cycles 2254system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369914500 # number of demand (read+write) MSHR miss cycles 2255system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14056803000 # number of demand (read+write) MSHR miss cycles 2256system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35861841499 # number of demand (read+write) MSHR miss cycles 2257system.cpu1.l2cache.demand_mshr_miss_latency::total 50808926999 # number of demand (read+write) MSHR miss cycles 2258system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of overall MSHR miss cycles 2259system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369914500 # number of overall MSHR miss cycles 2260system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14056803000 # number of overall MSHR miss cycles 2261system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35861841499 # number of overall MSHR miss cycles 2262system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of overall MSHR miss cycles 2263system.cpu1.l2cache.overall_mshr_miss_latency::total 78481933690 # number of overall MSHR miss cycles 2264system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10092500 # number of ReadReq MSHR uncacheable cycles 2265system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1202508000 # number of ReadReq MSHR uncacheable cycles 2266system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1212600500 # number of ReadReq MSHR uncacheable cycles 2267system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10092500 # number of overall MSHR uncacheable cycles 2268system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1202508000 # number of overall MSHR uncacheable cycles 2269system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1212600500 # number of overall MSHR uncacheable cycles 2270system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for ReadReq accesses 2271system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for ReadReq accesses 2272system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.070206 # mshr miss rate for ReadReq accesses |
| 2293system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2294system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2295system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2296system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2297system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2298system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2299system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2300system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2273system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2274system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2275system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2276system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2277system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2278system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2279system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2280system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2301system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226946 # mshr miss rate for ReadExReq accesses 2302system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226946 # mshr miss rate for ReadExReq accesses 2303system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for ReadCleanReq accesses 2304system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090876 # mshr miss rate for ReadCleanReq accesses 2305system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253009 # mshr miss rate for ReadSharedReq accesses 2306system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253009 # mshr miss rate for ReadSharedReq accesses 2307system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565542 # mshr miss rate for InvalidateReq accesses 2308system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565542 # mshr miss rate for InvalidateReq accesses 2309system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for demand accesses 2310system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for demand accesses 2311system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for demand accesses 2312system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for demand accesses 2313system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161990 # mshr miss rate for demand accesses 2314system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for overall accesses 2315system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for overall accesses 2316system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for overall accesses 2317system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for overall accesses | 2281system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220271 # mshr miss rate for ReadExReq accesses 2282system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220271 # mshr miss rate for ReadExReq accesses 2283system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for ReadCleanReq accesses 2284system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092692 # mshr miss rate for ReadCleanReq accesses 2285system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242623 # mshr miss rate for ReadSharedReq accesses 2286system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242623 # mshr miss rate for ReadSharedReq accesses 2287system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.556993 # mshr miss rate for InvalidateReq accesses 2288system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.556993 # mshr miss rate for InvalidateReq accesses 2289system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for demand accesses 2290system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for demand accesses 2291system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for demand accesses 2292system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for demand accesses 2293system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159467 # mshr miss rate for demand accesses 2294system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for overall accesses 2295system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for overall accesses 2296system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for overall accesses 2297system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for overall accesses |
| 2318system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2298system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2319system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228826 # mshr miss rate for overall accesses 2320system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average ReadReq mshr miss latency 2321system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average ReadReq mshr miss latency 2322system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541 # average ReadReq mshr miss latency 2323system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average HardPFReq mshr miss latency 2324system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380 # average HardPFReq mshr miss latency 2325system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462 # average UpgradeReq mshr miss latency 2326system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462 # average UpgradeReq mshr miss latency 2327system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699 # average SCUpgradeReq mshr miss latency 2328system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699 # average SCUpgradeReq mshr miss latency 2329system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333 # average SCUpgradeFailReq mshr miss latency 2330system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333 # average SCUpgradeFailReq mshr miss latency 2331system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684 # average ReadExReq mshr miss latency 2332system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684 # average ReadExReq mshr miss latency 2333system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average ReadCleanReq mshr miss latency 2334system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057 # average ReadCleanReq mshr miss latency 2335system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689 # average ReadSharedReq mshr miss latency 2336system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689 # average ReadSharedReq mshr miss latency 2337system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498 # average InvalidateReq mshr miss latency 2338system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498 # average InvalidateReq mshr miss latency 2339system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency 2340system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency 2341system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency 2342system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency 2343system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312 # average overall mshr miss latency 2344system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency 2345system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency 2346system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency 2347system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency 2348system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average overall mshr miss latency 2349system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310 # average overall mshr miss latency 2350system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average ReadReq mshr uncacheable latency 2351system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003 # average ReadReq mshr uncacheable latency 2352system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840 # average ReadReq mshr uncacheable latency 2353system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average overall mshr uncacheable latency 2354system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353 # average overall mshr uncacheable latency 2355system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859 # average overall mshr uncacheable latency 2356system.cpu1.toL2Bus.snoop_filter.tot_requests 20600525 # Total number of requests made to the snoop filter. 2357system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10578683 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2358system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2359system.cpu1.toL2Bus.snoop_filter.tot_snoops 558580 # Total number of snoops made to the snoop filter. 2360system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 558580 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 2299system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses 2300system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency 2301system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency 2302system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency 2303system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency 2304system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency 2305system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency 2306system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency 2307system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency 2308system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency 2309system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency 2310system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency 2311system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency 2312system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency 2313system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency 2314system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency 2315system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency 2316system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency 2317system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency 2318system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency 2319system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency 2320system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency 2321system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency 2322system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency 2323system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency 2324system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency 2325system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency 2326system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency 2327system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency 2328system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency 2329system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency 2330system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency 2331system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency 2332system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency 2333system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency 2334system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency 2335system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency 2336system.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter. 2337system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2338system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2339system.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter. 2340system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 2361system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2341system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2362system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2363system.cpu1.toL2Bus.trans_dist::ReadReq 484798 # Transaction distribution 2364system.cpu1.toL2Bus.trans_dist::ReadResp 9068801 # Transaction distribution 2365system.cpu1.toL2Bus.trans_dist::WriteReq 20755 # Transaction distribution 2366system.cpu1.toL2Bus.trans_dist::WriteResp 20755 # Transaction distribution 2367system.cpu1.toL2Bus.trans_dist::WritebackDirty 4199993 # Transaction distribution 2368system.cpu1.toL2Bus.trans_dist::WritebackClean 6807874 # Transaction distribution 2369system.cpu1.toL2Bus.trans_dist::CleanEvict 1098101 # Transaction distribution 2370system.cpu1.toL2Bus.trans_dist::HardPFReq 809012 # Transaction distribution 2371system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2372system.cpu1.toL2Bus.trans_dist::UpgradeReq 385894 # Transaction distribution 2373system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368515 # Transaction distribution 2374system.cpu1.toL2Bus.trans_dist::UpgradeResp 474989 # Transaction distribution | 2342system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 2343system.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution 2344system.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution 2345system.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution 2346system.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution 2347system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution 2348system.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution 2349system.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution 2350system.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution 2351system.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution 2352system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution 2353system.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution |
| 2375system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution | 2354system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution |
| 2376system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 2377system.cpu1.toL2Bus.trans_dist::ReadExReq 1114310 # Transaction distribution 2378system.cpu1.toL2Bus.trans_dist::ReadExResp 1093127 # Transaction distribution 2379system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4981828 # Transaction distribution 2380system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4385137 # Transaction distribution 2381system.cpu1.toL2Bus.trans_dist::InvalidateReq 490192 # Transaction distribution 2382system.cpu1.toL2Bus.trans_dist::InvalidateResp 441051 # Transaction distribution 2383system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14945187 # Packet count per connected master and slave (bytes) 2384system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16097398 # Packet count per connected master and slave (bytes) 2385system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332311 # Packet count per connected master and slave (bytes) 2386system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 526789 # Packet count per connected master and slave (bytes) 2387system.cpu1.toL2Bus.pkt_count::total 31901685 # Packet count per connected master and slave (bytes) 2388system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 637641336 # Cumulative packet size per connected master and slave (bytes) 2389system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617397659 # Cumulative packet size per connected master and slave (bytes) 2390system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1265008 # Cumulative packet size per connected master and slave (bytes) 2391system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1907912 # Cumulative packet size per connected master and slave (bytes) 2392system.cpu1.toL2Bus.pkt_size::total 1258211915 # Cumulative packet size per connected master and slave (bytes) 2393system.cpu1.toL2Bus.snoops 4504290 # Total snoops (count) 2394system.cpu1.toL2Bus.snoopTraffic 75632944 # Total snoop traffic (bytes) 2395system.cpu1.toL2Bus.snoop_fanout::samples 15215883 # Request fanout histogram 2396system.cpu1.toL2Bus.snoop_fanout::mean 0.052359 # Request fanout histogram 2397system.cpu1.toL2Bus.snoop_fanout::stdev 0.222750 # Request fanout histogram | 2355system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 2356system.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution 2357system.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution 2358system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution 2359system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution 2360system.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution 2361system.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution 2362system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes) 2363system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes) 2364system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes) 2365system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes) 2366system.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes) 2367system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes) 2368system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes) 2369system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes) 2370system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes) 2371system.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes) 2372system.cpu1.toL2Bus.snoops 4569933 # Total snoops (count) 2373system.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes) 2374system.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram 2375system.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram 2376system.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram |
| 2398system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2377system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2399system.cpu1.toL2Bus.snoop_fanout::0 14419192 94.76% 94.76% # Request fanout histogram 2400system.cpu1.toL2Bus.snoop_fanout::1 796691 5.24% 100.00% # Request fanout histogram | 2378system.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram 2379system.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram |
| 2401system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2402system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2403system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2404system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 2380system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2381system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2382system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2383system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2405system.cpu1.toL2Bus.snoop_fanout::total 15215883 # Request fanout histogram 2406system.cpu1.toL2Bus.reqLayer0.occupancy 20375325498 # Layer occupancy (ticks) | 2384system.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram 2385system.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks) |
| 2407system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2386system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2408system.cpu1.toL2Bus.snoopLayer0.occupancy 176794994 # Layer occupancy (ticks) | 2387system.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks) |
| 2409system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2388system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2410system.cpu1.toL2Bus.respLayer0.occupancy 7472852000 # Layer occupancy (ticks) | 2389system.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks) |
| 2411system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2390system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2412system.cpu1.toL2Bus.respLayer1.occupancy 7357432377 # Layer occupancy (ticks) | 2391system.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks) |
| 2413system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2392system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2414system.cpu1.toL2Bus.respLayer2.occupancy 174185000 # Layer occupancy (ticks) | 2393system.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks) |
| 2415system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2394system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2416system.cpu1.toL2Bus.respLayer3.occupancy 288300000 # Layer occupancy (ticks) | 2395system.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks) |
| 2417system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2396system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2418system.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2419system.iobus.trans_dist::ReadReq 40355 # Transaction distribution 2420system.iobus.trans_dist::ReadResp 40355 # Transaction distribution 2421system.iobus.trans_dist::WriteReq 136628 # Transaction distribution 2422system.iobus.trans_dist::WriteResp 136628 # Transaction distribution 2423system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) | 2397system.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 2398system.iobus.trans_dist::ReadReq 40383 # Transaction distribution 2399system.iobus.trans_dist::ReadResp 40383 # Transaction distribution 2400system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 2401system.iobus.trans_dist::WriteResp 136636 # Transaction distribution 2402system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes) |
| 2424system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2425system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2426system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2427system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2428system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2429system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2430system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2431system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2432system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2433system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 2403system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2404system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2405system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2406system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2407system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2408system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2409system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2410system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2411system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2412system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 2434system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) | 2413system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) |
| 2435system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) | 2414system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) |
| 2436system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) 2437system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) 2438system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) | 2415system.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes) 2416system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) 2417system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) |
| 2439system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2440system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 2418system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2419system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 2441system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) 2442system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) | 2420system.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes) 2421system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes) |
| 2443system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2444system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2445system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2446system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2447system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2448system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2449system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2450system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2451system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2452system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 2422system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2423system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2424system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2425system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2426system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2427system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2428system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2429system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2430system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2431system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 2453system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) | 2432system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) |
| 2454system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) | 2433system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) |
| 2455system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) 2456system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) 2457system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) | 2434system.iobus.pkt_size_system.bridge.master::total 155799 # Cumulative packet size per connected master and slave (bytes) 2435system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) 2436system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) |
| 2458system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2459system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 2437system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2438system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 2460system.iobus.pkt_size::total 7496784 # Cumulative packet size per connected master and slave (bytes) 2461system.iobus.reqLayer0.occupancy 36982500 # Layer occupancy (ticks) | 2439system.iobus.pkt_size::total 7496965 # Cumulative packet size per connected master and slave (bytes) 2440system.iobus.reqLayer0.occupancy 36934001 # Layer occupancy (ticks) |
| 2462system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2441system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2463system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) | 2442system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) |
| 2464system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2443system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2465system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) | 2444system.iobus.reqLayer2.occupancy 319001 # Layer occupancy (ticks) |
| 2466system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2445system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2467system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) | 2446system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) |
| 2468system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 2447system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 2469system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) | 2448system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) |
| 2470system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2471system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2472system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) | 2449system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2450system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2451system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
| 2473system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) | 2452system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) |
| 2474system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2475system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2476system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2477system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2478system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 2453system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2454system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2455system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2456system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2457system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 2479system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) | 2458system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) |
| 2480system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2481system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2482system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 2459system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2460system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2461system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 2483system.iobus.reqLayer23.occupancy 26451500 # Layer occupancy (ticks) | 2462system.iobus.reqLayer23.occupancy 25636500 # Layer occupancy (ticks) |
| 2484system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 2463system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 2485system.iobus.reqLayer24.occupancy 37417000 # Layer occupancy (ticks) | 2464system.iobus.reqLayer24.occupancy 37418000 # Layer occupancy (ticks) |
| 2486system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 2465system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 2487system.iobus.reqLayer25.occupancy 569427501 # Layer occupancy (ticks) | 2466system.iobus.reqLayer25.occupancy 570101370 # Layer occupancy (ticks) |
| 2488system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) | 2467system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) |
| 2489system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) | 2468system.iobus.respLayer0.occupancy 92787000 # Layer occupancy (ticks) |
| 2490system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2469system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2491system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) | 2470system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) |
| 2492system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2493system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2494system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 2471system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2472system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2473system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 2495system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2496system.iocache.tags.replacements 115615 # number of replacements 2497system.iocache.tags.tagsinuse 11.298649 # Cycle average of tags in use | 2474system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 2475system.iocache.tags.replacements 115614 # number of replacements 2476system.iocache.tags.tagsinuse 11.296592 # Cycle average of tags in use |
| 2498system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 2477system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 2499system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. | 2478system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. |
| 2500system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 2479system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 2501system.iocache.tags.warmup_cycle 9136560427000 # Cycle when the warmup percentage was hit. 2502system.iocache.tags.occ_blocks::realview.ethernet 7.416178 # Average occupied blocks per requestor 2503system.iocache.tags.occ_blocks::realview.ide 3.882471 # Average occupied blocks per requestor 2504system.iocache.tags.occ_percent::realview.ethernet 0.463511 # Average percentage of cache occupancy 2505system.iocache.tags.occ_percent::realview.ide 0.242654 # Average percentage of cache occupancy 2506system.iocache.tags.occ_percent::total 0.706166 # Average percentage of cache occupancy | 2480system.iocache.tags.warmup_cycle 9136749782000 # Cycle when the warmup percentage was hit. 2481system.iocache.tags.occ_blocks::realview.ethernet 3.841541 # Average occupied blocks per requestor 2482system.iocache.tags.occ_blocks::realview.ide 7.455051 # Average occupied blocks per requestor 2483system.iocache.tags.occ_percent::realview.ethernet 0.240096 # Average percentage of cache occupancy 2484system.iocache.tags.occ_percent::realview.ide 0.465941 # Average percentage of cache occupancy 2485system.iocache.tags.occ_percent::total 0.706037 # Average percentage of cache occupancy |
| 2507system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2508system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2509system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2486system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2487system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2488system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2510system.iocache.tags.tag_accesses 1040856 # Number of tag accesses 2511system.iocache.tags.data_accesses 1040856 # Number of data accesses 2512system.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 2489system.iocache.tags.tag_accesses 1041054 # Number of tag accesses 2490system.iocache.tags.data_accesses 1041054 # Number of data accesses 2491system.iocache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 2513system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 2492system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 2514system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses 2515system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses | 2493system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses 2494system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses |
| 2516system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2517system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2518system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2519system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2520system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 2495system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2496system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2497system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2498system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2499system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 2521system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses 2522system.iocache.demand_misses::total 115651 # number of demand (read+write) misses | 2500system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses 2501system.iocache.demand_misses::total 115673 # number of demand (read+write) misses |
| 2523system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 2502system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 2524system.iocache.overall_misses::realview.ide 115611 # number of overall misses 2525system.iocache.overall_misses::total 115651 # number of overall misses 2526system.iocache.ReadReq_miss_latency::realview.ethernet 5193500 # number of ReadReq miss cycles 2527system.iocache.ReadReq_miss_latency::realview.ide 1828649003 # number of ReadReq miss cycles 2528system.iocache.ReadReq_miss_latency::total 1833842503 # number of ReadReq miss cycles | 2503system.iocache.overall_misses::realview.ide 115633 # number of overall misses 2504system.iocache.overall_misses::total 115673 # number of overall misses 2505system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 2506system.iocache.ReadReq_miss_latency::realview.ide 1975225504 # number of ReadReq miss cycles 2507system.iocache.ReadReq_miss_latency::total 1980423504 # number of ReadReq miss cycles |
| 2529system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2530system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles | 2508system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2509system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles |
| 2531system.iocache.WriteLineReq_miss_latency::realview.ide 13346157998 # number of WriteLineReq miss cycles 2532system.iocache.WriteLineReq_miss_latency::total 13346157998 # number of WriteLineReq miss cycles 2533system.iocache.demand_miss_latency::realview.ethernet 5562500 # number of demand (read+write) miss cycles 2534system.iocache.demand_miss_latency::realview.ide 15174807001 # number of demand (read+write) miss cycles 2535system.iocache.demand_miss_latency::total 15180369501 # number of demand (read+write) miss cycles 2536system.iocache.overall_miss_latency::realview.ethernet 5562500 # number of overall miss cycles 2537system.iocache.overall_miss_latency::realview.ide 15174807001 # number of overall miss cycles 2538system.iocache.overall_miss_latency::total 15180369501 # number of overall miss cycles | 2510system.iocache.WriteLineReq_miss_latency::realview.ide 13261468866 # number of WriteLineReq miss cycles 2511system.iocache.WriteLineReq_miss_latency::total 13261468866 # number of WriteLineReq miss cycles 2512system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 2513system.iocache.demand_miss_latency::realview.ide 15236694370 # number of demand (read+write) miss cycles 2514system.iocache.demand_miss_latency::total 15242261370 # number of demand (read+write) miss cycles 2515system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 2516system.iocache.overall_miss_latency::realview.ide 15236694370 # number of overall miss cycles 2517system.iocache.overall_miss_latency::total 15242261370 # number of overall miss cycles |
| 2539system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 2518system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 2540system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) 2541system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) | 2519system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) 2520system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) |
| 2542system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2543system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2544system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2545system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2546system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 2521system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2522system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2523system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2524system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2525system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 2547system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses 2548system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses | 2526system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses 2527system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses |
| 2549system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 2528system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 2550system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses 2551system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses | 2529system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses 2530system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses |
| 2552system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2553system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2554system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2555system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2556system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2557system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2558system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2559system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2560system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2561system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2562system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2563system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2564system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2531system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2532system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2533system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2534system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2535system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2536system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2537system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2538system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2539system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2540system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2541system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2542system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2543system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2565system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865 # average ReadReq miss latency 2566system.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686 # average ReadReq miss latency 2567system.iocache.ReadReq_avg_miss_latency::total 205587.724552 # average ReadReq miss latency | 2544system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 2545system.iocache.ReadReq_avg_miss_latency::realview.ide 221810.837058 # average ReadReq miss latency 2546system.iocache.ReadReq_avg_miss_latency::total 221474.335048 # average ReadReq miss latency |
| 2568system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2569system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency | 2547system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2548system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency |
| 2570system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442 # average WriteLineReq miss latency 2571system.iocache.WriteLineReq_avg_miss_latency::total 125048.328442 # average WriteLineReq miss latency 2572system.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency 2573system.iocache.demand_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency 2574system.iocache.demand_avg_miss_latency::total 131260.166371 # average overall miss latency 2575system.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency 2576system.iocache.overall_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency 2577system.iocache.overall_avg_miss_latency::total 131260.166371 # average overall miss latency 2578system.iocache.blocked_cycles::no_mshrs 41899 # number of cycles access was blocked | 2549system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124254.824095 # average WriteLineReq miss latency 2550system.iocache.WriteLineReq_avg_miss_latency::total 124254.824095 # average WriteLineReq miss latency 2551system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2552system.iocache.demand_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency 2553system.iocache.demand_avg_miss_latency::total 131770.260735 # average overall miss latency 2554system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2555system.iocache.overall_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency 2556system.iocache.overall_avg_miss_latency::total 131770.260735 # average overall miss latency 2557system.iocache.blocked_cycles::no_mshrs 49344 # number of cycles access was blocked |
| 2579system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2558system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2580system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked | 2559system.iocache.blocked::no_mshrs 3519 # number of cycles access was blocked |
| 2581system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2560system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2582system.iocache.avg_blocked_cycles::no_mshrs 11.852617 # average number of cycles each access was blocked | 2561system.iocache.avg_blocked_cycles::no_mshrs 14.022165 # average number of cycles each access was blocked |
| 2583system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2562system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2584system.iocache.writebacks::writebacks 106702 # number of writebacks 2585system.iocache.writebacks::total 106702 # number of writebacks | 2563system.iocache.writebacks::writebacks 106694 # number of writebacks 2564system.iocache.writebacks::total 106694 # number of writebacks |
| 2586system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses | 2565system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
| 2587system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses 2588system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses | 2566system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses 2567system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses |
| 2589system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2590system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2591system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2592system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2593system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 2568system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2569system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2570system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2571system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2572system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 2594system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses 2595system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses | 2573system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses 2574system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses |
| 2596system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 2575system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 2597system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses 2598system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses 2599system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3343500 # number of ReadReq MSHR miss cycles 2600system.iocache.ReadReq_mshr_miss_latency::realview.ide 1384499003 # number of ReadReq MSHR miss cycles 2601system.iocache.ReadReq_mshr_miss_latency::total 1387842503 # number of ReadReq MSHR miss cycles | 2576system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses 2577system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses 2578system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 2579system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529975504 # number of ReadReq MSHR miss cycles 2580system.iocache.ReadReq_mshr_miss_latency::total 1533323504 # number of ReadReq MSHR miss cycles |
| 2602system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2603system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles | 2581system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2582system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles |
| 2604system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8000796585 # number of WriteLineReq MSHR miss cycles 2605system.iocache.WriteLineReq_mshr_miss_latency::total 8000796585 # number of WriteLineReq MSHR miss cycles 2606system.iocache.demand_mshr_miss_latency::realview.ethernet 3562500 # number of demand (read+write) MSHR miss cycles 2607system.iocache.demand_mshr_miss_latency::realview.ide 9385295588 # number of demand (read+write) MSHR miss cycles 2608system.iocache.demand_mshr_miss_latency::total 9388858088 # number of demand (read+write) MSHR miss cycles 2609system.iocache.overall_mshr_miss_latency::realview.ethernet 3562500 # number of overall MSHR miss cycles 2610system.iocache.overall_mshr_miss_latency::realview.ide 9385295588 # number of overall MSHR miss cycles 2611system.iocache.overall_mshr_miss_latency::total 9388858088 # number of overall MSHR miss cycles | 2583system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7919102558 # number of WriteLineReq MSHR miss cycles 2584system.iocache.WriteLineReq_mshr_miss_latency::total 7919102558 # number of WriteLineReq MSHR miss cycles 2585system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 2586system.iocache.demand_mshr_miss_latency::realview.ide 9449078062 # number of demand (read+write) MSHR miss cycles 2587system.iocache.demand_mshr_miss_latency::total 9452645062 # number of demand (read+write) MSHR miss cycles 2588system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 2589system.iocache.overall_mshr_miss_latency::realview.ide 9449078062 # number of overall MSHR miss cycles 2590system.iocache.overall_mshr_miss_latency::total 9452645062 # number of overall MSHR miss cycles |
| 2612system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2613system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2614system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2615system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2616system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2617system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2618system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2619system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2620system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2621system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2622system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2623system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2624system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2591system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2592system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2593system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2594system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2595system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2596system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2597system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2598system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2599system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2600system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2601system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2602system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2603system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2625system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865 # average ReadReq mshr miss latency 2626system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686 # average ReadReq mshr miss latency 2627system.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552 # average ReadReq mshr miss latency | 2604system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 2605system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171810.837058 # average ReadReq mshr miss latency 2606system.iocache.ReadReq_avg_mshr_miss_latency::total 171474.335048 # average ReadReq mshr miss latency |
| 2628system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2629system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency | 2607system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2608system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency |
| 2630system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74964.363475 # average WriteLineReq mshr miss latency 2631system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74964.363475 # average WriteLineReq mshr miss latency 2632system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency 2633system.iocache.demand_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency 2634system.iocache.demand_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency 2635system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency 2636system.iocache.overall_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency 2637system.iocache.overall_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency 2638system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2639system.l2c.tags.replacements 1376932 # number of replacements 2640system.l2c.tags.tagsinuse 65061.419917 # Cycle average of tags in use 2641system.l2c.tags.total_refs 5975056 # Total number of references to valid blocks. 2642system.l2c.tags.sampled_refs 1437120 # Sample count of references to valid blocks. 2643system.l2c.tags.avg_refs 4.157660 # Average number of references to valid blocks. 2644system.l2c.tags.warmup_cycle 9858759500 # Cycle when the warmup percentage was hit. 2645system.l2c.tags.occ_blocks::writebacks 11843.449139 # Average occupied blocks per requestor 2646system.l2c.tags.occ_blocks::cpu0.dtb.walker 304.799159 # Average occupied blocks per requestor 2647system.l2c.tags.occ_blocks::cpu0.itb.walker 356.696004 # Average occupied blocks per requestor 2648system.l2c.tags.occ_blocks::cpu0.inst 3585.763677 # Average occupied blocks per requestor 2649system.l2c.tags.occ_blocks::cpu0.data 19085.445505 # Average occupied blocks per requestor 2650system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945 # Average occupied blocks per requestor 2651system.l2c.tags.occ_blocks::cpu1.dtb.walker 128.223998 # Average occupied blocks per requestor 2652system.l2c.tags.occ_blocks::cpu1.itb.walker 149.509582 # Average occupied blocks per requestor 2653system.l2c.tags.occ_blocks::cpu1.inst 3193.954857 # Average occupied blocks per requestor 2654system.l2c.tags.occ_blocks::cpu1.data 6240.562219 # Average occupied blocks per requestor 2655system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5949.868833 # Average occupied blocks per requestor 2656system.l2c.tags.occ_percent::writebacks 0.180717 # Average percentage of cache occupancy 2657system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004651 # Average percentage of cache occupancy 2658system.l2c.tags.occ_percent::cpu0.itb.walker 0.005443 # Average percentage of cache occupancy 2659system.l2c.tags.occ_percent::cpu0.inst 0.054714 # Average percentage of cache occupancy 2660system.l2c.tags.occ_percent::cpu0.data 0.291221 # Average percentage of cache occupancy 2661system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217028 # Average percentage of cache occupancy 2662system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001957 # Average percentage of cache occupancy 2663system.l2c.tags.occ_percent::cpu1.itb.walker 0.002281 # Average percentage of cache occupancy 2664system.l2c.tags.occ_percent::cpu1.inst 0.048736 # Average percentage of cache occupancy 2665system.l2c.tags.occ_percent::cpu1.data 0.095223 # Average percentage of cache occupancy 2666system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.090788 # Average percentage of cache occupancy 2667system.l2c.tags.occ_percent::total 0.992758 # Average percentage of cache occupancy 2668system.l2c.tags.occ_task_id_blocks::1022 11266 # Occupied blocks per task id 2669system.l2c.tags.occ_task_id_blocks::1023 259 # Occupied blocks per task id 2670system.l2c.tags.occ_task_id_blocks::1024 48663 # Occupied blocks per task id 2671system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2672system.l2c.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id 2673system.l2c.tags.age_task_id_blocks_1022::3 297 # Occupied blocks per task id 2674system.l2c.tags.age_task_id_blocks_1022::4 10816 # Occupied blocks per task id 2675system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id | 2609system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74198.922101 # average WriteLineReq mshr miss latency 2610system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74198.922101 # average WriteLineReq mshr miss latency 2611system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2612system.iocache.demand_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency 2613system.iocache.demand_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency 2614system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2615system.iocache.overall_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency 2616system.iocache.overall_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency 2617system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 2618system.l2c.tags.replacements 1381741 # number of replacements 2619system.l2c.tags.tagsinuse 65067.880129 # Cycle average of tags in use 2620system.l2c.tags.total_refs 5923587 # Total number of references to valid blocks. 2621system.l2c.tags.sampled_refs 1442494 # Sample count of references to valid blocks. 2622system.l2c.tags.avg_refs 4.106490 # Average number of references to valid blocks. 2623system.l2c.tags.warmup_cycle 9880371500 # Cycle when the warmup percentage was hit. 2624system.l2c.tags.occ_blocks::writebacks 12193.656277 # Average occupied blocks per requestor 2625system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.628854 # Average occupied blocks per requestor 2626system.l2c.tags.occ_blocks::cpu0.itb.walker 215.563389 # Average occupied blocks per requestor 2627system.l2c.tags.occ_blocks::cpu0.inst 4072.894051 # Average occupied blocks per requestor 2628system.l2c.tags.occ_blocks::cpu0.data 15215.630293 # Average occupied blocks per requestor 2629system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9216.886744 # Average occupied blocks per requestor 2630system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.489010 # Average occupied blocks per requestor 2631system.l2c.tags.occ_blocks::cpu1.itb.walker 298.478725 # Average occupied blocks per requestor 2632system.l2c.tags.occ_blocks::cpu1.inst 2688.288956 # Average occupied blocks per requestor 2633system.l2c.tags.occ_blocks::cpu1.data 9916.445518 # Average occupied blocks per requestor 2634system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10812.918313 # Average occupied blocks per requestor 2635system.l2c.tags.occ_percent::writebacks 0.186060 # Average percentage of cache occupancy 2636system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy 2637system.l2c.tags.occ_percent::cpu0.itb.walker 0.003289 # Average percentage of cache occupancy 2638system.l2c.tags.occ_percent::cpu0.inst 0.062147 # Average percentage of cache occupancy 2639system.l2c.tags.occ_percent::cpu0.data 0.232172 # Average percentage of cache occupancy 2640system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.140639 # Average percentage of cache occupancy 2641system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004021 # Average percentage of cache occupancy 2642system.l2c.tags.occ_percent::cpu1.itb.walker 0.004554 # Average percentage of cache occupancy 2643system.l2c.tags.occ_percent::cpu1.inst 0.041020 # Average percentage of cache occupancy 2644system.l2c.tags.occ_percent::cpu1.data 0.151313 # Average percentage of cache occupancy 2645system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.164992 # Average percentage of cache occupancy 2646system.l2c.tags.occ_percent::total 0.992857 # Average percentage of cache occupancy 2647system.l2c.tags.occ_task_id_blocks::1022 10723 # Occupied blocks per task id 2648system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id 2649system.l2c.tags.occ_task_id_blocks::1024 49775 # Occupied blocks per task id 2650system.l2c.tags.age_task_id_blocks_1022::2 111 # Occupied blocks per task id 2651system.l2c.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id 2652system.l2c.tags.age_task_id_blocks_1022::4 10351 # Occupied blocks per task id 2653system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2654system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id |
| 2676system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id | 2655system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id |
| 2677system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 2678system.l2c.tags.age_task_id_blocks_1024::2 888 # Occupied blocks per task id 2679system.l2c.tags.age_task_id_blocks_1024::3 4525 # Occupied blocks per task id 2680system.l2c.tags.age_task_id_blocks_1024::4 43209 # Occupied blocks per task id 2681system.l2c.tags.occ_task_id_percent::1022 0.171906 # Percentage of cache occupancy per task id 2682system.l2c.tags.occ_task_id_percent::1023 0.003952 # Percentage of cache occupancy per task id 2683system.l2c.tags.occ_task_id_percent::1024 0.742538 # Percentage of cache occupancy per task id 2684system.l2c.tags.tag_accesses 68586261 # Number of tag accesses 2685system.l2c.tags.data_accesses 68586261 # Number of data accesses 2686system.l2c.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2687system.l2c.WritebackDirty_hits::writebacks 2589224 # number of WritebackDirty hits 2688system.l2c.WritebackDirty_hits::total 2589224 # number of WritebackDirty hits 2689system.l2c.UpgradeReq_hits::cpu0.data 191644 # number of UpgradeReq hits 2690system.l2c.UpgradeReq_hits::cpu1.data 164185 # number of UpgradeReq hits 2691system.l2c.UpgradeReq_hits::total 355829 # number of UpgradeReq hits 2692system.l2c.SCUpgradeReq_hits::cpu0.data 48914 # number of SCUpgradeReq hits 2693system.l2c.SCUpgradeReq_hits::cpu1.data 48173 # number of SCUpgradeReq hits 2694system.l2c.SCUpgradeReq_hits::total 97087 # number of SCUpgradeReq hits 2695system.l2c.ReadExReq_hits::cpu0.data 47737 # number of ReadExReq hits 2696system.l2c.ReadExReq_hits::cpu1.data 58567 # number of ReadExReq hits 2697system.l2c.ReadExReq_hits::total 106304 # number of ReadExReq hits 2698system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 9201 # number of ReadSharedReq hits 2699system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3860 # number of ReadSharedReq hits 2700system.l2c.ReadSharedReq_hits::cpu0.inst 408160 # number of ReadSharedReq hits 2701system.l2c.ReadSharedReq_hits::cpu0.data 537157 # number of ReadSharedReq hits 2702system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 271610 # number of ReadSharedReq hits 2703system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10477 # number of ReadSharedReq hits 2704system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5555 # number of ReadSharedReq hits 2705system.l2c.ReadSharedReq_hits::cpu1.inst 408048 # number of ReadSharedReq hits 2706system.l2c.ReadSharedReq_hits::cpu1.data 521656 # number of ReadSharedReq hits 2707system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 272486 # number of ReadSharedReq hits 2708system.l2c.ReadSharedReq_hits::total 2448210 # number of ReadSharedReq hits 2709system.l2c.InvalidateReq_hits::cpu0.data 124551 # number of InvalidateReq hits 2710system.l2c.InvalidateReq_hits::cpu1.data 127410 # number of InvalidateReq hits 2711system.l2c.InvalidateReq_hits::total 251961 # number of InvalidateReq hits 2712system.l2c.demand_hits::cpu0.dtb.walker 9201 # number of demand (read+write) hits 2713system.l2c.demand_hits::cpu0.itb.walker 3860 # number of demand (read+write) hits 2714system.l2c.demand_hits::cpu0.inst 408160 # number of demand (read+write) hits 2715system.l2c.demand_hits::cpu0.data 584894 # number of demand (read+write) hits 2716system.l2c.demand_hits::cpu0.l2cache.prefetcher 271610 # number of demand (read+write) hits 2717system.l2c.demand_hits::cpu1.dtb.walker 10477 # number of demand (read+write) hits 2718system.l2c.demand_hits::cpu1.itb.walker 5555 # number of demand (read+write) hits 2719system.l2c.demand_hits::cpu1.inst 408048 # number of demand (read+write) hits 2720system.l2c.demand_hits::cpu1.data 580223 # number of demand (read+write) hits 2721system.l2c.demand_hits::cpu1.l2cache.prefetcher 272486 # number of demand (read+write) hits 2722system.l2c.demand_hits::total 2554514 # number of demand (read+write) hits 2723system.l2c.overall_hits::cpu0.dtb.walker 9201 # number of overall hits 2724system.l2c.overall_hits::cpu0.itb.walker 3860 # number of overall hits 2725system.l2c.overall_hits::cpu0.inst 408160 # number of overall hits 2726system.l2c.overall_hits::cpu0.data 584894 # number of overall hits 2727system.l2c.overall_hits::cpu0.l2cache.prefetcher 271610 # number of overall hits 2728system.l2c.overall_hits::cpu1.dtb.walker 10477 # number of overall hits 2729system.l2c.overall_hits::cpu1.itb.walker 5555 # number of overall hits 2730system.l2c.overall_hits::cpu1.inst 408048 # number of overall hits 2731system.l2c.overall_hits::cpu1.data 580223 # number of overall hits 2732system.l2c.overall_hits::cpu1.l2cache.prefetcher 272486 # number of overall hits 2733system.l2c.overall_hits::total 2554514 # number of overall hits 2734system.l2c.UpgradeReq_misses::cpu0.data 24439 # number of UpgradeReq misses 2735system.l2c.UpgradeReq_misses::cpu1.data 23204 # number of UpgradeReq misses 2736system.l2c.UpgradeReq_misses::total 47643 # number of UpgradeReq misses 2737system.l2c.SCUpgradeReq_misses::cpu0.data 628 # number of SCUpgradeReq misses 2738system.l2c.SCUpgradeReq_misses::cpu1.data 554 # number of SCUpgradeReq misses 2739system.l2c.SCUpgradeReq_misses::total 1182 # number of SCUpgradeReq misses 2740system.l2c.ReadExReq_misses::cpu0.data 75730 # number of ReadExReq misses 2741system.l2c.ReadExReq_misses::cpu1.data 50449 # number of ReadExReq misses 2742system.l2c.ReadExReq_misses::total 126179 # number of ReadExReq misses 2743system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1681 # number of ReadSharedReq misses 2744system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1744 # number of ReadSharedReq misses 2745system.l2c.ReadSharedReq_misses::cpu0.inst 48585 # number of ReadSharedReq misses 2746system.l2c.ReadSharedReq_misses::cpu0.data 141383 # number of ReadSharedReq misses 2747system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 241091 # number of ReadSharedReq misses 2748system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1909 # number of ReadSharedReq misses 2749system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1973 # number of ReadSharedReq misses 2750system.l2c.ReadSharedReq_misses::cpu1.inst 44680 # number of ReadSharedReq misses 2751system.l2c.ReadSharedReq_misses::cpu1.data 100605 # number of ReadSharedReq misses 2752system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq misses 2753system.l2c.ReadSharedReq_misses::total 753125 # number of ReadSharedReq misses 2754system.l2c.InvalidateReq_misses::cpu0.data 440725 # number of InvalidateReq misses 2755system.l2c.InvalidateReq_misses::cpu1.data 106525 # number of InvalidateReq misses 2756system.l2c.InvalidateReq_misses::total 547250 # number of InvalidateReq misses 2757system.l2c.demand_misses::cpu0.dtb.walker 1681 # number of demand (read+write) misses 2758system.l2c.demand_misses::cpu0.itb.walker 1744 # number of demand (read+write) misses 2759system.l2c.demand_misses::cpu0.inst 48585 # number of demand (read+write) misses 2760system.l2c.demand_misses::cpu0.data 217113 # number of demand (read+write) misses 2761system.l2c.demand_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) misses 2762system.l2c.demand_misses::cpu1.dtb.walker 1909 # number of demand (read+write) misses 2763system.l2c.demand_misses::cpu1.itb.walker 1973 # number of demand (read+write) misses 2764system.l2c.demand_misses::cpu1.inst 44680 # number of demand (read+write) misses 2765system.l2c.demand_misses::cpu1.data 151054 # number of demand (read+write) misses 2766system.l2c.demand_misses::cpu1.l2cache.prefetcher 169474 # number of demand (read+write) misses 2767system.l2c.demand_misses::total 879304 # number of demand (read+write) misses 2768system.l2c.overall_misses::cpu0.dtb.walker 1681 # number of overall misses 2769system.l2c.overall_misses::cpu0.itb.walker 1744 # number of overall misses 2770system.l2c.overall_misses::cpu0.inst 48585 # number of overall misses 2771system.l2c.overall_misses::cpu0.data 217113 # number of overall misses 2772system.l2c.overall_misses::cpu0.l2cache.prefetcher 241091 # number of overall misses 2773system.l2c.overall_misses::cpu1.dtb.walker 1909 # number of overall misses 2774system.l2c.overall_misses::cpu1.itb.walker 1973 # number of overall misses 2775system.l2c.overall_misses::cpu1.inst 44680 # number of overall misses 2776system.l2c.overall_misses::cpu1.data 151054 # number of overall misses 2777system.l2c.overall_misses::cpu1.l2cache.prefetcher 169474 # number of overall misses 2778system.l2c.overall_misses::total 879304 # number of overall misses 2779system.l2c.UpgradeReq_miss_latency::cpu0.data 162640000 # number of UpgradeReq miss cycles 2780system.l2c.UpgradeReq_miss_latency::cpu1.data 138377500 # number of UpgradeReq miss cycles 2781system.l2c.UpgradeReq_miss_latency::total 301017500 # number of UpgradeReq miss cycles 2782system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7502500 # number of SCUpgradeReq miss cycles 2783system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7047000 # number of SCUpgradeReq miss cycles 2784system.l2c.SCUpgradeReq_miss_latency::total 14549500 # number of SCUpgradeReq miss cycles 2785system.l2c.ReadExReq_miss_latency::cpu0.data 8218459999 # number of ReadExReq miss cycles 2786system.l2c.ReadExReq_miss_latency::cpu1.data 5520286999 # number of ReadExReq miss cycles 2787system.l2c.ReadExReq_miss_latency::total 13738746998 # number of ReadExReq miss cycles 2788system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 167721500 # number of ReadSharedReq miss cycles 2789system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 180518500 # number of ReadSharedReq miss cycles 2790system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5556413500 # number of ReadSharedReq miss cycles 2791system.l2c.ReadSharedReq_miss_latency::cpu0.data 15487743000 # number of ReadSharedReq miss cycles 2792system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of ReadSharedReq miss cycles 2793system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 194137000 # number of ReadSharedReq miss cycles 2794system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 210753000 # number of ReadSharedReq miss cycles 2795system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5171670000 # number of ReadSharedReq miss cycles 2796system.l2c.ReadSharedReq_miss_latency::cpu1.data 11743795000 # number of ReadSharedReq miss cycles 2797system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of ReadSharedReq miss cycles 2798system.l2c.ReadSharedReq_miss_latency::total 93664269011 # number of ReadSharedReq miss cycles 2799system.l2c.InvalidateReq_miss_latency::cpu0.data 42596000 # number of InvalidateReq miss cycles 2800system.l2c.InvalidateReq_miss_latency::cpu1.data 33301500 # number of InvalidateReq miss cycles 2801system.l2c.InvalidateReq_miss_latency::total 75897500 # number of InvalidateReq miss cycles 2802system.l2c.demand_miss_latency::cpu0.dtb.walker 167721500 # number of demand (read+write) miss cycles 2803system.l2c.demand_miss_latency::cpu0.itb.walker 180518500 # number of demand (read+write) miss cycles 2804system.l2c.demand_miss_latency::cpu0.inst 5556413500 # number of demand (read+write) miss cycles 2805system.l2c.demand_miss_latency::cpu0.data 23706202999 # number of demand (read+write) miss cycles 2806system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of demand (read+write) miss cycles 2807system.l2c.demand_miss_latency::cpu1.dtb.walker 194137000 # number of demand (read+write) miss cycles 2808system.l2c.demand_miss_latency::cpu1.itb.walker 210753000 # number of demand (read+write) miss cycles 2809system.l2c.demand_miss_latency::cpu1.inst 5171670000 # number of demand (read+write) miss cycles 2810system.l2c.demand_miss_latency::cpu1.data 17264081999 # number of demand (read+write) miss cycles 2811system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of demand (read+write) miss cycles 2812system.l2c.demand_miss_latency::total 107403016009 # number of demand (read+write) miss cycles 2813system.l2c.overall_miss_latency::cpu0.dtb.walker 167721500 # number of overall miss cycles 2814system.l2c.overall_miss_latency::cpu0.itb.walker 180518500 # number of overall miss cycles 2815system.l2c.overall_miss_latency::cpu0.inst 5556413500 # number of overall miss cycles 2816system.l2c.overall_miss_latency::cpu0.data 23706202999 # number of overall miss cycles 2817system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of overall miss cycles 2818system.l2c.overall_miss_latency::cpu1.dtb.walker 194137000 # number of overall miss cycles 2819system.l2c.overall_miss_latency::cpu1.itb.walker 210753000 # number of overall miss cycles 2820system.l2c.overall_miss_latency::cpu1.inst 5171670000 # number of overall miss cycles 2821system.l2c.overall_miss_latency::cpu1.data 17264081999 # number of overall miss cycles 2822system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of overall miss cycles 2823system.l2c.overall_miss_latency::total 107403016009 # number of overall miss cycles 2824system.l2c.WritebackDirty_accesses::writebacks 2589224 # number of WritebackDirty accesses(hits+misses) 2825system.l2c.WritebackDirty_accesses::total 2589224 # number of WritebackDirty accesses(hits+misses) 2826system.l2c.UpgradeReq_accesses::cpu0.data 216083 # number of UpgradeReq accesses(hits+misses) 2827system.l2c.UpgradeReq_accesses::cpu1.data 187389 # number of UpgradeReq accesses(hits+misses) 2828system.l2c.UpgradeReq_accesses::total 403472 # number of UpgradeReq accesses(hits+misses) 2829system.l2c.SCUpgradeReq_accesses::cpu0.data 49542 # number of SCUpgradeReq accesses(hits+misses) 2830system.l2c.SCUpgradeReq_accesses::cpu1.data 48727 # number of SCUpgradeReq accesses(hits+misses) 2831system.l2c.SCUpgradeReq_accesses::total 98269 # number of SCUpgradeReq accesses(hits+misses) 2832system.l2c.ReadExReq_accesses::cpu0.data 123467 # number of ReadExReq accesses(hits+misses) 2833system.l2c.ReadExReq_accesses::cpu1.data 109016 # number of ReadExReq accesses(hits+misses) 2834system.l2c.ReadExReq_accesses::total 232483 # number of ReadExReq accesses(hits+misses) 2835system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10882 # number of ReadSharedReq accesses(hits+misses) 2836system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5604 # number of ReadSharedReq accesses(hits+misses) 2837system.l2c.ReadSharedReq_accesses::cpu0.inst 456745 # number of ReadSharedReq accesses(hits+misses) 2838system.l2c.ReadSharedReq_accesses::cpu0.data 678540 # number of ReadSharedReq accesses(hits+misses) 2839system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 512701 # number of ReadSharedReq accesses(hits+misses) 2840system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12386 # number of ReadSharedReq accesses(hits+misses) 2841system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7528 # number of ReadSharedReq accesses(hits+misses) 2842system.l2c.ReadSharedReq_accesses::cpu1.inst 452728 # number of ReadSharedReq accesses(hits+misses) 2843system.l2c.ReadSharedReq_accesses::cpu1.data 622261 # number of ReadSharedReq accesses(hits+misses) 2844system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 441960 # number of ReadSharedReq accesses(hits+misses) 2845system.l2c.ReadSharedReq_accesses::total 3201335 # number of ReadSharedReq accesses(hits+misses) 2846system.l2c.InvalidateReq_accesses::cpu0.data 565276 # number of InvalidateReq accesses(hits+misses) 2847system.l2c.InvalidateReq_accesses::cpu1.data 233935 # number of InvalidateReq accesses(hits+misses) 2848system.l2c.InvalidateReq_accesses::total 799211 # number of InvalidateReq accesses(hits+misses) 2849system.l2c.demand_accesses::cpu0.dtb.walker 10882 # number of demand (read+write) accesses 2850system.l2c.demand_accesses::cpu0.itb.walker 5604 # number of demand (read+write) accesses 2851system.l2c.demand_accesses::cpu0.inst 456745 # number of demand (read+write) accesses 2852system.l2c.demand_accesses::cpu0.data 802007 # number of demand (read+write) accesses 2853system.l2c.demand_accesses::cpu0.l2cache.prefetcher 512701 # number of demand (read+write) accesses 2854system.l2c.demand_accesses::cpu1.dtb.walker 12386 # number of demand (read+write) accesses 2855system.l2c.demand_accesses::cpu1.itb.walker 7528 # number of demand (read+write) accesses 2856system.l2c.demand_accesses::cpu1.inst 452728 # number of demand (read+write) accesses 2857system.l2c.demand_accesses::cpu1.data 731277 # number of demand (read+write) accesses 2858system.l2c.demand_accesses::cpu1.l2cache.prefetcher 441960 # number of demand (read+write) accesses 2859system.l2c.demand_accesses::total 3433818 # number of demand (read+write) accesses 2860system.l2c.overall_accesses::cpu0.dtb.walker 10882 # number of overall (read+write) accesses 2861system.l2c.overall_accesses::cpu0.itb.walker 5604 # number of overall (read+write) accesses 2862system.l2c.overall_accesses::cpu0.inst 456745 # number of overall (read+write) accesses 2863system.l2c.overall_accesses::cpu0.data 802007 # number of overall (read+write) accesses 2864system.l2c.overall_accesses::cpu0.l2cache.prefetcher 512701 # number of overall (read+write) accesses 2865system.l2c.overall_accesses::cpu1.dtb.walker 12386 # number of overall (read+write) accesses 2866system.l2c.overall_accesses::cpu1.itb.walker 7528 # number of overall (read+write) accesses 2867system.l2c.overall_accesses::cpu1.inst 452728 # number of overall (read+write) accesses 2868system.l2c.overall_accesses::cpu1.data 731277 # number of overall (read+write) accesses 2869system.l2c.overall_accesses::cpu1.l2cache.prefetcher 441960 # number of overall (read+write) accesses 2870system.l2c.overall_accesses::total 3433818 # number of overall (read+write) accesses 2871system.l2c.UpgradeReq_miss_rate::cpu0.data 0.113100 # miss rate for UpgradeReq accesses 2872system.l2c.UpgradeReq_miss_rate::cpu1.data 0.123828 # miss rate for UpgradeReq accesses 2873system.l2c.UpgradeReq_miss_rate::total 0.118083 # miss rate for UpgradeReq accesses 2874system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012676 # miss rate for SCUpgradeReq accesses 2875system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.011369 # miss rate for SCUpgradeReq accesses 2876system.l2c.SCUpgradeReq_miss_rate::total 0.012028 # miss rate for SCUpgradeReq accesses 2877system.l2c.ReadExReq_miss_rate::cpu0.data 0.613362 # miss rate for ReadExReq accesses 2878system.l2c.ReadExReq_miss_rate::cpu1.data 0.462767 # miss rate for ReadExReq accesses 2879system.l2c.ReadExReq_miss_rate::total 0.542745 # miss rate for ReadExReq accesses 2880system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for ReadSharedReq accesses 2881system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.311206 # miss rate for ReadSharedReq accesses 2882system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106372 # miss rate for ReadSharedReq accesses 2883system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.208364 # miss rate for ReadSharedReq accesses 2884system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for ReadSharedReq accesses 2885system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for ReadSharedReq accesses 2886system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.262088 # miss rate for ReadSharedReq accesses 2887system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098691 # miss rate for ReadSharedReq accesses 2888system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.161677 # miss rate for ReadSharedReq accesses 2889system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for ReadSharedReq accesses 2890system.l2c.ReadSharedReq_miss_rate::total 0.235253 # miss rate for ReadSharedReq accesses 2891system.l2c.InvalidateReq_miss_rate::cpu0.data 0.779663 # miss rate for InvalidateReq accesses 2892system.l2c.InvalidateReq_miss_rate::cpu1.data 0.455362 # miss rate for InvalidateReq accesses 2893system.l2c.InvalidateReq_miss_rate::total 0.684738 # miss rate for InvalidateReq accesses 2894system.l2c.demand_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for demand accesses 2895system.l2c.demand_miss_rate::cpu0.itb.walker 0.311206 # miss rate for demand accesses 2896system.l2c.demand_miss_rate::cpu0.inst 0.106372 # miss rate for demand accesses 2897system.l2c.demand_miss_rate::cpu0.data 0.270712 # miss rate for demand accesses 2898system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for demand accesses 2899system.l2c.demand_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for demand accesses 2900system.l2c.demand_miss_rate::cpu1.itb.walker 0.262088 # miss rate for demand accesses 2901system.l2c.demand_miss_rate::cpu1.inst 0.098691 # miss rate for demand accesses 2902system.l2c.demand_miss_rate::cpu1.data 0.206562 # miss rate for demand accesses 2903system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for demand accesses 2904system.l2c.demand_miss_rate::total 0.256072 # miss rate for demand accesses 2905system.l2c.overall_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for overall accesses 2906system.l2c.overall_miss_rate::cpu0.itb.walker 0.311206 # miss rate for overall accesses 2907system.l2c.overall_miss_rate::cpu0.inst 0.106372 # miss rate for overall accesses 2908system.l2c.overall_miss_rate::cpu0.data 0.270712 # miss rate for overall accesses 2909system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for overall accesses 2910system.l2c.overall_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for overall accesses 2911system.l2c.overall_miss_rate::cpu1.itb.walker 0.262088 # miss rate for overall accesses 2912system.l2c.overall_miss_rate::cpu1.inst 0.098691 # miss rate for overall accesses 2913system.l2c.overall_miss_rate::cpu1.data 0.206562 # miss rate for overall accesses 2914system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for overall accesses 2915system.l2c.overall_miss_rate::total 0.256072 # miss rate for overall accesses 2916system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6654.936781 # average UpgradeReq miss latency 2917system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5963.519221 # average UpgradeReq miss latency 2918system.l2c.UpgradeReq_avg_miss_latency::total 6318.189451 # average UpgradeReq miss latency 2919system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11946.656051 # average SCUpgradeReq miss latency 2920system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12720.216606 # average SCUpgradeReq miss latency 2921system.l2c.SCUpgradeReq_avg_miss_latency::total 12309.221658 # average SCUpgradeReq miss latency 2922system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108523.174422 # average ReadExReq miss latency 2923system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109423.120359 # average ReadExReq miss latency 2924system.l2c.ReadExReq_avg_miss_latency::total 108882.991607 # average ReadExReq miss latency 2925system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average ReadSharedReq miss latency 2926system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 103508.314220 # average ReadSharedReq miss latency 2927system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114364.793661 # average ReadSharedReq miss latency 2928system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109544.591641 # average ReadSharedReq miss latency 2929system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average ReadSharedReq miss latency 2930system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average ReadSharedReq miss latency 2931system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 106818.550431 # average ReadSharedReq miss latency 2932system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 115749.104745 # average ReadSharedReq miss latency 2933system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116731.723075 # average ReadSharedReq miss latency 2934system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average ReadSharedReq miss latency 2935system.l2c.ReadSharedReq_avg_miss_latency::total 124367.494122 # average ReadSharedReq miss latency 2936system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 96.649838 # average InvalidateReq miss latency 2937system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 312.616757 # average InvalidateReq miss latency 2938system.l2c.InvalidateReq_avg_miss_latency::total 138.688899 # average InvalidateReq miss latency 2939system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average overall miss latency 2940system.l2c.demand_avg_miss_latency::cpu0.itb.walker 103508.314220 # average overall miss latency 2941system.l2c.demand_avg_miss_latency::cpu0.inst 114364.793661 # average overall miss latency 2942system.l2c.demand_avg_miss_latency::cpu0.data 109188.316678 # average overall miss latency 2943system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average overall miss latency 2944system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average overall miss latency 2945system.l2c.demand_avg_miss_latency::cpu1.itb.walker 106818.550431 # average overall miss latency 2946system.l2c.demand_avg_miss_latency::cpu1.inst 115749.104745 # average overall miss latency 2947system.l2c.demand_avg_miss_latency::cpu1.data 114290.796662 # average overall miss latency 2948system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average overall miss latency 2949system.l2c.demand_avg_miss_latency::total 122145.487805 # average overall miss latency 2950system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average overall miss latency 2951system.l2c.overall_avg_miss_latency::cpu0.itb.walker 103508.314220 # average overall miss latency 2952system.l2c.overall_avg_miss_latency::cpu0.inst 114364.793661 # average overall miss latency 2953system.l2c.overall_avg_miss_latency::cpu0.data 109188.316678 # average overall miss latency 2954system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average overall miss latency 2955system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average overall miss latency 2956system.l2c.overall_avg_miss_latency::cpu1.itb.walker 106818.550431 # average overall miss latency 2957system.l2c.overall_avg_miss_latency::cpu1.inst 115749.104745 # average overall miss latency 2958system.l2c.overall_avg_miss_latency::cpu1.data 114290.796662 # average overall miss latency 2959system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average overall miss latency 2960system.l2c.overall_avg_miss_latency::total 122145.487805 # average overall miss latency 2961system.l2c.blocked_cycles::no_mshrs 340 # number of cycles access was blocked | 2656system.l2c.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 2657system.l2c.tags.age_task_id_blocks_1024::2 1155 # Occupied blocks per task id 2658system.l2c.tags.age_task_id_blocks_1024::3 4128 # Occupied blocks per task id 2659system.l2c.tags.age_task_id_blocks_1024::4 44374 # Occupied blocks per task id 2660system.l2c.tags.occ_task_id_percent::1022 0.163620 # Percentage of cache occupancy per task id 2661system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id 2662system.l2c.tags.occ_task_id_percent::1024 0.759506 # Percentage of cache occupancy per task id 2663system.l2c.tags.tag_accesses 67794643 # Number of tag accesses 2664system.l2c.tags.data_accesses 67794643 # Number of data accesses 2665system.l2c.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 2666system.l2c.WritebackDirty_hits::writebacks 2588139 # number of WritebackDirty hits 2667system.l2c.WritebackDirty_hits::total 2588139 # number of WritebackDirty hits 2668system.l2c.UpgradeReq_hits::cpu0.data 176729 # number of UpgradeReq hits 2669system.l2c.UpgradeReq_hits::cpu1.data 155906 # number of UpgradeReq hits 2670system.l2c.UpgradeReq_hits::total 332635 # number of UpgradeReq hits 2671system.l2c.SCUpgradeReq_hits::cpu0.data 47999 # number of SCUpgradeReq hits 2672system.l2c.SCUpgradeReq_hits::cpu1.data 52030 # number of SCUpgradeReq hits 2673system.l2c.SCUpgradeReq_hits::total 100029 # number of SCUpgradeReq hits 2674system.l2c.ReadExReq_hits::cpu0.data 45484 # number of ReadExReq hits 2675system.l2c.ReadExReq_hits::cpu1.data 61265 # number of ReadExReq hits 2676system.l2c.ReadExReq_hits::total 106749 # number of ReadExReq hits 2677system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 8895 # number of ReadSharedReq hits 2678system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3831 # number of ReadSharedReq hits 2679system.l2c.ReadSharedReq_hits::cpu0.inst 389694 # number of ReadSharedReq hits 2680system.l2c.ReadSharedReq_hits::cpu0.data 511362 # number of ReadSharedReq hits 2681system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 253998 # number of ReadSharedReq hits 2682system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11472 # number of ReadSharedReq hits 2683system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5780 # number of ReadSharedReq hits 2684system.l2c.ReadSharedReq_hits::cpu1.inst 424247 # number of ReadSharedReq hits 2685system.l2c.ReadSharedReq_hits::cpu1.data 536390 # number of ReadSharedReq hits 2686system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284910 # number of ReadSharedReq hits 2687system.l2c.ReadSharedReq_hits::total 2430579 # number of ReadSharedReq hits 2688system.l2c.InvalidateReq_hits::cpu0.data 112195 # number of InvalidateReq hits 2689system.l2c.InvalidateReq_hits::cpu1.data 128573 # number of InvalidateReq hits 2690system.l2c.InvalidateReq_hits::total 240768 # number of InvalidateReq hits 2691system.l2c.demand_hits::cpu0.dtb.walker 8895 # number of demand (read+write) hits 2692system.l2c.demand_hits::cpu0.itb.walker 3831 # number of demand (read+write) hits 2693system.l2c.demand_hits::cpu0.inst 389694 # number of demand (read+write) hits 2694system.l2c.demand_hits::cpu0.data 556846 # number of demand (read+write) hits 2695system.l2c.demand_hits::cpu0.l2cache.prefetcher 253998 # number of demand (read+write) hits 2696system.l2c.demand_hits::cpu1.dtb.walker 11472 # number of demand (read+write) hits 2697system.l2c.demand_hits::cpu1.itb.walker 5780 # number of demand (read+write) hits 2698system.l2c.demand_hits::cpu1.inst 424247 # number of demand (read+write) hits 2699system.l2c.demand_hits::cpu1.data 597655 # number of demand (read+write) hits 2700system.l2c.demand_hits::cpu1.l2cache.prefetcher 284910 # number of demand (read+write) hits 2701system.l2c.demand_hits::total 2537328 # number of demand (read+write) hits 2702system.l2c.overall_hits::cpu0.dtb.walker 8895 # number of overall hits 2703system.l2c.overall_hits::cpu0.itb.walker 3831 # number of overall hits 2704system.l2c.overall_hits::cpu0.inst 389694 # number of overall hits 2705system.l2c.overall_hits::cpu0.data 556846 # number of overall hits 2706system.l2c.overall_hits::cpu0.l2cache.prefetcher 253998 # number of overall hits 2707system.l2c.overall_hits::cpu1.dtb.walker 11472 # number of overall hits 2708system.l2c.overall_hits::cpu1.itb.walker 5780 # number of overall hits 2709system.l2c.overall_hits::cpu1.inst 424247 # number of overall hits 2710system.l2c.overall_hits::cpu1.data 597655 # number of overall hits 2711system.l2c.overall_hits::cpu1.l2cache.prefetcher 284910 # number of overall hits 2712system.l2c.overall_hits::total 2537328 # number of overall hits 2713system.l2c.UpgradeReq_misses::cpu0.data 21760 # number of UpgradeReq misses 2714system.l2c.UpgradeReq_misses::cpu1.data 23268 # number of UpgradeReq misses 2715system.l2c.UpgradeReq_misses::total 45028 # number of UpgradeReq misses 2716system.l2c.SCUpgradeReq_misses::cpu0.data 910 # number of SCUpgradeReq misses 2717system.l2c.SCUpgradeReq_misses::cpu1.data 658 # number of SCUpgradeReq misses 2718system.l2c.SCUpgradeReq_misses::total 1568 # number of SCUpgradeReq misses 2719system.l2c.ReadExReq_misses::cpu0.data 75776 # number of ReadExReq misses 2720system.l2c.ReadExReq_misses::cpu1.data 50200 # number of ReadExReq misses 2721system.l2c.ReadExReq_misses::total 125976 # number of ReadExReq misses 2722system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses 2723system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1542 # number of ReadSharedReq misses 2724system.l2c.ReadSharedReq_misses::cpu0.inst 53195 # number of ReadSharedReq misses 2725system.l2c.ReadSharedReq_misses::cpu0.data 142597 # number of ReadSharedReq misses 2726system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq misses 2727system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq misses 2728system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2105 # number of ReadSharedReq misses 2729system.l2c.ReadSharedReq_misses::cpu1.inst 39604 # number of ReadSharedReq misses 2730system.l2c.ReadSharedReq_misses::cpu1.data 101630 # number of ReadSharedReq misses 2731system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq misses 2732system.l2c.ReadSharedReq_misses::total 753120 # number of ReadSharedReq misses 2733system.l2c.InvalidateReq_misses::cpu0.data 431914 # number of InvalidateReq misses 2734system.l2c.InvalidateReq_misses::cpu1.data 78834 # number of InvalidateReq misses 2735system.l2c.InvalidateReq_misses::total 510748 # number of InvalidateReq misses 2736system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses 2737system.l2c.demand_misses::cpu0.itb.walker 1542 # number of demand (read+write) misses 2738system.l2c.demand_misses::cpu0.inst 53195 # number of demand (read+write) misses 2739system.l2c.demand_misses::cpu0.data 218373 # number of demand (read+write) misses 2740system.l2c.demand_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) misses 2741system.l2c.demand_misses::cpu1.dtb.walker 2105 # number of demand (read+write) misses 2742system.l2c.demand_misses::cpu1.itb.walker 2105 # number of demand (read+write) misses 2743system.l2c.demand_misses::cpu1.inst 39604 # number of demand (read+write) misses 2744system.l2c.demand_misses::cpu1.data 151830 # number of demand (read+write) misses 2745system.l2c.demand_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) misses 2746system.l2c.demand_misses::total 879096 # number of demand (read+write) misses 2747system.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses 2748system.l2c.overall_misses::cpu0.itb.walker 1542 # number of overall misses 2749system.l2c.overall_misses::cpu0.inst 53195 # number of overall misses 2750system.l2c.overall_misses::cpu0.data 218373 # number of overall misses 2751system.l2c.overall_misses::cpu0.l2cache.prefetcher 239651 # number of overall misses 2752system.l2c.overall_misses::cpu1.dtb.walker 2105 # number of overall misses 2753system.l2c.overall_misses::cpu1.itb.walker 2105 # number of overall misses 2754system.l2c.overall_misses::cpu1.inst 39604 # number of overall misses 2755system.l2c.overall_misses::cpu1.data 151830 # number of overall misses 2756system.l2c.overall_misses::cpu1.l2cache.prefetcher 169145 # number of overall misses 2757system.l2c.overall_misses::total 879096 # number of overall misses 2758system.l2c.UpgradeReq_miss_latency::cpu0.data 125369500 # number of UpgradeReq miss cycles 2759system.l2c.UpgradeReq_miss_latency::cpu1.data 122687000 # number of UpgradeReq miss cycles 2760system.l2c.UpgradeReq_miss_latency::total 248056500 # number of UpgradeReq miss cycles 2761system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8279000 # number of SCUpgradeReq miss cycles 2762system.l2c.SCUpgradeReq_miss_latency::cpu1.data 9419500 # number of SCUpgradeReq miss cycles 2763system.l2c.SCUpgradeReq_miss_latency::total 17698500 # number of SCUpgradeReq miss cycles 2764system.l2c.ReadExReq_miss_latency::cpu0.data 8192378000 # number of ReadExReq miss cycles 2765system.l2c.ReadExReq_miss_latency::cpu1.data 5499536500 # number of ReadExReq miss cycles 2766system.l2c.ReadExReq_miss_latency::total 13691914500 # number of ReadExReq miss cycles 2767system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 156458500 # number of ReadSharedReq miss cycles 2768system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 155995000 # number of ReadSharedReq miss cycles 2769system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5894542000 # number of ReadSharedReq miss cycles 2770system.l2c.ReadSharedReq_miss_latency::cpu0.data 15712860500 # number of ReadSharedReq miss cycles 2771system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of ReadSharedReq miss cycles 2772system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 215561000 # number of ReadSharedReq miss cycles 2773system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 217319500 # number of ReadSharedReq miss cycles 2774system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4715127500 # number of ReadSharedReq miss cycles 2775system.l2c.ReadSharedReq_miss_latency::cpu1.data 11789045500 # number of ReadSharedReq miss cycles 2776system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of ReadSharedReq miss cycles 2777system.l2c.ReadSharedReq_miss_latency::total 93763070682 # number of ReadSharedReq miss cycles 2778system.l2c.demand_miss_latency::cpu0.dtb.walker 156458500 # number of demand (read+write) miss cycles 2779system.l2c.demand_miss_latency::cpu0.itb.walker 155995000 # number of demand (read+write) miss cycles 2780system.l2c.demand_miss_latency::cpu0.inst 5894542000 # number of demand (read+write) miss cycles 2781system.l2c.demand_miss_latency::cpu0.data 23905238500 # number of demand (read+write) miss cycles 2782system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of demand (read+write) miss cycles 2783system.l2c.demand_miss_latency::cpu1.dtb.walker 215561000 # number of demand (read+write) miss cycles 2784system.l2c.demand_miss_latency::cpu1.itb.walker 217319500 # number of demand (read+write) miss cycles 2785system.l2c.demand_miss_latency::cpu1.inst 4715127500 # number of demand (read+write) miss cycles 2786system.l2c.demand_miss_latency::cpu1.data 17288582000 # number of demand (read+write) miss cycles 2787system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of demand (read+write) miss cycles 2788system.l2c.demand_miss_latency::total 107454985182 # number of demand (read+write) miss cycles 2789system.l2c.overall_miss_latency::cpu0.dtb.walker 156458500 # number of overall miss cycles 2790system.l2c.overall_miss_latency::cpu0.itb.walker 155995000 # number of overall miss cycles 2791system.l2c.overall_miss_latency::cpu0.inst 5894542000 # number of overall miss cycles 2792system.l2c.overall_miss_latency::cpu0.data 23905238500 # number of overall miss cycles 2793system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of overall miss cycles 2794system.l2c.overall_miss_latency::cpu1.dtb.walker 215561000 # number of overall miss cycles 2795system.l2c.overall_miss_latency::cpu1.itb.walker 217319500 # number of overall miss cycles 2796system.l2c.overall_miss_latency::cpu1.inst 4715127500 # number of overall miss cycles 2797system.l2c.overall_miss_latency::cpu1.data 17288582000 # number of overall miss cycles 2798system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of overall miss cycles 2799system.l2c.overall_miss_latency::total 107454985182 # number of overall miss cycles 2800system.l2c.WritebackDirty_accesses::writebacks 2588139 # number of WritebackDirty accesses(hits+misses) 2801system.l2c.WritebackDirty_accesses::total 2588139 # number of WritebackDirty accesses(hits+misses) 2802system.l2c.UpgradeReq_accesses::cpu0.data 198489 # number of UpgradeReq accesses(hits+misses) 2803system.l2c.UpgradeReq_accesses::cpu1.data 179174 # number of UpgradeReq accesses(hits+misses) 2804system.l2c.UpgradeReq_accesses::total 377663 # number of UpgradeReq accesses(hits+misses) 2805system.l2c.SCUpgradeReq_accesses::cpu0.data 48909 # number of SCUpgradeReq accesses(hits+misses) 2806system.l2c.SCUpgradeReq_accesses::cpu1.data 52688 # number of SCUpgradeReq accesses(hits+misses) 2807system.l2c.SCUpgradeReq_accesses::total 101597 # number of SCUpgradeReq accesses(hits+misses) 2808system.l2c.ReadExReq_accesses::cpu0.data 121260 # number of ReadExReq accesses(hits+misses) 2809system.l2c.ReadExReq_accesses::cpu1.data 111465 # number of ReadExReq accesses(hits+misses) 2810system.l2c.ReadExReq_accesses::total 232725 # number of ReadExReq accesses(hits+misses) 2811system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10441 # number of ReadSharedReq accesses(hits+misses) 2812system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5373 # number of ReadSharedReq accesses(hits+misses) 2813system.l2c.ReadSharedReq_accesses::cpu0.inst 442889 # number of ReadSharedReq accesses(hits+misses) 2814system.l2c.ReadSharedReq_accesses::cpu0.data 653959 # number of ReadSharedReq accesses(hits+misses) 2815system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 493649 # number of ReadSharedReq accesses(hits+misses) 2816system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 13577 # number of ReadSharedReq accesses(hits+misses) 2817system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7885 # number of ReadSharedReq accesses(hits+misses) 2818system.l2c.ReadSharedReq_accesses::cpu1.inst 463851 # number of ReadSharedReq accesses(hits+misses) 2819system.l2c.ReadSharedReq_accesses::cpu1.data 638020 # number of ReadSharedReq accesses(hits+misses) 2820system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 454055 # number of ReadSharedReq accesses(hits+misses) 2821system.l2c.ReadSharedReq_accesses::total 3183699 # number of ReadSharedReq accesses(hits+misses) 2822system.l2c.InvalidateReq_accesses::cpu0.data 544109 # number of InvalidateReq accesses(hits+misses) 2823system.l2c.InvalidateReq_accesses::cpu1.data 207407 # number of InvalidateReq accesses(hits+misses) 2824system.l2c.InvalidateReq_accesses::total 751516 # number of InvalidateReq accesses(hits+misses) 2825system.l2c.demand_accesses::cpu0.dtb.walker 10441 # number of demand (read+write) accesses 2826system.l2c.demand_accesses::cpu0.itb.walker 5373 # number of demand (read+write) accesses 2827system.l2c.demand_accesses::cpu0.inst 442889 # number of demand (read+write) accesses 2828system.l2c.demand_accesses::cpu0.data 775219 # number of demand (read+write) accesses 2829system.l2c.demand_accesses::cpu0.l2cache.prefetcher 493649 # number of demand (read+write) accesses 2830system.l2c.demand_accesses::cpu1.dtb.walker 13577 # number of demand (read+write) accesses 2831system.l2c.demand_accesses::cpu1.itb.walker 7885 # number of demand (read+write) accesses 2832system.l2c.demand_accesses::cpu1.inst 463851 # number of demand (read+write) accesses 2833system.l2c.demand_accesses::cpu1.data 749485 # number of demand (read+write) accesses 2834system.l2c.demand_accesses::cpu1.l2cache.prefetcher 454055 # number of demand (read+write) accesses 2835system.l2c.demand_accesses::total 3416424 # number of demand (read+write) accesses 2836system.l2c.overall_accesses::cpu0.dtb.walker 10441 # number of overall (read+write) accesses 2837system.l2c.overall_accesses::cpu0.itb.walker 5373 # number of overall (read+write) accesses 2838system.l2c.overall_accesses::cpu0.inst 442889 # number of overall (read+write) accesses 2839system.l2c.overall_accesses::cpu0.data 775219 # number of overall (read+write) accesses 2840system.l2c.overall_accesses::cpu0.l2cache.prefetcher 493649 # number of overall (read+write) accesses 2841system.l2c.overall_accesses::cpu1.dtb.walker 13577 # number of overall (read+write) accesses 2842system.l2c.overall_accesses::cpu1.itb.walker 7885 # number of overall (read+write) accesses 2843system.l2c.overall_accesses::cpu1.inst 463851 # number of overall (read+write) accesses 2844system.l2c.overall_accesses::cpu1.data 749485 # number of overall (read+write) accesses 2845system.l2c.overall_accesses::cpu1.l2cache.prefetcher 454055 # number of overall (read+write) accesses 2846system.l2c.overall_accesses::total 3416424 # number of overall (read+write) accesses 2847system.l2c.UpgradeReq_miss_rate::cpu0.data 0.109628 # miss rate for UpgradeReq accesses 2848system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129863 # miss rate for UpgradeReq accesses 2849system.l2c.UpgradeReq_miss_rate::total 0.119228 # miss rate for UpgradeReq accesses 2850system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018606 # miss rate for SCUpgradeReq accesses 2851system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012489 # miss rate for SCUpgradeReq accesses 2852system.l2c.SCUpgradeReq_miss_rate::total 0.015434 # miss rate for SCUpgradeReq accesses 2853system.l2c.ReadExReq_miss_rate::cpu0.data 0.624905 # miss rate for ReadExReq accesses 2854system.l2c.ReadExReq_miss_rate::cpu1.data 0.450366 # miss rate for ReadExReq accesses 2855system.l2c.ReadExReq_miss_rate::total 0.541308 # miss rate for ReadExReq accesses 2856system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for ReadSharedReq accesses 2857system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286991 # miss rate for ReadSharedReq accesses 2858system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.120109 # miss rate for ReadSharedReq accesses 2859system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218052 # miss rate for ReadSharedReq accesses 2860system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for ReadSharedReq accesses 2861system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for ReadSharedReq accesses 2862system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.266963 # miss rate for ReadSharedReq accesses 2863system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085381 # miss rate for ReadSharedReq accesses 2864system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.159290 # miss rate for ReadSharedReq accesses 2865system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for ReadSharedReq accesses 2866system.l2c.ReadSharedReq_miss_rate::total 0.236555 # miss rate for ReadSharedReq accesses 2867system.l2c.InvalidateReq_miss_rate::cpu0.data 0.793801 # miss rate for InvalidateReq accesses 2868system.l2c.InvalidateReq_miss_rate::cpu1.data 0.380093 # miss rate for InvalidateReq accesses 2869system.l2c.InvalidateReq_miss_rate::total 0.679624 # miss rate for InvalidateReq accesses 2870system.l2c.demand_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for demand accesses 2871system.l2c.demand_miss_rate::cpu0.itb.walker 0.286991 # miss rate for demand accesses 2872system.l2c.demand_miss_rate::cpu0.inst 0.120109 # miss rate for demand accesses 2873system.l2c.demand_miss_rate::cpu0.data 0.281692 # miss rate for demand accesses 2874system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for demand accesses 2875system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for demand accesses 2876system.l2c.demand_miss_rate::cpu1.itb.walker 0.266963 # miss rate for demand accesses 2877system.l2c.demand_miss_rate::cpu1.inst 0.085381 # miss rate for demand accesses 2878system.l2c.demand_miss_rate::cpu1.data 0.202579 # miss rate for demand accesses 2879system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for demand accesses 2880system.l2c.demand_miss_rate::total 0.257315 # miss rate for demand accesses 2881system.l2c.overall_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for overall accesses 2882system.l2c.overall_miss_rate::cpu0.itb.walker 0.286991 # miss rate for overall accesses 2883system.l2c.overall_miss_rate::cpu0.inst 0.120109 # miss rate for overall accesses 2884system.l2c.overall_miss_rate::cpu0.data 0.281692 # miss rate for overall accesses 2885system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for overall accesses 2886system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for overall accesses 2887system.l2c.overall_miss_rate::cpu1.itb.walker 0.266963 # miss rate for overall accesses 2888system.l2c.overall_miss_rate::cpu1.inst 0.085381 # miss rate for overall accesses 2889system.l2c.overall_miss_rate::cpu1.data 0.202579 # miss rate for overall accesses 2890system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for overall accesses 2891system.l2c.overall_miss_rate::total 0.257315 # miss rate for overall accesses 2892system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5761.465993 # average UpgradeReq miss latency 2893system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5272.778064 # average UpgradeReq miss latency 2894system.l2c.UpgradeReq_avg_miss_latency::total 5508.938882 # average UpgradeReq miss latency 2895system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9097.802198 # average SCUpgradeReq miss latency 2896system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14315.349544 # average SCUpgradeReq miss latency 2897system.l2c.SCUpgradeReq_avg_miss_latency::total 11287.308673 # average SCUpgradeReq miss latency 2898system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108113.096495 # average ReadExReq miss latency 2899system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109552.519920 # average ReadExReq miss latency 2900system.l2c.ReadExReq_avg_miss_latency::total 108686.690322 # average ReadExReq miss latency 2901system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average ReadSharedReq miss latency 2902system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 101164.072633 # average ReadSharedReq miss latency 2903system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110810.076135 # average ReadSharedReq miss latency 2904system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110190.680730 # average ReadSharedReq miss latency 2905system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average ReadSharedReq miss latency 2906system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average ReadSharedReq miss latency 2907system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103239.667458 # average ReadSharedReq miss latency 2908system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 119056.850318 # average ReadSharedReq miss latency 2909system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115999.660533 # average ReadSharedReq miss latency 2910system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average ReadSharedReq miss latency 2911system.l2c.ReadSharedReq_avg_miss_latency::total 124499.509616 # average ReadSharedReq miss latency 2912system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency 2913system.l2c.demand_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency 2914system.l2c.demand_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency 2915system.l2c.demand_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency 2916system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency 2917system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency 2918system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency 2919system.l2c.demand_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency 2920system.l2c.demand_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency 2921system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency 2922system.l2c.demand_avg_miss_latency::total 122233.504853 # average overall miss latency 2923system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency 2924system.l2c.overall_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency 2925system.l2c.overall_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency 2926system.l2c.overall_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency 2927system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency 2928system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency 2929system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency 2930system.l2c.overall_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency 2931system.l2c.overall_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency 2932system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency 2933system.l2c.overall_avg_miss_latency::total 122233.504853 # average overall miss latency 2934system.l2c.blocked_cycles::no_mshrs 213 # number of cycles access was blocked |
| 2962system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2935system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2963system.l2c.blocked::no_mshrs 16 # number of cycles access was blocked | 2936system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked |
| 2964system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 2937system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 2965system.l2c.avg_blocked_cycles::no_mshrs 21.250000 # average number of cycles each access was blocked | 2938system.l2c.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked |
| 2966system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2939system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2967system.l2c.writebacks::writebacks 1062552 # number of writebacks 2968system.l2c.writebacks::total 1062552 # number of writebacks 2969system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 178 # number of ReadSharedReq MSHR hits 2970system.l2c.ReadSharedReq_mshr_hits::cpu0.data 32 # number of ReadSharedReq MSHR hits 2971system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 123 # number of ReadSharedReq MSHR hits 2972system.l2c.ReadSharedReq_mshr_hits::cpu1.data 57 # number of ReadSharedReq MSHR hits 2973system.l2c.ReadSharedReq_mshr_hits::total 390 # number of ReadSharedReq MSHR hits 2974system.l2c.demand_mshr_hits::cpu0.inst 178 # number of demand (read+write) MSHR hits 2975system.l2c.demand_mshr_hits::cpu0.data 32 # number of demand (read+write) MSHR hits 2976system.l2c.demand_mshr_hits::cpu1.inst 123 # number of demand (read+write) MSHR hits 2977system.l2c.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits 2978system.l2c.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits 2979system.l2c.overall_mshr_hits::cpu0.inst 178 # number of overall MSHR hits 2980system.l2c.overall_mshr_hits::cpu0.data 32 # number of overall MSHR hits 2981system.l2c.overall_mshr_hits::cpu1.inst 123 # number of overall MSHR hits 2982system.l2c.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits 2983system.l2c.overall_mshr_hits::total 390 # number of overall MSHR hits 2984system.l2c.CleanEvict_mshr_misses::writebacks 55381 # number of CleanEvict MSHR misses 2985system.l2c.CleanEvict_mshr_misses::total 55381 # number of CleanEvict MSHR misses 2986system.l2c.UpgradeReq_mshr_misses::cpu0.data 24439 # number of UpgradeReq MSHR misses 2987system.l2c.UpgradeReq_mshr_misses::cpu1.data 23204 # number of UpgradeReq MSHR misses 2988system.l2c.UpgradeReq_mshr_misses::total 47643 # number of UpgradeReq MSHR misses 2989system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 628 # number of SCUpgradeReq MSHR misses 2990system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 554 # number of SCUpgradeReq MSHR misses 2991system.l2c.SCUpgradeReq_mshr_misses::total 1182 # number of SCUpgradeReq MSHR misses 2992system.l2c.ReadExReq_mshr_misses::cpu0.data 75730 # number of ReadExReq MSHR misses 2993system.l2c.ReadExReq_mshr_misses::cpu1.data 50449 # number of ReadExReq MSHR misses 2994system.l2c.ReadExReq_mshr_misses::total 126179 # number of ReadExReq MSHR misses 2995system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1681 # number of ReadSharedReq MSHR misses 2996system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1744 # number of ReadSharedReq MSHR misses 2997system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 48407 # number of ReadSharedReq MSHR misses 2998system.l2c.ReadSharedReq_mshr_misses::cpu0.data 141351 # number of ReadSharedReq MSHR misses 2999system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of ReadSharedReq MSHR misses 3000system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1909 # number of ReadSharedReq MSHR misses 3001system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1973 # number of ReadSharedReq MSHR misses 3002system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44557 # number of ReadSharedReq MSHR misses 3003system.l2c.ReadSharedReq_mshr_misses::cpu1.data 100548 # number of ReadSharedReq MSHR misses 3004system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq MSHR misses 3005system.l2c.ReadSharedReq_mshr_misses::total 752735 # number of ReadSharedReq MSHR misses 3006system.l2c.InvalidateReq_mshr_misses::cpu0.data 440725 # number of InvalidateReq MSHR misses 3007system.l2c.InvalidateReq_mshr_misses::cpu1.data 106525 # number of InvalidateReq MSHR misses 3008system.l2c.InvalidateReq_mshr_misses::total 547250 # number of InvalidateReq MSHR misses 3009system.l2c.demand_mshr_misses::cpu0.dtb.walker 1681 # number of demand (read+write) MSHR misses 3010system.l2c.demand_mshr_misses::cpu0.itb.walker 1744 # number of demand (read+write) MSHR misses 3011system.l2c.demand_mshr_misses::cpu0.inst 48407 # number of demand (read+write) MSHR misses 3012system.l2c.demand_mshr_misses::cpu0.data 217081 # number of demand (read+write) MSHR misses 3013system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) MSHR misses 3014system.l2c.demand_mshr_misses::cpu1.dtb.walker 1909 # number of demand (read+write) MSHR misses 3015system.l2c.demand_mshr_misses::cpu1.itb.walker 1973 # number of demand (read+write) MSHR misses 3016system.l2c.demand_mshr_misses::cpu1.inst 44557 # number of demand (read+write) MSHR misses 3017system.l2c.demand_mshr_misses::cpu1.data 150997 # number of demand (read+write) MSHR misses 3018system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of demand (read+write) MSHR misses 3019system.l2c.demand_mshr_misses::total 878914 # number of demand (read+write) MSHR misses 3020system.l2c.overall_mshr_misses::cpu0.dtb.walker 1681 # number of overall MSHR misses 3021system.l2c.overall_mshr_misses::cpu0.itb.walker 1744 # number of overall MSHR misses 3022system.l2c.overall_mshr_misses::cpu0.inst 48407 # number of overall MSHR misses 3023system.l2c.overall_mshr_misses::cpu0.data 217081 # number of overall MSHR misses 3024system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of overall MSHR misses 3025system.l2c.overall_mshr_misses::cpu1.dtb.walker 1909 # number of overall MSHR misses 3026system.l2c.overall_mshr_misses::cpu1.itb.walker 1973 # number of overall MSHR misses 3027system.l2c.overall_mshr_misses::cpu1.inst 44557 # number of overall MSHR misses 3028system.l2c.overall_mshr_misses::cpu1.data 150997 # number of overall MSHR misses 3029system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of overall MSHR misses 3030system.l2c.overall_mshr_misses::total 878914 # number of overall MSHR misses | 2940system.l2c.writebacks::writebacks 1061178 # number of writebacks 2941system.l2c.writebacks::total 1061178 # number of writebacks 2942system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 79 # number of ReadSharedReq MSHR hits 2943system.l2c.ReadSharedReq_mshr_hits::cpu0.data 77 # number of ReadSharedReq MSHR hits 2944system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 76 # number of ReadSharedReq MSHR hits 2945system.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits 2946system.l2c.ReadSharedReq_mshr_hits::total 269 # number of ReadSharedReq MSHR hits 2947system.l2c.demand_mshr_hits::cpu0.inst 79 # number of demand (read+write) MSHR hits 2948system.l2c.demand_mshr_hits::cpu0.data 77 # number of demand (read+write) MSHR hits 2949system.l2c.demand_mshr_hits::cpu1.inst 76 # number of demand (read+write) MSHR hits 2950system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits 2951system.l2c.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits 2952system.l2c.overall_mshr_hits::cpu0.inst 79 # number of overall MSHR hits 2953system.l2c.overall_mshr_hits::cpu0.data 77 # number of overall MSHR hits 2954system.l2c.overall_mshr_hits::cpu1.inst 76 # number of overall MSHR hits 2955system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits 2956system.l2c.overall_mshr_hits::total 269 # number of overall MSHR hits 2957system.l2c.CleanEvict_mshr_misses::writebacks 55507 # number of CleanEvict MSHR misses 2958system.l2c.CleanEvict_mshr_misses::total 55507 # number of CleanEvict MSHR misses 2959system.l2c.UpgradeReq_mshr_misses::cpu0.data 21760 # number of UpgradeReq MSHR misses 2960system.l2c.UpgradeReq_mshr_misses::cpu1.data 23268 # number of UpgradeReq MSHR misses 2961system.l2c.UpgradeReq_mshr_misses::total 45028 # number of UpgradeReq MSHR misses 2962system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 910 # number of SCUpgradeReq MSHR misses 2963system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 658 # number of SCUpgradeReq MSHR misses 2964system.l2c.SCUpgradeReq_mshr_misses::total 1568 # number of SCUpgradeReq MSHR misses 2965system.l2c.ReadExReq_mshr_misses::cpu0.data 75776 # number of ReadExReq MSHR misses 2966system.l2c.ReadExReq_mshr_misses::cpu1.data 50200 # number of ReadExReq MSHR misses 2967system.l2c.ReadExReq_mshr_misses::total 125976 # number of ReadExReq MSHR misses 2968system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq MSHR misses 2969system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1542 # number of ReadSharedReq MSHR misses 2970system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 53116 # number of ReadSharedReq MSHR misses 2971system.l2c.ReadSharedReq_mshr_misses::cpu0.data 142520 # number of ReadSharedReq MSHR misses 2972system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq MSHR misses 2973system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq MSHR misses 2974system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2105 # number of ReadSharedReq MSHR misses 2975system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39528 # number of ReadSharedReq MSHR misses 2976system.l2c.ReadSharedReq_mshr_misses::cpu1.data 101593 # number of ReadSharedReq MSHR misses 2977system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq MSHR misses 2978system.l2c.ReadSharedReq_mshr_misses::total 752851 # number of ReadSharedReq MSHR misses 2979system.l2c.InvalidateReq_mshr_misses::cpu0.data 431914 # number of InvalidateReq MSHR misses 2980system.l2c.InvalidateReq_mshr_misses::cpu1.data 78834 # number of InvalidateReq MSHR misses 2981system.l2c.InvalidateReq_mshr_misses::total 510748 # number of InvalidateReq MSHR misses 2982system.l2c.demand_mshr_misses::cpu0.dtb.walker 1546 # number of demand (read+write) MSHR misses 2983system.l2c.demand_mshr_misses::cpu0.itb.walker 1542 # number of demand (read+write) MSHR misses 2984system.l2c.demand_mshr_misses::cpu0.inst 53116 # number of demand (read+write) MSHR misses 2985system.l2c.demand_mshr_misses::cpu0.data 218296 # number of demand (read+write) MSHR misses 2986system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) MSHR misses 2987system.l2c.demand_mshr_misses::cpu1.dtb.walker 2105 # number of demand (read+write) MSHR misses 2988system.l2c.demand_mshr_misses::cpu1.itb.walker 2105 # number of demand (read+write) MSHR misses 2989system.l2c.demand_mshr_misses::cpu1.inst 39528 # number of demand (read+write) MSHR misses 2990system.l2c.demand_mshr_misses::cpu1.data 151793 # number of demand (read+write) MSHR misses 2991system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) MSHR misses 2992system.l2c.demand_mshr_misses::total 878827 # number of demand (read+write) MSHR misses 2993system.l2c.overall_mshr_misses::cpu0.dtb.walker 1546 # number of overall MSHR misses 2994system.l2c.overall_mshr_misses::cpu0.itb.walker 1542 # number of overall MSHR misses 2995system.l2c.overall_mshr_misses::cpu0.inst 53116 # number of overall MSHR misses 2996system.l2c.overall_mshr_misses::cpu0.data 218296 # number of overall MSHR misses 2997system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of overall MSHR misses 2998system.l2c.overall_mshr_misses::cpu1.dtb.walker 2105 # number of overall MSHR misses 2999system.l2c.overall_mshr_misses::cpu1.itb.walker 2105 # number of overall MSHR misses 3000system.l2c.overall_mshr_misses::cpu1.inst 39528 # number of overall MSHR misses 3001system.l2c.overall_mshr_misses::cpu1.data 151793 # number of overall MSHR misses 3002system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of overall MSHR misses 3003system.l2c.overall_mshr_misses::total 878827 # number of overall MSHR misses |
| 3031system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable | 3004system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable |
| 3032system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable | 3005system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable |
| 3033system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable | 3006system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable |
| 3034system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22201 # number of ReadReq MSHR uncacheable 3035system.l2c.ReadReq_mshr_uncacheable::total 81817 # number of ReadReq MSHR uncacheable 3036system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 3037system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 3038system.l2c.WriteReq_mshr_uncacheable::total 38449 # number of WriteReq MSHR uncacheable | 3007system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8722 # number of ReadReq MSHR uncacheable 3008system.l2c.ReadReq_mshr_uncacheable::total 81785 # number of ReadReq MSHR uncacheable 3009system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable 3010system.l2c.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable 3011system.l2c.WriteReq_mshr_uncacheable::total 38414 # number of WriteReq MSHR uncacheable |
| 3039system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses | 3012system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses |
| 3040system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses | 3013system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses |
| 3041system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses | 3014system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses |
| 3042system.l2c.overall_mshr_uncacheable_misses::cpu1.data 42956 # number of overall MSHR uncacheable misses 3043system.l2c.overall_mshr_uncacheable_misses::total 120266 # number of overall MSHR uncacheable misses 3044system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 494587500 # number of UpgradeReq MSHR miss cycles 3045system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 479394000 # number of UpgradeReq MSHR miss cycles 3046system.l2c.UpgradeReq_mshr_miss_latency::total 973981500 # number of UpgradeReq MSHR miss cycles 3047system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15163500 # number of SCUpgradeReq MSHR miss cycles 3048system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13789000 # number of SCUpgradeReq MSHR miss cycles 3049system.l2c.SCUpgradeReq_mshr_miss_latency::total 28952500 # number of SCUpgradeReq MSHR miss cycles 3050system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7461135548 # number of ReadExReq MSHR miss cycles 3051system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5015765562 # number of ReadExReq MSHR miss cycles 3052system.l2c.ReadExReq_mshr_miss_latency::total 12476901110 # number of ReadExReq MSHR miss cycles 3053system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of ReadSharedReq MSHR miss cycles 3054system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 163078500 # number of ReadSharedReq MSHR miss cycles 3055system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5057062528 # number of ReadSharedReq MSHR miss cycles 3056system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14070826165 # number of ReadSharedReq MSHR miss cycles 3057system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of ReadSharedReq MSHR miss cycles 3058system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of ReadSharedReq MSHR miss cycles 3059system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 191021503 # number of ReadSharedReq MSHR miss cycles 3060system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4714685544 # number of ReadSharedReq MSHR miss cycles 3061system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10733108269 # number of ReadSharedReq MSHR miss cycles 3062system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of ReadSharedReq MSHR miss cycles 3063system.l2c.ReadSharedReq_mshr_miss_latency::total 86101249279 # number of ReadSharedReq MSHR miss cycles 3064system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8759971500 # number of InvalidateReq MSHR miss cycles 3065system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2141412000 # number of InvalidateReq MSHR miss cycles 3066system.l2c.InvalidateReq_mshr_miss_latency::total 10901383500 # number of InvalidateReq MSHR miss cycles 3067system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of demand (read+write) MSHR miss cycles 3068system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 163078500 # number of demand (read+write) MSHR miss cycles 3069system.l2c.demand_mshr_miss_latency::cpu0.inst 5057062528 # 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number of overall MSHR miss cycles | 3015system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17777 # number of overall MSHR uncacheable misses 3016system.l2c.overall_mshr_uncacheable_misses::total 120199 # number of overall MSHR uncacheable misses 3017system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 441512500 # number of UpgradeReq MSHR miss cycles 3018system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483331000 # number of UpgradeReq MSHR miss cycles 3019system.l2c.UpgradeReq_mshr_miss_latency::total 924843500 # number of UpgradeReq MSHR miss cycles 3020system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22384000 # number of SCUpgradeReq MSHR miss cycles 3021system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16407000 # number of SCUpgradeReq MSHR miss cycles 3022system.l2c.SCUpgradeReq_mshr_miss_latency::total 38791000 # number of SCUpgradeReq MSHR miss cycles 3023system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7434596046 # number of ReadExReq MSHR miss cycles 3024system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4997490093 # 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number of ReadSharedReq MSHR miss cycles 3034system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10767710172 # number of ReadSharedReq MSHR miss cycles 3035system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of ReadSharedReq MSHR miss cycles 3036system.l2c.ReadSharedReq_mshr_miss_latency::total 86205092450 # number of ReadSharedReq MSHR miss cycles 3037system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8509679500 # number of InvalidateReq MSHR miss cycles 3038system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1503443500 # number of InvalidateReq MSHR miss cycles 3039system.l2c.InvalidateReq_mshr_miss_latency::total 10013123000 # number of InvalidateReq MSHR miss cycles 3040system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of demand (read+write) MSHR miss cycles 3041system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140574501 # number of demand (read+write) MSHR miss cycles 3042system.l2c.demand_mshr_miss_latency::cpu0.inst 5355219542 # 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number of overall MSHR miss cycles 3052system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140574501 # number of overall MSHR miss cycles 3053system.l2c.overall_mshr_miss_latency::cpu0.inst 5355219542 # number of overall MSHR miss cycles 3054system.l2c.overall_mshr_miss_latency::cpu0.data 21714443231 # number of overall MSHR miss cycles 3055system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of overall MSHR miss cycles 3056system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of overall MSHR miss cycles 3057system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 196268502 # number of overall MSHR miss cycles 3058system.l2c.overall_mshr_miss_latency::cpu1.inst 4312153532 # number of overall MSHR miss cycles 3059system.l2c.overall_mshr_miss_latency::cpu1.data 15765200265 # number of overall MSHR miss cycles 3060system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of overall MSHR miss cycles 3061system.l2c.overall_mshr_miss_latency::total 98637178589 # number of overall MSHR miss cycles |
| 3089system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles | 3062system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles |
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| 3094system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles | 3067system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles |
| 3095system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2614209002 # number of overall MSHR uncacheable cycles 3096system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7665500 # number of overall MSHR uncacheable cycles 3097system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3345576000 # number of overall MSHR uncacheable cycles 3098system.l2c.overall_mshr_uncacheable_latency::total 8984296502 # number of overall MSHR uncacheable cycles | 3068system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4911881502 # number of overall MSHR uncacheable cycles 3069system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 8111000 # number of overall MSHR uncacheable cycles 3070system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1045413500 # number of overall MSHR uncacheable cycles 3071system.l2c.overall_mshr_uncacheable_latency::total 8982252002 # number of overall MSHR uncacheable cycles |
| 3099system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3100system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 3072system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3073system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 3101system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.113100 # mshr miss rate for UpgradeReq accesses 3102system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.123828 # mshr miss rate for UpgradeReq accesses 3103system.l2c.UpgradeReq_mshr_miss_rate::total 0.118083 # mshr miss rate for UpgradeReq accesses 3104system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012676 # mshr miss rate for SCUpgradeReq accesses 3105system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011369 # mshr miss rate for SCUpgradeReq accesses 3106system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.012028 # mshr miss rate for SCUpgradeReq accesses 3107system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.613362 # mshr miss rate for ReadExReq accesses 3108system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462767 # mshr miss rate for ReadExReq accesses 3109system.l2c.ReadExReq_mshr_miss_rate::total 0.542745 # mshr miss rate for ReadExReq accesses 3110system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for ReadSharedReq accesses 3111system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for ReadSharedReq accesses 3112system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for ReadSharedReq accesses 3113system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208316 # mshr miss rate for ReadSharedReq accesses 3114system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for ReadSharedReq accesses 3115system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for ReadSharedReq accesses 3116system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for ReadSharedReq accesses 3117system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for ReadSharedReq accesses 3118system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.161585 # mshr miss rate for ReadSharedReq accesses 3119system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for ReadSharedReq accesses 3120system.l2c.ReadSharedReq_mshr_miss_rate::total 0.235132 # mshr miss rate for ReadSharedReq accesses 3121system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779663 # mshr miss rate for InvalidateReq accesses 3122system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.455362 # mshr miss rate for InvalidateReq accesses 3123system.l2c.InvalidateReq_mshr_miss_rate::total 0.684738 # mshr miss rate for InvalidateReq accesses 3124system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for demand accesses 3125system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for demand accesses 3126system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for demand accesses 3127system.l2c.demand_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for demand accesses 3128system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for demand accesses 3129system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for demand accesses 3130system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for demand accesses 3131system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for demand accesses 3132system.l2c.demand_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for demand accesses 3133system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for demand accesses 3134system.l2c.demand_mshr_miss_rate::total 0.255958 # mshr miss rate for demand accesses 3135system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for overall accesses 3136system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for overall accesses 3137system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for overall accesses 3138system.l2c.overall_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for overall accesses 3139system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for overall accesses 3140system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for overall accesses 3141system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for overall accesses 3142system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for overall accesses 3143system.l2c.overall_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for overall accesses 3144system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for overall accesses 3145system.l2c.overall_mshr_miss_rate::total 0.255958 # mshr miss rate for overall accesses 3146system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20237.632473 # average UpgradeReq mshr miss latency 3147system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20659.972419 # average UpgradeReq mshr miss latency 3148system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20443.328506 # average UpgradeReq mshr miss latency 3149system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24145.700637 # average SCUpgradeReq mshr miss latency 3150system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24889.891697 # average SCUpgradeReq mshr miss latency 3151system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24494.500846 # average SCUpgradeReq mshr miss latency 3152system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98522.851552 # average ReadExReq mshr miss latency 3153system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99422.497215 # average ReadExReq mshr miss latency 3154system.l2c.ReadExReq_avg_mshr_miss_latency::total 98882.548681 # average ReadExReq mshr miss latency 3155system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average ReadSharedReq mshr miss latency 3156system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average ReadSharedReq mshr miss latency 3157system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average ReadSharedReq mshr miss latency 3158system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99545.289138 # average ReadSharedReq mshr miss latency 3159system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average ReadSharedReq mshr miss latency 3160system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average ReadSharedReq mshr miss latency 3161system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average ReadSharedReq mshr miss latency 3162system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average ReadSharedReq mshr miss latency 3163system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106746.113985 # average ReadSharedReq mshr miss latency 3164system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average ReadSharedReq mshr miss latency 3165system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114384.543404 # average ReadSharedReq mshr miss latency 3166system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19876.275455 # average InvalidateReq mshr miss latency 3167system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20102.436048 # average InvalidateReq mshr miss latency 3168system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19920.298767 # average InvalidateReq mshr miss latency 3169system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency 3170system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency 3171system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency 3172system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency 3173system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency 3174system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency 3175system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency 3176system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency 3177system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency 3178system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency 3179system.l2c.demand_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency 3180system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency 3181system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency 3182system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency 3183system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency 3184system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency 3185system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency 3186system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency 3187system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency 3188system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency 3189system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency 3190system.l2c.overall_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency | 3074system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.109628 # mshr miss rate for UpgradeReq accesses 3075system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129863 # mshr miss rate for UpgradeReq accesses 3076system.l2c.UpgradeReq_mshr_miss_rate::total 0.119228 # mshr miss rate for UpgradeReq accesses 3077system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018606 # mshr miss rate for SCUpgradeReq accesses 3078system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012489 # mshr miss rate for SCUpgradeReq accesses 3079system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015434 # mshr miss rate for SCUpgradeReq accesses 3080system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.624905 # mshr miss rate for ReadExReq accesses 3081system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.450366 # mshr miss rate for ReadExReq accesses 3082system.l2c.ReadExReq_mshr_miss_rate::total 0.541308 # mshr miss rate for ReadExReq accesses 3083system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for ReadSharedReq accesses 3084system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for ReadSharedReq accesses 3085system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for ReadSharedReq accesses 3086system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.217934 # mshr miss rate for ReadSharedReq accesses 3087system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for ReadSharedReq accesses 3088system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for ReadSharedReq accesses 3089system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for ReadSharedReq accesses 3090system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for ReadSharedReq accesses 3091system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159232 # mshr miss rate for ReadSharedReq accesses 3092system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for ReadSharedReq accesses 3093system.l2c.ReadSharedReq_mshr_miss_rate::total 0.236471 # mshr miss rate for ReadSharedReq accesses 3094system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.793801 # mshr miss rate for InvalidateReq accesses 3095system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.380093 # mshr miss rate for InvalidateReq accesses 3096system.l2c.InvalidateReq_mshr_miss_rate::total 0.679624 # mshr miss rate for InvalidateReq accesses 3097system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for demand accesses 3098system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for demand accesses 3099system.l2c.demand_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for demand accesses 3100system.l2c.demand_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for demand accesses 3101system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for demand accesses 3102system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for demand accesses 3103system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for demand accesses 3104system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for demand accesses 3105system.l2c.demand_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for demand accesses 3106system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for demand accesses 3107system.l2c.demand_mshr_miss_rate::total 0.257236 # mshr miss rate for demand accesses 3108system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for overall accesses 3109system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for overall accesses 3110system.l2c.overall_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for overall accesses 3111system.l2c.overall_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for overall accesses 3112system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for overall accesses 3113system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for overall accesses 3114system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for overall accesses 3115system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for overall accesses 3116system.l2c.overall_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for overall accesses 3117system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for overall accesses 3118system.l2c.overall_mshr_miss_rate::total 0.257236 # mshr miss rate for overall accesses 3119system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20290.096507 # average UpgradeReq mshr miss latency 3120system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20772.348289 # average UpgradeReq mshr miss latency 3121system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20539.297770 # average UpgradeReq mshr miss latency 3122system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.802198 # average SCUpgradeReq mshr miss latency 3123system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24934.650456 # average SCUpgradeReq mshr miss latency 3124system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24739.158163 # average SCUpgradeReq mshr miss latency 3125system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98112.806773 # average ReadExReq mshr miss latency 3126system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99551.595478 # average ReadExReq mshr miss latency 3127system.l2c.ReadExReq_avg_mshr_miss_latency::total 98686.147671 # average ReadExReq mshr miss latency 3128system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average ReadSharedReq mshr miss latency 3129system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average ReadSharedReq mshr miss latency 3130system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average ReadSharedReq mshr miss latency 3131system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100195.391419 # average ReadSharedReq mshr miss latency 3132system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average ReadSharedReq mshr miss latency 3133system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average ReadSharedReq mshr miss latency 3134system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average ReadSharedReq mshr miss latency 3135system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average ReadSharedReq mshr miss latency 3136system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105988.701702 # average ReadSharedReq mshr miss latency 3137system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average ReadSharedReq mshr miss latency 3138system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114504.852155 # average ReadSharedReq mshr miss latency 3139system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19702.254384 # average InvalidateReq mshr miss latency 3140system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19071.003628 # average InvalidateReq mshr miss latency 3141system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19604.820773 # average InvalidateReq mshr miss latency 3142system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency 3143system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency 3144system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency 3145system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency 3146system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency 3147system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency 3148system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency 3149system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency 3150system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency 3151system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency 3152system.l2c.demand_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency 3153system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency 3154system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency 3155system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency 3156system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency 3157system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency 3158system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency 3159system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency 3160system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency 3161system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency 3162system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency 3163system.l2c.overall_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency |
| 3191system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency | 3164system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency |
| 3192system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320 # average ReadReq mshr uncacheable latency 3193system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average ReadReq mshr uncacheable latency 3194system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566 # average ReadReq mshr uncacheable latency 3195system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497 # average ReadReq mshr uncacheable latency | 3165system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency 3166system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency 3167system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency 3168system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency |
| 3196system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency | 3169system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency |
| 3197system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383 # average overall mshr uncacheable latency 3198system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average overall mshr uncacheable latency 3199system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062 # average overall mshr uncacheable latency 3200system.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659 # average overall mshr uncacheable latency 3201system.membus.snoop_filter.tot_requests 3576184 # Total number of requests made to the snoop filter. 3202system.membus.snoop_filter.hit_single_requests 2127782 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3203system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 3170system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency 3171system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency 3172system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency 3173system.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency 3174system.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter. 3175system.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3176system.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3204system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3205system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3206system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3177system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3178system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3179system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3207system.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3208system.membus.trans_dist::ReadReq 81817 # Transaction distribution 3209system.membus.trans_dist::ReadResp 843472 # Transaction distribution 3210system.membus.trans_dist::WriteReq 38449 # Transaction distribution 3211system.membus.trans_dist::WriteResp 38449 # Transaction distribution 3212system.membus.trans_dist::WritebackDirty 1169254 # Transaction distribution 3213system.membus.trans_dist::CleanEvict 223620 # Transaction distribution 3214system.membus.trans_dist::UpgradeReq 320332 # Transaction distribution 3215system.membus.trans_dist::SCUpgradeReq 305580 # Transaction distribution 3216system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 3217system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 3218system.membus.trans_dist::ReadExReq 143723 # Transaction distribution 3219system.membus.trans_dist::ReadExResp 125482 # Transaction distribution 3220system.membus.trans_dist::ReadSharedReq 761655 # Transaction distribution 3221system.membus.trans_dist::InvalidateReq 651499 # Transaction distribution 3222system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) | 3180system.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3181system.membus.trans_dist::ReadReq 81785 # Transaction distribution 3182system.membus.trans_dist::ReadResp 843578 # Transaction distribution 3183system.membus.trans_dist::WriteReq 38414 # Transaction distribution 3184system.membus.trans_dist::WriteResp 38414 # Transaction distribution 3185system.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution 3186system.membus.trans_dist::CleanEvict 225685 # Transaction distribution 3187system.membus.trans_dist::UpgradeReq 305919 # Transaction distribution 3188system.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution 3189system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3190system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3191system.membus.trans_dist::ReadExReq 142258 # Transaction distribution 3192system.membus.trans_dist::ReadExResp 125306 # Transaction distribution 3193system.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution 3194system.membus.trans_dist::InvalidateReq 628104 # Transaction distribution 3195system.membus.trans_dist::InvalidateResp 29933 # Transaction distribution 3196system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes) |
| 3223system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) | 3197system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) |
| 3224system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26178 # Packet count per connected master and slave (bytes) 3225system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4313500 # Packet count per connected master and slave (bytes) 3226system.membus.pkt_count_system.l2c.mem_side::total 4462434 # Packet count per connected master and slave (bytes) 3227system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238025 # Packet count per connected master and slave (bytes) 3228system.membus.pkt_count_system.iocache.mem_side::total 238025 # Packet count per connected master and slave (bytes) 3229system.membus.pkt_count::total 4700459 # Packet count per connected master and slave (bytes) 3230system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) | 3198system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes) 3199system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes) 3200system.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes) 3201system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes) 3202system.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes) 3203system.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes) 3204system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes) |
| 3231system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) | 3205system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) |
| 3232system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52356 # Cumulative packet size per connected master and slave (bytes) 3233system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124357036 # Cumulative packet size per connected master and slave (bytes) 3234system.membus.pkt_size_system.l2c.mem_side::total 124565390 # Cumulative packet size per connected master and slave (bytes) 3235system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261504 # Cumulative packet size per connected master and slave (bytes) 3236system.membus.pkt_size_system.iocache.mem_side::total 7261504 # Cumulative packet size per connected master and slave (bytes) 3237system.membus.pkt_size::total 131826894 # Cumulative packet size per connected master and slave (bytes) 3238system.membus.snoops 595046 # Total snoops (count) 3239system.membus.snoopTraffic 184128 # Total snoop traffic (bytes) 3240system.membus.snoop_fanout::samples 2303059 # Request fanout histogram 3241system.membus.snoop_fanout::mean 0.014256 # Request fanout histogram 3242system.membus.snoop_fanout::stdev 0.118544 # Request fanout histogram | 3206system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes) 3207system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes) 3208system.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes) 3209system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes) 3210system.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes) 3211system.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes) 3212system.membus.snoops 601899 # Total snoops (count) 3213system.membus.snoopTraffic 182272 # Total snoop traffic (bytes) 3214system.membus.snoop_fanout::samples 2241138 # Request fanout histogram 3215system.membus.snoop_fanout::mean 0.014818 # Request fanout histogram 3216system.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram |
| 3243system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3217system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3244system.membus.snoop_fanout::0 2270227 98.57% 98.57% # Request fanout histogram 3245system.membus.snoop_fanout::1 32832 1.43% 100.00% # Request fanout histogram | 3218system.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram 3219system.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram |
| 3246system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3247system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3248system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3249system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 3220system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3221system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3222system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3223system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 3250system.membus.snoop_fanout::total 2303059 # Request fanout histogram 3251system.membus.reqLayer0.occupancy 101257500 # Layer occupancy (ticks) | 3224system.membus.snoop_fanout::total 2241138 # Request fanout histogram 3225system.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks) |
| 3252system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3226system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3253system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) | 3227system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) |
| 3254system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 3228system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3255system.membus.reqLayer2.occupancy 21679000 # Layer occupancy (ticks) | 3229system.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks) |
| 3256system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 3230system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 3257system.membus.reqLayer5.occupancy 8033203938 # Layer occupancy (ticks) | 3231system.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks) |
| 3258system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 3232system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 3259system.membus.respLayer2.occupancy 4846349578 # Layer occupancy (ticks) | 3233system.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks) |
| 3260system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 3234system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 3261system.membus.respLayer3.occupancy 45469982 # Layer occupancy (ticks) | 3235system.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks) |
| 3262system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 3236system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3263system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3264system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3265system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3266system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3267system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3268system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3269system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 3237system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3238system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3239system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3240system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3241system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3242system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3243system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 3270system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3271system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3272system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3273system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3274system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3275system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 3244system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3245system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3246system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3247system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3248system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3249system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 3276system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3277system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 3250system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3251system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 3278system.realview.ethernet.txBytes 966 # Bytes Transmitted 3279system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3280system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3281system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3282system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3283system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3284system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3285system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 3312system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3313system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3314system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3315system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3316system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3317system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3318system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3319system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3252system.realview.ethernet.txBytes 966 # Bytes Transmitted 3253system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3254system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3255system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3256system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3257system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3258system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3259system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 3286system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3287system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3288system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3289system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3290system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3291system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3292system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3293system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3320system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3321system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3322system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3323system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3324system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3325system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3326system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states | 3294system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3295system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3296system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3297system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3298system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3299system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3300system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states |
| 3327system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3328system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3329system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3330system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3301system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3302system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3303system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3304system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3331system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3332system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3333system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3334system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3335system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3336system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3337system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3338system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3339system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3340system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3341system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3342system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3343system.toL2Bus.snoop_filter.tot_requests 10759482 # Total number of requests made to the snoop filter. 3344system.toL2Bus.snoop_filter.hit_single_requests 5851735 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3345system.toL2Bus.snoop_filter.hit_multi_requests 1766751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3346system.toL2Bus.snoop_filter.tot_snoops 181547 # Total number of snoops made to the snoop filter. 3347system.toL2Bus.snoop_filter.hit_single_snoops 166860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3348system.toL2Bus.snoop_filter.hit_multi_snoops 14687 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3349system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3350system.toL2Bus.trans_dist::ReadReq 81819 # Transaction distribution 3351system.toL2Bus.trans_dist::ReadResp 4062742 # Transaction distribution 3352system.toL2Bus.trans_dist::WriteReq 38449 # Transaction distribution 3353system.toL2Bus.trans_dist::WriteResp 38449 # Transaction distribution 3354system.toL2Bus.trans_dist::WritebackDirty 3651776 # Transaction distribution 3355system.toL2Bus.trans_dist::CleanEvict 2342209 # Transaction distribution 3356system.toL2Bus.trans_dist::UpgradeReq 672985 # Transaction distribution 3357system.toL2Bus.trans_dist::SCUpgradeReq 402667 # Transaction distribution 3358system.toL2Bus.trans_dist::UpgradeResp 1075652 # Transaction distribution 3359system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution 3360system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 3361system.toL2Bus.trans_dist::ReadExReq 288170 # Transaction distribution 3362system.toL2Bus.trans_dist::ReadExResp 288170 # Transaction distribution 3363system.toL2Bus.trans_dist::ReadSharedReq 3981632 # Transaction distribution 3364system.toL2Bus.trans_dist::InvalidateReq 828938 # Transaction distribution 3365system.toL2Bus.trans_dist::InvalidateResp 799211 # Transaction distribution 3366system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8607895 # Packet count per connected master and slave (bytes) 3367system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7128520 # Packet count per connected master and slave (bytes) 3368system.toL2Bus.pkt_count::total 15736415 # Packet count per connected master and slave (bytes) 3369system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 211923339 # Cumulative packet size per connected master and slave (bytes) 3370system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 174059331 # Cumulative packet size per connected master and slave (bytes) 3371system.toL2Bus.pkt_size::total 385982670 # Cumulative packet size per connected master and slave (bytes) 3372system.toL2Bus.snoops 2818319 # Total snoops (count) 3373system.toL2Bus.snoopTraffic 121467536 # Total snoop traffic (bytes) 3374system.toL2Bus.snoop_fanout::samples 7671705 # Request fanout histogram 3375system.toL2Bus.snoop_fanout::mean 0.367658 # Request fanout histogram 3376system.toL2Bus.snoop_fanout::stdev 0.486122 # Request fanout histogram | 3305system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3306system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3307system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3308system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3309system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3310system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3311system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3312system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3313system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3314system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3315system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3316system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3317system.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter. 3318system.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3319system.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3320system.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter. 3321system.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3322system.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3323system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states 3324system.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution 3325system.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution 3326system.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution 3327system.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution 3328system.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution 3329system.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution 3330system.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution 3331system.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution 3332system.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution 3333system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution 3334system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 3335system.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution 3336system.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution 3337system.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution 3338system.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution 3339system.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution 3340system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes) 3341system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes) 3342system.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes) 3343system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes) 3344system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes) 3345system.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes) 3346system.toL2Bus.snoops 2851175 # Total snoops (count) 3347system.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes) 3348system.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram 3349system.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram 3350system.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram |
| 3377system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3351system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3378system.toL2Bus.snoop_fanout::0 4865825 63.43% 63.43% # Request fanout histogram 3379system.toL2Bus.snoop_fanout::1 2791193 36.38% 99.81% # Request fanout histogram 3380system.toL2Bus.snoop_fanout::2 14687 0.19% 100.00% # Request fanout histogram | 3352system.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram 3353system.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram 3354system.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram |
| 3381system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3382system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3383system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3355system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3356system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3357system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3384system.toL2Bus.snoop_fanout::total 7671705 # Request fanout histogram 3385system.toL2Bus.reqLayer0.occupancy 8456586164 # Layer occupancy (ticks) | 3358system.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram 3359system.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks) |
| 3386system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3360system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3387system.toL2Bus.snoopLayer0.occupancy 2556167 # Layer occupancy (ticks) | 3361system.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks) |
| 3388system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3362system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3389system.toL2Bus.respLayer0.occupancy 3921212144 # Layer occupancy (ticks) | 3363system.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks) |
| 3390system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 3364system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3391system.toL2Bus.respLayer1.occupancy 3534160915 # Layer occupancy (ticks) | 3365system.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks) |
| 3392system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3393 3394---------- End Simulation Statistics ---------- | 3366system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3367 3368---------- End Simulation Statistics ---------- |