| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.522770 # Number of seconds simulated 4sim_ticks 47522770414500 # Number of ticks simulated 5final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.522770 # Number of seconds simulated 4sim_ticks 47522770414500 # Number of ticks simulated 5final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 967829 # Simulator instruction rate (inst/s) 8host_op_rate 1138446 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52174728436 # Simulator tick rate (ticks/s) 10host_mem_usage 796444 # Number of bytes of host memory used 11host_seconds 910.84 # Real time elapsed on the host | 7host_inst_rate 594104 # Simulator instruction rate (inst/s) 8host_op_rate 698838 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32027606991 # Simulator tick rate (ticks/s) 10host_mem_usage 752504 # Number of bytes of host memory used 11host_seconds 1483.81 # Real time elapsed on the host |
| 12sim_insts 881535802 # Number of instructions simulated 13sim_ops 1036940641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory --- 452 unchanged lines hidden (view full) --- 472system.cpu0.dtb.read_hits 86856517 # DTB read hits 473system.cpu0.dtb.read_misses 84644 # DTB read misses 474system.cpu0.dtb.write_hits 78666499 # DTB write hits 475system.cpu0.dtb.write_misses 26878 # DTB write misses 476system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 477system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 478system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 479system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 12sim_insts 881535802 # Number of instructions simulated 13sim_ops 1036940641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory --- 452 unchanged lines hidden (view full) --- 472system.cpu0.dtb.read_hits 86856517 # DTB read hits 473system.cpu0.dtb.read_misses 84644 # DTB read misses 474system.cpu0.dtb.write_hits 78666499 # DTB write hits 475system.cpu0.dtb.write_misses 26878 # DTB write misses 476system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 477system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 478system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 479system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 480system.cpu0.dtb.flush_entries 37476 # Number of entries that have been flushed from TLB | 480system.cpu0.dtb.flush_entries 37412 # Number of entries that have been flushed from TLB |
| 481system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 482system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch 483system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions 485system.cpu0.dtb.read_accesses 86941161 # DTB read accesses 486system.cpu0.dtb.write_accesses 78693377 # DTB write accesses 487system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 488system.cpu0.dtb.hits 165523016 # DTB hits --- 69 unchanged lines hidden (view full) --- 558system.cpu0.itb.read_hits 0 # DTB read hits 559system.cpu0.itb.read_misses 0 # DTB read misses 560system.cpu0.itb.write_hits 0 # DTB write hits 561system.cpu0.itb.write_misses 0 # DTB write misses 562system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 563system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 564system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 565system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 481system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 482system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch 483system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions 485system.cpu0.dtb.read_accesses 86941161 # DTB read accesses 486system.cpu0.dtb.write_accesses 78693377 # DTB write accesses 487system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 488system.cpu0.dtb.hits 165523016 # DTB hits --- 69 unchanged lines hidden (view full) --- 558system.cpu0.itb.read_hits 0 # DTB read hits 559system.cpu0.itb.read_misses 0 # DTB read misses 560system.cpu0.itb.write_hits 0 # DTB write hits 561system.cpu0.itb.write_misses 0 # DTB write misses 562system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 563system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 564system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 565system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 566system.cpu0.itb.flush_entries 26626 # Number of entries that have been flushed from TLB | 566system.cpu0.itb.flush_entries 26562 # Number of entries that have been flushed from TLB |
| 567system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 568system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 569system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 570system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 571system.cpu0.itb.read_accesses 0 # DTB read accesses 572system.cpu0.itb.write_accesses 0 # DTB write accesses 573system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses 574system.cpu0.itb.hits 461199865 # DTB hits --- 898 unchanged lines hidden (view full) --- 1473system.cpu1.dtb.read_hits 79229823 # DTB read hits 1474system.cpu1.dtb.read_misses 76992 # DTB read misses 1475system.cpu1.dtb.write_hits 72255246 # DTB write hits 1476system.cpu1.dtb.write_misses 28021 # DTB write misses 1477system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1478system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1479system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 1480system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 567system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 568system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 569system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 570system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 571system.cpu0.itb.read_accesses 0 # DTB read accesses 572system.cpu0.itb.write_accesses 0 # DTB write accesses 573system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses 574system.cpu0.itb.hits 461199865 # DTB hits --- 898 unchanged lines hidden (view full) --- 1473system.cpu1.dtb.read_hits 79229823 # DTB read hits 1474system.cpu1.dtb.read_misses 76992 # DTB read misses 1475system.cpu1.dtb.write_hits 72255246 # DTB write hits 1476system.cpu1.dtb.write_misses 28021 # DTB write misses 1477system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1478system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1479system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 1480system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 1481system.cpu1.dtb.flush_entries 37178 # Number of entries that have been flushed from TLB | 1481system.cpu1.dtb.flush_entries 37114 # Number of entries that have been flushed from TLB |
| 1482system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1483system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch 1484system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1485system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions 1486system.cpu1.dtb.read_accesses 79306815 # DTB read accesses 1487system.cpu1.dtb.write_accesses 72283267 # DTB write accesses 1488system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1489system.cpu1.dtb.hits 151485069 # DTB hits --- 75 unchanged lines hidden (view full) --- 1565system.cpu1.itb.read_hits 0 # DTB read hits 1566system.cpu1.itb.read_misses 0 # DTB read misses 1567system.cpu1.itb.write_hits 0 # DTB write hits 1568system.cpu1.itb.write_misses 0 # DTB write misses 1569system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1570system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1571system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 1572system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 1482system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1483system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch 1484system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1485system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions 1486system.cpu1.dtb.read_accesses 79306815 # DTB read accesses 1487system.cpu1.dtb.write_accesses 72283267 # DTB write accesses 1488system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1489system.cpu1.dtb.hits 151485069 # DTB hits --- 75 unchanged lines hidden (view full) --- 1565system.cpu1.itb.read_hits 0 # DTB read hits 1566system.cpu1.itb.read_misses 0 # DTB read misses 1567system.cpu1.itb.write_hits 0 # DTB write hits 1568system.cpu1.itb.write_misses 0 # DTB write misses 1569system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1570system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1571system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 1572system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 1573system.cpu1.itb.flush_entries 25875 # Number of entries that have been flushed from TLB | 1573system.cpu1.itb.flush_entries 25811 # Number of entries that have been flushed from TLB |
| 1574system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1575system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1576system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1577system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1578system.cpu1.itb.read_accesses 0 # DTB read accesses 1579system.cpu1.itb.write_accesses 0 # DTB write accesses 1580system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses 1581system.cpu1.itb.hits 420888418 # DTB hits --- 1797 unchanged lines hidden --- | 1574system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1575system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1576system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1577system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1578system.cpu1.itb.read_accesses 0 # DTB read accesses 1579system.cpu1.itb.write_accesses 0 # DTB write accesses 1580system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses 1581system.cpu1.itb.hits 420888418 # DTB hits --- 1797 unchanged lines hidden --- |