| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.522770 # Number of seconds simulated 4sim_ticks 47522770414500 # Number of ticks simulated 5final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.522770 # Number of seconds simulated 4sim_ticks 47522770414500 # Number of ticks simulated 5final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 771698 # Simulator instruction rate (inst/s) 8host_op_rate 907739 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41601502224 # Simulator tick rate (ticks/s) 10host_mem_usage 746908 # Number of bytes of host memory used 11host_seconds 1142.33 # Real time elapsed on the host | 7host_inst_rate 967829 # Simulator instruction rate (inst/s) 8host_op_rate 1138446 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52174728436 # Simulator tick rate (ticks/s) 10host_mem_usage 796444 # Number of bytes of host memory used 11host_seconds 910.84 # Real time elapsed on the host |
| 12sim_insts 881535802 # Number of instructions simulated 13sim_ops 1036940641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 881535802 # Number of instructions simulated 13sim_ops 1036940641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 13811400 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 14713664 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 137344 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 135424 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2499960 # Number of bytes read from this memory --- 323 unchanged lines hidden (view full) --- 347system.physmem_1.preBackEnergy 27465937231500 # Energy for precharge background per rank (pJ) 348system.physmem_1.totalEnergy 31777629038250 # Total energy per rank (pJ) 349system.physmem_1.averagePower 668.682174 # Core power per rank (mW) 350system.physmem_1.memoryStateTime::IDLE 45691606890492 # Time in different power states 351system.physmem_1.memoryStateTime::REF 1586889720000 # Time in different power states 352system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 353system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states 354system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 13811400 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 14713664 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 137344 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 135424 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2499960 # Number of bytes read from this memory --- 323 unchanged lines hidden (view full) --- 348system.physmem_1.preBackEnergy 27465937231500 # Energy for precharge background per rank (pJ) 349system.physmem_1.totalEnergy 31777629038250 # Total energy per rank (pJ) 350system.physmem_1.averagePower 668.682174 # Core power per rank (mW) 351system.physmem_1.memoryStateTime::IDLE 45691606890492 # Time in different power states 352system.physmem_1.memoryStateTime::REF 1586889720000 # Time in different power states 353system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 354system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states 355system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 356system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 355system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 362system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 373system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 378system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 379system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) | 357system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 360system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 362system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 363system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 364system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 375system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 378system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 379system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 381system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 382system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) |
| 383system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 384system.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 385system.bridge.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 381system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 382system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 383system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 384system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 385system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 386system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 387system.cpu_clk_domain.clock 500 # Clock period in ticks | 386system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 387system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 388system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 389system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 390system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 391system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 392system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 393system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 409system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 410system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 412system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 413system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 414system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 415system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 416system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 415system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 418system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 419system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 420system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 421system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 422system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 423system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 417system.cpu0.dtb.walker.walks 111522 # Table walker walks requested 418system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors 419system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate 420system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84023 # Level at which table walker walks with long descriptors terminate 421system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting 422system.cpu0.dtb.walker.walkWaitTime::samples 111498 # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::mean 0.224219 # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::stdev 74.869765 # Table walker wait (enqueue to first request) latency --- 51 unchanged lines hidden (view full) --- 476system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions 478system.cpu0.dtb.read_accesses 86941161 # DTB read accesses 479system.cpu0.dtb.write_accesses 78693377 # DTB write accesses 480system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 481system.cpu0.dtb.hits 165523016 # DTB hits 482system.cpu0.dtb.misses 111522 # DTB misses 483system.cpu0.dtb.accesses 165634538 # DTB accesses | 424system.cpu0.dtb.walker.walks 111522 # Table walker walks requested 425system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84023 # Level at which table walker walks with long descriptors terminate 428system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting 429system.cpu0.dtb.walker.walkWaitTime::samples 111498 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::mean 0.224219 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::stdev 74.869765 # Table walker wait (enqueue to first request) latency --- 51 unchanged lines hidden (view full) --- 483system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions 485system.cpu0.dtb.read_accesses 86941161 # DTB read accesses 486system.cpu0.dtb.write_accesses 78693377 # DTB write accesses 487system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 488system.cpu0.dtb.hits 165523016 # DTB hits 489system.cpu0.dtb.misses 111522 # DTB misses 490system.cpu0.dtb.accesses 165634538 # DTB accesses |
| 491system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 484system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 505system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 506system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 507system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 508system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 509system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 510system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 511system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 512system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 492system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 513system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 514system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 515system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 516system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 517system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 518system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 519system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 520system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 521system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 513system.cpu0.itb.walker.walks 57441 # Table walker walks requested 514system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors 515system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate 516system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51280 # Level at which table walker walks with long descriptors terminate 517system.cpu0.itb.walker.walkWaitTime::samples 57441 # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::0 57441 100.00% 100.00% # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::total 57441 # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkCompletionTime::samples 51913 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 560system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 561system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 562system.cpu0.itb.read_accesses 0 # DTB read accesses 563system.cpu0.itb.write_accesses 0 # DTB write accesses 564system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses 565system.cpu0.itb.hits 461199865 # DTB hits 566system.cpu0.itb.misses 57441 # DTB misses 567system.cpu0.itb.accesses 461257306 # DTB accesses | 522system.cpu0.itb.walker.walks 57441 # Table walker walks requested 523system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors 524system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate 525system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51280 # Level at which table walker walks with long descriptors terminate 526system.cpu0.itb.walker.walkWaitTime::samples 57441 # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::0 57441 100.00% 100.00% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::total 57441 # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkCompletionTime::samples 51913 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 569system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 570system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 571system.cpu0.itb.read_accesses 0 # DTB read accesses 572system.cpu0.itb.write_accesses 0 # DTB write accesses 573system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses 574system.cpu0.itb.hits 461199865 # DTB hits 575system.cpu0.itb.misses 57441 # DTB misses 576system.cpu0.itb.accesses 461257306 # DTB accesses |
| 577system.cpu0.numPwrStateTransitions 27854 # Number of power state transitions 578system.cpu0.pwrStateClkGateDist::samples 13927 # Distribution of time spent in the clock gated state 579system.cpu0.pwrStateClkGateDist::mean 3371332712.012135 # Distribution of time spent in the clock gated state 580system.cpu0.pwrStateClkGateDist::stdev 65010943687.031532 # Distribution of time spent in the clock gated state 581system.cpu0.pwrStateClkGateDist::underflows 3873 27.81% 27.81% # Distribution of time spent in the clock gated state 582system.cpu0.pwrStateClkGateDist::1000-5e+10 10023 71.97% 99.78% # Distribution of time spent in the clock gated state 583system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.80% # Distribution of time spent in the clock gated state 584system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state 585system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state 586system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 587system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state 588system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 589system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::overflows 18 0.13% 100.00% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::max_value 1988778348716 # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::total 13927 # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateResidencyTicks::ON 570219734307 # Cumulative time (in ticks) in various power states 597system.cpu0.pwrStateResidencyTicks::CLK_GATED 46952550680193 # Cumulative time (in ticks) in various power states |
|
| 568system.cpu0.numCycles 95045540829 # number of cpu cycles simulated 569system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 570system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 571system.cpu0.kern.inst.arm 0 # number of arm instructions executed 572system.cpu0.kern.inst.quiesce 13927 # number of quiesce instructions executed 573system.cpu0.committedInsts 460929213 # Number of instructions committed 574system.cpu0.committedOps 541179982 # Number of ops (including micro ops) committed 575system.cpu0.num_int_alu_accesses 497492129 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 622system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction 623system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction 624system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction 625system.cpu0.op_class::MemRead 86852092 16.04% 85.47% # Class of executed instruction 626system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Class of executed instruction 627system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 628system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 629system.cpu0.op_class::total 541493758 # Class of executed instruction | 598system.cpu0.numCycles 95045540829 # number of cpu cycles simulated 599system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 600system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 601system.cpu0.kern.inst.arm 0 # number of arm instructions executed 602system.cpu0.kern.inst.quiesce 13927 # number of quiesce instructions executed 603system.cpu0.committedInsts 460929213 # Number of instructions committed 604system.cpu0.committedOps 541179982 # Number of ops (including micro ops) committed 605system.cpu0.num_int_alu_accesses 497492129 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 652system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction 653system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction 654system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction 655system.cpu0.op_class::MemRead 86852092 16.04% 85.47% # Class of executed instruction 656system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Class of executed instruction 657system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 658system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 659system.cpu0.op_class::total 541493758 # Class of executed instruction |
| 660system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 630system.cpu0.dcache.tags.replacements 5689621 # number of replacements 631system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use 632system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks. 633system.cpu0.dcache.tags.sampled_refs 5690133 # Sample count of references to valid blocks. 634system.cpu0.dcache.tags.avg_refs 28.045414 # Average number of references to valid blocks. 635system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. 636system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.423656 # Average occupied blocks per requestor 637system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993015 # Average percentage of cache occupancy 638system.cpu0.dcache.tags.occ_percent::total 0.993015 # Average percentage of cache occupancy 639system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 640system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 641system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id 642system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id 643system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 644system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses 645system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses | 661system.cpu0.dcache.tags.replacements 5689621 # number of replacements 662system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use 663system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks. 664system.cpu0.dcache.tags.sampled_refs 5690133 # Sample count of references to valid blocks. 665system.cpu0.dcache.tags.avg_refs 28.045414 # Average number of references to valid blocks. 666system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. 667system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.423656 # Average occupied blocks per requestor 668system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993015 # Average percentage of cache occupancy 669system.cpu0.dcache.tags.occ_percent::total 0.993015 # Average percentage of cache occupancy 670system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 671system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 672system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id 673system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id 674system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 675system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses 676system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses |
| 677system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 646system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits 647system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits 648system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits 649system.cpu0.dcache.WriteReq_hits::total 74279623 # number of WriteReq hits 650system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199389 # number of SoftPFReq hits 651system.cpu0.dcache.SoftPFReq_hits::total 199389 # number of SoftPFReq hits 652system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162229 # number of WriteLineReq hits 653system.cpu0.dcache.WriteLineReq_hits::total 162229 # number of WriteLineReq hits --- 180 unchanged lines hidden (view full) --- 834system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187 # average overall mshr miss latency 835system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187 # average overall mshr miss latency 836system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072 # average overall mshr miss latency 837system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072 # average overall mshr miss latency 838system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 # average ReadReq mshr uncacheable latency 839system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency 840system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency 841system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency | 678system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits 679system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits 680system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits 681system.cpu0.dcache.WriteReq_hits::total 74279623 # number of WriteReq hits 682system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199389 # number of SoftPFReq hits 683system.cpu0.dcache.SoftPFReq_hits::total 199389 # number of SoftPFReq hits 684system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162229 # number of WriteLineReq hits 685system.cpu0.dcache.WriteLineReq_hits::total 162229 # number of WriteLineReq hits --- 180 unchanged lines hidden (view full) --- 866system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187 # average overall mshr miss latency 867system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187 # average overall mshr miss latency 868system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072 # average overall mshr miss latency 869system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072 # average overall mshr miss latency 870system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 # average ReadReq mshr uncacheable latency 871system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency 872system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency 873system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency |
| 874system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 842system.cpu0.icache.tags.replacements 5142905 # number of replacements 843system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use 844system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks. 845system.cpu0.icache.tags.sampled_refs 5143417 # Sample count of references to valid blocks. 846system.cpu0.icache.tags.avg_refs 88.667990 # Average number of references to valid blocks. 847system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. 848system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.908178 # Average occupied blocks per requestor 849system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999821 # Average percentage of cache occupancy 850system.cpu0.icache.tags.occ_percent::total 0.999821 # Average percentage of cache occupancy 851system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 852system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 853system.cpu0.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 854system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id 855system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 856system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 857system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses 858system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses | 875system.cpu0.icache.tags.replacements 5142905 # number of replacements 876system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use 877system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks. 878system.cpu0.icache.tags.sampled_refs 5143417 # Sample count of references to valid blocks. 879system.cpu0.icache.tags.avg_refs 88.667990 # Average number of references to valid blocks. 880system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. 881system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.908178 # Average occupied blocks per requestor 882system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999821 # Average percentage of cache occupancy 883system.cpu0.icache.tags.occ_percent::total 0.999821 # Average percentage of cache occupancy 884system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 885system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 886system.cpu0.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 887system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id 888system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 889system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 890system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses 891system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses |
| 892system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 859system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits 860system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits 861system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits 862system.cpu0.icache.demand_hits::total 456056448 # number of demand (read+write) hits 863system.cpu0.icache.overall_hits::cpu0.inst 456056448 # number of overall hits 864system.cpu0.icache.overall_hits::total 456056448 # number of overall hits 865system.cpu0.icache.ReadReq_misses::cpu0.inst 5143417 # number of ReadReq misses 866system.cpu0.icache.ReadReq_misses::total 5143417 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 931system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency 932system.cpu0.icache.demand_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency 933system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency 934system.cpu0.icache.overall_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency 935system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency 936system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency 937system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency 938system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency | 893system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits 894system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits 895system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits 896system.cpu0.icache.demand_hits::total 456056448 # number of demand (read+write) hits 897system.cpu0.icache.overall_hits::cpu0.inst 456056448 # number of overall hits 898system.cpu0.icache.overall_hits::total 456056448 # number of overall hits 899system.cpu0.icache.ReadReq_misses::cpu0.inst 5143417 # number of ReadReq misses 900system.cpu0.icache.ReadReq_misses::total 5143417 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 965system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency 966system.cpu0.icache.demand_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency 967system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency 968system.cpu0.icache.overall_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency 969system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency 970system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency 971system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency 972system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency |
| 973system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 939system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued 940system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified 941system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 942system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 943system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 944system.cpu0.l2cache.prefetcher.pfSpanPage 1013066 # number of prefetches not generated due to page crossing | 974system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued 975system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified 976system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 977system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 978system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 979system.cpu0.l2cache.prefetcher.pfSpanPage 1013066 # number of prefetches not generated due to page crossing |
| 980system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 945system.cpu0.l2cache.tags.replacements 2348165 # number of replacements 946system.cpu0.l2cache.tags.tagsinuse 16134.688776 # Cycle average of tags in use 947system.cpu0.l2cache.tags.total_refs 15333996 # Total number of references to valid blocks. 948system.cpu0.l2cache.tags.sampled_refs 2364235 # Sample count of references to valid blocks. 949system.cpu0.l2cache.tags.avg_refs 6.485817 # Average number of references to valid blocks. 950system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. 951system.cpu0.l2cache.tags.occ_blocks::writebacks 15208.455915 # Average occupied blocks per requestor 952system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.858641 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 972system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4517 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3841 # Occupied blocks per task id 975system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id 976system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 977system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id 978system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses 979system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses | 981system.cpu0.l2cache.tags.replacements 2348165 # number of replacements 982system.cpu0.l2cache.tags.tagsinuse 16134.688776 # Cycle average of tags in use 983system.cpu0.l2cache.tags.total_refs 15333996 # Total number of references to valid blocks. 984system.cpu0.l2cache.tags.sampled_refs 2364235 # Sample count of references to valid blocks. 985system.cpu0.l2cache.tags.avg_refs 6.485817 # Average number of references to valid blocks. 986system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. 987system.cpu0.l2cache.tags.occ_blocks::writebacks 15208.455915 # Average occupied blocks per requestor 988system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.858641 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 1008system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4517 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3841 # Occupied blocks per task id 1011system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id 1012system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 1013system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id 1014system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses 1015system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses |
| 1016system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 980system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits 981system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # number of ReadReq hits 982system.cpu0.l2cache.ReadReq_hits::total 411890 # number of ReadReq hits 983system.cpu0.l2cache.WritebackDirty_hits::writebacks 3764500 # number of WritebackDirty hits 984system.cpu0.l2cache.WritebackDirty_hits::total 3764500 # number of WritebackDirty hits 985system.cpu0.l2cache.WritebackClean_hits::writebacks 7067152 # number of WritebackClean hits 986system.cpu0.l2cache.WritebackClean_hits::total 7067152 # number of WritebackClean hits 987system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 393 # number of UpgradeReq hits --- 313 unchanged lines hidden (view full) --- 1301system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961 # average overall mshr uncacheable latency 1302system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516 # average overall mshr uncacheable latency 1303system.cpu0.toL2Bus.snoop_filter.tot_requests 22441141 # Total number of requests made to the snoop filter. 1304system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11511110 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1305system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1306system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter. 1307system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1308system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1017system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits 1018system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # number of ReadReq hits 1019system.cpu0.l2cache.ReadReq_hits::total 411890 # number of ReadReq hits 1020system.cpu0.l2cache.WritebackDirty_hits::writebacks 3764500 # number of WritebackDirty hits 1021system.cpu0.l2cache.WritebackDirty_hits::total 3764500 # number of WritebackDirty hits 1022system.cpu0.l2cache.WritebackClean_hits::writebacks 7067152 # number of WritebackClean hits 1023system.cpu0.l2cache.WritebackClean_hits::total 7067152 # number of WritebackClean hits 1024system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 393 # number of UpgradeReq hits --- 313 unchanged lines hidden (view full) --- 1338system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961 # average overall mshr uncacheable latency 1339system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516 # average overall mshr uncacheable latency 1340system.cpu0.toL2Bus.snoop_filter.tot_requests 22441141 # Total number of requests made to the snoop filter. 1341system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11511110 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1342system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1343system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter. 1344system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1345system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1346system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1309system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution 1310system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution 1311system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution 1312system.cpu0.toL2Bus.trans_dist::WriteResp 26565 # Transaction distribution 1313system.cpu0.toL2Bus.trans_dist::WritebackDirty 5274768 # Transaction distribution 1314system.cpu0.toL2Bus.trans_dist::WritebackClean 7068022 # Transaction distribution 1315system.cpu0.toL2Bus.trans_dist::CleanEvict 2298392 # Transaction distribution 1316system.cpu0.toL2Bus.trans_dist::HardPFReq 883953 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1354system.cpu0.toL2Bus.respLayer0.occupancy 7758250500 # Layer occupancy (ticks) 1355system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1356system.cpu0.toL2Bus.respLayer1.occupancy 8155256101 # Layer occupancy (ticks) 1357system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1358system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # Layer occupancy (ticks) 1359system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1360system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks) 1361system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1347system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution 1348system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution 1349system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution 1350system.cpu0.toL2Bus.trans_dist::WriteResp 26565 # Transaction distribution 1351system.cpu0.toL2Bus.trans_dist::WritebackDirty 5274768 # Transaction distribution 1352system.cpu0.toL2Bus.trans_dist::WritebackClean 7068022 # Transaction distribution 1353system.cpu0.toL2Bus.trans_dist::CleanEvict 2298392 # Transaction distribution 1354system.cpu0.toL2Bus.trans_dist::HardPFReq 883953 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1392system.cpu0.toL2Bus.respLayer0.occupancy 7758250500 # Layer occupancy (ticks) 1393system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1394system.cpu0.toL2Bus.respLayer1.occupancy 8155256101 # Layer occupancy (ticks) 1395system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1396system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # Layer occupancy (ticks) 1397system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1398system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks) 1399system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1400system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1362system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1363system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1364system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1365system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1366system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1367system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1368system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1369system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1383system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1384system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1385system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1386system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1387system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1388system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1389system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1390system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1401system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1402system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1403system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1404system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1405system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1406system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1407system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1408system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1422system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1423system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1424system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1425system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1426system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1427system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1428system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1429system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1430system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1391system.cpu1.dtb.walker.walks 105013 # Table walker walks requested 1392system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors 1393system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate 1394system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79078 # Level at which table walker walks with long descriptors terminate 1395system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting 1396system.cpu1.dtb.walker.walkWaitTime::samples 105006 # Table walker wait (enqueue to first request) latency 1397system.cpu1.dtb.walker.walkWaitTime::mean 0.076186 # Table walker wait (enqueue to first request) latency 1398system.cpu1.dtb.walker.walkWaitTime::stdev 24.687831 # Table walker wait (enqueue to first request) latency --- 45 unchanged lines hidden (view full) --- 1444system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1445system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions 1446system.cpu1.dtb.read_accesses 79306815 # DTB read accesses 1447system.cpu1.dtb.write_accesses 72283267 # DTB write accesses 1448system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1449system.cpu1.dtb.hits 151485069 # DTB hits 1450system.cpu1.dtb.misses 105013 # DTB misses 1451system.cpu1.dtb.accesses 151590082 # DTB accesses | 1431system.cpu1.dtb.walker.walks 105013 # Table walker walks requested 1432system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors 1433system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate 1434system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79078 # Level at which table walker walks with long descriptors terminate 1435system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting 1436system.cpu1.dtb.walker.walkWaitTime::samples 105006 # Table walker wait (enqueue to first request) latency 1437system.cpu1.dtb.walker.walkWaitTime::mean 0.076186 # Table walker wait (enqueue to first request) latency 1438system.cpu1.dtb.walker.walkWaitTime::stdev 24.687831 # Table walker wait (enqueue to first request) latency --- 45 unchanged lines hidden (view full) --- 1484system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1485system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions 1486system.cpu1.dtb.read_accesses 79306815 # DTB read accesses 1487system.cpu1.dtb.write_accesses 72283267 # DTB write accesses 1488system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1489system.cpu1.dtb.hits 151485069 # DTB hits 1490system.cpu1.dtb.misses 105013 # DTB misses 1491system.cpu1.dtb.accesses 151590082 # DTB accesses |
| 1492system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1452system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1453system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1454system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1455system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1456system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1457system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1458system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1459system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1473system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1474system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1475system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1476system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1477system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1478system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1479system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1480system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1493system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1494system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1495system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1496system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1497system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1498system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1499system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1500system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1514system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1515system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1516system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1517system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1518system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1519system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1520system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1521system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1522system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1481system.cpu1.itb.walker.walks 58945 # Table walker walks requested 1482system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors 1483system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate 1484system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53052 # Level at which table walker walks with long descriptors terminate 1485system.cpu1.itb.walker.walkWaitTime::samples 58945 # Table walker wait (enqueue to first request) latency 1486system.cpu1.itb.walker.walkWaitTime::0 58945 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1487system.cpu1.itb.walker.walkWaitTime::total 58945 # Table walker wait (enqueue to first request) latency 1488system.cpu1.itb.walker.walkCompletionTime::samples 53613 # Table walker service (enqueue to completion) latency --- 45 unchanged lines hidden (view full) --- 1534system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1535system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1536system.cpu1.itb.read_accesses 0 # DTB read accesses 1537system.cpu1.itb.write_accesses 0 # DTB write accesses 1538system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses 1539system.cpu1.itb.hits 420888418 # DTB hits 1540system.cpu1.itb.misses 58945 # DTB misses 1541system.cpu1.itb.accesses 420947363 # DTB accesses | 1523system.cpu1.itb.walker.walks 58945 # Table walker walks requested 1524system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors 1525system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate 1526system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53052 # Level at which table walker walks with long descriptors terminate 1527system.cpu1.itb.walker.walkWaitTime::samples 58945 # Table walker wait (enqueue to first request) latency 1528system.cpu1.itb.walker.walkWaitTime::0 58945 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1529system.cpu1.itb.walker.walkWaitTime::total 58945 # Table walker wait (enqueue to first request) latency 1530system.cpu1.itb.walker.walkCompletionTime::samples 53613 # Table walker service (enqueue to completion) latency --- 45 unchanged lines hidden (view full) --- 1576system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1577system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1578system.cpu1.itb.read_accesses 0 # DTB read accesses 1579system.cpu1.itb.write_accesses 0 # DTB write accesses 1580system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses 1581system.cpu1.itb.hits 420888418 # DTB hits 1582system.cpu1.itb.misses 58945 # DTB misses 1583system.cpu1.itb.accesses 420947363 # DTB accesses |
| 1584system.cpu1.numPwrStateTransitions 9975 # Number of power state transitions 1585system.cpu1.pwrStateClkGateDist::samples 4987 # Distribution of time spent in the clock gated state 1586system.cpu1.pwrStateClkGateDist::mean 9429340547.425106 # Distribution of time spent in the clock gated state 1587system.cpu1.pwrStateClkGateDist::stdev 186307084392.504211 # Distribution of time spent in the clock gated state 1588system.cpu1.pwrStateClkGateDist::underflows 3401 68.20% 68.20% # Distribution of time spent in the clock gated state 1589system.cpu1.pwrStateClkGateDist::1000-5e+10 1566 31.40% 99.60% # Distribution of time spent in the clock gated state 1590system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.74% # Distribution of time spent in the clock gated state 1591system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.78% # Distribution of time spent in the clock gated state 1592system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state 1593system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 1594system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state 1595system.cpu1.pwrStateClkGateDist::overflows 8 0.16% 100.00% # Distribution of time spent in the clock gated state 1596system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1597system.cpu1.pwrStateClkGateDist::max_value 7390880609428 # Distribution of time spent in the clock gated state 1598system.cpu1.pwrStateClkGateDist::total 4987 # Distribution of time spent in the clock gated state 1599system.cpu1.pwrStateResidencyTicks::ON 498649104491 # Cumulative time (in ticks) in various power states 1600system.cpu1.pwrStateResidencyTicks::CLK_GATED 47024121310009 # Cumulative time (in ticks) in various power states |
|
| 1542system.cpu1.numCycles 95045540824 # number of cpu cycles simulated 1543system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1544system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1545system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1546system.cpu1.kern.inst.quiesce 4988 # number of quiesce instructions executed 1547system.cpu1.committedInsts 420606589 # Number of instructions committed 1548system.cpu1.committedOps 495760659 # Number of ops (including micro ops) committed 1549system.cpu1.num_int_alu_accesses 455422102 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 1596system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction 1597system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction 1598system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction 1599system.cpu1.op_class::MemRead 79227868 15.97% 85.43% # Class of executed instruction 1600system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Class of executed instruction 1601system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1602system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1603system.cpu1.op_class::total 496042597 # Class of executed instruction | 1601system.cpu1.numCycles 95045540824 # number of cpu cycles simulated 1602system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1603system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1604system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1605system.cpu1.kern.inst.quiesce 4988 # number of quiesce instructions executed 1606system.cpu1.committedInsts 420606589 # Number of instructions committed 1607system.cpu1.committedOps 495760659 # Number of ops (including micro ops) committed 1608system.cpu1.num_int_alu_accesses 455422102 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 1655system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction 1656system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction 1657system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction 1658system.cpu1.op_class::MemRead 79227868 15.97% 85.43% # Class of executed instruction 1659system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Class of executed instruction 1660system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1661system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1662system.cpu1.op_class::total 496042597 # Class of executed instruction |
| 1663system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1604system.cpu1.dcache.tags.replacements 5018466 # number of replacements 1605system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use 1606system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks. 1607system.cpu1.dcache.tags.sampled_refs 5018977 # Sample count of references to valid blocks. 1608system.cpu1.dcache.tags.avg_refs 29.144932 # Average number of references to valid blocks. 1609system.cpu1.dcache.tags.warmup_cycle 8378732349000 # Cycle when the warmup percentage was hit. 1610system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.493139 # Average occupied blocks per requestor 1611system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848619 # Average percentage of cache occupancy 1612system.cpu1.dcache.tags.occ_percent::total 0.848619 # Average percentage of cache occupancy 1613system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1614system.cpu1.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 1615system.cpu1.dcache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 1616system.cpu1.dcache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id 1617system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1618system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1619system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses 1620system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses | 1664system.cpu1.dcache.tags.replacements 5018466 # number of replacements 1665system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use 1666system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks. 1667system.cpu1.dcache.tags.sampled_refs 5018977 # Sample count of references to valid blocks. 1668system.cpu1.dcache.tags.avg_refs 29.144932 # Average number of references to valid blocks. 1669system.cpu1.dcache.tags.warmup_cycle 8378732349000 # Cycle when the warmup percentage was hit. 1670system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.493139 # Average occupied blocks per requestor 1671system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848619 # Average percentage of cache occupancy 1672system.cpu1.dcache.tags.occ_percent::total 0.848619 # Average percentage of cache occupancy 1673system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1674system.cpu1.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 1675system.cpu1.dcache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 1676system.cpu1.dcache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id 1677system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1678system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1679system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses 1680system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses |
| 1681system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1621system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits 1622system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits 1623system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits 1624system.cpu1.dcache.WriteReq_hits::total 68485479 # number of WriteReq hits 1625system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174561 # number of SoftPFReq hits 1626system.cpu1.dcache.SoftPFReq_hits::total 174561 # number of SoftPFReq hits 1627system.cpu1.dcache.WriteLineReq_hits::cpu1.data 162110 # number of WriteLineReq hits 1628system.cpu1.dcache.WriteLineReq_hits::total 162110 # number of WriteLineReq hits --- 180 unchanged lines hidden (view full) --- 1809system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291 # average overall mshr miss latency 1810system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291 # average overall mshr miss latency 1811system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966 # average overall mshr miss latency 1812system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966 # average overall mshr miss latency 1813system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 # average ReadReq mshr uncacheable latency 1814system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency 1815system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency 1816system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency | 1682system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits 1683system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits 1684system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits 1685system.cpu1.dcache.WriteReq_hits::total 68485479 # number of WriteReq hits 1686system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174561 # number of SoftPFReq hits 1687system.cpu1.dcache.SoftPFReq_hits::total 174561 # number of SoftPFReq hits 1688system.cpu1.dcache.WriteLineReq_hits::cpu1.data 162110 # number of WriteLineReq hits 1689system.cpu1.dcache.WriteLineReq_hits::total 162110 # number of WriteLineReq hits --- 180 unchanged lines hidden (view full) --- 1870system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291 # average overall mshr miss latency 1871system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291 # average overall mshr miss latency 1872system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966 # average overall mshr miss latency 1873system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966 # average overall mshr miss latency 1874system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 # average ReadReq mshr uncacheable latency 1875system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency 1876system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency 1877system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency |
| 1878system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1817system.cpu1.icache.tags.replacements 4797887 # number of replacements 1818system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use 1819system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks. 1820system.cpu1.icache.tags.sampled_refs 4798399 # Sample count of references to valid blocks. 1821system.cpu1.icache.tags.avg_refs 86.714342 # Average number of references to valid blocks. 1822system.cpu1.icache.tags.warmup_cycle 8378704245000 # Cycle when the warmup percentage was hit. 1823system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.259979 # Average occupied blocks per requestor 1824system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969258 # Average percentage of cache occupancy 1825system.cpu1.icache.tags.occ_percent::total 0.969258 # Average percentage of cache occupancy 1826system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1827system.cpu1.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 1828system.cpu1.icache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id 1829system.cpu1.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id 1830system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 1831system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1832system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses 1833system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses | 1879system.cpu1.icache.tags.replacements 4797887 # number of replacements 1880system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use 1881system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks. 1882system.cpu1.icache.tags.sampled_refs 4798399 # Sample count of references to valid blocks. 1883system.cpu1.icache.tags.avg_refs 86.714342 # Average number of references to valid blocks. 1884system.cpu1.icache.tags.warmup_cycle 8378704245000 # Cycle when the warmup percentage was hit. 1885system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.259979 # Average occupied blocks per requestor 1886system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969258 # Average percentage of cache occupancy 1887system.cpu1.icache.tags.occ_percent::total 0.969258 # Average percentage of cache occupancy 1888system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1889system.cpu1.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 1890system.cpu1.icache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id 1891system.cpu1.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id 1892system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 1893system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1894system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses 1895system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses |
| 1896system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1834system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits 1835system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits 1836system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits 1837system.cpu1.icache.demand_hits::total 416090013 # number of demand (read+write) hits 1838system.cpu1.icache.overall_hits::cpu1.inst 416090013 # number of overall hits 1839system.cpu1.icache.overall_hits::total 416090013 # number of overall hits 1840system.cpu1.icache.ReadReq_misses::cpu1.inst 4798405 # number of ReadReq misses 1841system.cpu1.icache.ReadReq_misses::total 4798405 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1906system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency 1907system.cpu1.icache.demand_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency 1908system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency 1909system.cpu1.icache.overall_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency 1910system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average ReadReq mshr uncacheable latency 1911system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency 1912system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency 1913system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency | 1897system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits 1898system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits 1899system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits 1900system.cpu1.icache.demand_hits::total 416090013 # number of demand (read+write) hits 1901system.cpu1.icache.overall_hits::cpu1.inst 416090013 # number of overall hits 1902system.cpu1.icache.overall_hits::total 416090013 # number of overall hits 1903system.cpu1.icache.ReadReq_misses::cpu1.inst 4798405 # number of ReadReq misses 1904system.cpu1.icache.ReadReq_misses::total 4798405 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1969system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency 1970system.cpu1.icache.demand_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency 1971system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency 1972system.cpu1.icache.overall_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency 1973system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average ReadReq mshr uncacheable latency 1974system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency 1975system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency 1976system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency |
| 1977system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1914system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued 1915system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified 1916system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1917system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1918system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1919system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing | 1978system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued 1979system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified 1980system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1981system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1982system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1983system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing |
| 1984system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1920system.cpu1.l2cache.tags.replacements 1970256 # number of replacements 1921system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use 1922system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks. 1923system.cpu1.l2cache.tags.sampled_refs 1985806 # Sample count of references to valid blocks. 1924system.cpu1.l2cache.tags.avg_refs 7.166669 # Average number of references to valid blocks. 1925system.cpu1.l2cache.tags.warmup_cycle 10058718427000 # Cycle when the warmup percentage was hit. 1926system.cpu1.l2cache.tags.occ_blocks::writebacks 12287.437490 # Average occupied blocks per requestor 1927system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.190300 # Average occupied blocks per requestor --- 18 unchanged lines hidden (view full) --- 1946system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2519 # Occupied blocks per task id 1947system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5802 # Occupied blocks per task id 1948system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5375 # Occupied blocks per task id 1949system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.096558 # Percentage of cache occupancy per task id 1950system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id 1951system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id 1952system.cpu1.l2cache.tags.tag_accesses 333785497 # Number of tag accesses 1953system.cpu1.l2cache.tags.data_accesses 333785497 # Number of data accesses | 1985system.cpu1.l2cache.tags.replacements 1970256 # number of replacements 1986system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use 1987system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks. 1988system.cpu1.l2cache.tags.sampled_refs 1985806 # Sample count of references to valid blocks. 1989system.cpu1.l2cache.tags.avg_refs 7.166669 # Average number of references to valid blocks. 1990system.cpu1.l2cache.tags.warmup_cycle 10058718427000 # Cycle when the warmup percentage was hit. 1991system.cpu1.l2cache.tags.occ_blocks::writebacks 12287.437490 # Average occupied blocks per requestor 1992system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.190300 # Average occupied blocks per requestor --- 18 unchanged lines hidden (view full) --- 2011system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2519 # Occupied blocks per task id 2012system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5802 # Occupied blocks per task id 2013system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5375 # Occupied blocks per task id 2014system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.096558 # Percentage of cache occupancy per task id 2015system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id 2016system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id 2017system.cpu1.l2cache.tags.tag_accesses 333785497 # Number of tag accesses 2018system.cpu1.l2cache.tags.data_accesses 333785497 # Number of data accesses |
| 2019system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 1954system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 241732 # number of ReadReq hits 1955system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150683 # number of ReadReq hits 1956system.cpu1.l2cache.ReadReq_hits::total 392415 # number of ReadReq hits 1957system.cpu1.l2cache.WritebackDirty_hits::writebacks 3174179 # number of WritebackDirty hits 1958system.cpu1.l2cache.WritebackDirty_hits::total 3174179 # number of WritebackDirty hits 1959system.cpu1.l2cache.WritebackClean_hits::writebacks 6641283 # number of WritebackClean hits 1960system.cpu1.l2cache.WritebackClean_hits::total 6641283 # number of WritebackClean hits 1961system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits --- 315 unchanged lines hidden (view full) --- 2277system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428 # average overall mshr uncacheable latency 2278system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529 # average overall mshr uncacheable latency 2279system.cpu1.toL2Bus.snoop_filter.tot_requests 20384822 # Total number of requests made to the snoop filter. 2280system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10471744 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2281system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2282system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter. 2283system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2284system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2020system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 241732 # number of ReadReq hits 2021system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150683 # number of ReadReq hits 2022system.cpu1.l2cache.ReadReq_hits::total 392415 # number of ReadReq hits 2023system.cpu1.l2cache.WritebackDirty_hits::writebacks 3174179 # number of WritebackDirty hits 2024system.cpu1.l2cache.WritebackDirty_hits::total 3174179 # number of WritebackDirty hits 2025system.cpu1.l2cache.WritebackClean_hits::writebacks 6641283 # number of WritebackClean hits 2026system.cpu1.l2cache.WritebackClean_hits::total 6641283 # number of WritebackClean hits 2027system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits --- 315 unchanged lines hidden (view full) --- 2343system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428 # average overall mshr uncacheable latency 2344system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529 # average overall mshr uncacheable latency 2345system.cpu1.toL2Bus.snoop_filter.tot_requests 20384822 # Total number of requests made to the snoop filter. 2346system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10471744 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2347system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2348system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter. 2349system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2350system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2351system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 2285system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution 2286system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution 2287system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution 2288system.cpu1.toL2Bus.trans_dist::WriteResp 11949 # Transaction distribution 2289system.cpu1.toL2Bus.trans_dist::WritebackDirty 4279928 # Transaction distribution 2290system.cpu1.toL2Bus.trans_dist::WritebackClean 6642170 # Transaction distribution 2291system.cpu1.toL2Bus.trans_dist::CleanEvict 2284917 # Transaction distribution 2292system.cpu1.toL2Bus.trans_dist::HardPFReq 836860 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 2330system.cpu1.toL2Bus.respLayer0.occupancy 7197716000 # Layer occupancy (ticks) 2331system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2332system.cpu1.toL2Bus.respLayer1.occupancy 7451139989 # Layer occupancy (ticks) 2333system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2334system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # Layer occupancy (ticks) 2335system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2336system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks) 2337system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2352system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution 2353system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution 2354system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution 2355system.cpu1.toL2Bus.trans_dist::WriteResp 11949 # Transaction distribution 2356system.cpu1.toL2Bus.trans_dist::WritebackDirty 4279928 # Transaction distribution 2357system.cpu1.toL2Bus.trans_dist::WritebackClean 6642170 # Transaction distribution 2358system.cpu1.toL2Bus.trans_dist::CleanEvict 2284917 # Transaction distribution 2359system.cpu1.toL2Bus.trans_dist::HardPFReq 836860 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 2397system.cpu1.toL2Bus.respLayer0.occupancy 7197716000 # Layer occupancy (ticks) 2398system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2399system.cpu1.toL2Bus.respLayer1.occupancy 7451139989 # Layer occupancy (ticks) 2400system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2401system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # Layer occupancy (ticks) 2402system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2403system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks) 2404system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2405system.iobus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 2338system.iobus.trans_dist::ReadReq 40346 # Transaction distribution 2339system.iobus.trans_dist::ReadResp 40346 # Transaction distribution 2340system.iobus.trans_dist::WriteReq 136634 # Transaction distribution 2341system.iobus.trans_dist::WriteResp 136634 # Transaction distribution 2342system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47740 # Packet count per connected master and slave (bytes) 2343system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2344system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2345system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 60 unchanged lines hidden (view full) --- 2406system.iobus.reqLayer25.occupancy 569020926 # Layer occupancy (ticks) 2407system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2408system.iobus.respLayer0.occupancy 92771000 # Layer occupancy (ticks) 2409system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2410system.iobus.respLayer3.occupancy 147902000 # Layer occupancy (ticks) 2411system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2412system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2413system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 2406system.iobus.trans_dist::ReadReq 40346 # Transaction distribution 2407system.iobus.trans_dist::ReadResp 40346 # Transaction distribution 2408system.iobus.trans_dist::WriteReq 136634 # Transaction distribution 2409system.iobus.trans_dist::WriteResp 136634 # Transaction distribution 2410system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47740 # Packet count per connected master and slave (bytes) 2411system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2412system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2413system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 60 unchanged lines hidden (view full) --- 2474system.iobus.reqLayer25.occupancy 569020926 # Layer occupancy (ticks) 2475system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2476system.iobus.respLayer0.occupancy 92771000 # Layer occupancy (ticks) 2477system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2478system.iobus.respLayer3.occupancy 147902000 # Layer occupancy (ticks) 2479system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2480system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2481system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 2482system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 2414system.iocache.tags.replacements 115585 # number of replacements 2415system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use 2416system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2417system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. 2418system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2419system.iocache.tags.warmup_cycle 9095565849000 # Cycle when the warmup percentage was hit. 2420system.iocache.tags.occ_blocks::realview.ethernet 3.827817 # Average occupied blocks per requestor 2421system.iocache.tags.occ_blocks::realview.ide 7.416000 # Average occupied blocks per requestor 2422system.iocache.tags.occ_percent::realview.ethernet 0.239239 # Average percentage of cache occupancy 2423system.iocache.tags.occ_percent::realview.ide 0.463500 # Average percentage of cache occupancy 2424system.iocache.tags.occ_percent::total 0.702739 # Average percentage of cache occupancy 2425system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2426system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2427system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2428system.iocache.tags.tag_accesses 1040784 # Number of tag accesses 2429system.iocache.tags.data_accesses 1040784 # Number of data accesses | 2483system.iocache.tags.replacements 115585 # number of replacements 2484system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use 2485system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2486system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. 2487system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2488system.iocache.tags.warmup_cycle 9095565849000 # Cycle when the warmup percentage was hit. 2489system.iocache.tags.occ_blocks::realview.ethernet 3.827817 # Average occupied blocks per requestor 2490system.iocache.tags.occ_blocks::realview.ide 7.416000 # Average occupied blocks per requestor 2491system.iocache.tags.occ_percent::realview.ethernet 0.239239 # Average percentage of cache occupancy 2492system.iocache.tags.occ_percent::realview.ide 0.463500 # Average percentage of cache occupancy 2493system.iocache.tags.occ_percent::total 0.702739 # Average percentage of cache occupancy 2494system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2495system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2496system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2497system.iocache.tags.tag_accesses 1040784 # Number of tag accesses 2498system.iocache.tags.data_accesses 1040784 # Number of data accesses |
| 2499system.iocache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 2430system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2431system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses 2432system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses 2433system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2434system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2435system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2436system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2437system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 109 unchanged lines hidden (view full) --- 2547system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70834.061455 # average WriteLineReq mshr miss latency 2548system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70834.061455 # average WriteLineReq mshr miss latency 2549system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2550system.iocache.demand_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency 2551system.iocache.demand_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency 2552system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2553system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency 2554system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency | 2500system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2501system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses 2502system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses 2503system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2504system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2505system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2506system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2507system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 109 unchanged lines hidden (view full) --- 2617system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70834.061455 # average WriteLineReq mshr miss latency 2618system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70834.061455 # average WriteLineReq mshr miss latency 2619system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2620system.iocache.demand_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency 2621system.iocache.demand_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency 2622system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2623system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency 2624system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency |
| 2625system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 2555system.l2c.tags.replacements 1336257 # number of replacements 2556system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use 2557system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks. 2558system.l2c.tags.sampled_refs 1394864 # Sample count of references to valid blocks. 2559system.l2c.tags.avg_refs 3.864457 # Average number of references to valid blocks. 2560system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. 2561system.l2c.tags.occ_blocks::writebacks 23096.089917 # Average occupied blocks per requestor 2562system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.068224 # Average occupied blocks per requestor --- 30 unchanged lines hidden (view full) --- 2593system.l2c.tags.age_task_id_blocks_1024::2 1623 # Occupied blocks per task id 2594system.l2c.tags.age_task_id_blocks_1024::3 5220 # Occupied blocks per task id 2595system.l2c.tags.age_task_id_blocks_1024::4 40883 # Occupied blocks per task id 2596system.l2c.tags.occ_task_id_percent::1022 0.160416 # Percentage of cache occupancy per task id 2597system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id 2598system.l2c.tags.occ_task_id_percent::1024 0.730392 # Percentage of cache occupancy per task id 2599system.l2c.tags.tag_accesses 69855982 # Number of tag accesses 2600system.l2c.tags.data_accesses 69855982 # Number of data accesses | 2626system.l2c.tags.replacements 1336257 # number of replacements 2627system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use 2628system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks. 2629system.l2c.tags.sampled_refs 1394864 # Sample count of references to valid blocks. 2630system.l2c.tags.avg_refs 3.864457 # Average number of references to valid blocks. 2631system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. 2632system.l2c.tags.occ_blocks::writebacks 23096.089917 # Average occupied blocks per requestor 2633system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.068224 # Average occupied blocks per requestor --- 30 unchanged lines hidden (view full) --- 2664system.l2c.tags.age_task_id_blocks_1024::2 1623 # Occupied blocks per task id 2665system.l2c.tags.age_task_id_blocks_1024::3 5220 # Occupied blocks per task id 2666system.l2c.tags.age_task_id_blocks_1024::4 40883 # Occupied blocks per task id 2667system.l2c.tags.occ_task_id_percent::1022 0.160416 # Percentage of cache occupancy per task id 2668system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id 2669system.l2c.tags.occ_task_id_percent::1024 0.730392 # Percentage of cache occupancy per task id 2670system.l2c.tags.tag_accesses 69855982 # Number of tag accesses 2671system.l2c.tags.data_accesses 69855982 # Number of data accesses |
| 2672system.l2c.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 2601system.l2c.WritebackDirty_hits::writebacks 2606701 # number of WritebackDirty hits 2602system.l2c.WritebackDirty_hits::total 2606701 # number of WritebackDirty hits 2603system.l2c.UpgradeReq_hits::cpu0.data 157949 # number of UpgradeReq hits 2604system.l2c.UpgradeReq_hits::cpu1.data 130434 # number of UpgradeReq hits 2605system.l2c.UpgradeReq_hits::total 288383 # number of UpgradeReq hits 2606system.l2c.SCUpgradeReq_hits::cpu0.data 36828 # number of SCUpgradeReq hits 2607system.l2c.SCUpgradeReq_hits::cpu1.data 37034 # number of SCUpgradeReq hits 2608system.l2c.SCUpgradeReq_hits::total 73862 # number of SCUpgradeReq hits --- 504 unchanged lines hidden (view full) --- 3113system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551 # average overall mshr uncacheable latency 3114system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324 # average overall mshr uncacheable latency 3115system.membus.snoop_filter.tot_requests 3697678 # Total number of requests made to the snoop filter. 3116system.membus.snoop_filter.hit_single_requests 2246661 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3117system.membus.snoop_filter.hit_multi_requests 3188 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3118system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3119system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3120system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2673system.l2c.WritebackDirty_hits::writebacks 2606701 # number of WritebackDirty hits 2674system.l2c.WritebackDirty_hits::total 2606701 # number of WritebackDirty hits 2675system.l2c.UpgradeReq_hits::cpu0.data 157949 # number of UpgradeReq hits 2676system.l2c.UpgradeReq_hits::cpu1.data 130434 # number of UpgradeReq hits 2677system.l2c.UpgradeReq_hits::total 288383 # number of UpgradeReq hits 2678system.l2c.SCUpgradeReq_hits::cpu0.data 36828 # number of SCUpgradeReq hits 2679system.l2c.SCUpgradeReq_hits::cpu1.data 37034 # number of SCUpgradeReq hits 2680system.l2c.SCUpgradeReq_hits::total 73862 # number of SCUpgradeReq hits --- 504 unchanged lines hidden (view full) --- 3185system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551 # average overall mshr uncacheable latency 3186system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324 # average overall mshr uncacheable latency 3187system.membus.snoop_filter.tot_requests 3697678 # Total number of requests made to the snoop filter. 3188system.membus.snoop_filter.hit_single_requests 2246661 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3189system.membus.snoop_filter.hit_multi_requests 3188 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3190system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3191system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3192system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3193system.membus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 3121system.membus.trans_dist::ReadReq 81885 # Transaction distribution 3122system.membus.trans_dist::ReadResp 837971 # Transaction distribution 3123system.membus.trans_dist::WriteReq 38514 # Transaction distribution 3124system.membus.trans_dist::WriteResp 38514 # Transaction distribution 3125system.membus.trans_dist::WritebackDirty 1175339 # Transaction distribution 3126system.membus.trans_dist::CleanEvict 216465 # Transaction distribution 3127system.membus.trans_dist::UpgradeReq 402269 # Transaction distribution 3128system.membus.trans_dist::SCUpgradeReq 335845 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3167system.membus.reqLayer2.occupancy 21861496 # Layer occupancy (ticks) 3168system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3169system.membus.reqLayer5.occupancy 8209418227 # Layer occupancy (ticks) 3170system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3171system.membus.respLayer2.occupancy 4835085635 # Layer occupancy (ticks) 3172system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3173system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks) 3174system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 3194system.membus.trans_dist::ReadReq 81885 # Transaction distribution 3195system.membus.trans_dist::ReadResp 837971 # Transaction distribution 3196system.membus.trans_dist::WriteReq 38514 # Transaction distribution 3197system.membus.trans_dist::WriteResp 38514 # Transaction distribution 3198system.membus.trans_dist::WritebackDirty 1175339 # Transaction distribution 3199system.membus.trans_dist::CleanEvict 216465 # Transaction distribution 3200system.membus.trans_dist::UpgradeReq 402269 # Transaction distribution 3201system.membus.trans_dist::SCUpgradeReq 335845 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3240system.membus.reqLayer2.occupancy 21861496 # Layer occupancy (ticks) 3241system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3242system.membus.reqLayer5.occupancy 8209418227 # Layer occupancy (ticks) 3243system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3244system.membus.respLayer2.occupancy 4835085635 # Layer occupancy (ticks) 3245system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3246system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks) 3247system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3248system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3249system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3250system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3251system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3252system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3253system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3254system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 3175system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3176system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3177system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3178system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3179system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3180system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 3255system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3256system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3257system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3258system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3259system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3260system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 3261system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3262system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 3181system.realview.ethernet.txBytes 966 # Bytes Transmitted 3182system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3183system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3184system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3185system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3186system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3187system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3188system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 3215system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3216system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3217system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3218system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3219system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3220system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3221system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3222system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3263system.realview.ethernet.txBytes 966 # Bytes Transmitted 3264system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3265system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3266system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3267system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3268system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3269system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3270system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 3297system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3298system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3299system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3300system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3301system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3302system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3303system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3304system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3305system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3306system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3307system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3308system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3309system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3310system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3311system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 3223system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3224system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3225system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3226system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3312system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3313system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3314system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3315system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3316system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3317system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3318system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3319system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3320system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3321system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3322system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3323system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3324system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3325system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3326system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3327system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 3227system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter. 3228system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3229system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3230system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter. 3231system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3232system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3328system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter. 3329system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3330system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3331system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter. 3332system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3333system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3334system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states |
|
| 3233system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution 3234system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution 3235system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution 3236system.toL2Bus.trans_dist::WriteResp 38514 # Transaction distribution 3237system.toL2Bus.trans_dist::WritebackDirty 3675345 # Transaction distribution 3238system.toL2Bus.trans_dist::CleanEvict 2314292 # Transaction distribution 3239system.toL2Bus.trans_dist::UpgradeReq 683405 # Transaction distribution 3240system.toL2Bus.trans_dist::SCUpgradeReq 409707 # Transaction distribution --- 36 unchanged lines hidden --- | 3335system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution 3336system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution 3337system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution 3338system.toL2Bus.trans_dist::WriteResp 38514 # Transaction distribution 3339system.toL2Bus.trans_dist::WritebackDirty 3675345 # Transaction distribution 3340system.toL2Bus.trans_dist::CleanEvict 2314292 # Transaction distribution 3341system.toL2Bus.trans_dist::UpgradeReq 683405 # Transaction distribution 3342system.toL2Bus.trans_dist::SCUpgradeReq 409707 # Transaction distribution --- 36 unchanged lines hidden --- |