| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.460623 # Number of seconds simulated 4sim_ticks 47460623015500 # Number of ticks simulated 5final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.460623 # Number of seconds simulated 4sim_ticks 47460623015500 # Number of ticks simulated 5final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 731783 # Simulator instruction rate (inst/s) 8host_op_rate 860761 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39683148028 # Simulator tick rate (ticks/s) 10host_mem_usage 744736 # Number of bytes of host memory used 11host_seconds 1195.99 # Real time elapsed on the host | 7host_inst_rate 734945 # Simulator instruction rate (inst/s) 8host_op_rate 864481 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39854660745 # Simulator tick rate (ticks/s) 10host_mem_usage 745756 # Number of bytes of host memory used 11host_seconds 1190.84 # Real time elapsed on the host |
| 12sim_insts 875204273 # Number of instructions simulated 13sim_ops 1029460892 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 81920 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 78144 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3183732 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 11874696 # Number of bytes read from this memory --- 621 unchanged lines hidden (view full) --- 641system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199556 # number of SoftPFReq hits 642system.cpu0.dcache.SoftPFReq_hits::total 199556 # number of SoftPFReq hits 643system.cpu0.dcache.WriteLineReq_hits::cpu0.data 181390 # number of WriteLineReq hits 644system.cpu0.dcache.WriteLineReq_hits::total 181390 # number of WriteLineReq hits 645system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847375 # number of LoadLockedReq hits 646system.cpu0.dcache.LoadLockedReq_hits::total 1847375 # number of LoadLockedReq hits 647system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1814831 # number of StoreCondReq hits 648system.cpu0.dcache.StoreCondReq_hits::total 1814831 # number of StoreCondReq hits | 12sim_insts 875204273 # Number of instructions simulated 13sim_ops 1029460892 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 81920 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 78144 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3183732 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 11874696 # Number of bytes read from this memory --- 621 unchanged lines hidden (view full) --- 641system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199556 # number of SoftPFReq hits 642system.cpu0.dcache.SoftPFReq_hits::total 199556 # number of SoftPFReq hits 643system.cpu0.dcache.WriteLineReq_hits::cpu0.data 181390 # number of WriteLineReq hits 644system.cpu0.dcache.WriteLineReq_hits::total 181390 # number of WriteLineReq hits 645system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847375 # number of LoadLockedReq hits 646system.cpu0.dcache.LoadLockedReq_hits::total 1847375 # number of LoadLockedReq hits 647system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1814831 # number of StoreCondReq hits 648system.cpu0.dcache.StoreCondReq_hits::total 1814831 # number of StoreCondReq hits |
| 649system.cpu0.dcache.demand_hits::cpu0.data 152875582 # number of demand (read+write) hits 650system.cpu0.dcache.demand_hits::total 152875582 # number of demand (read+write) hits 651system.cpu0.dcache.overall_hits::cpu0.data 153075138 # number of overall hits 652system.cpu0.dcache.overall_hits::total 153075138 # number of overall hits | 649system.cpu0.dcache.demand_hits::cpu0.data 153056972 # number of demand (read+write) hits 650system.cpu0.dcache.demand_hits::total 153056972 # number of demand (read+write) hits 651system.cpu0.dcache.overall_hits::cpu0.data 153256528 # number of overall hits 652system.cpu0.dcache.overall_hits::total 153256528 # number of overall hits |
| 653system.cpu0.dcache.ReadReq_misses::cpu0.data 2983943 # number of ReadReq misses 654system.cpu0.dcache.ReadReq_misses::total 2983943 # number of ReadReq misses 655system.cpu0.dcache.WriteReq_misses::cpu0.data 1350734 # number of WriteReq misses 656system.cpu0.dcache.WriteReq_misses::total 1350734 # number of WriteReq misses 657system.cpu0.dcache.SoftPFReq_misses::cpu0.data 619590 # number of SoftPFReq misses 658system.cpu0.dcache.SoftPFReq_misses::total 619590 # number of SoftPFReq misses 659system.cpu0.dcache.WriteLineReq_misses::cpu0.data 750130 # number of WriteLineReq misses 660system.cpu0.dcache.WriteLineReq_misses::total 750130 # number of WriteLineReq misses 661system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 159632 # number of LoadLockedReq misses 662system.cpu0.dcache.LoadLockedReq_misses::total 159632 # number of LoadLockedReq misses 663system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191006 # number of StoreCondReq misses 664system.cpu0.dcache.StoreCondReq_misses::total 191006 # number of StoreCondReq misses | 653system.cpu0.dcache.ReadReq_misses::cpu0.data 2983943 # number of ReadReq misses 654system.cpu0.dcache.ReadReq_misses::total 2983943 # number of ReadReq misses 655system.cpu0.dcache.WriteReq_misses::cpu0.data 1350734 # number of WriteReq misses 656system.cpu0.dcache.WriteReq_misses::total 1350734 # number of WriteReq misses 657system.cpu0.dcache.SoftPFReq_misses::cpu0.data 619590 # number of SoftPFReq misses 658system.cpu0.dcache.SoftPFReq_misses::total 619590 # number of SoftPFReq misses 659system.cpu0.dcache.WriteLineReq_misses::cpu0.data 750130 # number of WriteLineReq misses 660system.cpu0.dcache.WriteLineReq_misses::total 750130 # number of WriteLineReq misses 661system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 159632 # number of LoadLockedReq misses 662system.cpu0.dcache.LoadLockedReq_misses::total 159632 # number of LoadLockedReq misses 663system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191006 # number of StoreCondReq misses 664system.cpu0.dcache.StoreCondReq_misses::total 191006 # number of StoreCondReq misses |
| 665system.cpu0.dcache.demand_misses::cpu0.data 4334677 # number of demand (read+write) misses 666system.cpu0.dcache.demand_misses::total 4334677 # number of demand (read+write) misses 667system.cpu0.dcache.overall_misses::cpu0.data 4954267 # number of overall misses 668system.cpu0.dcache.overall_misses::total 4954267 # number of overall misses | 665system.cpu0.dcache.demand_misses::cpu0.data 5084807 # number of demand (read+write) misses 666system.cpu0.dcache.demand_misses::total 5084807 # number of demand (read+write) misses 667system.cpu0.dcache.overall_misses::cpu0.data 5704397 # number of overall misses 668system.cpu0.dcache.overall_misses::total 5704397 # number of overall misses |
| 669system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47916762500 # number of ReadReq miss cycles 670system.cpu0.dcache.ReadReq_miss_latency::total 47916762500 # number of ReadReq miss cycles 671system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34952130000 # number of WriteReq miss cycles 672system.cpu0.dcache.WriteReq_miss_latency::total 34952130000 # number of WriteReq miss cycles 673system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46124909500 # number of WriteLineReq miss cycles 674system.cpu0.dcache.WriteLineReq_miss_latency::total 46124909500 # number of WriteLineReq miss cycles 675system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2449383000 # number of LoadLockedReq miss cycles 676system.cpu0.dcache.LoadLockedReq_miss_latency::total 2449383000 # number of LoadLockedReq miss cycles 677system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5329904000 # number of StoreCondReq miss cycles 678system.cpu0.dcache.StoreCondReq_miss_latency::total 5329904000 # number of StoreCondReq miss cycles 679system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5776000 # number of StoreCondFailReq miss cycles 680system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5776000 # number of StoreCondFailReq miss cycles | 669system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47916762500 # number of ReadReq miss cycles 670system.cpu0.dcache.ReadReq_miss_latency::total 47916762500 # number of ReadReq miss cycles 671system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34952130000 # number of WriteReq miss cycles 672system.cpu0.dcache.WriteReq_miss_latency::total 34952130000 # number of WriteReq miss cycles 673system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46124909500 # number of WriteLineReq miss cycles 674system.cpu0.dcache.WriteLineReq_miss_latency::total 46124909500 # number of WriteLineReq miss cycles 675system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2449383000 # number of LoadLockedReq miss cycles 676system.cpu0.dcache.LoadLockedReq_miss_latency::total 2449383000 # number of LoadLockedReq miss cycles 677system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5329904000 # number of StoreCondReq miss cycles 678system.cpu0.dcache.StoreCondReq_miss_latency::total 5329904000 # number of StoreCondReq miss cycles 679system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5776000 # number of StoreCondFailReq miss cycles 680system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5776000 # number of StoreCondFailReq miss cycles |
| 681system.cpu0.dcache.demand_miss_latency::cpu0.data 82868892500 # number of demand (read+write) miss cycles 682system.cpu0.dcache.demand_miss_latency::total 82868892500 # number of demand (read+write) miss cycles 683system.cpu0.dcache.overall_miss_latency::cpu0.data 82868892500 # number of overall miss cycles 684system.cpu0.dcache.overall_miss_latency::total 82868892500 # number of overall miss cycles | 681system.cpu0.dcache.demand_miss_latency::cpu0.data 128993802000 # number of demand (read+write) miss cycles 682system.cpu0.dcache.demand_miss_latency::total 128993802000 # number of demand (read+write) miss cycles 683system.cpu0.dcache.overall_miss_latency::cpu0.data 128993802000 # number of overall miss cycles 684system.cpu0.dcache.overall_miss_latency::total 128993802000 # number of overall miss cycles |
| 685system.cpu0.dcache.ReadReq_accesses::cpu0.data 82707420 # number of ReadReq accesses(hits+misses) 686system.cpu0.dcache.ReadReq_accesses::total 82707420 # number of ReadReq accesses(hits+misses) 687system.cpu0.dcache.WriteReq_accesses::cpu0.data 74502839 # number of WriteReq accesses(hits+misses) 688system.cpu0.dcache.WriteReq_accesses::total 74502839 # number of WriteReq accesses(hits+misses) 689system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 819146 # number of SoftPFReq accesses(hits+misses) 690system.cpu0.dcache.SoftPFReq_accesses::total 819146 # number of SoftPFReq accesses(hits+misses) 691system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 931520 # number of WriteLineReq accesses(hits+misses) 692system.cpu0.dcache.WriteLineReq_accesses::total 931520 # number of WriteLineReq accesses(hits+misses) 693system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2007007 # number of LoadLockedReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::total 2007007 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2005837 # number of StoreCondReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::total 2005837 # number of StoreCondReq accesses(hits+misses) | 685system.cpu0.dcache.ReadReq_accesses::cpu0.data 82707420 # number of ReadReq accesses(hits+misses) 686system.cpu0.dcache.ReadReq_accesses::total 82707420 # number of ReadReq accesses(hits+misses) 687system.cpu0.dcache.WriteReq_accesses::cpu0.data 74502839 # number of WriteReq accesses(hits+misses) 688system.cpu0.dcache.WriteReq_accesses::total 74502839 # number of WriteReq accesses(hits+misses) 689system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 819146 # number of SoftPFReq accesses(hits+misses) 690system.cpu0.dcache.SoftPFReq_accesses::total 819146 # number of SoftPFReq accesses(hits+misses) 691system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 931520 # number of WriteLineReq accesses(hits+misses) 692system.cpu0.dcache.WriteLineReq_accesses::total 931520 # number of WriteLineReq accesses(hits+misses) 693system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2007007 # number of LoadLockedReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::total 2007007 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2005837 # number of StoreCondReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::total 2005837 # number of StoreCondReq accesses(hits+misses) |
| 697system.cpu0.dcache.demand_accesses::cpu0.data 157210259 # number of demand (read+write) accesses 698system.cpu0.dcache.demand_accesses::total 157210259 # number of demand (read+write) accesses 699system.cpu0.dcache.overall_accesses::cpu0.data 158029405 # number of overall (read+write) accesses 700system.cpu0.dcache.overall_accesses::total 158029405 # number of overall (read+write) accesses | 697system.cpu0.dcache.demand_accesses::cpu0.data 158141779 # number of demand (read+write) accesses 698system.cpu0.dcache.demand_accesses::total 158141779 # number of demand (read+write) accesses 699system.cpu0.dcache.overall_accesses::cpu0.data 158960925 # number of overall (read+write) accesses 700system.cpu0.dcache.overall_accesses::total 158960925 # number of overall (read+write) accesses |
| 701system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036078 # miss rate for ReadReq accesses 702system.cpu0.dcache.ReadReq_miss_rate::total 0.036078 # miss rate for ReadReq accesses 703system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018130 # miss rate for WriteReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::total 0.018130 # miss rate for WriteReq accesses 705system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756385 # miss rate for SoftPFReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756385 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.805275 # miss rate for WriteLineReq accesses 708system.cpu0.dcache.WriteLineReq_miss_rate::total 0.805275 # miss rate for WriteLineReq accesses 709system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079537 # miss rate for LoadLockedReq accesses 710system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079537 # miss rate for LoadLockedReq accesses 711system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095225 # miss rate for StoreCondReq accesses 712system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095225 # miss rate for StoreCondReq accesses | 701system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036078 # miss rate for ReadReq accesses 702system.cpu0.dcache.ReadReq_miss_rate::total 0.036078 # miss rate for ReadReq accesses 703system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018130 # miss rate for WriteReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::total 0.018130 # miss rate for WriteReq accesses 705system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756385 # miss rate for SoftPFReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756385 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.805275 # miss rate for WriteLineReq accesses 708system.cpu0.dcache.WriteLineReq_miss_rate::total 0.805275 # miss rate for WriteLineReq accesses 709system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079537 # miss rate for LoadLockedReq accesses 710system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079537 # miss rate for LoadLockedReq accesses 711system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095225 # miss rate for StoreCondReq accesses 712system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095225 # miss rate for StoreCondReq accesses |
| 713system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027572 # miss rate for demand accesses 714system.cpu0.dcache.demand_miss_rate::total 0.027572 # miss rate for demand accesses 715system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031350 # miss rate for overall accesses 716system.cpu0.dcache.overall_miss_rate::total 0.031350 # miss rate for overall accesses | 713system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032153 # miss rate for demand accesses 714system.cpu0.dcache.demand_miss_rate::total 0.032153 # miss rate for demand accesses 715system.cpu0.dcache.overall_miss_rate::cpu0.data 0.035886 # miss rate for overall accesses 716system.cpu0.dcache.overall_miss_rate::total 0.035886 # miss rate for overall accesses |
| 717system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022 # average ReadReq miss latency 718system.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022 # average ReadReq miss latency 719system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573 # average WriteReq miss latency 720system.cpu0.dcache.WriteReq_avg_miss_latency::total 25876.397573 # average WriteReq miss latency 721system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61489.221202 # average WriteLineReq miss latency 722system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61489.221202 # average WriteLineReq miss latency 723system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15343.934800 # average LoadLockedReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15343.934800 # average LoadLockedReq miss latency 725system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967 # average StoreCondReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 717system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022 # average ReadReq miss latency 718system.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022 # average ReadReq miss latency 719system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573 # average WriteReq miss latency 720system.cpu0.dcache.WriteReq_avg_miss_latency::total 25876.397573 # average WriteReq miss latency 721system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61489.221202 # average WriteLineReq miss latency 722system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61489.221202 # average WriteLineReq miss latency 723system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15343.934800 # average LoadLockedReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15343.934800 # average LoadLockedReq miss latency 725system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967 # average StoreCondReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 729system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631 # average overall miss latency 730system.cpu0.dcache.demand_avg_miss_latency::total 19117.662631 # average overall miss latency 731system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::total 16726.771589 # average overall miss latency | 729system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25368.475539 # average overall miss latency 730system.cpu0.dcache.demand_avg_miss_latency::total 25368.475539 # average overall miss latency 731system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.047795 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::total 22613.047795 # average overall miss latency |
| 733system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 737system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 733system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 737system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 739system.cpu0.dcache.fast_writes 0 # number of fast writes performed 740system.cpu0.dcache.cache_copies 0 # number of cache copies performed | |
| 741system.cpu0.dcache.writebacks::writebacks 5459134 # number of writebacks 742system.cpu0.dcache.writebacks::total 5459134 # number of writebacks 743system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 24235 # number of ReadReq MSHR hits 744system.cpu0.dcache.ReadReq_mshr_hits::total 24235 # number of ReadReq MSHR hits 745system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21402 # number of WriteReq MSHR hits 746system.cpu0.dcache.WriteReq_mshr_hits::total 21402 # number of WriteReq MSHR hits 747system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43300 # number of LoadLockedReq MSHR hits 748system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43300 # number of LoadLockedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 757system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 618446 # number of SoftPFReq MSHR misses 758system.cpu0.dcache.SoftPFReq_mshr_misses::total 618446 # number of SoftPFReq MSHR misses 759system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 750130 # number of WriteLineReq MSHR misses 760system.cpu0.dcache.WriteLineReq_mshr_misses::total 750130 # number of WriteLineReq MSHR misses 761system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 116332 # number of LoadLockedReq MSHR misses 762system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116332 # number of LoadLockedReq MSHR misses 763system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191006 # number of StoreCondReq MSHR misses 764system.cpu0.dcache.StoreCondReq_mshr_misses::total 191006 # number of StoreCondReq MSHR misses | 739system.cpu0.dcache.writebacks::writebacks 5459134 # number of writebacks 740system.cpu0.dcache.writebacks::total 5459134 # number of writebacks 741system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 24235 # number of ReadReq MSHR hits 742system.cpu0.dcache.ReadReq_mshr_hits::total 24235 # number of ReadReq MSHR hits 743system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21402 # number of WriteReq MSHR hits 744system.cpu0.dcache.WriteReq_mshr_hits::total 21402 # number of WriteReq MSHR hits 745system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43300 # number of LoadLockedReq MSHR hits 746system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43300 # number of LoadLockedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 755system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 618446 # number of SoftPFReq MSHR misses 756system.cpu0.dcache.SoftPFReq_mshr_misses::total 618446 # number of SoftPFReq MSHR misses 757system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 750130 # number of WriteLineReq MSHR misses 758system.cpu0.dcache.WriteLineReq_mshr_misses::total 750130 # number of WriteLineReq MSHR misses 759system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 116332 # number of LoadLockedReq MSHR misses 760system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116332 # number of LoadLockedReq MSHR misses 761system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191006 # number of StoreCondReq MSHR misses 762system.cpu0.dcache.StoreCondReq_mshr_misses::total 191006 # number of StoreCondReq MSHR misses |
| 765system.cpu0.dcache.demand_mshr_misses::cpu0.data 4289040 # number of demand (read+write) MSHR misses 766system.cpu0.dcache.demand_mshr_misses::total 4289040 # number of demand (read+write) MSHR misses 767system.cpu0.dcache.overall_mshr_misses::cpu0.data 4907486 # number of overall MSHR misses 768system.cpu0.dcache.overall_mshr_misses::total 4907486 # number of overall MSHR misses | 763system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039170 # number of demand (read+write) MSHR misses 764system.cpu0.dcache.demand_mshr_misses::total 5039170 # number of demand (read+write) MSHR misses 765system.cpu0.dcache.overall_mshr_misses::cpu0.data 5657616 # number of overall MSHR misses 766system.cpu0.dcache.overall_mshr_misses::total 5657616 # number of overall MSHR misses |
| 769system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable 770system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29450 # number of ReadReq MSHR uncacheable 771system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable 772system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28924 # number of WriteReq MSHR uncacheable 773system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses 774system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58374 # number of overall MSHR uncacheable misses 775system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43283569500 # number of ReadReq MSHR miss cycles 776system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43283569500 # number of ReadReq MSHR miss cycles --- 4 unchanged lines hidden (view full) --- 781system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45374779500 # number of WriteLineReq MSHR miss cycles 782system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45374779500 # number of WriteLineReq MSHR miss cycles 783system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1623777500 # number of LoadLockedReq MSHR miss cycles 784system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1623777500 # number of LoadLockedReq MSHR miss cycles 785system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5138961000 # number of StoreCondReq MSHR miss cycles 786system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5138961000 # number of StoreCondReq MSHR miss cycles 787system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5713000 # number of StoreCondFailReq MSHR miss cycles 788system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5713000 # number of StoreCondFailReq MSHR miss cycles | 767system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable 768system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29450 # number of ReadReq MSHR uncacheable 769system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable 770system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28924 # number of WriteReq MSHR uncacheable 771system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses 772system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58374 # number of overall MSHR uncacheable misses 773system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43283569500 # number of ReadReq MSHR miss cycles 774system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43283569500 # number of ReadReq MSHR miss cycles --- 4 unchanged lines hidden (view full) --- 779system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45374779500 # number of WriteLineReq MSHR miss cycles 780system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45374779500 # number of WriteLineReq MSHR miss cycles 781system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1623777500 # number of LoadLockedReq MSHR miss cycles 782system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1623777500 # number of LoadLockedReq MSHR miss cycles 783system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5138961000 # number of StoreCondReq MSHR miss cycles 784system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5138961000 # number of StoreCondReq MSHR miss cycles 785system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5713000 # number of StoreCondFailReq MSHR miss cycles 786system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5713000 # number of StoreCondFailReq MSHR miss cycles |
| 789system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 76374032500 # number of demand (read+write) MSHR miss cycles 790system.cpu0.dcache.demand_mshr_miss_latency::total 76374032500 # number of demand (read+write) MSHR miss cycles 791system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91252922000 # number of overall MSHR miss cycles 792system.cpu0.dcache.overall_mshr_miss_latency::total 91252922000 # number of overall MSHR miss cycles | 787system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 121748812000 # number of demand (read+write) MSHR miss cycles 788system.cpu0.dcache.demand_mshr_miss_latency::total 121748812000 # number of demand (read+write) MSHR miss cycles 789system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136627701500 # number of overall MSHR miss cycles 790system.cpu0.dcache.overall_mshr_miss_latency::total 136627701500 # number of overall MSHR miss cycles |
| 793system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5439516500 # number of ReadReq MSHR uncacheable cycles 794system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5439516500 # number of ReadReq MSHR uncacheable cycles | 791system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5439516500 # number of ReadReq MSHR uncacheable cycles 792system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5439516500 # number of ReadReq MSHR uncacheable cycles |
| 795system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5307758000 # number of WriteReq MSHR uncacheable cycles 796system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5307758000 # number of WriteReq MSHR uncacheable cycles 797system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10747274500 # number of overall MSHR uncacheable cycles 798system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10747274500 # number of overall MSHR uncacheable cycles | 793system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5439516500 # number of overall MSHR uncacheable cycles 794system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5439516500 # number of overall MSHR uncacheable cycles |
| 799system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035785 # mshr miss rate for ReadReq accesses 800system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035785 # mshr miss rate for ReadReq accesses 801system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017843 # mshr miss rate for WriteReq accesses 802system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017843 # mshr miss rate for WriteReq accesses 803system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754989 # mshr miss rate for SoftPFReq accesses 804system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754989 # mshr miss rate for SoftPFReq accesses 805system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.805275 # mshr miss rate for WriteLineReq accesses 806system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.805275 # mshr miss rate for WriteLineReq accesses 807system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057963 # mshr miss rate for LoadLockedReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057963 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095225 # mshr miss rate for StoreCondReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095225 # mshr miss rate for StoreCondReq accesses | 795system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035785 # mshr miss rate for ReadReq accesses 796system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035785 # mshr miss rate for ReadReq accesses 797system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017843 # mshr miss rate for WriteReq accesses 798system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017843 # mshr miss rate for WriteReq accesses 799system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754989 # mshr miss rate for SoftPFReq accesses 800system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754989 # mshr miss rate for SoftPFReq accesses 801system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.805275 # mshr miss rate for WriteLineReq accesses 802system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.805275 # mshr miss rate for WriteLineReq accesses 803system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057963 # mshr miss rate for LoadLockedReq accesses 804system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057963 # mshr miss rate for LoadLockedReq accesses 805system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095225 # mshr miss rate for StoreCondReq accesses 806system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095225 # mshr miss rate for StoreCondReq accesses |
| 811system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for demand accesses 812system.cpu0.dcache.demand_mshr_miss_rate::total 0.027282 # mshr miss rate for demand accesses 813system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031054 # mshr miss rate for overall accesses 814system.cpu0.dcache.overall_mshr_miss_rate::total 0.031054 # mshr miss rate for overall accesses | 807system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for demand accesses 808system.cpu0.dcache.demand_mshr_miss_rate::total 0.031865 # mshr miss rate for demand accesses 809system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035591 # mshr miss rate for overall accesses 810system.cpu0.dcache.overall_mshr_miss_rate::total 0.035591 # mshr miss rate for overall accesses |
| 815system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198 # average ReadReq mshr miss latency 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198 # average ReadReq mshr miss latency 817system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792 # average WriteReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24892.549792 # average WriteReq mshr miss latency 819system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24058.510363 # average SoftPFReq mshr miss latency 820system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24058.510363 # average SoftPFReq mshr miss latency 821system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60489.221202 # average WriteLineReq mshr miss latency 822system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60489.221202 # average WriteLineReq mshr miss latency 823system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13958.132758 # average LoadLockedReq mshr miss latency 824system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13958.132758 # average LoadLockedReq mshr miss latency 825system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800 # average StoreCondReq mshr miss latency 826system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800 # average StoreCondReq mshr miss latency 827system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 828system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 811system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198 # average ReadReq mshr miss latency 812system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198 # average ReadReq mshr miss latency 813system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792 # average WriteReq mshr miss latency 814system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24892.549792 # average WriteReq mshr miss latency 815system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24058.510363 # average SoftPFReq mshr miss latency 816system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24058.510363 # average SoftPFReq mshr miss latency 817system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60489.221202 # average WriteLineReq mshr miss latency 818system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60489.221202 # average WriteLineReq mshr miss latency 819system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13958.132758 # average LoadLockedReq mshr miss latency 820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13958.132758 # average LoadLockedReq mshr miss latency 821system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800 # average StoreCondReq mshr miss latency 822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800 # average StoreCondReq mshr miss latency 823system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 824system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 829system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515 # average overall mshr miss latency 830system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515 # average overall mshr miss latency 831system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254 # average overall mshr miss latency 832system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254 # average overall mshr miss latency | 825system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24160.489128 # average overall mshr miss latency 826system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24160.489128 # average overall mshr miss latency 827system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24149.341613 # average overall mshr miss latency 828system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24149.341613 # average overall mshr miss latency |
| 833system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520 # average ReadReq mshr uncacheable latency 834system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520 # average ReadReq mshr uncacheable latency | 829system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520 # average ReadReq mshr uncacheable latency 830system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520 # average ReadReq mshr uncacheable latency |
| 835system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966 # average WriteReq mshr uncacheable latency 836system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966 # average WriteReq mshr uncacheable latency 837system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011 # average overall mshr uncacheable latency 838system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011 # average overall mshr uncacheable latency 839system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 831system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93183.891801 # average overall mshr uncacheable latency 832system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93183.891801 # average overall mshr uncacheable latency |
| 840system.cpu0.icache.tags.replacements 5000286 # number of replacements 841system.cpu0.icache.tags.tagsinuse 511.853700 # Cycle average of tags in use 842system.cpu0.icache.tags.total_refs 450204172 # Total number of references to valid blocks. 843system.cpu0.icache.tags.sampled_refs 5000798 # Sample count of references to valid blocks. 844system.cpu0.icache.tags.avg_refs 90.026466 # Average number of references to valid blocks. 845system.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit. 846system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.853700 # Average occupied blocks per requestor 847system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999714 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 890system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11095.841385 # average overall miss latency 891system.cpu0.icache.overall_avg_miss_latency::total 11095.841385 # average overall miss latency 892system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 893system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 894system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 895system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 896system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 897system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 833system.cpu0.icache.tags.replacements 5000286 # number of replacements 834system.cpu0.icache.tags.tagsinuse 511.853700 # Cycle average of tags in use 835system.cpu0.icache.tags.total_refs 450204172 # Total number of references to valid blocks. 836system.cpu0.icache.tags.sampled_refs 5000798 # Sample count of references to valid blocks. 837system.cpu0.icache.tags.avg_refs 90.026466 # Average number of references to valid blocks. 838system.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit. 839system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.853700 # Average occupied blocks per requestor 840system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999714 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 883system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11095.841385 # average overall miss latency 884system.cpu0.icache.overall_avg_miss_latency::total 11095.841385 # average overall miss latency 885system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 886system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 887system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 888system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 889system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 890system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 898system.cpu0.icache.fast_writes 0 # number of fast writes performed 899system.cpu0.icache.cache_copies 0 # number of cache copies performed | |
| 900system.cpu0.icache.writebacks::writebacks 5000286 # number of writebacks 901system.cpu0.icache.writebacks::total 5000286 # number of writebacks 902system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5000799 # number of ReadReq MSHR misses 903system.cpu0.icache.ReadReq_mshr_misses::total 5000799 # number of ReadReq MSHR misses 904system.cpu0.icache.demand_mshr_misses::cpu0.inst 5000799 # number of demand (read+write) MSHR misses 905system.cpu0.icache.demand_mshr_misses::total 5000799 # number of demand (read+write) MSHR misses 906system.cpu0.icache.overall_mshr_misses::cpu0.inst 5000799 # number of overall MSHR misses 907system.cpu0.icache.overall_mshr_misses::total 5000799 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 930system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency 931system.cpu0.icache.demand_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency 932system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency 933system.cpu0.icache.overall_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency 934system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 935system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 936system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 937system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency | 891system.cpu0.icache.writebacks::writebacks 5000286 # number of writebacks 892system.cpu0.icache.writebacks::total 5000286 # number of writebacks 893system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5000799 # number of ReadReq MSHR misses 894system.cpu0.icache.ReadReq_mshr_misses::total 5000799 # number of ReadReq MSHR misses 895system.cpu0.icache.demand_mshr_misses::cpu0.inst 5000799 # number of demand (read+write) MSHR misses 896system.cpu0.icache.demand_mshr_misses::total 5000799 # number of demand (read+write) MSHR misses 897system.cpu0.icache.overall_mshr_misses::cpu0.inst 5000799 # number of overall MSHR misses 898system.cpu0.icache.overall_mshr_misses::total 5000799 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 921system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency 922system.cpu0.icache.demand_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency 923system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency 924system.cpu0.icache.overall_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency 925system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 926system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 927system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 928system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency |
| 938system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 939system.cpu0.l2cache.prefetcher.num_hwpf_issued 7383328 # number of hwpf issued 940system.cpu0.l2cache.prefetcher.pfIdentified 7383330 # number of prefetch candidates identified 941system.cpu0.l2cache.prefetcher.pfBufferHit 1 # number of redundant prefetches already in prefetch queue 942system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 943system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 944system.cpu0.l2cache.prefetcher.pfSpanPage 974782 # number of prefetches not generated due to page crossing 945system.cpu0.l2cache.tags.replacements 2298690 # number of replacements 946system.cpu0.l2cache.tags.tagsinuse 16186.717586 # Cycle average of tags in use --- 197 unchanged lines hidden (view full) --- 1144system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45229.955209 # average overall miss latency 1145system.cpu0.l2cache.overall_avg_miss_latency::total 43628.299919 # average overall miss latency 1146system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1147system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1148system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1149system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1150system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1151system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 929system.cpu0.l2cache.prefetcher.num_hwpf_issued 7383328 # number of hwpf issued 930system.cpu0.l2cache.prefetcher.pfIdentified 7383330 # number of prefetch candidates identified 931system.cpu0.l2cache.prefetcher.pfBufferHit 1 # number of redundant prefetches already in prefetch queue 932system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 933system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 934system.cpu0.l2cache.prefetcher.pfSpanPage 974782 # number of prefetches not generated due to page crossing 935system.cpu0.l2cache.tags.replacements 2298690 # number of replacements 936system.cpu0.l2cache.tags.tagsinuse 16186.717586 # Cycle average of tags in use --- 197 unchanged lines hidden (view full) --- 1134system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45229.955209 # average overall miss latency 1135system.cpu0.l2cache.overall_avg_miss_latency::total 43628.299919 # average overall miss latency 1136system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1137system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1138system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1139system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1140system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1141system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1152system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1153system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | |
| 1154system.cpu0.l2cache.unused_prefetches 39383 # number of HardPF blocks evicted w/o reference 1155system.cpu0.l2cache.writebacks::writebacks 1473434 # number of writebacks 1156system.cpu0.l2cache.writebacks::total 1473434 # number of writebacks 1157system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5831 # number of ReadExReq MSHR hits 1158system.cpu0.l2cache.ReadExReq_mshr_hits::total 5831 # number of ReadExReq MSHR hits 1159system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 658 # number of ReadSharedReq MSHR hits 1160system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 658 # number of ReadSharedReq MSHR hits 1161system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6489 # number of demand (read+write) MSHR hits --- 66 unchanged lines hidden (view full) --- 1228system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 281362000 # number of overall MSHR miss cycles 1229system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15454024500 # number of overall MSHR miss cycles 1230system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44782129999 # number of overall MSHR miss cycles 1231system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37650647602 # number of overall MSHR miss cycles 1232system.cpu0.l2cache.overall_mshr_miss_latency::total 98500032601 # number of overall MSHR miss cycles 1233system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 1234system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5203415000 # number of ReadReq MSHR uncacheable cycles 1235system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10834186500 # number of ReadReq MSHR uncacheable cycles | 1142system.cpu0.l2cache.unused_prefetches 39383 # number of HardPF blocks evicted w/o reference 1143system.cpu0.l2cache.writebacks::writebacks 1473434 # number of writebacks 1144system.cpu0.l2cache.writebacks::total 1473434 # number of writebacks 1145system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5831 # number of ReadExReq MSHR hits 1146system.cpu0.l2cache.ReadExReq_mshr_hits::total 5831 # number of ReadExReq MSHR hits 1147system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 658 # number of ReadSharedReq MSHR hits 1148system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 658 # number of ReadSharedReq MSHR hits 1149system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6489 # number of demand (read+write) MSHR hits --- 66 unchanged lines hidden (view full) --- 1216system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 281362000 # number of overall MSHR miss cycles 1217system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15454024500 # number of overall MSHR miss cycles 1218system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44782129999 # number of overall MSHR miss cycles 1219system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37650647602 # number of overall MSHR miss cycles 1220system.cpu0.l2cache.overall_mshr_miss_latency::total 98500032601 # number of overall MSHR miss cycles 1221system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 1222system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5203415000 # number of ReadReq MSHR uncacheable cycles 1223system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10834186500 # number of ReadReq MSHR uncacheable cycles |
| 1236system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5090437000 # number of WriteReq MSHR uncacheable cycles 1237system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5090437000 # number of WriteReq MSHR uncacheable cycles | |
| 1238system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles | 1224system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles |
| 1239system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10293852000 # number of overall MSHR uncacheable cycles 1240system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15924623500 # number of overall MSHR uncacheable cycles | 1225system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5203415000 # number of overall MSHR uncacheable cycles 1226system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10834186500 # number of overall MSHR uncacheable cycles |
| 1241system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for ReadReq accesses 1242system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for ReadReq accesses 1243system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043899 # mshr miss rate for ReadReq accesses 1244system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1245system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1246system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998394 # mshr miss rate for UpgradeReq accesses 1247system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998394 # mshr miss rate for UpgradeReq accesses 1248system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses --- 47 unchanged lines hidden (view full) --- 1296system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency 1297system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency 1298system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency 1299system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average overall mshr miss latency 1300system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834 # average overall mshr miss latency 1301system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 1302system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657 # average ReadReq mshr uncacheable latency 1303system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871 # average ReadReq mshr uncacheable latency | 1227system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for ReadReq accesses 1228system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for ReadReq accesses 1229system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043899 # mshr miss rate for ReadReq accesses 1230system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1231system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1232system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998394 # mshr miss rate for UpgradeReq accesses 1233system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998394 # mshr miss rate for UpgradeReq accesses 1234system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses --- 47 unchanged lines hidden (view full) --- 1282system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency 1283system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency 1284system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency 1285system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average overall mshr miss latency 1286system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834 # average overall mshr miss latency 1287system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 1288system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657 # average ReadReq mshr uncacheable latency 1289system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871 # average ReadReq mshr uncacheable latency |
| 1304system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781 # average WriteReq mshr uncacheable latency 1305system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781 # average WriteReq mshr uncacheable latency | |
| 1306system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency | 1290system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency |
| 1307system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955 # average overall mshr uncacheable latency 1308system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122 # average overall mshr uncacheable latency 1309system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1291system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89139.257204 # average overall mshr uncacheable latency 1292system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106741.805338 # average overall mshr uncacheable latency |
| 1310system.cpu0.toL2Bus.snoop_filter.tot_requests 21678176 # Total number of requests made to the snoop filter. 1311system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128402 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1312system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 962 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1313system.cpu0.toL2Bus.snoop_filter.tot_snoops 1759585 # Total number of snoops made to the snoop filter. 1314system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1759287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1315system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1316system.cpu0.toL2Bus.trans_dist::ReadReq 537700 # Transaction distribution 1317system.cpu0.toL2Bus.trans_dist::ReadResp 9321471 # Transaction distribution --- 311 unchanged lines hidden (view full) --- 1629system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171099 # number of SoftPFReq hits 1630system.cpu1.dcache.SoftPFReq_hits::total 171099 # number of SoftPFReq hits 1631system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145458 # number of WriteLineReq hits 1632system.cpu1.dcache.WriteLineReq_hits::total 145458 # number of WriteLineReq hits 1633system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1631683 # number of LoadLockedReq hits 1634system.cpu1.dcache.LoadLockedReq_hits::total 1631683 # number of LoadLockedReq hits 1635system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602426 # number of StoreCondReq hits 1636system.cpu1.dcache.StoreCondReq_hits::total 1602426 # number of StoreCondReq hits | 1293system.cpu0.toL2Bus.snoop_filter.tot_requests 21678176 # Total number of requests made to the snoop filter. 1294system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128402 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1295system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 962 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1296system.cpu0.toL2Bus.snoop_filter.tot_snoops 1759585 # Total number of snoops made to the snoop filter. 1297system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1759287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1298system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1299system.cpu0.toL2Bus.trans_dist::ReadReq 537700 # Transaction distribution 1300system.cpu0.toL2Bus.trans_dist::ReadResp 9321471 # Transaction distribution --- 311 unchanged lines hidden (view full) --- 1612system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171099 # number of SoftPFReq hits 1613system.cpu1.dcache.SoftPFReq_hits::total 171099 # number of SoftPFReq hits 1614system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145458 # number of WriteLineReq hits 1615system.cpu1.dcache.WriteLineReq_hits::total 145458 # number of WriteLineReq hits 1616system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1631683 # number of LoadLockedReq hits 1617system.cpu1.dcache.LoadLockedReq_hits::total 1631683 # number of LoadLockedReq hits 1618system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602426 # number of StoreCondReq hits 1619system.cpu1.dcache.StoreCondReq_hits::total 1602426 # number of StoreCondReq hits |
| 1637system.cpu1.dcache.demand_hits::cpu1.data 142590680 # number of demand (read+write) hits 1638system.cpu1.dcache.demand_hits::total 142590680 # number of demand (read+write) hits 1639system.cpu1.dcache.overall_hits::cpu1.data 142761779 # number of overall hits 1640system.cpu1.dcache.overall_hits::total 142761779 # number of overall hits | 1620system.cpu1.dcache.demand_hits::cpu1.data 142736138 # number of demand (read+write) hits 1621system.cpu1.dcache.demand_hits::total 142736138 # number of demand (read+write) hits 1622system.cpu1.dcache.overall_hits::cpu1.data 142907237 # number of overall hits 1623system.cpu1.dcache.overall_hits::total 142907237 # number of overall hits |
| 1641system.cpu1.dcache.ReadReq_misses::cpu1.data 2875045 # number of ReadReq misses 1642system.cpu1.dcache.ReadReq_misses::total 2875045 # number of ReadReq misses 1643system.cpu1.dcache.WriteReq_misses::cpu1.data 1313230 # number of WriteReq misses 1644system.cpu1.dcache.WriteReq_misses::total 1313230 # number of WriteReq misses 1645system.cpu1.dcache.SoftPFReq_misses::cpu1.data 626301 # number of SoftPFReq misses 1646system.cpu1.dcache.SoftPFReq_misses::total 626301 # number of SoftPFReq misses 1647system.cpu1.dcache.WriteLineReq_misses::cpu1.data 483495 # number of WriteLineReq misses 1648system.cpu1.dcache.WriteLineReq_misses::total 483495 # number of WriteLineReq misses 1649system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165519 # number of LoadLockedReq misses 1650system.cpu1.dcache.LoadLockedReq_misses::total 165519 # number of LoadLockedReq misses 1651system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193387 # number of StoreCondReq misses 1652system.cpu1.dcache.StoreCondReq_misses::total 193387 # number of StoreCondReq misses | 1624system.cpu1.dcache.ReadReq_misses::cpu1.data 2875045 # number of ReadReq misses 1625system.cpu1.dcache.ReadReq_misses::total 2875045 # number of ReadReq misses 1626system.cpu1.dcache.WriteReq_misses::cpu1.data 1313230 # number of WriteReq misses 1627system.cpu1.dcache.WriteReq_misses::total 1313230 # number of WriteReq misses 1628system.cpu1.dcache.SoftPFReq_misses::cpu1.data 626301 # number of SoftPFReq misses 1629system.cpu1.dcache.SoftPFReq_misses::total 626301 # number of SoftPFReq misses 1630system.cpu1.dcache.WriteLineReq_misses::cpu1.data 483495 # number of WriteLineReq misses 1631system.cpu1.dcache.WriteLineReq_misses::total 483495 # number of WriteLineReq misses 1632system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165519 # number of LoadLockedReq misses 1633system.cpu1.dcache.LoadLockedReq_misses::total 165519 # number of LoadLockedReq misses 1634system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193387 # number of StoreCondReq misses 1635system.cpu1.dcache.StoreCondReq_misses::total 193387 # number of StoreCondReq misses |
| 1653system.cpu1.dcache.demand_misses::cpu1.data 4188275 # number of demand (read+write) misses 1654system.cpu1.dcache.demand_misses::total 4188275 # number of demand (read+write) misses 1655system.cpu1.dcache.overall_misses::cpu1.data 4814576 # number of overall misses 1656system.cpu1.dcache.overall_misses::total 4814576 # number of overall misses | 1636system.cpu1.dcache.demand_misses::cpu1.data 4671770 # number of demand (read+write) misses 1637system.cpu1.dcache.demand_misses::total 4671770 # number of demand (read+write) misses 1638system.cpu1.dcache.overall_misses::cpu1.data 5298071 # number of overall misses 1639system.cpu1.dcache.overall_misses::total 5298071 # number of overall misses |
| 1657system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45279528500 # number of ReadReq miss cycles 1658system.cpu1.dcache.ReadReq_miss_latency::total 45279528500 # number of ReadReq miss cycles 1659system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 30099423000 # number of WriteReq miss cycles 1660system.cpu1.dcache.WriteReq_miss_latency::total 30099423000 # number of WriteReq miss cycles 1661system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18095848000 # number of WriteLineReq miss cycles 1662system.cpu1.dcache.WriteLineReq_miss_latency::total 18095848000 # number of WriteLineReq miss cycles 1663system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2729020500 # number of LoadLockedReq miss cycles 1664system.cpu1.dcache.LoadLockedReq_miss_latency::total 2729020500 # number of LoadLockedReq miss cycles 1665system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5550193500 # number of StoreCondReq miss cycles 1666system.cpu1.dcache.StoreCondReq_miss_latency::total 5550193500 # number of StoreCondReq miss cycles 1667system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6333000 # number of StoreCondFailReq miss cycles 1668system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6333000 # number of StoreCondFailReq miss cycles | 1640system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45279528500 # number of ReadReq miss cycles 1641system.cpu1.dcache.ReadReq_miss_latency::total 45279528500 # number of ReadReq miss cycles 1642system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 30099423000 # number of WriteReq miss cycles 1643system.cpu1.dcache.WriteReq_miss_latency::total 30099423000 # number of WriteReq miss cycles 1644system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18095848000 # number of WriteLineReq miss cycles 1645system.cpu1.dcache.WriteLineReq_miss_latency::total 18095848000 # number of WriteLineReq miss cycles 1646system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2729020500 # number of LoadLockedReq miss cycles 1647system.cpu1.dcache.LoadLockedReq_miss_latency::total 2729020500 # number of LoadLockedReq miss cycles 1648system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5550193500 # number of StoreCondReq miss cycles 1649system.cpu1.dcache.StoreCondReq_miss_latency::total 5550193500 # number of StoreCondReq miss cycles 1650system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6333000 # number of StoreCondFailReq miss cycles 1651system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6333000 # number of StoreCondFailReq miss cycles |
| 1669system.cpu1.dcache.demand_miss_latency::cpu1.data 75378951500 # number of demand (read+write) miss cycles 1670system.cpu1.dcache.demand_miss_latency::total 75378951500 # number of demand (read+write) miss cycles 1671system.cpu1.dcache.overall_miss_latency::cpu1.data 75378951500 # number of overall miss cycles 1672system.cpu1.dcache.overall_miss_latency::total 75378951500 # number of overall miss cycles | 1652system.cpu1.dcache.demand_miss_latency::cpu1.data 93474799500 # number of demand (read+write) miss cycles 1653system.cpu1.dcache.demand_miss_latency::total 93474799500 # number of demand (read+write) miss cycles 1654system.cpu1.dcache.overall_miss_latency::cpu1.data 93474799500 # number of overall miss cycles 1655system.cpu1.dcache.overall_miss_latency::total 93474799500 # number of overall miss cycles |
| 1673system.cpu1.dcache.ReadReq_accesses::cpu1.data 76904053 # number of ReadReq accesses(hits+misses) 1674system.cpu1.dcache.ReadReq_accesses::total 76904053 # number of ReadReq accesses(hits+misses) 1675system.cpu1.dcache.WriteReq_accesses::cpu1.data 69874902 # number of WriteReq accesses(hits+misses) 1676system.cpu1.dcache.WriteReq_accesses::total 69874902 # number of WriteReq accesses(hits+misses) 1677system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 797400 # number of SoftPFReq accesses(hits+misses) 1678system.cpu1.dcache.SoftPFReq_accesses::total 797400 # number of SoftPFReq accesses(hits+misses) 1679system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 628953 # number of WriteLineReq accesses(hits+misses) 1680system.cpu1.dcache.WriteLineReq_accesses::total 628953 # number of WriteLineReq accesses(hits+misses) 1681system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1797202 # number of LoadLockedReq accesses(hits+misses) 1682system.cpu1.dcache.LoadLockedReq_accesses::total 1797202 # number of LoadLockedReq accesses(hits+misses) 1683system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1795813 # number of StoreCondReq accesses(hits+misses) 1684system.cpu1.dcache.StoreCondReq_accesses::total 1795813 # number of StoreCondReq accesses(hits+misses) | 1656system.cpu1.dcache.ReadReq_accesses::cpu1.data 76904053 # number of ReadReq accesses(hits+misses) 1657system.cpu1.dcache.ReadReq_accesses::total 76904053 # number of ReadReq accesses(hits+misses) 1658system.cpu1.dcache.WriteReq_accesses::cpu1.data 69874902 # number of WriteReq accesses(hits+misses) 1659system.cpu1.dcache.WriteReq_accesses::total 69874902 # number of WriteReq accesses(hits+misses) 1660system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 797400 # number of SoftPFReq accesses(hits+misses) 1661system.cpu1.dcache.SoftPFReq_accesses::total 797400 # number of SoftPFReq accesses(hits+misses) 1662system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 628953 # number of WriteLineReq accesses(hits+misses) 1663system.cpu1.dcache.WriteLineReq_accesses::total 628953 # number of WriteLineReq accesses(hits+misses) 1664system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1797202 # number of LoadLockedReq accesses(hits+misses) 1665system.cpu1.dcache.LoadLockedReq_accesses::total 1797202 # number of LoadLockedReq accesses(hits+misses) 1666system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1795813 # number of StoreCondReq accesses(hits+misses) 1667system.cpu1.dcache.StoreCondReq_accesses::total 1795813 # number of StoreCondReq accesses(hits+misses) |
| 1685system.cpu1.dcache.demand_accesses::cpu1.data 146778955 # number of demand (read+write) accesses 1686system.cpu1.dcache.demand_accesses::total 146778955 # number of demand (read+write) accesses 1687system.cpu1.dcache.overall_accesses::cpu1.data 147576355 # number of overall (read+write) accesses 1688system.cpu1.dcache.overall_accesses::total 147576355 # number of overall (read+write) accesses | 1668system.cpu1.dcache.demand_accesses::cpu1.data 147407908 # number of demand (read+write) accesses 1669system.cpu1.dcache.demand_accesses::total 147407908 # number of demand (read+write) accesses 1670system.cpu1.dcache.overall_accesses::cpu1.data 148205308 # number of overall (read+write) accesses 1671system.cpu1.dcache.overall_accesses::total 148205308 # number of overall (read+write) accesses |
| 1689system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037385 # miss rate for ReadReq accesses 1690system.cpu1.dcache.ReadReq_miss_rate::total 0.037385 # miss rate for ReadReq accesses 1691system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018794 # miss rate for WriteReq accesses 1692system.cpu1.dcache.WriteReq_miss_rate::total 0.018794 # miss rate for WriteReq accesses 1693system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.785429 # miss rate for SoftPFReq accesses 1694system.cpu1.dcache.SoftPFReq_miss_rate::total 0.785429 # miss rate for SoftPFReq accesses 1695system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.768730 # miss rate for WriteLineReq accesses 1696system.cpu1.dcache.WriteLineReq_miss_rate::total 0.768730 # miss rate for WriteLineReq accesses 1697system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092098 # miss rate for LoadLockedReq accesses 1698system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092098 # miss rate for LoadLockedReq accesses 1699system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.107688 # miss rate for StoreCondReq accesses 1700system.cpu1.dcache.StoreCondReq_miss_rate::total 0.107688 # miss rate for StoreCondReq accesses | 1672system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037385 # miss rate for ReadReq accesses 1673system.cpu1.dcache.ReadReq_miss_rate::total 0.037385 # miss rate for ReadReq accesses 1674system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018794 # miss rate for WriteReq accesses 1675system.cpu1.dcache.WriteReq_miss_rate::total 0.018794 # miss rate for WriteReq accesses 1676system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.785429 # miss rate for SoftPFReq accesses 1677system.cpu1.dcache.SoftPFReq_miss_rate::total 0.785429 # miss rate for SoftPFReq accesses 1678system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.768730 # miss rate for WriteLineReq accesses 1679system.cpu1.dcache.WriteLineReq_miss_rate::total 0.768730 # miss rate for WriteLineReq accesses 1680system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092098 # miss rate for LoadLockedReq accesses 1681system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092098 # miss rate for LoadLockedReq accesses 1682system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.107688 # miss rate for StoreCondReq accesses 1683system.cpu1.dcache.StoreCondReq_miss_rate::total 0.107688 # miss rate for StoreCondReq accesses |
| 1701system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses 1702system.cpu1.dcache.demand_miss_rate::total 0.028535 # miss rate for demand accesses 1703system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032624 # miss rate for overall accesses 1704system.cpu1.dcache.overall_miss_rate::total 0.032624 # miss rate for overall accesses | 1684system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031693 # miss rate for demand accesses 1685system.cpu1.dcache.demand_miss_rate::total 0.031693 # miss rate for demand accesses 1686system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035748 # miss rate for overall accesses 1687system.cpu1.dcache.overall_miss_rate::total 0.035748 # miss rate for overall accesses |
| 1705system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709 # average ReadReq miss latency 1706system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709 # average ReadReq miss latency 1707system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748 # average WriteReq miss latency 1708system.cpu1.dcache.WriteReq_avg_miss_latency::total 22920.145748 # average WriteReq miss latency 1709system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37427.166775 # average WriteLineReq miss latency 1710system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37427.166775 # average WriteLineReq miss latency 1711system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16487.657006 # average LoadLockedReq miss latency 1712system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16487.657006 # average LoadLockedReq miss latency 1713system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709 # average StoreCondReq miss latency 1714system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709 # average StoreCondReq miss latency 1715system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1716system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1688system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709 # average ReadReq miss latency 1689system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709 # average ReadReq miss latency 1690system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748 # average WriteReq miss latency 1691system.cpu1.dcache.WriteReq_avg_miss_latency::total 22920.145748 # average WriteReq miss latency 1692system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37427.166775 # average WriteLineReq miss latency 1693system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37427.166775 # average WriteLineReq miss latency 1694system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16487.657006 # average LoadLockedReq miss latency 1695system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16487.657006 # average LoadLockedReq miss latency 1696system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709 # average StoreCondReq miss latency 1697system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709 # average StoreCondReq miss latency 1698system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1699system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1717system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740 # average overall miss latency 1718system.cpu1.dcache.demand_avg_miss_latency::total 17997.612740 # average overall miss latency 1719system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946 # average overall miss latency 1720system.cpu1.dcache.overall_avg_miss_latency::total 15656.404946 # average overall miss latency | 1700system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20008.433527 # average overall miss latency 1701system.cpu1.dcache.demand_avg_miss_latency::total 20008.433527 # average overall miss latency 1702system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17643.176073 # average overall miss latency 1703system.cpu1.dcache.overall_avg_miss_latency::total 17643.176073 # average overall miss latency |
| 1721system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1722system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1723system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1724system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1725system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1726system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1704system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1705system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1706system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1707system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1708system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1709system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1727system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1728system.cpu1.dcache.cache_copies 0 # number of cache copies performed | |
| 1729system.cpu1.dcache.writebacks::writebacks 5111729 # number of writebacks 1730system.cpu1.dcache.writebacks::total 5111729 # number of writebacks 1731system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16692 # number of ReadReq MSHR hits 1732system.cpu1.dcache.ReadReq_mshr_hits::total 16692 # number of ReadReq MSHR hits 1733system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits 1734system.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits 1735system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44979 # number of LoadLockedReq MSHR hits 1736system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44979 # number of LoadLockedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 1745system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 626301 # number of SoftPFReq MSHR misses 1746system.cpu1.dcache.SoftPFReq_mshr_misses::total 626301 # number of SoftPFReq MSHR misses 1747system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 483495 # number of WriteLineReq MSHR misses 1748system.cpu1.dcache.WriteLineReq_mshr_misses::total 483495 # number of WriteLineReq MSHR misses 1749system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses 1750system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses 1751system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193387 # number of StoreCondReq MSHR misses 1752system.cpu1.dcache.StoreCondReq_mshr_misses::total 193387 # number of StoreCondReq MSHR misses | 1710system.cpu1.dcache.writebacks::writebacks 5111729 # number of writebacks 1711system.cpu1.dcache.writebacks::total 5111729 # number of writebacks 1712system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16692 # number of ReadReq MSHR hits 1713system.cpu1.dcache.ReadReq_mshr_hits::total 16692 # number of ReadReq MSHR hits 1714system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits 1715system.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits 1716system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44979 # number of LoadLockedReq MSHR hits 1717system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44979 # number of LoadLockedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 1726system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 626301 # number of SoftPFReq MSHR misses 1727system.cpu1.dcache.SoftPFReq_mshr_misses::total 626301 # number of SoftPFReq MSHR misses 1728system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 483495 # number of WriteLineReq MSHR misses 1729system.cpu1.dcache.WriteLineReq_mshr_misses::total 483495 # number of WriteLineReq MSHR misses 1730system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses 1731system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses 1732system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193387 # number of StoreCondReq MSHR misses 1733system.cpu1.dcache.StoreCondReq_mshr_misses::total 193387 # number of StoreCondReq MSHR misses |
| 1753system.cpu1.dcache.demand_mshr_misses::cpu1.data 4171181 # number of demand (read+write) MSHR misses 1754system.cpu1.dcache.demand_mshr_misses::total 4171181 # number of demand (read+write) MSHR misses 1755system.cpu1.dcache.overall_mshr_misses::cpu1.data 4797482 # number of overall MSHR misses 1756system.cpu1.dcache.overall_mshr_misses::total 4797482 # number of overall MSHR misses | 1734system.cpu1.dcache.demand_mshr_misses::cpu1.data 4654676 # number of demand (read+write) MSHR misses 1735system.cpu1.dcache.demand_mshr_misses::total 4654676 # number of demand (read+write) MSHR misses 1736system.cpu1.dcache.overall_mshr_misses::cpu1.data 5280977 # number of overall MSHR misses 1737system.cpu1.dcache.overall_mshr_misses::total 5280977 # number of overall MSHR misses |
| 1757system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable 1758system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8711 # number of ReadReq MSHR uncacheable 1759system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable 1760system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9093 # number of WriteReq MSHR uncacheable 1761system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17804 # number of overall MSHR uncacheable misses 1762system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17804 # number of overall MSHR uncacheable misses 1763system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40977017000 # number of ReadReq MSHR miss cycles 1764system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40977017000 # number of ReadReq MSHR miss cycles --- 4 unchanged lines hidden (view full) --- 1769system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17612353000 # number of WriteLineReq MSHR miss cycles 1770system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17612353000 # number of WriteLineReq MSHR miss cycles 1771system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1713373500 # number of LoadLockedReq MSHR miss cycles 1772system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1713373500 # number of LoadLockedReq MSHR miss cycles 1773system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5356877500 # number of StoreCondReq MSHR miss cycles 1774system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5356877500 # number of StoreCondReq MSHR miss cycles 1775system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6262000 # number of StoreCondFailReq MSHR miss cycles 1776system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6262000 # number of StoreCondFailReq MSHR miss cycles | 1738system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable 1739system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8711 # number of ReadReq MSHR uncacheable 1740system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable 1741system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9093 # number of WriteReq MSHR uncacheable 1742system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17804 # number of overall MSHR uncacheable misses 1743system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17804 # number of overall MSHR uncacheable misses 1744system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40977017000 # number of ReadReq MSHR miss cycles 1745system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40977017000 # number of ReadReq MSHR miss cycles --- 4 unchanged lines hidden (view full) --- 1750system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17612353000 # number of WriteLineReq MSHR miss cycles 1751system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17612353000 # number of WriteLineReq MSHR miss cycles 1752system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1713373500 # number of LoadLockedReq MSHR miss cycles 1753system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1713373500 # number of LoadLockedReq MSHR miss cycles 1754system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5356877500 # number of StoreCondReq MSHR miss cycles 1755system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5356877500 # number of StoreCondReq MSHR miss cycles 1756system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6262000 # number of StoreCondFailReq MSHR miss cycles 1757system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6262000 # number of StoreCondFailReq MSHR miss cycles |
| 1777system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69734968500 # number of demand (read+write) MSHR miss cycles 1778system.cpu1.dcache.demand_mshr_miss_latency::total 69734968500 # number of demand (read+write) MSHR miss cycles 1779system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84014947000 # number of overall MSHR miss cycles 1780system.cpu1.dcache.overall_mshr_miss_latency::total 84014947000 # number of overall MSHR miss cycles | 1758system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 87347321500 # number of demand (read+write) MSHR miss cycles 1759system.cpu1.dcache.demand_mshr_miss_latency::total 87347321500 # number of demand (read+write) MSHR miss cycles 1760system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101627300000 # number of overall MSHR miss cycles 1761system.cpu1.dcache.overall_mshr_miss_latency::total 101627300000 # number of overall MSHR miss cycles |
| 1781system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1460511000 # number of ReadReq MSHR uncacheable cycles 1782system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1460511000 # number of ReadReq MSHR uncacheable cycles | 1762system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1460511000 # number of ReadReq MSHR uncacheable cycles 1763system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1460511000 # number of ReadReq MSHR uncacheable cycles |
| 1783system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1571513500 # number of WriteReq MSHR uncacheable cycles 1784system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1571513500 # number of WriteReq MSHR uncacheable cycles 1785system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3032024500 # number of overall MSHR uncacheable cycles 1786system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3032024500 # number of overall MSHR uncacheable cycles | 1764system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1460511000 # number of overall MSHR uncacheable cycles 1765system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1460511000 # number of overall MSHR uncacheable cycles |
| 1787system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037168 # mshr miss rate for ReadReq accesses 1788system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037168 # mshr miss rate for ReadReq accesses 1789system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018788 # mshr miss rate for WriteReq accesses 1790system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018788 # mshr miss rate for WriteReq accesses 1791system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.785429 # mshr miss rate for SoftPFReq accesses 1792system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.785429 # mshr miss rate for SoftPFReq accesses 1793system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.768730 # mshr miss rate for WriteLineReq accesses 1794system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.768730 # mshr miss rate for WriteLineReq accesses 1795system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067071 # mshr miss rate for LoadLockedReq accesses 1796system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067071 # mshr miss rate for LoadLockedReq accesses 1797system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.107688 # mshr miss rate for StoreCondReq accesses 1798system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.107688 # mshr miss rate for StoreCondReq accesses | 1766system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037168 # mshr miss rate for ReadReq accesses 1767system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037168 # mshr miss rate for ReadReq accesses 1768system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018788 # mshr miss rate for WriteReq accesses 1769system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018788 # mshr miss rate for WriteReq accesses 1770system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.785429 # mshr miss rate for SoftPFReq accesses 1771system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.785429 # mshr miss rate for SoftPFReq accesses 1772system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.768730 # mshr miss rate for WriteLineReq accesses 1773system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.768730 # mshr miss rate for WriteLineReq accesses 1774system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067071 # mshr miss rate for LoadLockedReq accesses 1775system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067071 # mshr miss rate for LoadLockedReq accesses 1776system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.107688 # mshr miss rate for StoreCondReq accesses 1777system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.107688 # mshr miss rate for StoreCondReq accesses |
| 1799system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028418 # mshr miss rate for demand accesses 1800system.cpu1.dcache.demand_mshr_miss_rate::total 0.028418 # mshr miss rate for demand accesses 1801system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032508 # mshr miss rate for overall accesses 1802system.cpu1.dcache.overall_mshr_miss_rate::total 0.032508 # mshr miss rate for overall accesses | 1778system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031577 # mshr miss rate for demand accesses 1779system.cpu1.dcache.demand_mshr_miss_rate::total 0.031577 # mshr miss rate for demand accesses 1780system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses 1781system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses |
| 1803system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986 # average ReadReq mshr miss latency 1804system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986 # average ReadReq mshr miss latency 1805system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940 # average WriteReq mshr miss latency 1806system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21905.345940 # average WriteReq mshr miss latency 1807system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22800.504071 # average SoftPFReq mshr miss latency 1808system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22800.504071 # average SoftPFReq mshr miss latency 1809system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36427.166775 # average WriteLineReq mshr miss latency 1810system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36427.166775 # average WriteLineReq mshr miss latency 1811system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14214.148830 # average LoadLockedReq mshr miss latency 1812system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14214.148830 # average LoadLockedReq mshr miss latency 1813system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848 # average StoreCondReq mshr miss latency 1814system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848 # average StoreCondReq mshr miss latency 1815system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1816system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1782system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986 # average ReadReq mshr miss latency 1783system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986 # average ReadReq mshr miss latency 1784system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940 # average WriteReq mshr miss latency 1785system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21905.345940 # average WriteReq mshr miss latency 1786system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22800.504071 # average SoftPFReq mshr miss latency 1787system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22800.504071 # average SoftPFReq mshr miss latency 1788system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36427.166775 # average WriteLineReq mshr miss latency 1789system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36427.166775 # average WriteLineReq mshr miss latency 1790system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14214.148830 # average LoadLockedReq mshr miss latency 1791system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14214.148830 # average LoadLockedReq mshr miss latency 1792system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848 # average StoreCondReq mshr miss latency 1793system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848 # average StoreCondReq mshr miss latency 1794system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1795system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1817system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188 # average overall mshr miss latency 1818system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188 # average overall mshr miss latency 1819system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619 # average overall mshr miss latency 1820system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619 # average overall mshr miss latency | 1796system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18765.499790 # average overall mshr miss latency 1797system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18765.499790 # average overall mshr miss latency 1798system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19244.033822 # average overall mshr miss latency 1799system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19244.033822 # average overall mshr miss latency |
| 1821system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087 # average ReadReq mshr uncacheable latency 1822system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087 # average ReadReq mshr uncacheable latency | 1800system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087 # average ReadReq mshr uncacheable latency 1801system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087 # average ReadReq mshr uncacheable latency |
| 1823system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851 # average WriteReq mshr uncacheable latency 1824system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851 # average WriteReq mshr uncacheable latency 1825system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352 # average overall mshr uncacheable latency 1826system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352 # average overall mshr uncacheable latency 1827system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1802system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82032.745450 # average overall mshr uncacheable latency 1803system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82032.745450 # average overall mshr uncacheable latency |
| 1828system.cpu1.icache.tags.replacements 4920276 # number of replacements 1829system.cpu1.icache.tags.tagsinuse 496.059748 # Cycle average of tags in use 1830system.cpu1.icache.tags.total_refs 415625824 # Total number of references to valid blocks. 1831system.cpu1.icache.tags.sampled_refs 4920788 # Sample count of references to valid blocks. 1832system.cpu1.icache.tags.avg_refs 84.463266 # Average number of references to valid blocks. 1833system.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit. 1834system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.059748 # Average occupied blocks per requestor 1835system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968867 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 1877system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency 1878system.cpu1.icache.overall_avg_miss_latency::total 10923.162994 # average overall miss latency 1879system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1880system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1881system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1882system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1883system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1884system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1804system.cpu1.icache.tags.replacements 4920276 # number of replacements 1805system.cpu1.icache.tags.tagsinuse 496.059748 # Cycle average of tags in use 1806system.cpu1.icache.tags.total_refs 415625824 # Total number of references to valid blocks. 1807system.cpu1.icache.tags.sampled_refs 4920788 # Sample count of references to valid blocks. 1808system.cpu1.icache.tags.avg_refs 84.463266 # Average number of references to valid blocks. 1809system.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit. 1810system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.059748 # Average occupied blocks per requestor 1811system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968867 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 1853system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency 1854system.cpu1.icache.overall_avg_miss_latency::total 10923.162994 # average overall miss latency 1855system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1856system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1857system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1858system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1859system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1860system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1885system.cpu1.icache.fast_writes 0 # number of fast writes performed 1886system.cpu1.icache.cache_copies 0 # number of cache copies performed | |
| 1887system.cpu1.icache.writebacks::writebacks 4920276 # number of writebacks 1888system.cpu1.icache.writebacks::total 4920276 # number of writebacks 1889system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4920793 # number of ReadReq MSHR misses 1890system.cpu1.icache.ReadReq_mshr_misses::total 4920793 # number of ReadReq MSHR misses 1891system.cpu1.icache.demand_mshr_misses::cpu1.inst 4920793 # number of demand (read+write) MSHR misses 1892system.cpu1.icache.demand_mshr_misses::total 4920793 # number of demand (read+write) MSHR misses 1893system.cpu1.icache.overall_mshr_misses::cpu1.inst 4920793 # number of overall MSHR misses 1894system.cpu1.icache.overall_mshr_misses::total 4920793 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 1917system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency 1918system.cpu1.icache.demand_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency 1919system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency 1920system.cpu1.icache.overall_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency 1921system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average ReadReq mshr uncacheable latency 1922system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency 1923system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency 1924system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency | 1861system.cpu1.icache.writebacks::writebacks 4920276 # number of writebacks 1862system.cpu1.icache.writebacks::total 4920276 # number of writebacks 1863system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4920793 # number of ReadReq MSHR misses 1864system.cpu1.icache.ReadReq_mshr_misses::total 4920793 # number of ReadReq MSHR misses 1865system.cpu1.icache.demand_mshr_misses::cpu1.inst 4920793 # number of demand (read+write) MSHR misses 1866system.cpu1.icache.demand_mshr_misses::total 4920793 # number of demand (read+write) MSHR misses 1867system.cpu1.icache.overall_mshr_misses::cpu1.inst 4920793 # number of overall MSHR misses 1868system.cpu1.icache.overall_mshr_misses::total 4920793 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 1891system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency 1892system.cpu1.icache.demand_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency 1893system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency 1894system.cpu1.icache.overall_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency 1895system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average ReadReq mshr uncacheable latency 1896system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency 1897system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency 1898system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency |
| 1925system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1926system.cpu1.l2cache.prefetcher.num_hwpf_issued 7108517 # number of hwpf issued 1927system.cpu1.l2cache.prefetcher.pfIdentified 7108606 # number of prefetch candidates identified 1928system.cpu1.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue 1929system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1930system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1931system.cpu1.l2cache.prefetcher.pfSpanPage 877146 # number of prefetches not generated due to page crossing 1932system.cpu1.l2cache.tags.replacements 1947890 # number of replacements 1933system.cpu1.l2cache.tags.tagsinuse 13258.686630 # Cycle average of tags in use --- 193 unchanged lines hidden (view full) --- 2127system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42888.821599 # average overall miss latency 2128system.cpu1.l2cache.overall_avg_miss_latency::total 41525.970048 # average overall miss latency 2129system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2130system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2131system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2132system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2133system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2134system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1899system.cpu1.l2cache.prefetcher.num_hwpf_issued 7108517 # number of hwpf issued 1900system.cpu1.l2cache.prefetcher.pfIdentified 7108606 # number of prefetch candidates identified 1901system.cpu1.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue 1902system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1903system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1904system.cpu1.l2cache.prefetcher.pfSpanPage 877146 # number of prefetches not generated due to page crossing 1905system.cpu1.l2cache.tags.replacements 1947890 # number of replacements 1906system.cpu1.l2cache.tags.tagsinuse 13258.686630 # Cycle average of tags in use --- 193 unchanged lines hidden (view full) --- 2100system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42888.821599 # average overall miss latency 2101system.cpu1.l2cache.overall_avg_miss_latency::total 41525.970048 # average overall miss latency 2102system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2103system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2104system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2105system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2106system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2107system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2135system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2136system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | |
| 2137system.cpu1.l2cache.unused_prefetches 39620 # number of HardPF blocks evicted w/o reference 2138system.cpu1.l2cache.writebacks::writebacks 1103180 # number of writebacks 2139system.cpu1.l2cache.writebacks::total 1103180 # number of writebacks 2140system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6962 # number of ReadExReq MSHR hits 2141system.cpu1.l2cache.ReadExReq_mshr_hits::total 6962 # number of ReadExReq MSHR hits 2142system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 454 # number of ReadSharedReq MSHR hits 2143system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 454 # number of ReadSharedReq MSHR hits 2144system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits --- 68 unchanged lines hidden (view full) --- 2213system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369251500 # number of overall MSHR miss cycles 2214system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14347084000 # number of overall MSHR miss cycles 2215system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39806402498 # number of overall MSHR miss cycles 2216system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40532964082 # number of overall MSHR miss cycles 2217system.cpu1.l2cache.overall_mshr_miss_latency::total 95457897080 # number of overall MSHR miss cycles 2218system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13938500 # number of ReadReq MSHR uncacheable cycles 2219system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1390451500 # number of ReadReq MSHR uncacheable cycles 2220system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1404390000 # number of ReadReq MSHR uncacheable cycles | 2108system.cpu1.l2cache.unused_prefetches 39620 # number of HardPF blocks evicted w/o reference 2109system.cpu1.l2cache.writebacks::writebacks 1103180 # number of writebacks 2110system.cpu1.l2cache.writebacks::total 1103180 # number of writebacks 2111system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6962 # number of ReadExReq MSHR hits 2112system.cpu1.l2cache.ReadExReq_mshr_hits::total 6962 # number of ReadExReq MSHR hits 2113system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 454 # number of ReadSharedReq MSHR hits 2114system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 454 # number of ReadSharedReq MSHR hits 2115system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits --- 68 unchanged lines hidden (view full) --- 2184system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369251500 # number of overall MSHR miss cycles 2185system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14347084000 # number of overall MSHR miss cycles 2186system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39806402498 # number of overall MSHR miss cycles 2187system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40532964082 # number of overall MSHR miss cycles 2188system.cpu1.l2cache.overall_mshr_miss_latency::total 95457897080 # number of overall MSHR miss cycles 2189system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13938500 # number of ReadReq MSHR uncacheable cycles 2190system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1390451500 # number of ReadReq MSHR uncacheable cycles 2191system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1404390000 # number of ReadReq MSHR uncacheable cycles |
| 2221system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1502902000 # number of WriteReq MSHR uncacheable cycles 2222system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1502902000 # number of WriteReq MSHR uncacheable cycles | |
| 2223system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13938500 # number of overall MSHR uncacheable cycles | 2192system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13938500 # number of overall MSHR uncacheable cycles |
| 2224system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2893353500 # number of overall MSHR uncacheable cycles 2225system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2907292000 # number of overall MSHR uncacheable cycles | 2193system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1390451500 # number of overall MSHR uncacheable cycles 2194system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1404390000 # number of overall MSHR uncacheable cycles |
| 2226system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for ReadReq accesses 2227system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for ReadReq accesses 2228system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041059 # mshr miss rate for ReadReq accesses 2229system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2230system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2231system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997567 # mshr miss rate for UpgradeReq accesses 2232system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997567 # mshr miss rate for UpgradeReq accesses 2233system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses --- 47 unchanged lines hidden (view full) --- 2281system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency 2282system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency 2283system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency 2284system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average overall mshr miss latency 2285system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452 # average overall mshr miss latency 2286system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency 2287system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860 # average ReadReq mshr uncacheable latency 2288system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154 # average ReadReq mshr uncacheable latency | 2195system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for ReadReq accesses 2196system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for ReadReq accesses 2197system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041059 # mshr miss rate for ReadReq accesses 2198system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2199system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2200system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997567 # mshr miss rate for UpgradeReq accesses 2201system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997567 # mshr miss rate for UpgradeReq accesses 2202system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses --- 47 unchanged lines hidden (view full) --- 2250system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency 2251system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency 2252system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency 2253system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average overall mshr miss latency 2254system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452 # average overall mshr miss latency 2255system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency 2256system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860 # average ReadReq mshr uncacheable latency 2257system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154 # average ReadReq mshr uncacheable latency |
| 2289system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323 # average WriteReq mshr uncacheable latency 2290system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323 # average WriteReq mshr uncacheable latency | |
| 2291system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency | 2258system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency |
| 2292system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016 # average overall mshr uncacheable latency 2293system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496 # average overall mshr uncacheable latency 2294system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2259system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78097.702763 # average overall mshr uncacheable latency 2260system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78396.226415 # average overall mshr uncacheable latency |
| 2295system.cpu1.toL2Bus.snoop_filter.tot_requests 20782124 # Total number of requests made to the snoop filter. 2296system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10655468 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2297system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2298system.cpu1.toL2Bus.snoop_filter.tot_snoops 1707466 # Total number of snoops made to the snoop filter. 2299system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1707307 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2300system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 159 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2301system.cpu1.toL2Bus.trans_dist::ReadReq 502417 # Transaction distribution 2302system.cpu1.toL2Bus.trans_dist::ReadResp 9121363 # Transaction distribution --- 143 unchanged lines hidden (view full) --- 2446system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2447system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses 2448system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses 2449system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2450system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2451system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2452system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2453system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 2261system.cpu1.toL2Bus.snoop_filter.tot_requests 20782124 # Total number of requests made to the snoop filter. 2262system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10655468 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2263system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2264system.cpu1.toL2Bus.snoop_filter.tot_snoops 1707466 # Total number of snoops made to the snoop filter. 2265system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1707307 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2266system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 159 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2267system.cpu1.toL2Bus.trans_dist::ReadReq 502417 # Transaction distribution 2268system.cpu1.toL2Bus.trans_dist::ReadResp 9121363 # Transaction distribution --- 143 unchanged lines hidden (view full) --- 2412system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2413system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses 2414system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses 2415system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2416system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2417system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2418system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2419system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 2454system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses 2455system.iocache.demand_misses::total 8919 # number of demand (read+write) misses | 2420system.iocache.demand_misses::realview.ide 115607 # number of demand (read+write) misses 2421system.iocache.demand_misses::total 115647 # number of demand (read+write) misses |
| 2456system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 2422system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 2457system.iocache.overall_misses::realview.ide 8879 # number of overall misses 2458system.iocache.overall_misses::total 8919 # number of overall misses | 2423system.iocache.overall_misses::realview.ide 115607 # number of overall misses 2424system.iocache.overall_misses::total 115647 # number of overall misses |
| 2459system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 2460system.iocache.ReadReq_miss_latency::realview.ide 1680349949 # number of ReadReq miss cycles 2461system.iocache.ReadReq_miss_latency::total 1685547949 # number of ReadReq miss cycles 2462system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2463system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2464system.iocache.WriteLineReq_miss_latency::realview.ide 13547011908 # number of WriteLineReq miss cycles 2465system.iocache.WriteLineReq_miss_latency::total 13547011908 # number of WriteLineReq miss cycles 2466system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles | 2425system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 2426system.iocache.ReadReq_miss_latency::realview.ide 1680349949 # number of ReadReq miss cycles 2427system.iocache.ReadReq_miss_latency::total 1685547949 # number of ReadReq miss cycles 2428system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2429system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2430system.iocache.WriteLineReq_miss_latency::realview.ide 13547011908 # number of WriteLineReq miss cycles 2431system.iocache.WriteLineReq_miss_latency::total 13547011908 # number of WriteLineReq miss cycles 2432system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles |
| 2467system.iocache.demand_miss_latency::realview.ide 1680349949 # number of demand (read+write) miss cycles 2468system.iocache.demand_miss_latency::total 1685916949 # number of demand (read+write) miss cycles | 2433system.iocache.demand_miss_latency::realview.ide 15227361857 # number of demand (read+write) miss cycles 2434system.iocache.demand_miss_latency::total 15232928857 # number of demand (read+write) miss cycles |
| 2469system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles | 2435system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles |
| 2470system.iocache.overall_miss_latency::realview.ide 1680349949 # number of overall miss cycles 2471system.iocache.overall_miss_latency::total 1685916949 # number of overall miss cycles | 2436system.iocache.overall_miss_latency::realview.ide 15227361857 # number of overall miss cycles 2437system.iocache.overall_miss_latency::total 15232928857 # number of overall miss cycles |
| 2472system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2473system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) 2474system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) 2475system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2476system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2477system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2478system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2479system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 2438system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2439system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) 2440system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) 2441system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2442system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2443system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2444system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2445system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 2480system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses 2481system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses | 2446system.iocache.demand_accesses::realview.ide 115607 # number of demand (read+write) accesses 2447system.iocache.demand_accesses::total 115647 # number of demand (read+write) accesses |
| 2482system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 2448system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 2483system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses 2484system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses | 2449system.iocache.overall_accesses::realview.ide 115607 # number of overall (read+write) accesses 2450system.iocache.overall_accesses::total 115647 # number of overall (read+write) accesses |
| 2485system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2486system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2487system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2488system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2489system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2490system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2491system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2492system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 2498system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 2499system.iocache.ReadReq_avg_miss_latency::realview.ide 189249.909787 # average ReadReq miss latency 2500system.iocache.ReadReq_avg_miss_latency::total 189047.549237 # average ReadReq miss latency 2501system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2502system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2503system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743 # average WriteLineReq miss latency 2504system.iocache.WriteLineReq_avg_miss_latency::total 126930.251743 # average WriteLineReq miss latency 2505system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency | 2451system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2452system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2453system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2454system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2455system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2456system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2457system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2458system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 2464system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 2465system.iocache.ReadReq_avg_miss_latency::realview.ide 189249.909787 # average ReadReq miss latency 2466system.iocache.ReadReq_avg_miss_latency::total 189047.549237 # average ReadReq miss latency 2467system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2468system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2469system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743 # average WriteLineReq miss latency 2470system.iocache.WriteLineReq_avg_miss_latency::total 126930.251743 # average WriteLineReq miss latency 2471system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency |
| 2506system.iocache.demand_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency 2507system.iocache.demand_avg_miss_latency::total 189025.333445 # average overall miss latency | 2472system.iocache.demand_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency 2473system.iocache.demand_avg_miss_latency::total 131719.187329 # average overall miss latency |
| 2508system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency | 2474system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency |
| 2509system.iocache.overall_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency 2510system.iocache.overall_avg_miss_latency::total 189025.333445 # average overall miss latency | 2475system.iocache.overall_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency 2476system.iocache.overall_avg_miss_latency::total 131719.187329 # average overall miss latency |
| 2511system.iocache.blocked_cycles::no_mshrs 33462 # number of cycles access was blocked 2512system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2513system.iocache.blocked::no_mshrs 3547 # number of cycles access was blocked 2514system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2515system.iocache.avg_blocked_cycles::no_mshrs 9.433888 # average number of cycles each access was blocked 2516system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2477system.iocache.blocked_cycles::no_mshrs 33462 # number of cycles access was blocked 2478system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2479system.iocache.blocked::no_mshrs 3547 # number of cycles access was blocked 2480system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2481system.iocache.avg_blocked_cycles::no_mshrs 9.433888 # average number of cycles each access was blocked 2482system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2517system.iocache.fast_writes 0 # number of fast writes performed 2518system.iocache.cache_copies 0 # number of cache copies performed | |
| 2519system.iocache.writebacks::writebacks 106693 # number of writebacks 2520system.iocache.writebacks::total 106693 # number of writebacks 2521system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2522system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses 2523system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses 2524system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2525system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2526system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2527system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2528system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 2483system.iocache.writebacks::writebacks 106693 # number of writebacks 2484system.iocache.writebacks::total 106693 # number of writebacks 2485system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2486system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses 2487system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses 2488system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2489system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2490system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2491system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2492system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 2529system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses 2530system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses | 2493system.iocache.demand_mshr_misses::realview.ide 115607 # number of demand (read+write) MSHR misses 2494system.iocache.demand_mshr_misses::total 115647 # number of demand (read+write) MSHR misses |
| 2531system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 2495system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 2532system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses 2533system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses | 2496system.iocache.overall_mshr_misses::realview.ide 115607 # number of overall MSHR misses 2497system.iocache.overall_mshr_misses::total 115647 # number of overall MSHR misses |
| 2534system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 2535system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236399949 # number of ReadReq MSHR miss cycles 2536system.iocache.ReadReq_mshr_miss_latency::total 1239747949 # number of ReadReq MSHR miss cycles 2537system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2538system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2539system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8204144644 # number of WriteLineReq MSHR miss cycles 2540system.iocache.WriteLineReq_mshr_miss_latency::total 8204144644 # number of WriteLineReq MSHR miss cycles 2541system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles | 2498system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 2499system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236399949 # number of ReadReq MSHR miss cycles 2500system.iocache.ReadReq_mshr_miss_latency::total 1239747949 # number of ReadReq MSHR miss cycles 2501system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2502system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2503system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8204144644 # number of WriteLineReq MSHR miss cycles 2504system.iocache.WriteLineReq_mshr_miss_latency::total 8204144644 # number of WriteLineReq MSHR miss cycles 2505system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles |
| 2542system.iocache.demand_mshr_miss_latency::realview.ide 1236399949 # number of demand (read+write) MSHR miss cycles 2543system.iocache.demand_mshr_miss_latency::total 1239966949 # number of demand (read+write) MSHR miss cycles | 2506system.iocache.demand_mshr_miss_latency::realview.ide 9440544593 # number of demand (read+write) MSHR miss cycles 2507system.iocache.demand_mshr_miss_latency::total 9444111593 # number of demand (read+write) MSHR miss cycles |
| 2544system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles | 2508system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles |
| 2545system.iocache.overall_mshr_miss_latency::realview.ide 1236399949 # number of overall MSHR miss cycles 2546system.iocache.overall_mshr_miss_latency::total 1239966949 # number of overall MSHR miss cycles | 2509system.iocache.overall_mshr_miss_latency::realview.ide 9440544593 # number of overall MSHR miss cycles 2510system.iocache.overall_mshr_miss_latency::total 9444111593 # number of overall MSHR miss cycles |
| 2547system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2548system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2549system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2550system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2551system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2552system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2553system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2554system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 2560system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 2561system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139249.909787 # average ReadReq mshr miss latency 2562system.iocache.ReadReq_avg_mshr_miss_latency::total 139047.549237 # average ReadReq mshr miss latency 2563system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2564system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2565system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76869.655985 # average WriteLineReq mshr miss latency 2566system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76869.655985 # average WriteLineReq mshr miss latency 2567system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency | 2511system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2512system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2513system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2514system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2515system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2516system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2517system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2518system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 2524system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 2525system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139249.909787 # average ReadReq mshr miss latency 2526system.iocache.ReadReq_avg_mshr_miss_latency::total 139047.549237 # average ReadReq mshr miss latency 2527system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2528system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2529system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76869.655985 # average WriteLineReq mshr miss latency 2530system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76869.655985 # average WriteLineReq mshr miss latency 2531system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency |
| 2568system.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency 2569system.iocache.demand_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency | 2532system.iocache.demand_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency 2533system.iocache.demand_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency |
| 2570system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency | 2534system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency |
| 2571system.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency 2572system.iocache.overall_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency 2573system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2535system.iocache.overall_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency 2536system.iocache.overall_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency |
| 2574system.l2c.tags.replacements 1288575 # number of replacements 2575system.l2c.tags.tagsinuse 63334.482670 # Cycle average of tags in use 2576system.l2c.tags.total_refs 5304464 # Total number of references to valid blocks. 2577system.l2c.tags.sampled_refs 1347256 # Sample count of references to valid blocks. 2578system.l2c.tags.avg_refs 3.937235 # Average number of references to valid blocks. 2579system.l2c.tags.warmup_cycle 17731050500 # Cycle when the warmup percentage was hit. 2580system.l2c.tags.occ_blocks::writebacks 24026.415823 # Average occupied blocks per requestor 2581system.l2c.tags.occ_blocks::cpu0.dtb.walker 182.847205 # Average occupied blocks per requestor --- 310 unchanged lines hidden (view full) --- 2892system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894 # average overall miss latency 2893system.l2c.overall_avg_miss_latency::total 152790.436710 # average overall miss latency 2894system.l2c.blocked_cycles::no_mshrs 1300 # number of cycles access was blocked 2895system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2896system.l2c.blocked::no_mshrs 25 # number of cycles access was blocked 2897system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2898system.l2c.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked 2899system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2537system.l2c.tags.replacements 1288575 # number of replacements 2538system.l2c.tags.tagsinuse 63334.482670 # Cycle average of tags in use 2539system.l2c.tags.total_refs 5304464 # Total number of references to valid blocks. 2540system.l2c.tags.sampled_refs 1347256 # Sample count of references to valid blocks. 2541system.l2c.tags.avg_refs 3.937235 # Average number of references to valid blocks. 2542system.l2c.tags.warmup_cycle 17731050500 # Cycle when the warmup percentage was hit. 2543system.l2c.tags.occ_blocks::writebacks 24026.415823 # Average occupied blocks per requestor 2544system.l2c.tags.occ_blocks::cpu0.dtb.walker 182.847205 # Average occupied blocks per requestor --- 310 unchanged lines hidden (view full) --- 2855system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894 # average overall miss latency 2856system.l2c.overall_avg_miss_latency::total 152790.436710 # average overall miss latency 2857system.l2c.blocked_cycles::no_mshrs 1300 # number of cycles access was blocked 2858system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2859system.l2c.blocked::no_mshrs 25 # number of cycles access was blocked 2860system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2861system.l2c.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked 2862system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2900system.l2c.fast_writes 0 # number of fast writes performed 2901system.l2c.cache_copies 0 # number of cache copies performed | |
| 2902system.l2c.writebacks::writebacks 1038944 # number of writebacks 2903system.l2c.writebacks::total 1038944 # number of writebacks 2904system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 98 # number of ReadSharedReq MSHR hits 2905system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits 2906system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 68 # number of ReadSharedReq MSHR hits 2907system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 2908system.l2c.ReadSharedReq_mshr_hits::total 208 # number of ReadSharedReq MSHR hits 2909system.l2c.demand_mshr_hits::cpu0.inst 98 # number of demand (read+write) MSHR hits --- 111 unchanged lines hidden (view full) --- 3021system.l2c.overall_mshr_miss_latency::cpu1.data 19824782063 # number of overall MSHR miss cycles 3022system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33521925244 # number of overall MSHR miss cycles 3023system.l2c.overall_mshr_miss_latency::total 119579260538 # number of overall MSHR miss cycles 3024system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles 3025system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4673220523 # number of ReadReq MSHR uncacheable cycles 3026system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11957000 # number of ReadReq MSHR uncacheable cycles 3027system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1233601518 # number of ReadReq MSHR uncacheable cycles 3028system.l2c.ReadReq_mshr_uncacheable_latency::total 10773300041 # number of ReadReq MSHR uncacheable cycles | 2863system.l2c.writebacks::writebacks 1038944 # number of writebacks 2864system.l2c.writebacks::total 1038944 # number of writebacks 2865system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 98 # number of ReadSharedReq MSHR hits 2866system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits 2867system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 68 # number of ReadSharedReq MSHR hits 2868system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 2869system.l2c.ReadSharedReq_mshr_hits::total 208 # number of ReadSharedReq MSHR hits 2870system.l2c.demand_mshr_hits::cpu0.inst 98 # number of demand (read+write) MSHR hits --- 111 unchanged lines hidden (view full) --- 2982system.l2c.overall_mshr_miss_latency::cpu1.data 19824782063 # number of overall MSHR miss cycles 2983system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33521925244 # number of overall MSHR miss cycles 2984system.l2c.overall_mshr_miss_latency::total 119579260538 # number of overall MSHR miss cycles 2985system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles 2986system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4673220523 # number of ReadReq MSHR uncacheable cycles 2987system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11957000 # number of ReadReq MSHR uncacheable cycles 2988system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1233601518 # number of ReadReq MSHR uncacheable cycles 2989system.l2c.ReadReq_mshr_uncacheable_latency::total 10773300041 # number of ReadReq MSHR uncacheable cycles |
| 3029system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4598373544 # number of WriteReq MSHR uncacheable cycles 3030system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1348007106 # number of WriteReq MSHR uncacheable cycles 3031system.l2c.WriteReq_mshr_uncacheable_latency::total 5946380650 # number of WriteReq MSHR uncacheable cycles | |
| 3032system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles | 2990system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles |
| 3033system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9271594067 # number of overall MSHR uncacheable cycles | 2991system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4673220523 # number of overall MSHR uncacheable cycles |
| 3034system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11957000 # number of overall MSHR uncacheable cycles | 2992system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11957000 # number of overall MSHR uncacheable cycles |
| 3035system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2581608624 # number of overall MSHR uncacheable cycles 3036system.l2c.overall_mshr_uncacheable_latency::total 16719680691 # number of overall MSHR uncacheable cycles | 2993system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1233601518 # number of overall MSHR uncacheable cycles 2994system.l2c.overall_mshr_uncacheable_latency::total 10773300041 # number of overall MSHR uncacheable cycles |
| 3037system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3038system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3039system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275559 # mshr miss rate for UpgradeReq accesses 3040system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315189 # mshr miss rate for UpgradeReq accesses 3041system.l2c.UpgradeReq_mshr_miss_rate::total 0.293598 # mshr miss rate for UpgradeReq accesses 3042system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.244994 # mshr miss rate for SCUpgradeReq accesses 3043system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.272905 # mshr miss rate for SCUpgradeReq accesses 3044system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.259336 # mshr miss rate for SCUpgradeReq accesses --- 81 unchanged lines hidden (view full) --- 3126system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency 3127system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency 3128system.l2c.overall_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency 3129system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 3130system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610 # average ReadReq mshr uncacheable latency 3131system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency 3132system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814 # average ReadReq mshr uncacheable latency 3133system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610 # average ReadReq mshr uncacheable latency | 2995system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2996system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2997system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275559 # mshr miss rate for UpgradeReq accesses 2998system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315189 # mshr miss rate for UpgradeReq accesses 2999system.l2c.UpgradeReq_mshr_miss_rate::total 0.293598 # mshr miss rate for UpgradeReq accesses 3000system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.244994 # mshr miss rate for SCUpgradeReq accesses 3001system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.272905 # mshr miss rate for SCUpgradeReq accesses 3002system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.259336 # mshr miss rate for SCUpgradeReq accesses --- 81 unchanged lines hidden (view full) --- 3084system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency 3085system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency 3086system.l2c.overall_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency 3087system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 3088system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610 # average ReadReq mshr uncacheable latency 3089system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency 3090system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814 # average ReadReq mshr uncacheable latency 3091system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610 # average ReadReq mshr uncacheable latency |
| 3134system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471 # average WriteReq mshr uncacheable latency 3135system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922 # average WriteReq mshr uncacheable latency 3136system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754 # average WriteReq mshr uncacheable latency | |
| 3137system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency | 3092system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency |
| 3138system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760 # average overall mshr uncacheable latency | 3093system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80056.540977 # average overall mshr uncacheable latency |
| 3139system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency | 3094system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency |
| 3140system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214 # average overall mshr uncacheable latency 3141system.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084 # average overall mshr uncacheable latency 3142system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 3095system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69295.670037 # average overall mshr uncacheable latency 3096system.l2c.overall_avg_mshr_uncacheable_latency::total 90220.331804 # average overall mshr uncacheable latency |
| 3143system.membus.trans_dist::ReadReq 81394 # Transaction distribution 3144system.membus.trans_dist::ReadResp 801457 # Transaction distribution 3145system.membus.trans_dist::WriteReq 38017 # Transaction distribution 3146system.membus.trans_dist::WriteResp 38017 # Transaction distribution 3147system.membus.trans_dist::WritebackDirty 1145637 # Transaction distribution 3148system.membus.trans_dist::CleanEvict 202586 # Transaction distribution 3149system.membus.trans_dist::UpgradeReq 388021 # Transaction distribution 3150system.membus.trans_dist::SCUpgradeReq 309846 # Transaction distribution --- 148 unchanged lines hidden --- | 3097system.membus.trans_dist::ReadReq 81394 # Transaction distribution 3098system.membus.trans_dist::ReadResp 801457 # Transaction distribution 3099system.membus.trans_dist::WriteReq 38017 # Transaction distribution 3100system.membus.trans_dist::WriteResp 38017 # Transaction distribution 3101system.membus.trans_dist::WritebackDirty 1145637 # Transaction distribution 3102system.membus.trans_dist::CleanEvict 202586 # Transaction distribution 3103system.membus.trans_dist::UpgradeReq 388021 # Transaction distribution 3104system.membus.trans_dist::SCUpgradeReq 309846 # Transaction distribution --- 148 unchanged lines hidden --- |