3,5c3,5
< sim_seconds 47.405081 # Number of seconds simulated
< sim_ticks 47405080882500 # Number of ticks simulated
< final_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.401371 # Number of seconds simulated
> sim_ticks 47401370587500 # Number of ticks simulated
> final_tick 47401370587500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1071981 # Simulator instruction rate (inst/s)
< host_op_rate 1260946 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 57861452624 # Simulator tick rate (ticks/s)
< host_mem_usage 765552 # Number of bytes of host memory used
< host_seconds 819.29 # Real time elapsed on the host
< sim_insts 878258906 # Number of instructions simulated
< sim_ops 1033075205 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1122973 # Simulator instruction rate (inst/s)
> host_op_rate 1337206 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 65940331964 # Simulator tick rate (ticks/s)
> host_mem_usage 757896 # Number of bytes of host memory used
> host_seconds 718.85 # Real time elapsed on the host
> sim_insts 807251718 # Number of instructions simulated
> sim_ops 961253990 # Number of ops (including micro ops) simulated
16,32c16,32
< system.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory
< system.physmem.bytes_read::total 56765124 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu0.dtb.walker 62784 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 59776 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 2908084 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 11497800 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 12850688 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 108160 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 115584 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 2943416 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 9887760 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 11019584 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 443392 # Number of bytes read from this memory
> system.physmem.bytes_read::total 51897028 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 2908084 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 2943416 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 5851500 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 70859904 # Number of bytes written to this memory
35,48c35,48
< system.physmem.bytes_written::total 74764392 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 927476 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 70880488 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 981 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 934 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 49846 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 179666 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 200792 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 1690 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1806 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 46079 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 154509 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 172181 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6928 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 815412 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1107186 # Number of write requests responded to by this memory
51,67c51,67
< system.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 53373 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1109760 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 1325 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 1261 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 61350 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 242563 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 271104 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 2282 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 2438 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 62096 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 208597 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 232474 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 9354 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1094842 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 61350 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 62096 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 123446 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1494891 # Write bandwidth from this memory (bytes/s)
70,94c70,94
< system.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 927476 # Number of read requests accepted
< system.physmem.writeReqs 1170446 # Number of write requests accepted
< system.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue
< system.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 1495326 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1494891 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 1325 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 1261 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 61350 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 242997 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 271104 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 2282 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 62096 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 208597 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 232474 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 9354 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2590168 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 815412 # Number of read requests accepted
> system.physmem.writeReqs 1109760 # Number of write requests accepted
> system.physmem.readBursts 815412 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1109760 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 52162176 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 24192 # Total number of bytes read from write queue
> system.physmem.bytesWritten 70877120 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 51897028 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 70880488 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 378 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2280 # Number of DRAM write bursts merged with an existing one
96,127c96,127
< system.physmem.perBankRdBursts::0 53525 # Per bank write bursts
< system.physmem.perBankRdBursts::1 58700 # Per bank write bursts
< system.physmem.perBankRdBursts::2 53136 # Per bank write bursts
< system.physmem.perBankRdBursts::3 59915 # Per bank write bursts
< system.physmem.perBankRdBursts::4 57558 # Per bank write bursts
< system.physmem.perBankRdBursts::5 67025 # Per bank write bursts
< system.physmem.perBankRdBursts::6 57593 # Per bank write bursts
< system.physmem.perBankRdBursts::7 57551 # Per bank write bursts
< system.physmem.perBankRdBursts::8 45941 # Per bank write bursts
< system.physmem.perBankRdBursts::9 94599 # Per bank write bursts
< system.physmem.perBankRdBursts::10 49635 # Per bank write bursts
< system.physmem.perBankRdBursts::11 57294 # Per bank write bursts
< system.physmem.perBankRdBursts::12 48522 # Per bank write bursts
< system.physmem.perBankRdBursts::13 56965 # Per bank write bursts
< system.physmem.perBankRdBursts::14 52794 # Per bank write bursts
< system.physmem.perBankRdBursts::15 56368 # Per bank write bursts
< system.physmem.perBankWrBursts::0 71875 # Per bank write bursts
< system.physmem.perBankWrBursts::1 75753 # Per bank write bursts
< system.physmem.perBankWrBursts::2 71549 # Per bank write bursts
< system.physmem.perBankWrBursts::3 77042 # Per bank write bursts
< system.physmem.perBankWrBursts::4 73392 # Per bank write bursts
< system.physmem.perBankWrBursts::5 80022 # Per bank write bursts
< system.physmem.perBankWrBursts::6 71461 # Per bank write bursts
< system.physmem.perBankWrBursts::7 73088 # Per bank write bursts
< system.physmem.perBankWrBursts::8 65465 # Per bank write bursts
< system.physmem.perBankWrBursts::9 74249 # Per bank write bursts
< system.physmem.perBankWrBursts::10 70475 # Per bank write bursts
< system.physmem.perBankWrBursts::11 74236 # Per bank write bursts
< system.physmem.perBankWrBursts::12 69250 # Per bank write bursts
< system.physmem.perBankWrBursts::13 75271 # Per bank write bursts
< system.physmem.perBankWrBursts::14 70641 # Per bank write bursts
< system.physmem.perBankWrBursts::15 74378 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 50443 # Per bank write bursts
> system.physmem.perBankRdBursts::1 58279 # Per bank write bursts
> system.physmem.perBankRdBursts::2 46176 # Per bank write bursts
> system.physmem.perBankRdBursts::3 52637 # Per bank write bursts
> system.physmem.perBankRdBursts::4 47826 # Per bank write bursts
> system.physmem.perBankRdBursts::5 55648 # Per bank write bursts
> system.physmem.perBankRdBursts::6 52176 # Per bank write bursts
> system.physmem.perBankRdBursts::7 51274 # Per bank write bursts
> system.physmem.perBankRdBursts::8 44248 # Per bank write bursts
> system.physmem.perBankRdBursts::9 55412 # Per bank write bursts
> system.physmem.perBankRdBursts::10 43487 # Per bank write bursts
> system.physmem.perBankRdBursts::11 55151 # Per bank write bursts
> system.physmem.perBankRdBursts::12 50800 # Per bank write bursts
> system.physmem.perBankRdBursts::13 57431 # Per bank write bursts
> system.physmem.perBankRdBursts::14 46539 # Per bank write bursts
> system.physmem.perBankRdBursts::15 47507 # Per bank write bursts
> system.physmem.perBankWrBursts::0 68734 # Per bank write bursts
> system.physmem.perBankWrBursts::1 74075 # Per bank write bursts
> system.physmem.perBankWrBursts::2 65910 # Per bank write bursts
> system.physmem.perBankWrBursts::3 69531 # Per bank write bursts
> system.physmem.perBankWrBursts::4 66080 # Per bank write bursts
> system.physmem.perBankWrBursts::5 73115 # Per bank write bursts
> system.physmem.perBankWrBursts::6 69817 # Per bank write bursts
> system.physmem.perBankWrBursts::7 69743 # Per bank write bursts
> system.physmem.perBankWrBursts::8 63555 # Per bank write bursts
> system.physmem.perBankWrBursts::9 71485 # Per bank write bursts
> system.physmem.perBankWrBursts::10 64662 # Per bank write bursts
> system.physmem.perBankWrBursts::11 72406 # Per bank write bursts
> system.physmem.perBankWrBursts::12 68380 # Per bank write bursts
> system.physmem.perBankWrBursts::13 74722 # Per bank write bursts
> system.physmem.perBankWrBursts::14 65945 # Per bank write bursts
> system.physmem.perBankWrBursts::15 69295 # Per bank write bursts
129,130c129,130
< system.physmem.numWrRetry 399 # Number of times write queue was full causing retry
< system.physmem.totGap 47405077592000 # Total gap between requests
---
> system.physmem.numWrRetry 463 # Number of times write queue was full causing retry
> system.physmem.totGap 47401367297000 # Total gap between requests
133c133
< system.physmem.readPktSize::2 43195 # Read request sizes (log2)
---
> system.physmem.readPktSize::2 4795 # Read request sizes (log2)
137c137
< system.physmem.readPktSize::6 884251 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 810587 # Read request sizes (log2)
144,163c144,163
< system.physmem.writePktSize::6 1167872 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 648346 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 87693 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 41445 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 33200 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 28689 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 25203 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 22073 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 18329 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 15555 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2733 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1025 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 772 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 592 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 417 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 272 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 219 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 187 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 159 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 104 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1107186 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 559891 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 78604 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 37389 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 30365 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 26588 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 23379 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 20454 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 17072 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 14604 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2581 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1059 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 789 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 635 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 471 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 255 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 170 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see
165,166c165,166
< system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
192,295c192,317
< system.physmem.wrQLenPdf::15 28770 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 36931 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 48299 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 54487 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 61032 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 63693 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 65505 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 67515 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 70215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 70242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 73447 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 75382 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 72205 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 70493 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 71352 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 75176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 68341 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 65445 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 3675 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 2020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1597 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 1000 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 958 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 839 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 771 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 710 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 701 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 747 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 686 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 747 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 673 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 670 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 663 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 668 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 587 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 676 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 672 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 672 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 955 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 727 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 585 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 1023 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 1347 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 1254 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 573 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 921 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 928498 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 144.423393 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 98.327252 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 191.341879 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 616929 66.44% 66.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 189662 20.43% 86.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 44616 4.81% 91.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 20270 2.18% 93.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 14755 1.59% 95.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 9179 0.99% 96.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 6168 0.66% 97.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5453 0.59% 97.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 21466 2.31% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 928498 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 60682 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 15.278254 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 130.725132 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 60680 100.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 60682 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.250305 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.439777 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 8.504538 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 53685 88.47% 88.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 4623 7.62% 96.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 1219 2.01% 98.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 192 0.32% 98.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 86 0.14% 98.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 66 0.11% 98.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 562 0.93% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 118 0.19% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 38 0.06% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 2 0.00% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 5 0.01% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 14 0.02% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 2 0.00% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 2 0.00% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 28 0.05% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 15 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 2 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-159 2 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-167 1 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 2 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 6 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 5 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 5 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads
< system.physmem.totQLat 46391884854 # Total ticks spent queuing
< system.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::15 27848 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 35713 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 46446 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 51674 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 57512 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 59733 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 61607 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 63717 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 66102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 66334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 69492 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 71245 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 67739 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 66506 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 67172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 70520 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 64778 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 61855 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 3835 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1949 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1570 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1271 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 993 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 955 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 864 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 764 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 797 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 853 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 725 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 779 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 736 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 651 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 706 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 626 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 643 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 783 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 761 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 1111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 881 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 672 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 1107 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 1228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 1273 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 618 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1057 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 862223 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 142.699715 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 97.984234 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 187.236614 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 572247 66.37% 66.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 178435 20.69% 87.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 41649 4.83% 91.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 18745 2.17% 94.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 13461 1.56% 95.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 8413 0.98% 96.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 6049 0.70% 97.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5161 0.60% 97.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 18063 2.09% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 862223 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 57012 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 14.295727 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 26.624569 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-255 57003 99.98% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::256-511 3 0.01% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-767 3 0.01% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1280-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 57012 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 57012 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 19.424946 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.563445 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 8.850614 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 45452 79.72% 79.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 4610 8.09% 87.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 2793 4.90% 92.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 1774 3.11% 95.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 1007 1.77% 97.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 224 0.39% 97.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 148 0.26% 98.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 47 0.08% 98.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 57 0.10% 98.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 22 0.04% 98.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 26 0.05% 98.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 34 0.06% 98.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 476 0.83% 99.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 79 0.14% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 57 0.10% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 65 0.11% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 45 0.08% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.00% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 2 0.00% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 3 0.01% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.00% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 12 0.02% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 4 0.01% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 2 0.00% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 16 0.03% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 7 0.01% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 4 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 5 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 3 0.01% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 3 0.01% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 1 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 3 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 2 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 9 0.02% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 57012 # Writes before turning the bus around for reads
> system.physmem.totQLat 43191913053 # Total ticks spent queuing
> system.physmem.totMemAccLat 58473800553 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 4075170000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 52994.00 # Average queueing delay per DRAM burst
297,301c319,323
< system.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 71744.00 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s
307,352c329,374
< system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing
< system.physmem.readRowHits 687053 # Number of row buffer hits during reads
< system.physmem.writeRowHits 479716 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes
< system.physmem.avgGap 22596205.96 # Average gap between requests
< system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ)
< system.physmem_0.averagePower 243.004907 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states
< system.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ)
< system.physmem_1.averagePower 242.918480 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states
< system.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing
> system.physmem.readRowHits 599171 # Number of row buffer hits during reads
> system.physmem.writeRowHits 461094 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 73.51 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes
> system.physmem.avgGap 24621886.93 # Average gap between requests
> system.physmem.pageHitRate 55.15 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3125163720 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1661060115 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 2959237260 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 2907566100 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 39767208000.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 44841459390 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 2203203840 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 73351636740 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 56747456160 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 11284217805975 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 11511799212150 # Total energy per rank (pJ)
> system.physmem_0.averagePower 242.857940 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 47297258186903 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 3926700752 # Time in different power states
> system.physmem_0.memoryStateTime::REF 16898782000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 46988619115750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 147779602583 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 83286870095 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 160859516320 # Time in different power states
> system.physmem_1.actEnergy 3031115640 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1611076170 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 2860105500 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 2873349000 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 40284120240.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 45341107710 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 2193321120 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 73446933900 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 57703512480 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 11283525763155 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 11512888807215 # Total energy per rank (pJ)
> system.physmem_1.averagePower 242.880926 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 47296183842356 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 3879016799 # Time in different power states
> system.physmem_1.memoryStateTime::REF 17119770000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 46984848194500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 150269925291 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 84186543595 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 161067137315 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
379,381c401,403
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
389c411
< system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
419,428c441,450
< system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.dtb.walker.walks 105104 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.dtb.walker.walks 92556 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 92556 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8240 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 69143 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 92545 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 0.280944 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 85.466687 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-2047 92544 100.00% 100.00% # Table walker wait (enqueue to first request) latency
430,443c452,464
< system.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walkWaitTime::total 92545 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 77394 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 23265.414632 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 21722.582011 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 14143.873172 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 76797 99.23% 99.23% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 427 0.55% 99.78% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 102 0.13% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 27 0.03% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 20 0.03% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
445,456c466,476
< system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkCompletionTime::total 77394 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 6740631600 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.619851 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.485423 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0 2562444572 38.01% 38.01% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::1 4178187028 61.99% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 6740631600 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 69143 89.35% 89.35% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 8240 10.65% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 77383 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 92556 # Table walker requests started/completed, data/inst
458,459c478,479
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 92556 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77383 # Table walker requests started/completed, data/inst
461,462c481,482
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77383 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 169939 # Table walker requests started/completed, data/inst
465,468c485,488
< system.cpu0.dtb.read_hits 85250979 # DTB read hits
< system.cpu0.dtb.read_misses 79026 # DTB read misses
< system.cpu0.dtb.write_hits 77401552 # DTB write hits
< system.cpu0.dtb.write_misses 26078 # DTB write misses
---
> system.cpu0.dtb.read_hits 77415423 # DTB read hits
> system.cpu0.dtb.read_misses 69730 # DTB read misses
> system.cpu0.dtb.write_hits 70114940 # DTB write hits
> system.cpu0.dtb.write_misses 22826 # DTB write misses
471,473c491,493
< system.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 34306 # Number of entries that have been flushed from TLB
475c495
< system.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 3960 # Number of TLB faults due to prefetch
477,479c497,499
< system.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 85330005 # DTB read accesses
< system.cpu0.dtb.write_accesses 77427630 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 8638 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 77485153 # DTB read accesses
> system.cpu0.dtb.write_accesses 70137766 # DTB write accesses
481,484c501,504
< system.cpu0.dtb.hits 162652531 # DTB hits
< system.cpu0.dtb.misses 105104 # DTB misses
< system.cpu0.dtb.accesses 162757635 # DTB accesses
< system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dtb.hits 147530363 # DTB hits
> system.cpu0.dtb.misses 92556 # DTB misses
> system.cpu0.dtb.accesses 147622919 # DTB accesses
> system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
514,542c534,562
< system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.itb.walker.walks 55600 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated
---
> system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.itb.walker.walks 51144 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 51144 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 535 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 45125 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 51144 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 51144 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 51144 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 45660 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 24927.069645 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 23080.556454 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 20288.256560 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 45087 98.75% 98.75% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 348 0.76% 99.51% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 137 0.30% 99.81% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 34 0.07% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.04% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::589824-655359 16 0.04% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 45660 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 618561500 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 618561500 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 618561500 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 45125 98.83% 98.83% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 535 1.17% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 45660 # Table walker page sizes translated
544,545c564,565
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 51144 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 51144 # Table walker requests started/completed, data/inst
547,551c567,571
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 455710659 # ITB inst hits
< system.cpu0.itb.inst_misses 55600 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 45660 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 45660 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 96804 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 385005651 # ITB inst hits
> system.cpu0.itb.inst_misses 51144 # ITB inst misses
558,560c578,580
< system.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 24319 # Number of entries that have been flushed from TLB
567,590c587,610
< system.cpu0.itb.inst_accesses 455766259 # ITB inst accesses
< system.cpu0.itb.hits 455710659 # DTB hits
< system.cpu0.itb.misses 55600 # DTB misses
< system.cpu0.itb.accesses 455766259 # DTB accesses
< system.cpu0.numPwrStateTransitions 25961 # Number of power state transitions
< system.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states
< system.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states
< system.cpu0.numCycles 94809604801 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 385056795 # ITB inst accesses
> system.cpu0.itb.hits 385005651 # DTB hits
> system.cpu0.itb.misses 51144 # DTB misses
> system.cpu0.itb.accesses 385056795 # DTB accesses
> system.cpu0.numPwrStateTransitions 8306 # Number of power state transitions
> system.cpu0.pwrStateClkGateDist::samples 4153 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::mean 11295325194.838190 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::stdev 176339050181.920959 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::underflows 2776 66.84% 66.84% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1000-5e+10 1353 32.58% 99.42% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.14% 99.57% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.59% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::overflows 12 0.29% 100.00% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::max_value 6953821743500 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::total 4153 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateResidencyTicks::ON 491885053337 # Cumulative time (in ticks) in various power states
> system.cpu0.pwrStateResidencyTicks::CLK_GATED 46909485534163 # Cumulative time (in ticks) in various power states
> system.cpu0.numCycles 94802741175 # number of cpu cycles simulated
594,616c614,636
< system.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed
< system.cpu0.committedInsts 455440444 # Number of instructions committed
< system.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses
< system.cpu0.num_func_calls 27345084 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 490602455 # number of integer instructions
< system.cpu0.num_fp_insts 409464 # number of float instructions
< system.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written
< system.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written
< system.cpu0.num_mem_refs 162644052 # number of memory refs
< system.cpu0.num_load_insts 85246888 # Number of load instructions
< system.cpu0.num_store_insts 77397164 # Number of store instructions
< system.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles
< system.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.988028 # Percentage of idle cycles
< system.cpu0.Branches 101837898 # Number of branches fetched
---
> system.cpu0.kern.inst.quiesce 4153 # number of quiesce instructions executed
> system.cpu0.committedInsts 384730653 # Number of instructions committed
> system.cpu0.committedOps 456411878 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 424236423 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 341428 # Number of float alu accesses
> system.cpu0.num_func_calls 24795410 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 55287954 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 424236423 # number of integer instructions
> system.cpu0.num_fp_insts 341428 # number of float instructions
> system.cpu0.num_int_register_reads 565685630 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 332181203 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 574384 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 236428 # number of times the floating registers were written
> system.cpu0.num_cc_register_reads 85999446 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 85681176 # number of times the CC registers were written
> system.cpu0.num_mem_refs 147523428 # number of memory refs
> system.cpu0.num_load_insts 77412307 # Number of load instructions
> system.cpu0.num_store_insts 70111121 # Number of store instructions
> system.cpu0.num_idle_cycles 93818971068.324020 # Number of idle cycles
> system.cpu0.num_busy_cycles 983770106.675979 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.010377 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.989623 # Percentage of idle cycles
> system.cpu0.Branches 84896632 # Number of branches fetched
618,652c638,672
< system.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction
< system.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction
< system.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction
< system.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction
< system.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction
< system.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction
< system.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 307975543 67.44% 67.44% # Class of executed instruction
> system.cpu0.op_class::IntMult 1108929 0.24% 67.68% # Class of executed instruction
> system.cpu0.op_class::IntDiv 55110 0.01% 67.69% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 67.69% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 67.69% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 67.69% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 67.69% # Class of executed instruction
> system.cpu0.op_class::FloatMultAcc 0 0.00% 67.69% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 67.69% # Class of executed instruction
> system.cpu0.op_class::FloatMisc 28590 0.01% 67.70% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMult 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.70% # Class of executed instruction
> system.cpu0.op_class::MemRead 77373487 16.94% 84.64% # Class of executed instruction
> system.cpu0.op_class::MemWrite 69837103 15.29% 99.93% # Class of executed instruction
> system.cpu0.op_class::FloatMemRead 38820 0.01% 99.94% # Class of executed instruction
> system.cpu0.op_class::FloatMemWrite 274018 0.06% 100.00% # Class of executed instruction
655,762c675,784
< system.cpu0.op_class::total 534571495 # Class of executed instruction
< system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.tags.replacements 5548235 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.308001 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992789 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.992789 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 330814481 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 330814481 # Number of data accesses
< system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.ReadReq_hits::cpu0.data 79405965 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 79405965 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 72971377 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 72971377 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204972 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 204972 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263219 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 263219 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813440 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1813440 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787735 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1787735 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 152640561 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 152640561 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 152845533 # number of overall hits
< system.cpu0.dcache.overall_hits::total 152845533 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 3006341 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 3006341 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1360477 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1360477 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 626311 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 626311 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 794287 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 794287 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164142 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 164142 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188530 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 188530 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 5161105 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 5161105 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 5787416 # number of overall misses
< system.cpu0.dcache.overall_misses::total 5787416 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47850868000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 47850868000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29377875000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 29377875000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25259415500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 25259415500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2486803500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 2486803500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4498365000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4498365000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2057500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2057500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 102488158500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 102488158500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 102488158500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 102488158500 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 82412306 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 82412306 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 74331854 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 74331854 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 831283 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 831283 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1057506 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 1057506 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1977582 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 1977582 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1976265 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 1976265 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 157801666 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 157801666 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 158632949 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 158632949 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036479 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.036479 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018303 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.018303 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.753427 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.753427 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.751095 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.751095 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083001 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083001 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095397 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095397 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032706 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.032706 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036483 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.036483 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21593.804967 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 21593.804967 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31801.370915 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31801.370915 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15150.318017 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15150.318017 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23860.207924 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency
---
> system.cpu0.op_class::total 456691600 # Class of executed instruction
> system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.tags.replacements 5013046 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 470.143979 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 142293396 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 5013556 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 28.381731 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 637122000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.143979 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.918250 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.918250 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 300094424 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 300094424 # Number of data accesses
> system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.ReadReq_hits::cpu0.data 72133805 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 72133805 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 66092358 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 66092358 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186275 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 186275 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 227046 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 227046 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1654353 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1654353 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1603859 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1603859 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 138453209 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 138453209 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 138639484 # number of overall hits
> system.cpu0.dcache.overall_hits::total 138639484 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 2704079 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 2704079 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1255388 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1255388 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 579222 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 579222 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 722220 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 722220 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141818 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 141818 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191065 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 191065 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 4681687 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 4681687 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 5260909 # number of overall misses
> system.cpu0.dcache.overall_misses::total 5260909 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41586194000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 41586194000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27254591500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 27254591500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 23833661500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 23833661500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2088985000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 2088985000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536311000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4536311000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2828500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2828500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 92674447000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 92674447000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 92674447000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 92674447000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 74837884 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 74837884 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 67347746 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 67347746 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 765497 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 765497 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 949266 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 949266 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1796171 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 1796171 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1794924 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 1794924 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 143134896 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 143134896 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 143900393 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 143900393 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036132 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.036132 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018640 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.018640 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756661 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756661 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760819 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760819 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078956 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078956 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.106447 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.106447 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032708 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.032708 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036559 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.036559 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15379.060301 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 15379.060301 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21710.094011 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 21710.094011 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33000.555925 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33000.555925 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.041321 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.041321 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23742.239552 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23742.239552 # average StoreCondReq miss latency
765,768c787,790
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19857.793728 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 19857.793728 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17708.794132 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19795.096725 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19795.096725 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17615.671930 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 17615.671930 # average overall miss latency
775,858c797,880
< system.cpu0.dcache.writebacks::writebacks 5548235 # number of writebacks
< system.cpu0.dcache.writebacks::total 5548235 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26826 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 26826 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21220 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 21220 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43038 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43038 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 48046 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 48046 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 48046 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 48046 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2979515 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 2979515 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1339257 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1339257 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 624730 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 624730 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 794287 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 794287 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121104 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188530 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 188530 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 5113059 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 5113059 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 5737789 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 5737789 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59187 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43367868500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43367868500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27478579500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27478579500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14655261000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14655261000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24465128500 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24465128500 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1605767000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4309885000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4309885000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2007500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2007500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95311576500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 95311576500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109966837500 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 109966837500 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5687970000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018017 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018017 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.751525 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751525 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.751095 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.751095 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061238 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061238 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095397 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095397 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032402 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.032402 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036170 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.036170 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14555.344914 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14555.344914 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20517.779261 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20517.779261 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23458.551694 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30801.370915 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30801.370915 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13259.405139 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22860.473134 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22860.473134 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 5013046 # number of writebacks
> system.cpu0.dcache.writebacks::total 5013046 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26558 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 26558 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21241 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 21241 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 37285 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 37285 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 47799 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 47799 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 47799 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 47799 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2677521 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 2677521 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1234147 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1234147 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 577585 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 577585 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 722220 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 722220 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104533 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104533 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191065 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 191065 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 4633888 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 4633888 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 5211473 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 5211473 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15891 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32691 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37485691500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37485691500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25473400500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25473400500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13565827500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13565827500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 23111441500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 23111441500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1404174500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1404174500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4345314000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4345314000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2760500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 86070533500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 86070533500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 99636361000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 99636361000 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2929733500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2929733500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2929733500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2929733500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035778 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035778 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018325 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018325 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754523 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754523 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760819 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760819 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058198 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058198 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.106447 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.106447 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032374 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.032374 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036216 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.036216 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14000.148458 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14000.148458 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20640.491368 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20640.491368 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23487.153406 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23487.153406 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32000.555925 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32000.555925 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13432.834607 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13432.834607 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22742.595452 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22742.595452 # average StoreCondReq mshr miss latency
861,878c883,900
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18640.812965 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18640.812965 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19165.367967 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19165.367967 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190692.302535 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190692.302535 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96101.677733 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96101.677733 # average overall mshr uncacheable latency
< system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.tags.replacements 4928137 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.903899 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 450782010 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 4928649 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 91.461577 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 30794452000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903899 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18574.150584 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18574.150584 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.656280 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19118.656280 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184364.325719 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184364.325719 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89618.962406 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89618.962406 # average overall mshr uncacheable latency
> system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.tags.replacements 4327935 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.943806 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 380677204 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 4328447 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 87.947757 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 27073430000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.943806 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999890 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999890 # Average percentage of cache occupancy
880,881c902,905
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
883,921c907,945
< system.cpu0.icache.tags.tag_accesses 916349967 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 916349967 # Number of data accesses
< system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.ReadReq_hits::cpu0.inst 450782010 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 450782010 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 450782010 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 450782010 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 450782010 # number of overall hits
< system.cpu0.icache.overall_hits::total 450782010 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 4928649 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 4928649 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 4928649 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 4928649 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 4928649 # number of overall misses
< system.cpu0.icache.overall_misses::total 4928649 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54016215500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 54016215500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 54016215500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 54016215500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 54016215500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 54016215500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 455710659 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 455710659 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 455710659 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 455710659 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 455710659 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 455710659 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010815 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.010815 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010815 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.010815 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010815 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.010815 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10959.639345 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10959.639345 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10959.639345 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10959.639345 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 774339749 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 774339749 # Number of data accesses
> system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.ReadReq_hits::cpu0.inst 380677204 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 380677204 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 380677204 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 380677204 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 380677204 # number of overall hits
> system.cpu0.icache.overall_hits::total 380677204 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 4328447 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 4328447 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 4328447 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 4328447 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 4328447 # number of overall misses
> system.cpu0.icache.overall_misses::total 4328447 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47943054500 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 47943054500 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 47943054500 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 47943054500 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 47943054500 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 47943054500 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 385005651 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 385005651 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 385005651 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 385005651 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 385005651 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 385005651 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011243 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.011243 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011243 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.011243 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011243 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.011243 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11076.271582 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 11076.271582 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 11076.271582 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 11076.271582 # average overall miss latency
928,969c952,993
< system.cpu0.icache.writebacks::writebacks 4928137 # number of writebacks
< system.cpu0.icache.writebacks::total 4928137 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4928649 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 4928649 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 4928649 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 4928649 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 4928649 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 4928649 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
< system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
< system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
< system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51551891000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 51551891000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51551891000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 51551891000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51551891000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 51551891000 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010815 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.010815 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.010815 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10459.639345 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency
< system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 7424522 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 7424525 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.icache.writebacks::writebacks 4327935 # number of writebacks
> system.cpu0.icache.writebacks::total 4327935 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4328447 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 4328447 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 4328447 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 4328447 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 4328447 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 4328447 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.ReadReq_mshr_uncacheable::total 4725 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses
> system.cpu0.icache.overall_mshr_uncacheable_misses::total 4725 # number of overall MSHR uncacheable misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45778831000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 45778831000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45778831000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 45778831000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45778831000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 45778831000 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 463686000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 463686000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 463686000 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 463686000 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011243 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.011243 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.011243 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10576.271582 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98134.603175 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98134.603175 # average overall mshr uncacheable latency
> system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 7077148 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 7077156 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
972,1119c996,1144
< system.cpu0.l2cache.prefetcher.pfSpanPage 998915 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.tags.replacements 2238289 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 15477.322343 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 8961437 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2253120 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 3.977346 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 5406108500 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 15186.002225 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.160912 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.574333 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.584873 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.926880 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001963 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001622 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014196 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.944661 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 343 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14429 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8440 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4747 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020935 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880676 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 361005368 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 361005368 # Number of data accesses
< system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 239188 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140105 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 379293 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 3693855 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 3693855 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 6781361 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 6781361 # number of WritebackClean hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 879738 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 879738 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4485760 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 4485760 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2821736 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 2821736 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211609 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 211609 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 239188 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140105 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 4485760 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 3701474 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 8566527 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 239188 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140105 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 4485760 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 3701474 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 8566527 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16649 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8661 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 25310 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 231687 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 231687 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 188526 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 188526 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 243594 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 243594 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 442889 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 442889 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 903613 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 903613 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582678 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 582678 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 16649 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8661 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 442889 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1147207 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 1615406 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 16649 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8661 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 442889 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1147207 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 1615406 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 524453500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 332493500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 856947000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 896560000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 896560000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 330254000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 330254000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1931999 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1931999 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13649420499 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 13649420499 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17214501500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17214501500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35658673000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 35658673000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 429500 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 429500 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 524453500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 332493500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17214501500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 49308093499 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 67379541999 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 524453500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 332493500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17214501500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 49308093499 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 67379541999 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 255837 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148766 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 404603 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3693855 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 3693855 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 6781361 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 6781361 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231687 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 231687 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188526 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 188526 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1123332 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1123332 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4928649 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 4928649 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3725349 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 3725349 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794287 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 794287 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 255837 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148766 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 4928649 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 4848681 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 10181933 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 255837 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148766 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 4928649 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 4848681 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 10181933 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058219 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.062555 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 919708 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.tags.replacements 2034832 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 15580.971228 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 7927218 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2050121 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 3.866707 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 1712003500 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 15267.042973 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.154482 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 11.284107 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 280.489666 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.931826 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001352 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000689 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.017120 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.950987 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 305 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14912 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 65 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 109 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 131 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 540 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4190 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7117 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2983 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018616 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.910156 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 322659786 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 322659786 # Number of data accesses
> system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 205975 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128170 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 334145 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 3330860 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 3330860 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 6009144 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 6009144 # number of WritebackClean hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 802570 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 802570 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 3917036 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 3917036 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2528867 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 2528867 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 164054 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 164054 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 205975 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 128170 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 3917036 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 3331437 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 7582618 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 205975 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 128170 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 3917036 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 3331437 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 7582618 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 15216 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8071 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 23287 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 218667 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 218667 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 191059 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 191059 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 228793 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 228793 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 411411 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 411411 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 830772 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 830772 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 558166 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 558166 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 15216 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8071 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 411411 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1059565 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 1494263 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 15216 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8071 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 411411 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1059565 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 1494263 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 436278500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 272723500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 709002000 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 867672000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 867672000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 318347000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 318347000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2656998 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2656998 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12612589500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 12612589500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 15771055500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 15771055500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 30943358500 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 30943358500 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 436278500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 272723500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15771055500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 43555948000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 60036005500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 436278500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 272723500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15771055500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 43555948000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 60036005500 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 221191 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 136241 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 357432 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3330860 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 3330860 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 6009144 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 6009144 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218667 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 218667 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 191059 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 191059 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1031363 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1031363 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4328447 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 4328447 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3359639 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 3359639 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 722220 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 722220 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 221191 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 136241 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 4328447 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 4391002 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 9076881 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 221191 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 136241 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 4328447 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 4391002 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 9076881 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059241 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.065151 # miss rate for ReadReq accesses
1126,1170c1151,1193
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.216850 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.216850 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089860 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089860 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242558 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242558 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733586 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733586 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058219 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089860 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.236602 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.158654 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058219 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089860 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.236602 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.158654 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38389.735596 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33858.040300 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3869.703522 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3869.703522 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1751.768987 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1751.768987 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 482999.750000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 482999.750000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56033.483990 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56033.483990 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38868.658964 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38868.658964 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39462.328453 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39462.328453 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.737114 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.737114 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 41710.592878 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 41710.592878 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.221836 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.221836 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.095048 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.095048 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.247280 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.247280 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.772848 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.772848 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059241 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.095048 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241304 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.164623 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059241 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.095048 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241304 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.164623 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33790.546401 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30446.257569 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3968.006146 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3968.006146 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1666.223523 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1666.223523 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 442833 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 442833 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55126.640675 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55126.640675 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38334.063746 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38334.063746 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37246.511076 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37246.511076 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 40177.669861 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 40177.669861 # average overall miss latency
1177,1266c1200,1287
< system.cpu0.l2cache.unused_prefetches 36707 # number of HardPF blocks evicted w/o reference
< system.cpu0.l2cache.writebacks::writebacks 1501692 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1501692 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6241 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 6241 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 600 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 600 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 1 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6841 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 6841 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6841 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 6841 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 16649 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8661 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 25310 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 726594 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 231687 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 231687 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 188526 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 188526 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 237353 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 237353 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 442889 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 442889 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 903013 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 903013 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 582677 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 582677 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 16649 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8661 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 442889 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1140366 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 1608565 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 16649 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8661 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 442889 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1140366 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2335159 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72953 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 102312 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 280527500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 705087000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37258472903 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4314197500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4314197500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2894861999 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2894861999 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1631999 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1631999 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11516279999 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11516279999 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14557167500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14557167500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30162372000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30162372000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18401745500 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18401745500 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 280527500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14557167500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 41678651999 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 56940906499 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 280527500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14557167500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 41678651999 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 94199379402 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5448952500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9242049000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5448952500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9242049000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062555 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.unused_prefetches 34479 # number of HardPF blocks evicted w/o reference
> system.cpu0.l2cache.writebacks::writebacks 1361012 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1361012 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5370 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 5370 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 489 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 489 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5859 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 5859 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5859 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 5859 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 15216 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8071 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 23287 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 675054 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 218667 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 218667 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 191059 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 191059 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 223423 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 223423 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 411411 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 411411 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 830283 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 830283 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 558166 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 558166 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 15216 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8071 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 411411 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1053706 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 1488404 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 15216 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8071 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 411411 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1053706 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2163458 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20616 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37416 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 224297500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 569280000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32033056811 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4084370000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4084370000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2911469499 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2911469499 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2248998 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2248998 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10644364000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10644364000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 13302589500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 13302589500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 25893671500 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 25893671500 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 17612762500 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 17612762500 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 224297500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13302589500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36538035500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 50409905000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 224297500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13302589500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36538035500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 82442961811 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 428248500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2802283500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3230532000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 428248500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2802283500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 3230532000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065151 # mshr miss rate for ReadReq accesses
1275,1291c1296,1312
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.211294 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.211294 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089860 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242397 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242397 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.733585 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.733585 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157982 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216629 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216629 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095048 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247135 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247135 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772848 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772848 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163977 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for overall accesses
1293,1334c1314,1355
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229343 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27858.040300 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51278.255674 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18620.800908 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18620.800908 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15355.240121 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15355.240121 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 407999.750000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 407999.750000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48519.631094 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48519.631094 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32868.658964 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33401.924446 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33401.924446 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31581.382996 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency
< system.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.238348 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24446.257569 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 47452.584254 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18678.492868 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18678.492868 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15238.588598 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15238.588598 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 374833 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 374833 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 47642.203354 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 47642.203354 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32334.063746 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31186.561088 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31186.561088 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31554.703260 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31554.703260 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33868.428867 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38107.031341 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176344.062677 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156700.232829 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85720.335872 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86340.923669 # average overall mshr uncacheable latency
> system.cpu0.toL2Bus.snoop_filter.tot_requests 19414965 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 9975279 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 976 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 578988 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 578988 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1336,1370c1357,1391
< system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 5091046 # Total snoops (count)
< system.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes)
< system.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram
---
> system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu0.toL2Bus.trans_dist::ReadReq 442233 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 8226522 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 16801 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 16800 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 4707887 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 6010120 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 978928 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 831060 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 419258 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 359151 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 478987 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1069161 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1041370 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4328447 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4301809 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 793195 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 723551 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12994279 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16301256 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 289006 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 490041 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 30074582 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 554027348 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 608753046 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1089928 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1769528 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1165639850 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 4847803 # Total snoops (count)
> system.cpu0.toL2Bus.snoopTraffic 95443532 # Total snoop traffic (bytes)
> system.cpu0.toL2Bus.snoop_fanout::samples 14917131 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.053800 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.225623 # Request fanout histogram
1372,1373c1393,1394
< system.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 14114583 94.62% 94.62% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 802548 5.38% 100.00% # Request fanout histogram
1378,1379c1399,1400
< system.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 14917131 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 19175088002 # Layer occupancy (ticks)
1381c1402
< system.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 194853286 # Layer occupancy (ticks)
1383c1404
< system.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 6497395500 # Layer occupancy (ticks)
1385c1406
< system.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 7177011173 # Layer occupancy (ticks)
1387c1408
< system.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 152765499 # Layer occupancy (ticks)
1389c1410
< system.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 268850499 # Layer occupancy (ticks)
1391c1412
< system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
1421,1430c1442,1451
< system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.dtb.walker.walks 105151 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.dtb.walker.walks 108097 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 108097 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9121 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84193 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 108080 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 0.074019 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 24.334214 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-511 108079 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1432,1441c1453,1462
< system.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walkWaitTime::total 108080 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 93331 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 24327.977842 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 22238.306429 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 18706.694176 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 92079 98.66% 98.66% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 920 0.99% 99.64% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 176 0.19% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 54 0.06% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.05% 99.94% # Table walker service (enqueue to completion) latency
1443,1458c1464,1479
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 93331 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 5379088140 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.979144 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.142902 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 112185648 2.09% 2.09% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::1 5266902492 97.91% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 5379088140 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 84194 90.23% 90.23% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 9121 9.77% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 93315 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108097 # Table walker requests started/completed, data/inst
1460,1461c1481,1482
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108097 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93315 # Table walker requests started/completed, data/inst
1463,1464c1484,1485
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93315 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 201412 # Table walker requests started/completed, data/inst
1467,1470c1488,1491
< system.cpu1.dtb.read_hits 80227147 # DTB read hits
< system.cpu1.dtb.read_misses 76874 # DTB read misses
< system.cpu1.dtb.write_hits 72873093 # DTB write hits
< system.cpu1.dtb.write_misses 28277 # DTB write misses
---
> system.cpu1.dtb.read_hits 86913541 # DTB read hits
> system.cpu1.dtb.read_misses 78813 # DTB read misses
> system.cpu1.dtb.write_hits 79382446 # DTB write hits
> system.cpu1.dtb.write_misses 29284 # DTB write misses
1473,1475c1494,1496
< system.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 38404 # Number of entries that have been flushed from TLB
1477c1498
< system.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 4493 # Number of TLB faults due to prefetch
1479,1481c1500,1502
< system.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 80304021 # DTB read accesses
< system.cpu1.dtb.write_accesses 72901370 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 10593 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 86992354 # DTB read accesses
> system.cpu1.dtb.write_accesses 79411730 # DTB write accesses
1483,1486c1504,1507
< system.cpu1.dtb.hits 153100240 # DTB hits
< system.cpu1.dtb.misses 105151 # DTB misses
< system.cpu1.dtb.accesses 153205391 # DTB accesses
< system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dtb.hits 166295987 # DTB hits
> system.cpu1.dtb.misses 108097 # DTB misses
> system.cpu1.dtb.accesses 166404084 # DTB accesses
> system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
1516,1537c1537,1557
< system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.itb.walker.walks 60537 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.itb.walker.walks 67294 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 67294 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61475 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 67294 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 67294 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 67294 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 62101 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 26137.727251 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 23789.803797 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 22700.198457 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 60815 97.93% 97.93% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 864 1.39% 99.32% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 247 0.40% 99.72% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 72 0.12% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::589824-655359 23 0.04% 100.00% # Table walker service (enqueue to completion) latency
1539,1545c1559,1565
< system.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walkCompletionTime::total 62101 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples -17274852 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 -17274852 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total -17274852 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 61475 98.99% 98.99% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 626 1.01% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 62101 # Table walker page sizes translated
1547,1548c1567,1568
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67294 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67294 # Table walker requests started/completed, data/inst
1550,1554c1570,1574
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 423099313 # ITB inst hits
< system.cpu1.itb.inst_misses 60537 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62101 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62101 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 129395 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 422829218 # ITB inst hits
> system.cpu1.itb.inst_misses 67294 # ITB inst misses
1561,1563c1581,1583
< system.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 27014 # Number of entries that have been flushed from TLB
1570,1584c1590,1608
< system.cpu1.itb.inst_accesses 423159850 # ITB inst accesses
< system.cpu1.itb.hits 423099313 # DTB hits
< system.cpu1.itb.misses 60537 # DTB misses
< system.cpu1.itb.accesses 423159850 # DTB accesses
< system.cpu1.numPwrStateTransitions 11486 # Number of power state transitions
< system.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state
---
> system.cpu1.itb.inst_accesses 422896512 # ITB inst accesses
> system.cpu1.itb.hits 422829218 # DTB hits
> system.cpu1.itb.misses 67294 # DTB misses
> system.cpu1.itb.accesses 422896512 # DTB accesses
> system.cpu1.numPwrStateTransitions 29136 # Number of power state transitions
> system.cpu1.pwrStateClkGateDist::samples 14568 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::mean 3216976278.654242 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::stdev 84611127659.505341 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::underflows 4387 30.11% 30.11% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1000-5e+10 10152 69.69% 99.80% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.84% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
1586,1590c1610,1614
< system.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states
< system.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states
< system.cpu1.numCycles 94810161765 # number of cpu cycles simulated
---
> system.cpu1.pwrStateClkGateDist::max_value 7390879628476 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::total 14568 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateResidencyTicks::ON 536460160065 # Cumulative time (in ticks) in various power states
> system.cpu1.pwrStateResidencyTicks::CLK_GATED 46864910427435 # Cumulative time (in ticks) in various power states
> system.cpu1.numCycles 94802741175 # number of cpu cycles simulated
1594,1616c1618,1640
< system.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed
< system.cpu1.committedInsts 422818462 # Number of instructions committed
< system.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses
< system.cpu1.num_func_calls 25225246 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 458669371 # number of integer instructions
< system.cpu1.num_fp_insts 488965 # number of float instructions
< system.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read
< system.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written
< system.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written
< system.cpu1.num_mem_refs 153090665 # number of memory refs
< system.cpu1.num_load_insts 80223644 # Number of load instructions
< system.cpu1.num_store_insts 72867021 # Number of store instructions
< system.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles
< system.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.989313 # Percentage of idle cycles
< system.cpu1.Branches 94103649 # Number of branches fetched
---
> system.cpu1.kern.inst.quiesce 14568 # number of quiesce instructions executed
> system.cpu1.committedInsts 422521065 # Number of instructions committed
> system.cpu1.committedOps 504842112 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 470472983 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 594254 # Number of float alu accesses
> system.cpu1.num_func_calls 27792823 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 60626161 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 470472983 # number of integer instructions
> system.cpu1.num_fp_insts 594254 # number of float instructions
> system.cpu1.num_int_register_reads 624330931 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 367229936 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 937660 # number of times the floating registers were read
> system.cpu1.num_fp_register_writes 547764 # number of times the floating registers were written
> system.cpu1.num_cc_register_reads 91358730 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 91073731 # number of times the CC registers were written
> system.cpu1.num_mem_refs 166284311 # number of memory refs
> system.cpu1.num_load_insts 86908703 # Number of load instructions
> system.cpu1.num_store_insts 79375608 # Number of store instructions
> system.cpu1.num_idle_cycles 93729820854.868027 # Number of idle cycles
> system.cpu1.num_busy_cycles 1072920320.131977 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.011317 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.988683 # Percentage of idle cycles
> system.cpu1.Branches 93458434 # Number of branches fetched
1618,1652c1642,1676
< system.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction
< system.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction
< system.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction
< system.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction
< system.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction
< system.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction
< system.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 337624684 66.84% 66.84% # Class of executed instruction
> system.cpu1.op_class::IntMult 1094737 0.22% 67.05% # Class of executed instruction
> system.cpu1.op_class::IntDiv 62780 0.01% 67.07% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 8 0.00% 67.07% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 13 0.00% 67.07% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 21 0.00% 67.07% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 67.07% # Class of executed instruction
> system.cpu1.op_class::FloatMultAcc 0 0.00% 67.07% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 0 0.00% 67.07% # Class of executed instruction
> system.cpu1.op_class::FloatMisc 83819 0.02% 67.08% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.08% # Class of executed instruction
> system.cpu1.op_class::MemRead 86829386 17.19% 84.27% # Class of executed instruction
> system.cpu1.op_class::MemWrite 78944532 15.63% 99.90% # Class of executed instruction
> system.cpu1.op_class::FloatMemRead 79317 0.02% 99.91% # Class of executed instruction
> system.cpu1.op_class::FloatMemWrite 431076 0.09% 100.00% # Class of executed instruction
1655,1665c1679,1689
< system.cpu1.op_class::total 499098010 # Class of executed instruction
< system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.tags.replacements 5131141 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy
---
> system.cpu1.op_class::total 505150374 # Class of executed instruction
> system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.tags.replacements 5478037 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 455.042894 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 160612984 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5478549 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 29.316701 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8375929793000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.042894 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888756 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.888756 # Average percentage of cache occupancy
1668,1669c1692,1693
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
---
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
1671,1715c1695,1739
< system.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses
< system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60851 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 60851 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1670690 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1670690 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1646008 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1646008 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 143907086 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 143907086 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 144074861 # number of overall hits
< system.cpu1.dcache.overall_hits::total 144074861 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 2897407 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 2897407 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 1336766 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 1336766 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634591 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 634591 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446061 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 446061 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170887 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 170887 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194464 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 194464 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 4680234 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 4680234 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 5314825 # number of overall misses
< system.cpu1.dcache.overall_misses::total 5314825 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43647010000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 43647010000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25591315500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 25591315500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9621405000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 9621405000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2591957500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 2591957500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4654513500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 4654513500 # number of StoreCondReq miss cycles
---
> system.cpu1.dcache.tags.tag_accesses 338044480 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 338044480 # Number of data accesses
> system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.ReadReq_hits::cpu1.data 80989814 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 80989814 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 75375313 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 75375313 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188638 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 188638 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 105231 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 105231 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782566 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1782566 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1758380 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1758380 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 156470358 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 156470358 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 156658996 # number of overall hits
> system.cpu1.dcache.overall_hits::total 156658996 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 3115552 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 3115552 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 1383415 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 1383415 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634948 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 634948 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 525445 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 525445 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 179669 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 179669 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202611 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 202611 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 5024412 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 5024412 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 5659360 # number of overall misses
> system.cpu1.dcache.overall_misses::total 5659360 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46416085500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 46416085500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 26188875500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 26188875500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10762345500 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 10762345500 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2779147000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 2779147000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4838630000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 4838630000 # number of StoreCondReq miss cycles
1718,1763c1742,1787
< system.cpu1.dcache.demand_miss_latency::cpu1.data 78859730500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 78859730500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 78859730500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 78859730500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 77574498 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 77574498 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 70505910 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 70505910 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 802366 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 802366 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 506912 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 506912 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1841577 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1841577 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1840472 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1840472 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 148587320 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 148587320 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 149389686 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 149389686 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037350 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.037350 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018960 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.018960 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790900 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790900 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.879957 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.879957 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092794 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092794 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105660 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105660 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031498 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.031498 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035577 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.035577 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15064.162543 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15064.162543 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19144.199882 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 19144.199882 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 21569.706834 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 21569.706834 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15167.669279 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15167.669279 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23935.090814 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23935.090814 # average StoreCondReq miss latency
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 83367306500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 83367306500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 83367306500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 83367306500 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 84105366 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 84105366 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 76758728 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 76758728 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823586 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 823586 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 630676 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 630676 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1962235 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 1962235 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1960991 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1960991 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 161494770 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 161494770 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 162318356 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 162318356 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037043 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.037043 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018023 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.018023 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.770955 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.770955 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.833146 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.833146 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091563 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091563 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103321 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103321 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031112 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.031112 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034866 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.034866 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14898.189952 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 14898.189952 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18930.599639 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 18930.599639 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20482.344489 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 20482.344489 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15468.149764 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15468.149764 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23881.378602 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23881.378602 # average StoreCondReq miss latency
1766,1769c1790,1793
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16849.527289 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 16849.527289 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14837.690893 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 14837.690893 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16592.450321 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 16592.450321 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14730.871777 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 14730.871777 # average overall miss latency
1776,1859c1800,1883
< system.cpu1.dcache.writebacks::writebacks 5131141 # number of writebacks
< system.cpu1.dcache.writebacks::total 5131141 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17932 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 17932 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 468 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 468 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44381 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44381 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 18400 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 18400 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 18400 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 18400 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879475 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2879475 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1336298 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1336298 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634591 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 634591 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446061 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 446061 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126506 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126506 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194464 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 194464 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4661834 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4661834 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 5296425 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 5296425 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8724 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17779 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39613799000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39613799000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24222435000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24222435000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14015397000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14015397000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9175344000 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9175344000 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1695802000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1695802000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4460100500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4460100500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2195000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2195000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73011578000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 73011578000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87026975000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 87026975000 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1272776000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1272776000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037119 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037119 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018953 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018953 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790900 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790900 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879957 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879957 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068694 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068694 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105660 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105660 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031374 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.031374 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035454 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.035454 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13757.299160 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13757.299160 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18126.521928 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18126.521928 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22085.716627 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 20569.706834 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 20569.706834 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13404.913601 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22935.353073 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22935.353073 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 5478037 # number of writebacks
> system.cpu1.dcache.writebacks::total 5478037 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17265 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 17265 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 318 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 318 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 49763 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 49763 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 17583 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 17583 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 17583 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3098287 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 3098287 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1383097 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1383097 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634948 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 634948 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 525445 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 525445 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 129906 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 129906 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202611 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 202611 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 5006829 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 5006829 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5641777 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5641777 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22372 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 43715 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42239304500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42239304500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24787763000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24787763000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13852353000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13852353000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10236900500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10236900500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1787997500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1787997500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4636074000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4636074000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2191000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2191000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77263968000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 77263968000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91116321000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 91116321000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3993280500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3993280500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3993280500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3993280500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036838 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036838 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018019 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.770955 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.770955 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.833146 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.833146 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066203 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066203 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103321 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103321 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031003 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031003 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034757 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.034757 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13633.115493 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13633.115493 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17921.926662 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17921.926662 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21816.515683 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21816.515683 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19482.344489 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 19482.344489 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13763.779194 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13763.779194 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.650058 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.650058 # average StoreCondReq mshr miss latency
1862,1879c1886,1903
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15661.556804 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15661.556804 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16431.267317 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16431.267317 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145893.626777 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 145893.626777 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 71588.728275 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 71588.728275 # average overall mshr uncacheable latency
< system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.tags.replacements 5003710 # number of replacements
< system.cpu1.icache.tags.tagsinuse 496.211749 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 418095086 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 5004222 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 83.548469 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8379626352000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.211749 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15431.716961 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15431.716961 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16150.287578 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16150.287578 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178494.569104 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178494.569104 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91348.061306 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91348.061306 # average overall mshr uncacheable latency
> system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.tags.replacements 5778503 # number of replacements
> system.cpu1.icache.tags.tagsinuse 496.250731 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 417050198 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 5779015 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 72.166312 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8375901500000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.250731 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969240 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.969240 # Average percentage of cache occupancy
1881c1905
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
1883c1907,1908
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 129 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
1885,1923c1910,1948
< system.cpu1.icache.tags.tag_accesses 851202853 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 851202853 # Number of data accesses
< system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.ReadReq_hits::cpu1.inst 418095086 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 418095086 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 418095086 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 418095086 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 418095086 # number of overall hits
< system.cpu1.icache.overall_hits::total 418095086 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 5004227 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 5004227 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 5004227 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 5004227 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 5004227 # number of overall misses
< system.cpu1.icache.overall_misses::total 5004227 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54129933000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 54129933000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 54129933000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 54129933000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 54129933000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 54129933000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 423099313 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 423099313 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 423099313 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 423099313 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 423099313 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 423099313 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011828 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.011828 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011828 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.011828 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011828 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.011828 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10816.842042 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 10816.842042 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 10816.842042 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 10816.842042 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 851437456 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 851437456 # Number of data accesses
> system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.ReadReq_hits::cpu1.inst 417050198 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 417050198 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 417050198 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 417050198 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 417050198 # number of overall hits
> system.cpu1.icache.overall_hits::total 417050198 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 5779020 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 5779020 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 5779020 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 5779020 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 5779020 # number of overall misses
> system.cpu1.icache.overall_misses::total 5779020 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61138169500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 61138169500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 61138169500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 61138169500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 61138169500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 61138169500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 422829218 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 422829218 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 422829218 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 422829218 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 422829218 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 422829218 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013668 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.013668 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013668 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.013668 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013668 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.013668 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10579.331703 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10579.331703 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10579.331703 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10579.331703 # average overall miss latency
1930,1937c1955,1962
< system.cpu1.icache.writebacks::writebacks 5003710 # number of writebacks
< system.cpu1.icache.writebacks::total 5003710 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5004227 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 5004227 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 5004227 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 5004227 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 5004227 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 5004227 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 5778503 # number of writebacks
> system.cpu1.icache.writebacks::total 5778503 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5779020 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 5779020 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 5779020 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 5779020 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 5779020 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 5779020 # number of overall MSHR misses
1942,1971c1967,1996
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51627819500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 51627819500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51627819500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 51627819500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51627819500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 51627819500 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10917500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10917500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 10917500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011828 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.011828 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.011828 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10316.842042 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99250 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99250 # average overall mshr uncacheable latency
< system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 7173608 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 7173625 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58248659500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 58248659500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58248659500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 58248659500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58248659500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 58248659500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10594500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10594500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10594500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 10594500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.013668 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.013668 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10079.331703 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96313.636364 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96313.636364 # average overall mshr uncacheable latency
> system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 7190671 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 7190679 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
1974,1980c1999,2005
< system.cpu1.l2cache.prefetcher.pfSpanPage 895743 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.tags.replacements 1888854 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13151.739114 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 8987368 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 1904692 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 4.718541 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 898577 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.tags.replacements 1924030 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 12969.443296 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 10103718 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 1939825 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 5.208572 # Average number of references to valid blocks.
1982,1997c2007,2022
< system.cpu1.l2cache.tags.occ_blocks::writebacks 12880.289345 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.911148 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 9.232940 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 244.305681 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.786150 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001093 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000564 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014911 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.802718 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 70 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 12701.469256 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 37.295961 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.822764 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 203.855315 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.775236 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002276 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001637 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.012442 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.791592 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 331 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15403 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 95 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id
1999,2125c2024,2150
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 46 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1447 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5487 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7313 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1113 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 349452832 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 349452832 # Number of data accesses
< system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 234483 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153773 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 388256 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 3241183 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 3241183 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 6893065 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 6893065 # number of WritebackClean hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 876408 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 876408 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4540376 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 4540376 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2756982 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2756982 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 197607 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 197607 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 234483 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153773 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 4540376 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3633390 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 8562022 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 234483 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153773 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 4540376 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3633390 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 8562022 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18869 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10447 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 29316 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206667 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 206667 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194457 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 194457 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253441 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 253441 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463851 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 463851 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 883590 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 883590 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 248454 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 248454 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18869 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10447 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 463851 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1137031 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1630198 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18869 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10447 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 463851 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1137031 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1630198 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 633582000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 432596500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 1066178500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 941410000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 941410000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 356938000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 356938000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2118500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2118500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11335810999 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 11335810999 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16839909000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16839909000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31901147000 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31901147000 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 63500 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 63500 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 633582000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 432596500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16839909000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 43236957999 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 61143045499 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 633582000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 432596500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16839909000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 43236957999 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 61143045499 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 253352 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164220 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 417572 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3241183 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 3241183 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 6893065 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 6893065 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206667 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 206667 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194457 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 194457 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1129849 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1129849 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5004227 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 5004227 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3640572 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3640572 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 446061 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 446061 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 253352 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164220 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 5004227 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4770421 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 10192220 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 253352 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164220 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 5004227 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4770421 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 10192220 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063616 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.070206 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1498 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5779 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5762 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2244 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020203 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940125 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 387081443 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 387081443 # Number of data accesses
> system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 243745 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 174457 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 418202 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 3475258 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 3475258 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 7780467 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 7780467 # number of WritebackClean hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 920068 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 920068 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5308980 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 5308980 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2962504 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2962504 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 264311 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 264311 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 243745 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 174457 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 5308980 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3882572 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 9609754 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 243745 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 174457 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 5308980 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3882572 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 9609754 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18156 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9553 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 27709 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208398 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 208398 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202605 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 202605 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254808 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 254808 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 470040 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 470040 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 900637 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 900637 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 261134 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 261134 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18156 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9553 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 470040 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1155445 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1653194 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18156 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9553 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 470040 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1155445 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1653194 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 581758000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 383665000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 965423000 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 884282500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 884282500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 360962500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 360962500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2107498 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2107498 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11534187000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 11534187000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17654070500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17654070500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32780970500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32780970500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 198500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 198500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 581758000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 383665000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17654070500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 44315157500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 62934651000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 581758000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 383665000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17654070500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 44315157500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 62934651000 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 261901 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 184010 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 445911 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3475258 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 3475258 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 7780467 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 7780467 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208398 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 208398 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202605 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 202605 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1174876 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1174876 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5779020 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 5779020 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3863141 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3863141 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 525445 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 525445 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 261901 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 184010 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 5779020 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 5038017 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 11262948 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 261901 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 184010 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 5779020 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 5038017 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 11262948 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051916 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.062140 # miss rate for ReadReq accesses
2132,2176c2157,2201
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224314 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224314 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092692 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092692 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242706 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242706 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.556996 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.556996 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063616 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092692 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238350 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.159945 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063616 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092692 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238350 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.159945 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41408.681918 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36368.484786 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4555.202330 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4555.202330 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1835.562618 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1835.562618 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 302642.857143 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 302642.857143 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44727.613129 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44727.613129 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36304.565475 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36304.565475 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36104.015437 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36104.015437 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.255581 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.255581 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 37506.514852 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 37506.514852 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.216881 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.216881 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.081336 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.081336 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.233136 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.233136 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.496977 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.496977 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051916 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.081336 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.229345 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.146782 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051916 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.081336 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.229345 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.146782 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40161.729300 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34841.495543 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4243.238899 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4243.238899 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1781.607068 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1781.607068 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 351249.666667 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 351249.666667 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45266.188660 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45266.188660 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37558.655646 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37558.655646 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36397.539186 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36397.539186 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.760146 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.760146 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40161.729300 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37558.655646 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38353.324909 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 38068.521299 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40161.729300 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37558.655646 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38353.324909 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 38068.521299 # average overall miss latency
2183,2189c2208,2214
< system.cpu1.l2cache.unused_prefetches 39938 # number of HardPF blocks evicted w/o reference
< system.cpu1.l2cache.writebacks::writebacks 1086447 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1086447 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4568 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 4568 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 305 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 305 # number of ReadSharedReq MSHR hits
---
> system.cpu1.l2cache.unused_prefetches 40493 # number of HardPF blocks evicted w/o reference
> system.cpu1.l2cache.writebacks::writebacks 1134178 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1134178 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4642 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 4642 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 415 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 415 # number of ReadSharedReq MSHR hits
2192,2225c2217,2250
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4873 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4873 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 4873 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18869 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10447 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 29316 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 688963 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206667 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206667 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194457 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194457 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248873 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 248873 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463851 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463851 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 883285 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 883285 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 248453 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 248453 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18869 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10447 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463851 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1132158 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1625325 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18869 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10447 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463851 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1132158 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2314288 # number of overall MSHR misses
---
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5057 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 5057 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5057 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 5057 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18156 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9553 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 27709 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 685885 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 685885 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208398 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 208398 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202605 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202605 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 250166 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 250166 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 470040 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 470040 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 900222 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 900222 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 261133 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 261133 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18156 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9553 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 470040 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1150388 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1648137 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18156 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9553 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 470040 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1150388 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 685885 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2334022 # number of overall MSHR misses
2227,2230c2252,2255
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8834 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22482 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable
2232,2272c2257,2297
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17889 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369914500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 890282500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27673006691 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3909692000 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3909692000 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3000401499 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3000401499 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1812500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1812500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9302871999 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9302871999 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14056803000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14056803000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26558969500 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26558969500 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5731021500 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5731021500 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369914500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14056803000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35861841499 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 50808926999 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369914500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14056803000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35861841499 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 78481933690 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10092500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1202508000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1212600500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10092500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1202508000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1212600500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.070206 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43825 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 326347000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 799169000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28141665535 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28141665535 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3910093000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3910093000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3115291500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3115291500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1777498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1777498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9489009000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9489009000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14833830500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14833830500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27315818000 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27315818000 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6163710000 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6163710000 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 326347000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14833830500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36804827000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 52437826500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 326347000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14833830500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36804827000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28141665535 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 80579492035 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9769500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3813749500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3823519000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9769500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3813749500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3823519000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.062140 # mshr miss rate for ReadReq accesses
2281,2297c2306,2322
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220271 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220271 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092692 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242623 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242623 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.556993 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.556993 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159467 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212930 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212930 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081336 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.233029 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.233029 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.496975 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.496975 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.146333 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for overall accesses
2299,2376c2324,2401
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency
< system.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 4569933 # Total snoops (count)
< system.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes)
< system.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.207230 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28841.495543 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41029.714216 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18762.622482 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18762.622482 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15376.182720 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15376.182720 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296249.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296249.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37930.849916 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37930.849916 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31558.655646 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30343.424178 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30343.424178 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23603.719178 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23603.719178 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31816.424545 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34523.878539 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170469.761309 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170070.233965 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87241.210111 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87245.156874 # average overall mshr uncacheable latency
> system.cpu1.toL2Bus.snoop_filter.tot_requests 23256823 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11916693 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 817 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 568685 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 568681 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.cpu1.toL2Bus.trans_dist::ReadReq 538115 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 10263353 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 21343 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 21343 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 4626226 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 7781279 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 1111211 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 833315 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 380175 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364314 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 469217 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1205096 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1180975 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5779020 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4693276 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 584455 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 526474 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17336763 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17662942 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385121 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576423 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 35961249 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 739681912 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 678880625 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472080 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2095208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1422129825 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 4566671 # Total snoops (count)
> system.cpu1.toL2Bus.snoopTraffic 79930832 # Total snoop traffic (bytes)
> system.cpu1.toL2Bus.snoop_fanout::samples 16661362 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.048994 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.215856 # Request fanout histogram
2378,2380c2403,2405
< system.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 15845064 95.10% 95.10% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 816294 4.90% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram
2383,2385c2408,2410
< system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::total 16661362 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 23051952997 # Layer occupancy (ticks)
2387c2412
< system.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 163764383 # Layer occupancy (ticks)
2389c2414
< system.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 8668640000 # Layer occupancy (ticks)
2391c2416
< system.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 8058549119 # Layer occupancy (ticks)
2393c2418
< system.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 201111499 # Layer occupancy (ticks)
2395c2420
< system.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 314522000 # Layer occupancy (ticks)
2397,2402c2422,2427
< system.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 40383 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40383 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136636 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136636 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes)
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 40263 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40263 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136535 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136535 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47338 # Packet count per connected master and slave (bytes)
2415,2417c2440,2442
< system.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122272 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231244 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231244 # Packet count per connected master and slave (bytes)
2420,2421c2445,2446
< system.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47358 # Cumulative packet size per connected master and slave (bytes)
2434,2436c2459,2461
< system.iobus.pkt_size_system.bridge.master::total 155799 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155379 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338992 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7338992 # Cumulative packet size per connected master and slave (bytes)
2439,2440c2464,2465
< system.iobus.pkt_size::total 7496965 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 36934001 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7496457 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 36598000 # Layer occupancy (ticks)
2442c2467
< system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
2444c2469
< system.iobus.reqLayer2.occupancy 319001 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks)
2448c2473
< system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
2452c2477
< system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2454c2479
< system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
2462c2487
< system.iobus.reqLayer23.occupancy 25636500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 25735000 # Layer occupancy (ticks)
2464c2489
< system.iobus.reqLayer24.occupancy 37418000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 37421000 # Layer occupancy (ticks)
2466c2491
< system.iobus.reqLayer25.occupancy 570101370 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 570201068 # Layer occupancy (ticks)
2468c2493
< system.iobus.respLayer0.occupancy 92787000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92468000 # Layer occupancy (ticks)
2470c2495
< system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147940000 # Layer occupancy (ticks)
2474,2476c2499,2501
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 115614 # number of replacements
< system.iocache.tags.tagsinuse 11.296592 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 115618 # number of replacements
> system.iocache.tags.tagsinuse 11.260426 # Cycle average of tags in use
2478c2503
< system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115634 # Sample count of references to valid blocks.
2480,2485c2505,2510
< system.iocache.tags.warmup_cycle 9136749782000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.841541 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 7.455051 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.240096 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.465941 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.706037 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9133276021000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 7.412431 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 3.847995 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.463277 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.240500 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.703777 # Average percentage of cache occupancy
2489,2491c2514,2516
< system.iocache.tags.tag_accesses 1041054 # Number of tag accesses
< system.iocache.tags.data_accesses 1041054 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.tag_accesses 1040955 # Number of tag accesses
> system.iocache.tags.data_accesses 1040955 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
2493,2494c2518,2519
< system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8894 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8931 # number of ReadReq misses
2500,2501c2525,2526
< system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses
< system.iocache.demand_misses::total 115673 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115622 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115662 # number of demand (read+write) misses
2503,2507c2528,2532
< system.iocache.overall_misses::realview.ide 115633 # number of overall misses
< system.iocache.overall_misses::total 115673 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1975225504 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1980423504 # number of ReadReq miss cycles
---
> system.iocache.overall_misses::realview.ide 115622 # number of overall misses
> system.iocache.overall_misses::total 115662 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 2022255480 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 2027450480 # number of ReadReq miss cycles
2510,2517c2535,2542
< system.iocache.WriteLineReq_miss_latency::realview.ide 13261468866 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13261468866 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 15236694370 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 15242261370 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 15236694370 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 15242261370 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13353085588 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13353085588 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 15375341068 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15380905068 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 15375341068 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15380905068 # number of overall miss cycles
2519,2520c2544,2545
< system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8894 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8931 # number of ReadReq accesses(hits+misses)
2526,2527c2551,2552
< system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115622 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115662 # number of demand (read+write) accesses
2529,2530c2554,2555
< system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115622 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115662 # number of overall (read+write) accesses
2544,2546c2569,2571
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 221810.837058 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 221474.335048 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 227373.002024 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 227012.706304 # average ReadReq miss latency
2549,2557c2574,2582
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124254.824095 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 124254.824095 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 131770.260735 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 131770.260735 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 49344 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125113.237276 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 125113.237276 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 132981.489755 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 132981.489755 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 51037 # number of cycles access was blocked
2559c2584
< system.iocache.blocked::no_mshrs 3519 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked
2561c2586
< system.iocache.avg_blocked_cycles::no_mshrs 14.022165 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 14.437624 # average number of cycles each access was blocked
2566,2567c2591,2592
< system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8894 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8931 # number of ReadReq MSHR misses
2573,2574c2598,2599
< system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115622 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115662 # number of demand (read+write) MSHR misses
2576,2580c2601,2605
< system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529975504 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1533323504 # number of ReadReq MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 115622 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115662 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1577555480 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1580900480 # number of ReadReq MSHR miss cycles
2583,2590c2608,2615
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7919102558 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7919102558 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 9449078062 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 9452645062 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 9449078062 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 9452645062 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8010840420 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8010840420 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 9588395900 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9591959900 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 9588395900 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9591959900 # number of overall MSHR miss cycles
2604,2606c2629,2631
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171810.837058 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 171474.335048 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177373.002024 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 177012.706304 # average ReadReq mshr miss latency
2609,2934c2634,2959
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74198.922101 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74198.922101 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency
< system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.l2c.tags.replacements 1381741 # number of replacements
< system.l2c.tags.tagsinuse 65067.880129 # Cycle average of tags in use
< system.l2c.tags.total_refs 5923587 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1442494 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 4.106490 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 9880371500 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 12193.656277 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.628854 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 215.563389 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4072.894051 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 15215.630293 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9216.886744 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.489010 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 298.478725 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 2688.288956 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 9916.445518 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10812.918313 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.186060 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.003289 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.062147 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.232172 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.140639 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004021 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.004554 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.041020 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.151313 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.164992 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.992857 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 10723 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 49775 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 111 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 10351 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 1155 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 4128 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 44374 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.163620 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.759506 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 67794643 # Number of tag accesses
< system.l2c.tags.data_accesses 67794643 # Number of data accesses
< system.l2c.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.l2c.WritebackDirty_hits::writebacks 2588139 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 2588139 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 176729 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 155906 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 332635 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 47999 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 52030 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 100029 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 45484 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 61265 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 106749 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 8895 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3831 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 389694 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 511362 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 253998 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11472 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5780 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 424247 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 536390 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284910 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 2430579 # number of ReadSharedReq hits
< system.l2c.InvalidateReq_hits::cpu0.data 112195 # number of InvalidateReq hits
< system.l2c.InvalidateReq_hits::cpu1.data 128573 # number of InvalidateReq hits
< system.l2c.InvalidateReq_hits::total 240768 # number of InvalidateReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 8895 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 3831 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 389694 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 556846 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 253998 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 11472 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 5780 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 424247 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 597655 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 284910 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2537328 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 8895 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 3831 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 389694 # number of overall hits
< system.l2c.overall_hits::cpu0.data 556846 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 253998 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 11472 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 5780 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 424247 # number of overall hits
< system.l2c.overall_hits::cpu1.data 597655 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 284910 # number of overall hits
< system.l2c.overall_hits::total 2537328 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 21760 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 23268 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 45028 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 910 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 658 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1568 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 75776 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 50200 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 125976 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1542 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 53195 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 142597 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2105 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 39604 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 101630 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 753120 # number of ReadSharedReq misses
< system.l2c.InvalidateReq_misses::cpu0.data 431914 # number of InvalidateReq misses
< system.l2c.InvalidateReq_misses::cpu1.data 78834 # number of InvalidateReq misses
< system.l2c.InvalidateReq_misses::total 510748 # number of InvalidateReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 1542 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 53195 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 218373 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 2105 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 2105 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 39604 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 151830 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) misses
< system.l2c.demand_misses::total 879096 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 1542 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 53195 # number of overall misses
< system.l2c.overall_misses::cpu0.data 218373 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 239651 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 2105 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 2105 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 39604 # number of overall misses
< system.l2c.overall_misses::cpu1.data 151830 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 169145 # number of overall misses
< system.l2c.overall_misses::total 879096 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 125369500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 122687000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 248056500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8279000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 9419500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 17698500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 8192378000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 5499536500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 13691914500 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 156458500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 155995000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5894542000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 15712860500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 215561000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 217319500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4715127500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 11789045500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 93763070682 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 156458500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 155995000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 5894542000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 23905238500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 215561000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 217319500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 4715127500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 17288582000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 107454985182 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 156458500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 155995000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 5894542000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 23905238500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 215561000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 217319500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 4715127500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 17288582000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 107454985182 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 2588139 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 2588139 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 198489 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 179174 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 377663 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 48909 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 52688 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 101597 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 121260 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 111465 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 232725 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10441 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5373 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 442889 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 653959 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 493649 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 13577 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7885 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 463851 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 638020 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 454055 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3183699 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::cpu0.data 544109 # number of InvalidateReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::cpu1.data 207407 # number of InvalidateReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::total 751516 # number of InvalidateReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 10441 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 5373 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 442889 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 775219 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 493649 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 13577 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 7885 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 463851 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 749485 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 454055 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 3416424 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 10441 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 5373 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 442889 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 775219 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 493649 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 13577 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 7885 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 463851 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 749485 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 454055 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 3416424 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.109628 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129863 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.119228 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018606 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012489 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.015434 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.624905 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.450366 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.541308 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286991 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.120109 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218052 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.266963 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085381 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.159290 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.236555 # miss rate for ReadSharedReq accesses
< system.l2c.InvalidateReq_miss_rate::cpu0.data 0.793801 # miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_miss_rate::cpu1.data 0.380093 # miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_miss_rate::total 0.679624 # miss rate for InvalidateReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.286991 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.120109 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.281692 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.266963 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.085381 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.202579 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.257315 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.286991 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.120109 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.281692 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.266963 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.085381 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.202579 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.257315 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5761.465993 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5272.778064 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 5508.938882 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9097.802198 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14315.349544 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 11287.308673 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108113.096495 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109552.519920 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 108686.690322 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 101164.072633 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110810.076135 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110190.680730 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103239.667458 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 119056.850318 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115999.660533 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 124499.509616 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 122233.504853 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 122233.504853 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 213 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75058.470317 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75058.470317 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency
> system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.l2c.tags.replacements 1289685 # number of replacements
> system.l2c.tags.tagsinuse 65148.785380 # Cycle average of tags in use
> system.l2c.tags.total_refs 5723107 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1350729 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 4.237051 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 6059472500 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 12155.679811 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 124.426191 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 138.926128 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 3396.773965 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 12605.328956 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8503.765275 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 300.348884 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 348.970492 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 3831.795073 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 12139.257493 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11603.513111 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.185481 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001899 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.002120 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.051831 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.192342 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.129757 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004583 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.005325 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.058469 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.185230 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.177056 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.994092 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 12163 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 48582 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 318 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 11671 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 297 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 1173 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 4557 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 42755 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.185593 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.004562 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.741302 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 65194650 # Number of tag accesses
> system.l2c.tags.data_accesses 65194650 # Number of data accesses
> system.l2c.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.l2c.WritebackDirty_hits::writebacks 2495189 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 2495189 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 165997 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 157094 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 323091 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 44921 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 51888 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 96809 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 41742 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 58696 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 100438 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7485 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3707 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 366128 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 471159 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 250331 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11134 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 423879 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 535784 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283571 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 2358374 # number of ReadSharedReq hits
> system.l2c.InvalidateReq_hits::cpu0.data 108961 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::cpu1.data 126093 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::total 235054 # number of InvalidateReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 7485 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 3707 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 366128 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 512901 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 250331 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 11134 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 423879 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 594480 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 283571 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2458812 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 7485 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 3707 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 366128 # number of overall hits
> system.l2c.overall_hits::cpu0.data 512901 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 250331 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 11134 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 423879 # number of overall hits
> system.l2c.overall_hits::cpu1.data 594480 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 283571 # number of overall hits
> system.l2c.overall_hits::total 2458812 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 21704 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 22525 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 44229 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 639 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 868 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1507 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 68872 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 49716 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 118588 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 981 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 934 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 45283 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 111817 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 200821 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1691 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1806 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 46161 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 105560 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 172390 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 687444 # number of ReadSharedReq misses
> system.l2c.InvalidateReq_misses::cpu0.data 412236 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::cpu1.data 90358 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::total 502594 # number of InvalidateReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 981 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 934 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 45283 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 180689 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 200821 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 1691 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1806 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 46161 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 155276 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 172390 # number of demand (read+write) misses
> system.l2c.demand_misses::total 806032 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 981 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 934 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 45283 # number of overall misses
> system.l2c.overall_misses::cpu0.data 180689 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 200821 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 1691 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1806 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 46161 # number of overall misses
> system.l2c.overall_misses::cpu1.data 155276 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 172390 # number of overall misses
> system.l2c.overall_misses::total 806032 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 123357500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 137680500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 261038000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7905500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 10002000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 17907500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 7461780500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 5660273500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 13122054000 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 100552000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 104158000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5195669500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 12454113000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 176942500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 186194000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5476488000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 12376112000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 86331961414 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 100552000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 104158000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 5195669500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 19915893500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 176942500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 186194000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 5476488000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 18036385500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 99454015414 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 100552000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 104158000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 5195669500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 19915893500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 176942500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 186194000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 5476488000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 18036385500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 99454015414 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 2495189 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 2495189 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 187701 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 179619 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 367320 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 45560 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 52756 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 98316 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 110614 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 108412 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 219026 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8466 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4641 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 411411 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 582976 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 451152 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12825 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7002 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 470040 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 641344 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 455961 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 3045818 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu0.data 521197 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu1.data 216451 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::total 737648 # number of InvalidateReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 8466 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 4641 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 411411 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 693590 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 451152 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 12825 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 7002 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 470040 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 749756 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 455961 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 3264844 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 8466 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 4641 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 411411 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 693590 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 451152 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 12825 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 7002 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 470040 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 749756 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 455961 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 3264844 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.115631 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.125404 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.120410 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.014025 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016453 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.015328 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.622634 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.458584 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.541433 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.201250 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.110068 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.191804 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.257926 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098207 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164592 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.225701 # miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu0.data 0.790941 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu1.data 0.417452 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::total 0.681347 # miss rate for InvalidateReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.201250 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.110068 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.260513 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.257926 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.098207 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.207102 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.246882 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.201250 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.110068 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.260513 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.257926 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.098207 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.207102 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.246882 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5683.629746 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6112.341842 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 5901.964774 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12371.674491 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11523.041475 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 11882.879894 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108342.729992 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 113852.150213 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 110652.460620 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 111518.201285 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114737.749266 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111379.423522 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103097.452935 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 118638.850978 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117242.440318 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 125583.991444 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 111518.201285 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 114737.749266 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 110221.947656 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103097.452935 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 118638.850978 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 116156.943121 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 123387.179931 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 111518.201285 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 114737.749266 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 110221.947656 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103097.452935 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 118638.850978 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 116156.943121 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 123387.179931 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 70 # number of cycles access was blocked
2938c2963
< system.l2c.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 23.333333 # average number of cycles each access was blocked
2940,3005c2965,3039
< system.l2c.writebacks::writebacks 1061178 # number of writebacks
< system.l2c.writebacks::total 1061178 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 79 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 77 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 76 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 269 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 79 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 77 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 76 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 79 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 77 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 76 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 269 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 55507 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 55507 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 21760 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 23268 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 45028 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 910 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 658 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1568 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 75776 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 50200 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 125976 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1542 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 53116 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 142520 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2105 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39528 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 101593 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 752851 # number of ReadSharedReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::cpu0.data 431914 # number of InvalidateReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::cpu1.data 78834 # number of InvalidateReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::total 510748 # number of InvalidateReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 1546 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 1542 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 53116 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 218296 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 2105 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 2105 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 39528 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 151793 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 878827 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 1546 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 1542 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 53116 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 218296 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 2105 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 2105 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 39528 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 151793 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 878827 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable
---
> system.l2c.writebacks::writebacks 1000492 # number of writebacks
> system.l2c.writebacks::total 1000492 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 125 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 495 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 176 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 174 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 975 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 125 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 495 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 176 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 174 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 975 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 125 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 495 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 176 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 174 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 975 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 48951 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 48951 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 21704 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 22525 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 44229 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 639 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 868 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1507 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 68872 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 49716 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 118588 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 981 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 934 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45158 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 111322 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1690 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1806 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 45985 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 105386 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 686469 # number of ReadSharedReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu0.data 412236 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu1.data 90358 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::total 502594 # number of InvalidateReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 981 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 934 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 45158 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 180194 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 1690 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1806 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 45985 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 155102 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 805057 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 981 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 934 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 45158 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 180194 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 1690 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1806 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 45985 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 155102 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 805057 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable
3007,3013c3041,3047
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8722 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 81785 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 38414 # number of WriteReq MSHR uncacheable
< system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22370 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 43096 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 38143 # number of WriteReq MSHR uncacheable
> system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses
3015,3071c3049,3105
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17777 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 120199 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 441512500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483331000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 924843500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22384000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16407000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 38791000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7434596046 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4997490093 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 12432086139 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 140574501 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5355219542 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14279847185 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 196268502 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4312153532 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10767710172 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 86205092450 # number of ReadSharedReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8509679500 # number of InvalidateReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1503443500 # number of InvalidateReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::total 10013123000 # number of InvalidateReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140574501 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 5355219542 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 21714443231 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 196268502 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 4312153532 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 15765200265 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 98637178589 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140574501 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 5355219542 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 21714443231 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 196268502 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 4312153532 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 15765200265 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 98637178589 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4911881502 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 8111000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1045413500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 8982252002 # number of ReadReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4911881502 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 8111000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1045413500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 8982252002 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 43713 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 81239 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 437084000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 466716500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 903800500 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15328000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21488000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 36816000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6773036549 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5163079069 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 11936115618 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 94817501 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4733313024 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11297480109 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 168133501 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5000535031 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11306213655 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 79380267960 # number of ReadSharedReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8132910000 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1724009500 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::total 9856919500 # number of InvalidateReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94817501 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 4733313024 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 18070516658 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 168133501 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5000535031 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 16469292724 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 91316383578 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94817501 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 4733313024 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 18070516658 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 168133501 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5000535031 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 16469292724 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 91316383578 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343198000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2516105003 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7788000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3411021500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6278112503 # number of ReadReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343198000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2516105003 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7788000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3411021500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 6278112503 # number of overall MSHR uncacheable cycles
3074,3176c3108,3210
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.109628 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129863 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.119228 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018606 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012489 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015434 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.624905 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.450366 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.541308 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.217934 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159232 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.236471 # mshr miss rate for ReadSharedReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.793801 # mshr miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.380093 # mshr miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::total 0.679624 # mshr miss rate for InvalidateReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.257236 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.257236 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20290.096507 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20772.348289 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20539.297770 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.802198 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24934.650456 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24739.158163 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98112.806773 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99551.595478 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 98686.147671 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100195.391419 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105988.701702 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114504.852155 # average ReadSharedReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19702.254384 # average InvalidateReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19071.003628 # average InvalidateReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19604.820773 # average InvalidateReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency
< system.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.115631 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125404 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.120410 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.014025 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016453 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015328 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.622634 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.458584 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.541433 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.190955 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164321 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225381 # mshr miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790941 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.417452 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::total 0.681347 # mshr miss rate for InvalidateReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.246584 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.246584 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20138.407667 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20719.933407 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20434.567817 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23987.480438 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24755.760369 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24429.993364 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98342.382231 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 103851.457660 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 100651.968310 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101484.703015 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107283.829493 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 115635.619321 # average ReadSharedReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19728.771869 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19079.766042 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19612.091469 # average InvalidateReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158335.221383 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152481.962450 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 145677.383121 # average ReadReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76966.290508 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78032.198659 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 77279.539421 # average overall mshr uncacheable latency
> system.membus.snoop_filter.tot_requests 3361893 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 1995718 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 3092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3180,3188c3214,3222
< system.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadReq 81785 # Transaction distribution
< system.membus.trans_dist::ReadResp 843578 # Transaction distribution
< system.membus.trans_dist::WriteReq 38414 # Transaction distribution
< system.membus.trans_dist::WriteResp 38414 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution
< system.membus.trans_dist::CleanEvict 225685 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 305919 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadReq 43096 # Transaction distribution
> system.membus.trans_dist::ReadResp 738496 # Transaction distribution
> system.membus.trans_dist::WriteReq 38143 # Transaction distribution
> system.membus.trans_dist::WriteResp 38143 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1107186 # Transaction distribution
> system.membus.trans_dist::CleanEvict 202416 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 304555 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 296744 # Transaction distribution
3190,3196c3224,3230
< system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
< system.membus.trans_dist::ReadExReq 142258 # Transaction distribution
< system.membus.trans_dist::ReadExResp 125306 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 628104 # Transaction distribution
< system.membus.trans_dist::InvalidateResp 29933 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
> system.membus.trans_dist::ReadExReq 135023 # Transaction distribution
> system.membus.trans_dist::ReadExResp 117908 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 695400 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 620101 # Transaction distribution
> system.membus.trans_dist::InvalidateResp 29545 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122272 # Packet count per connected master and slave (bytes)
3198,3204c3232,3238
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25316 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3948606 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 4096286 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238208 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 238208 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 4334494 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155379 # Cumulative packet size per connected master and slave (bytes)
3206,3216c3240,3250
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 601899 # Total snoops (count)
< system.membus.snoopTraffic 182272 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 2241138 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.014818 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50632 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 115505708 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 115711923 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271808 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7271808 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 122983731 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 615067 # Total snoops (count)
> system.membus.snoopTraffic 174144 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 2133066 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.015313 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.122793 # Request fanout histogram
3218,3219c3252,3253
< system.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram
< system.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 2100403 98.47% 98.47% # Request fanout histogram
> system.membus.snoop_fanout::1 32663 1.53% 100.00% # Request fanout histogram
3224,3225c3258,3259
< system.membus.snoop_fanout::total 2241138 # Request fanout histogram
< system.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 2133066 # Request fanout histogram
> system.membus.reqLayer0.occupancy 100156000 # Layer occupancy (ticks)
3229c3263
< system.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 21088500 # Layer occupancy (ticks)
3231c3265
< system.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 7525887071 # Layer occupancy (ticks)
3233c3267
< system.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 4366874131 # Layer occupancy (ticks)
3235c3269
< system.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 80052408 # Layer occupancy (ticks)
3237,3243c3271,3277
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
3250,3251c3284,3285
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
3294,3300c3328,3334
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
3305,3350c3339,3384
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
< system.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 2851175 # Total snoops (count)
< system.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes)
< system.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.toL2Bus.snoop_filter.tot_requests 10343091 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 5462203 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 1986792 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 195863 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 175744 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 20119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states
> system.toL2Bus.trans_dist::ReadReq 43098 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 3851068 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38143 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38143 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 3495681 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 2217175 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 626966 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 393553 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 1020519 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 123 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 273712 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 273712 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 3808446 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 849023 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateResp 832010 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7676666 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7311446 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 14988112 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 187677530 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 181320537 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 368998067 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 2787811 # Total snoops (count)
> system.toL2Bus.snoopTraffic 116317008 # Total snoop traffic (bytes)
> system.toL2Bus.snoop_fanout::samples 7322753 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.391714 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.493730 # Request fanout histogram
3352,3354c3386,3388
< system.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 4474450 61.10% 61.10% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 2828184 38.62% 99.73% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 20119 0.27% 100.00% # Request fanout histogram
3358,3359c3392,3393
< system.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 7322753 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 8114772770 # Layer occupancy (ticks)
3361c3395
< system.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 9310827 # Layer occupancy (ticks)
3363c3397
< system.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 3511032286 # Layer occupancy (ticks)
3365c3399
< system.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 3606444627 # Layer occupancy (ticks)